Purpose: Invalidity Analysis


Patent: US9632727B2
Filed: 2006-12-06
Issued: 2017-04-25
Patent Holder: (Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC
Inventor(s): David Flynn, Jonathan Thatcher, Michael Zappe

Title: Systems and methods for identifying storage resources that are not in use

Abstract: An apparatus, system, and method are disclosed for managing a non-volatile storage medium. A storage controller receives a message that identifies data that no longer needs to be retained on the non-volatile storage medium. The data may be identified using a logical identifier. The message may comprise a hint, directive, or other indication that the data has been erased and/or deleted. In response to the message, the storage controller records an indication that the contents of a physical storage location and/or physical address associated with the logical identifier do not need to be preserved on the non-volatile storage medium.



Refer to: Unified Patents PATROLL Contests

Refer to: Unification Technologies LLC - US 9,632,727 (Solid-State Drive (SSD) Devices) and Litigation Background (Deadline: August 31, 2020)

Refer to: Pseudo Claim Charts Prepared by Apex Standards for other PATROLL Contests

Disclaimer: The promise of Apex Standards Pseudo Claim Charting (PCC) is not to replace expert opinion but to provide due diligence and transparency prior to high precision charting. PCC conducts aggressive mapping (based on Broadest Reasonable, Ordinary or Customary Interpretation and Multilingual Translation) between a target patent's claim elements and other documents (potential technical standard specification or prior arts in the same or across different jurisdictions), therefore allowing for a top-down, apriori evaluation, with which, stakeholders can assess standard essentiality (potential strengths) or invalidity (potential weaknesses) quickly and effectively before making complex, high-value decisions. PCC is designed to relieve initial burden of proof via an exhaustive listing of contextual semantic mapping as potential building blocks towards a litigation-ready work product. Stakeholders may then use the mapping to modify upon shortlisted PCC or identify other relevant materials in order to formulate strategy and achieve further purposes.

Click on references to view corresponding claim charts.


GroundReferencesOwner of the ReferenceTitleSemantic MappingChallenged Claims
123456789101213141516
1WO2006113334A2

(Clark D. Nicholson, 2006)
(Original Assignee) Microsoft Corporation     In-line non volatile memory disk read cache and write buffer computer system power connectors, computer system
index entry available space
solid state solid state
XXX
2WO2005103878A2

(Gil Sever, 2005)
(Original Assignee) Storewiz, Inc.     Method and system for compression of files for storage and operation on compressed files external SATA predefined criteria
storing data computer program
internet SCSI interface, read request logical unit
storage client entire file
storage processor data store
Small Computer System Interface said list
XXXXXX
3CN1632765A

(叶青, 2005)
(Original Assignee) 大唐微电子技术有限公司     一种闪存文件系统管理方法 storage operations 进行操作
PCI Express bus interface 初始值
Serial ATA 的文件
XXX
4US7120051B2

(Sergey Anatolievich Gorobets, 2006)
(Original Assignee) SanDisk Corp     

(Current Assignee)
SanDisk Technologies LLC
Pipelined programming of non-volatile memories using early data flash memory device programming operations
garbage collector, read request specifying one logical page
storing data more sector
internet SCSI interface new data
XXXXXXX
5US20060075057A1

(Kevin Gildea, 2006)
(Original Assignee) International Business Machines Corp     

(Current Assignee)
International Business Machines Corp
Remote direct memory access system and method storing data readable recording medium
internet SCSI interface direct memory access, device driver
solid state storage medium write operation
storage client different paths
storage processor data store
Advanced Technology when i
XXXXXX
6JP2006031268A

(Yoshiyuki Nakai, 2006)
(Original Assignee) Sharp Corp; シャープ株式会社     情報処理装置、及び記憶制御装置 state storage controller, storage operations 前記記憶部
flash memory device アドレス
block directive command 消去指示
read request specifying one する情報
XXXXXXXXX
7JP2005339198A

(Toshiyuki Hama, 2005)
(Original Assignee) Internatl Business Mach Corp <Ibm>; インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation     キャッシュヒット率推定装置、キャッシュヒット率推定方法、プログラム及び記録媒体 index entries リスト
storage client サーバ
XXX
8JP2005293774A

(Tetsuya Kamimura, 2005)
(Original Assignee) Hitachi Global Storage Technologies Netherlands Bv; ヒタチグローバルストレージテクノロジーズネザーランドビーブイ     ディスク装置の制御方法 block directive command 制御コマンド
storage operations の符号
XX
9US7139864B2

(Alan David Bennett, 2006)
(Original Assignee) SanDisk Corp     

(Current Assignee)
SanDisk Technologies LLC
Non-volatile memory and method with block management system block directive command second blocks
Advanced Technology second order
store data, storing data said memory
XXX
10US20050144358A1

(Kevin Conley, 2005)
(Original Assignee) SanDisk Corp     

(Current Assignee)
SanDisk Technologies LLC
Management of non-volatile memory systems having large erase blocks Small Computer, Small Computer System Interface determined sequence
index entries logical blocks
block directive command second blocks
storage processor data store
uniform logic n groups
XXXXXX
11JP2005115600A

(Noboru Furuumi, 2005)
(Original Assignee) Hitachi Ltd; 株式会社日立製作所     情報処理装置及び方法 store data 複数通り, 要素又
read request specifying one する情報
XX
12JP2004310621A

(健一 ▲筑▼地, 2004)
(Original Assignee) Hitachi Ltd; 株式会社日立製作所     記憶装置システムにおけるファイルアクセス方法及びファイルアクセスのためのプログラム read request specifying one する情報
storage processor メモリ
XXX
13JP2004227098A

(Naotaka Kobayashi, 2004)
(Original Assignee) Hitachi Ltd; 株式会社日立製作所     記憶デバイス制御装置の制御方法、及び記憶デバイス制御装置 block directive command するアプリケーションプログラム
storage controller 調べるステップ
storage client 前記割り当て, サーバ
solid state, state storage medium ロック
index entries リスト
storage processor メモリ
XXXXXXXXX
14US7005350B2

(Andrew J. Walker, 2006)
(Original Assignee) SanDisk 3D LLC     

(Current Assignee)
SanDisk Technologies LLC
Method for fabricating programmable memory array structures incorporating series-connected transistor strings state storage system semiconductor layer
index entry memory array
store data, storing data said memory
Fibre Channel interface one channel
XXXX
15JP2004086295A

(Jin-Shian Lin, 2004)
(Original Assignee) Megawin Technology Co Ltd; 笙泉科技股▲ふん▼有限公司     Nand型フラッシュメモリディスク装置及び論理アドレス検出の方法 Small Computer SRAM
storage processor メモリ
XXXX
16JP2004030438A

(Hiroyuki Kimura, 2004)
(Original Assignee) Renesas Technology Corp; 株式会社ルネサステクノロジ     マイクロコンピュータ storing data タイミング
store data 周辺機器
solid state, state storage medium ロック
XX
17JP2004021811A

(Tetsuya Abe, 2004)
(Original Assignee) Hitachi Ltd; 株式会社日立製作所     不揮発メモリを使用したディスク制御装置 PCI Express bus interface メモリモジュール, ホスト
uniform logic 論理アドレス
data string コード
XXX
18US20030021417A1

(Ognjen Vasic, 2003)
(Original Assignee) ERUCES Inc     

(Current Assignee)
Central Valley Administrators ; Farrukh Abdallah Dr ; ERUCES Inc
Hidden link dynamic key manager for use in computer systems with database structure for storage of encrypted data and method for storage and retrieval of encrypted data host operating system secure communication
InfiniBand interface access control list
store data software component
index metadata encrypted data
Small Computer, Small Computer System Interface readable data
read request n information
storage processor data store
XXXXXX
19JP2003281071A

(伸之 ▲斎▼藤, 2003)
(Original Assignee) Seiko Epson Corp; セイコーエプソン株式会社     データ転送制御装置、電子機器及びデータ転送制御方法 flash memory device アドレス
data bits クロック
XXX
20US6871257B2

(Kevin M. Conley, 2005)
(Original Assignee) SanDisk Corp     

(Current Assignee)
SanDisk Technologies LLC
Pipelined parallel programming operation in a non-volatile memory system uniform logic non-volatile storage
storage processor data store
XXXX
21US6748504B2

(Wayne A. Sawdon, 2004)
(Original Assignee) International Business Machines Corp     

(Current Assignee)
International Business Machines Corp
Deferred copy-on-write of a snapshot storing data computer readable medium
read request corresponding data
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22US6525953B1

(Mark G. Johnson, 2003)
(Original Assignee) SanDisk 3D LLC     

(Current Assignee)
SanDisk Technologies LLC
Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication Fibre Channel interface third plurality
host operating system, data string one dimension
index entry memory array, d line
store data, storing data said memory
XXXXXX
23JP2003006041A

(Kazushige Ayukawa, 2003)
(Original Assignee) Hitachi Ltd; Hitachi Ulsi Systems Co Ltd; 株式会社日立製作所; 株式会社日立超エル・エス・アイ・システムズ     半導体装置 read request, read request specifying one メモリアクセス
storage processor 外部アクセス
block directive command コマンド信号
state storage controller, storage controller 制御信号
Small Computer SRAM
flash memory device アドレス
data bits クロック
XXXXXXXXX
24US20020049883A1

(Eric Schneider, 2002)
(Original Assignee) Roxio Inc     

(Current Assignee)
NortonLifeLock Inc
System and method for restoring a computer system after a failure external Serial, external Serial Advanced Technology Attachment bus interface Universal Serial Bus
indexer comprises firmware electronic hardware
PCI Express bus interface, bus interface communication link, complex data
computer system computer system
external SATA large numbers
external SATA bus interface visible image
read request, read request specifying one current data, read request
storage operations only memory
storage processor data store
state storage medium, state storage system hard disk
Small Computer System Interface said list
particular storage two disk
XXXXXXXX
25US6725321B1

(Alan Welsh Sinclair, 2004)
(Original Assignee) Lexar Media Inc     

(Current Assignee)
Micron Technology Inc
Memory system external Serial temporary memory
solid state storage medium write operation
index entry logical sector, memory array
store data, storing data said memory, more sector
solid state solid state
Small Computer System Interface said list
XXXX
26US6606690B2

(Michael Padovano, 2003)
(Original Assignee) Hewlett Packard Development Co LP     

(Current Assignee)
Hewlett Packard Enterprise Development LP
System and method for accessing a storage area network as network attached storage Small Computer allocation message
storage interface to accept requests to perform storage operations third interface
external SATA first host, more host
storage processor data store
index entry d line
XXXXXX
27US6763424B2

(Kevin M. Conley, 2004)
(Original Assignee) SanDisk Corp     

(Current Assignee)
SanDisk Technologies LLC
Partial block data programming and reading operations in a non-volatile memory index metadata overlapping blocks
block directive command individual blocks
garbage collector, read request specifying one logical page
external SATA, external SATA bus interface host system
storage processor data store
XXXXXX
28US6594712B1

(Christopher Pettey, 2003)
(Original Assignee) Banderacom Inc     

(Current Assignee)
Intel Corp
Inifiniband channel adapter for performing direct DMA between PCI bus and inifiniband link storage processer remote direct memory access
read request transferring said data, read request
storage interface virtual addresses
store data, storing data direct transfer, said memory
index entries, index entry local node
PCI Express bus interface PCI bus
XXXXXXX
29US6404647B1

(Mark W. Minne′, 2002)
(Original Assignee) HP Inc     

(Current Assignee)
Seagate Technology LLC
Solid-state mass memory storage device storing data store information
store data memory storage
XX
30JP2002056671A

(Yutaka Ito, 2002)
(Original Assignee) Hitachi Ltd; 株式会社日立製作所     ダイナミック型ramのデータ保持方法と半導体集積回路装置 flash memory device アドレス
storage processor メモリ
XXXX
31JP2001297316A

(Hidenori Mitani, 2001)
(Original Assignee) Mitsubishi Electric Corp; 三菱電機株式会社     メモリカード及びその制御方法 storage operations 動作周波数
flash memory device アドレス
data bits クロック
XXXXX
32US6240040B1

(Takao Akaogi, 2001)
(Original Assignee) Fujitsu Ltd; Advanced Micro Devices Inc     

(Current Assignee)
Monterey Research LLC
Multiple bank simultaneous operation for a flash memory state storage controller, host operating system operation control
Peripheral Component Interconnect address buffer
storage interface first portions
data bits read data bus
XXXXX
33US6170047B1

(Thomas A. Dye, 2001)
(Original Assignee) Interactive Silicon Inc     

(Current Assignee)
Intellectual Ventures I LLC
System and method for managing system memory and/or non-volatile memory using a memory controller with integrated compression and decompression capabilities garbage collector nonvolatile memory
computer system computer system
state storage medium, solid state storage medium data accesses
storing data storing data
XXXX
34US6278633B1

(Sau C. Wong, 2001)
(Original Assignee) Multi Level Memory Technology     

(Current Assignee)
Samsung Electronics Co Ltd
High bandwidth flash memory that selects programming parameters according to measurements of previous programming operations flash memory device programming operations
solid state storage medium write operation
particular storage block write circuit
store data, storage client store data
XXXXX
35US6336174B1

(Qiang Li, 2002)
(Original Assignee) Maxtor Corp     

(Current Assignee)
Maxtor Corp
Hardware assisted memory backup system and method internet SCSI interface central processing unit
host operating system host operating system
state storage medium, state storage controller backup system
PCI Express bus interface system memory
read request n information
XXXX
36US6374266B1

(Ralph Shnelvar, 2002)
(Original Assignee) Ralph Shnelvar     

(Current Assignee)
Chrysalis Storage LLC
Method and apparatus for storing information in a data processing system computer system computer system
Fibre Channel interface system input
index entries data entry
data string next data
internet SCSI interface new data
XXXXX
37JP2000259525A

(Masaya Matsuzono, 2000)
(Original Assignee) Nec Corp; 日本電気株式会社     通信プロトコルにおける応答返却方法および通信制御装置 internet SCSI interface プロトコル
storage interface to accept requests to perform storage operations 通信時
XX
38US6412080B1

(Michael K. Fleming, 2002)
(Original Assignee) Microsoft Corp     

(Current Assignee)
Microsoft Technology Licensing LLC
Lightweight persistent storage system for flash memory devices uniform logic non-volatile storage
bus interface comprises one first location
storage processor data store
XXXXX
39US6295577B1

(David B. Anderson, 2001)
(Original Assignee) Seagate Technology LLC     

(Current Assignee)
Seagate Technology LLC
Disc storage system having a non-volatile cache to store write data in the event of a power failure store data, storage client store data
PCI Express bus interface power up
XXXX
40US6034882A

(Mark G. Johnson, 2000)
(Original Assignee) SanDisk 3D LLC     

(Current Assignee)
RHOMBUS Inc ; SanDisk Technologies LLC
Vertically stacked field programmable nonvolatile memory and method of fabrication storage interface junction field
host operating system, data string one dimension
state storage medium effect device
index entry d line
XXXXXX
41JP2000122814A

(Shigekazu Inohara, 2000)
(Original Assignee) Hitachi Ltd; 株式会社日立製作所     拡張型ネットワーク接続二次記憶方法及び装置 computer system 行うこと
index entries リスト
data string 特定部
XXXXX
42US6209088B1

(Ken Reneris, 2001)
(Original Assignee) Microsoft Corp     

(Current Assignee)
Microsoft Technology Licensing LLC
Computer hibernation implemented by a computer operating system state storage medium, solid state storage medium readable storage media
garbage collector allocating memory
storage interface following steps
Small Computer known location
internet SCSI interface device driver
XXXXX
43US6269382B1

(Luis Felipe Cabrera, 2001)
(Original Assignee) Microsoft Corp     

(Current Assignee)
Microsoft Technology Licensing LLC ; Clouding Corp
Systems and methods for migration and recall of data from local and remote storage storing data computer readable medium
storage processor data store
Small Computer System Interface said list
XXXXXX
44JP2000076117A

(Hiroshi Nishikawa, 2000)
(Original Assignee) Kano Densan Hongkong Yugenkoshi; 佳能電産香港有限公司     電子機器及びその制御方法及び記憶媒体 storing data タイミング
flash memory device アドレス
read request specifying one する情報
XXXXX
45US6353878B1

(Scott R. Dunham, 2002)
(Original Assignee) EMC Corp     

(Current Assignee)
EMC Corp
Remote control of backup media in a secondary storage subsystem through access to a primary storage subsystem flash memory device storage capacity
block directive command control commands
storage client, storage interface to accept requests to perform storage operations access request
external SATA first host
storage processor data store
external SATA bus interface data port
XXXXXXX
46US6185654B1

(Stephen Richard Van Doren, 2001)
(Original Assignee) Compaq Computer Corp     

(Current Assignee)
Hewlett Packard Enterprise Development LP
Phantom resource memory address mapping system storing data address translation
index entry interleave units
storage processor data store
XXXXXX
47JP2000020490A

(Yuji Imai, 2000)
(Original Assignee) Fujitsu Ltd; 富士通株式会社     遠隔手続き呼出し機構またはオブジェクトリクエストブローカ機構を有する計算機、データ転送方法、および転送方法記憶媒体 state storage medium メッセー
computer system 行うこと
Integrated Drive Electronics 可能記憶
XX
48US5969986A

(Sau C. Wong, 1999)
(Original Assignee) INVOX Technology     

(Current Assignee)
INNOVATIVE MEMORY SYSTEMS Inc
High-bandwidth read and write architectures for non-volatile memories solid state storage medium write operation
data string output signal
uniform logic level hold circuits
read request, read request specifying one first write
XXX
49US6209003B1

(Peter Mattis, 2001)
(Original Assignee) Inktomi Corp     

(Current Assignee)
Altaba Inc
Garbage collection in an object cache storage interface computer apparatus
garbage collector garbage collection
read request n information
store data main memory
XXXXX
50US6374336B1

(Eric C. Peters, 2002)
(Original Assignee) Avid Technology Inc     

(Current Assignee)
CERBERUS BUSINESS FINANCE AS COLLATERAL AGENT LLC
Computer system and process for transferring multiple high bandwidth streams of data between multiple storage units and multiple applications in a scalable and reliable manner host operating system waiting time
storage processor data store
XXXX
51US6138125A

(Robert A. DeMoss, 2000)
(Original Assignee) LSI Corp     

(Current Assignee)
Avago Technologies International Sales Pte Ltd
Block coding method and system for failure recovery in disk arrays flash memory device storage subsystem, storage capacity
solid state storage medium write operation
storing data storing data
XXXX
52US6069827A

(Alan Welsh Sinclair, 2000)
(Original Assignee) Memory Corp PLC     

(Current Assignee)
Micron Technology Inc
Memory system Small Computer, Small Computer System Interface determined sequence
store data, storing data said memory
solid state solid state
XXX
53US6157963A

(II William V. Courtright, 2000)
(Original Assignee) LSI Corp     

(Current Assignee)
NetApp Inc
System controller with plurality of memory queues for prioritized scheduling of I/O requests from priority assigned clients flash memory device array controller
storage interface to accept requests to perform storage operations third interface
store data, storing data said memory
storage client file server
XXXXX
54US6418478B1

(Paul Ignatius, 2002)
(Original Assignee) Commvault Systems Inc     

(Current Assignee)
Commvault Systems Inc
Pipelined high speed data transfer mechanism storage processer data transfer apparatus
Small Computer carrying data
XX
55US6081878A

(Petro Estakhri, 2000)
(Original Assignee) Lexar Media Inc     

(Current Assignee)
Micron Technology Inc
Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices garbage collector logical block address, nonvolatile memory
storage client semiconductor memory
store data storing information, second address
storing data store information, storing data
solid state storage medium write operation
external Serial single memory
read request n information
storage processer logic unit
external SATA bus interface data port
XXXXXX
56US6415373B1

(Eric C. Peters, 2002)
(Original Assignee) Avid Technology Inc     

(Current Assignee)
CERBERUS BUSINESS FINANCE AS COLLATERAL AGENT LLC
Computer system and process for transferring multiple high bandwidth streams of data between multiple storage units and multiple applications in a scalable and reliable manner host operating system waiting time
storage processor data store
XXXX
57US6567889B1

(Rodney A. DeKoning, 2003)
(Original Assignee) LSI Corp     

(Current Assignee)
NetApp Inc
Apparatus and method to provide virtual solid state disk in cache memory in a storage controller Peripheral Component Interconnect computational result
store data storing information
storage controller storage controller
data bits data transfer rate
storing data store information, storing data
indexer comprises firmware checkpoint data
internet SCSI interface, read request logical unit
computer system stored data
storage processor data store
XXXXXXXXX
58US5930815A

(Petro Estakhri, 1999)
(Original Assignee) Lexar Media Inc     

(Current Assignee)
Micron Technology Inc
Moving sequential sectors within a block of information in a flash memory mass storage architecture particular storage particular storage
garbage collector nonvolatile memory
block directive command receiving commands, sequential write
solid state storage medium write operation
external SATA bus interface data port
XXXX
59US6151641A

(Brian K. Herbert, 2000)
(Original Assignee) LSI Corp     

(Current Assignee)
Avago Technologies General IP Singapore Pte Ltd
DMA controller of a RAID storage controller with integrated XOR parity computation capability adapted to compute parity in parallel with the transfer of data segments storage controller storage controller
flash memory device storage subsystem
read request n information
Advanced Technology second order
external SATA, external SATA bus interface host system, data port
store data, storing data said memory, store data
data string next data
XXXXXXXXX
60US6000006A

(Ricardo H. Bruce, 1999)
(Original Assignee) BIT Microsystems Inc     

(Current Assignee)
Bitmicro LLC
Unified re-map and cache-index table with dual write-counters for wear-leveling of non-volatile flash RAM mass storage uniform logic, Small Computer non-volatile storage, lock point
storing data address translation
external SATA, external SATA bus interface host system
XXXX
61US6424872B1

(David A. Glanzer, 2002)
(Original Assignee) Fieldbus Foundation     

(Current Assignee)
Fieldcomm Group Inc
Block oriented control system storing data computer program, storing data
external SATA bus interface, internet SCSI interface controls access
read request n information
data bits system time
XXXXX
62US6044438A

(Howard Thomas Olnowich, 2000)
(Original Assignee) International Business Machines Corp     

(Current Assignee)
International Business Machines Corp
Memory controller for controlling memory accesses across networks in distributed shared memory processing systems host operating system interrupt signal
read request read request
XX
63US6092158A

(David J. Harriman, 2000)
(Original Assignee) Intel Corp     

(Current Assignee)
Intel Corp
Method and apparatus for arbitrating between command streams storage processer, storage processor received write command, memory circuit
store data, storing data said memory, main memory
Small Computer System Interface, data string order r
XXXXXXXX
64JPH10301719A

(Nobukazu Toba, 1998)
(Original Assignee) Yamaha Corp; ヤマハ株式会社     ディスクアレイ装置及びそれを用いた情報処理システム read request specifying one する情報
PCI Express bus interface ホスト
XX
65US5907856A

(Petro Estakhri, 1999)
(Original Assignee) Lexar Media Inc     

(Current Assignee)
Micron Technology Inc
Moving sectors within a block of information in a flash memory mass storage architecture garbage collector logical block address
store data, storing data storing information, said memory
flash memory device flash memory device
solid state storage medium write operation
bus interface comprises one first location
XXXXXX
66US5961660A

(Louis Bennie Capps, 1999)
(Original Assignee) International Business Machines Corp     

(Current Assignee)
International Business Machines Corp
Method and apparatus for optimizing ECC memory performance storage interface initial program
computer system computer system
store data, storing data said memory
read request same memory
XXXXXX
67US6073232A

(Richard Mark Kroeker, 2000)
(Original Assignee) International Business Machines Corp     

(Current Assignee)
International Business Machines Corp
Method for minimizing a computer's initial program load time after a system reset or a power-on using non-volatile storage storage interface processing apparatus, following steps
computer system computer system, stored data
storage processor data store
state storage medium, state storage system hard disk
Advanced Technology when i
XXXXXX
68US5802602A

(Monis Rahman, 1998)
(Original Assignee) Intel Corp     

(Current Assignee)
Intel Corp
Method and apparatus for performing reads of related data from a set-associative cache memory data string, data bits memory arrangement
read request n information
index entries first entry
XXX
69US6279069B1

(Kurt B. Robinson, 2001)
(Original Assignee) Intel Corp     

(Current Assignee)
Intel Corp
Interface for flash EEPROM memory arrays solid state storage medium write operation
computer system computer system
XX
70US6073218A

(Rodney A. DeKoning, 2000)
(Original Assignee) LSI Corp     

(Current Assignee)
NetApp Inc
Methods and apparatus for coordinating shared multiple raid controller access to common storage devices flash memory device storage subsystem
computer system computer system
store data associating one
storage interface designating one
XXXXX
71US5867430A

(Johnny C. Chen, 1999)
(Original Assignee) Fujitsu Ltd; Advanced Micro Devices Inc     

(Current Assignee)
Spansion LLC ; AMD US Holdings Inc
Bank architecture for a non-volatile memory enabling simultaneous reading and writing solid state storage medium write operation
Peripheral Component Interconnect address buffer
store data, storing data said memory
index entry d line
XXXX
72JPH10154101A

(Hiroshi Sukegawa, 1998)
(Original Assignee) Toshiba Corp; 株式会社東芝     データ記憶システム及び同システムに適用するキャッシュ制御方法 block directive command 前記コマンド
storage operations 保存機能
storage processor メモリ
XXXXX
73US5890192A

(Douglas J. Lee, 1999)
(Original Assignee) SanDisk Corp     

(Current Assignee)
SanDisk Technologies LLC
Concurrent write of multiple chunks of data into multiple subarrays of flash EEPROM read request corresponding data
Fibre Channel interface third plurality
storing data storing data
computer system stored data
storage processor data store
XXXXXX
74US5754567A

(Robert D. Norman, 1998)
(Original Assignee) Micron Quantum Devices Inc     

(Current Assignee)
Micron Technology Inc
Write reduction in flash memory systems through ECC usage particular storage confirmation signal
block directive command memory commands
storage processor data store
XXXX
75US5798968A

(Douglas J. Lee, 1998)
(Original Assignee) SanDisk Corp     

(Current Assignee)
SanDisk Technologies LLC
Plane decode/virtual sector architecture Fibre Channel interface third plurality
particular storage block address decoder
garbage collector opposite side
storage operations control gate
flash memory device common bit
index entry d line
XXXXXXXX
76US6014724A

(Detlef Jenett, 2000)
(Original Assignee) SCM Microsystems US Inc     

(Current Assignee)
Samsung Electronics Co Ltd
Flash translation layer block indication map revision system and method flash memory device said determination
storing data storing data
XXXX
77US5996054A

(Joel E. Ledain, 1999)
(Original Assignee) Veritas Software Corp     

(Current Assignee)
Veritas Technologies LLC
Efficient virtualized mapping space for log device data storage system index entry data blocks storing data
computer system computer system
index metadata primary data
XXXX
78US5758118A

(David Mun-Hien Choy, 1998)
(Original Assignee) International Business Machines Corp     

(Current Assignee)
International Business Machines Corp
Methods and data storage devices for RAID expansion by on-line addition of new DASDs Small Computer readable instructions
solid state storage medium write operation
storage processor comprise logic
XXXXX
79US5799200A

(William A. Brant, 1998)
(Original Assignee) EMC Corp     

(Current Assignee)
EMC Corp
Power failure responsive apparatus and method having a shadow dram, a flash ROM, an auxiliary battery, and a controller read request specifying one memory apparatus
storing data storing data
storage interface said module
storage processor data store
Advanced Technology when i
XXXXXXX
80US5835935A

(Petro Estakhri, 1998)
(Original Assignee) Lexar Media Inc     

(Current Assignee)
Micron Technology Inc
Method of and architecture for controlling system data with automatic wear leveling in a semiconductor non-volatile mass storage memory flash memory device flash memory device
store data, storing data said memory, store information
solid state storage medium write operation
XXXX
81US5754563A

(Philip E. White, 1998)
(Original Assignee) ECC Tech Inc     

(Current Assignee)
ECC Tech Inc
Byte-parallel system for implementing reed-solomon error-correcting codes bus interface, external Serial single semiconductor, parallel data
Small Computer, uniform logic level processor system
read request n information
store data, storing data message bits, said memory
Fibre Channel interface input bit
data bits data bits
XXXXX
82US5845313A

(Petro Estakhri, 1998)
(Original Assignee) Lexar Media Inc     

(Current Assignee)
Micron Technology Inc
Direct logical block addressing flash memory mass storage architecture garbage collector logical block address
storage processor data store
XXXX
83US5603001A

(Hiroshi Sukegawa, 1997)
(Original Assignee) Toshiba Corp     

(Current Assignee)
Toshiba Corp
Semiconductor disk system having a plurality of flash memories solid state storage medium write operation
storage processor data indicative, data store
storing data writing means
PCI Express bus interface read command
read request read request
XXXXXX
84US5701434A

(Takayuki Nakagawa, 1997)
(Original Assignee) Hitachi Ltd     

(Current Assignee)
Hitachi Ltd
Interleave memory controller with a common access queue storage operations said sequence
internet SCSI interface single access
XXX
85US5535328A

(Eliyahou Harari, 1996)
(Original Assignee) SanDisk Corp     

(Current Assignee)
SanDisk Technologies LLC
Non-volatile memory system card with flash erasable sectors of EEprom cells including a mechanism for substituting defective cells computer system computer system
index entry memory array
storing data, store data storing data, said memory
storage processor data store
external SATA bus interface data port
XXXXXXX
86US5566315A

(Michael S. Milillo, 1996)
(Original Assignee) Oracle StorageTek     

(Current Assignee)
Oracle StorageTek
Process of predicting and controlling the use of cache memory in a computer system computer system computer system
host operating system first frequency
store data main memory
XX
87US5541886A

(Robert Hasbun, 1996)
(Original Assignee) Intel Corp     

(Current Assignee)
Intel Corp
Method and apparatus for storing control information in multi-bit non-volatile memory arrays flash memory device nonvolatile memory cells
solid state, store data read only memory
particular storage block given address
index entry memory array
storing data storing data
storage processor data store
XXXXXXXX
88US5586291A

(Jeffrey M. Lasker, 1996)
(Original Assignee) EMC Corp     

(Current Assignee)
SWAN CHARLES A ; EMC Corp
Disk controller with volatile and non-volatile cache memories flash memory device storage subsystem
garbage collector memory management
solid state storage medium, state storage medium write operation, one disk
external SATA, external SATA bus interface DMA transfer
Advanced Technology represents a
storage processor data store
XXXXXXXX
89JPH086854A

(T Price Felis, 1996)
(Original Assignee) Unisys Corp; ユニシス コーポレイシヨン     アウトボードファイルキャッシュ外部処理コンプレックス block directive command コマンド信号, 前記コマンド
storing data タイミング
state storage controller, storage controller 制御信号
storage processor メモリ
XXXXXXXX
90JPH08153014A

(Norihiro Gotou, 1996)
(Original Assignee) Hitachi Ltd; 株式会社日立製作所     クライアントサーバシステム bus interface, storage interface 入出力インタフェース
storage client サーバシステム
computer system 行うこと
storage processor メモリ
XXXXXXX
91US6002411A

(Thomas Anthony Dye, 1999)
(Original Assignee) Interactive Silicon Inc     

(Current Assignee)
Intellectual Ventures I LLC
Integrated video and memory controller with data processing and graphical processing capabilities uniform logic non-volatile storage
flash memory device storage subsystem
computer system, bus interface bus interface
state storage controller, storage controller control unit
PCI Express bus interface output ports
XXXXXXX
92US5504882A

(Philip K. Chai, 1996)
(Original Assignee) International Business Machines Corp     

(Current Assignee)
International Business Machines Corp
Fault tolerant data storage subsystem employing hierarchically arranged controllers flash memory device storage subsystem
external SATA host processor
external SATA bus interface, PCI Express bus interface input ports, output ports
XXXXX
93US5696917A

(Duane R. Mills, 1997)
(Original Assignee) Intel Corp     

(Current Assignee)
Intel Corp
Method and apparatus for performing burst read operations in an asynchronous nonvolatile memory garbage collector nonvolatile memory
particular storage block memory components
computer system computer system
storage interface following steps
store data main memory
index entries chip enable
read request same memory
XXXXXXXX
94US5809527A

(Thomas P. Cooper, 1998)
(Original Assignee) Unisys Corp     

(Current Assignee)
Unisys Corp
Outboard file cache system external SATA first host
storage processor data store
internet SCSI interface file data
XXXX
95US5337275A

(Richard P. Garner, 1994)
(Original Assignee) Intel Corp     

(Current Assignee)
Intel Corp
Method for releasing space in flash EEPROM memory array to allow the storage of compressed data store data, index entry allocation table, logical sector
storage processor data store
internet SCSI interface new data
XXXXXX
96US5485595A

(Mahmud Assar, 1996)
(Original Assignee) Cirrus Logic Inc     

(Current Assignee)
Micron Technology Inc
Flash memory mass storage architecture incorporating wear leveling technique without using cam cells garbage collector logical block address
index entries logical blocks
external SATA, external SATA bus interface maximum count
XXX
97US5592641A

(Mickey L. Fandrich, 1997)
(Original Assignee) Intel Corp     

(Current Assignee)
Intel Corp
Method and device for selectively locking write access to blocks in a memory array using write protect inputs and block enabled status flash memory device program operations, array controller
InfiniBand interface available block
index entry memory array
store data main memory
XXXXX
98US5325509A

(Marvin Lautzenheiser, 1994)
(Original Assignee) Zitel Corp     

(Current Assignee)
Zitel Corp
Method of operating a cache memory including determining desirability of cache ahead or cache behind based on a number of available I/O operations state storage system said first side
index entries logical blocks
storing data more sector
storage processor data store
XXXXXX
99US5544347A

(Moshe Yanai, 1996)
(Original Assignee) EMC Corp     

(Current Assignee)
EMC Corp
Data storage system controlled remote data mirroring with respectively maintained data indices PCI Express bus interface communication link
read request corresponding data
bus interface comprises one first location
storing data storing data
external SATA first host
storage processor data store
XXXXXX
100US5388083A

(Mahmud Assar, 1995)
(Original Assignee) Cirrus Logic Inc     

(Current Assignee)
Micron Technology Inc
Flash memory mass storage architecture uniform logic non-volatile storage
Advanced Technology represents a
store data, storage client store data
XXXXX
101US5479638A

(Mahmud Assar, 1995)
(Original Assignee) Cirrus Logic Inc     

(Current Assignee)
Micron Technology Inc
Flash memory mass storage architecture incorporation wear leveling technique uniform logic non-volatile storage
external SATA, external SATA bus interface first controller, maximum count
Advanced Technology represents a
storing data storing data
store data, storage client store data
internet SCSI interface new data
XXXXX
102US5404485A

(Amir Ban, 1995)
(Original Assignee) SanDisk IL Ltd     

(Current Assignee)
SanDisk IL Ltd
Flash file system garbage collector memory management
storage interface virtual addresses
XXX
103JPH0628108A

(賢一 ▲高▼本, 1994)
(Original Assignee) Hitachi Ltd; 株式会社日立製作所     データ記憶システム PCI Express bus interface ホスト
storage processor メモリ
XXXX
104US5394531A

(Kevin F. Smith, 1995)
(Original Assignee) International Business Machines Corp     

(Current Assignee)
LSI Corp
Dynamic storage allocation system for a prioritized cache solid state storage medium write operation
storing data storing data
XX
105US5438671A

(John C. Miles, 1995)
(Original Assignee) Dell USA LP     

(Current Assignee)
Dell USA LP
Method and system for transferring compressed bytes of information between separate hard disk drive units Integrated Drive Electronics Integrated Drive Electronics
flash memory device storage capacity
external Serial, bus interface parallel data, first serial
storage client, state storage medium one disk, hard disk
XXXXXX
106US5274799A

(William A. Brant, 1993)
(Original Assignee) Array Tech Corp     

(Current Assignee)
EMC Corp
Storage device array architecture with copyback cache store data storing information
read request corresponding data
storing data storing data
storage interface to accept requests to perform storage operations such request
XXXX
107US5307497A

(Barry A. Feigenbaum, 1994)
(Original Assignee) International Business Machines Corp     

(Current Assignee)
Lenovo Singapore Pte Ltd
Disk operating system loadable from read only memory using installable file system interface bus interface personal computer system, self test
solid state, store data read only memory, allocation table
host operating system dent portion
state storage medium up period
XXXX
108US5193184A

(Jay S. Belsan, 1993)
(Original Assignee) Oracle StorageTek     

(Current Assignee)
Oracle StorageTek
Deleted data file space release system for a dynamically mapped virtual data storage subsystem storage client predefined commands
Small Computer transmitting means
storage processor data indicative
particular storage two disk
XXXXXX
109US5261068A

(Darius D. Gaskins, 1993)
(Original Assignee) Dell USA LP     

(Current Assignee)
Dell USA LP
Dual path memory retrieval system for an interleaved dynamic RAM memory unit storage processor first output signal
bus interface, PCI Express bus interface second latches, parallel data
store data, storing data said memory
XXXXXX
110US5124987A

(Charles A. Milligan, 1992)
(Original Assignee) Oracle StorageTek     

(Current Assignee)
Oracle StorageTek
Logical track write scheduling system for a parallel disk drive array data storage subsystem storage processor data indicative
storing data writing means
XXXXX
111US5197130A

(Steve S. Chen, 1993)
(Original Assignee) Supercomputer Systems LP     

(Current Assignee)
Morgan Stanley and Co LLC ; Hewlett Packard Enterprise Development LP ; IBM Holdings Inc
Cluster architecture for a highly parallel scalar/vector multiprocessor system read request transferring said data
storage operations, storage interface logical address space
bus interface comprises one said instructions
state storage controller, host operating system shared resources, interrupt signal
storage processor more processors
store data, storing data said memory, main memory
storage processer logic unit
XXXXXXX
112US5371885A

(James G. Letwin, 1994)
(Original Assignee) Microsoft Corp     

(Current Assignee)
Microsoft Technology Licensing LLC
High performance file system store data storing information
garbage collector allocating memory
index entries directory entry
read request read request
external SATA bus interface data port
XXXXX
113WO2006124718A2

(Shuangtong Feng, 2006)
(Original Assignee) Microsoft Corporation     Method and system for closing an rdma connection storage processer remote direct memory access
storing data computer readable medium
flash memory device interface card
XXXXX
114WO2006076993A1

(Vadim Makhervaks, 2006)
(Original Assignee) International Business Machines Corporation; Ibm United Kingdom Limited     RNIC-BASED OFFLOAD OF iSCSI DATA MOVEMENT FUNCTION BY TARGET Small Computer System Interface Small Computer System Interface
storing data computer program
solid state storage medium write operation
XXX
115WO2006065626A1

(William P. Mcgovern, 2006)
(Original Assignee) Network Appliance, Inc.     Rendering disk data unrecoverable using encryption bus interface, PCI Express bus interface graphic data
Advanced Technology represents a
storage processor data store
XXXX
116WO2006050455A2

(Geoffrey S. Barrall, 2006)
(Original Assignee) Trusted Data Corporation     Dynamically expandable and contractible fault-tolerant storage system with virtual hot spare flash memory device storage capacity
storing data storing data
bus interface data loss
XXXXX
117KR20050057185A

(윌리엄 토드 보이드, 2005)
(Original Assignee) 인터내셔널 비지네스 머신즈 코포레이션     리모트 다이렉트 메모리 액세스가 가능한 네트워크 인터페이스 콘트롤러 스위치오버 및 스위치백 지원 장치 및 방법 respective physical block addresses, physical block addresses 어드레스
Small Computer System Interface 프로그램
XX
118WO2006062511A1

(Peter Jensen, 2006)
(Original Assignee) Teac Aerospace Technologies, Inc.     System and method of erasing non-volatile recording media garbage collector logical block address
computer system stored data
solid state solid state
state storage medium, state storage system hard disk
XXXX
119WO2005013143A2

(Christos J. Georgiou, 2005)
(Original Assignee) International Business Machines Corporation     A single chip protocol converter internet SCSI interface direct memory access
uniform logic, host operating system multiple processors
Drive Electronics, Integrated Drive Electronics Integrated Circuit
read request corresponding data
flash memory device arithmetic logic
solid state first function
store data memory storage
PCI Express bus interface, external SATA bus interface bridge device, DMA controller
storage interface more processor
computer system, bus interface bus interface
storage processer logic unit
XXXXXXXX
120EP1498822A2

(Khawar M. Zuberi, 2005)
(Original Assignee) Microsoft Corp     

(Current Assignee)
Microsoft Corp
State migration in multiple NIC RDMA enabled devices storage processer remote direct memory access
InfiniBand interface network interfaces
XX
121KR20050009685A

(즈베리카워엠., 2005)
(Original Assignee) 마이크로소프트 코포레이션     다수의 nic rdma가 가능한 장치의 상태 이동 external Serial 인터페이스를
physical storage 관련되고
internet SCSI interface 프로토콜
XXX
122CN1771495A

(理查德·V·基斯利, 2006)
(Original Assignee) 国际商业机器公司     分布式文件服务体系结构系统 index metadata 相关联的数据
state storage controller, storage controller 保持存储
uniform logic 逻辑单元
Integrated Drive Electronics 体系结构
storage operations 的操作
external SATA bus interface DMA传送
XXXXXX
123WO2004099989A2

(Richard Victor Kisley, 2004)
(Original Assignee) International Business Machines Corporation; Ibm United Kingdom Limited     Distributed file serving architecture system storage processer remote direct memory access
internet SCSI interface, Fibre Channel interface central processing unit, logical unit number
storage controller storage controller
storage client, storage interface to accept requests to perform storage operations access request
read request n information
external SATA, external SATA bus interface DMA transfer
storing data storing data
XXXXXXXX
124EP1465203A1

(Jin-Yub Lee, 2004)
(Original Assignee) Samsung Electronics Co Ltd     

(Current Assignee)
Samsung Electronics Co Ltd
Nonvolatile memory with page copy capability and method thereof storing data storing data
store data, storage client store data
storage processor data store
index entry d line
XXXXXX
125JP2005223753A

(Katsu Iwashita, 2005)
(Original Assignee) Nippon Telegr & Teleph Corp <Ntt>; 日本電信電話株式会社     移動体通信用ネットワークのモビリティ管理方法及びハンドオーバ制御方法 storing data タイミング
computer system 行うこと
flash memory device アドレス
XXXXX
126WO2004077214A2

(Vinayak K. Rao, 2004)
(Original Assignee) Vaman Technologies (R & D) Limited     System and method for scheduling server functions irrespective of server functionality PCI Express bus interface finite state
store data, storing data said memory
XXX
127EP1418502A2

(Robert C Chang, 2004)
(Original Assignee) SanDisk Corp     

(Current Assignee)
SanDisk Technologies LLC
Unusable block management within a non-volatile memory system storing data store information
flash memory device storage elements
XXXX
128CN1701309A

(罗伯特·张, 2005)
(Original Assignee) 桑迪士克股份有限公司     非易失性存储系统中的损耗平衡 bus interface, PCI Express bus interface 成多个
Small Computer 一个擦
flash memory device 以访问
XXX
129WO2004040459A1

(Robert C. Chang, 2004)
(Original Assignee) Sandisk Corporation     Tracking the least frequently erased blocks in non-volatile memory systems garbage collector nonvolatile memory, memory management
flash memory device storage elements
PCI Express bus interface system memory
Advanced Technology when i
XXXX
130EP1552409A1

(Uri Elzur, 2005)
(Original Assignee) Broadcom Corp     

(Current Assignee)
Broadcom Corp
One-shot rdma storage processer remote direct memory access
solid state storage medium write operation
flash memory device interface card
storage client send message
bus interface, PCI Express bus interface own memory
XXXXXX
131WO2004017220A1

(Scott S. Mcdaniel, 2004)
(Original Assignee) Broadcom Corporation     One-shot rdma storage processer remote direct memory access
solid state storage medium write operation
flash memory device interface card
storage client send message
bus interface, PCI Express bus interface own memory
XXXXXX
132EP1543422A1

(William Todd Boyd, 2005)
(Original Assignee) International Business Machines Corp     

(Current Assignee)
International Business Machines Corp
Remote direct memory access enabled network interface controller switchover and switchback support storing data computer program
computer system computer system
XXX
133WO2004023305A1

(William Todd Boyd, 2004)
(Original Assignee) International Business Machines Corporation; Ibm United Kingdom Limited     Remote direct memory access enabled network interface controller switchover and switchback support storing data computer program
computer system computer system
XXX
134EP1331548A2

(Petro Estakhri, 2003)
(Original Assignee) Lexar Media Inc     

(Current Assignee)
Lexar Media Inc
File management of one-time-programmable non volatile memory devices store data, storing data storing information, said memory
block directive command receiving commands
state storage controller control device
internet SCSI interface new data
XXX
135JP2004110436A

(Yoshio Iwahashi, 2004)
(Original Assignee) Koatsu Gas Kogyo Co Ltd; Nippon Lsi Card Co Ltd; 日本エルエスアイカード株式会社; 高圧ガス工業株式会社     メモリのリード/ライト制御回路、無接点メモリカード、リード/ライト装置及び無接点メモリカードのリード/ライトシステム data string アクティブ
state storage controller, storage controller 制御信号
data bits クロック
XXXXXX
136EP1271332A2

(Xiaohua Cheng, 2003)
(Original Assignee) Netac Tech Co Ltd     

(Current Assignee)
Netac Tech Co Ltd
A multifunction semiconductor storage device and a method for booting-up computer host external SATA, external SATA bus interface computer host, host system
state storage system, state storage medium boot program, hard disk
Integrated Drive Electronics LED power
XXX
137KR20030040817A

(백창규, 2003)
(Original Assignee) 삼성전자주식회사     플래시 메모리 관리방법 index entries 테이블의
flash memory device 스캐닝
read request 사항을
XXXX
138EP1280047A2

(Naoto Hitachi Ltd. Int. Prop. Group Matsunami, 2003)
(Original Assignee) Hitachi Ltd     

(Current Assignee)
Hitachi Ltd
A storage system having a plurality of controllers store data storing information
computer system computer system
storage client, storage interface to accept requests to perform storage operations access request
index entries storage pool
storing data storing data
storage processor data store
XXXXXXXX
139JP2003036204A

(Yasutsugu Toyoda, 2003)
(Original Assignee) Matsushita Electric Ind Co Ltd; 松下電器産業株式会社     フラッシュ型メモリの更新方法 flash memory device アドレス
storage processor メモリ
XXXX
140EP1299800A2

(Robert Rodriquez, 2003)
(Original Assignee) Sun Microsystems Inc     

(Current Assignee)
Sun Microsystems Inc
System and method for migrating processes on a network storage operations virtual machines
solid state more states
indexer comprises firmware system code
XXX
141EP1100001A2

(Yousef A. Khalidi, 2001)
(Original Assignee) Sun Microsystems Inc     

(Current Assignee)
Sun Microsystems Inc
Storage system supporting file-level and block-level accesses block directive command non-volatile storage medium
computer system computer system
storage client, storage interface to accept requests to perform storage operations access request
internet SCSI interface, Fibre Channel interface fiber channel
storing data storing data
XXXXX
142JP2000242434A

(Yasuyuki Ajimatsu, 2000)
(Original Assignee) Hitachi Ltd; 株式会社日立製作所     記憶装置システム uniform logic 論理アドレス
computer system 前記スイッチ
storage operations オペレータ
read request specifying one する情報
XXXXX
143WO9828685A1

(Rodney A. Dekoning, 1998)
(Original Assignee) Symbios, Inc.     Coordinating shared access to common storage flash memory device storage subsystem
computer system computer system
store data associating one
storage interface designating one
XXXXX
144JPH113290A

(Yoshiaki Hisada, 1999)
(Original Assignee) Hitachi Ltd; 株式会社日立製作所     メモリ制御方式 data bits 1ビット
flash memory device アドレス
storage processor メモリ
XXXXX
145WO9838568A1

(David Alan Styczinski, 1998)
(Original Assignee) International Business Machines Corporation     Transformational raid for hierarchical storage management system storage interface processing apparatus
computer system computer system
storing data, store data storing data, said memory
state storage medium, state storage system hard disk
XXXXXX
146WO9737296A1

(Alan Welsh Sinclair, 1997)
(Original Assignee) Memory Corporation Plc     Memory devices storage operations, storage interface logical address space
garbage collector logical locations
store data second address
XXXX
147EP0747822A2

(Yoshiko Matsumoto, 1996)
(Original Assignee) Hitachi Ltd     

(Current Assignee)
Hitachi Ltd
External storage system with redundant storage controllers read request transferring said data, n information
state storage controller, storage operations same storage
store data, storing data said memory, storing data
XXXX
148WO9612225A1

(Michael E. Thomas, 1996)
(Original Assignee) Framdrive     Non-volatile solid state random access storage device used in place of a rotating disk drive unit in a computer system internet SCSI interface central processing unit
external SATA, flash memory device drive controller
bus interface, external Serial command signals, parallel data
particular storage block address decoder
storage operations receiving step
storing data, store data storing data, said memory
solid state solid state
storage processor data store
XXXXXXXXX
149WO9420906A1

(Amir Ban, 1994)
(Original Assignee) M-Systems Ltd.; M-Systems Inc.     Flash file system garbage collector memory management
storage interface virtual addresses
flash memory device one zone
XXXX
150EP0544252A2

(Noriyuki c/o Fujitsu Limited Matsui, 1993)
(Original Assignee) Fujitsu Ltd     

(Current Assignee)
Fujitsu Ltd
Data management system for programming-limited type semiconductor memory and IC memory card having the data management system indexer comprises firmware data management system
bus interface single semiconductor
storage client semiconductor memory
storage processor data store
XXXXXX
151EP0686976A2

(Noriyuki C/O Fujitsu Ltd. Matsui, 1995)
(Original Assignee) Fujitsu Ltd     

(Current Assignee)
Fujitsu Ltd
Data management system for programming-limited type semiconductor memory and IC memory card having the data management system store data storing information
solid state storage medium write operation
storing data storing data
storage processor data store
XXXXX
152WO9406210A1

(Prabhakar Goel, 1994)
(Original Assignee) Prabhakar Goel     Multichip ic design using tdm read request specifying one shift registers
storage interface said module
XXX
153EP0522780A2

(Yoshinori Sakaue, 1993)
(Original Assignee) International Business Machines Corp     

(Current Assignee)
International Business Machines Corp
Control method for a computer memory device index entry address translation table
storage client semiconductor memory
garbage collector memory management
InfiniBand interface, storage interface articular region
computer system computer system
storage controller control section
state storage controller control device
read request n information, data reading
PCI Express bus interface read command
store data main memory
XXXXXXXXXX
154JPH05204561A

(Takeshi Furuno, 1993)
(Original Assignee) Hitachi Ltd; 株式会社日立製作所     フラッシュメモリを記憶媒体とした半導体ディスク storage interface 処理単位
flash memory device アドレス
solid state, state storage medium ロック
PCI Express bus interface ホスト
block directive command の命令
XXXXX
155GB2251324A

(Kurt Brian Robinson, 1992)
(Original Assignee) Intel Corp     

(Current Assignee)
Intel Corp
File structure for a non-volatile semiconductor memory internet SCSI interface central processing unit
store data, index entry allocation table
external SATA bus interface, Fibre Channel interface direct memory
storage operations only memory
XXXX
156EP0502211A1

(Hiromasa Fujitsu Limited Takahashi, 1992)
(Original Assignee) Fujitsu Ltd     

(Current Assignee)
Fujitsu Ltd
System equipped with processor and method of converting addresses in said system storing data address translation
store data main memory
storage processor data store
XXXXX
157GB2251323A

(Gerald S Holzhammer, 1992)
(Original Assignee) Intel Corp     

(Current Assignee)
Intel Corp
Disk emulation for a non-volatile semiconductor memory internet SCSI interface central processing unit
computer system computer system
external SATA bus interface, Fibre Channel interface direct memory
storage operations only memory
XXX
158JPH0527924A

(Hideto Niijima, 1993)
(Original Assignee) Internatl Business Mach Corp <Ibm>; インターナシヨナル・ビジネス・マシーンズ・コーポレイシヨン     半導体メモリを用いた外部記憶システム及びその制御方法 block directive command 前記コマンド
uniform logic 論理アドレス
storage interface, storage processor 主記憶装置
indexer comprises firmware 記表示
XXXXXX
159JPH052502A

(Masashi Nagasawa, 1993)
(Original Assignee) Nec Corp; 日本電気株式会社     情報処理装置の電圧マージン試験方式 read request specifying one する情報
storage processor メモリ
XXX
160EP0489204A1

(Kevin Lloyd-Jones, 1992)
(Original Assignee) Hewlett Packard Ltd     

(Current Assignee)
Hewlett Packard Ltd
Reprogrammable data storage device storage processor data indicative
storage interface following steps
PCI Express bus interface power up
XXXXX




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
WO2006113334A2

Filed: 2006-04-13     Issued: 2006-10-26

In-line non volatile memory disk read cache and write buffer

(Original Assignee) Microsoft Corporation     

Clark D. Nicholson, Michael R. Fortin, Shaun B. Wiley, Cenk Ergan
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state (solid state) storage medium in response to requests from a computer system (power connectors, computer system) , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
WO2006113334A2
CLAIM 1
. An in-line persistent storage device comprising : a housing adapted to be connected to a disk drive connector of a disk drive ;
an array of solid state (solid state) , non-volatile (" ;
NV" ;
) memory blocks mounted within the housing and in communication with the disk drive and a controller , the controller in communication with the disk drive , the controller for controlling the NV memory and adapted to store at least one data block received from a computing device in at least one memory block in NV memory and flush the at least one block of data in response to receiving a flush command , the array of solid state NV memory blocks .

WO2006113334A2
CLAIM 8
. The in-line persistent storage device of claim 1 further comprising a pair of power connectors (computer system) , one of the pair of power connectors connecting to a disk drive power connector and the other of the pair of connectors connecting to a power cable .

WO2006113334A2
CLAIM 16
. The in-line persistent storage device of claim 1 wherein the controller is further adapted to provide capabilities to the computer system (computer system) in response to receiving a request to provide capabilities .

US9632727B2
CLAIM 2
. The apparatus of claim 1 , wherein the indexer assigns logical addresses to physical addresses by use of index entries , and wherein the indexer removes an index entry (available space) corresponding to the identified logical address in response to the message .
WO2006113334A2
CLAIM 18
. The in-line persistent storage device of claim 1 wherein the controller is further adapted to : determine when the NV memory available space (index entry) is below a threshold ;
and flush at least a portion of the NV memory to the disk drive if the NV memory available space is below the threshold .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system (power connectors, computer system) , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
WO2006113334A2
CLAIM 8
. The in-line persistent storage device of claim 1 further comprising a pair of power connectors (computer system) , one of the pair of power connectors connecting to a disk drive power connector and the other of the pair of connectors connecting to a power cable .

WO2006113334A2
CLAIM 16
. The in-line persistent storage device of claim 1 wherein the controller is further adapted to provide capabilities to the computer system (computer system) in response to receiving a request to provide capabilities .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
WO2005103878A2

Filed: 2005-04-21     Issued: 2005-11-03

Method and system for compression of files for storage and operation on compressed files

(Original Assignee) Storewiz, Inc.     

Gil Sever, Noach Amit, Nadav Kedem, Yakov Cohen
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system , including storing data (computer program) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
WO2005103878A2
CLAIM 39
. For use with a file access storage , a computer program (storing data) product comprising a computer useable medium having computer readable program code embodied therein of creating compressed file for storage , said computer program product comprising : a) computer readable program code for causing the computer to compress a raw file and thereby generating the compressed data , wherein at least one fixed-size portion of data (cluster) of the raw file is sequentially processed into corresponding compressed section divided into at least one fixed-size compression logical units (CLU) ;
b) computer readable program code for causing the computer to facilitate storing of the compressed data as a compressed file , the compressed file containing the compressed sections corresponding to the clusters of the raw file and a header comprising unique file descriptor ;
c) computer readable program code for causing the computer to create a section table comprising records of compressed sections , said records holding information on CLUs corresponding to the compressed section and storage location pointers pertaining to said CLUs .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA (predefined criteria) bus interface , a Small Computer System Interface (said list) (SCSI) bus interface , an internet SCSI interface (logical unit) , and a Fibre Channel interface .
WO2005103878A2
CLAIM 1
. For use with a file access storage , a method of creating compressed file for storage , said method comprising : a) compressing a raw file and thereby generating compressed data , wherein at least one fixed-size portion of data (cluster) of the raw file is sequentially processed into corresponding compressed section divided into at least one fixed-size compression logical unit (internet SCSI interface, read request) s (CLU) ;
b) facilitating storing of the compressed data as a compressed file , the compressed file containing the compressed sections corresponding to the clusters of the raw file and a header comprising unique file descriptor ;
c) creating a section table comprising at least one record describing a compressed section , said record holding at least information on CLUs corresponding to the compressed section and storage location pointers pertaining to said CLUs .

WO2005103878A2
CLAIM 11
. The method of Claim 1 wherein compressing of a file is providing only if the file fits predefined criteria (external SATA) .

WO2005103878A2
CLAIM 20
. The method of Claim 18 further comprising handling a list of free CLUs released during writing data to the compressed file , said list (Small Computer System Interface) is handled during all sessions related to the file until the file is closed .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (computer program) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client (entire file) that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
WO2005103878A2
CLAIM 39
. For use with a file access storage , a computer program (storing data) product comprising a computer useable medium having computer readable program code embodied therein of creating compressed file for storage , said computer program product comprising : a) computer readable program code for causing the computer to compress a raw file and thereby generating the compressed data , wherein at least one fixed-size portion of data (cluster) of the raw file is sequentially processed into corresponding compressed section divided into at least one fixed-size compression logical units (CLU) ;
b) computer readable program code for causing the computer to facilitate storing of the compressed data as a compressed file , the compressed file containing the compressed sections corresponding to the clusters of the raw file and a header comprising unique file descriptor ;
c) computer readable program code for causing the computer to create a section table comprising records of compressed sections , said records holding information on CLUs corresponding to the compressed section and storage location pointers pertaining to said CLUs .

WO2005103878A2
CLAIM 41
. For use with file access storage , a method of writing data to a file stored as compressed data , wherein the compressed data of a raw file are packed into one or more compressed units , said method facilitating update of one or more corresponding compressed unit with no need of restoring the entire file (storage client) whilst maintaining de- fragmented structure of the compressed units .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client (entire file) ;

a storage processor (data store) coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
WO2005103878A2
CLAIM 15
. The method of Claim 1 wherein the size of the last CLU in the last compressed section is defined by actual size of compressed data store (storage processor) d in said CLU .

WO2005103878A2
CLAIM 41
. For use with file access storage , a method of writing data to a file stored as compressed data , wherein the compressed data of a raw file are packed into one or more compressed units , said method facilitating update of one or more corresponding compressed unit with no need of restoring the entire file (storage client) whilst maintaining de- fragmented structure of the compressed units .

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (data store) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
WO2005103878A2
CLAIM 15
. The method of Claim 1 wherein the size of the last CLU in the last compressed section is defined by actual size of compressed data store (storage processor) d in said CLU .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request (logical unit) specifying one or more logical addresses included in the empty-block directive command , the storage processor (data store) returns a predetermined data string .
WO2005103878A2
CLAIM 1
. For use with a file access storage , a method of creating compressed file for storage , said method comprising : a) compressing a raw file and thereby generating compressed data , wherein at least one fixed-size portion of data (cluster) of the raw file is sequentially processed into corresponding compressed section divided into at least one fixed-size compression logical unit (internet SCSI interface, read request) s (CLU) ;
b) facilitating storing of the compressed data as a compressed file , the compressed file containing the compressed sections corresponding to the clusters of the raw file and a header comprising unique file descriptor ;
c) creating a section table comprising at least one record describing a compressed section , said record holding at least information on CLUs corresponding to the compressed section and storage location pointers pertaining to said CLUs .

WO2005103878A2
CLAIM 15
. The method of Claim 1 wherein the size of the last CLU in the last compressed section is defined by actual size of compressed data store (storage processor) d in said CLU .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
CN1632765A

Filed: 2004-12-31     Issued: 2005-06-29

一种闪存文件系统管理方法

(Original Assignee) 大唐微电子技术有限公司     

叶青, 孙旭, 阮征, 傅宇晨, 李治国
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations (进行操作) on the solid state storage medium in response to requests from a computer system , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
CN1632765A
CLAIM 1
. 一种闪存文件系统管理方法,包括以下步骤:(a)将闪存按功能划分为文件分配表区和文件数据存储区,同时将其划分为多个包含相同数量的块的块区并编号;(b)上电后,在内存中建立空间映射表,读取所述文件分配表中的有效记录和闪存中的数据块,在空间映射表中写入各文件包含的数据块所在块区号的信息;(c)创建新文件时,根据新文件的大小计算需要占用多少数据块,并判断空闲块的数量是否够用,如果不够,先进行擦除整理操作;(d)在文件分配表中追加一条新记录,将该新文件的标识、文件所占块的数量、分配的文件索引号写入到该新记录中;(e)依次将该新文件的各个数据块写入空闲块中,并查询该各个数据块所在块区号在空间映射表中对应的位置,将各数据块所在块区号写入该空间映射表,完成一个新文件的创建;(f)更新文件数据时,只对文件数据存储区进行操作 (storage operations) ,将新的数据写入到新的数据块中或者添加在原数据块的剩余空间中,完成更新;(g)读取数据时,根据用户给出的偏移和长度确定要读的数据在文件的哪些数据块中,由文件标识和级联块号查询这些数据块所在块区号在空间映射表中的位置,并得到其所在块区号;(h)根据文件标识和级联块号在查到的块区内查找该文件的数据块,将数据读入内存,处理后交给用户。

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface (初始值) , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (的文件) (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
CN1632765A
CLAIM 1
. 一种闪存文件系统管理方法,包括以下步骤:(a)将闪存按功能划分为文件分配表区和文件数据存储区,同时将其划分为多个包含相同数量的块的块区并编号;(b)上电后,在内存中建立空间映射表,读取所述文件分配表中的有效记录和闪存中的数据块,在空间映射表中写入各文件包含的数据块所在块区号的信息;(c)创建新文件时,根据新文件的大小计算需要占用多少数据块,并判断空闲块的数量是否够用,如果不够,先进行擦除整理操作;(d)在文件分配表中追加一条新记录,将该新文件的标识、文件所占块的数量、分配的文件 (Serial ATA) 索引号写入到该新记录中;(e)依次将该新文件的各个数据块写入空闲块中,并查询该各个数据块所在块区号在空间映射表中对应的位置,将各数据块所在块区号写入该空间映射表,完成一个新文件的创建;(f)更新文件数据时,只对文件数据存储区进行操作,将新的数据写入到新的数据块中或者添加在原数据块的剩余空间中,完成更新;(g)读取数据时,根据用户给出的偏移和长度确定要读的数据在文件的哪些数据块中,由文件标识和级联块号查询这些数据块所在块区号在空间映射表中的位置,并得到其所在块区号;(h)根据文件标识和级联块号在查到的块区内查找该文件的数据块,将数据读入内存,处理后交给用户。

CN1632765A
CLAIM 6
. 如权利要求1或2所述的方法,其特征在于,所述文件索引号的分配由以下步骤实现:(o)上电后,在内存中开辟一个文件索引管理区,该管理区包含的二进制位数与最大文件数相同,初始值 (PCI Express bus interface) 为0;(p)逐条扫描文件分配表,每检索到一条有效记录,将文件索引号管理区内该记录中的文件索引号对应的二进制位置“1”;(q)创建一个新文件时,扫描文件索引管理区中的每一位,将扫描到的第一个为“0”的位对应的索引号分配给新文件,然后将该位置1;(r)删除一个文件后,把该文件索引号在文件索引管理区中对应的位置为0。

US9632727B2
CLAIM 8
. The system of claim 7 , further comprising means for providing a storage interface to accept requests to perform storage operations (进行操作) on the solid-state storage medium in reference to the logical blocks and to accept the message identifying the logical block that is not being used to reference data stored on the solid-state storage medium .
CN1632765A
CLAIM 1
. 一种闪存文件系统管理方法,包括以下步骤:(a)将闪存按功能划分为文件分配表区和文件数据存储区,同时将其划分为多个包含相同数量的块的块区并编号;(b)上电后,在内存中建立空间映射表,读取所述文件分配表中的有效记录和闪存中的数据块,在空间映射表中写入各文件包含的数据块所在块区号的信息;(c)创建新文件时,根据新文件的大小计算需要占用多少数据块,并判断空闲块的数量是否够用,如果不够,先进行擦除整理操作;(d)在文件分配表中追加一条新记录,将该新文件的标识、文件所占块的数量、分配的文件索引号写入到该新记录中;(e)依次将该新文件的各个数据块写入空闲块中,并查询该各个数据块所在块区号在空间映射表中对应的位置,将各数据块所在块区号写入该空间映射表,完成一个新文件的创建;(f)更新文件数据时,只对文件数据存储区进行操作 (storage operations) ,将新的数据写入到新的数据块中或者添加在原数据块的剩余空间中,完成更新;(g)读取数据时,根据用户给出的偏移和长度确定要读的数据在文件的哪些数据块中,由文件标识和级联块号查询这些数据块所在块区号在空间映射表中的位置,并得到其所在块区号;(h)根据文件标识和级联块号在查到的块区内查找该文件的数据块,将数据读入内存,处理后交给用户。




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US7120051B2

Filed: 2004-12-14     Issued: 2006-10-10

Pipelined programming of non-volatile memories using early data

(Original Assignee) SanDisk Corp     (Current Assignee) SanDisk Technologies LLC

Sergey Anatolievich Gorobets, Yan Li
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system , including storing data (more sector) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US7120051B2
CLAIM 13
. The method of claim 12 , wherein said page comprises multiple sectors , wherein said first data content comprises one or more , but less than all , sectors of the page , and the additional data content comprises one or more sector (storing data) s of the page .

US9632727B2
CLAIM 5
. The apparatus of claim 1 , further comprising a garbage collector (logical page) configured to designate that the physical address previously assigned to the identified logical address comprises data suitable for removal from the solid-state storage medium in response to the message .
US7120051B2
CLAIM 24
. The method of claim 23 , wherein said plurality of storage units are multi-state storage units and are formed into a physical page storing a plurality of logical page (garbage collector, read request specifying one) s and wherein the first data content specifies data content for less than all of said plurality of pages .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface (new data) , and a Fibre Channel interface .
US7120051B2
CLAIM 33
. A method of operating a non-volatile memory , wherein data is concurrently programmable from multiple data buffers into a plurality of storage units formed into a physical page , the method comprising : performing a programming operation where data is written from a plurality of said buffers into said physical page ;
verifying that the data content of storage units corresponding to one or more , but less than all , of said plurality of buffers is successfully written ;
continuing said programming operation for the storage units corresponding to ones of said plurality of buffers other than those corresponding to storage units whose content is verified as successfully written ;
and concurrently with said continuing said programming operation , receiving new data (internet SCSI interface) content into the buffers corresponding to storage units whose content is verified as successfully written .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (more sector) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
US7120051B2
CLAIM 13
. The method of claim 12 , wherein said page comprises multiple sectors , wherein said first data content comprises one or more , but less than all , sectors of the page , and the additional data content comprises one or more sector (storing data) s of the page .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor coupled to the storage interface ;

a flash memory device (programming operations) coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US7120051B2
CLAIM 6
. The method of claim 5 , wherein said programming operations (flash memory device) use a programming waveform comprising a series of pulses of increasing magnitude .

US9632727B2
CLAIM 13
. The system of claim 12 , wherein the logical-to-physical translation layer is stored in the flash memory device (programming operations) .
US7120051B2
CLAIM 6
. The method of claim 5 , wherein said programming operations (flash memory device) use a programming waveform comprising a series of pulses of increasing magnitude .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one (logical page) or more logical addresses included in the empty-block directive command , the storage processor returns a predetermined data string .
US7120051B2
CLAIM 24
. The method of claim 23 , wherein said plurality of storage units are multi-state storage units and are formed into a physical page storing a plurality of logical page (garbage collector, read request specifying one) s and wherein the first data content specifies data content for less than all of said plurality of pages .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US20060075057A1

Filed: 2004-08-30     Issued: 2006-04-06

Remote direct memory access system and method

(Original Assignee) International Business Machines Corp     (Current Assignee) International Business Machines Corp

Kevin Gildea, Rama Govindaraju, Donald Grice, Peter Hochschild, Fu Chung Chang
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium (write operation) in response to requests from a computer system , including storing data (readable recording medium) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US20060075057A1
CLAIM 10
. A method as claimed in claim 1 , wherein the DMA request specifies a write operation (solid state storage medium) from the sending node to the receiving node .

US20060075057A1
CLAIM 33
. A machine-readable recording medium (storing data) having instructions recorded thereon for performing a method of transferring data by direct memory access (DMA) over a network between a memory of a first node of a multi-processor system having a plurality of nodes connected by a network and a memory of a second node of the multi-processor system , the method comprising : presenting to a first node a request for DMA access with respect to the second memory of the second node ;
transmitting data stored in the memory of a sending node selected from the first and second nodes to a receiving node selected from the other one of the first and second nodes in a plurality of portions in fulfillment of the DMA request , each portion transmitted together with identifying information and information identifying a location for storing the portion in the memory of the receiving node ;
receiving at the receiving node at least a portion of the plurality of transmitted portions together with the identifying information and location identifying information ;
and storing the data contained in the received portion at the location in the memory of the receiving node identified by the location identifying information .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology (when i) Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface (direct memory access, device driver) , and a Fibre Channel interface .
US20060075057A1
CLAIM 1
. A method of transferring data by direct memory access (internet SCSI interface) (DMA) over a network between a memory of a first node of a multi-processor system having a plurality of nodes connected by a network and a memory of a second node of the multi-processor system , comprising : presenting to a first node a DMA request with respect to the second memory of the second node ;
transmitting data stored in the memory of a sending node selected from the first and second nodes to a receiving node selected from the other one of the first and second nodes in a plurality of portions in fulfillment of the DMA request , each portion transmitted together with identifying information and information identifying a location for storing the portion in the memory of the receiving node ;
receiving at the receiving node at least a portion of the plurality of transmitted portions together with the identifying information and location identifying information ;
and storing the data contained in the received portion at the location in the memory of the receiving node identified by the location identifying information .

US20060075057A1
CLAIM 18
. A method as claimed in claim 17 , wherein the resource manager is a device driver (internet SCSI interface) of the network adapter .

US20060075057A1
CLAIM 26
. A multi-processor system as claimed in claim 24 , wherein the first ULP is operable to specify a transaction identification (TID) when i (Advanced Technology) nitiating the DMA request , the first network adapter being operable to transmit the TID with each transmitted portion of the data .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (readable recording medium) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client (different paths) that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
US20060075057A1
CLAIM 31
. A multi-processor system as claimed in claim 30 , wherein the first network adapter is operable to transmit respective ones of the portions of the data over different paths (storage client) of the network to the second network adapter .

US20060075057A1
CLAIM 33
. A machine-readable recording medium (storing data) having instructions recorded thereon for performing a method of transferring data by direct memory access (DMA) over a network between a memory of a first node of a multi-processor system having a plurality of nodes connected by a network and a memory of a second node of the multi-processor system , the method comprising : presenting to a first node a request for DMA access with respect to the second memory of the second node ;
transmitting data stored in the memory of a sending node selected from the first and second nodes to a receiving node selected from the other one of the first and second nodes in a plurality of portions in fulfillment of the DMA request , each portion transmitted together with identifying information and information identifying a location for storing the portion in the memory of the receiving node ;
receiving at the receiving node at least a portion of the plurality of transmitted portions together with the identifying information and location identifying information ;
and storing the data contained in the received portion at the location in the memory of the receiving node identified by the location identifying information .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client (different paths) ;

a storage processor (data store) coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US20060075057A1
CLAIM 1
. A method of transferring data by direct memory access (DMA) over a network between a memory of a first node of a multi-processor system having a plurality of nodes connected by a network and a memory of a second node of the multi-processor system , comprising : presenting to a first node a DMA request with respect to the second memory of the second node ;
transmitting data store (storage processor) d in the memory of a sending node selected from the first and second nodes to a receiving node selected from the other one of the first and second nodes in a plurality of portions in fulfillment of the DMA request , each portion transmitted together with identifying information and information identifying a location for storing the portion in the memory of the receiving node ;
receiving at the receiving node at least a portion of the plurality of transmitted portions together with the identifying information and location identifying information ;
and storing the data contained in the received portion at the location in the memory of the receiving node identified by the location identifying information .

US20060075057A1
CLAIM 31
. A multi-processor system as claimed in claim 30 , wherein the first network adapter is operable to transmit respective ones of the portions of the data over different paths (storage client) of the network to the second network adapter .

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (data store) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
US20060075057A1
CLAIM 1
. A method of transferring data by direct memory access (DMA) over a network between a memory of a first node of a multi-processor system having a plurality of nodes connected by a network and a memory of a second node of the multi-processor system , comprising : presenting to a first node a DMA request with respect to the second memory of the second node ;
transmitting data store (storage processor) d in the memory of a sending node selected from the first and second nodes to a receiving node selected from the other one of the first and second nodes in a plurality of portions in fulfillment of the DMA request , each portion transmitted together with identifying information and information identifying a location for storing the portion in the memory of the receiving node ;
receiving at the receiving node at least a portion of the plurality of transmitted portions together with the identifying information and location identifying information ;
and storing the data contained in the received portion at the location in the memory of the receiving node identified by the location identifying information .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor (data store) returns a predetermined data string .
US20060075057A1
CLAIM 1
. A method of transferring data by direct memory access (DMA) over a network between a memory of a first node of a multi-processor system having a plurality of nodes connected by a network and a memory of a second node of the multi-processor system , comprising : presenting to a first node a DMA request with respect to the second memory of the second node ;
transmitting data store (storage processor) d in the memory of a sending node selected from the first and second nodes to a receiving node selected from the other one of the first and second nodes in a plurality of portions in fulfillment of the DMA request , each portion transmitted together with identifying information and information identifying a location for storing the portion in the memory of the receiving node ;
receiving at the receiving node at least a portion of the plurality of transmitted portions together with the identifying information and location identifying information ;
and storing the data contained in the received portion at the location in the memory of the receiving node identified by the location identifying information .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
JP2006031268A

Filed: 2004-07-14     Issued: 2006-02-02

情報処理装置、及び記憶制御装置

(Original Assignee) Sharp Corp; シャープ株式会社     

Yoshiyuki Nakai, Yoichi Shimazawa, Koichi Tsunoda, Takao Yamanouchi, 嘉之 中井, 隆男 山之内, 耀一 嶋澤, 浩一 角田
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller (前記記憶部) configured to implement storage operations (前記記憶部) on the solid state storage medium in response to requests from a computer system , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
JP2006031268A
CLAIM 1
情報を処理する情報処理部と、データを記憶する記憶部と、前記情報処理部及び前記記憶部 (state storage controller, storage operations, storage controller, storage client, state storage controller configured to implement storage operations) に接続され、前記記憶部に対する情報の入出力を制御する記憶制御部とを備える情報処理装置において、 前記情報処理部は、前記記憶部が記憶している特定のデータの消去指示を前記記憶制御部へ出力する手段を備え、 前記記憶制御部は、 前記データを上書き消去するための上書き用データを生成するデータ生成手段と、 前記情報処理部から入力された前記消去指示に従って、前記データ生成手段が生成した上書き用データ、及び前記上書き用データを上書きすることによって前記データを消去することを指示する上書き消去指示を前記記憶部へ送信する送信手段と を備え、 前記記憶部は、前記記憶制御部から入力された前記上書き消去指示に従って、前記データが記憶されているアドレスに前記上書き用データを書き込む手段を備えること を特徴とする情報処理装置。

US9632727B2
CLAIM 3
. The apparatus of claim 1 , wherein the indexer assigns logical addresses to physical addresses by use of index metadata maintained in a memory of the storage controller (前記記憶部) .
JP2006031268A
CLAIM 1
情報を処理する情報処理部と、データを記憶する記憶部と、前記情報処理部及び前記記憶部 (state storage controller, storage operations, storage controller, storage client, state storage controller configured to implement storage operations) に接続され、前記記憶部に対する情報の入出力を制御する記憶制御部とを備える情報処理装置において、 前記情報処理部は、前記記憶部が記憶している特定のデータの消去指示を前記記憶制御部へ出力する手段を備え、 前記記憶制御部は、 前記データを上書き消去するための上書き用データを生成するデータ生成手段と、 前記情報処理部から入力された前記消去指示に従って、前記データ生成手段が生成した上書き用データ、及び前記上書き用データを上書きすることによって前記データを消去することを指示する上書き消去指示を前記記憶部へ送信する送信手段と を備え、 前記記憶部は、前記記憶制御部から入力された前記上書き消去指示に従って、前記データが記憶されているアドレスに前記上書き用データを書き込む手段を備えること を特徴とする情報処理装置。

US9632727B2
CLAIM 4
. The apparatus of claim 1 , wherein the indexer comprises firmware of the solid-state storage controller (前記記憶部) .
JP2006031268A
CLAIM 1
情報を処理する情報処理部と、データを記憶する記憶部と、前記情報処理部及び前記記憶部 (state storage controller, storage operations, storage controller, storage client, state storage controller configured to implement storage operations) に接続され、前記記憶部に対する情報の入出力を制御する記憶制御部とを備える情報処理装置において、 前記情報処理部は、前記記憶部が記憶している特定のデータの消去指示を前記記憶制御部へ出力する手段を備え、 前記記憶制御部は、 前記データを上書き消去するための上書き用データを生成するデータ生成手段と、 前記情報処理部から入力された前記消去指示に従って、前記データ生成手段が生成した上書き用データ、及び前記上書き用データを上書きすることによって前記データを消去することを指示する上書き消去指示を前記記憶部へ送信する送信手段と を備え、 前記記憶部は、前記記憶制御部から入力された前記上書き消去指示に従って、前記データが記憶されているアドレスに前記上書き用データを書き込む手段を備えること を特徴とする情報処理装置。

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller (前記記憶部) comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
JP2006031268A
CLAIM 1
情報を処理する情報処理部と、データを記憶する記憶部と、前記情報処理部及び前記記憶部 (state storage controller, storage operations, storage controller, storage client, state storage controller configured to implement storage operations) に接続され、前記記憶部に対する情報の入出力を制御する記憶制御部とを備える情報処理装置において、 前記情報処理部は、前記記憶部が記憶している特定のデータの消去指示を前記記憶制御部へ出力する手段を備え、 前記記憶制御部は、 前記データを上書き消去するための上書き用データを生成するデータ生成手段と、 前記情報処理部から入力された前記消去指示に従って、前記データ生成手段が生成した上書き用データ、及び前記上書き用データを上書きすることによって前記データを消去することを指示する上書き消去指示を前記記憶部へ送信する送信手段と を備え、 前記記憶部は、前記記憶制御部から入力された前記上書き消去指示に従って、前記データが記憶されているアドレスに前記上書き用データを書き込む手段を備えること を特徴とする情報処理装置。

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client (前記記憶部) that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
JP2006031268A
CLAIM 1
情報を処理する情報処理部と、データを記憶する記憶部と、前記情報処理部及び前記記憶部 (state storage controller, storage operations, storage controller, storage client, state storage controller configured to implement storage operations) に接続され、前記記憶部に対する情報の入出力を制御する記憶制御部とを備える情報処理装置において、 前記情報処理部は、前記記憶部が記憶している特定のデータの消去指示を前記記憶制御部へ出力する手段を備え、 前記記憶制御部は、 前記データを上書き消去するための上書き用データを生成するデータ生成手段と、 前記情報処理部から入力された前記消去指示に従って、前記データ生成手段が生成した上書き用データ、及び前記上書き用データを上書きすることによって前記データを消去することを指示する上書き消去指示を前記記憶部へ送信する送信手段と を備え、 前記記憶部は、前記記憶制御部から入力された前記上書き消去指示に従って、前記データが記憶されているアドレスに前記上書き用データを書き込む手段を備えること を特徴とする情報処理装置。

US9632727B2
CLAIM 8
. The system of claim 7 , further comprising means for providing a storage interface to accept requests to perform storage operations (前記記憶部) on the solid-state storage medium in reference to the logical blocks and to accept the message identifying the logical block that is not being used to reference data stored on the solid-state storage medium .
JP2006031268A
CLAIM 1
情報を処理する情報処理部と、データを記憶する記憶部と、前記情報処理部及び前記記憶部 (state storage controller, storage operations, storage controller, storage client, state storage controller configured to implement storage operations) に接続され、前記記憶部に対する情報の入出力を制御する記憶制御部とを備える情報処理装置において、 前記情報処理部は、前記記憶部が記憶している特定のデータの消去指示を前記記憶制御部へ出力する手段を備え、 前記記憶制御部は、 前記データを上書き消去するための上書き用データを生成するデータ生成手段と、 前記情報処理部から入力された前記消去指示に従って、前記データ生成手段が生成した上書き用データ、及び前記上書き用データを上書きすることによって前記データを消去することを指示する上書き消去指示を前記記憶部へ送信する送信手段と を備え、 前記記憶部は、前記記憶制御部から入力された前記上書き消去指示に従って、前記データが記憶されているアドレスに前記上書き用データを書き込む手段を備えること を特徴とする情報処理装置。

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client (前記記憶部) ;

a storage processor coupled to the storage interface ;

a flash memory device (アドレス) coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
JP2006031268A
CLAIM 1
情報を処理する情報処理部と、データを記憶する記憶部と、前記情報処理部及び前記記憶部 (state storage controller, storage operations, storage controller, storage client, state storage controller configured to implement storage operations) に接続され、前記記憶部に対する情報の入出力を制御する記憶制御部とを備える情報処理装置において、 前記情報処理部は、前記記憶部が記憶している特定のデータの消去指示を前記記憶制御部へ出力する手段を備え、 前記記憶制御部は、 前記データを上書き消去するための上書き用データを生成するデータ生成手段と、 前記情報処理部から入力された前記消去指示に従って、前記データ生成手段が生成した上書き用データ、及び前記上書き用データを上書きすることによって前記データを消去することを指示する上書き消去指示を前記記憶部へ送信する送信手段と を備え、 前記記憶部は、前記記憶制御部から入力された前記上書き消去指示に従って、前記データが記憶されているアドレス (flash memory device) に前記上書き用データを書き込む手段を備えること を特徴とする情報処理装置。

US9632727B2
CLAIM 13
. The system of claim 12 , wherein the logical-to-physical translation layer is stored in the flash memory device (アドレス) .
JP2006031268A
CLAIM 1
情報を処理する情報処理部と、データを記憶する記憶部と、前記情報処理部及び前記記憶部に接続され、前記記憶部に対する情報の入出力を制御する記憶制御部とを備える情報処理装置において、 前記情報処理部は、前記記憶部が記憶している特定のデータの消去指示を前記記憶制御部へ出力する手段を備え、 前記記憶制御部は、 前記データを上書き消去するための上書き用データを生成するデータ生成手段と、 前記情報処理部から入力された前記消去指示に従って、前記データ生成手段が生成した上書き用データ、及び前記上書き用データを上書きすることによって前記データを消去することを指示する上書き消去指示を前記記憶部へ送信する送信手段と を備え、 前記記憶部は、前記記憶制御部から入力された前記上書き消去指示に従って、前記データが記憶されているアドレス (flash memory device) に前記上書き用データを書き込む手段を備えること を特徴とする情報処理装置。

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one (する情報) or more logical addresses included in the empty-block directive command , the storage processor returns a predetermined data string .
JP2006031268A
CLAIM 1
情報を処理する情報 (read request specifying one) 処理部と、データを記憶する記憶部と、前記情報処理部及び前記記憶部に接続され、前記記憶部に対する情報の入出力を制御する記憶制御部とを備える情報処理装置において、 前記情報処理部は、前記記憶部が記憶している特定のデータの消去指示を前記記憶制御部へ出力する手段を備え、 前記記憶制御部は、 前記データを上書き消去するための上書き用データを生成するデータ生成手段と、 前記情報処理部から入力された前記消去指示に従って、前記データ生成手段が生成した上書き用データ、及び前記上書き用データを上書きすることによって前記データを消去することを指示する上書き消去指示を前記記憶部へ送信する送信手段と を備え、 前記記憶部は、前記記憶制御部から入力された前記上書き消去指示に従って、前記データが記憶されているアドレスに前記上書き用データを書き込む手段を備えること を特徴とする情報処理装置。




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
JP2005339198A

Filed: 2004-05-27     Issued: 2005-12-08

キャッシュヒット率推定装置、キャッシュヒット率推定方法、プログラム及び記録媒体

(Original Assignee) Internatl Business Mach Corp <Ibm>; インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation     

Toshiyuki Hama, Ryo Hiraide, 涼 平出, 利行 濱
US9632727B2
CLAIM 2
. The apparatus of claim 1 , wherein the indexer assigns logical addresses to physical addresses by use of index entries (リスト) , and wherein the indexer removes an index entry corresponding to the identified logical address in response to the message .
JP2005339198A
CLAIM 11
それぞれの前記アクセス対象データには、当該アクセス対象データをキャッシュする優先度が定められており、 前記キャッシュ装置は、 キャッシュされた前記アクセス対象データをLRU方式により管理する、優先度毎に設けられた複数のLRUリスト (index entries) と、 アクセス要求を受けた前記アクセス対象データを、当該アクセス対象データの優先度に対応する前記LRUリストの先頭に移動するエントリ移動部と、 優先度が最も低い前記LRUリストが空である場合に、前記複数のLRUリストのそれぞれに登録された前記アクセス対象データを、より優先度が低い前記LRUリストに登録し直すシフト処理を行うLRUリストシフト部と を備え、 前記キャッシュヒット率推定関数生成部は、 前記複数のアクセス対象データの前記キャッシュ有効時間分布関数に基づいて、前記複数のLRUリストに登録された前記アクセス対象データの合計数の期待値を求めるエントリ数期待値関数を生成するエントリ数期待値関数生成部と、 前記エントリ数期待値関数に基づいて、前記シフト処理の周期の期待値を算出するシフト周期算出部と、 前記シフト処理の周期を複数に等分した各時点において前記アクセス対象データへのアクセス要求を受けてから当該アクセス対象データが他の前記アクセス対象データに置換されるまでのリプレース時間の期待値を算出するリプレース時間算出部と、 それぞれの前記アクセス対象データについて、前記シフト処理の周期を複数に等分した各時点において当該アクセス対象データに対するアクセス要求を受信してから前記リプレース時間の期待値により定められる時間の経過までに当該アクセス対象データに対する次のアクセス要求を受信する確率を算出する次アクセスヒット率推定関数を、前記次アクセスヒット時間分布関数及び前記リプレース時間に基づいて生成する次アクセスヒット率推定関数生成部と、 それぞれの前記アクセス対象データについて、前記シフト処理の周期を複数に等分した前記複数の時点のそれぞれにおいて当該アクセス対象データに対するアクセス要求を受信した場合の前記次アクセスヒット率推定関数を全ての前記時点について平均し、当該アクセス対象データの前記キャッシュヒット率推定関数とする次アクセスヒット率平均化部と を有する 請求項7記載のキャッシュヒット率推定装置。

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client (サーバ) that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
JP2005339198A
CLAIM 12
前記アクセス対象データは、前記アクセス要求を受信したサーバ (storage client) 装置上で当該アクセス要求に対応するサーバプログラムを、前記アクセスコストにより指定される処理時間実行することにより生成され、 前記キャッシュ装置は、前記サーバ装置により生成された前記アクセス対象データをキャッシュするキャッシュ記憶領域を備える 請求項2記載のキャッシュヒット率推定装置。

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client (サーバ) ;

a storage processor coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
JP2005339198A
CLAIM 12
前記アクセス対象データは、前記アクセス要求を受信したサーバ (storage client) 装置上で当該アクセス要求に対応するサーバプログラムを、前記アクセスコストにより指定される処理時間実行することにより生成され、 前記キャッシュ装置は、前記サーバ装置により生成された前記アクセス対象データをキャッシュするキャッシュ記憶領域を備える 請求項2記載のキャッシュヒット率推定装置。




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
JP2005293774A

Filed: 2004-04-02     Issued: 2005-10-20

ディスク装置の制御方法

(Original Assignee) Hitachi Global Storage Technologies Netherlands Bv; ヒタチグローバルストレージテクノロジーズネザーランドビーブイ     

Tetsuya Kamimura, 上村  哲也
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations (の符号) on the solid state storage medium in response to requests from a computer system , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
JP2005293774A
CLAIM 3
請求項2記載のディスク装置の制御方法において、前記一つの管理領域に連続する複数の論理ブロックアドレスの値を書き込む際の符号 (storage operations) 化方式として、論理ブロックアドレスの開始アドレスと、連続して書き込むサイズとを用いること を特徴とするディスク装置の制御方法。

US9632727B2
CLAIM 8
. The system of claim 7 , further comprising means for providing a storage interface to accept requests to perform storage operations (の符号) on the solid-state storage medium in reference to the logical blocks and to accept the message identifying the logical block that is not being used to reference data stored on the solid-state storage medium .
JP2005293774A
CLAIM 3
請求項2記載のディスク装置の制御方法において、前記一つの管理領域に連続する複数の論理ブロックアドレスの値を書き込む際の符号 (storage operations) 化方式として、論理ブロックアドレスの開始アドレスと、連続して書き込むサイズとを用いること を特徴とするディスク装置の制御方法。




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US7139864B2

Filed: 2003-12-30     Issued: 2006-11-21

Non-volatile memory and method with block management system

(Original Assignee) SanDisk Corp     (Current Assignee) SanDisk Technologies LLC

Alan David Bennett, Alan Douglas Bryce, Sergey Gorobets, Alan Welsh Sinclair, Peter John Smith
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system , including storing data (said memory) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data (said memory) pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US7139864B2
CLAIM 1
. In a nonvolatile memory organized into a plurality of blocks , each block being a plurality of memory units that are erasable together , each memory unit for storing a logical unit of data , a method of storing and updating data in said memory (store data, storing data) comprising : organizing data into a plurality of logical groups , each logical group partitioned into a plurality of logical units of data ;
each logical unit storable in a memory unit of a block ;
storing all logical units of a given logical group among memory units of a first block according to a first order ;
storing a series of updated logical units of said given logical group among memory units of a second block dedicated to said given logical group according to a second order , until a predetermined closure condition exists that closes said second block to storing further updates ;
and responsive to said second block being closed , either : replacing said first block with said second block when said second and first orders are similar , or replacing said first block with a third block when said second and first orders are not similar , said third block having been consolidated according to said first order with a latest version of each logical unit of said given logical group gathered from said first and second blocks .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology (second order) Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
US7139864B2
CLAIM 1
. In a nonvolatile memory organized into a plurality of blocks , each block being a plurality of memory units that are erasable together , each memory unit for storing a logical unit of data , a method of storing and updating data in said memory comprising : organizing data into a plurality of logical groups , each logical group partitioned into a plurality of logical units of data ;
each logical unit storable in a memory unit of a block ;
storing all logical units of a given logical group among memory units of a first block according to a first order ;
storing a series of updated logical units of said given logical group among memory units of a second block dedicated to said given logical group according to a second order (Advanced Technology) , until a predetermined closure condition exists that closes said second block to storing further updates ;
and responsive to said second block being closed , either : replacing said first block with said second block when said second and first orders are similar , or replacing said first block with a third block when said second and first orders are not similar , said third block having been consolidated according to said first order with a latest version of each logical unit of said given logical group gathered from said first and second blocks .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (said memory) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
US7139864B2
CLAIM 1
. In a nonvolatile memory organized into a plurality of blocks , each block being a plurality of memory units that are erasable together , each memory unit for storing a logical unit of data , a method of storing and updating data in said memory (store data, storing data) comprising : organizing data into a plurality of logical groups , each logical group partitioned into a plurality of logical units of data ;
each logical unit storable in a memory unit of a block ;
storing all logical units of a given logical group among memory units of a first block according to a first order ;
storing a series of updated logical units of said given logical group among memory units of a second block dedicated to said given logical group according to a second order , until a predetermined closure condition exists that closes said second block to storing further updates ;
and responsive to said second block being closed , either : replacing said first block with said second block when said second and first orders are similar , or replacing said first block with a third block when said second and first orders are not similar , said third block having been consolidated according to said first order with a latest version of each logical unit of said given logical group gathered from said first and second blocks .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US20050144358A1

Filed: 2003-12-30     Issued: 2005-06-30

Management of non-volatile memory systems having large erase blocks

(Original Assignee) SanDisk Corp     (Current Assignee) SanDisk Technologies LLC

Kevin Conley, Carlos Gonzalez
US9632727B2
CLAIM 2
. The apparatus of claim 1 , wherein the indexer assigns logical addresses to physical addresses by use of index entries (logical blocks) , and wherein the indexer removes an index entry corresponding to the identified logical address in response to the message .
US20050144358A1
CLAIM 23
. The method of claim 20 , wherein the first and second ranges of logical addresses contain common addresses of logical blocks (index entries) .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer (determined sequence) System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
US20050144358A1
CLAIM 25
. A memory system , comprising : an array of non-volatile memory cells organized into a plurality of sub-arrays that individually include addressing , programming and reading circuits , the sub-arrays being divided into units of memory cells that are erased together , the erase units further being divided into units of cells that are programmed together , the programming units being identified by programming unit offset addresses within their erase units , a controller that controls operation of the memory cell array , at least one erase unit within individual ones of the sub-arrays being designated by the controller to store updated data of sequentially addressed programming units of a first group of one or more others of the erase units within individual ones of the sub-arrays in programming units having the same address order as the programming units within said at least one other of the erase units and with an address offset of zero or more , and at least another erase unit within individual ones of the sub-arrays being designated by the controller to store updated data of programming units of a second group of one or more others of the erase units within individual ones of the sub-arrays in pages according to a predetermined sequence (Small Computer, Small Computer System Interface) without regard to the address sequence or programming unit offset of the programming unit data being updated .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor (data store) coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US20050144358A1
CLAIM 20
. In a non-volatile memory having memory cells organized in groups of one or more blocks of a minimum number of cells that are simultaneously erasable and wherein a given number of host units of data are programmed into individual ones of the groups of one or more blocks , a method of updating less than all the data store (storage processor) d in a given group of one or more blocks in response to a host command , comprising : designating at least a first group of one or more blocks to store in sequential physical block locations host units of data within a first range of logical addresses without regard to whether the logical addresses of such data are sequential or not , and designating at least a second group of one or more blocks to store host units of data within a second range of logical addresses with sequential logical addresses therein designated for sequential physical locations with an address offset of zero or more .

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (data store) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
US20050144358A1
CLAIM 20
. In a non-volatile memory having memory cells organized in groups of one or more blocks of a minimum number of cells that are simultaneously erasable and wherein a given number of host units of data are programmed into individual ones of the groups of one or more blocks , a method of updating less than all the data store (storage processor) d in a given group of one or more blocks in response to a host command , comprising : designating at least a first group of one or more blocks to store in sequential physical block locations host units of data within a first range of logical addresses without regard to whether the logical addresses of such data are sequential or not , and designating at least a second group of one or more blocks to store host units of data within a second range of logical addresses with sequential logical addresses therein designated for sequential physical locations with an address offset of zero or more .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor (data store) returns a predetermined data string .
US20050144358A1
CLAIM 20
. In a non-volatile memory having memory cells organized in groups of one or more blocks of a minimum number of cells that are simultaneously erasable and wherein a given number of host units of data are programmed into individual ones of the groups of one or more blocks , a method of updating less than all the data store (storage processor) d in a given group of one or more blocks in response to a host command , comprising : designating at least a first group of one or more blocks to store in sequential physical block locations host units of data within a first range of logical addresses without regard to whether the logical addresses of such data are sequential or not , and designating at least a second group of one or more blocks to store host units of data within a second range of logical addresses with sequential logical addresses therein designated for sequential physical locations with an address offset of zero or more .

US9632727B2
CLAIM 16
. The system of claim 15 , wherein data bits of the predetermined data string have a uniform logic (n groups) level .
US20050144358A1
CLAIM 8
. In a non-volatile memory having memory cells organized in groups (uniform logic) of one or more blocks of a minimum number of cells that are simultaneously erasable and wherein a given number of pages of data are programmed into individual ones of the groups of blocks , a method of updating data in less than all pages of a given group of one or more blocks , comprising : determining whether at least one predefined condition of the data update is satisfied , and if it is determined that the condition is satisfied , thereafter writing the updated pages of data into pages of a first other group of one or more blocks having page numbers selected independently of the page numbers of the pages of data within the given group of blocks that are being updated , or if it is determined that the condition is not satisfied , thereafter writing the updated pages of data into correspondingly numbered pages of a second other group of one or more blocks .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
JP2005115600A

Filed: 2003-10-07     Issued: 2005-04-28

情報処理装置及び方法

(Original Assignee) Hitachi Ltd; 株式会社日立製作所     

Noboru Furuumi, Hisaharu Takeuchi, Misako Tamura, 昇 古海, 美佐子 田村, 久治 竹内
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data (複数通り, 要素又) pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
JP2005115600A
CLAIM 1
1以上の情報要素を有する情報セットを発行する1又は複数の情報セットソースから前記情報セットの各々に含まれる情報要素を受信する受信手段と、 前記受信された情報要素の処理を行う情報処理手段と、 受信された2以上の情報セットに含まれる未処理又は処理中の複数の情報要素に基づいて、前記2以上の情報セット又は前記複数の情報要素の処理手順を決定するものであって、前記2以上の情報セットの処理時間長の平均に関する値が、前記複数の情報要素又 (store data) は前記2以上の情報セットをそれの受信順序に従って処理するときの値以下になるような、前記受信順序とは異なる前記処理手順を決定する決定手段と を備え、前記情報処理手段は、前記決定された処理手順に基づいて、前記未処理又は処理中の複数の情報要素の処理を開始する、 情報処理装置。

JP2005115600A
CLAIM 6
前記決定手段は、前記複数の情報要素についての複数通り (store data) の前記処理手順にそれぞれ対応した複数通りの前記平均に関する値のうち最小の値となるような前記処理手順を決定する、 請求項1記載の情報処理装置。

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one (する情報) or more logical addresses included in the empty-block directive command , the storage processor returns a predetermined data string .
JP2005115600A
CLAIM 1
1以上の情報要素を有する情報 (read request specifying one) セットを発行する1又は複数の情報セットソースから前記情報セットの各々に含まれる情報要素を受信する受信手段と、 前記受信された情報要素の処理を行う情報処理手段と、 受信された2以上の情報セットに含まれる未処理又は処理中の複数の情報要素に基づいて、前記2以上の情報セット又は前記複数の情報要素の処理手順を決定するものであって、前記2以上の情報セットの処理時間長の平均に関する値が、前記複数の情報要素又は前記2以上の情報セットをそれの受信順序に従って処理するときの値以下になるような、前記受信順序とは異なる前記処理手順を決定する決定手段と を備え、前記情報処理手段は、前記決定された処理手順に基づいて、前記未処理又は処理中の複数の情報要素の処理を開始する、 情報処理装置。




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
JP2004310621A

Filed: 2003-04-10     Issued: 2004-11-04

記憶装置システムにおけるファイルアクセス方法及びファイルアクセスのためのプログラム

(Original Assignee) Hitachi Ltd; 株式会社日立製作所     

健一 ▲筑▼地, Masaaki Iwasaki, Naoto Matsunami, Junji Ogawa, Koji Sonoda, Kenichi Tsukiji, 純司 小川, 正明 岩嵜, 直人 松並, 浩二 薗田
US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor (メモリ) coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
JP2004310621A
CLAIM 4
請求項3記載のファイルアクセス方法であって、 前記属性情報には、ファイルのデータを前記ディスクコントローラが有するキャッシュメモリ (storage processor) に優先的に格納しておくよう指定するための制御情報が含まれ、 前記ディスクコントローラは前記制御情報に対応するファイルのデータを前記キャッシュメモリに優先的に格納するよう制御し、 前記制御情報に対応するファイルのデータに対するアクセス要求を受信した場合には、前記キャッシュメモリに優先的にアクセスすることを特徴とするファイルアクセス方法。

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (メモリ) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
JP2004310621A
CLAIM 4
請求項3記載のファイルアクセス方法であって、 前記属性情報には、ファイルのデータを前記ディスクコントローラが有するキャッシュメモリ (storage processor) に優先的に格納しておくよう指定するための制御情報が含まれ、 前記ディスクコントローラは前記制御情報に対応するファイルのデータを前記キャッシュメモリに優先的に格納するよう制御し、 前記制御情報に対応するファイルのデータに対するアクセス要求を受信した場合には、前記キャッシュメモリに優先的にアクセスすることを特徴とするファイルアクセス方法。

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one (する情報) or more logical addresses included in the empty-block directive command , the storage processor (メモリ) returns a predetermined data string .
JP2004310621A
CLAIM 4
請求項3記載のファイルアクセス方法であって、 前記属性情報には、ファイルのデータを前記ディスクコントローラが有するキャッシュメモリ (storage processor) に優先的に格納しておくよう指定するための制御情報が含まれ、 前記ディスクコントローラは前記制御情報に対応するファイルのデータを前記キャッシュメモリに優先的に格納するよう制御し、 前記制御情報に対応するファイルのデータに対するアクセス要求を受信した場合には、前記キャッシュメモリに優先的にアクセスすることを特徴とするファイルアクセス方法。

JP2004310621A
CLAIM 14
一又は複数の計算機と接続される記憶装置システムであって、 計算機からファイルを特定するために用いられるファイルに関する情報 (read request specifying one) を受信する第一のインタフェース制御装置と、 前記第一のインタフェース制御装置に接続される第二のインタフェース制御装置と、 前記第二のインタフェース制御装置に接続される一又は複数のディスクとを有し、 前記第一のインタフェース制御装置は、 前記記憶装置システムに格納されるファイルの内容であるファイルデータから、一部のデータを選択してインデックス情報として管理し、 計算機からアクセス対象のファイルに関する情報を有するアクセス要求を受信した場合に、該ファイルに関する情報をキーとして前記インデックス情報を検索し、検索によって選択されたファイルのデータにアクセスするよう前記第二のインタフェース制御装置を制御することを特徴とする記憶装置システム。




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
JP2004227098A

Filed: 2003-01-20     Issued: 2004-08-12

記憶デバイス制御装置の制御方法、及び記憶デバイス制御装置

(Original Assignee) Hitachi Ltd; 株式会社日立製作所     

Naotaka Kobayashi, Shinichi Nakayama, Yutaka Ogasawara, Nobuyuki Saiga, Jinichi Shikawa, 信一 中山, 直孝 小林, 裕 小笠原, 甚一 志川, 信之 雑賀
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller (調べるステップ) configured to implement storage operations on the solid state (ロック) storage medium in response to requests from a computer system , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
JP2004227098A
CLAIM 4
請求項3に記載の記憶デバイス制御装置の制御方法において、 前記チャネル制御部が、前記データ入出力要求を受信した場合にそのデータ入出力要求が前記チャネル制御部へのアクセスを許可されている前記情報処理装置から送信されたものであるかどうかを、記憶している前記情報に基づいて調べるステップ (storage controller) と、 前記チャネル制御部が、前記チャネル制御部へのアクセスを許可されていない場合にそのデータ入出力要求についての処理を行わないステップと、 を備えることを特徴とする記憶デバイス制御装置の制御方法。

JP2004227098A
CLAIM 10
情報処理装置から送信されるファイル単位でのデータ入出力要求を第一のネットワークを通じて受信するファイルアクセス処理部と、記憶デバイスに対する前記データ入出力要求に対応するI/O要求を出力するI/Oプロセッサとが形成された回路基板を有する複数の第一のチャネル制御部と、 情報処理装置から送信されるブロック (solid state, state storage medium, solid state storage medium) 単位でのデータ入出力要求を第二のネットワークを通じて受信して、記憶デバイスに対して前記データ入出力要求に対応するI/O要求を出力する第二のチャネル制御部と、 前記I/O要求に応じて前記記憶デバイスに対するデータ入出力を実行するディスク制御部と、 を含んで構成される記憶デバイス制御装置の制御方法であって、 前記第一のチャネル制御部が、前記情報処理装置から送信される、前記記憶デバイスに記憶されているデータについてのバックアップに関する設定情報を受信するステップと、 前記第一のチャネル制御部が、前記ディスク制御部に指示することにより前記ディスク制御部が前記設定情報に基づいて前記記憶デバイスに記憶されているバックアップ対象となるデータを読み出して、そのデータを前記第二のチャネル制御部に送信するステップと、 前記第二のチャネル制御部が、前記データを前記第二のネットワークに接続するバックアップデバイスに送信するステップと、 を備えることを特徴とする記憶デバイス制御装置の制御方法。

US9632727B2
CLAIM 2
. The apparatus of claim 1 , wherein the indexer assigns logical addresses to physical addresses by use of index entries (リスト) , and wherein the indexer removes an index entry corresponding to the identified logical address in response to the message .
JP2004227098A
CLAIM 12
情報処理装置から送信されるファイル単位でのデータ入出力要求をネットワークを通じて受信するファイルアクセス処理部と、記憶デバイスに対する前記データ入出力要求に対応するI/O要求を出力するI/Oプロセッサとが形成された回路基板を有する複数のチャネル制御部と、 前記I/Oプロセッサから送信される前記I/O要求に応じて前記記憶デバイスに対するデータ入出力を実行するディスク制御部と、 を含んで構成される記憶デバイス制御装置の制御方法であって、 前記チャネル制御部が、前記情報処理装置から送信される、リスト (index entries) アに関する設定情報を受信するステップと、 前記チャネル制御部が、前記設定情報に従って前記ネットワークに接続されているバックアップデバイスからバックアップされているデータを読み出してこれを前記記憶デバイスに書き込むステップと、 を備えることを特徴とする記憶デバイス制御装置の制御方法。

US9632727B2
CLAIM 3
. The apparatus of claim 1 , wherein the indexer assigns logical addresses to physical addresses by use of index metadata maintained in a memory of the storage controller (調べるステップ) .
JP2004227098A
CLAIM 4
請求項3に記載の記憶デバイス制御装置の制御方法において、 前記チャネル制御部が、前記データ入出力要求を受信した場合にそのデータ入出力要求が前記チャネル制御部へのアクセスを許可されている前記情報処理装置から送信されたものであるかどうかを、記憶している前記情報に基づいて調べるステップ (storage controller) と、 前記チャネル制御部が、前記チャネル制御部へのアクセスを許可されていない場合にそのデータ入出力要求についての処理を行わないステップと、 を備えることを特徴とする記憶デバイス制御装置の制御方法。

US9632727B2
CLAIM 4
. The apparatus of claim 1 , wherein the indexer comprises firmware of the solid-state storage controller (調べるステップ) .
JP2004227098A
CLAIM 4
請求項3に記載の記憶デバイス制御装置の制御方法において、 前記チャネル制御部が、前記データ入出力要求を受信した場合にそのデータ入出力要求が前記チャネル制御部へのアクセスを許可されている前記情報処理装置から送信されたものであるかどうかを、記憶している前記情報に基づいて調べるステップ (storage controller) と、 前記チャネル制御部が、前記チャネル制御部へのアクセスを許可されていない場合にそのデータ入出力要求についての処理を行わないステップと、 を備えることを特徴とする記憶デバイス制御装置の制御方法。

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller (調べるステップ) comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
JP2004227098A
CLAIM 4
請求項3に記載の記憶デバイス制御装置の制御方法において、 前記チャネル制御部が、前記データ入出力要求を受信した場合にそのデータ入出力要求が前記チャネル制御部へのアクセスを許可されている前記情報処理装置から送信されたものであるかどうかを、記憶している前記情報に基づいて調べるステップ (storage controller) と、 前記チャネル制御部が、前記チャネル制御部へのアクセスを許可されていない場合にそのデータ入出力要求についての処理を行わないステップと、 を備えることを特徴とする記憶デバイス制御装置の制御方法。

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client (前記割り当て, サーバ) that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
JP2004227098A
CLAIM 1
情報処理装置から送信されるファイル単位でのデータ入出力要求をネットワークを通じて受信するファイルアクセス処理部と、記憶デバイスに対する前記データ入出力要求に対応するI/O要求を出力するI/Oプロセッサとが形成された回路基板を有する複数のチャネル制御部と、 前記I/Oプロセッサから送信される前記I/O要求に応じて前記記憶デバイスに対するデータ入出力を実行するディスク制御部と、 を含んで構成され、 前記記憶デバイスにより提供される記憶領域をその記憶領域に論理的に設定される記憶領域である論理ボリュームを単位として管理する記憶デバイス制御装置の制御方法であって、 前記チャネル制御部が、前記情報処理装置から送信される、前記チャネル制御部に対する前記論理ボリュームの割り当てが指定されたデータを受信するステップと、 前記チャネル制御部が、受信した前記割り当て (storage client) を記憶するステップと、 を備えることを特徴とする記憶デバイス制御装置の制御方法。

JP2004227098A
CLAIM 16
請求項14または15に記載の記憶デバイス制御装置の制御方法において、 前記チャネル制御部はWebサーバ (storage client) としての機能を備え、 前記プログラムまたは前記不揮発性メモリの内容を更新するためのデータは、前記ネットワークを通じて前記情報処理装置に提供されるWebページの機能を利用して前記チャネル制御部に送信されることを特徴とする記憶デバイス制御装置の制御方法。

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client (前記割り当て, サーバ) ;

a storage processor (メモリ) coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
JP2004227098A
CLAIM 1
情報処理装置から送信されるファイル単位でのデータ入出力要求をネットワークを通じて受信するファイルアクセス処理部と、記憶デバイスに対する前記データ入出力要求に対応するI/O要求を出力するI/Oプロセッサとが形成された回路基板を有する複数のチャネル制御部と、 前記I/Oプロセッサから送信される前記I/O要求に応じて前記記憶デバイスに対するデータ入出力を実行するディスク制御部と、 を含んで構成され、 前記記憶デバイスにより提供される記憶領域をその記憶領域に論理的に設定される記憶領域である論理ボリュームを単位として管理する記憶デバイス制御装置の制御方法であって、 前記チャネル制御部が、前記情報処理装置から送信される、前記チャネル制御部に対する前記論理ボリュームの割り当てが指定されたデータを受信するステップと、 前記チャネル制御部が、受信した前記割り当て (storage client) を記憶するステップと、 を備えることを特徴とする記憶デバイス制御装置の制御方法。

JP2004227098A
CLAIM 15
情報処理装置から送信されるファイル単位でのデータ入出力要求をネットワークを通じて受信するファイルアクセス処理部と、記憶デバイスに対する前記データ入出力要求に対応するI/O要求を出力するI/Oプロセッサとが形成された回路基板を有する複数のチャネル制御部と、 前記I/Oプロセッサから送信される前記I/O要求に応じて前記記憶デバイスに対するデータ入出力を実行するディスク制御部と、 前記チャネル制御部または前記ディスク制御部の少なくともいずれか一方に備えられた不揮発性メモリ (storage processor) と、 を含んで構成される記憶デバイス制御装置における、前記ファームウェアを更新するための記憶デバイス制御装置の制御方法であって、 前記チャネル制御部が、前記情報処理装置から送信される前記不揮発性メモリの内容を更新するためのデータを受信するステップと、 前記記憶デバイス制御装置が、前記不揮発性メモリの内容を更新するためのデータにより前記不揮発性メモリの内容を更新するステップと、 を備えることを特徴と記憶デバイス制御装置の制御方法。

JP2004227098A
CLAIM 16
請求項14または15に記載の記憶デバイス制御装置の制御方法において、 前記チャネル制御部はWebサーバ (storage client) としての機能を備え、 前記プログラムまたは前記不揮発性メモリの内容を更新するためのデータは、前記ネットワークを通じて前記情報処理装置に提供されるWebページの機能を利用して前記チャネル制御部に送信されることを特徴とする記憶デバイス制御装置の制御方法。

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (メモリ) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
JP2004227098A
CLAIM 15
情報処理装置から送信されるファイル単位でのデータ入出力要求をネットワークを通じて受信するファイルアクセス処理部と、記憶デバイスに対する前記データ入出力要求に対応するI/O要求を出力するI/Oプロセッサとが形成された回路基板を有する複数のチャネル制御部と、 前記I/Oプロセッサから送信される前記I/O要求に応じて前記記憶デバイスに対するデータ入出力を実行するディスク制御部と、 前記チャネル制御部または前記ディスク制御部の少なくともいずれか一方に備えられた不揮発性メモリ (storage processor) と、 を含んで構成される記憶デバイス制御装置における、前記ファームウェアを更新するための記憶デバイス制御装置の制御方法であって、 前記チャネル制御部が、前記情報処理装置から送信される前記不揮発性メモリの内容を更新するためのデータを受信するステップと、 前記記憶デバイス制御装置が、前記不揮発性メモリの内容を更新するためのデータにより前記不揮発性メモリの内容を更新するステップと、 を備えることを特徴と記憶デバイス制御装置の制御方法。

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor (メモリ) returns a predetermined data string .
JP2004227098A
CLAIM 15
情報処理装置から送信されるファイル単位でのデータ入出力要求をネットワークを通じて受信するファイルアクセス処理部と、記憶デバイスに対する前記データ入出力要求に対応するI/O要求を出力するI/Oプロセッサとが形成された回路基板を有する複数のチャネル制御部と、 前記I/Oプロセッサから送信される前記I/O要求に応じて前記記憶デバイスに対するデータ入出力を実行するディスク制御部と、 前記チャネル制御部または前記ディスク制御部の少なくともいずれか一方に備えられた不揮発性メモリ (storage processor) と、 を含んで構成される記憶デバイス制御装置における、前記ファームウェアを更新するための記憶デバイス制御装置の制御方法であって、 前記チャネル制御部が、前記情報処理装置から送信される前記不揮発性メモリの内容を更新するためのデータを受信するステップと、 前記記憶デバイス制御装置が、前記不揮発性メモリの内容を更新するためのデータにより前記不揮発性メモリの内容を更新するステップと、 を備えることを特徴と記憶デバイス制御装置の制御方法。




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US7005350B2

Filed: 2002-12-31     Issued: 2006-02-28

Method for fabricating programmable memory array structures incorporating series-connected transistor strings

(Original Assignee) SanDisk 3D LLC     (Current Assignee) SanDisk Technologies LLC

Andrew J. Walker, En-Hsing Chen, Sucheta Nallamothu, Roy E. Scheuerlein, Alper Ilkbahar, Luca Fasoli, Igor Koutnetsov, Christopher Petti
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system , including storing data (said memory) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data (said memory) pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US7005350B2
CLAIM 23
. The integrated circuit as recited in claim 17 wherein , for each memory level of said integrated circuit , a respective memory cell is defined at least in part by a respective one of plurality of gate stripes and a respective one of the plurality of channel stripes , wherein said memory (store data, storing data) cells are configured in series-connected NAND strings having at least three such memory cells in series between contacts to such NAND strings .

US9632727B2
CLAIM 2
. The apparatus of claim 1 , wherein the indexer assigns logical addresses to physical addresses by use of index entries , and wherein the indexer removes an index entry (memory array) corresponding to the identified logical address in response to the message .
US7005350B2
CLAIM 1
. A method for manufacturing an integrated circuit memory array (index entry) , said method comprising the steps of : depositing a semiconductor layer on a dielectric layer above a substrate ;
forming a plurality of channel stripes in the semiconductor layer , said channel stripes running in a first direction ;
forming a charge storage dielectric layer on the channel stripes ;
forming a plurality of gate stripes on the charge storage dielectric layer , said gate stripes running in a second direction different than the first direction ;
forming heavily-doped regions in the channel stripes between the gate stripes , wherein adjacent heavily-doped regions do not make contact beneath the gate strips ;
and forming an interlevel dielectric layer above the gate stripes .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface (one channel) .
US7005350B2
CLAIM 3
. The method as recited in claim 2 wherein the step for forming plugged vias comprises : forming openings in the interlevel dielectric layer to expose a portion of at least one channel (Fibre Channel interface) stripe or gate stripe therebelow ;
filling the openings with a conductive metal ;
and planarizing the resultant structure to form plugged vias having a top surface in common with a top surface of the interlevel dielectric layer .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (said memory) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
US7005350B2
CLAIM 23
. The integrated circuit as recited in claim 17 wherein , for each memory level of said integrated circuit , a respective memory cell is defined at least in part by a respective one of plurality of gate stripes and a respective one of the plurality of channel stripes , wherein said memory (store data, storing data) cells are configured in series-connected NAND strings having at least three such memory cells in series between contacts to such NAND strings .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
JP2004086295A

Filed: 2002-08-23     Issued: 2004-03-18

Nand型フラッシュメモリディスク装置及び論理アドレス検出の方法

(Original Assignee) Megawin Technology Co Ltd; 笙泉科技股▲ふん▼有限公司     

Jin-Shian Lin, 林 晉賢
US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer (SRAM) System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
JP2004086295A
CLAIM 3
請求項1に記載のNAND型フラッシュメモリディスク装置において、RAMがSRAM (Small Computer) とされたことを特徴とする、NAND型フラッシュメモリディスク装置。

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor (メモリ) coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
JP2004086295A
CLAIM 1
NAND型フラッシュメモリ (storage processor) ディスク装置において、該装置はシステム起動時にまず物理アドレスとそれの対応する論理アドレスの関係を直接複製して部分物理/論理アドレスマッピング表を構築し、このフラッシュメモリディスク装置を利用してサーチ待機論理アドレスがサーチされ、このフラッシュメモリディスク装置が、 続けてアドレス信号を発送する計数器と、 内部に該部分物理/論理アドレスマッピング表を記録し、該アドレス信号に基づき、該部分物理/論理アドレスマッピング表中より対応する論理アドレス信号を得て、並びにそれを伝送する、RAMと、 該論理アドレス信号と、サーチ待機論理アドレスを受け取りこれを比較した後、この二つの論理アドレスが同じであれば、即ち、該サーチ待機論理アドレスとその対応する物理位置を得て、計数器の運転を停止させる、比較器と、 を具えたことを特徴とする、NAND型フラッシュメモリディスク装置。

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (メモリ) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
JP2004086295A
CLAIM 1
NAND型フラッシュメモリ (storage processor) ディスク装置において、該装置はシステム起動時にまず物理アドレスとそれの対応する論理アドレスの関係を直接複製して部分物理/論理アドレスマッピング表を構築し、このフラッシュメモリディスク装置を利用してサーチ待機論理アドレスがサーチされ、このフラッシュメモリディスク装置が、 続けてアドレス信号を発送する計数器と、 内部に該部分物理/論理アドレスマッピング表を記録し、該アドレス信号に基づき、該部分物理/論理アドレスマッピング表中より対応する論理アドレス信号を得て、並びにそれを伝送する、RAMと、 該論理アドレス信号と、サーチ待機論理アドレスを受け取りこれを比較した後、この二つの論理アドレスが同じであれば、即ち、該サーチ待機論理アドレスとその対応する物理位置を得て、計数器の運転を停止させる、比較器と、 を具えたことを特徴とする、NAND型フラッシュメモリディスク装置。

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor (メモリ) returns a predetermined data string .
JP2004086295A
CLAIM 1
NAND型フラッシュメモリ (storage processor) ディスク装置において、該装置はシステム起動時にまず物理アドレスとそれの対応する論理アドレスの関係を直接複製して部分物理/論理アドレスマッピング表を構築し、このフラッシュメモリディスク装置を利用してサーチ待機論理アドレスがサーチされ、このフラッシュメモリディスク装置が、 続けてアドレス信号を発送する計数器と、 内部に該部分物理/論理アドレスマッピング表を記録し、該アドレス信号に基づき、該部分物理/論理アドレスマッピング表中より対応する論理アドレス信号を得て、並びにそれを伝送する、RAMと、 該論理アドレス信号と、サーチ待機論理アドレスを受け取りこれを比較した後、この二つの論理アドレスが同じであれば、即ち、該サーチ待機論理アドレスとその対応する物理位置を得て、計数器の運転を停止させる、比較器と、 を具えたことを特徴とする、NAND型フラッシュメモリディスク装置。




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
JP2004030438A

Filed: 2002-06-27     Issued: 2004-01-29

マイクロコンピュータ

(Original Assignee) Renesas Technology Corp; 株式会社ルネサステクノロジ     

Hiroyuki Kimura, Toshihiro Sezaki, Kunio Tani, Satoru Tashiro, Makoto Yamamoto, 山本 誠, 木村 宏行, 瀬崎 利博, 田代 哲, 谷 国雄
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state (ロック) storage medium in response to requests from a computer system , including storing data (タイミング) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data (周辺機器) pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
JP2004030438A
CLAIM 1
少なくともCPU、このCPUにより実行可能である自動消去および自動書き込みシーケンスを備え、外部からの制御により上記自動消去および自動書き込みの中断・再開が可能な不揮発性メモリおよび周辺機器 (store data) を備えたマイクロコンピュータにおいて、 上記周辺機器または外部からの割り込み要求により、上記不揮発性メモリの自動消去または自動書き込み処理が一時中断し、当該メモリ内のデータを上記CPUが読み出し可能となることを特徴とするマイクロコンピュータ。

JP2004030438A
CLAIM 4
不揮発性メモリは、不揮発性トランジスタからなる複数のメモリセルが行列状に配置されたメモリアレイを有するメモリブロック (solid state, state storage medium, solid state storage medium) を、複数個集めてブロックメモリアレイを構成するとともに、 書き込み及び消去処理を処理シーケンス中の各フェーズ後に中断する割り込み手段と、 書き込み及び消去処理を中断する第一の割り込みでは、処理シーケンス中の第一の割り込みの入ったタイミング (storing data) に応じたフェーズで処理を中断し、 書き込み及び消去処理を中断する第二の割り込みでは、処理シーケンス中の特定のフェーズで処理を中断する手段とを備え、 前記処理の中断中は、前記不揮発性メモリの内容が読み出せることを特徴とする請求項1記載のマイクロコンピュータ。

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (タイミング) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
JP2004030438A
CLAIM 4
不揮発性メモリは、不揮発性トランジスタからなる複数のメモリセルが行列状に配置されたメモリアレイを有するメモリブロックを、複数個集めてブロックメモリアレイを構成するとともに、 書き込み及び消去処理を処理シーケンス中の各フェーズ後に中断する割り込み手段と、 書き込み及び消去処理を中断する第一の割り込みでは、処理シーケンス中の第一の割り込みの入ったタイミング (storing data) に応じたフェーズで処理を中断し、 書き込み及び消去処理を中断する第二の割り込みでは、処理シーケンス中の特定のフェーズで処理を中断する手段とを備え、 前記処理の中断中は、前記不揮発性メモリの内容が読み出せることを特徴とする請求項1記載のマイクロコンピュータ。




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
JP2004021811A

Filed: 2002-06-19     Issued: 2004-01-22

不揮発メモリを使用したディスク制御装置

(Original Assignee) Hitachi Ltd; 株式会社日立製作所     

Tetsuya Abe, 阿部 哲也
US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface (メモリモジュール, ホスト) , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
JP2004021811A
CLAIM 1
ホスト (PCI Express bus interface) インタフェース部と、ディスクインターフェース部と、ホストとディスクとでやり取りされるデータを一時的に保持するキャッシュ部と、不揮発メモリとを備える不揮発メモリを使用したディスク制御装置において、 前記不揮発メモリ部は、 実データ格納デバイス、予備用の格納デバイス、実データのパリティ冗長データが格納されるパリティ冗長データ用デバイスの三種の不揮発メモリデバイスからなるメモリモジュール (PCI Express bus interface) を含み、 しかも、これらの不揮発メモリデバイスは、並列に実装して構成され、 それぞれの不揮発メモリデバイスには、最小ブロック単位ごとにデータを保持し、 前記最小ブロック単位は、実データと、論理管理IDと、そのブロックの良、不良を判定するための保護コードとを含むことを特徴とする不揮発メモリを使用したディスク制御装置。

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor returns a predetermined data string (コード) .
JP2004021811A
CLAIM 1
ホストインタフェース部と、ディスクインターフェース部と、ホストとディスクとでやり取りされるデータを一時的に保持するキャッシュ部と、不揮発メモリとを備える不揮発メモリを使用したディスク制御装置において、 前記不揮発メモリ部は、 実データ格納デバイス、予備用の格納デバイス、実データのパリティ冗長データが格納されるパリティ冗長データ用デバイスの三種の不揮発メモリデバイスからなるメモリモジュールを含み、 しかも、これらの不揮発メモリデバイスは、並列に実装して構成され、 それぞれの不揮発メモリデバイスには、最小ブロック単位ごとにデータを保持し、 前記最小ブロック単位は、実データと、論理管理IDと、そのブロックの良、不良を判定するための保護コード (data string) とを含むことを特徴とする不揮発メモリを使用したディスク制御装置。

US9632727B2
CLAIM 16
. The system of claim 15 , wherein data bits of the predetermined data string (コード) have a uniform logic (論理アドレス) level .
JP2004021811A
CLAIM 1
ホストインタフェース部と、ディスクインターフェース部と、ホストとディスクとでやり取りされるデータを一時的に保持するキャッシュ部と、不揮発メモリとを備える不揮発メモリを使用したディスク制御装置において、 前記不揮発メモリ部は、 実データ格納デバイス、予備用の格納デバイス、実データのパリティ冗長データが格納されるパリティ冗長データ用デバイスの三種の不揮発メモリデバイスからなるメモリモジュールを含み、 しかも、これらの不揮発メモリデバイスは、並列に実装して構成され、 それぞれの不揮発メモリデバイスには、最小ブロック単位ごとにデータを保持し、 前記最小ブロック単位は、実データと、論理管理IDと、そのブロックの良、不良を判定するための保護コード (data string) とを含むことを特徴とする不揮発メモリを使用したディスク制御装置。

JP2004021811A
CLAIM 5
前記不揮発メモリ部は、この不揮発メモリ部にアクセスする論理アドレス (uniform logic) を、内部の物理アドレスに変換する機構を有することを特徴とする請求項1ないし請求項4記載のいずれかの不揮発メモリを使用したディスク制御装置。




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US20030021417A1

Filed: 2002-05-15     Issued: 2003-01-30

Hidden link dynamic key manager for use in computer systems with database structure for storage of encrypted data and method for storage and retrieval of encrypted data

(Original Assignee) ERUCES Inc     (Current Assignee) Central Valley Administrators ; Farrukh Abdallah Dr ; ERUCES Inc

Ognjen Vasic, Suhail Ansari, Ping Gan, Jinhui Hu, Bassam Khulusi, Adam Madoukh, Alexander Tyshlek
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data (software component) pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system (secure communication) , the message indicating that the identified logical address is erased .
US20030021417A1
CLAIM 14
. The distributed network according to claim 12 , wherein secure communication (host operating system) between the remote cryptographic agent and the remote cryptographic engine is secured using a shared operational key .

US20030021417A1
CLAIM 16
. A computer readable data transmission medium containing a data structure for facilitating the secure exchange and use of encrypted data , the data structure comprising : at least one data entity encrypted by at least one encryption key ;
at least one key association that associates the data entity with the encryption key ;
and instructions operable to receive commands from an application software component (store data) to generate a new encryption key , to store the data entity in encrypted form , and to transmit an unencrypted form of the data entity to the application software component , the commands proxied through a trusted cryptographic agent .

US9632727B2
CLAIM 3
. The apparatus of claim 1 , wherein the indexer assigns logical addresses to physical addresses by use of index metadata (encrypted data) maintained in a memory of the storage controller .
US20030021417A1
CLAIM 16
. A computer readable data transmission medium containing a data structure for facilitating the secure exchange and use of encrypted data (index metadata) , the data structure comprising : at least one data entity encrypted by at least one encryption key ;
at least one key association that associates the data entity with the encryption key ;
and instructions operable to receive commands from an application software component to generate a new encryption key , to store the data entity in encrypted form , and to transmit an unencrypted form of the data entity to the application software component , the commands proxied through a trusted cryptographic agent .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface (access control list) , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer (readable data) System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
US20030021417A1
CLAIM 3
. The computer system according to claim 1 further comprising : an authorization module coupled with at least one access control list (InfiniBand interface) , wherein access to operations based on the session key is provided based on the access control list .

US20030021417A1
CLAIM 16
. A computer readable data (Small Computer, Small Computer System Interface) transmission medium containing a data structure for facilitating the secure exchange and use of encrypted data , the data structure comprising : at least one data entity encrypted by at least one encryption key ;
at least one key association that associates the data entity with the encryption key ;
and instructions operable to receive commands from an application software component to generate a new encryption key , to store the data entity in encrypted form , and to transmit an unencrypted form of the data entity to the application software component , the commands proxied through a trusted cryptographic agent .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor (data store) coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US20030021417A1
CLAIM 1
. A computer system containing cryptographic keys and cryptographic key identifiers , the computer system comprising : a repository cryptographic engine operable to communicate securely with a remote cryptographic engine , the repository cryptographic engine associated with a user data store (storage processor) having at least one hidden link including a session key identifier encrypted with at least one protection key , the hidden link associated with at least one remote data entity ;
at least one session key encrypted with at least one session-key-protection key , the session key operable to be used in connection with cryptographic operations on the remote data entity ;
and a repository key exchange module operable to exchange the session key with a remote key exchange module .

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (data store) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
US20030021417A1
CLAIM 1
. A computer system containing cryptographic keys and cryptographic key identifiers , the computer system comprising : a repository cryptographic engine operable to communicate securely with a remote cryptographic engine , the repository cryptographic engine associated with a user data store (storage processor) having at least one hidden link including a session key identifier encrypted with at least one protection key , the hidden link associated with at least one remote data entity ;
at least one session key encrypted with at least one session-key-protection key , the session key operable to be used in connection with cryptographic operations on the remote data entity ;
and a repository key exchange module operable to exchange the session key with a remote key exchange module .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request (n information) specifying one or more logical addresses included in the empty-block directive command , the storage processor (data store) returns a predetermined data string .
US20030021417A1
CLAIM 1
. A computer system containing cryptographic keys and cryptographic key identifiers , the computer system comprising : a repository cryptographic engine operable to communicate securely with a remote cryptographic engine , the repository cryptographic engine associated with a user data store (storage processor) having at least one hidden link including a session key identifier encrypted with at least one protection key , the hidden link associated with at least one remote data entity ;
at least one session key encrypted with at least one session-key-protection key , the session key operable to be used in connection with cryptographic operations on the remote data entity ;
and a repository key exchange module operable to exchange the session key with a remote key exchange module .

US20030021417A1
CLAIM 19
. A cryptographic method for facilitating the secure processing of information using trusted components , the method comprising : receiving electronic code associated with a software component ;
receiving a component identifier associated with the software component ;
calculating a fingerprint associated with the electronic code ;
reading a registration key from a registration key source ;
executing a registration challenge response protocol using the registration key , whereby authority to register the software component is demonstrated ;
storing registration information (read request) and the fingerprint in connection with the component identifier of the software component ;
receiving request from the software component at a cryptographic agent to perform an authorized cryptographic operation ;
and transmitting a request for challenge to a cryptography server regarding the software component ;
providing a challenge to agent ;
receiving a response to the challenge ;
verifying the response to the challenge including calculating the fingerprint and verifying an operational key .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
JP2003281071A

Filed: 2002-03-20     Issued: 2003-10-03

データ転送制御装置、電子機器及びデータ転送制御方法

(Original Assignee) Seiko Epson Corp; セイコーエプソン株式会社     

伸之 ▲斎▼藤, Yoshimi Oka, Nobuyuki Saito, 義美 岡
US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor coupled to the storage interface ;

a flash memory device (アドレス) coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
JP2003281071A
CLAIM 11
【請求項11】 請求項1乃至10のいずれかにおい て、 前記第2のメモリが、 連続したアドレス (flash memory device) のデータを所与のクロックに同期して 入出力できる同期型メモリであることを特徴とするデー タ転送制御装置。

US9632727B2
CLAIM 13
. The system of claim 12 , wherein the logical-to-physical translation layer is stored in the flash memory device (アドレス) .
JP2003281071A
CLAIM 11
【請求項11】 請求項1乃至10のいずれかにおい て、 前記第2のメモリが、 連続したアドレス (flash memory device) のデータを所与のクロックに同期して 入出力できる同期型メモリであることを特徴とするデー タ転送制御装置。

US9632727B2
CLAIM 16
. The system of claim 15 , wherein data bits (クロック) of the predetermined data string have a uniform logic level .
JP2003281071A
CLAIM 11
【請求項11】 請求項1乃至10のいずれかにおい て、 前記第2のメモリが、 連続したアドレスのデータを所与のクロック (data bits) に同期して 入出力できる同期型メモリであることを特徴とするデー タ転送制御装置。




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US6871257B2

Filed: 2002-02-22     Issued: 2005-03-22

Pipelined parallel programming operation in a non-volatile memory system

(Original Assignee) SanDisk Corp     (Current Assignee) SanDisk Technologies LLC

Kevin M. Conley, Yoram Cedar
US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor (data store) coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US6871257B2
CLAIM 4
. The memory system circuit of claim 3 , wherein each of the data storage sections further comprises an array of non-volatile storage units into which data store (storage processor) d in the data register is programmed .

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (data store) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
US6871257B2
CLAIM 4
. The memory system circuit of claim 3 , wherein each of the data storage sections further comprises an array of non-volatile storage units into which data store (storage processor) d in the data register is programmed .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor (data store) returns a predetermined data string .
US6871257B2
CLAIM 4
. The memory system circuit of claim 3 , wherein each of the data storage sections further comprises an array of non-volatile storage units into which data store (storage processor) d in the data register is programmed .

US9632727B2
CLAIM 16
. The system of claim 15 , wherein data bits of the predetermined data string have a uniform logic (non-volatile storage) level .
US6871257B2
CLAIM 4
. The memory system circuit of claim 3 , wherein each of the data storage sections further comprises an array of non-volatile storage (uniform logic) units into which data stored in the data register is programmed .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US6748504B2

Filed: 2002-02-15     Issued: 2004-06-08

Deferred copy-on-write of a snapshot

(Original Assignee) International Business Machines Corp     (Current Assignee) International Business Machines Corp

Wayne A. Sawdon, Frank B. Schmuck
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system , including storing data (computer readable medium) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US6748504B2
CLAIM 15
. A computer readable medium (storing data) including computer instructions for deferring copy-on-write , the computer instructions comprising instructions for : generating a snapshot including a source file ;
referencing in the snapshot , upon modification of a first data block associated with the source file , the first data block ;
allocating a second data block for the source file ;
assigning a value to a first variable associated with the source file , wherein the value indicates the lack of a complete source file data block ;
and assigning a value to a second variable associated with the source file , wherein the value indicates a valid portion of the second data block .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (computer readable medium) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
US6748504B2
CLAIM 15
. A computer readable medium (storing data) including computer instructions for deferring copy-on-write , the computer instructions comprising instructions for : generating a snapshot including a source file ;
referencing in the snapshot , upon modification of a first data block associated with the source file , the first data block ;
allocating a second data block for the source file ;
assigning a value to a first variable associated with the source file , wherein the value indicates the lack of a complete source file data block ;
and assigning a value to a second variable associated with the source file , wherein the value indicates a valid portion of the second data block .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request (corresponding data) specifying one or more logical addresses included in the empty-block directive command , the storage processor returns a predetermined data string .
US6748504B2
CLAIM 25
. A method for deferring copy-on-write , comprising : generating a snapshot including a source file ;
referencing in the snapshot , upon modification of at least one of a first plurality of data blocks associated with the source file , the at least one data block being modified ;
allocating a data block for the source file ;
assigning a value to a first variable associated with the source file , wherein the value indicates incomplete data blocks associated with the source file ;
and assigning a value to each of a plurality of variables , wherein each of the plurality of variables is associated with one of the plurality of data blocks associated with the source file and wherein the value of each of the plurality of variables indicates a valid portion of the corresponding data (read request) block .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US6525953B1

Filed: 2001-08-13     Issued: 2003-02-25

Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication

(Original Assignee) SanDisk 3D LLC     (Current Assignee) SanDisk Technologies LLC

Mark G. Johnson
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system , including storing data (said memory) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data (said memory) pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system (one dimension) , the message indicating that the identified logical address is erased .
US6525953B1
CLAIM 1
. A memory cell comprising : a first conductor ;
a second conductor ;
a pillar having a generally rectangular first end surface comprising first spaced-apart edges and a second , opposite end surface comprising second spaced-apart edges ;
the first spaced-apart edges at the first end surface being aligned with the first conductor with the first end surface being in continuous contact with the first conductor , the second spaced-apart edges at the second end surface being aligned with the second conductor with the second end surface being in continuous contact with the second conductor ;
said memory (store data, storing data) cell comprising an anti-fuse layer and first and second diode components separated by the anti-fuse layer , said diode components forming a diode only after the anti-fuse layer is disrupted , said anti-fuse layer included in said pillar .

US6525953B1
CLAIM 6
. The memory cell defined by claim 1 wherein the first conductor has a width approximately equal to one dimension (host operating system, data string) of the rectangular cross-section .

US9632727B2
CLAIM 2
. The apparatus of claim 1 , wherein the indexer assigns logical addresses to physical addresses by use of index entries , and wherein the indexer removes an index entry (memory array, d line) corresponding to the identified logical address in response to the message .
US6525953B1
CLAIM 21
. The cell defined by claim 8 wherein one of the terminals of the cell is connected to a word line (index entry) .

US6525953B1
CLAIM 23
. A memory array (index entry) comprising : a first plurality of spaced-apart , parallel , substantially coplanar conductors ;
a second plurality of spaced-apart , parallel , substantially coplanar conductors disposed generally vertically above and spaced-apart from the first conductors , said first and second conductors being generally orthogonal to one another ;
and a plurality of first pillars , each first pillar directly disposed between one of the first and one of the second conductors and located where a vertical projection of the first conductors intersects the second conductors , a third plurality of spaced-apart , parallel , substantially coplanar conductors disposed generally vertically above and spaced-apart from the second conductors , the third conductors running in the same direction as the first conductors ;
a plurality of second pillars , each second pillar directly disposed between one of the second conductors and one of the third conductors and located where a vertical projection of the second conductors intersects the third conductors , each of said pillars and associated conductors forming a respective memory cell , each memory cell comprising a respective anti-fuse layer and respective first and second diode components separated by the respective anti-fuse layer , each pair of said diode components forming a respective diode only after the respective anti-fuse layer is disrupted , each pillar comprising the respective anti-fuse layer .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface (third plurality) .
US6525953B1
CLAIM 23
. A memory array comprising : a first plurality of spaced-apart , parallel , substantially coplanar conductors ;
a second plurality of spaced-apart , parallel , substantially coplanar conductors disposed generally vertically above and spaced-apart from the first conductors , said first and second conductors being generally orthogonal to one another ;
and a plurality of first pillars , each first pillar directly disposed between one of the first and one of the second conductors and located where a vertical projection of the first conductors intersects the second conductors , a third plurality (Fibre Channel interface) of spaced-apart , parallel , substantially coplanar conductors disposed generally vertically above and spaced-apart from the second conductors , the third conductors running in the same direction as the first conductors ;
a plurality of second pillars , each second pillar directly disposed between one of the second conductors and one of the third conductors and located where a vertical projection of the second conductors intersects the third conductors , each of said pillars and associated conductors forming a respective memory cell , each memory cell comprising a respective anti-fuse layer and respective first and second diode components separated by the respective anti-fuse layer , each pair of said diode components forming a respective diode only after the respective anti-fuse layer is disrupted , each pillar comprising the respective anti-fuse layer .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (said memory) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
US6525953B1
CLAIM 1
. A memory cell comprising : a first conductor ;
a second conductor ;
a pillar having a generally rectangular first end surface comprising first spaced-apart edges and a second , opposite end surface comprising second spaced-apart edges ;
the first spaced-apart edges at the first end surface being aligned with the first conductor with the first end surface being in continuous contact with the first conductor , the second spaced-apart edges at the second end surface being aligned with the second conductor with the second end surface being in continuous contact with the second conductor ;
said memory (store data, storing data) cell comprising an anti-fuse layer and first and second diode components separated by the anti-fuse layer , said diode components forming a diode only after the anti-fuse layer is disrupted , said anti-fuse layer included in said pillar .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor returns a predetermined data string (one dimension) .
US6525953B1
CLAIM 6
. The memory cell defined by claim 1 wherein the first conductor has a width approximately equal to one dimension (host operating system, data string) of the rectangular cross-section .

US9632727B2
CLAIM 16
. The system of claim 15 , wherein data bits of the predetermined data string (one dimension) have a uniform logic level .
US6525953B1
CLAIM 6
. The memory cell defined by claim 1 wherein the first conductor has a width approximately equal to one dimension (host operating system, data string) of the rectangular cross-section .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
JP2003006041A

Filed: 2001-06-20     Issued: 2003-01-10

半導体装置

(Original Assignee) Hitachi Ltd; Hitachi Ulsi Systems Co Ltd; 株式会社日立製作所; 株式会社日立超エル・エス・アイ・システムズ     

Kazushige Ayukawa, Koichi Hoshi, Tetsuya Iwamura, Seishi Miura, Yoshikazu Saito, 誓士 三浦, 哲哉 岩村, 良和 斎藤, 浩一 星, 一重 鮎川
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller (制御信号) configured to implement storage operations on the solid state storage medium in response to requests from a computer system , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
JP2003006041A
CLAIM 12
【請求項12】請求項11において、前記半導体装置 は、前記第1及び第2メモリに対するアクセス制御する ための信号が供給される複数の第1制御信号 (state storage controller, storage controller) 端子と、前 記不揮発性メモリのアクセス制御のための信号が供給さ れる複数の第2制御信号端子と、前記第1から第4半導 体チップに対する複数の電源端子とを更に有する半導体 装置。

US9632727B2
CLAIM 3
. The apparatus of claim 1 , wherein the indexer assigns logical addresses to physical addresses by use of index metadata maintained in a memory of the storage controller (制御信号) .
JP2003006041A
CLAIM 12
【請求項12】請求項11において、前記半導体装置 は、前記第1及び第2メモリに対するアクセス制御する ための信号が供給される複数の第1制御信号 (state storage controller, storage controller) 端子と、前 記不揮発性メモリのアクセス制御のための信号が供給さ れる複数の第2制御信号端子と、前記第1から第4半導 体チップに対する複数の電源端子とを更に有する半導体 装置。

US9632727B2
CLAIM 4
. The apparatus of claim 1 , wherein the indexer comprises firmware of the solid-state storage controller (制御信号) .
JP2003006041A
CLAIM 12
【請求項12】請求項11において、前記半導体装置 は、前記第1及び第2メモリに対するアクセス制御する ための信号が供給される複数の第1制御信号 (state storage controller, storage controller) 端子と、前 記不揮発性メモリのアクセス制御のための信号が供給さ れる複数の第2制御信号端子と、前記第1から第4半導 体チップに対する複数の電源端子とを更に有する半導体 装置。

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller (制御信号) comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer (SRAM) System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
JP2003006041A
CLAIM 7
【請求項7】請求項1において、前記第1及び第2チッ プのそれぞれはDRAMメモリチップであり、前記第3 チップはSRAM (Small Computer) メモリを更に含み、 前記第3チップの前記複数の第5ノードに供給される前 記外部アクセス信号はSRAMインターフェースである 半導体装置。

JP2003006041A
CLAIM 12
【請求項12】請求項11において、前記半導体装置 は、前記第1及び第2メモリに対するアクセス制御する ための信号が供給される複数の第1制御信号 (state storage controller, storage controller) 端子と、前 記不揮発性メモリのアクセス制御のための信号が供給さ れる複数の第2制御信号端子と、前記第1から第4半導 体チップに対する複数の電源端子とを更に有する半導体 装置。

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor (外部アクセス) coupled to the storage interface ;

a flash memory device (アドレス) coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
JP2003006041A
CLAIM 2
【請求項2】請求項1において、 前記メモリコントローラは、前記第1期間において、前 記外部アクセス (storage processor) 信号に対応して前記第1メモリに対する 読み出しまたは書込コマンド信号を前記第1アクセス信 号として出力可能とされるともに、前記第2メモリに対 するリフレッシュを行うためのリフレッシュコマンド信 号を前記第2アクセス信号として出力可能とされ、 前記メモリコントローラは、前記第2期間において、前 記外部アクセス信号に対応して前記第2メモリに対する 読み出しまたは書込コマンド信号を前記第2アクセス信 号として出力可能とされるともに、前記第1メモリに対 するリフレッシュを行うためのリフレッシュコマンド信 号を前記第1アクセス信号として出力可能とされる半導 体装置。

JP2003006041A
CLAIM 4
【請求項4】請求項1において、前記第1期間におい て、前記メモリコントローラは、前記第1メモリにデー タ書込が起きた場合には、当該書込データは所定の手順 で前記第2メモリの対応するアドレス (flash memory device) の前記第2メモリ セルに転写される半導体装置。

US9632727B2
CLAIM 13
. The system of claim 12 , wherein the logical-to-physical translation layer is stored in the flash memory device (アドレス) .
JP2003006041A
CLAIM 4
【請求項4】請求項1において、前記第1期間におい て、前記メモリコントローラは、前記第1メモリにデー タ書込が起きた場合には、当該書込データは所定の手順 で前記第2メモリの対応するアドレス (flash memory device) の前記第2メモリ セルに転写される半導体装置。

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (外部アクセス) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
JP2003006041A
CLAIM 2
【請求項2】請求項1において、 前記メモリコントローラは、前記第1期間において、前 記外部アクセス (storage processor) 信号に対応して前記第1メモリに対する 読み出しまたは書込コマンド信号を前記第1アクセス信 号として出力可能とされるともに、前記第2メモリに対 するリフレッシュを行うためのリフレッシュコマンド信 号を前記第2アクセス信号として出力可能とされ、 前記メモリコントローラは、前記第2期間において、前 記外部アクセス信号に対応して前記第2メモリに対する 読み出しまたは書込コマンド信号を前記第2アクセス信 号として出力可能とされるともに、前記第1メモリに対 するリフレッシュを行うためのリフレッシュコマンド信 号を前記第1アクセス信号として出力可能とされる半導 体装置。

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request (メモリアクセス) specifying one or more logical addresses included in the empty-block directive command , the storage processor (外部アクセス) returns a predetermined data string .
JP2003006041A
CLAIM 1
【請求項1】第1キャパシタと第1MISFETをそれ ぞれに持つ複数の第1メモリセルを含む第1メモリと、 前記第1メモリに対する第1アクセス信号の入力のため の複数の第1ノードとを含む第1チップと、 第2キャパシタと第2MISFETをそれぞれに持つ複 数の第2メモリセルを含む第2メモリと、前記第2メモ リに対する第2アクセス信号の入力のための複数の第2 ノードとを含む第2チップと、 前記複数の第1ノードに結合され前記第1チップに対す る第1アクセス信号を供給する複数の第3ノードと、前 記複数の第2ノードに結合され前記第2チップに対する 第2アクセス信号を供給する複数の第4ノードと、外部 アクセス信号を受けるための複数の第5ノードとを有す るメモリコントローラを含む第3チップとを備え、 前記メモリコントローラは、第1期間において前記外部 アクセス信号を受けた場合には前記第1メモリに対して アクセスを行うよう第1アクセス信号を出力し、第2期 間において前記外部メモリアクセス (read request, read request specifying one) 信号を受けた場合に は前記第2メモリに対してアクセスを行うよう第2アク セス信号を出力する半導体装置。

JP2003006041A
CLAIM 2
【請求項2】請求項1において、 前記メモリコントローラは、前記第1期間において、前 記外部アクセス (storage processor) 信号に対応して前記第1メモリに対する 読み出しまたは書込コマンド信号を前記第1アクセス信 号として出力可能とされるともに、前記第2メモリに対 するリフレッシュを行うためのリフレッシュコマンド信 号を前記第2アクセス信号として出力可能とされ、 前記メモリコントローラは、前記第2期間において、前 記外部アクセス信号に対応して前記第2メモリに対する 読み出しまたは書込コマンド信号を前記第2アクセス信 号として出力可能とされるともに、前記第1メモリに対 するリフレッシュを行うためのリフレッシュコマンド信 号を前記第1アクセス信号として出力可能とされる半導 体装置。

US9632727B2
CLAIM 16
. The system of claim 15 , wherein data bits (クロック) of the predetermined data string have a uniform logic level .
JP2003006041A
CLAIM 13
【請求項13】請求項1において、前記第1及び第2チ ップのそれぞれは、クロック (data bits) に同期したコマンドにより 読出し/書込みを行うダイナミック・ランダムアクセス ・メモリ(DRAM)チップであり、前記第4チップ は、フラッシュメモリチップである半導体装置。




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US20020049883A1

Filed: 2001-04-25     Issued: 2002-04-25

System and method for restoring a computer system after a failure

(Original Assignee) Roxio Inc     (Current Assignee) NortonLifeLock Inc

Eric Schneider, Chuck Ferril, Doug Wheeler, Larry Schwartz, Edward Bruggeman
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations (only memory) on the solid state storage medium (hard disk) in response to requests from a computer system (computer system) , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US20020049883A1
CLAIM 16
. A method according to claim 9 of restoring the roles of the simulated and current disks , where the roles are either automatically restored upon re-starting a computer system (computer system) having the disk , or upon appropriate signaling from the user , wherein the current disk' ;
s state is reverted to that of the simulated disk .

US20020049883A1
CLAIM 30
. A method according to claim 1 further including providing hardware redundancy for a main disk on which both a current operating system visible image as well as circular record of the prior states of overwritten disk locations is maintained , comprising providing a second hard disk (state storage medium, state storage system, storage processer) and a communication link between it and a computer to which the main hard disk is interfaced , wherein original states of overwritten data is maintained on both disks , and where synchronization between the two disks is maintained such that if the second disk does not contain any data from the main disk , or such data is so far out of date that a simulated disk established on the main disk cannot reach sufficiently back in time to reflect the current image last established on the second disk , then the second disk' ;
s contents is discarded and re-initialized by : suspending the second disk' ;
s normal processing , establishing a simulated disk on the main disk near the current time , and transferring the simulated image to the second disk , and should the main disk' ;
s simulated image be overrun by changes occurring on the main disk , re-starting the process , and once the simulated image has been transferred , the available historic prior states of overwritten data on the main disk , starting at the time at which the simulated disk was established , and moving backward to more distant times , are transferred to the second disk for as much as there is such data on the main disk and sufficient disk space on the second disk to accept it .

US20020049883A1
CLAIM 49
. A method according to claim 44 wherein trusted code for which access to resources is allowed resides in a read-only memory (storage operations) (ROM) .

US9632727B2
CLAIM 4
. The apparatus of claim 1 , wherein the indexer comprises firmware (electronic hardware) of the solid-state storage controller .
US20020049883A1
CLAIM 45
. A method according to claim 44 wherein the gate is implemented by electronic hardware (indexer comprises firmware) that in response to a request from executing non-trusted code , causes the processor to process an interrupt request and vector into known and trusted code , and at the same time , enable access to the resources .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface (communication link, complex data) configured to communicatively couple the solid-state storage controller to the computer system (computer system) , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial (Universal Serial Bus) Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface (communication link, complex data) , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA (large numbers) bus interface , a Small Computer System Interface (said list) (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
US20020049883A1
CLAIM 6
. A method according to claim 1 wherein the record that maintains where overwritten data has been re-directed for the purpose of preserving the original states is maintained on a disk and involves complex data (PCI Express bus interface, bus interface) structures that cannot be updated in a single disk write , and further wherein safe transitions from one usable state of the record to another is provided by representing the record using a mapping system in which the record is broken into a set of components , providing for the existence of two records , one of which is the prior valid record state and the other is a transitional state , where both versions may share common components , where the valid record is fully flushed and present on the physical disk , where a switch page on the disk holds sufficient information to locate the prior valid record mapping , wherein the transitional record state mapping is defined in terms of zero or more components present in the prior valid record state as well as components reflective of desired changes to achieve a new valid state , wherein after all data associated with the transitional version is stored to disk , the switch page is updated to establish this transitional version as the new prior valid record state , and wherein any interrupt of this update results in a switch page that either in effect indicates the original prior valid state or the new state that was associated with the transitional state .

US20020049883A1
CLAIM 16
. A method according to claim 9 of restoring the roles of the simulated and current disks , where the roles are either automatically restored upon re-starting a computer system (computer system) having the disk , or upon appropriate signaling from the user , wherein the current disk' ;
s state is reverted to that of the simulated disk .

US20020049883A1
CLAIM 29
. A method according to claim 7 for reverting a disk to an earlier state while at the same time maintaining certain files in their current state , comprising reverting the disk to a specified time in the past time , scanning a record of previous file activity to establish a list of files that have changed between the specified time in the past and the time just prior to the requested revert , presenting said list (Small Computer System Interface) of files to a user and allowing files to be selected , and at a time after the revert , and retrieving the last state of said files just prior to the reversion .

US20020049883A1
CLAIM 30
. A method according to claim 1 further including providing hardware redundancy for a main disk on which both a current operating system visible image (external SATA bus interface) as well as circular record of the prior states of overwritten disk locations is maintained , comprising providing a second hard disk and a communication link (PCI Express bus interface, bus interface) between it and a computer to which the main hard disk is interfaced , wherein original states of overwritten data is maintained on both disks , and where synchronization between the two disks is maintained such that if the second disk does not contain any data from the main disk , or such data is so far out of date that a simulated disk established on the main disk cannot reach sufficiently back in time to reflect the current image last established on the second disk , then the second disk' ;
s contents is discarded and re-initialized by : suspending the second disk' ;
s normal processing , establishing a simulated disk on the main disk near the current time , and transferring the simulated image to the second disk , and should the main disk' ;
s simulated image be overrun by changes occurring on the main disk , re-starting the process , and once the simulated image has been transferred , the available historic prior states of overwritten data on the main disk , starting at the time at which the simulated disk was established , and moving backward to more distant times , are transferred to the second disk for as much as there is such data on the main disk and sufficient disk space on the second disk to accept it .

US20020049883A1
CLAIM 34
. A method of providing redundant disk storage according to claim 30 wherein the second disk interfaces to the computer associated with the main disk using a parallel port , serial port , Universal Serial Bus (external Serial, external Serial Advanced Technology Attachment bus interface) (USB) , Firewire , or network interface .

US20020049883A1
CLAIM 43
. A method of saving the original states of data on a hard disk that are about to be overwritten by an operating system , wherein as part of the mapping and optimization of such processes , large numbers (external SATA) of disk pages are exchanged , whereas such exchanging is optimally done in batch processes involving sweeping read and write passes , that to avoid having to wait until such batch operation competes in order to service a disk read request by the operating system , the read request is immediately processed , comprising interrupting the batch exchange process , determining where the data to be read currently exists and re-directing the read to such location , and then resuming processing of the batch exchange .

US9632727B2
CLAIM 8
. The system of claim 7 , further comprising means for providing a storage interface to accept requests to perform storage operations (only memory) on the solid-state storage medium in reference to the logical blocks and to accept the message identifying the logical block that is not being used to reference data stored on the solid-state storage medium .
US20020049883A1
CLAIM 49
. A method according to claim 44 wherein trusted code for which access to resources is allowed resides in a read-only memory (storage operations) (ROM) .

US9632727B2
CLAIM 9
. The system of claim 7 , wherein unmapping the identified logical block comprises invalidating an entry of the logical-to-physical mappings , the entry indicating a mapping between the identified logical block and the particular storage (two disk) block .
US20020049883A1
CLAIM 30
. A method according to claim 1 further including providing hardware redundancy for a main disk on which both a current operating system visible image as well as circular record of the prior states of overwritten disk locations is maintained , comprising providing a second hard disk and a communication link between it and a computer to which the main hard disk is interfaced , wherein original states of overwritten data is maintained on both disks , and where synchronization between the two disk (particular storage) s is maintained such that if the second disk does not contain any data from the main disk , or such data is so far out of date that a simulated disk established on the main disk cannot reach sufficiently back in time to reflect the current image last established on the second disk , then the second disk' ;
s contents is discarded and re-initialized by : suspending the second disk' ;
s normal processing , establishing a simulated disk on the main disk near the current time , and transferring the simulated image to the second disk , and should the main disk' ;
s simulated image be overrun by changes occurring on the main disk , re-starting the process , and once the simulated image has been transferred , the available historic prior states of overwritten data on the main disk , starting at the time at which the simulated disk was established , and moving backward to more distant times , are transferred to the second disk for as much as there is such data on the main disk and sufficient disk space on the second disk to accept it .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor (data store) coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US20020049883A1
CLAIM 1
. A method , comprising keeping a record of the roles of some disk locations X and Y , wherein after an operating system requests overwriting of old data at location X with new data , the storing of the new data is at least initially diverted to a different disk location Y instead of taking the place of the old data at location X , and wherein the old data remains in its original location on the disk ;
and reconstructing a prior state of data store (storage processor) d on the disk by (i) reading data from the disk which the operating system has not requested to be overwritten before the prior state occurred , (ii) reading old data retained on the disk , and (iii) combining the data read from both sources (i) and (ii) .

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (data store) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
US20020049883A1
CLAIM 1
. A method , comprising keeping a record of the roles of some disk locations X and Y , wherein after an operating system requests overwriting of old data at location X with new data , the storing of the new data is at least initially diverted to a different disk location Y instead of taking the place of the old data at location X , and wherein the old data remains in its original location on the disk ;
and reconstructing a prior state of data store (storage processor) d on the disk by (i) reading data from the disk which the operating system has not requested to be overwritten before the prior state occurred , (ii) reading old data retained on the disk , and (iii) combining the data read from both sources (i) and (ii) .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer (hard disk) is configured such that , responsive to receiving a read request (current data, read request) specifying one or more logical addresses included in the empty-block directive command , the storage processor (data store) returns a predetermined data string .
US20020049883A1
CLAIM 1
. A method , comprising keeping a record of the roles of some disk locations X and Y , wherein after an operating system requests overwriting of old data at location X with new data , the storing of the new data is at least initially diverted to a different disk location Y instead of taking the place of the old data at location X , and wherein the old data remains in its original location on the disk ;
and reconstructing a prior state of data store (storage processor) d on the disk by (i) reading data from the disk which the operating system has not requested to be overwritten before the prior state occurred , (ii) reading old data retained on the disk , and (iii) combining the data read from both sources (i) and (ii) .

US20020049883A1
CLAIM 7
. A method according to claim 1 wherein the disk' ;
s state , as viewable by the operating system , is effectively returned to a state from an earlier time , by moving data and/or re-mapping the current and old data such that accesses by the operating system to various disk locations are re-directed to the disk locations that contain the data from this earlier time , while at the same time maintaining current data (read request, read request specifying one) on the disk .

US20020049883A1
CLAIM 30
. A method according to claim 1 further including providing hardware redundancy for a main disk on which both a current operating system visible image as well as circular record of the prior states of overwritten disk locations is maintained , comprising providing a second hard disk (state storage medium, state storage system, storage processer) and a communication link between it and a computer to which the main hard disk is interfaced , wherein original states of overwritten data is maintained on both disks , and where synchronization between the two disks is maintained such that if the second disk does not contain any data from the main disk , or such data is so far out of date that a simulated disk established on the main disk cannot reach sufficiently back in time to reflect the current image last established on the second disk , then the second disk' ;
s contents is discarded and re-initialized by : suspending the second disk' ;
s normal processing , establishing a simulated disk on the main disk near the current time , and transferring the simulated image to the second disk , and should the main disk' ;
s simulated image be overrun by changes occurring on the main disk , re-starting the process , and once the simulated image has been transferred , the available historic prior states of overwritten data on the main disk , starting at the time at which the simulated disk was established , and moving backward to more distant times , are transferred to the second disk for as much as there is such data on the main disk and sufficient disk space on the second disk to accept it .

US20020049883A1
CLAIM 43
. A method of saving the original states of data on a hard disk that are about to be overwritten by an operating system , wherein as part of the mapping and optimization of such processes , large numbers of disk pages are exchanged , whereas such exchanging is optimally done in batch processes involving sweeping read and write passes , that to avoid having to wait until such batch operation competes in order to service a disk read request (read request, read request specifying one) by the operating system , the read request is immediately processed , comprising interrupting the batch exchange process , determining where the data to be read currently exists and re-directing the read to such location , and then resuming processing of the batch exchange .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US6725321B1

Filed: 2001-03-01     Issued: 2004-04-20

Memory system

(Original Assignee) Lexar Media Inc     (Current Assignee) Micron Technology Inc

Alan Welsh Sinclair, Natalia Victorovna Ouspenskaia, Richard Michael Taylor, Sergey Anatolievich Gorobets
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state (solid state) storage medium (write operation) in response to requests from a computer system , including storing data (said memory, more sector) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data (said memory, more sector) pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US6725321B1
CLAIM 1
. A memory system for connection to a host processor , the system comprising : a solid state (solid state) memory having non-volatile memory sectors which are individually addressable and which are arranged in erasable blocks of sectors , each said sector having a physical address defining its physical position in the memory ;
and a controller for writing data structures to and reading data structures from the memory , and for sorting the blocks of sectors into blocks which are treated as erased and blocks which are treated as not erased ;
wherein the controller includes : means for translating logical addresses received from the host processor to physical addresses of said memory (store data, storing data) sectors in the memory ;
a Write Pointer (WP) for pointing to the physical address of a sector to which data is to be written to from the host processor , said Write Pointer (WP) being controlled by the controller to move in a predetermined order through the physical addresses of the memory sectors of any block which is treated as erased and , when the block has been filled , to move another of the erased blocks ;
wherein the controller is configured so that , when a sector write command is received from the host processor , the controller translates a logical address received from the host processor to a physical address to which data is written by allocating for said logical address that physical address to which said Write Pointer (WP) is currently pointing , and wherein the controller is configured to compile a Sector Allocation Table (SAT) of logical addresses with respective physical addresses which have been allocated therefore by the controller , and to update the SAT less frequently than memory sectors are written to with data from the host processor and further wherein the controller is configured so that , when a sector write command is received by the controller from the host processor which command renders obsolete data previously written to another sector , the controller stores in a temporary memory of the memory system the address of the sector containing the now obsolete data and further wherein the controller is configured so as to allow only a fixed predetermined number of blocks at any time , herein referred to as the Current Obsolete Blocks (COBs) , to contain one or more sector (store data, storing data) s containing obsolete data which was written by the Write Pointer (WP) , and so that when all the sectors in a said COB contain obsolete data , the COB is immediately erased .

US6725321B1
CLAIM 12
. A memory system according to claim 11 , wherein the controller is configured so that for every n contiguous sector write operation (solid state storage medium) s the controller executes for a multiple sector write command received from the host processor , where n is less than or equal to the number of solid state memory chips in the memory system , the controller writes substantially concurrently to one sector in each of n of the chips .

US9632727B2
CLAIM 2
. The apparatus of claim 1 , wherein the indexer assigns logical addresses to physical addresses by use of index entries , and wherein the indexer removes an index entry (logical sector, memory array) corresponding to the identified logical address in response to the message .
US6725321B1
CLAIM 10
. A memory system according to claim 7 , wherein the controller is configured to store in a temporary memory of the memory system respective lists of logical sector (index entry) addresses corresponding to sectors in the memory to which relocated data has been written to by the RP (herein referred to as the Relocation Sector List or RSL) , the SWP (herein referred to as the Write System Sector List or WSSL) , and the SRP (herein referred to as the System Relocation Sector List or SRSL) since the SAT was last updated , and the controller is configured to store in said temporary memory corresponding lists of the order of blocks which have been used by the RP , SWP and SRP (herein referred to as the Relocation Block List (RBL) , the Write System Block List (WSBL) and the System Relocation Block List(SRBL)) .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial (temporary memory) Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (said list) (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
US6725321B1
CLAIM 1
. A memory system for connection to a host processor , the system comprising : a solid state memory having non-volatile memory sectors which are individually addressable and which are arranged in erasable blocks of sectors , each said sector having a physical address defining its physical position in the memory ;
and a controller for writing data structures to and reading data structures from the memory , and for sorting the blocks of sectors into blocks which are treated as erased and blocks which are treated as not erased ;
wherein the controller includes : means for translating logical addresses received from the host processor to physical addresses of said memory sectors in the memory ;
a Write Pointer (WP) for pointing to the physical address of a sector to which data is to be written to from the host processor , said Write Pointer (WP) being controlled by the controller to move in a predetermined order through the physical addresses of the memory sectors of any block which is treated as erased and , when the block has been filled , to move another of the erased blocks ;
wherein the controller is configured so that , when a sector write command is received from the host processor , the controller translates a logical address received from the host processor to a physical address to which data is written by allocating for said logical address that physical address to which said Write Pointer (WP) is currently pointing , and wherein the controller is configured to compile a Sector Allocation Table (SAT) of logical addresses with respective physical addresses which have been allocated therefore by the controller , and to update the SAT less frequently than memory sectors are written to with data from the host processor and further wherein the controller is configured so that , when a sector write command is received by the controller from the host processor which command renders obsolete data previously written to another sector , the controller stores in a temporary memory (external Serial) of the memory system the address of the sector containing the now obsolete data and further wherein the controller is configured so as to allow only a fixed predetermined number of blocks at any time , herein referred to as the Current Obsolete Blocks (COBs) , to contain one or more sectors containing obsolete data which was written by the Write Pointer (WP) , and so that when all the sectors in a said COB contain obsolete data , the COB is immediately erased .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (said memory, more sector) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
US6725321B1
CLAIM 1
. A memory system for connection to a host processor , the system comprising : a solid state memory having non-volatile memory sectors which are individually addressable and which are arranged in erasable blocks of sectors , each said sector having a physical address defining its physical position in the memory ;
and a controller for writing data structures to and reading data structures from the memory , and for sorting the blocks of sectors into blocks which are treated as erased and blocks which are treated as not erased ;
wherein the controller includes : means for translating logical addresses received from the host processor to physical addresses of said memory (store data, storing data) sectors in the memory ;
a Write Pointer (WP) for pointing to the physical address of a sector to which data is to be written to from the host processor , said Write Pointer (WP) being controlled by the controller to move in a predetermined order through the physical addresses of the memory sectors of any block which is treated as erased and , when the block has been filled , to move another of the erased blocks ;
wherein the controller is configured so that , when a sector write command is received from the host processor , the controller translates a logical address received from the host processor to a physical address to which data is written by allocating for said logical address that physical address to which said Write Pointer (WP) is currently pointing , and wherein the controller is configured to compile a Sector Allocation Table (SAT) of logical addresses with respective physical addresses which have been allocated therefore by the controller , and to update the SAT less frequently than memory sectors are written to with data from the host processor and further wherein the controller is configured so that , when a sector write command is received by the controller from the host processor which command renders obsolete data previously written to another sector , the controller stores in a temporary memory of the memory system the address of the sector containing the now obsolete data and further wherein the controller is configured so as to allow only a fixed predetermined number of blocks at any time , herein referred to as the Current Obsolete Blocks (COBs) , to contain one or more sector (store data, storing data) s containing obsolete data which was written by the Write Pointer (WP) , and so that when all the sectors in a said COB contain obsolete data , the COB is immediately erased .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US6606690B2

Filed: 2001-02-20     Issued: 2003-08-12

System and method for accessing a storage area network as network attached storage

(Original Assignee) Hewlett Packard Development Co LP     (Current Assignee) Hewlett Packard Enterprise Development LP

Michael Padovano
US9632727B2
CLAIM 2
. The apparatus of claim 1 , wherein the indexer assigns logical addresses to physical addresses by use of index entries , and wherein the indexer removes an index entry (d line) corresponding to the identified logical address in response to the message .
US6606690B2
CLAIM 17
. The method of claim 16 , further comprising the steps of : (d) providing an command line (index entry) interface (CLI) at the graphical user interface ;
and (e) allowing a user to input the storage directive as a CLI command into the CLI .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA (first host, more host) bus interface , a Small Computer (allocation message) System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
US6606690B2
CLAIM 1
. A method for interfacing a storage area network (SAN) with a first data communication network , wherein one or more host (external SATA) s coupled to the first data communication network can access data stored in one or more of a plurality of storage devices in the SAN , wherein the one or more hosts access one or more of the plurality of storage devices as network attached storage (NAS) , comprising the steps of : coupling a SAN server to a SAN ;
coupling a NAS server to the SAN server through a second data communication network ;
coupling the NAS server to the first data communication network ;
allocating a portion of at least one of the plurality of storage devices from the SAN server to the NAS server ;
configuring the allocated portion as NAS storage in the NAS server ;
exporting the configured portion from the NAS server to be accessible to the one or more hosts coupled to the first data communication network .

US6606690B2
CLAIM 6
. The method of claim 5 , wherein said allocating step comprises the step of : sending a NAS protocol storage allocation message (Small Computer) from the SAN server to the NAS server .

US6606690B2
CLAIM 20
. An apparatus for accessing a plurality of storage devices in a storage area network (SAN) as network attached storage (NAS) in a data communication network , comprising : a SAN server that includes : a first interface configured to be coupled to the SAN ;
and a second interface that is coupled to a first data communication network ;
and a NAS server that includes : a third interface configured to be coupled to a second data communication network ;
and a fourth interface that is coupled to said first data communication network ;
wherein said SAN server allocates a first portion of the plurality of storage devices in the SAN to be accessible through said second interface to at least one first host (external SATA) coupled to said first data communication network ;
wherein said SAN server allocates a second portion of the plurality of storage devices in the SAN to said NAS server ;
and wherein said NAS server configures access to said second portion of the plurality of storage devices to at least one second host coupled to said second data communication network .

US9632727B2
CLAIM 8
. The system of claim 7 , further comprising means for providing a storage interface to accept requests to perform storage operations (third interface) on the solid-state storage medium in reference to the logical blocks and to accept the message identifying the logical block that is not being used to reference data stored on the solid-state storage medium .
US6606690B2
CLAIM 20
. An apparatus for accessing a plurality of storage devices in a storage area network (SAN) as network attached storage (NAS) in a data communication network , comprising : a SAN server that includes : a first interface configured to be coupled to the SAN ;
and a second interface that is coupled to a first data communication network ;
and a NAS server that includes : a third interface (storage interface to accept requests to perform storage operations) configured to be coupled to a second data communication network ;
and a fourth interface that is coupled to said first data communication network ;
wherein said SAN server allocates a first portion of the plurality of storage devices in the SAN to be accessible through said second interface to at least one first host coupled to said first data communication network ;
wherein said SAN server allocates a second portion of the plurality of storage devices in the SAN to said NAS server ;
and wherein said NAS server configures access to said second portion of the plurality of storage devices to at least one second host coupled to said second data communication network .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor (data store) coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US6606690B2
CLAIM 1
. A method for interfacing a storage area network (SAN) with a first data communication network , wherein one or more hosts coupled to the first data communication network can access data store (storage processor) d in one or more of a plurality of storage devices in the SAN , wherein the one or more hosts access one or more of the plurality of storage devices as network attached storage (NAS) , comprising the steps of : coupling a SAN server to a SAN ;
coupling a NAS server to the SAN server through a second data communication network ;
coupling the NAS server to the first data communication network ;
allocating a portion of at least one of the plurality of storage devices from the SAN server to the NAS server ;
configuring the allocated portion as NAS storage in the NAS server ;
exporting the configured portion from the NAS server to be accessible to the one or more hosts coupled to the first data communication network .

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (data store) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
US6606690B2
CLAIM 1
. A method for interfacing a storage area network (SAN) with a first data communication network , wherein one or more hosts coupled to the first data communication network can access data store (storage processor) d in one or more of a plurality of storage devices in the SAN , wherein the one or more hosts access one or more of the plurality of storage devices as network attached storage (NAS) , comprising the steps of : coupling a SAN server to a SAN ;
coupling a NAS server to the SAN server through a second data communication network ;
coupling the NAS server to the first data communication network ;
allocating a portion of at least one of the plurality of storage devices from the SAN server to the NAS server ;
configuring the allocated portion as NAS storage in the NAS server ;
exporting the configured portion from the NAS server to be accessible to the one or more hosts coupled to the first data communication network .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor (data store) returns a predetermined data string .
US6606690B2
CLAIM 1
. A method for interfacing a storage area network (SAN) with a first data communication network , wherein one or more hosts coupled to the first data communication network can access data store (storage processor) d in one or more of a plurality of storage devices in the SAN , wherein the one or more hosts access one or more of the plurality of storage devices as network attached storage (NAS) , comprising the steps of : coupling a SAN server to a SAN ;
coupling a NAS server to the SAN server through a second data communication network ;
coupling the NAS server to the first data communication network ;
allocating a portion of at least one of the plurality of storage devices from the SAN server to the NAS server ;
configuring the allocated portion as NAS storage in the NAS server ;
exporting the configured portion from the NAS server to be accessible to the one or more hosts coupled to the first data communication network .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US6763424B2

Filed: 2001-01-19     Issued: 2004-07-13

Partial block data programming and reading operations in a non-volatile memory

(Original Assignee) SanDisk Corp     (Current Assignee) SanDisk Technologies LLC

Kevin M. Conley
US9632727B2
CLAIM 3
. The apparatus of claim 1 , wherein the indexer assigns logical addresses to physical addresses by use of index metadata (overlapping blocks) maintained in a memory of the storage controller .
US6763424B2
CLAIM 17
. A method of operating a non-volatile memory system having an array of memory storage elements organized into at least two sub-arrays , wherein the individual sub-arrays are divided into a plurality of non-overlapping blocks (index metadata) of storage elements wherein a block contains the smallest group of memory storage elements that are erasable together , and the individual blocks are divided into a plurality of pages of storage elements wherein a page is the smallest group of memory storage elements that are programmable together , comprising : linking at least one block from individual ones of said at least two sub-arrays to form a metablock wherein its component blocks are erased together as a unit , and updating pages of original data within any of the metablock component blocks less than all the pages within the block by programming replacement data into pages within another at least one block in only a designated one of the sub-arrays regardless of which sub-array the data being updated is stored .

US9632727B2
CLAIM 5
. The apparatus of claim 1 , further comprising a garbage collector (logical page) configured to designate that the physical address previously assigned to the identified logical address comprises data suitable for removal from the solid-state storage medium in response to the message .
US6763424B2
CLAIM 12
. In a non-volatile memory system having a plurality of blocks of memory storage elements that are individually erasable as a unit and which are individually organized into a plurality of pages of memory storage elements that are individually programmable together , a method of substituting new data for superceded data within at least one page of one of the plurality of blocks while data in at least another page of said one block is not replaced , comprising : programming the new data into at least one page of said one or another of the plurality of blocks , wherein pages within the individual blocks are programmed in a designated order , identifying the at least one page of superceded data and the at least one page of new data by a common logical address , reading pages of data within said one and , if new data has been programmed thereinto , another block in a reverse order from which they were programmed , passing over any pages of data so read which have the same logical page (garbage collector, read request specifying one) address as a page whose data has already been read ;
and wherein the at least one page of superceded data is less than all the data contained in said one block .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA (host system) bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
US6763424B2
CLAIM 16
. The method of any one of claims 1 , 2 and 3 - 6 , wherein the non-volatile memory system is formed within an enclosed card having an electrical connector along one edge thereof that operably connects with a host system (external SATA, external SATA bus interface) .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor (data store) coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US6763424B2
CLAIM 27
. The method of claim 20 , wherein reading and assembling data includes reading and using original data store (storage processor) d in the first plurality of pages that has not been updated .

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (data store) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
US6763424B2
CLAIM 27
. The method of claim 20 , wherein reading and assembling data includes reading and using original data store (storage processor) d in the first plurality of pages that has not been updated .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one (logical page) or more logical addresses included in the empty-block directive command , the storage processor (data store) returns a predetermined data string .
US6763424B2
CLAIM 12
. In a non-volatile memory system having a plurality of blocks of memory storage elements that are individually erasable as a unit and which are individually organized into a plurality of pages of memory storage elements that are individually programmable together , a method of substituting new data for superceded data within at least one page of one of the plurality of blocks while data in at least another page of said one block is not replaced , comprising : programming the new data into at least one page of said one or another of the plurality of blocks , wherein pages within the individual blocks are programmed in a designated order , identifying the at least one page of superceded data and the at least one page of new data by a common logical address , reading pages of data within said one and , if new data has been programmed thereinto , another block in a reverse order from which they were programmed , passing over any pages of data so read which have the same logical page (garbage collector, read request specifying one) address as a page whose data has already been read ;
and wherein the at least one page of superceded data is less than all the data contained in said one block .

US6763424B2
CLAIM 27
. The method of claim 20 , wherein reading and assembling data includes reading and using original data store (storage processor) d in the first plurality of pages that has not been updated .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US6594712B1

Filed: 2000-10-20     Issued: 2003-07-15

Inifiniband channel adapter for performing direct DMA between PCI bus and inifiniband link

(Original Assignee) Banderacom Inc     (Current Assignee) Intel Corp

Christopher Pettey, Lawrence H. Rubin
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system , including storing data (direct transfer, said memory) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data (direct transfer, said memory) pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US6594712B1
CLAIM 11
. The Infiniband channel adapter of claim 10 , wherein each of said plurality of programmable registers includes a block number portion , wherein said block number portion specifies one of a plurality of blocks within said memory (store data, storing data) for storing Infiniband RDMA Write packets .

US6594712B1
CLAIM 39
. The method of claim 38 , further comprising : programming a configuration register for specifying an address range within said local address space dedicated to direct transfer (store data, storing data) s of data between said I/O controller and said channel adapter , wherein said local address is within said address range , prior to said receiving said first virtual address .

US9632727B2
CLAIM 2
. The apparatus of claim 1 , wherein the indexer assigns logical addresses to physical addresses by use of index entries (local node) , and wherein the indexer removes an index entry (local node) corresponding to the identified logical address in response to the message .
US6594712B1
CLAIM 38
. A method for translating Infiniband remote virtual addresses to local addresses , comprising : receiving in a first Infiniband packet a first virtual address of a first memory location in a remote Infiniband node , by a local Infiniband node ;
allocating a local address within a local address space of a local bus on said local node (index entries, index entry) for transferring first data directly between an I/O controller of said local node and an Infiniband channel adapter of said local node in response to said receiving said first virtual address ;
receiving in a second Infiniband packet a second virtual address of a second memory location in said remote Infiniband node , by said local Infiniband node , wherein said first and second virtual addresses are spatially disparate ;
and allocating said local address for transferring second data directly between said I/O controller and said channel adapter in response to said receiving said second virtual address .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface (PCI bus) , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
US6594712B1
CLAIM 15
. The Infiniband channel adapter of claim 1 , wherein said local bus interface is a PCI bus (PCI Express bus interface) interface .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (direct transfer, said memory) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
US6594712B1
CLAIM 11
. The Infiniband channel adapter of claim 10 , wherein each of said plurality of programmable registers includes a block number portion , wherein said block number portion specifies one of a plurality of blocks within said memory (store data, storing data) for storing Infiniband RDMA Write packets .

US6594712B1
CLAIM 39
. The method of claim 38 , further comprising : programming a configuration register for specifying an address range within said local address space dedicated to direct transfer (store data, storing data) s of data between said I/O controller and said channel adapter , wherein said local address is within said address range , prior to said receiving said first virtual address .

US9632727B2
CLAIM 8
. The system of claim 7 , further comprising means for providing a storage interface (virtual addresses) to accept requests to perform storage operations on the solid-state storage medium in reference to the logical blocks and to accept the message identifying the logical block that is not being used to reference data stored on the solid-state storage medium .
US6594712B1
CLAIM 38
. A method for translating Infiniband remote virtual addresses (storage interface) to local addresses , comprising : receiving in a first Infiniband packet a first virtual address of a first memory location in a remote Infiniband node , by a local Infiniband node ;
allocating a local address within a local address space of a local bus on said local node for transferring first data directly between an I/O controller of said local node and an Infiniband channel adapter of said local node in response to said receiving said first virtual address ;
receiving in a second Infiniband packet a second virtual address of a second memory location in said remote Infiniband node , by said local Infiniband node , wherein said first and second virtual addresses are spatially disparate ;
and allocating said local address for transferring second data directly between said I/O controller and said channel adapter in response to said receiving said second virtual address .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface (virtual addresses) configured to communicate with a storage client ;

a storage processor coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US6594712B1
CLAIM 38
. A method for translating Infiniband remote virtual addresses (storage interface) to local addresses , comprising : receiving in a first Infiniband packet a first virtual address of a first memory location in a remote Infiniband node , by a local Infiniband node ;
allocating a local address within a local address space of a local bus on said local node for transferring first data directly between an I/O controller of said local node and an Infiniband channel adapter of said local node in response to said receiving said first virtual address ;
receiving in a second Infiniband packet a second virtual address of a second memory location in said remote Infiniband node , by said local Infiniband node , wherein said first and second virtual addresses are spatially disparate ;
and allocating said local address for transferring second data directly between said I/O controller and said channel adapter in response to said receiving said second virtual address .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer (remote direct memory access) is configured such that , responsive to receiving a read request (transferring said data, read request) specifying one or more logical addresses included in the empty-block directive command , the storage processor returns a predetermined data string .
US6594712B1
CLAIM 1
. An Infiniband channel adapter , comprising : a local bus interface , for coupling the channel adapter to an I/O controller by a local bus , configured to receive data from the I/O controller if a local bus address of said data is within a predetermined address range of the local bus address space ;
and a bus router , in communication with said local bus interface , configured to create an Infiniband remote direct memory access (storage processer) (RDMA) . Write packet including said data in response to said local bus interface receiving said data from the I/O controller for transmission to a remote Infiniband node previously requesting said data .

US6594712B1
CLAIM 34
. The Infiniband I/O unit of claim 29 , wherein said processor is configured to program said I/O controller to transfer said data to said channel adapter at said address and to program said channel adapter to receive said data from said I/O controller and to create said Infiniband RDMA Write packet in response to receiving an out-of-band I/O read request (read request) Infiniband packet from the remote Infiniband node .

US6594712B1
CLAIM 37
. The Infiniband I/O unit of claim 35 , wherein said channel adapter is further configured to determine from said Infiniband RDMA Read Response packet which of a plurality of address sub-ranges of said predetermined address range was previously allocated for use by said I/O controller for transferring said data (read request) .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US6404647B1

Filed: 2000-08-24     Issued: 2002-06-11

Solid-state mass memory storage device

(Original Assignee) HP Inc     (Current Assignee) Seagate Technology LLC

Mark W. Minne′
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system , including storing data (store information) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data (memory storage) pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US6404647B1
CLAIM 1
. A solid-state mass memory storage (store data) device , comprising : a printed circuit assembly ;
a plurality of nonvolatile , high density storage devices mounted to said printed circuit assembly and electrically connected thereto ;
at least one controller mounted to said printed circuit assembly and electrically connected thereto ;
and a connector mounted to said printed circuit assembly and electrically connected thereto , said connector being adapted to electrically connect said solid-state mass memory storage device to a separate electronic device ;
wherein said mass memory storage device has a form factor equivalent to that of a conventional disk drive such that said storage device is configured for replacing a disk drive of a computing device .

US6404647B1
CLAIM 5
. The device of claim 1 , wherein said high density storage devices are electrically connected in a redundant . array such that said high density storage devices redundantly store information (storing data) .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (store information) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
US6404647B1
CLAIM 5
. The device of claim 1 , wherein said high density storage devices are electrically connected in a redundant . array such that said high density storage devices redundantly store information (storing data) .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
JP2002056671A

Filed: 2000-08-14     Issued: 2002-02-22

ダイナミック型ramのデータ保持方法と半導体集積回路装置

(Original Assignee) Hitachi Ltd; 株式会社日立製作所     

Yutaka Ito, Hidetoshi Iwai, 伊藤  豊, 秀俊 岩井
US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor (メモリ) coupled to the storage interface ;

a flash memory device (アドレス) coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
JP2002056671A
CLAIM 3
【請求項3】 記憶キャパシタとアドレス (flash memory device) 選択MOSF ETからなるダイナミック型メモリ (storage processor) セルを含み、他の回 路との間で読み出しと書き込み動作を行なわない情報保 持モードを有するメモリ回路と、 データ保持制御回路とを備え、 上記データ保持制御回路は、 ECC回路及びリフレッシュ周期設定回路を含み、 上記ECC回路は、上記メモリ回路の情報保持モードに 入るのときに起動され、上記メモリ回路に保持された複 数のデータを読み出して誤り検出訂正用の検査ビットを 生成して記憶させる第1動作と、上記情報保持モードか ら他の回路との間で読み出し又は書き込み動作が行われ る通常動作に復帰するときに起動され、上記メモリ回路 に保持された複数のデータと検査ビットを読み出してデ ータの誤りビットを修正して対応するメモリセルに書き 込む第2動作を行ない、 上記リフレッシュ周期設定回路は、上記ECC回路での 上記検査ビットを用いたエラー発生の許容範囲内で長く された周期を設定してリフレッシュ動作を行わせるもの であることを特徴とする半導体集積回路装置。

US9632727B2
CLAIM 13
. The system of claim 12 , wherein the logical-to-physical translation layer is stored in the flash memory device (アドレス) .
JP2002056671A
CLAIM 3
【請求項3】 記憶キャパシタとアドレス (flash memory device) 選択MOSF ETからなるダイナミック型メモリセルを含み、他の回 路との間で読み出しと書き込み動作を行なわない情報保 持モードを有するメモリ回路と、 データ保持制御回路とを備え、 上記データ保持制御回路は、 ECC回路及びリフレッシュ周期設定回路を含み、 上記ECC回路は、上記メモリ回路の情報保持モードに 入るのときに起動され、上記メモリ回路に保持された複 数のデータを読み出して誤り検出訂正用の検査ビットを 生成して記憶させる第1動作と、上記情報保持モードか ら他の回路との間で読み出し又は書き込み動作が行われ る通常動作に復帰するときに起動され、上記メモリ回路 に保持された複数のデータと検査ビットを読み出してデ ータの誤りビットを修正して対応するメモリセルに書き 込む第2動作を行ない、 上記リフレッシュ周期設定回路は、上記ECC回路での 上記検査ビットを用いたエラー発生の許容範囲内で長く された周期を設定してリフレッシュ動作を行わせるもの であることを特徴とする半導体集積回路装置。

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (メモリ) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
JP2002056671A
CLAIM 3
【請求項3】 記憶キャパシタとアドレス選択MOSF ETからなるダイナミック型メモリ (storage processor) セルを含み、他の回 路との間で読み出しと書き込み動作を行なわない情報保 持モードを有するメモリ回路と、 データ保持制御回路とを備え、 上記データ保持制御回路は、 ECC回路及びリフレッシュ周期設定回路を含み、 上記ECC回路は、上記メモリ回路の情報保持モードに 入るのときに起動され、上記メモリ回路に保持された複 数のデータを読み出して誤り検出訂正用の検査ビットを 生成して記憶させる第1動作と、上記情報保持モードか ら他の回路との間で読み出し又は書き込み動作が行われ る通常動作に復帰するときに起動され、上記メモリ回路 に保持された複数のデータと検査ビットを読み出してデ ータの誤りビットを修正して対応するメモリセルに書き 込む第2動作を行ない、 上記リフレッシュ周期設定回路は、上記ECC回路での 上記検査ビットを用いたエラー発生の許容範囲内で長く された周期を設定してリフレッシュ動作を行わせるもの であることを特徴とする半導体集積回路装置。

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor (メモリ) returns a predetermined data string .
JP2002056671A
CLAIM 3
【請求項3】 記憶キャパシタとアドレス選択MOSF ETからなるダイナミック型メモリ (storage processor) セルを含み、他の回 路との間で読み出しと書き込み動作を行なわない情報保 持モードを有するメモリ回路と、 データ保持制御回路とを備え、 上記データ保持制御回路は、 ECC回路及びリフレッシュ周期設定回路を含み、 上記ECC回路は、上記メモリ回路の情報保持モードに 入るのときに起動され、上記メモリ回路に保持された複 数のデータを読み出して誤り検出訂正用の検査ビットを 生成して記憶させる第1動作と、上記情報保持モードか ら他の回路との間で読み出し又は書き込み動作が行われ る通常動作に復帰するときに起動され、上記メモリ回路 に保持された複数のデータと検査ビットを読み出してデ ータの誤りビットを修正して対応するメモリセルに書き 込む第2動作を行ない、 上記リフレッシュ周期設定回路は、上記ECC回路での 上記検査ビットを用いたエラー発生の許容範囲内で長く された周期を設定してリフレッシュ動作を行わせるもの であることを特徴とする半導体集積回路装置。




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
JP2001297316A

Filed: 2000-04-14     Issued: 2001-10-26

メモリカード及びその制御方法

(Original Assignee) Mitsubishi Electric Corp; 三菱電機株式会社     

Hidenori Mitani, 秀徳 三谷
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations (動作周波数) on the solid state storage medium in response to requests from a computer system , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
JP2001297316A
CLAIM 1
【請求項1】 少なくとも一つの記憶素子と、 原クロックを生成する原クロック発生回路と、 前記原クロックを可変の分周比で分周し、前記記憶素子 の動作周波数 (storage operations) を規定するクロック信号を生成する分周回 路とを備えるメモリカード。

US9632727B2
CLAIM 8
. The system of claim 7 , further comprising means for providing a storage interface to accept requests to perform storage operations (動作周波数) on the solid-state storage medium in reference to the logical blocks and to accept the message identifying the logical block that is not being used to reference data stored on the solid-state storage medium .
JP2001297316A
CLAIM 1
【請求項1】 少なくとも一つの記憶素子と、 原クロックを生成する原クロック発生回路と、 前記原クロックを可変の分周比で分周し、前記記憶素子 の動作周波数 (storage operations) を規定するクロック信号を生成する分周回 路とを備えるメモリカード。

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor coupled to the storage interface ;

a flash memory device (アドレス) coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
JP2001297316A
CLAIM 4
【請求項4】 複数の記憶素子と、 前記複数の記憶素子に書き込みが行われた物理アドレス (flash memory device) を格納する、複数のタスクレジスタとを備えるメモリカ ード。

US9632727B2
CLAIM 13
. The system of claim 12 , wherein the logical-to-physical translation layer is stored in the flash memory device (アドレス) .
JP2001297316A
CLAIM 4
【請求項4】 複数の記憶素子と、 前記複数の記憶素子に書き込みが行われた物理アドレス (flash memory device) を格納する、複数のタスクレジスタとを備えるメモリカ ード。

US9632727B2
CLAIM 16
. The system of claim 15 , wherein data bits (クロック) of the predetermined data string have a uniform logic level .
JP2001297316A
CLAIM 1
【請求項1】 少なくとも一つの記憶素子と、 原クロック (data bits) を生成する原クロック発生回路と、 前記原クロックを可変の分周比で分周し、前記記憶素子 の動作周波数を規定するクロック信号を生成する分周回 路とを備えるメモリカード。




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US6240040B1

Filed: 2000-03-15     Issued: 2001-05-29

Multiple bank simultaneous operation for a flash memory

(Original Assignee) Fujitsu Ltd; Advanced Micro Devices Inc     (Current Assignee) Monterey Research LLC

Takao Akaogi, Lee Edward Cleveland, Kendra Nguyen
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system (operation control) , the message indicating that the identified logical address is erased .
US6240040B1
CLAIM 2
. The address buffering and decoding architecture of claim 1 , further comprising : a write operation control (state storage controller, host operating system, state storage system) circuit located at each of the N banks , wherein each write operation control circuit is responsive to a respective one of the N write select signals .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (address buffer) (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
US6240040B1
CLAIM 1
. An address buffer (Peripheral Component Interconnect) ing and decoding architecture to facilitate simultaneous reading from and writing to N banks of core memory cells in a memory , wherein for the duration of a read operation at one bank of the N banks , a write operation can only be performed on any one of the other N- 1 banks ;
and wherein for the duration of a write operation at one bank of the N banks , a read operation can only be performed on any one of the other N- 1 banks , the architecture comprising : a control logic circuit to generate N read select signals to select one bank of the N banks for a read operation and N write select signals to select another bank of the N banks for a write operation ;
an address selection circuit located at each of the N banks , wherein each address selection circuit is configured to receive from the control logic circuit a respective one of the N read select signals and a respective one of the N write select signals ;
and address buffer circuitry to simultaneously provide a write address and a read address in order to access core memory cells , wherein respective first portions of the write and read addresses are provided to the control logic circuit to generate the respective N read select signals and N write select signals , and respective second portions of the write and read addresses are provided to the respective address selection circuit .

US9632727B2
CLAIM 8
. The system of claim 7 , further comprising means for providing a storage interface (first portions) to accept requests to perform storage operations on the solid-state storage medium in reference to the logical blocks and to accept the message identifying the logical block that is not being used to reference data stored on the solid-state storage medium .
US6240040B1
CLAIM 1
. An address buffering and decoding architecture to facilitate simultaneous reading from and writing to N banks of core memory cells in a memory , wherein for the duration of a read operation at one bank of the N banks , a write operation can only be performed on any one of the other N- 1 banks ;
and wherein for the duration of a write operation at one bank of the N banks , a read operation can only be performed on any one of the other N- 1 banks , the architecture comprising : a control logic circuit to generate N read select signals to select one bank of the N banks for a read operation and N write select signals to select another bank of the N banks for a write operation ;
an address selection circuit located at each of the N banks , wherein each address selection circuit is configured to receive from the control logic circuit a respective one of the N read select signals and a respective one of the N write select signals ;
and address buffer circuitry to simultaneously provide a write address and a read address in order to access core memory cells , wherein respective first portions (storage interface) of the write and read addresses are provided to the control logic circuit to generate the respective N read select signals and N write select signals , and respective second portions of the write and read addresses are provided to the respective address selection circuit .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface (first portions) configured to communicate with a storage client ;

a storage processor coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US6240040B1
CLAIM 1
. An address buffering and decoding architecture to facilitate simultaneous reading from and writing to N banks of core memory cells in a memory , wherein for the duration of a read operation at one bank of the N banks , a write operation can only be performed on any one of the other N- 1 banks ;
and wherein for the duration of a write operation at one bank of the N banks , a read operation can only be performed on any one of the other N- 1 banks , the architecture comprising : a control logic circuit to generate N read select signals to select one bank of the N banks for a read operation and N write select signals to select another bank of the N banks for a write operation ;
an address selection circuit located at each of the N banks , wherein each address selection circuit is configured to receive from the control logic circuit a respective one of the N read select signals and a respective one of the N write select signals ;
and address buffer circuitry to simultaneously provide a write address and a read address in order to access core memory cells , wherein respective first portions (storage interface) of the write and read addresses are provided to the control logic circuit to generate the respective N read select signals and N write select signals , and respective second portions of the write and read addresses are provided to the respective address selection circuit .

US9632727B2
CLAIM 16
. The system of claim 15 , wherein data bits (read data bus) of the predetermined data string have a uniform logic level .
US6240040B1
CLAIM 6
. The address buffering and decoding architecture of claim 1 , further comprising : a read data bus (data bits) located at each of the N banks , wherein each read data bus is configured for connection to a sense amplifier responsively to a respective one of the N read select signals .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US6170047B1

Filed: 1999-12-14     Issued: 2001-01-02

System and method for managing system memory and/or non-volatile memory using a memory controller with integrated compression and decompression capabilities

(Original Assignee) Interactive Silicon Inc     (Current Assignee) Intellectual Ventures I LLC

Thomas A. Dye
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium (data accesses) in response to requests from a computer system (computer system) , including storing data (storing data) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US6170047B1
CLAIM 7
. The method of claim 4 , wherein the computer system (computer system) includes a non-volatile memory coupled to the memory controller , wherein the requested data resides in the nonvolatile memory , wherein the memory controller performing said access of data comprises : the memory controller accessing said requested data from the non-volatile memory ;
the memory controller storing said requested data in the system memory ;
and the memory controller providing said requested data to the CPU .

US6170047B1
CLAIM 20
. A method for managing data accesses (state storage medium, solid state storage medium) in a system including a CPU , a system memory for storing data (storing data) , a memory controller coupled to the system memory , and a non-volatile memory coupled to the memory controller , wherein the memory controller performs memory control functions for the system memory , wherein the memory controller includes a hardware compression and decompression engine , the method comprising : determining a replacement block of data in the system memory , wherein the system memory is a volatile memory which stores uncompressed data currently being used for execution by the CPU , wherein the uncompressed data includes most recently used data ;
the memory controller compressing said replacement block of data ;
the memory controller transferring said compressed replacement block to the non-volatile memory for storage after said compressing said replacement block of data ;
wherein said compressing said replacement block of data and transferring said compressed replacement block of data to the non-volatile memory operates to free up at least a portion of said system memory .

US9632727B2
CLAIM 5
. The apparatus of claim 1 , further comprising a garbage collector (nonvolatile memory) configured to designate that the physical address previously assigned to the identified logical address comprises data suitable for removal from the solid-state storage medium in response to the message .
US6170047B1
CLAIM 7
. The method of claim 4 , wherein the computer system includes a non-volatile memory coupled to the memory controller , wherein the requested data resides in the nonvolatile memory (garbage collector) , wherein the memory controller performing said access of data comprises : the memory controller accessing said requested data from the non-volatile memory ;
the memory controller storing said requested data in the system memory ;
and the memory controller providing said requested data to the CPU .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system (computer system) , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
US6170047B1
CLAIM 7
. The method of claim 4 , wherein the computer system (computer system) includes a non-volatile memory coupled to the memory controller , wherein the requested data resides in the nonvolatile memory , wherein the memory controller performing said access of data comprises : the memory controller accessing said requested data from the non-volatile memory ;
the memory controller storing said requested data in the system memory ;
and the memory controller providing said requested data to the CPU .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (storing data) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
US6170047B1
CLAIM 20
. A method for managing data accesses in a system including a CPU , a system memory for storing data (storing data) , a memory controller coupled to the system memory , and a non-volatile memory coupled to the memory controller , wherein the memory controller performs memory control functions for the system memory , wherein the memory controller includes a hardware compression and decompression engine , the method comprising : determining a replacement block of data in the system memory , wherein the system memory is a volatile memory which stores uncompressed data currently being used for execution by the CPU , wherein the uncompressed data includes most recently used data ;
the memory controller compressing said replacement block of data ;
the memory controller transferring said compressed replacement block to the non-volatile memory for storage after said compressing said replacement block of data ;
wherein said compressing said replacement block of data and transferring said compressed replacement block of data to the non-volatile memory operates to free up at least a portion of said system memory .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US6278633B1

Filed: 1999-11-05     Issued: 2001-08-21

High bandwidth flash memory that selects programming parameters according to measurements of previous programming operations

(Original Assignee) Multi Level Memory Technology     (Current Assignee) Samsung Electronics Co Ltd

Sau C. Wong, Hock C. So
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium (write operation) in response to requests from a computer system , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data (store data) pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US6278633B1
CLAIM 3
. The memory of claim 1 , wherein the selected memory cell comprises a dummy cell that is not used to store data (store data, storage client) .

US6278633B1
CLAIM 6
. A multi-level , non-volatile memory comprising a plurality of pipelines , wherein each pipeline comprises : an array of non-volatile memory cells ;
a write circuit coupled to the array , the write circuit programming a selected memory cell by applying programming voltages to the array to change a threshold voltage of the selected memory cell ;
a measurement circuit that measures a programming of the selected memory cell ;
and a selection circuit that selects a programming parameter for subsequent write operation (solid state storage medium) s according to a measurement of the programming of the selected memory cell .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client (store data) that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
US6278633B1
CLAIM 3
. The memory of claim 1 , wherein the selected memory cell comprises a dummy cell that is not used to store data (store data, storage client) .

US9632727B2
CLAIM 9
. The system of claim 7 , wherein unmapping the identified logical block comprises invalidating an entry of the logical-to-physical mappings , the entry indicating a mapping between the identified logical block and the particular storage block (write circuit) .
US6278633B1
CLAIM 1
. A non-volatile memory comprising : an array of non-volatile memory cells ;
a write circuit (particular storage block) coupled to the array , the write circuit programming a selected memory cell by applying programming voltages to the array to change a threshold voltage of the selected memory cell ;
a measurement circuit that measures a programming operation performed on the selected memory cell ;
and a selection circuit that selects a programming parameter for subsequent programming operations according to a measurement of the programming operation performed on the selected memory cell .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client (store data) ;

a storage processor coupled to the storage interface ;

a flash memory device (programming operations) coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US6278633B1
CLAIM 1
. A non-volatile memory comprising : an array of non-volatile memory cells ;
a write circuit coupled to the array , the write circuit programming a selected memory cell by applying programming voltages to the array to change a threshold voltage of the selected memory cell ;
a measurement circuit that measures a programming operation performed on the selected memory cell ;
and a selection circuit that selects a programming parameter for subsequent programming operations (flash memory device) according to a measurement of the programming operation performed on the selected memory cell .

US6278633B1
CLAIM 3
. The memory of claim 1 , wherein the selected memory cell comprises a dummy cell that is not used to store data (store data, storage client) .

US9632727B2
CLAIM 13
. The system of claim 12 , wherein the logical-to-physical translation layer is stored in the flash memory device (programming operations) .
US6278633B1
CLAIM 1
. A non-volatile memory comprising : an array of non-volatile memory cells ;
a write circuit coupled to the array , the write circuit programming a selected memory cell by applying programming voltages to the array to change a threshold voltage of the selected memory cell ;
a measurement circuit that measures a programming operation performed on the selected memory cell ;
and a selection circuit that selects a programming parameter for subsequent programming operations (flash memory device) according to a measurement of the programming operation performed on the selected memory cell .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US6336174B1

Filed: 1999-08-09     Issued: 2002-01-01

Hardware assisted memory backup system and method

(Original Assignee) Maxtor Corp     (Current Assignee) Maxtor Corp

Qiang Li, Clifford E. Strang, Jr., Jon F. Zahornacky
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations (backup system) on the solid state storage medium (backup system) in response to requests from a computer system , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system (host operating system) , the message indicating that the identified logical address is erased .
US6336174B1
CLAIM 13
. The apparatus of claim 1 , the controller further comprising : a control circuit for generating address and control signals for accessing the volatile and nonvolatile memory ;
a power interface circuit coupled to an auxiliary power supply for providing power to the apparatus in response to the trigger event ;
and a timing device for determining if the host operating system (host operating system) of the host computer system has hung .

US6336174B1
CLAIM 17
. A memory backup system (state storage medium, state storage controller, storage operations, solid state storage medium, state storage system) coupled to a host computer for providing memory backup in response to a trigger event , the system comprising : a volatile memory coupled to an information source for receiving and storing the digital information ;
a nonvolatile memory coupled to the volatile memory for receiving and storing the digital information communicated from the volatile memory ;
a controller coupled to the volatile memory and the nonvolatile memory for controlling the communication of the digital information between the volatile memory and the nonvolatile memory in response to the trigger event , the controller configured to determine the type of the trigger event from control information stored in the volatile memory ;
isolation devices for electrically isolating the system from the host computer in response to the trigger event ;
and an auxiliary power source for providing power to the system in response to the trigger event .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface (system memory) , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface (central processing unit) , and a Fibre Channel interface .
US6336174B1
CLAIM 48
. The system of claim 41 , wherein the system is adapted to be directly connected to a system memory (PCI Express bus interface) bus that is directly connected to a central processing unit (internet SCSI interface) .

US9632727B2
CLAIM 8
. The system of claim 7 , further comprising means for providing a storage interface to accept requests to perform storage operations (backup system) on the solid-state storage medium in reference to the logical blocks and to accept the message identifying the logical block that is not being used to reference data stored on the solid-state storage medium .
US6336174B1
CLAIM 17
. A memory backup system (state storage medium, state storage controller, storage operations, solid state storage medium, state storage system) coupled to a host computer for providing memory backup in response to a trigger event , the system comprising : a volatile memory coupled to an information source for receiving and storing the digital information ;
a nonvolatile memory coupled to the volatile memory for receiving and storing the digital information communicated from the volatile memory ;
a controller coupled to the volatile memory and the nonvolatile memory for controlling the communication of the digital information between the volatile memory and the nonvolatile memory in response to the trigger event , the controller configured to determine the type of the trigger event from control information stored in the volatile memory ;
isolation devices for electrically isolating the system from the host computer in response to the trigger event ;
and an auxiliary power source for providing power to the system in response to the trigger event .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request (n information) specifying one or more logical addresses included in the empty-block directive command , the storage processor returns a predetermined data string .
US6336174B1
CLAIM 1
. An apparatus coupled to a host computer system for communicating digital information between volatile and nonvolatile memory in response to a trigger event , the apparatus comprising : a volatile memory coupled to an information (read request) source for receiving and storing the digital information ;
a nonvolatile memory coupled to the volatile memory for receiving and storing the digital information communicated from the volatile memory ;
and a controller coupled to the volatile memory and the nonvolatile memory for controlling the communication of the digital information between the volatile memory and the nonvolatile memory in response to the trigger event , the controller configured to determine the type of the trigger event from control information stored in the volatile memory .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US6374266B1

Filed: 1999-07-24     Issued: 2002-04-16

Method and apparatus for storing information in a data processing system

(Original Assignee) Ralph Shnelvar     (Current Assignee) Chrysalis Storage LLC

Ralph Shnelvar
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system (computer system) , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US6374266B1
CLAIM 1
. In a computer system (computer system) including at least one data source wherein data is stored in source allocation units and a data repository having access to the data source and including a storage device for storing data in repository allocation units , a method for storing data from the data source in the storage device of the data repository , comprising the steps of : (a) reading data from the source allocation units and restructuring the data into data unit having a size corresponding to the repository allocation units ;
(b) for each data unit read from the data source , generating a hash value for the data of each data unit ;
(c) for each data unit read from the data source , searching a data table for a table entry having a hash value matching a hash value of the data unit read from the data source , wherein each table entry contains the hash value of a data unit stored in a repository allocation unit and a repository allocation unit pointer to the corresponding repository allocation unit ;
(d) when the hash value of a data unit does not match any hash value of any table entry in the data table , writing the data of the data unit into a newly allocated repository allocation unit , generating a new table entry containing the hash value of the data unit and a repository allocation unit pointer to the newly allocated repository allocation unit , and writing the new table entry containing the hash value and a repository allocation unit pointer to the newly allocated repository allocation unit to the data table ;
(e) when the hash value of a data unit matches the hash value of a data entry in the data table , accessing the table entry having a matching hash value and using the repository allocation unit pointer therein to read the data of the corresponding repository allocation unit , and comparing the data of the data unit and the data of the corresponding repository allocation unit , if the data of the data unit matches the data of the corresponding repository allocation unit , discarding the data unit , and if the data of the data unit does not match the data of the corresponding repository allocation unit , writing the data of the data unit into a newly allocated repository allocation unit , generating a new table entry containing the hash value of the data unit and a repository allocation unit pointer to the newly allocated repository allocation unit , and inserting the new table entry into the data table ;
and , (f) repeating steps (a) through (e) until all source allocation units have been read .

US9632727B2
CLAIM 2
. The apparatus of claim 1 , wherein the indexer assigns logical addresses to physical addresses by use of index entries (data entry) , and wherein the indexer removes an index entry corresponding to the identified logical address in response to the message .
US6374266B1
CLAIM 1
. In a computer system including at least one data source wherein data is stored in source allocation units and a data repository having access to the data source and including a storage device for storing data in repository allocation units , a method for storing data from the data source in the storage device of the data repository , comprising the steps of : (a) reading data from the source allocation units and restructuring the data into data unit having a size corresponding to the repository allocation units ;
(b) for each data unit read from the data source , generating a hash value for the data of each data unit ;
(c) for each data unit read from the data source , searching a data table for a table entry having a hash value matching a hash value of the data unit read from the data source , wherein each table entry contains the hash value of a data unit stored in a repository allocation unit and a repository allocation unit pointer to the corresponding repository allocation unit ;
(d) when the hash value of a data unit does not match any hash value of any table entry in the data table , writing the data of the data unit into a newly allocated repository allocation unit , generating a new table entry containing the hash value of the data unit and a repository allocation unit pointer to the newly allocated repository allocation unit , and writing the new table entry containing the hash value and a repository allocation unit pointer to the newly allocated repository allocation unit to the data table ;
(e) when the hash value of a data unit matches the hash value of a data entry (index entries) in the data table , accessing the table entry having a matching hash value and using the repository allocation unit pointer therein to read the data of the corresponding repository allocation unit , and comparing the data of the data unit and the data of the corresponding repository allocation unit , if the data of the data unit matches the data of the corresponding repository allocation unit , discarding the data unit , and if the data of the data unit does not match the data of the corresponding repository allocation unit , writing the data of the data unit into a newly allocated repository allocation unit , generating a new table entry containing the hash value of the data unit and a repository allocation unit pointer to the newly allocated repository allocation unit , and inserting the new table entry into the data table ;
and , (f) repeating steps (a) through (e) until all source allocation units have been read .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system (computer system) , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface (new data) , and a Fibre Channel interface (system input) .
US6374266B1
CLAIM 1
. In a computer system (computer system) including at least one data source wherein data is stored in source allocation units and a data repository having access to the data source and including a storage device for storing data in repository allocation units , a method for storing data from the data source in the storage device of the data repository , comprising the steps of : (a) reading data from the source allocation units and restructuring the data into data unit having a size corresponding to the repository allocation units ;
(b) for each data unit read from the data source , generating a hash value for the data of each data unit ;
(c) for each data unit read from the data source , searching a data table for a table entry having a hash value matching a hash value of the data unit read from the data source , wherein each table entry contains the hash value of a data unit stored in a repository allocation unit and a repository allocation unit pointer to the corresponding repository allocation unit ;
(d) when the hash value of a data unit does not match any hash value of any table entry in the data table , writing the data of the data unit into a newly allocated repository allocation unit , generating a new table entry containing the hash value of the data unit and a repository allocation unit pointer to the newly allocated repository allocation unit , and writing the new table entry containing the hash value and a repository allocation unit pointer to the newly allocated repository allocation unit to the data table ;
(e) when the hash value of a data unit matches the hash value of a data entry in the data table , accessing the table entry having a matching hash value and using the repository allocation unit pointer therein to read the data of the corresponding repository allocation unit , and comparing the data of the data unit and the data of the corresponding repository allocation unit , if the data of the data unit matches the data of the corresponding repository allocation unit , discarding the data unit , and if the data of the data unit does not match the data of the corresponding repository allocation unit , writing the data of the data unit into a newly allocated repository allocation unit , generating a new table entry containing the hash value of the data unit and a repository allocation unit pointer to the newly allocated repository allocation unit , and inserting the new table entry into the data table ;
and , (f) repeating steps (a) through (e) until all source allocation units have been read .

US6374266B1
CLAIM 7
. The method of claim 5 for storing data from the data source in the storage device of the data repository , wherein step (d) includes the steps of : (d1) determining whether a data record exists to receive the table entry of the newly received data unit , and if a data record does not exist to receive the table entry , going to step (d2) , and if a data record exists to receive the table entry , going to step (d3) ;
(d2) creating a new data (internet SCSI interface) record to receive the table entry of the newly received data unit , (d3) determining whether the data record has space to receive a new table entry , and if the data record has space to receive a new table entry , going to step (d6) , and if the data record does not have space to receive a new table entry , going to step (d4) ;
(d4) sorting the last data record according to the hash values of the record entries appearing therein ;
(d5) creating a new data record to be a new last data record of the data table , and linking the new last data record to the chain of one or more data records of the data table ;
(d6) inserting the new table entry into the last data record of the data table , and returning to step (d) .

US6374266B1
CLAIM 21
. The method of claim 1 , further comprising the steps of : (g) mounting the contents of the repository allocation units of a data repository into a system as a restored disk volume having a directory structure identical to that of the data source , and accessing files on the restored disk volume from a software application using file system input (Fibre Channel interface) /output calls .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor returns a predetermined data string (next data) .
US6374266B1
CLAIM 6
. The method of claim 5 for storing data from the data source in the storage device of the data repository , wherein step (c) includes the steps of : (c1) fetching a first/next data (data string) record ;
(c2) determining whether the fetched first/next data record is the last data record of a linked list of one or more data records in the data table wherein the last data record of the data table is not sorted according to the hash values represented therein , and going to step (c3) when the fetched first/next data record is not the last data record of the data table , and going to step (c5) when the fetched data record is the last data record of the data table ;
(c3) determining whether the hash value of the newly received data unit is smaller than the hash value of the first table entry of the data record , and when the hash value of the newly received data unit is smaller than the hash value of the first table entry , going to step (c1) , and when the hash value of the newly received data unit is not smaller than the hash value of the first table entry , going to step (c4) ;
(c4) determining whether the hash value of the newly received data unit is larger than the hash value of the last table entry of the data record , and when the hash value of the newly received data unit is larger than the hash value of the last table entry of the data record , going to step (c1) , and when the hash value of the newly received data unit is not larger than the hash value of the last table entry of the data record , going to step (c6) ;
(c5) performing a linear search to find a match between the hash value of the newly received data unit and the hash value of a table entry in the data record , and when a match between the hash value of the newly received data unit and the hash value of a table entry in the data record is not found , returning to step (d) , and when a match between the hash value of the newly received data unit and the hash value of a table entry in the data record is found , returning to step (e) . (c6) performing a binary search to find a match between the hash value of the newly received data unit and the hash value of a table entry in the data record , and when a match between the hash value of the newly received data unit and the hash value of a table entry in the data record is not found , returning to step (d) , and when a match between the hash value of the newly received data unit and the hash value of a table entry in the data record is found , returning to step (e) .

US9632727B2
CLAIM 16
. The system of claim 15 , wherein data bits of the predetermined data string (next data) have a uniform logic level .
US6374266B1
CLAIM 6
. The method of claim 5 for storing data from the data source in the storage device of the data repository , wherein step (c) includes the steps of : (c1) fetching a first/next data (data string) record ;
(c2) determining whether the fetched first/next data record is the last data record of a linked list of one or more data records in the data table wherein the last data record of the data table is not sorted according to the hash values represented therein , and going to step (c3) when the fetched first/next data record is not the last data record of the data table , and going to step (c5) when the fetched data record is the last data record of the data table ;
(c3) determining whether the hash value of the newly received data unit is smaller than the hash value of the first table entry of the data record , and when the hash value of the newly received data unit is smaller than the hash value of the first table entry , going to step (c1) , and when the hash value of the newly received data unit is not smaller than the hash value of the first table entry , going to step (c4) ;
(c4) determining whether the hash value of the newly received data unit is larger than the hash value of the last table entry of the data record , and when the hash value of the newly received data unit is larger than the hash value of the last table entry of the data record , going to step (c1) , and when the hash value of the newly received data unit is not larger than the hash value of the last table entry of the data record , going to step (c6) ;
(c5) performing a linear search to find a match between the hash value of the newly received data unit and the hash value of a table entry in the data record , and when a match between the hash value of the newly received data unit and the hash value of a table entry in the data record is not found , returning to step (d) , and when a match between the hash value of the newly received data unit and the hash value of a table entry in the data record is found , returning to step (e) . (c6) performing a binary search to find a match between the hash value of the newly received data unit and the hash value of a table entry in the data record , and when a match between the hash value of the newly received data unit and the hash value of a table entry in the data record is not found , returning to step (d) , and when a match between the hash value of the newly received data unit and the hash value of a table entry in the data record is found , returning to step (e) .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
JP2000259525A

Filed: 1999-03-10     Issued: 2000-09-22

通信プロトコルにおける応答返却方法および通信制御装置

(Original Assignee) Nec Corp; 日本電気株式会社     

Masaya Matsuzono, 昌也 松薗
US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface (プロトコル) , and a Fibre Channel interface .
JP2000259525A
CLAIM 1
【請求項1】 コンピュータ装置間において通信を行う 際に使用される通信プロトコル (internet SCSI interface) において、 通信路確立時に、データ送信側コンピュータ装置の送信 バッファの最大容量を受信側コンピュータ装置に記憶さ せ、 通信時において、前記受信側コンピュータ装置が受信し たデータ量が前記送信バッファの最大容量の所定割合を 越えた時、前記受信側コンピュータ装置が応答返却信号 を前記送信側コンピュータ装置へ送信することを特徴と する通信プロトコルにおける応答返却方法。

US9632727B2
CLAIM 8
. The system of claim 7 , further comprising means for providing a storage interface to accept requests to perform storage operations (通信時) on the solid-state storage medium in reference to the logical blocks and to accept the message identifying the logical block that is not being used to reference data stored on the solid-state storage medium .
JP2000259525A
CLAIM 1
【請求項1】 コンピュータ装置間において通信を行う 際に使用される通信プロトコルにおいて、 通信路確立時に、データ送信側コンピュータ装置の送信 バッファの最大容量を受信側コンピュータ装置に記憶さ せ、 通信時 (storage interface to accept requests to perform storage operations) において、前記受信側コンピュータ装置が受信し たデータ量が前記送信バッファの最大容量の所定割合を 越えた時、前記受信側コンピュータ装置が応答返却信号 を前記送信側コンピュータ装置へ送信することを特徴と する通信プロトコルにおける応答返却方法。




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US6412080B1

Filed: 1999-02-23     Issued: 2002-06-25

Lightweight persistent storage system for flash memory devices

(Original Assignee) Microsoft Corp     (Current Assignee) Microsoft Technology Licensing LLC

Michael K. Fleming, Jun Liu
US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one (first location) of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
US6412080B1
CLAIM 14
. A method of operating an internet/television terminal having a CPU , RAM , and non-volatile storage for an operating system and user preferences , comprising : providing a flash memory to serve as said non-volatile storage ;
storing a user preference in a first location (bus interface comprises one) in said flash memory ;
if available storage in said flash memory exceeds a threshold , updating said user preference by marking the earlier-stored user preference as invalid , and storing an updated user preference in a different , second , location in said flash memory ;
if available storage in said flash memory does not exceed a threshold , updating said first user preference by copying valid data found in a first contiguous range of storage locations of length N bytes to a contiguous range of storage locations of length M bytes , and assuring that M is less than N by omitting copying of data that is invalid , and then storing the updated user preference .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor (data store) coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US6412080B1
CLAIM 7
. The method of claim 5 in which one of said single-bit flags indicates that the data store (storage processor) d in the sector may be invalid .

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (data store) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
US6412080B1
CLAIM 7
. The method of claim 5 in which one of said single-bit flags indicates that the data store (storage processor) d in the sector may be invalid .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor (data store) returns a predetermined data string .
US6412080B1
CLAIM 7
. The method of claim 5 in which one of said single-bit flags indicates that the data store (storage processor) d in the sector may be invalid .

US9632727B2
CLAIM 16
. The system of claim 15 , wherein data bits of the predetermined data string have a uniform logic (non-volatile storage) level .
US6412080B1
CLAIM 14
. A method of operating an internet/television terminal having a CPU , RAM , and non-volatile storage (uniform logic) for an operating system and user preferences , comprising : providing a flash memory to serve as said non-volatile storage ;
storing a user preference in a first location in said flash memory ;
if available storage in said flash memory exceeds a threshold , updating said user preference by marking the earlier-stored user preference as invalid , and storing an updated user preference in a different , second , location in said flash memory ;
if available storage in said flash memory does not exceed a threshold , updating said first user preference by copying valid data found in a first contiguous range of storage locations of length N bytes to a contiguous range of storage locations of length M bytes , and assuring that M is less than N by omitting copying of data that is invalid , and then storing the updated user preference .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US6295577B1

Filed: 1999-02-23     Issued: 2001-09-25

Disc storage system having a non-volatile cache to store write data in the event of a power failure

(Original Assignee) Seagate Technology LLC     (Current Assignee) Seagate Technology LLC

David B. Anderson, Mark A. Gaertner, Monty A. Forehand, Robert W. Norman, Jr.
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data (store data) pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US6295577B1
CLAIM 1
. A disc storage system , comprising : (a) a rotatable storage disc having a disc surface ;
(b) a spindle motor operably coupled to the disc which is adapted to rotate the disc ;
(c) a transducer adapted for reading and writing data on the disc surface ;
(d) a volatile memory cache adapted to store data (store data, storage client) prior to writing the data to the disc surface ;
(e) a non-volatile memory cache in the disc storage system adapted to store data during a power loss ;
and (f) a controller in the storage system adapted to receive data from a host computer interface , temporarily cache the data in the volatile memory cache , and subsequently write the data onto the disc surface with the transducer , the controller further adapted to store the data in the non-volatile memory only upon detection of a power loss to the storage system .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface (power up) , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
US6295577B1
CLAIM 4
. The disc storage system of claim 1 wherein the controller reads data from the non-volatile memory upon power up (PCI Express bus interface) of the storage system .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client (store data) that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
US6295577B1
CLAIM 1
. A disc storage system , comprising : (a) a rotatable storage disc having a disc surface ;
(b) a spindle motor operably coupled to the disc which is adapted to rotate the disc ;
(c) a transducer adapted for reading and writing data on the disc surface ;
(d) a volatile memory cache adapted to store data (store data, storage client) prior to writing the data to the disc surface ;
(e) a non-volatile memory cache in the disc storage system adapted to store data during a power loss ;
and (f) a controller in the storage system adapted to receive data from a host computer interface , temporarily cache the data in the volatile memory cache , and subsequently write the data onto the disc surface with the transducer , the controller further adapted to store the data in the non-volatile memory only upon detection of a power loss to the storage system .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client (store data) ;

a storage processor coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US6295577B1
CLAIM 1
. A disc storage system , comprising : (a) a rotatable storage disc having a disc surface ;
(b) a spindle motor operably coupled to the disc which is adapted to rotate the disc ;
(c) a transducer adapted for reading and writing data on the disc surface ;
(d) a volatile memory cache adapted to store data (store data, storage client) prior to writing the data to the disc surface ;
(e) a non-volatile memory cache in the disc storage system adapted to store data during a power loss ;
and (f) a controller in the storage system adapted to receive data from a host computer interface , temporarily cache the data in the volatile memory cache , and subsequently write the data onto the disc surface with the transducer , the controller further adapted to store the data in the non-volatile memory only upon detection of a power loss to the storage system .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US6034882A

Filed: 1998-11-16     Issued: 2000-03-07

Vertically stacked field programmable nonvolatile memory and method of fabrication

(Original Assignee) SanDisk 3D LLC     (Current Assignee) RHOMBUS Inc ; SanDisk Technologies LLC

Mark G. Johnson, Thomas H. Lee, Vivek Subramanian, Paul Michael Farmwald, James M. Cleeves
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium (effect device) in response to requests from a computer system , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system (one dimension) , the message indicating that the identified logical address is erased .
US6034882A
CLAIM 22
. The cell defined by claim 1 wherein the state change element employs a Hall effect device (state storage medium) .

US6034882A
CLAIM 33
. The memory cell defined by claim 28 having a first conductor in contact with the steering element , the first conductor having a width approximately equal to one dimension (host operating system, data string) of the rectangular cross-section .

US9632727B2
CLAIM 2
. The apparatus of claim 1 , wherein the indexer assigns logical addresses to physical addresses by use of index entries , and wherein the indexer removes an index entry (d line) corresponding to the identified logical address in response to the message .
US6034882A
CLAIM 26
. The cell defined by claim 1 wherein one of the terminals of the cell is connected to a word line (index entry) .

US9632727B2
CLAIM 8
. The system of claim 7 , further comprising means for providing a storage interface (junction field) to accept requests to perform storage operations on the solid-state storage medium in reference to the logical blocks and to accept the message identifying the logical block that is not being used to reference data stored on the solid-state storage medium .
US6034882A
CLAIM 5
. The cell defined by claim 1 wherein the steering element is a junction field (storage interface) -effect transistor with a gate connected to one of a source or drain region .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface (junction field) configured to communicate with a storage client ;

a storage processor coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US6034882A
CLAIM 5
. The cell defined by claim 1 wherein the steering element is a junction field (storage interface) -effect transistor with a gate connected to one of a source or drain region .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor returns a predetermined data string (one dimension) .
US6034882A
CLAIM 33
. The memory cell defined by claim 28 having a first conductor in contact with the steering element , the first conductor having a width approximately equal to one dimension (host operating system, data string) of the rectangular cross-section .

US9632727B2
CLAIM 16
. The system of claim 15 , wherein data bits of the predetermined data string (one dimension) have a uniform logic level .
US6034882A
CLAIM 33
. The memory cell defined by claim 28 having a first conductor in contact with the steering element , the first conductor having a width approximately equal to one dimension (host operating system, data string) of the rectangular cross-section .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
JP2000122814A

Filed: 1998-10-15     Issued: 2000-04-28

拡張型ネットワーク接続二次記憶方法及び装置

(Original Assignee) Hitachi Ltd; 株式会社日立製作所     

Shigekazu Inohara, Furederiko Mashieru, Itaru Nishizawa, Hiroaki Odawara, Nobutoshi Sagawa, Mamoru Sugie, Aki Tomita, Naoki Watanabe, フレデリコ マシエル, 暢俊 佐川, 亜紀 富田, 宏明 小田原, 衛 杉江, 直企 渡邉, 茂和 猪原, 格 西澤
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system (行うこと) , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
JP2000122814A
CLAIM 18
【請求項18】1つ以上の第1のコンピュータと、1つ 以上の二次記憶装置と、該第1のコンピュータと該二次 記憶装置とを接続するネットワークまたは入出力用信号 線を備え、第1のコンピュータが1つ以上の応用プログ ラムを動作させ、該二次記憶装置が、電源断後もデータ を保持することが可能な記憶媒体(二次記憶)を備え、 該二次記憶が、複数の格納単位(ブロック)からなり、 該二次記憶が、該応用プログラムが用いる1つ以上の応 用向けデータ(オブジェクト)を1つ以上のブロックに 格納しており、該二次記憶装置が、ブロック単位入出力 の機能と応用プログラム向けの入出力(高機能入出力) の機能とを第1のコンピュータに提供し、コンピュータ システムの二次記憶装置であって、ブロック単位入出力 の機能を用いてオブジェクト単位入出力の機能を実現す るオブジェクトアクセスモジュールを保持し、該オブジ ェクトアクセスモジュールを用いて該高機能入出力を実 現するモジュール(機能モジュール)を、第1のコンピ ュータまたは第1のコンピュータと異なる第2のコンピ ュータから受けた後に、第1のコンピュータから該高機 能入出力の要求を受け、該機能モジュールを実行するこ とにより該要求の入出力を行うこと (computer system) を特徴とする拡張型 ネットワーク接続二次記憶方法。

US9632727B2
CLAIM 2
. The apparatus of claim 1 , wherein the indexer assigns logical addresses to physical addresses by use of index entries (リスト) , and wherein the indexer removes an index entry corresponding to the identified logical address in response to the message .
JP2000122814A
CLAIM 29
【請求項29】1つ以上の第1のコンピュータと、1つ 以上の二次記憶装置と、1つの第2のコンピュータ(管 理マシン)と、該第1のコンピュータと該二次記憶装置 と該管理マシンを接続するネットワークまたは入出力用 信号線を備え、第1のコンピュータが1つ以上の応用プ ログラムを動作させ、第2のコンピュータが該二次記憶 装置のリスト (index entries) を保持しており、該二次記憶装置が、電源 断後もデータを保持することが可能な記憶媒体(二次記 憶)を備え、該二次記憶が、複数の格納単位(ブロッ ク)からなり、該二次記憶装置が、ブロック単位入出力 の機能と、該応用プログラム向けの入出力(高機能入出 力)の機能またはオブジェクト単位入出力の機能とを第 1のコンピュータに提供し、該高機能入出力を実現する プログラム・モジュール(モジュール)を第1のコンピ ュータが第2のコンピュータに送り、第2のコンピュー タが、該モジュールを受け取り、該リストに保持された 該二次記憶装置の一部または全部に該モジュールを送 り、該二次記憶装置が該モジュールを受け取り、第1の コンピュータが該高機能入出力の要求を二次記憶装置に 送り、該二次記憶装置が該モジュールを起動することに より該高機能入出力を行う、ことを特徴とする管理マシ ン。

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system (行うこと) , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
JP2000122814A
CLAIM 18
【請求項18】1つ以上の第1のコンピュータと、1つ 以上の二次記憶装置と、該第1のコンピュータと該二次 記憶装置とを接続するネットワークまたは入出力用信号 線を備え、第1のコンピュータが1つ以上の応用プログ ラムを動作させ、該二次記憶装置が、電源断後もデータ を保持することが可能な記憶媒体(二次記憶)を備え、 該二次記憶が、複数の格納単位(ブロック)からなり、 該二次記憶が、該応用プログラムが用いる1つ以上の応 用向けデータ(オブジェクト)を1つ以上のブロックに 格納しており、該二次記憶装置が、ブロック単位入出力 の機能と応用プログラム向けの入出力(高機能入出力) の機能とを第1のコンピュータに提供し、コンピュータ システムの二次記憶装置であって、ブロック単位入出力 の機能を用いてオブジェクト単位入出力の機能を実現す るオブジェクトアクセスモジュールを保持し、該オブジ ェクトアクセスモジュールを用いて該高機能入出力を実 現するモジュール(機能モジュール)を、第1のコンピ ュータまたは第1のコンピュータと異なる第2のコンピ ュータから受けた後に、第1のコンピュータから該高機 能入出力の要求を受け、該機能モジュールを実行するこ とにより該要求の入出力を行うこと (computer system) を特徴とする拡張型 ネットワーク接続二次記憶方法。

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor returns a predetermined data string (特定部) .
JP2000122814A
CLAIM 10
【請求項10】前記オブジェクト記述データが、1つ以 上のブロックの特定部 (data string) 分に格納されているデータが、特 定の値またはパターンであるかによって、前記オブジェ クトのファイルフォーマットを特定するデータである請 求項7記載の拡張型ネットワーク接続二次記憶方法。

US9632727B2
CLAIM 16
. The system of claim 15 , wherein data bits of the predetermined data string (特定部) have a uniform logic level .
JP2000122814A
CLAIM 10
【請求項10】前記オブジェクト記述データが、1つ以 上のブロックの特定部 (data string) 分に格納されているデータが、特 定の値またはパターンであるかによって、前記オブジェ クトのファイルフォーマットを特定するデータである請 求項7記載の拡張型ネットワーク接続二次記憶方法。




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US6209088B1

Filed: 1998-09-21     Issued: 2001-03-27

Computer hibernation implemented by a computer operating system

(Original Assignee) Microsoft Corp     (Current Assignee) Microsoft Technology Licensing LLC

Ken Reneris
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium (readable storage media) in response to requests from a computer system , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US6209088B1
CLAIM 18
. One or more computer-readable storage media (state storage medium, solid state storage medium) containing instructions that execute from volatile memory in a computer , the instructions being executable to perform steps comprising : identifying areas of volatile memory that will potentially change during a subsequent saving step , the identified areas having physical memory addresses in the volatile memory ;
creating duplicate areas in the volatile memory corresponding to the identified areas of the volatile memory ;
saving contents of respective areas of volatile memory along with their physical memory addresses to non-volatile secondary storage ;
wherein the duplicate areas are written in the place of the corresponding identified areas , along with the physical addresses of the identified areas corresponding to the duplicate areas .

US9632727B2
CLAIM 5
. The apparatus of claim 1 , further comprising a garbage collector (allocating memory) configured to designate that the physical address previously assigned to the identified logical address comprises data suitable for removal from the solid-state storage medium in response to the message .
US6209088B1
CLAIM 7
. A method as recited in claim 6 , further comprising a step of allocating memory (garbage collector) from an operating system for the duplicate areas of memory .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer (known location) System Interface (SCSI) bus interface , an internet SCSI interface (device driver) , and a Fibre Channel interface .
US6209088B1
CLAIM 2
. A method as recited in claim 1 , further comprising : using a primary device driver (internet SCSI interface) for secondary storage except during the saving step ;
using a simplified device driver for the secondary storage during the saving step .

US6209088B1
CLAIM 23
. A computer comprising : volatile executable memory ;
non-volatile secondary storage ;
a processor that retrieves and executes instructions from the executable memory , such instruction execution resulting in a changing processor state and a changing executable memory state ;
an operating system loader from known location (Small Computer) s of executable memory ;
wherein the operating system loader performs steps comprising : retrieving areas of executable memory data from non-volatile secondary storage along with physical memory addresses of the retrieved data areas , the physical addresses designating where in the executable memory the data areas are to be restored ;
restoring the retrieved data areas to the executable memory , wherein any retrieved areas having physical addresses within the operating system loader portions of the executable memory are written to pre-allocated areas of the executable memory ;
an awaken loader which copies the pre-allocated areas of the executable memory to the operating system loader portions of the executable memory to restore retrieved areas having physical addresses within the operating system loader portions of the executable memory .

US9632727B2
CLAIM 8
. The system of claim 7 , further comprising means for providing a storage interface (following steps) to accept requests to perform storage operations on the solid-state storage medium in reference to the logical blocks and to accept the message identifying the logical block that is not being used to reference data stored on the solid-state storage medium .
US6209088B1
CLAIM 6
. In a computer that retrieves and executes instructions from volatile executable memory , a method of temporarily suspending instruction execution and saving volatile executable memory state to non-volatile secondary storage prior to a computer power-down , comprising the following steps (storage interface) : identifying areas of the volatile memory that will potentially change during a subsequent saving step , the identified areas having physical addresses in the volatile memory ;
creating duplicate areas in the volatile memory corresponding to the identified areas of the volatile memory ;
saving contents of respective areas of volatile memory along with their physical memory addresses to non-volatile secondary storage ;
wherein the duplicate areas are written in the place of the corresponding identified areas , along with the physical addresses of the identified areas corresponding to the duplicate areas .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface (following steps) configured to communicate with a storage client ;

a storage processor coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US6209088B1
CLAIM 6
. In a computer that retrieves and executes instructions from volatile executable memory , a method of temporarily suspending instruction execution and saving volatile executable memory state to non-volatile secondary storage prior to a computer power-down , comprising the following steps (storage interface) : identifying areas of the volatile memory that will potentially change during a subsequent saving step , the identified areas having physical addresses in the volatile memory ;
creating duplicate areas in the volatile memory corresponding to the identified areas of the volatile memory ;
saving contents of respective areas of volatile memory along with their physical memory addresses to non-volatile secondary storage ;
wherein the duplicate areas are written in the place of the corresponding identified areas , along with the physical addresses of the identified areas corresponding to the duplicate areas .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US6269382B1

Filed: 1998-08-31     Issued: 2001-07-31

Systems and methods for migration and recall of data from local and remote storage

(Original Assignee) Microsoft Corp     (Current Assignee) Microsoft Technology Licensing LLC ; Clouding Corp

Luis Felipe Cabrera, Michael G. Lotz
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system , including storing data (computer readable medium) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US6269382B1
CLAIM 25
. A computer-readable medium having computer executable instructions for implementing a method for selectively returning data of a file from a remote storage medium to a local storage medium in response to an access request for the data made after the data has been migrated from the local storage medium to the remote storage medium , said computer readable medium (storing data) comprising : means for storing the data of the file on the remote storage medium after the data has been migrated from the local storage medium to the remote storage medium ;
means for storing attributes of the file at the local storage medium ;
means for receiving an access request that involves the file ;
means for determining whether a response to the access request can be provided using only the attributes of the file stored at the local storage medium ;
means for responding to the access request without recalling the data from the remote storage medium if it has been determined that the response can be provided using only the attributes stored at the local storage medium ;
and means for responding to the access request by recalling the data from the remote storage medium if it has been determined that the response cannot be provided using only the attributes stored at the local storage medium .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (said list) (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
US6269382B1
CLAIM 6
. A method as recited in claim 5 , wherein said list (Small Computer System Interface) is kept as an integral part of an I/O system in a manner that provides faster access than a normal file .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (computer readable medium) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
US6269382B1
CLAIM 25
. A computer-readable medium having computer executable instructions for implementing a method for selectively returning data of a file from a remote storage medium to a local storage medium in response to an access request for the data made after the data has been migrated from the local storage medium to the remote storage medium , said computer readable medium (storing data) comprising : means for storing the data of the file on the remote storage medium after the data has been migrated from the local storage medium to the remote storage medium ;
means for storing attributes of the file at the local storage medium ;
means for receiving an access request that involves the file ;
means for determining whether a response to the access request can be provided using only the attributes of the file stored at the local storage medium ;
means for responding to the access request without recalling the data from the remote storage medium if it has been determined that the response can be provided using only the attributes stored at the local storage medium ;
and means for responding to the access request by recalling the data from the remote storage medium if it has been determined that the response cannot be provided using only the attributes stored at the local storage medium .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor (data store) coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US6269382B1
CLAIM 27
. A computer-readable medium having computer executable instructions for implementing , in a system having access to both a local and a remote storage medium , wherein migration policies are used to migrate data from the local storage medium to the remote storage medium , a method of pre-migrating the data prior to fully migrating the data in a manner such that the data can be rapidly deleted from the local storage medium and migrated when migration policies associated with the data are satisfied , said computer readable medium comprising : means for obtaining parameters that specify migration policies under which data is to be migrated from the local storage medium to the remote storage medium such that , when the data is migrated , the data exists at the remote storage medium and does not exist at the local storage medium ;
means for identifying files , including a first file , that are stored on a local storage medium and that have not yet satisfied migration policies and are not yet eligible for migration from the local storage medium to the remote storage medium ;
means for pre-migrating data store (storage processor) d in said first file to said remote storage medium even though the migration policies have not yet been satisfied , so that the pre-migrated data exists on said local storage medium and also exists on the remote storage medium prior to said first file satisfying the migration policies ;
means for receiving a request to write incoming data to the local storage medium prior to said first file satisfying the migration policies , the local storage medium not having sufficient free space to store the incoming data without deleting data already stored at the local storage medium ;
means for determining whether a second file that (1) contains other pre-migrated data , and (2) has satisfied the migration policies , exists on the local storage medium ;
and means for performing the steps of : if said second file exists , migrating said second file from the local storage medium to the remote storage medium so as to create said sufficient free space ;
and if said second file does not exist , migrating said first file from the local storage medium to said remote storage medium to create said sufficient free space notwithstanding said first file not yet satisfying the migration policies .

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (data store) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
US6269382B1
CLAIM 27
. A computer-readable medium having computer executable instructions for implementing , in a system having access to both a local and a remote storage medium , wherein migration policies are used to migrate data from the local storage medium to the remote storage medium , a method of pre-migrating the data prior to fully migrating the data in a manner such that the data can be rapidly deleted from the local storage medium and migrated when migration policies associated with the data are satisfied , said computer readable medium comprising : means for obtaining parameters that specify migration policies under which data is to be migrated from the local storage medium to the remote storage medium such that , when the data is migrated , the data exists at the remote storage medium and does not exist at the local storage medium ;
means for identifying files , including a first file , that are stored on a local storage medium and that have not yet satisfied migration policies and are not yet eligible for migration from the local storage medium to the remote storage medium ;
means for pre-migrating data store (storage processor) d in said first file to said remote storage medium even though the migration policies have not yet been satisfied , so that the pre-migrated data exists on said local storage medium and also exists on the remote storage medium prior to said first file satisfying the migration policies ;
means for receiving a request to write incoming data to the local storage medium prior to said first file satisfying the migration policies , the local storage medium not having sufficient free space to store the incoming data without deleting data already stored at the local storage medium ;
means for determining whether a second file that (1) contains other pre-migrated data , and (2) has satisfied the migration policies , exists on the local storage medium ;
and means for performing the steps of : if said second file exists , migrating said second file from the local storage medium to the remote storage medium so as to create said sufficient free space ;
and if said second file does not exist , migrating said first file from the local storage medium to said remote storage medium to create said sufficient free space notwithstanding said first file not yet satisfying the migration policies .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor (data store) returns a predetermined data string .
US6269382B1
CLAIM 27
. A computer-readable medium having computer executable instructions for implementing , in a system having access to both a local and a remote storage medium , wherein migration policies are used to migrate data from the local storage medium to the remote storage medium , a method of pre-migrating the data prior to fully migrating the data in a manner such that the data can be rapidly deleted from the local storage medium and migrated when migration policies associated with the data are satisfied , said computer readable medium comprising : means for obtaining parameters that specify migration policies under which data is to be migrated from the local storage medium to the remote storage medium such that , when the data is migrated , the data exists at the remote storage medium and does not exist at the local storage medium ;
means for identifying files , including a first file , that are stored on a local storage medium and that have not yet satisfied migration policies and are not yet eligible for migration from the local storage medium to the remote storage medium ;
means for pre-migrating data store (storage processor) d in said first file to said remote storage medium even though the migration policies have not yet been satisfied , so that the pre-migrated data exists on said local storage medium and also exists on the remote storage medium prior to said first file satisfying the migration policies ;
means for receiving a request to write incoming data to the local storage medium prior to said first file satisfying the migration policies , the local storage medium not having sufficient free space to store the incoming data without deleting data already stored at the local storage medium ;
means for determining whether a second file that (1) contains other pre-migrated data , and (2) has satisfied the migration policies , exists on the local storage medium ;
and means for performing the steps of : if said second file exists , migrating said second file from the local storage medium to the remote storage medium so as to create said sufficient free space ;
and if said second file does not exist , migrating said first file from the local storage medium to said remote storage medium to create said sufficient free space notwithstanding said first file not yet satisfying the migration policies .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
JP2000076117A

Filed: 1998-08-31     Issued: 2000-03-14

電子機器及びその制御方法及び記憶媒体

(Original Assignee) Kano Densan Hongkong Yugenkoshi; 佳能電産香港有限公司     

Hiroshi Nishikawa, 寛 西川
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system , including storing data (タイミング) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
JP2000076117A
CLAIM 1
【請求項1】 フラッシュメモリを有する電気機器であ って、 フラッシュメモリの消去単位のセクタを複数のブロック に分割し、個々のブロックが自身のデータが有効か無効 かを示すコード情報を格納する領域を有し、前記ブロッ クを1つ或いは複数個で1つのファイルを管理するた め、前記ファイルの管理情報を有する管理手段と、 前記フラッシュメモリに格納されているファイルを消去 要求があったとき、当該ファイルを構成する各ブロック 中の前記領域に無効コードを書き込む消去手段と、 所定のタイミング (storing data) になったとき、セクタ単位に、当該セ クタ中の無効コードが格納されたブロック群を除く有効 ブロック群を、当該有効ブロックの格納アドレスの相対 位置を保持したまま所定の揮発性メモリに転送する転送 手段と、 該転送手段による転送を行った後、前記フラッシュメモ リにおける注目セクタを消去する消去手段と、 消去したセクタ内に、前記不揮発性メモリに転送した有 効ブロック群を、当該有効ブロックの格納アドレスの相 対位置を保持したまま書き込む書き込み手段とを有する ことを特徴とする電子機器。

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (タイミング) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
JP2000076117A
CLAIM 1
【請求項1】 フラッシュメモリを有する電気機器であ って、 フラッシュメモリの消去単位のセクタを複数のブロック に分割し、個々のブロックが自身のデータが有効か無効 かを示すコード情報を格納する領域を有し、前記ブロッ クを1つ或いは複数個で1つのファイルを管理するた め、前記ファイルの管理情報を有する管理手段と、 前記フラッシュメモリに格納されているファイルを消去 要求があったとき、当該ファイルを構成する各ブロック 中の前記領域に無効コードを書き込む消去手段と、 所定のタイミング (storing data) になったとき、セクタ単位に、当該セ クタ中の無効コードが格納されたブロック群を除く有効 ブロック群を、当該有効ブロックの格納アドレスの相対 位置を保持したまま所定の揮発性メモリに転送する転送 手段と、 該転送手段による転送を行った後、前記フラッシュメモ リにおける注目セクタを消去する消去手段と、 消去したセクタ内に、前記不揮発性メモリに転送した有 効ブロック群を、当該有効ブロックの格納アドレスの相 対位置を保持したまま書き込む書き込み手段とを有する ことを特徴とする電子機器。

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor coupled to the storage interface ;

a flash memory device (アドレス) coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
JP2000076117A
CLAIM 1
【請求項1】 フラッシュメモリを有する電気機器であ って、 フラッシュメモリの消去単位のセクタを複数のブロック に分割し、個々のブロックが自身のデータが有効か無効 かを示すコード情報を格納する領域を有し、前記ブロッ クを1つ或いは複数個で1つのファイルを管理するた め、前記ファイルの管理情報を有する管理手段と、 前記フラッシュメモリに格納されているファイルを消去 要求があったとき、当該ファイルを構成する各ブロック 中の前記領域に無効コードを書き込む消去手段と、 所定のタイミングになったとき、セクタ単位に、当該セ クタ中の無効コードが格納されたブロック群を除く有効 ブロック群を、当該有効ブロックの格納アドレス (flash memory device) の相対 位置を保持したまま所定の揮発性メモリに転送する転送 手段と、 該転送手段による転送を行った後、前記フラッシュメモ リにおける注目セクタを消去する消去手段と、 消去したセクタ内に、前記不揮発性メモリに転送した有 効ブロック群を、当該有効ブロックの格納アドレスの相 対位置を保持したまま書き込む書き込み手段とを有する ことを特徴とする電子機器。

US9632727B2
CLAIM 13
. The system of claim 12 , wherein the logical-to-physical translation layer is stored in the flash memory device (アドレス) .
JP2000076117A
CLAIM 1
【請求項1】 フラッシュメモリを有する電気機器であ って、 フラッシュメモリの消去単位のセクタを複数のブロック に分割し、個々のブロックが自身のデータが有効か無効 かを示すコード情報を格納する領域を有し、前記ブロッ クを1つ或いは複数個で1つのファイルを管理するた め、前記ファイルの管理情報を有する管理手段と、 前記フラッシュメモリに格納されているファイルを消去 要求があったとき、当該ファイルを構成する各ブロック 中の前記領域に無効コードを書き込む消去手段と、 所定のタイミングになったとき、セクタ単位に、当該セ クタ中の無効コードが格納されたブロック群を除く有効 ブロック群を、当該有効ブロックの格納アドレス (flash memory device) の相対 位置を保持したまま所定の揮発性メモリに転送する転送 手段と、 該転送手段による転送を行った後、前記フラッシュメモ リにおける注目セクタを消去する消去手段と、 消去したセクタ内に、前記不揮発性メモリに転送した有 効ブロック群を、当該有効ブロックの格納アドレスの相 対位置を保持したまま書き込む書き込み手段とを有する ことを特徴とする電子機器。

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one (する情報) or more logical addresses included in the empty-block directive command , the storage processor returns a predetermined data string .
JP2000076117A
CLAIM 2
【請求項2】 前記管理情報には、ファイルを構成する 先頭ブロックが格納されているセクタを特定する情報 (read request specifying one) 、 該セクタ内の前記先頭ブロックの格納位置を示すアドレ ス情報が含まれ、 前記ブロックには、更に、後続するブロックの存在の有 無及びその存在するセクタを特定する情報とセクタ内の 格納位置を示すアドレス情報、及び、実データが含まれ ることを特徴とする請求項第1項に記載の電子機器。




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US6353878B1

Filed: 1998-08-13     Issued: 2002-03-05

Remote control of backup media in a secondary storage subsystem through access to a primary storage subsystem

(Original Assignee) EMC Corp     (Current Assignee) EMC Corp

Scott R. Dunham
US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA (first host) bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
US6353878B1
CLAIM 11
. A method of operating a data storage system including a primary data storage subsystem and a secondary data storage subsystem linked to the primary data storage subsystem for transfer of backup data between the primary data storage subsystem and the secondary data storage subsystem , the primary data storage subsystem including a cached disk storage subsystem , the secondary data storage subsystem including a cached disk storage subsystem and a tape library unit for storage of the backup data , said method comprising : a) the secondary data storage subsystem maintaining a directory of versions of backup data stored in the tape library unit ;
b) the primary data storage subsystem receiving from a first host (external SATA) processor a backup media remote control request ;
the primary data storage subsystem sending to the secondary data storage subsystem a backup media remote control command corresponding to the backup media remote control request ;
the secondary data storage subsystem receiving the backup media remote control command , and the tape library unit executing the backup media remote control command and returning an acknowledgment to the primary data storage subsystem , and the primary data storage subsystem returning the acknowledgment to the first host processor ;
and c) the primary data storage subsystem receiving from a second host processor a backup request for backup of specified data in the primary data storage , and in response the primary data storage subsystem transmitting at least one command to the secondary data storage subsystem for storing a backup version of the specified data in tape storage in the tape library unit without requiring the second host processor to issue backup media remote control requests .

US6353878B1
CLAIM 16
. A data storage system comprising , in combination : a primary data storage subsystem including primary data storage and a storage controller coupled to the primary data storage for controlling access to the primary data storage , the storage controller having at least one data port (external SATA bus interface) for coupling to at least one host processor for receiving data access commands from the host processor for access to the primary data storage ;
the primary data storage including a primary cached disk storage subsystem , and a secondary data storage subsystem linked to the storage controller of the primary data storage subsystem for transfer of backup data between the primary data storage subsystem and the secondary data storage subsystem , the secondary data storage subsystem including a tape library unit for storage of the backup data , and a secondary cached disk storage subsystem and at least one processor coupled to the tape library unit for buffering backup data transmitted between the primary data storage subsystem and the tape library unit and maintaining a directory of versions of backup data stored in the tape library unit ;
wherein the storage controller of the primary data storage subsystem is programmed for receiving from the host processor a backup media remote control request , and sending to the secondary data storage subsystem a backup media remote control command corresponding to the backup media remote control request for execution of the backup media remote control command by the tape library unit .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client (access request) that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
US6353878B1
CLAIM 29
. A machine readable program storage device containing a program executable by a storage controller of a data storage subsystem having primary data storage , the storage controller having at least one data port for receiving storage access request (storage client, storage interface to accept requests to perform storage operations) s from at least one host processor , the storage controller being linked to a tape library unit for transfer of backup data between the storage controller and the tape library unit ;
wherein the program is executable by the storage controller for receiving from the host processors storage access requests and in response controlling access of the host processors to the primary data storage ;
wherein the program is executable by the storage controller for receiving from the host processors backup media remote control requests , and sending to the tape library unit backup media remote control commands corresponding to the backup media remote control requests for execution of the backup media remote control commands by the tape library unit , and for returning acknowledgments of the backup media remote control commands from the tape library unit to the host processors ;
and wherein the program is executable by the storage controller for receiving from the host processors backup requests for backup of specified data in the primary data storage , and in response for transmitting commands to the tape library unit for storing backup versions of the specified data in tape storage in the tape library unit without requiring the host processors to issue backup media remote control requests for storing the backup versions of the specified data in tape storage of the tape library unit .

US9632727B2
CLAIM 8
. The system of claim 7 , further comprising means for providing a storage interface to accept requests to perform storage operations (access request) on the solid-state storage medium in reference to the logical blocks and to accept the message identifying the logical block that is not being used to reference data stored on the solid-state storage medium .
US6353878B1
CLAIM 29
. A machine readable program storage device containing a program executable by a storage controller of a data storage subsystem having primary data storage , the storage controller having at least one data port for receiving storage access request (storage client, storage interface to accept requests to perform storage operations) s from at least one host processor , the storage controller being linked to a tape library unit for transfer of backup data between the storage controller and the tape library unit ;
wherein the program is executable by the storage controller for receiving from the host processors storage access requests and in response controlling access of the host processors to the primary data storage ;
wherein the program is executable by the storage controller for receiving from the host processors backup media remote control requests , and sending to the tape library unit backup media remote control commands corresponding to the backup media remote control requests for execution of the backup media remote control commands by the tape library unit , and for returning acknowledgments of the backup media remote control commands from the tape library unit to the host processors ;
and wherein the program is executable by the storage controller for receiving from the host processors backup requests for backup of specified data in the primary data storage , and in response for transmitting commands to the tape library unit for storing backup versions of the specified data in tape storage in the tape library unit without requiring the host processors to issue backup media remote control requests for storing the backup versions of the specified data in tape storage of the tape library unit .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client (access request) ;

a storage processor (data store) coupled to the storage interface ;

a flash memory device (storage capacity) coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US6353878B1
CLAIM 1
. A method of operating a data storage system including a primary data storage subsystem and a secondary data storage subsystem linked to the primary data storage subsystem for transfer of backup data between the primary data storage subsystem and the secondary data storage subsystem , the primary data storage subsystem including a cached disk storage subsystem , the secondary data storage subsystem including a cached disk storage subsystem and a tape library unit for storage of the backup data , said method comprising : a) the secondary data storage subsystem maintaining a directory of versions of backup data store (storage processor) d in the tape library unit ;
b) the primary data storage subsystem receiving from a host processor a backup media remote control request ;
c) the primary data storage subsystem sending to the secondary data storage subsystem a backup media remote control command corresponding to the backup media remote control request ;
and d) the secondary data storage subsystem receiving the backup media remote control command , and the tape library unit executing the backup media remote control command .

US6353878B1
CLAIM 7
. The method as claimed in claim 1 , which includes the host processor sending to the primary data storage subsystem a backup media remote control request for status information about a read/write station , and in response the tape library unit identifying a tape mounted in the read/write station , and reporting storage capacity (flash memory device) of the tape , block size of data blocks stored on the tape , a current block number , and an amount of data storage space remaining on the tape .

US6353878B1
CLAIM 29
. A machine readable program storage device containing a program executable by a storage controller of a data storage subsystem having primary data storage , the storage controller having at least one data port for receiving storage access request (storage client, storage interface to accept requests to perform storage operations) s from at least one host processor , the storage controller being linked to a tape library unit for transfer of backup data between the storage controller and the tape library unit ;
wherein the program is executable by the storage controller for receiving from the host processors storage access requests and in response controlling access of the host processors to the primary data storage ;
wherein the program is executable by the storage controller for receiving from the host processors backup media remote control requests , and sending to the tape library unit backup media remote control commands corresponding to the backup media remote control requests for execution of the backup media remote control commands by the tape library unit , and for returning acknowledgments of the backup media remote control commands from the tape library unit to the host processors ;
and wherein the program is executable by the storage controller for receiving from the host processors backup requests for backup of specified data in the primary data storage , and in response for transmitting commands to the tape library unit for storing backup versions of the specified data in tape storage in the tape library unit without requiring the host processors to issue backup media remote control requests for storing the backup versions of the specified data in tape storage of the tape library unit .

US9632727B2
CLAIM 13
. The system of claim 12 , wherein the logical-to-physical translation layer is stored in the flash memory device (storage capacity) .
US6353878B1
CLAIM 7
. The method as claimed in claim 1 , which includes the host processor sending to the primary data storage subsystem a backup media remote control request for status information about a read/write station , and in response the tape library unit identifying a tape mounted in the read/write station , and reporting storage capacity (flash memory device) of the tape , block size of data blocks stored on the tape , a current block number , and an amount of data storage space remaining on the tape .

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (data store) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
US6353878B1
CLAIM 1
. A method of operating a data storage system including a primary data storage subsystem and a secondary data storage subsystem linked to the primary data storage subsystem for transfer of backup data between the primary data storage subsystem and the secondary data storage subsystem , the primary data storage subsystem including a cached disk storage subsystem , the secondary data storage subsystem including a cached disk storage subsystem and a tape library unit for storage of the backup data , said method comprising : a) the secondary data storage subsystem maintaining a directory of versions of backup data store (storage processor) d in the tape library unit ;
b) the primary data storage subsystem receiving from a host processor a backup media remote control request ;
c) the primary data storage subsystem sending to the secondary data storage subsystem a backup media remote control command corresponding to the backup media remote control request ;
and d) the secondary data storage subsystem receiving the backup media remote control command , and the tape library unit executing the backup media remote control command .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor (data store) returns a predetermined data string .
US6353878B1
CLAIM 1
. A method of operating a data storage system including a primary data storage subsystem and a secondary data storage subsystem linked to the primary data storage subsystem for transfer of backup data between the primary data storage subsystem and the secondary data storage subsystem , the primary data storage subsystem including a cached disk storage subsystem , the secondary data storage subsystem including a cached disk storage subsystem and a tape library unit for storage of the backup data , said method comprising : a) the secondary data storage subsystem maintaining a directory of versions of backup data store (storage processor) d in the tape library unit ;
b) the primary data storage subsystem receiving from a host processor a backup media remote control request ;
c) the primary data storage subsystem sending to the secondary data storage subsystem a backup media remote control command corresponding to the backup media remote control request ;
and d) the secondary data storage subsystem receiving the backup media remote control command , and the tape library unit executing the backup media remote control command .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US6185654B1

Filed: 1998-07-17     Issued: 2001-02-06

Phantom resource memory address mapping system

(Original Assignee) Compaq Computer Corp     (Current Assignee) Hewlett Packard Enterprise Development LP

Stephen Richard Van Doren
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system , including storing data (address translation) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US6185654B1
CLAIM 19
. The memory address mapping system of claim 18 wherein the memory access circuitry further comprises stacked address translation (storing data) logic operating in parallel with the memory resource access , the stacked address translation logic isolating the actual memory resource referenced by the memory address request .

US9632727B2
CLAIM 2
. The apparatus of claim 1 , wherein the indexer assigns logical addresses to physical addresses by use of index entries , and wherein the indexer removes an index entry (interleave units) corresponding to the identified logical address in response to the message .
US6185654B1
CLAIM 11
. A memory address mapping system for reducing latency incurred when accessing data stored on memory resources of a data processing system in response to a memory reference request issued by a processor , the address mapping system comprising : memory access circuitry including a translation stage coupled to an arbitration stage , the translation stage mapping the memory reference request to an arbitration request directed to a fixed interleave configuration of logical interleave units (index entry) .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (address translation) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
US6185654B1
CLAIM 19
. The memory address mapping system of claim 18 wherein the memory access circuitry further comprises stacked address translation (storing data) logic operating in parallel with the memory resource access , the stacked address translation logic isolating the actual memory resource referenced by the memory address request .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor (data store) coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US6185654B1
CLAIM 1
. An address mapping system for reducing latency incurred when accessing data store (storage processor) d on memory resources of a data processing system in response to a memory reference request issued by a processor , the memory resources configured as one of a stacked-hybrid and a fully-interleaved hierarchy of memory resources , the address mapping system comprising : memory access circuitry having a topology that comprises interleaved-based translation circuitry and stacked-based translation circuitry , the topology further comprising a primary memory access path that includes the interleave-based translation circuitry .

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (data store) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
US6185654B1
CLAIM 1
. An address mapping system for reducing latency incurred when accessing data store (storage processor) d on memory resources of a data processing system in response to a memory reference request issued by a processor , the memory resources configured as one of a stacked-hybrid and a fully-interleaved hierarchy of memory resources , the address mapping system comprising : memory access circuitry having a topology that comprises interleaved-based translation circuitry and stacked-based translation circuitry , the topology further comprising a primary memory access path that includes the interleave-based translation circuitry .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor (data store) returns a predetermined data string .
US6185654B1
CLAIM 1
. An address mapping system for reducing latency incurred when accessing data store (storage processor) d on memory resources of a data processing system in response to a memory reference request issued by a processor , the memory resources configured as one of a stacked-hybrid and a fully-interleaved hierarchy of memory resources , the address mapping system comprising : memory access circuitry having a topology that comprises interleaved-based translation circuitry and stacked-based translation circuitry , the topology further comprising a primary memory access path that includes the interleave-based translation circuitry .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
JP2000020490A

Filed: 1998-07-01     Issued: 2000-01-21

遠隔手続き呼出し機構またはオブジェクトリクエストブローカ機構を有する計算機、データ転送方法、および転送方法記憶媒体

(Original Assignee) Fujitsu Ltd; 富士通株式会社     

Yuji Imai, 祐二 今井
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium (メッセー) in response to requests from a computer system (行うこと) , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
JP2000020490A
CLAIM 2
【請求項2】 前記遠隔直接データ転送手段が、前記ネ ットワークを構成するシステムエリアネットワーク(S AN)を物理通信路としてデータ転送を行うこと (computer system) を特徴 とする請求項1記載の遠隔手続き呼出し機構、またはオ ブジェクトリクエストブローカ機構を有する計算機。

JP2000020490A
CLAIM 4
【請求項4】 前記遠隔直接データ転送手段が、前記自 計算機の物理メモリ領域のデータを含むメッセー (state storage medium) ジに自 計算機側でのデータ表現形式を添付して転送することを 特徴とする請求項3記載の遠隔手続き呼出し機構、また はオブジェクトリクエストブローカ機構を有する計算 機。

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system (行うこと) , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (可能記憶) (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
JP2000020490A
CLAIM 2
【請求項2】 前記遠隔直接データ転送手段が、前記ネ ットワークを構成するシステムエリアネットワーク(S AN)を物理通信路としてデータ転送を行うこと (computer system) を特徴 とする請求項1記載の遠隔手続き呼出し機構、またはオ ブジェクトリクエストブローカ機構を有する計算機。

JP2000020490A
CLAIM 28
【請求項28】 分散コンピューティング環境における 遠隔手続き呼出し(RPC)機構、またはオブジェクト リクエストブローカ(ORB)機構を有する計算機にお いて使用される記憶媒体であって、 自計算機の物理メモリ領域上のデータを、ネットワーク を介して通信相手側計算機の物理メモリ領域に向けて直 接に転送させる機能を備えるプログラムを格納した計算 機読出し可能記憶 (Integrated Drive Electronics) 媒体。




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US5969986A

Filed: 1998-06-23     Issued: 1999-10-19

High-bandwidth read and write architectures for non-volatile memories

(Original Assignee) INVOX Technology     (Current Assignee) INNOVATIVE MEMORY SYSTEMS Inc

Sau C. Wong, Hock C. So
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium (write operation) in response to requests from a computer system , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US5969986A
CLAIM 1
. A memory comprising : a plurality of pipelines , wherein each pipeline comprises : an array of non-volatile memory cells ;
a first sample-and-hold circuit ;
a selection circuit that during a write operation (solid state storage medium) selects as a row line voltage , from a set of voltages including a first voltage from the first sample-and-hold circuit ;
a row decoder coupled to the array and the selection circuit , wherein the row decoder selects a row line and applies the row line voltage from the selection circuit to the selected row line ;
and a voltage generator that generates a first write signal having a voltage that depends on a data signal input to the voltage generator , wherein each first sample-and-hold circuit in the pipelines is coupled to sample the first write signal .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request (first write) specifying one or more logical addresses included in the empty-block directive command , the storage processor returns a predetermined data string (output signal) .
US5969986A
CLAIM 1
. A memory comprising : a plurality of pipelines , wherein each pipeline comprises : an array of non-volatile memory cells ;
a first sample-and-hold circuit ;
a selection circuit that during a write operation selects as a row line voltage , from a set of voltages including a first voltage from the first sample-and-hold circuit ;
a row decoder coupled to the array and the selection circuit , wherein the row decoder selects a row line and applies the row line voltage from the selection circuit to the selected row line ;
and a voltage generator that generates a first write (read request, read request specifying one) signal having a voltage that depends on a data signal input to the voltage generator , wherein each first sample-and-hold circuit in the pipelines is coupled to sample the first write signal .

US5969986A
CLAIM 25
. The memory of claim 24 , wherein : the multiplexer provides an output signal (data string) from the first sample-and-hold circuit when the selection circuit selects that the sense amplifier clocks the second sample-and-hold circuit samples ;
and the multiplexer provides an output signal from the second sample-and-hold circuit when the selection circuit selects that the sense amplifier clocks the first sample-and-hold circuit samples .

US9632727B2
CLAIM 16
. The system of claim 15 , wherein data bits of the predetermined data string (output signal) have a uniform logic level (hold circuits) .
US5969986A
CLAIM 2
. The memory of claim 1 , further comprising a timing circuit coupled to the first sample-and-hold circuits (uniform logic level) in the pipelines , wherein the timing circuit controls when each first sample-and-hold circuit samples the first write signal .

US5969986A
CLAIM 25
. The memory of claim 24 , wherein : the multiplexer provides an output signal (data string) from the first sample-and-hold circuit when the selection circuit selects that the sense amplifier clocks the second sample-and-hold circuit samples ;
and the multiplexer provides an output signal from the second sample-and-hold circuit when the selection circuit selects that the sense amplifier clocks the first sample-and-hold circuit samples .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US6209003B1

Filed: 1998-04-15     Issued: 2001-03-27

Garbage collection in an object cache

(Original Assignee) Inktomi Corp     (Current Assignee) Altaba Inc

Peter Mattis, John Plevyak, Matthew Haines, Adam Beguelin, Brian Totty, David Gourley
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data (main memory) pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US6209003B1
CLAIM 2
. The method recited in claim 1 , further comprising the steps of : (E) storing each of the arenas in one of a plurality of pools on the storage device ;
(F) storing a minimum occupancy value and a maximum occupancy value in a main memory (store data) ;
(G) for each of the pools , sensing when such pool is storing an amount of data greater than the minimum occupancy value , and executing steps (A) through (D) for each arena within such pool .

US9632727B2
CLAIM 5
. The apparatus of claim 1 , further comprising a garbage collector (garbage collection) configured to designate that the physical address previously assigned to the identified logical address comprises data suitable for removal from the solid-state storage medium in response to the message .
US6209003B1
CLAIM 1
. A method of garbage collection (garbage collector) in a cache of a plurality of fragments of an information object , wherein each of the fragments is stored in one of a plurality of arenas on a storage device , the method comprising the steps of : (A) selecting a selected arena from among the plurality of arenas based upon a first set of selection factors ;
(B) for each fragment within the selected arena , determining whether to delete such fragment and determining whether to retain such fragment based upon a second set of selection factors ;
(C) when such fragment is determined to be deleted , marking such fragment as deleted ;
(D) when such fragment is determined to be retained , storing such fragment in a second arena among the plurality of arenas .

US9632727B2
CLAIM 8
. The system of claim 7 , further comprising means for providing a storage interface (computer apparatus) to accept requests to perform storage operations on the solid-state storage medium in reference to the logical blocks and to accept the message identifying the logical block that is not being used to reference data stored on the solid-state storage medium .
US6209003B1
CLAIM 19
. A computer apparatus (storage interface) comprising one or more processors and a memory storing one or more sequences of instructions for garbage collection in a cache of a plurality of fragments of an information object , wherein each of the fragments is stored in one of a plurality of arenas on a storage device , wherein execution of the one or more sequences of instructions by the one or more processors causes the one or more processors to perform the steps of : (A) selecting a selected arena from among the plurality of arenas based upon a first set of selection factors ;
(B) for each fragment within the selected arena , determining whether to delete such fragment and determining whether to retain such fragment based upon a second set of selection factors ;
(C) when such fragment is determined to be deleted , marking such fragment as deleted ;
(D) when such fragment is determined to be retained , storing such fragment in a second arena among the plurality of arenas .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface (computer apparatus) configured to communicate with a storage client ;

a storage processor coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US6209003B1
CLAIM 19
. A computer apparatus (storage interface) comprising one or more processors and a memory storing one or more sequences of instructions for garbage collection in a cache of a plurality of fragments of an information object , wherein each of the fragments is stored in one of a plurality of arenas on a storage device , wherein execution of the one or more sequences of instructions by the one or more processors causes the one or more processors to perform the steps of : (A) selecting a selected arena from among the plurality of arenas based upon a first set of selection factors ;
(B) for each fragment within the selected arena , determining whether to delete such fragment and determining whether to retain such fragment based upon a second set of selection factors ;
(C) when such fragment is determined to be deleted , marking such fragment as deleted ;
(D) when such fragment is determined to be retained , storing such fragment in a second arena among the plurality of arenas .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request (n information) specifying one or more logical addresses included in the empty-block directive command , the storage processor returns a predetermined data string .
US6209003B1
CLAIM 1
. A method of garbage collection in a cache of a plurality of fragments of an information (read request) object , wherein each of the fragments is stored in one of a plurality of arenas on a storage device , the method comprising the steps of : (A) selecting a selected arena from among the plurality of arenas based upon a first set of selection factors ;
(B) for each fragment within the selected arena , determining whether to delete such fragment and determining whether to retain such fragment based upon a second set of selection factors ;
(C) when such fragment is determined to be deleted , marking such fragment as deleted ;
(D) when such fragment is determined to be retained , storing such fragment in a second arena among the plurality of arenas .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US6374336B1

Filed: 1998-04-03     Issued: 2002-04-16

Computer system and process for transferring multiple high bandwidth streams of data between multiple storage units and multiple applications in a scalable and reliable manner

(Original Assignee) Avid Technology Inc     (Current Assignee) CERBERUS BUSINESS FINANCE AS COLLATERAL AGENT LLC

Eric C. Peters, Stanley Rabinowitz, Herbert R. Jacobs, Richard Baker Gillett, Jr., Peter J. Fasciano
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system (waiting time) , the message indicating that the identified logical address is erased .
US6374336B1
CLAIM 2
. A file system for a computer , enabling the computer to access remote independent storage units over a computer network in response to a request , from an application executed on the computer , to read data stored in a file on the storage units , wherein a file includes segments of the data and corresponding redundancy information for each segment , and wherein , for each file , each segment of the data is stored on a randomly or pseudorandomly selected one of the storage units , and wherein , for each segment of the data , the corresponding redundancy information is stored on a randomly or pseudorandomly selected one of the storage units , the file system comprising : means , responsive to the request to read data from a file , for selecting , for each segment of the requested data , one of the storage units on which data representing the segment is stored ;
means for reading each segment of the requested data from the selected storage unit for the segment ;
means for serializing the segments read from the selected storage units ;
and means for providing the serialized data to the application ;
wherein the means for reading each segment comprises means for scheduling the transfer of the data from the selected storage unit such that the storage unit efficiently transfers data , and includes : in the file system : means for requesting transfer of the data from the selected storage unit , indicating a waiting time (host operating system) ;
means for requesting the data from another storage unit if the selected storage unit rejects the request to transfer the data ;
and in the storage unit : means for rejecting a request to transfer data if the data is not available to be transferred from the storage unit by the indicated waiting time ;
and means for transferring the data if the selected storage unit is able to transfer the data within the waiting time .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor (data store) coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US6374336B1
CLAIM 1
. A file system for a computer , enabling the computer to access remote independent storage units over a computer network in response to a request , from an application executed on the computer , to read data store (storage processor) d in a file on the storage units , wherein a file includes segments of the data and corresponding redundancy information for each segment , and wherein , for each file , each segment of the data is stored on a randomly or pseudorandomly selected one of the storage units , and wherein , for each segment of the data , the corresponding redundancy information is stored on a randomly or pseudorandomly selected one of the storage units , the file system comprising : means , responsive to the request to read data from a file , for selecting , for each segment of the requested data , one of the storage units on which data representing the segment is stored ;
means for reading each segment of the requested data from the selected storage unit for the segment ;
means for serializing the segments read from the selected storage units ;
and means for providing the serialized data to the application ;
wherein the means for selecting includes : in the file system : means for requesting data from one of the storage units , indicating an estimated time ;
means for requesting data from another of the storage units , indicating an estimated time , if the first storage unit rejects the request ;
and means for requesting the data from the first storage unit if the second storage unit rejects the request ;
and in each storage unit : means for rejecting a request for data if the request cannot be serviced by the storage unit within the estimated time ;
and means for accepting a request for data if the request can be serviced by the storage unit within the estimated time .

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (data store) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
US6374336B1
CLAIM 1
. A file system for a computer , enabling the computer to access remote independent storage units over a computer network in response to a request , from an application executed on the computer , to read data store (storage processor) d in a file on the storage units , wherein a file includes segments of the data and corresponding redundancy information for each segment , and wherein , for each file , each segment of the data is stored on a randomly or pseudorandomly selected one of the storage units , and wherein , for each segment of the data , the corresponding redundancy information is stored on a randomly or pseudorandomly selected one of the storage units , the file system comprising : means , responsive to the request to read data from a file , for selecting , for each segment of the requested data , one of the storage units on which data representing the segment is stored ;
means for reading each segment of the requested data from the selected storage unit for the segment ;
means for serializing the segments read from the selected storage units ;
and means for providing the serialized data to the application ;
wherein the means for selecting includes : in the file system : means for requesting data from one of the storage units , indicating an estimated time ;
means for requesting data from another of the storage units , indicating an estimated time , if the first storage unit rejects the request ;
and means for requesting the data from the first storage unit if the second storage unit rejects the request ;
and in each storage unit : means for rejecting a request for data if the request cannot be serviced by the storage unit within the estimated time ;
and means for accepting a request for data if the request can be serviced by the storage unit within the estimated time .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor (data store) returns a predetermined data string .
US6374336B1
CLAIM 1
. A file system for a computer , enabling the computer to access remote independent storage units over a computer network in response to a request , from an application executed on the computer , to read data store (storage processor) d in a file on the storage units , wherein a file includes segments of the data and corresponding redundancy information for each segment , and wherein , for each file , each segment of the data is stored on a randomly or pseudorandomly selected one of the storage units , and wherein , for each segment of the data , the corresponding redundancy information is stored on a randomly or pseudorandomly selected one of the storage units , the file system comprising : means , responsive to the request to read data from a file , for selecting , for each segment of the requested data , one of the storage units on which data representing the segment is stored ;
means for reading each segment of the requested data from the selected storage unit for the segment ;
means for serializing the segments read from the selected storage units ;
and means for providing the serialized data to the application ;
wherein the means for selecting includes : in the file system : means for requesting data from one of the storage units , indicating an estimated time ;
means for requesting data from another of the storage units , indicating an estimated time , if the first storage unit rejects the request ;
and means for requesting the data from the first storage unit if the second storage unit rejects the request ;
and in each storage unit : means for rejecting a request for data if the request cannot be serviced by the storage unit within the estimated time ;
and means for accepting a request for data if the request can be serviced by the storage unit within the estimated time .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US6138125A

Filed: 1998-03-31     Issued: 2000-10-24

Block coding method and system for failure recovery in disk arrays

(Original Assignee) LSI Corp     (Current Assignee) Avago Technologies International Sales Pte Ltd

Robert A. DeMoss
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium (write operation) in response to requests from a computer system , including storing data (storing data) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US6138125A
CLAIM 18
. An apparatus for storing data (storing data) in an array storage system having n storage devices where (n+1) is a prime number , said apparatus comprising : a matrix of dimension n×n data elements wherein said matrix comprises : (n 2 -2n) data elements ;
and 2n parity elements each corresponding to an associated set of n-2 elements of said data elements such that each of said data elements is associated with two of said parity elements ;
and means for storing said matrix on said storage devices such that each column of said matrix is written to a corresponding one of said storage devices .

US6138125A
CLAIM 34
. The apparatus of claim 28 wherein a large write operation (solid state storage medium) that updates each of said data blocks calculates said parity blocks with 2n(n-3) XOR calculations .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (storing data) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
US6138125A
CLAIM 18
. An apparatus for storing data (storing data) in an array storage system having n storage devices where (n+1) is a prime number , said apparatus comprising : a matrix of dimension n×n data elements wherein said matrix comprises : (n 2 -2n) data elements ;
and 2n parity elements each corresponding to an associated set of n-2 elements of said data elements such that each of said data elements is associated with two of said parity elements ;
and means for storing said matrix on said storage devices such that each column of said matrix is written to a corresponding one of said storage devices .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor coupled to the storage interface ;

a flash memory device (storage subsystem, storage capacity) coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US6138125A
CLAIM 1
. A method for encoding a data block onto an array of n data storage devices , where (n+1) is a prime number , and wherein said data block has a maximum size equal to the storage capacity (flash memory device) of (n-2) of the data storage devices , said method comprising the steps of : (a) creating a matrix of dimensions (n×n) ;
(b) storing (n 2 -2n) segments of said data block as data elements in said matrix , wherein said segments are stored in a configuration in which every location in said matrix , except those locations along each major diagonal thereof , contains one of said data elements ;
(c) calculating an XOR sum of all said data elements in a first wrapped minor diagonal of said matrix to produce a parity element which is stored in the major diagonal intersecting said wrapped minor diagonal ;
(d) repeating step (c) for all remaining said wrapped minor diagonals ;
and (e) writing each column in said matrix to a counterpart one of said data storage devices .

US6138125A
CLAIM 12
. The method of claim 5 further comprising the step of : writing said matrix to a plurality of storage devices in an array storage subsystem (flash memory device) having n storage devices and wherein each column of elements of said matrix is written to a corresponding one of said plurality of storage devices .

US9632727B2
CLAIM 13
. The system of claim 12 , wherein the logical-to-physical translation layer is stored in the flash memory device (storage subsystem, storage capacity) .
US6138125A
CLAIM 1
. A method for encoding a data block onto an array of n data storage devices , where (n+1) is a prime number , and wherein said data block has a maximum size equal to the storage capacity (flash memory device) of (n-2) of the data storage devices , said method comprising the steps of : (a) creating a matrix of dimensions (n×n) ;
(b) storing (n 2 -2n) segments of said data block as data elements in said matrix , wherein said segments are stored in a configuration in which every location in said matrix , except those locations along each major diagonal thereof , contains one of said data elements ;
(c) calculating an XOR sum of all said data elements in a first wrapped minor diagonal of said matrix to produce a parity element which is stored in the major diagonal intersecting said wrapped minor diagonal ;
(d) repeating step (c) for all remaining said wrapped minor diagonals ;
and (e) writing each column in said matrix to a counterpart one of said data storage devices .

US6138125A
CLAIM 12
. The method of claim 5 further comprising the step of : writing said matrix to a plurality of storage devices in an array storage subsystem (flash memory device) having n storage devices and wherein each column of elements of said matrix is written to a corresponding one of said plurality of storage devices .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US6069827A

Filed: 1998-03-24     Issued: 2000-05-30

Memory system

(Original Assignee) Memory Corp PLC     (Current Assignee) Micron Technology Inc

Alan Welsh Sinclair
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state (solid state) storage medium in response to requests from a computer system , including storing data (said memory) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data (said memory) pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US6069827A
CLAIM 1
. A memory system comprising : a plurality of memory locations each having a pre-defined physical address , said memory (store data, storing data) locations being arranged in erasable blocks of memory locations ;
translation means for translating a logical address to one of said predefined physical addresses , means for storing a first pointer that points to a memory location which is to be written to ;
means for storing a second pointer that points to one of said erasable blocks which is to be erased , said erasable block which is to be erased being the next unerased erasable block in a predetermined sequence of erasable blocks , the predetermined sequence including said memory location to be written to ;
and control means being provided to progress the first pointer sequentially through the blocks of memory locations in order of said predetermined sequence , and to ensure that there is always at least one erased erasable block in said predetermined sequence of blocks between the erasable block containing said memory location indicated by the first pointer and the erasable block indicated by the second pointer .

US6069827A
CLAIM 9
. A solid state (solid state) memory according to claim 1 characterised in that said memory locations are provided in a FLASH EPROM .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer (determined sequence) System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
US6069827A
CLAIM 1
. A memory system comprising : a plurality of memory locations each having a pre-defined physical address , said memory locations being arranged in erasable blocks of memory locations ;
translation means for translating a logical address to one of said predefined physical addresses , means for storing a first pointer that points to a memory location which is to be written to ;
means for storing a second pointer that points to one of said erasable blocks which is to be erased , said erasable block which is to be erased being the next unerased erasable block in a predetermined sequence (Small Computer, Small Computer System Interface) of erasable blocks , the predetermined sequence including said memory location to be written to ;
and control means being provided to progress the first pointer sequentially through the blocks of memory locations in order of said predetermined sequence , and to ensure that there is always at least one erased erasable block in said predetermined sequence of blocks between the erasable block containing said memory location indicated by the first pointer and the erasable block indicated by the second pointer .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (said memory) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
US6069827A
CLAIM 1
. A memory system comprising : a plurality of memory locations each having a pre-defined physical address , said memory (store data, storing data) locations being arranged in erasable blocks of memory locations ;
translation means for translating a logical address to one of said predefined physical addresses , means for storing a first pointer that points to a memory location which is to be written to ;
means for storing a second pointer that points to one of said erasable blocks which is to be erased , said erasable block which is to be erased being the next unerased erasable block in a predetermined sequence of erasable blocks , the predetermined sequence including said memory location to be written to ;
and control means being provided to progress the first pointer sequentially through the blocks of memory locations in order of said predetermined sequence , and to ensure that there is always at least one erased erasable block in said predetermined sequence of blocks between the erasable block containing said memory location indicated by the first pointer and the erasable block indicated by the second pointer .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US6157963A

Filed: 1998-03-24     Issued: 2000-12-05

System controller with plurality of memory queues for prioritized scheduling of I/O requests from priority assigned clients

(Original Assignee) LSI Corp     (Current Assignee) NetApp Inc

II William V. Courtright, William P. Delaney, Gerald J. Fredin
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system , including storing data (said memory) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data (said memory) pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US6157963A
CLAIM 8
. The storage controller as recited in claim 7 wherein each one of said memory (store data, storing data) queues are assigned a priority , and at least one of said plurality of memory queues is configured to receive I/O requests from at least one of said plurality of clients , and wherein said processing means selects an I/O request from one of said plurality of memory queues based on the priority assigned to each of said plurality of memory queues .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (said memory) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client (file server) that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
US6157963A
CLAIM 3
. The storage controller as recited in claim 1 wherein said storage controller is a file server (storage client) .

US6157963A
CLAIM 8
. The storage controller as recited in claim 7 wherein each one of said memory (store data, storing data) queues are assigned a priority , and at least one of said plurality of memory queues is configured to receive I/O requests from at least one of said plurality of clients , and wherein said processing means selects an I/O request from one of said plurality of memory queues based on the priority assigned to each of said plurality of memory queues .

US9632727B2
CLAIM 8
. The system of claim 7 , further comprising means for providing a storage interface to accept requests to perform storage operations (third interface) on the solid-state storage medium in reference to the logical blocks and to accept the message identifying the logical block that is not being used to reference data stored on the solid-state storage medium .
US6157963A
CLAIM 5
. The storage controller as recited in claim 1 further comprising a third interface (storage interface to accept requests to perform storage operations) means for receiving priority value information .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client (file server) ;

a storage processor coupled to the storage interface ;

a flash memory device (array controller) coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US6157963A
CLAIM 2
. The storage controller as recited in claim 1 wherein said storage controller is a disk array controller (flash memory device) .

US6157963A
CLAIM 3
. The storage controller as recited in claim 1 wherein said storage controller is a file server (storage client) .

US9632727B2
CLAIM 13
. The system of claim 12 , wherein the logical-to-physical translation layer is stored in the flash memory device (array controller) .
US6157963A
CLAIM 2
. The storage controller as recited in claim 1 wherein said storage controller is a disk array controller (flash memory device) .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US6418478B1

Filed: 1998-03-11     Issued: 2002-07-09

Pipelined high speed data transfer mechanism

(Original Assignee) Commvault Systems Inc     (Current Assignee) Commvault Systems Inc

Paul Ignatius, Anand Prahlad, Mahesh Tyagarajan
US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer (carrying data) System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
US6418478B1
CLAIM 1
. A communication system having an origination storage device , a destination storage device , and a data pipeline apparatus for transferring data from the origination storage device to the destination storage device , the data pipeline apparatus comprising : a dedicated memory associated with both the origination storage device and the destination storage device having a pool of buffers dedicated to carrying data (Small Computer) from the origination storage device to the destination storage device ;
a master control module for registering and initiating processes associated with the data transfer apparatus , the processes including : a first stage collection process that allocates a sequence of buffers from the pool of buffers located in the dedicated memory , the sequence of buffers being locked against further allocation until freed by the process to which the sequence of buffers are assigned ;
at least one restore process that stores the data resident in the sequence of buffers in the destination storage device and frees the sequence of buffers so that they may be reallocated ;
and a network control module that is responsive to the master control module , the network control module initiating a plurality of network agent processes such that the dedicated memory is shared among each of the processes participating in the data transfer pipeline .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer (data transfer apparatus) is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor returns a predetermined data string .
US6418478B1
CLAIM 1
. A communication system having an origination storage device , a destination storage device , and a data pipeline apparatus for transferring data from the origination storage device to the destination storage device , the data pipeline apparatus comprising : a dedicated memory associated with both the origination storage device and the destination storage device having a pool of buffers dedicated to carrying data from the origination storage device to the destination storage device ;
a master control module for registering and initiating processes associated with the data transfer apparatus (storage processer) , the processes including : a first stage collection process that allocates a sequence of buffers from the pool of buffers located in the dedicated memory , the sequence of buffers being locked against further allocation until freed by the process to which the sequence of buffers are assigned ;
at least one restore process that stores the data resident in the sequence of buffers in the destination storage device and frees the sequence of buffers so that they may be reallocated ;
and a network control module that is responsive to the master control module , the network control module initiating a plurality of network agent processes such that the dedicated memory is shared among each of the processes participating in the data transfer pipeline .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US6081878A

Filed: 1998-02-25     Issued: 2000-06-27

Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices

(Original Assignee) Lexar Media Inc     (Current Assignee) Micron Technology Inc

Petro Estakhri, Berhanu Iman
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium (write operation) in response to requests from a computer system , including storing data (store information, storing data) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data (storing information, second address) pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US6081878A
CLAIM 1
. A memory storage system for storing information (store data) organized in sectors within a nonvolatile memory bank defined by sector store locations spanning across two or more nonvolatile memory devices , each said sector including a user data portion and an overhead portion , said sectors being organized into blocks , each sector identified by a host provided logical block address (LBA) and an actual physical block address (PBA) derived from a virtual PBA , each block being identified by a modified LBA derived from said host-provided LBA and said virtual PBA , said host-provided LBA being received by said storage system from the host for identifying a sector of information to be accessed , said actual PBA developed by said storage system for identifying a free location within said memory bank wherein said accessed sector is to be stored , said storage system comprising : a memory controller coupled to said host ;
and a nonvolatile memory bank coupled to said memory controller via a memory bus , said memory bank including a first non-volatile semiconductor memory unit and a second non-volatile semiconductor memory unit , said memory bank having storage blocks each of which includes at least one memory row location having a first row-portion located in said first memory unit , and a corresponding second row-portion located in said second memory unit , each said memory row location providing storage space for two of said sectors , wherein the speed of performing write operation (solid state storage medium) s is increased by writing sector information to two or more nonvolatile memory devices simultaneously .

US6081878A
CLAIM 9
. A memory storage system as recited in claim 8 wherein said flag field is used to store block level flags including : a used/free block flag indicating whether said corresponding block is currently being used to store information (storing data) ;
and a defect block flag indicating whether said corresponding block is defective .

US6081878A
CLAIM 12
. A memory storage system as recited in claim 11 wherein : each of said first row-portions includes a first sector field for storing data (storing data) bytes of a first sector ;
each of said second row-portions includes a second sector field for storing data bytes of a second sector ;
said memory bus includes , a first split bus coupled to transmit (least significant ?) data bytes of said sectors between said memory controller and said first memory unit ;
a second split bus coupled to transmit (most significant ?) data bytes of said sectors between said memory controller and said second memory unit .

US6081878A
CLAIM 20
. In a storage system including a nonvolatile memory bank and a controller coupled to said memory bank via a memory bus , said memory bank including a first non-volatile memory unit and a second non-volatile memory unit , said memory bank having storage blocks for storing information sectors each of which includes a user data portion and an overhead portion , each block having associated therewith a logical block address (LBA) and a physical block address (PBA) , said LBA provided by a host to said controller for identifying a block to be accessed , said PBA developed by said storage system for identifying a free location within said memory bank wherein said accessed block is to be stored , each block including at least one memory row location having a first row-portion located in said first memory unit , and a corresponding second row-portion located in said second memory unit , a process of writing a first sector and a second sector to said memory bank during a single write operation , said process including the steps of : simultaneously providing a write command to said first and second memory units ;
addressing one of said memory row locations of said memory bank by simultaneously addressing corresponding first and second row portions of said addressed row location ;
storing even data bytes of an even sector to a first even sector field of said addressed first row-portion ;
storing even data bytes of an odd sector to a first odd sector field of said first addressed row-portion ;
storing odd data bytes of said even sector to a second even sector field of said second address (store data) ed row-portion ;
and storing odd data bytes of said odd sector of information to a second odd sector field of said second addressed row-portion .

US9632727B2
CLAIM 5
. The apparatus of claim 1 , further comprising a garbage collector (logical block address, nonvolatile memory) configured to designate that the physical address previously assigned to the identified logical address comprises data suitable for removal from the solid-state storage medium in response to the message .
US6081878A
CLAIM 1
. A memory storage system for storing information organized in sectors within a nonvolatile memory (garbage collector) bank defined by sector store locations spanning across two or more nonvolatile memory devices , each said sector including a user data portion and an overhead portion , said sectors being organized into blocks , each sector identified by a host provided logical block address (garbage collector) (LBA) and an actual physical block address (PBA) derived from a virtual PBA , each block being identified by a modified LBA derived from said host-provided LBA and said virtual PBA , said host-provided LBA being received by said storage system from the host for identifying a sector of information to be accessed , said actual PBA developed by said storage system for identifying a free location within said memory bank wherein said accessed sector is to be stored , said storage system comprising : a memory controller coupled to said host ;
and a nonvolatile memory bank coupled to said memory controller via a memory bus , said memory bank including a first non-volatile semiconductor memory unit and a second non-volatile semiconductor memory unit , said memory bank having storage blocks each of which includes at least one memory row location having a first row-portion located in said first memory unit , and a corresponding second row-portion located in said second memory unit , each said memory row location providing storage space for two of said sectors , wherein the speed of performing write operations is increased by writing sector information to two or more nonvolatile memory devices simultaneously .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial (single memory) Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface (data port) , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
US6081878A
CLAIM 1
. A memory storage system for storing information organized in sectors within a nonvolatile memory bank defined by sector store locations spanning across two or more nonvolatile memory devices , each said sector including a user data port (external SATA bus interface) ion and an overhead portion , said sectors being organized into blocks , each sector identified by a host provided logical block address (LBA) and an actual physical block address (PBA) derived from a virtual PBA , each block being identified by a modified LBA derived from said host-provided LBA and said virtual PBA , said host-provided LBA being received by said storage system from the host for identifying a sector of information to be accessed , said actual PBA developed by said storage system for identifying a free location within said memory bank wherein said accessed sector is to be stored , said storage system comprising : a memory controller coupled to said host ;
and a nonvolatile memory bank coupled to said memory controller via a memory bus , said memory bank including a first non-volatile semiconductor memory unit and a second non-volatile semiconductor memory unit , said memory bank having storage blocks each of which includes at least one memory row location having a first row-portion located in said first memory unit , and a corresponding second row-portion located in said second memory unit , each said memory row location providing storage space for two of said sectors , wherein the speed of performing write operations is increased by writing sector information to two or more nonvolatile memory devices simultaneously .

US6081878A
CLAIM 15
. In a storage system including a memory bank and a controller as recited in claim 14 wherein an even sector and an odd sector are stored in a single memory (external Serial) row location and wherein even user data bytes of said first and second sectors are stored in said first memory unit and odd user data bytes of said first and second sectors are stored in said second memory unit and wherein overhead information associated with said first and second sectors is stored in one of said first and second row portions .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (store information, storing data) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client (semiconductor memory) that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
US6081878A
CLAIM 1
. A memory storage system for storing information organized in sectors within a nonvolatile memory bank defined by sector store locations spanning across two or more nonvolatile memory devices , each said sector including a user data portion and an overhead portion , said sectors being organized into blocks , each sector identified by a host provided logical block address (LBA) and an actual physical block address (PBA) derived from a virtual PBA , each block being identified by a modified LBA derived from said host-provided LBA and said virtual PBA , said host-provided LBA being received by said storage system from the host for identifying a sector of information to be accessed , said actual PBA developed by said storage system for identifying a free location within said memory bank wherein said accessed sector is to be stored , said storage system comprising : a memory controller coupled to said host ;
and a nonvolatile memory bank coupled to said memory controller via a memory bus , said memory bank including a first non-volatile semiconductor memory (storage client) unit and a second non-volatile semiconductor memory unit , said memory bank having storage blocks each of which includes at least one memory row location having a first row-portion located in said first memory unit , and a corresponding second row-portion located in said second memory unit , each said memory row location providing storage space for two of said sectors , wherein the speed of performing write operations is increased by writing sector information to two or more nonvolatile memory devices simultaneously .

US6081878A
CLAIM 9
. A memory storage system as recited in claim 8 wherein said flag field is used to store block level flags including : a used/free block flag indicating whether said corresponding block is currently being used to store information (storing data) ;
and a defect block flag indicating whether said corresponding block is defective .

US6081878A
CLAIM 12
. A memory storage system as recited in claim 11 wherein : each of said first row-portions includes a first sector field for storing data (storing data) bytes of a first sector ;
each of said second row-portions includes a second sector field for storing data bytes of a second sector ;
said memory bus includes , a first split bus coupled to transmit (least significant ?) data bytes of said sectors between said memory controller and said first memory unit ;
a second split bus coupled to transmit (most significant ?) data bytes of said sectors between said memory controller and said second memory unit .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client (semiconductor memory) ;

a storage processor coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US6081878A
CLAIM 1
. A memory storage system for storing information organized in sectors within a nonvolatile memory bank defined by sector store locations spanning across two or more nonvolatile memory devices , each said sector including a user data portion and an overhead portion , said sectors being organized into blocks , each sector identified by a host provided logical block address (LBA) and an actual physical block address (PBA) derived from a virtual PBA , each block being identified by a modified LBA derived from said host-provided LBA and said virtual PBA , said host-provided LBA being received by said storage system from the host for identifying a sector of information to be accessed , said actual PBA developed by said storage system for identifying a free location within said memory bank wherein said accessed sector is to be stored , said storage system comprising : a memory controller coupled to said host ;
and a nonvolatile memory bank coupled to said memory controller via a memory bus , said memory bank including a first non-volatile semiconductor memory (storage client) unit and a second non-volatile semiconductor memory unit , said memory bank having storage blocks each of which includes at least one memory row location having a first row-portion located in said first memory unit , and a corresponding second row-portion located in said second memory unit , each said memory row location providing storage space for two of said sectors , wherein the speed of performing write operations is increased by writing sector information to two or more nonvolatile memory devices simultaneously .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer (logic unit) is configured such that , responsive to receiving a read request (n information) specifying one or more logical addresses included in the empty-block directive command , the storage processor returns a predetermined data string .
US6081878A
CLAIM 2
. A memory storage system as recited in claim 1 wherein said memory controller includes : a data buffer for temporarily storing said sector-organized information ;
a microprocessor ;
a space manager including a space manager controller and a space manager memory unit for maintaining a map for translating said LBA to said PBA ;
and an error correction code logic unit (storage processer) for performing error coding and correction operations on said sector-organized information .

US6081878A
CLAIM 4
. A memory storage system as recited in claim 3 wherein each of said second row-portions further includes : a first error correction field for storing error correction information (read request) corresponding to said even sector ;
a second error correction field for storing error correction information corresponding to said odd sector ;
a block address field for storing said PBA which specifies an address of said corresponding block , and a flag field for storing information indicative of the status of said corresponding block .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US6415373B1

Filed: 1998-01-12     Issued: 2002-07-02

Computer system and process for transferring multiple high bandwidth streams of data between multiple storage units and multiple applications in a scalable and reliable manner

(Original Assignee) Avid Technology Inc     (Current Assignee) CERBERUS BUSINESS FINANCE AS COLLATERAL AGENT LLC

Eric C. Peters, Stanley Rabinowitz, Herbert R. Jacobs, Peter J. Fasciano
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system (waiting time) , the message indicating that the identified logical address is erased .
US6415373B1
CLAIM 2
. A file system for a computer , enabling the computer to access remote independent storage units over a computer network in response to a request , from an application executed on the computer , to read data stored in one or more files on the storage units , wherein a file includes segments of the data and one or more copies of each segment , and wherein , for each file , each segment of the data is stored on a randomly or pseudorandomly selected one of the storage units , and wherein , for each copy of each segment , the copy is stored on a randomly or pseudorandomly selected on of the storage units , the file system comprising : means , responsive to the request to read data from a file , for selecting , for each segment of the requested data , one of the storage units on which the segment is stored ;
means for reading each segment of the requested data from the selected storage unit for the segment ;
means for serializing the segments read from the selected storage units ;
and means for providing the serialized data to the application ;
wherein the means for reading each segment comprises means for scheduling transfer of the data from the selected storage unit such that the storage unit efficiently transfers data , wherein the means for scheduling transfer includes : in the file system : means for requesting transfer of the data from the selected storage unit , indicating a waiting time (host operating system) ;
means for requesting the data from another storage unit if the selected storage unit rejects the request to transfer the data ;
and in the storage unit : means for rejecting a request to transfer data if the data is not available to be transferred from the storage unit by the indicated waiting time ;
means for transferring the data if the selected storage unit is able to transfer the data within the waiting time .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor (data store) coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US6415373B1
CLAIM 1
. A file system for a computer , enabling the computer to access remote independent storage units over a computer network in response to a request , from an application executed on the computer , to read data store (storage processor) d in one or more files on the storage units , wherein a file includes segments of the data and one or more copies of each segment , and wherein , for each file , each segment of the data is stored on a randomly or pseudorandomly selected one of the storage units , and wherein , for each copy of each segment , the copy is stored on a randomly or pseudorandomly selected on of the storage units , the file system comprising : means , responsive to the request to read data from a file , for selecting , for each segment of the requested data , one of the storage units on which the segment is stored ;
means for reading each segment of the requested data from the selected storage unit for the segment ;
means for serializing the segments read from the selected storage units ;
and means for providing the serialized data to the application wherein the means for selecting includes : in the file system : means for requesting data from one of the storage units , indicating an estimated time ;
means for requesting data from another of the storage units , indicating an estimated time , if the first storage unit rejects the request ;
means for requesting the data from the first storage unit if the second storage unit rejects the request ;
and in each storage unit : means for rejecting a request for data if the request cannot be serviced by the storage unit within the estimated time ;
and means for accepting a request for data if the request can be serviced by the storage unit within the estimated time .

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (data store) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
US6415373B1
CLAIM 1
. A file system for a computer , enabling the computer to access remote independent storage units over a computer network in response to a request , from an application executed on the computer , to read data store (storage processor) d in one or more files on the storage units , wherein a file includes segments of the data and one or more copies of each segment , and wherein , for each file , each segment of the data is stored on a randomly or pseudorandomly selected one of the storage units , and wherein , for each copy of each segment , the copy is stored on a randomly or pseudorandomly selected on of the storage units , the file system comprising : means , responsive to the request to read data from a file , for selecting , for each segment of the requested data , one of the storage units on which the segment is stored ;
means for reading each segment of the requested data from the selected storage unit for the segment ;
means for serializing the segments read from the selected storage units ;
and means for providing the serialized data to the application wherein the means for selecting includes : in the file system : means for requesting data from one of the storage units , indicating an estimated time ;
means for requesting data from another of the storage units , indicating an estimated time , if the first storage unit rejects the request ;
means for requesting the data from the first storage unit if the second storage unit rejects the request ;
and in each storage unit : means for rejecting a request for data if the request cannot be serviced by the storage unit within the estimated time ;
and means for accepting a request for data if the request can be serviced by the storage unit within the estimated time .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor (data store) returns a predetermined data string .
US6415373B1
CLAIM 1
. A file system for a computer , enabling the computer to access remote independent storage units over a computer network in response to a request , from an application executed on the computer , to read data store (storage processor) d in one or more files on the storage units , wherein a file includes segments of the data and one or more copies of each segment , and wherein , for each file , each segment of the data is stored on a randomly or pseudorandomly selected one of the storage units , and wherein , for each copy of each segment , the copy is stored on a randomly or pseudorandomly selected on of the storage units , the file system comprising : means , responsive to the request to read data from a file , for selecting , for each segment of the requested data , one of the storage units on which the segment is stored ;
means for reading each segment of the requested data from the selected storage unit for the segment ;
means for serializing the segments read from the selected storage units ;
and means for providing the serialized data to the application wherein the means for selecting includes : in the file system : means for requesting data from one of the storage units , indicating an estimated time ;
means for requesting data from another of the storage units , indicating an estimated time , if the first storage unit rejects the request ;
means for requesting the data from the first storage unit if the second storage unit rejects the request ;
and in each storage unit : means for rejecting a request for data if the request cannot be serviced by the storage unit within the estimated time ;
and means for accepting a request for data if the request can be serviced by the storage unit within the estimated time .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US6567889B1

Filed: 1997-12-19     Issued: 2003-05-20

Apparatus and method to provide virtual solid state disk in cache memory in a storage controller

(Original Assignee) LSI Corp     (Current Assignee) NetApp Inc

Rodney A. DeKoning, Gerald J. Fredin, Donald R. Humlicek
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller (storage controller) configured to implement storage operations on the solid state storage medium in response to requests from a computer system (stored data) , including storing data (store information, storing data) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data (storing information) pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US6567889B1
CLAIM 4
. Apparatus of claim 1 wherein said virtual solid state disk storage device in said primary RAID disk array controller is operable to store information (storing data) in accordance with RAID techniques .

US6567889B1
CLAIM 20
. The method of claim 17 further comprising the step of : storing information (store data) in said virtual solid state disk storage device in accordance with a pre-selected RAID level management technique .

US6567889B1
CLAIM 22
. A data storage subsystem for storing data (storing data) received from and providing stored data (computer system) to a host computer , said storage subsystem comprising : a disk array including a plurality of disk drives ;
a storage controller (storage controller) that includes a CPU and a cache memory , wherein said cache memory includes a first memory partition and a second memory partition , said first memory partition stores data and control information related to data stored in said disk array , and said second memory partition provides a virtual solid state disk drive ;
and a communication medium that provides communication between said storage controller and said disk array .

US9632727B2
CLAIM 3
. The apparatus of claim 1 , wherein the indexer assigns logical addresses to physical addresses by use of index metadata maintained in a memory of the storage controller (storage controller) .
US6567889B1
CLAIM 22
. A data storage subsystem for storing data received from and providing stored data to a host computer , said storage subsystem comprising : a disk array including a plurality of disk drives ;
a storage controller (storage controller) that includes a CPU and a cache memory , wherein said cache memory includes a first memory partition and a second memory partition , said first memory partition stores data and control information related to data stored in said disk array , and said second memory partition provides a virtual solid state disk drive ;
and a communication medium that provides communication between said storage controller and said disk array .

US9632727B2
CLAIM 4
. The apparatus of claim 1 , wherein the indexer comprises firmware (checkpoint data) of the solid-state storage controller (storage controller) .
US6567889B1
CLAIM 22
. A data storage subsystem for storing data received from and providing stored data to a host computer , said storage subsystem comprising : a disk array including a plurality of disk drives ;
a storage controller (storage controller) that includes a CPU and a cache memory , wherein said cache memory includes a first memory partition and a second memory partition , said first memory partition stores data and control information related to data stored in said disk array , and said second memory partition provides a virtual solid state disk drive ;
and a communication medium that provides communication between said storage controller and said disk array .

US6567889B1
CLAIM 33
. The storage subsystem of claim 31 wherein said selected data includes transaction checkpoint data (indexer comprises firmware) .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller (storage controller) comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system (stored data) , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (computational result) (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface (logical unit) , and a Fibre Channel interface .
US6567889B1
CLAIM 22
. A data storage subsystem for storing data received from and providing stored data (computer system) to a host computer , said storage subsystem comprising : a disk array including a plurality of disk drives ;
a storage controller (storage controller) that includes a CPU and a cache memory , wherein said cache memory includes a first memory partition and a second memory partition , said first memory partition stores data and control information related to data stored in said disk array , and said second memory partition provides a virtual solid state disk drive ;
and a communication medium that provides communication between said storage controller and said disk array .

US6567889B1
CLAIM 24
. The storage subsystem of claim 22 wherein said virtual solid state disk drive and said disk array in combination provide a virtual logical unit (internet SCSI interface, read request) for said storage controller .

US6567889B1
CLAIM 35
. The storage subsystem of claim 31 wherein said selected data includes intermediate computational result (Peripheral Component Interconnect) s .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (store information, storing data) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
US6567889B1
CLAIM 4
. Apparatus of claim 1 wherein said virtual solid state disk storage device in said primary RAID disk array controller is operable to store information (storing data) in accordance with RAID techniques .

US6567889B1
CLAIM 22
. A data storage subsystem for storing data (storing data) received from and providing stored data to a host computer , said storage subsystem comprising : a disk array including a plurality of disk drives ;
a storage controller that includes a CPU and a cache memory , wherein said cache memory includes a first memory partition and a second memory partition , said first memory partition stores data and control information related to data stored in said disk array , and said second memory partition provides a virtual solid state disk drive ;
and a communication medium that provides communication between said storage controller and said disk array .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor (data store) coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US6567889B1
CLAIM 22
. A data storage subsystem for storing data received from and providing stored data to a host computer , said storage subsystem comprising : a disk array including a plurality of disk drives ;
a storage controller that includes a CPU and a cache memory , wherein said cache memory includes a first memory partition and a second memory partition , said first memory partition stores data and control information related to data store (storage processor) d in said disk array , and said second memory partition provides a virtual solid state disk drive ;
and a communication medium that provides communication between said storage controller and said disk array .

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (data store) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
US6567889B1
CLAIM 22
. A data storage subsystem for storing data received from and providing stored data to a host computer , said storage subsystem comprising : a disk array including a plurality of disk drives ;
a storage controller that includes a CPU and a cache memory , wherein said cache memory includes a first memory partition and a second memory partition , said first memory partition stores data and control information related to data store (storage processor) d in said disk array , and said second memory partition provides a virtual solid state disk drive ;
and a communication medium that provides communication between said storage controller and said disk array .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request (logical unit) specifying one or more logical addresses included in the empty-block directive command , the storage processor (data store) returns a predetermined data string .
US6567889B1
CLAIM 22
. A data storage subsystem for storing data received from and providing stored data to a host computer , said storage subsystem comprising : a disk array including a plurality of disk drives ;
a storage controller that includes a CPU and a cache memory , wherein said cache memory includes a first memory partition and a second memory partition , said first memory partition stores data and control information related to data store (storage processor) d in said disk array , and said second memory partition provides a virtual solid state disk drive ;
and a communication medium that provides communication between said storage controller and said disk array .

US6567889B1
CLAIM 24
. The storage subsystem of claim 22 wherein said virtual solid state disk drive and said disk array in combination provide a virtual logical unit (internet SCSI interface, read request) for said storage controller .

US9632727B2
CLAIM 16
. The system of claim 15 , wherein data bits (data transfer rate) of the predetermined data string have a uniform logic level .
US6567889B1
CLAIM 44
. The storage subsystem of claim 22 including a second communication medium that provides communication between said CPU and said virtual solid state disk drive , wherein a data transfer rate (data bits) of said second communication medium is substantially higher than a data transfer rate of said communication medium .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US5930815A

Filed: 1997-10-07     Issued: 1999-07-27

Moving sequential sectors within a block of information in a flash memory mass storage architecture

(Original Assignee) Lexar Media Inc     (Current Assignee) Micron Technology Inc

Petro Estakhri, Berhanu Iman
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium (write operation) in response to requests from a computer system , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US5930815A
CLAIM 1
. A method for updating sector information in a digital system having a host coupled through a controller to a nonvolatile memory device for storing digital information organized into sectors in the nonvolatile memory , each sector having a data portion and an overhead portion and being uniquely identifiable by the host using an LBA (Logical Block Address) , the sector information stored within a sector location within the nonvolatile memory device , a group of sector locations defining a block addressable by the controller using a VPBA (Virtual Physical Block Address) , and each sector location within a block being identifiable by the controller using a PBA (Physical Block Address) , wherein the sector information stored in a sector location of a block within the nonvolatile memory device is updated prior to erasure of the block , the method comprising : a . developing an LBA value corresponding to a host-addressed sector in response to a command received from the host to re-write sector information to a sector identified by the host ;
b . developing an LBA block address from the LBA value for addressing a block within the memory device within which the sector provided by the host is to be stored ;
c . comparing the LBA value with a previous LBA (PREV -- LBA) value to determine whether or not there is a match ;
d . if the LBA value and PREV -- LBA match , checking for a previous write operation (solid state storage medium) to have been performed on the LBA block since the last erase operation of the LBA block ;
e . if a previous write operation has been performed , checking for whether or not any of the sectors of the block identified by the LBA block address have been transferred from one location within the memory device to another location within the memory device since the occurrence of the last erase operation on the LBA block ;
f . if the sectors of the block identified by the LBA block address have not been transferred , finding a free block within the nonvolatile memory device for storing the sector information , the free block being identified by a VPBA value corresponding to the LBA block ;
g . storing the sector information within a sector location of the free block corresponding to the sector location of the LBA block ;
h . storing the VPBA value in a PBA storage location for indicating the free block location within the memory device wherein the new sector information resides ;
i . incrementing the LBA value by one ;
and j . replacing the PREV -- LBA value with the incremented LBA value , wherein single sequential write operations are performed on a sector of a block that was previously written and not yet erased without moving all other sectors of the block .

US9632727B2
CLAIM 5
. The apparatus of claim 1 , further comprising a garbage collector (nonvolatile memory) configured to designate that the physical address previously assigned to the identified logical address comprises data suitable for removal from the solid-state storage medium in response to the message .
US5930815A
CLAIM 1
. A method for updating sector information in a digital system having a host coupled through a controller to a nonvolatile memory (garbage collector) device for storing digital information organized into sectors in the nonvolatile memory , each sector having a data portion and an overhead portion and being uniquely identifiable by the host using an LBA (Logical Block Address) , the sector information stored within a sector location within the nonvolatile memory device , a group of sector locations defining a block addressable by the controller using a VPBA (Virtual Physical Block Address) , and each sector location within a block being identifiable by the controller using a PBA (Physical Block Address) , wherein the sector information stored in a sector location of a block within the nonvolatile memory device is updated prior to erasure of the block , the method comprising : a . developing an LBA value corresponding to a host-addressed sector in response to a command received from the host to re-write sector information to a sector identified by the host ;
b . developing an LBA block address from the LBA value for addressing a block within the memory device within which the sector provided by the host is to be stored ;
c . comparing the LBA value with a previous LBA (PREV -- LBA) value to determine whether or not there is a match ;
d . if the LBA value and PREV -- LBA match , checking for a previous write operation to have been performed on the LBA block since the last erase operation of the LBA block ;
e . if a previous write operation has been performed , checking for whether or not any of the sectors of the block identified by the LBA block address have been transferred from one location within the memory device to another location within the memory device since the occurrence of the last erase operation on the LBA block ;
f . if the sectors of the block identified by the LBA block address have not been transferred , finding a free block within the nonvolatile memory device for storing the sector information , the free block being identified by a VPBA value corresponding to the LBA block ;
g . storing the sector information within a sector location of the free block corresponding to the sector location of the LBA block ;
h . storing the VPBA value in a PBA storage location for indicating the free block location within the memory device wherein the new sector information resides ;
i . incrementing the LBA value by one ;
and j . replacing the PREV -- LBA value with the incremented LBA value , wherein single sequential write operations are performed on a sector of a block that was previously written and not yet erased without moving all other sectors of the block .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface (data port) , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
US5930815A
CLAIM 1
. A method for updating sector information in a digital system having a host coupled through a controller to a nonvolatile memory device for storing digital information organized into sectors in the nonvolatile memory , each sector having a data port (external SATA bus interface) ion and an overhead portion and being uniquely identifiable by the host using an LBA (Logical Block Address) , the sector information stored within a sector location within the nonvolatile memory device , a group of sector locations defining a block addressable by the controller using a VPBA (Virtual Physical Block Address) , and each sector location within a block being identifiable by the controller using a PBA (Physical Block Address) , wherein the sector information stored in a sector location of a block within the nonvolatile memory device is updated prior to erasure of the block , the method comprising : a . developing an LBA value corresponding to a host-addressed sector in response to a command received from the host to re-write sector information to a sector identified by the host ;
b . developing an LBA block address from the LBA value for addressing a block within the memory device within which the sector provided by the host is to be stored ;
c . comparing the LBA value with a previous LBA (PREV -- LBA) value to determine whether or not there is a match ;
d . if the LBA value and PREV -- LBA match , checking for a previous write operation to have been performed on the LBA block since the last erase operation of the LBA block ;
e . if a previous write operation has been performed , checking for whether or not any of the sectors of the block identified by the LBA block address have been transferred from one location within the memory device to another location within the memory device since the occurrence of the last erase operation on the LBA block ;
f . if the sectors of the block identified by the LBA block address have not been transferred , finding a free block within the nonvolatile memory device for storing the sector information , the free block being identified by a VPBA value corresponding to the LBA block ;
g . storing the sector information within a sector location of the free block corresponding to the sector location of the LBA block ;
h . storing the VPBA value in a PBA storage location for indicating the free block location within the memory device wherein the new sector information resides ;
i . incrementing the LBA value by one ;
and j . replacing the PREV -- LBA value with the incremented LBA value , wherein single sequential write operations are performed on a sector of a block that was previously written and not yet erased without moving all other sectors of the block .

US9632727B2
CLAIM 9
. The system of claim 7 , wherein unmapping the identified logical block comprises invalidating an entry of the logical-to-physical mappings , the entry indicating a mapping between the identified logical block and the particular storage (particular storage) block .
US5930815A
CLAIM 2
. A method as recited in claim 1 , wherein a move locator value is generated and stored in a particular storage (particular storage) location , and further including , after said step of storing the sector information , the step of modifying the value of a move locator storage location to indicate the status of which sector within the LBA block has been updated by setting a bit in said particular storage location , the position of the bit within the move locator value corresponding to the position of the updated sector within the LBA block .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US6151641A

Filed: 1997-09-30     Issued: 2000-11-21

DMA controller of a RAID storage controller with integrated XOR parity computation capability adapted to compute parity in parallel with the transfer of data segments

(Original Assignee) LSI Corp     (Current Assignee) Avago Technologies General IP Singapore Pte Ltd

Brian K. Herbert
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller (storage controller) configured to implement storage operations on the solid state storage medium in response to requests from a computer system , including storing data (said memory, store data) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data (said memory, store data) pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US6151641A
CLAIM 1
. In a DMA controller of a RAID storage controller (storage controller) in a RAID storage subsystem , a method to compute parity comprising the steps of : transferring a data portion of a stripe from a host system to a RAID storage subsystem through said DMA controller from a random access source memory to a destination memory , wherein said data portion of said stripe is comprised of a plurality of data blocks wherein each of said plurality of data blocks is comprised of a plurality of data segments , and wherein said plurality of data segments are stored in said source memory in a first predetermined order and wherein said data segments are transferred to said destination memory in a second predetermined order different from said first predetermined order ;
and computing , within said DMA controller , a plurality of XOR parity segments corresponding to said plurality of data segments , wherein the step of transferring a data portion of a stripe further comprises the steps of : a) transferring a first data segment of said plurality of data segments of a data block of said plurality of data blocks of said stripe ;
b) transferring a corresponding data segment of said plurality of data segments of a next data block of said plurality of data blocks ;
c) storing XOR parity generated by said computing step in a buffer ;
d) repeating steps b) and c) for each data block of said stripe until each corresponding data segment of each block of said plurality of data blocks of said stripe have been transferred ;
and e) repeating steps a) through d) for a next data segment of said plurality of data segments in each of said plurality of blocks in said data portion of said stripe until all of said plurality of data segments have been transferred , and wherein the computing step is performed substantially simultaneously with said step of transferring .

US6151641A
CLAIM 7
. The DMA controller of claim 6 wherein said XOR buffer circuit includes : first means for controlling said memory (store data (store data, storing data, storage client) , storing data, storage client) to store data captured during transfer of said plurality of data segments in said memory ;
second means for controlling said memory and said XOR generation means to compute the bitwise XOR of data previously stored in said memory and data captured during transfer of said plurality of data segments and to store said bitwise XOR result in said memory ;
and third means for controlling said memory to read the contents of said memory for purposes of transferring parity data from said memory to said destination memory .

US9632727B2
CLAIM 3
. The apparatus of claim 1 , wherein the indexer assigns logical addresses to physical addresses by use of index metadata maintained in a memory of the storage controller (storage controller) .
US6151641A
CLAIM 1
. In a DMA controller of a RAID storage controller (storage controller) in a RAID storage subsystem , a method to compute parity comprising the steps of : transferring a data portion of a stripe from a host system to a RAID storage subsystem through said DMA controller from a random access source memory to a destination memory , wherein said data portion of said stripe is comprised of a plurality of data blocks wherein each of said plurality of data blocks is comprised of a plurality of data segments , and wherein said plurality of data segments are stored in said source memory in a first predetermined order and wherein said data segments are transferred to said destination memory in a second predetermined order different from said first predetermined order ;
and computing , within said DMA controller , a plurality of XOR parity segments corresponding to said plurality of data segments , wherein the step of transferring a data portion of a stripe further comprises the steps of : a) transferring a first data segment of said plurality of data segments of a data block of said plurality of data blocks of said stripe ;
b) transferring a corresponding data segment of said plurality of data segments of a next data block of said plurality of data blocks ;
c) storing XOR parity generated by said computing step in a buffer ;
d) repeating steps b) and c) for each data block of said stripe until each corresponding data segment of each block of said plurality of data blocks of said stripe have been transferred ;
and e) repeating steps a) through d) for a next data segment of said plurality of data segments in each of said plurality of blocks in said data portion of said stripe until all of said plurality of data segments have been transferred , and wherein the computing step is performed substantially simultaneously with said step of transferring .

US9632727B2
CLAIM 4
. The apparatus of claim 1 , wherein the indexer comprises firmware of the solid-state storage controller (storage controller) .
US6151641A
CLAIM 1
. In a DMA controller of a RAID storage controller (storage controller) in a RAID storage subsystem , a method to compute parity comprising the steps of : transferring a data portion of a stripe from a host system to a RAID storage subsystem through said DMA controller from a random access source memory to a destination memory , wherein said data portion of said stripe is comprised of a plurality of data blocks wherein each of said plurality of data blocks is comprised of a plurality of data segments , and wherein said plurality of data segments are stored in said source memory in a first predetermined order and wherein said data segments are transferred to said destination memory in a second predetermined order different from said first predetermined order ;
and computing , within said DMA controller , a plurality of XOR parity segments corresponding to said plurality of data segments , wherein the step of transferring a data portion of a stripe further comprises the steps of : a) transferring a first data segment of said plurality of data segments of a data block of said plurality of data blocks of said stripe ;
b) transferring a corresponding data segment of said plurality of data segments of a next data block of said plurality of data blocks ;
c) storing XOR parity generated by said computing step in a buffer ;
d) repeating steps b) and c) for each data block of said stripe until each corresponding data segment of each block of said plurality of data blocks of said stripe have been transferred ;
and e) repeating steps a) through d) for a next data segment of said plurality of data segments in each of said plurality of blocks in said data portion of said stripe until all of said plurality of data segments have been transferred , and wherein the computing step is performed substantially simultaneously with said step of transferring .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller (storage controller) comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology (second order) Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA (host system, data port) bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
US6151641A
CLAIM 1
. In a DMA controller of a RAID storage controller (storage controller) in a RAID storage subsystem , a method to compute parity comprising the steps of : transferring a data port (external SATA, external SATA bus interface) ion of a stripe from a host system (external SATA, external SATA bus interface) to a RAID storage subsystem through said DMA controller from a random access source memory to a destination memory , wherein said data portion of said stripe is comprised of a plurality of data blocks wherein each of said plurality of data blocks is comprised of a plurality of data segments , and wherein said plurality of data segments are stored in said source memory in a first predetermined order and wherein said data segments are transferred to said destination memory in a second predetermined order different from said first predetermined order ;
and computing , within said DMA controller , a plurality of XOR parity segments corresponding to said plurality of data segments , wherein the step of transferring a data portion of a stripe further comprises the steps of : a) transferring a first data segment of said plurality of data segments of a data block of said plurality of data blocks of said stripe ;
b) transferring a corresponding data segment of said plurality of data segments of a next data block of said plurality of data blocks ;
c) storing XOR parity generated by said computing step in a buffer ;
d) repeating steps b) and c) for each data block of said stripe until each corresponding data segment of each block of said plurality of data blocks of said stripe have been transferred ;
and e) repeating steps a) through d) for a next data segment of said plurality of data segments in each of said plurality of blocks in said data portion of said stripe until all of said plurality of data segments have been transferred , and wherein the computing step is performed substantially simultaneously with said step of transferring .

US6151641A
CLAIM 8
. A DMA controller for use in a RAID storage controller of a RAID storage subsystem , said DMA controller comprising : means for transferring a data portion of a stripe through said DMA controller from a random access source memory to a destination memory , wherein said stripe is stored in a predetermined first order in said source memory and wherein said stripe is transferred to said destination memory in a predetermined second order (Advanced Technology) different from said predetermined first order ;
and means for computing , within said DMA controller , a plurality of XOR parity segments corresponding to said stripe , wherein said means for computing and said means for transferring are operable substantially simultaneously , wherein said stripe is comprised of a plurality of blocks and wherein each block is comprised of a plurality of segments , and wherein said means for transferring further comprises : means for transferring a first data segment of said plurality of data segments of a data block of said plurality of data blocks of said stripe ;
means for transferring a corresponding data segment of said plurality of data segments of a next data block of said plurality of data blocks ;
buffer means for storing XOR parity generated by said means for computing ;
first means for repeating operation of said means for transferring a corresponding data segment and operation of said means for storing for each data block of said stripe until each corresponding data segment of each block of said plurality of data blocks of said stripe have been transferred ;
and first means for repeating operation of said means for transferring a first data segment and operation of said means for transferring a corresponding data segment and operation of said means for storing and operation of said means for repeating for a next data segment of said plurality of data segments in each of said plurality of blocks in said data portion of said stripe until all of said plurality of data segments have been transferred .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (said memory, store data) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client (said memory, store data) that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
US6151641A
CLAIM 7
. The DMA controller of claim 6 wherein said XOR buffer circuit includes : first means for controlling said memory (store data (store data, storing data, storage client) , storing data, storage client) to store data captured during transfer of said plurality of data segments in said memory ;
second means for controlling said memory and said XOR generation means to compute the bitwise XOR of data previously stored in said memory and data captured during transfer of said plurality of data segments and to store said bitwise XOR result in said memory ;
and third means for controlling said memory to read the contents of said memory for purposes of transferring parity data from said memory to said destination memory .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client (said memory, store data) ;

a storage processor coupled to the storage interface ;

a flash memory device (storage subsystem) coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US6151641A
CLAIM 1
. In a DMA controller of a RAID storage controller in a RAID storage subsystem (flash memory device) , a method to compute parity comprising the steps of : transferring a data portion of a stripe from a host system to a RAID storage subsystem through said DMA controller from a random access source memory to a destination memory , wherein said data portion of said stripe is comprised of a plurality of data blocks wherein each of said plurality of data blocks is comprised of a plurality of data segments , and wherein said plurality of data segments are stored in said source memory in a first predetermined order and wherein said data segments are transferred to said destination memory in a second predetermined order different from said first predetermined order ;
and computing , within said DMA controller , a plurality of XOR parity segments corresponding to said plurality of data segments , wherein the step of transferring a data portion of a stripe further comprises the steps of : a) transferring a first data segment of said plurality of data segments of a data block of said plurality of data blocks of said stripe ;
b) transferring a corresponding data segment of said plurality of data segments of a next data block of said plurality of data blocks ;
c) storing XOR parity generated by said computing step in a buffer ;
d) repeating steps b) and c) for each data block of said stripe until each corresponding data segment of each block of said plurality of data blocks of said stripe have been transferred ;
and e) repeating steps a) through d) for a next data segment of said plurality of data segments in each of said plurality of blocks in said data portion of said stripe until all of said plurality of data segments have been transferred , and wherein the computing step is performed substantially simultaneously with said step of transferring .

US6151641A
CLAIM 7
. The DMA controller of claim 6 wherein said XOR buffer circuit includes : first means for controlling said memory (store data (store data, storing data, storage client) , storing data, storage client) to store data captured during transfer of said plurality of data segments in said memory ;
second means for controlling said memory and said XOR generation means to compute the bitwise XOR of data previously stored in said memory and data captured during transfer of said plurality of data segments and to store said bitwise XOR result in said memory ;
and third means for controlling said memory to read the contents of said memory for purposes of transferring parity data from said memory to said destination memory .

US9632727B2
CLAIM 13
. The system of claim 12 , wherein the logical-to-physical translation layer is stored in the flash memory device (storage subsystem) .
US6151641A
CLAIM 1
. In a DMA controller of a RAID storage controller in a RAID storage subsystem (flash memory device) , a method to compute parity comprising the steps of : transferring a data portion of a stripe from a host system to a RAID storage subsystem through said DMA controller from a random access source memory to a destination memory , wherein said data portion of said stripe is comprised of a plurality of data blocks wherein each of said plurality of data blocks is comprised of a plurality of data segments , and wherein said plurality of data segments are stored in said source memory in a first predetermined order and wherein said data segments are transferred to said destination memory in a second predetermined order different from said first predetermined order ;
and computing , within said DMA controller , a plurality of XOR parity segments corresponding to said plurality of data segments , wherein the step of transferring a data portion of a stripe further comprises the steps of : a) transferring a first data segment of said plurality of data segments of a data block of said plurality of data blocks of said stripe ;
b) transferring a corresponding data segment of said plurality of data segments of a next data block of said plurality of data blocks ;
c) storing XOR parity generated by said computing step in a buffer ;
d) repeating steps b) and c) for each data block of said stripe until each corresponding data segment of each block of said plurality of data blocks of said stripe have been transferred ;
and e) repeating steps a) through d) for a next data segment of said plurality of data segments in each of said plurality of blocks in said data portion of said stripe until all of said plurality of data segments have been transferred , and wherein the computing step is performed substantially simultaneously with said step of transferring .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request (n information) specifying one or more logical addresses included in the empty-block directive command , the storage processor returns a predetermined data string (next data) .
US6151641A
CLAIM 1
. In a DMA controller of a RAID storage controller in a RAID storage subsystem , a method to compute parity comprising the steps of : transferring a data portion of a stripe from a host system to a RAID storage subsystem through said DMA controller from a random access source memory to a destination memory , wherein said data portion of said stripe is comprised of a plurality of data blocks wherein each of said plurality of data blocks is comprised of a plurality of data segments , and wherein said plurality of data segments are stored in said source memory in a first predetermined order and wherein said data segments are transferred to said destination memory in a second predetermined order different from said first predetermined order ;
and computing , within said DMA controller , a plurality of XOR parity segments corresponding to said plurality of data segments , wherein the step of transferring a data portion of a stripe further comprises the steps of : a) transferring a first data segment of said plurality of data segments of a data block of said plurality of data blocks of said stripe ;
b) transferring a corresponding data segment of said plurality of data segments of a next data (data string) block of said plurality of data blocks ;
c) storing XOR parity generated by said computing step in a buffer ;
d) repeating steps b) and c) for each data block of said stripe until each corresponding data segment of each block of said plurality of data blocks of said stripe have been transferred ;
and e) repeating steps a) through d) for a next data segment of said plurality of data segments in each of said plurality of blocks in said data portion of said stripe until all of said plurality of data segments have been transferred , and wherein the computing step is performed substantially simultaneously with said step of transferring .

US6151641A
CLAIM 12
. A system within a RAID storage system controller for performing transfer of a RAID stripe substantially simultaneous with computation of error detection and correction information (read request) , said system comprising : a DMA transfer controller for transferring said RAID stripe stored in a first predetermined order a random access source memory to a destination memory in a second predetermined order ;
and an error detection and correction computation element coupled to said DMA transfer controller for computing said error detection and correction information substantially simultaneously with the transfer of said RAID stripe by said DMA transfer controller , wherein said RAID stripe is comprised of a plurality of data blocks wherein each of said plurality of data blocks is comprised of a plurality of data segments , and wherein said DMA transfer controller is controllably operable to : a) transfer a first data segment of said plurality of data segments of a data block of said plurality of data blocks of said stripe ;
b) transfer a corresponding data segment of said plurality of data segments of a next data block of said plurality of data blocks ;
c) store XOR parity generated by said computing step in a buffer ;
d) repeat steps b) and c) for each data block of said stripe until each corresponding data segment of each block of said plurality of data blocks of said stripe have been transferred ;
and e) repeat steps a) through d) for a next data segment of said plurality of data segments in each of said plurality of blocks in said data portion of said stripe until all of said plurality of data segments have been transferred .

US9632727B2
CLAIM 16
. The system of claim 15 , wherein data bits of the predetermined data string (next data) have a uniform logic level .
US6151641A
CLAIM 1
. In a DMA controller of a RAID storage controller in a RAID storage subsystem , a method to compute parity comprising the steps of : transferring a data portion of a stripe from a host system to a RAID storage subsystem through said DMA controller from a random access source memory to a destination memory , wherein said data portion of said stripe is comprised of a plurality of data blocks wherein each of said plurality of data blocks is comprised of a plurality of data segments , and wherein said plurality of data segments are stored in said source memory in a first predetermined order and wherein said data segments are transferred to said destination memory in a second predetermined order different from said first predetermined order ;
and computing , within said DMA controller , a plurality of XOR parity segments corresponding to said plurality of data segments , wherein the step of transferring a data portion of a stripe further comprises the steps of : a) transferring a first data segment of said plurality of data segments of a data block of said plurality of data blocks of said stripe ;
b) transferring a corresponding data segment of said plurality of data segments of a next data (data string) block of said plurality of data blocks ;
c) storing XOR parity generated by said computing step in a buffer ;
d) repeating steps b) and c) for each data block of said stripe until each corresponding data segment of each block of said plurality of data blocks of said stripe have been transferred ;
and e) repeating steps a) through d) for a next data segment of said plurality of data segments in each of said plurality of blocks in said data portion of said stripe until all of said plurality of data segments have been transferred , and wherein the computing step is performed substantially simultaneously with said step of transferring .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US6000006A

Filed: 1997-08-25     Issued: 1999-12-07

Unified re-map and cache-index table with dual write-counters for wear-leveling of non-volatile flash RAM mass storage

(Original Assignee) BIT Microsystems Inc     (Current Assignee) Bitmicro LLC

Ricardo H. Bruce, Rolando H. Bruce, Earl T. Cohen, Allan J. Christie
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system , including storing data (address translation) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US6000006A
CLAIM 1
. A unified re-mapping table for a flash-memory system , the unified re-mapping table comprising : a plurality of entries , an entry in the plurality of entries selected by a logical address from a host system , each entry in the plurality of entries having : a physical-block-address field containing a physical block address of a block in an array of flash-memory devices , each flash-memory device containing non-volatile storage cells that retain data when a power supply is no longer applied to the flash-memory device ;
a total-write-counter field for indicating a total number of write-erase cycles of the block identified by the physical-block-address field ;
an incremental-write-counter field for indicating an incremental number of write-erase cycles since a wear-leveling operation for the block ;
wherein both the total number and the incremental number from the entry must exceed thresholds to initiate wear-leveling for the block ;
wherein the block is wear-leveled by moving the physical block address and the total number to a different entry in the unified re-mapping table when data is exchanged between blocks , wherein the flash-memory system further comprises : a total-threshold resister containing a total-write threshold for the flash-memory system ;
an incremental-threshold register containing an incremental-write threshold for the flash-memory system ;
total compare means , coupled to the total-threshold register and receiving the total number from the entry selected by a current logical address , for activating a first signal when the total number from the entry in the unified re-mapping table exceeds the total-write threshold ;
incremental compare means , coupled to the incremental-threshold register and receiving the incremental number from the entry selected by the current logical address , for activating a second signal when the incremental number from the entry in the unified re-mapping table exceeds the incremental-write threshold ;
wear-leveling means , activated by a write to the current logical address when both the first signal and the second signal are activated , for wear-leveling the block by moving the physical block address and the total number to a different entry in the unified re-mapping table , and for replacing the physical block address with a new physical block address for a physical block having a smaller total number of write-erase cycles , whereby the total number from the entry must exceed the total-write threshold and the incremental number must exceed the incremental-write threshold to initiate wear-leveling and whereby each entry includes the physical block address for address translation (storing data) to the flash-memory devices and two write-counters for wear-leveling .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA (host system) bus interface , a Small Computer (non-volatile storage, lock point) System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
US6000006A
CLAIM 1
. A unified re-mapping table for a flash-memory system , the unified re-mapping table comprising : a plurality of entries , an entry in the plurality of entries selected by a logical address from a host system (external SATA, external SATA bus interface) , each entry in the plurality of entries having : a physical-block-address field containing a physical block address of a block in an array of flash-memory devices , each flash-memory device containing non-volatile storage (uniform logic, Small Computer, Small Computer System Interface, uniform logic level) cells that retain data when a power supply is no longer applied to the flash-memory device ;
a total-write-counter field for indicating a total number of write-erase cycles of the block identified by the physical-block-address field ;
an incremental-write-counter field for indicating an incremental number of write-erase cycles since a wear-leveling operation for the block ;
wherein both the total number and the incremental number from the entry must exceed thresholds to initiate wear-leveling for the block ;
wherein the block is wear-leveled by moving the physical block address and the total number to a different entry in the unified re-mapping table when data is exchanged between blocks , wherein the flash-memory system further comprises : a total-threshold resister containing a total-write threshold for the flash-memory system ;
an incremental-threshold register containing an incremental-write threshold for the flash-memory system ;
total compare means , coupled to the total-threshold register and receiving the total number from the entry selected by a current logical address , for activating a first signal when the total number from the entry in the unified re-mapping table exceeds the total-write threshold ;
incremental compare means , coupled to the incremental-threshold register and receiving the incremental number from the entry selected by the current logical address , for activating a second signal when the incremental number from the entry in the unified re-mapping table exceeds the incremental-write threshold ;
wear-leveling means , activated by a write to the current logical address when both the first signal and the second signal are activated , for wear-leveling the block by moving the physical block address and the total number to a different entry in the unified re-mapping table , and for replacing the physical block address with a new physical block address for a physical block having a smaller total number of write-erase cycles , whereby the total number from the entry must exceed the total-write threshold and the incremental number must exceed the incremental-write threshold to initiate wear-leveling and whereby each entry includes the physical block address for address translation to the flash-memory devices and two write-counters for wear-leveling .

US6000006A
CLAIM 5
. The unified re-mapping table for a flash-memory system of claim 4 wherein the one byte for mapping for each page in a block of pages is combined with the one byte for mapping for other pages in the block to form a block point (uniform logic, Small Computer, Small Computer System Interface, uniform logic level) er , the block pointer containing a copy of the total number and the incremental number of writes from the entry in the unified re-mapping table for the block , whereby the block pointer contains the total number and incremental number for all pages in the block .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (address translation) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
US6000006A
CLAIM 1
. A unified re-mapping table for a flash-memory system , the unified re-mapping table comprising : a plurality of entries , an entry in the plurality of entries selected by a logical address from a host system , each entry in the plurality of entries having : a physical-block-address field containing a physical block address of a block in an array of flash-memory devices , each flash-memory device containing non-volatile storage cells that retain data when a power supply is no longer applied to the flash-memory device ;
a total-write-counter field for indicating a total number of write-erase cycles of the block identified by the physical-block-address field ;
an incremental-write-counter field for indicating an incremental number of write-erase cycles since a wear-leveling operation for the block ;
wherein both the total number and the incremental number from the entry must exceed thresholds to initiate wear-leveling for the block ;
wherein the block is wear-leveled by moving the physical block address and the total number to a different entry in the unified re-mapping table when data is exchanged between blocks , wherein the flash-memory system further comprises : a total-threshold resister containing a total-write threshold for the flash-memory system ;
an incremental-threshold register containing an incremental-write threshold for the flash-memory system ;
total compare means , coupled to the total-threshold register and receiving the total number from the entry selected by a current logical address , for activating a first signal when the total number from the entry in the unified re-mapping table exceeds the total-write threshold ;
incremental compare means , coupled to the incremental-threshold register and receiving the incremental number from the entry selected by the current logical address , for activating a second signal when the incremental number from the entry in the unified re-mapping table exceeds the incremental-write threshold ;
wear-leveling means , activated by a write to the current logical address when both the first signal and the second signal are activated , for wear-leveling the block by moving the physical block address and the total number to a different entry in the unified re-mapping table , and for replacing the physical block address with a new physical block address for a physical block having a smaller total number of write-erase cycles , whereby the total number from the entry must exceed the total-write threshold and the incremental number must exceed the incremental-write threshold to initiate wear-leveling and whereby each entry includes the physical block address for address translation (storing data) to the flash-memory devices and two write-counters for wear-leveling .

US9632727B2
CLAIM 16
. The system of claim 15 , wherein data bits of the predetermined data string have a uniform logic (non-volatile storage, lock point) level .
US6000006A
CLAIM 1
. A unified re-mapping table for a flash-memory system , the unified re-mapping table comprising : a plurality of entries , an entry in the plurality of entries selected by a logical address from a host system , each entry in the plurality of entries having : a physical-block-address field containing a physical block address of a block in an array of flash-memory devices , each flash-memory device containing non-volatile storage (uniform logic, Small Computer, Small Computer System Interface, uniform logic level) cells that retain data when a power supply is no longer applied to the flash-memory device ;
a total-write-counter field for indicating a total number of write-erase cycles of the block identified by the physical-block-address field ;
an incremental-write-counter field for indicating an incremental number of write-erase cycles since a wear-leveling operation for the block ;
wherein both the total number and the incremental number from the entry must exceed thresholds to initiate wear-leveling for the block ;
wherein the block is wear-leveled by moving the physical block address and the total number to a different entry in the unified re-mapping table when data is exchanged between blocks , wherein the flash-memory system further comprises : a total-threshold resister containing a total-write threshold for the flash-memory system ;
an incremental-threshold register containing an incremental-write threshold for the flash-memory system ;
total compare means , coupled to the total-threshold register and receiving the total number from the entry selected by a current logical address , for activating a first signal when the total number from the entry in the unified re-mapping table exceeds the total-write threshold ;
incremental compare means , coupled to the incremental-threshold register and receiving the incremental number from the entry selected by the current logical address , for activating a second signal when the incremental number from the entry in the unified re-mapping table exceeds the incremental-write threshold ;
wear-leveling means , activated by a write to the current logical address when both the first signal and the second signal are activated , for wear-leveling the block by moving the physical block address and the total number to a different entry in the unified re-mapping table , and for replacing the physical block address with a new physical block address for a physical block having a smaller total number of write-erase cycles , whereby the total number from the entry must exceed the total-write threshold and the incremental number must exceed the incremental-write threshold to initiate wear-leveling and whereby each entry includes the physical block address for address translation to the flash-memory devices and two write-counters for wear-leveling .

US6000006A
CLAIM 5
. The unified re-mapping table for a flash-memory system of claim 4 wherein the one byte for mapping for each page in a block of pages is combined with the one byte for mapping for other pages in the block to form a block point (uniform logic, Small Computer, Small Computer System Interface, uniform logic level) er , the block pointer containing a copy of the total number and the incremental number of writes from the entry in the unified re-mapping table for the block , whereby the block pointer contains the total number and incremental number for all pages in the block .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US6424872B1

Filed: 1997-08-21     Issued: 2002-07-23

Block oriented control system

(Original Assignee) Fieldbus Foundation     (Current Assignee) Fieldcomm Group Inc

David A. Glanzer, Terrance L. Blevins, Ram Ramachandran, Kenneth D. Krivoshein, Patricia E. Brett, Jack Elias, William R. Hodson, Frank Lynch, Ashok K. Gupta, Lee A. Neitzel, Thomas B. Kinney, Chuji Akiyama, Yasuo Kumeda, Hiroshi Mori, Mitsugu Tanaka
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system , including storing data (computer program, storing data) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US6424872B1
CLAIM 1
. An apparatus for operating in an open control system comprising : a memory , which includes system management data and a function block ;
wherein the system management data includes a system schedule ;
wherein the function block includes parameters and a computer program (storing data) ;
a processor , operably connected to the memory , wherein the processor executes the function block based on the system schedule ;
and a medium attachment unit , which translates input messages and output messages between the processor and a transmission medium .

US6424872B1
CLAIM 43
. A memory for storing data (storing data) for access by an application framework operating in a device within a control system , the memory comprising : a data structure stored in the memory , the data structure including : a resource block , which makes hardware specific characteristics of the device electronically readable ;
an encapsulated function block , wherein the function block includes a program and parameters ;
and at least one transducer block , wherein the at least one transducer block controls access to the function block .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface (controls access) , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface (controls access) , and a Fibre Channel interface .
US6424872B1
CLAIM 43
. A memory for storing data for access by an application framework operating in a device within a control system , the memory comprising : a data structure stored in the memory , the data structure including : a resource block , which makes hardware specific characteristics of the device electronically readable ;
an encapsulated function block , wherein the function block includes a program and parameters ;
and at least one transducer block , wherein the at least one transducer block controls access (external SATA bus interface, internet SCSI interface) to the function block .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (computer program, storing data) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
US6424872B1
CLAIM 1
. An apparatus for operating in an open control system comprising : a memory , which includes system management data and a function block ;
wherein the system management data includes a system schedule ;
wherein the function block includes parameters and a computer program (storing data) ;
a processor , operably connected to the memory , wherein the processor executes the function block based on the system schedule ;
and a medium attachment unit , which translates input messages and output messages between the processor and a transmission medium .

US6424872B1
CLAIM 43
. A memory for storing data (storing data) for access by an application framework operating in a device within a control system , the memory comprising : a data structure stored in the memory , the data structure including : a resource block , which makes hardware specific characteristics of the device electronically readable ;
an encapsulated function block , wherein the function block includes a program and parameters ;
and at least one transducer block , wherein the at least one transducer block controls access to the function block .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request (n information) specifying one or more logical addresses included in the empty-block directive command , the storage processor returns a predetermined data string .
US6424872B1
CLAIM 20
. The apparatus of claim 18 wherein the object dictionary includes object descriptions and the object descriptions contain information (read request) which describes data types and structures .

US9632727B2
CLAIM 16
. The system of claim 15 , wherein data bits (system time) of the predetermined data string have a uniform logic level .
US6424872B1
CLAIM 10
. The apparatus of claim 1 wherein the processor maintains a system time (data bits) , and wherein the system time is periodically published on the transmission medium .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US6044438A

Filed: 1997-07-10     Issued: 2000-03-28

Memory controller for controlling memory accesses across networks in distributed shared memory processing systems

(Original Assignee) International Business Machines Corp     (Current Assignee) International Business Machines Corp

Howard Thomas Olnowich
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system (interrupt signal) , the message indicating that the identified logical address is erased .
US6044438A
CLAIM 3
. A memory controller for a local node of a shared memory parallel processing system , said node including a node processor , a node memory , a node cache and an I/O adapter , said system including a multi-stage switching network for communications amongst said local node and a plurality of remote nodes , said node memory including a changeable portion and an unchangeable portion ;
said memory controller comprising : first means responsive to a request by said processor for access to a memory word for first accessing said node cache of said local node ;
second means responsive to said first means being unable to access said memory word in said node cache for accessing said memory word selectively from a cache line in said node memory or remote memory and storing said cache line to said node cache ;
and remote fetch interrupt means for issuing an interrupt signal (host operating system) to said node processor upon determining that said memory word is located in remote memory for causing said node processor to switch from a first instruction stream thread to a second instruction stream thread .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request (read request) specifying one or more logical addresses included in the empty-block directive command , the storage processor returns a predetermined data string .
US6044438A
CLAIM 4
. A memory controller for a local node of a shared memory parallel processing system , said node including a node processor , a node memory , a node cache and an I/O adapter , said system including a multi-stage switching network for communications amongst said local node and a plurality of remote nodes , said node memory including a changeable portion and an unchangeable portion ;
said memory controller comprising : first means responsive to a request by said processor for access to a memory word for first accessing said node cache of said local node ;
second means responsive to said first means being unable to access said memory word in said node cache for accessing said memory word selectively from a cache line in said node memory or remote memory and storing said cache line to said node cache ;
and data message generation means responsive to a request from a remote node for accessing a cache line identified by a remote request read address for generating a read response message to return the accessed cache line to said remote node , said read response message including a message header comprising message differentiation indicia for defining said read request (read request) message type ;
destination node indicia equal to the sector segment of said node memory for said addressed memory word ;
source node indicia set to the node ID number of the local node ;
message length indicia for defining said read request message as being comprised of said message header only ;
and memory address indicia for specifying the memory address of said memory word ;
said data message generation means further operable for delivering said read response message to a read send FIFO of said network adapter for transmission to said network and the remote node selected by said destination node indicia .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US6092158A

Filed: 1997-06-13     Issued: 2000-07-18

Method and apparatus for arbitrating between command streams

(Original Assignee) Intel Corp     (Current Assignee) Intel Corp

David J. Harriman, Brian K. Langendorf, Jasmin Ajanovic
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system , including storing data (said memory, main memory) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data (said memory, main memory) pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US6092158A
CLAIM 9
. A system comprising : a main memory (store data, storing data) ;
a bus agent configured to generate a plurality of commands to access said main memory ;
a processor ;
and a memory controller coupled to said processor , said main memory , and coupled to receive said plurality of commands from said bus agent , said memory (store data, storing data) controller including a normal priority read queue ;
a normal priority write queue ;
a high priority read and write queue ;
said memory controller to unblock high priority write commands from said bus agent by elevating a priority level for all write commands in either the normal priority write queue or the high priority read and write queue prior to a blocked high priority write command , and to select an available high priority read command over an available high priority write command unless said available high priority write command is a blocked high priority write command .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (order r) (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
US6092158A
CLAIM 2
. The memory controller of claim 1 wherein said arbitration logic comprises : a read arbiter coupled to reorder r (Small Computer System Interface, data string, storage interface to accept requests to perform storage operations) ead commands from said normal priority read command queue ;
a write and priority arbiter coupled to select commands from said normal priority write command queue and said priority command queue ;
and a command stream arbiter coupled to select commands from said read arbiter and said write and priority arbiter .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (said memory, main memory) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
US6092158A
CLAIM 9
. A system comprising : a main memory (store data, storing data) ;
a bus agent configured to generate a plurality of commands to access said main memory ;
a processor ;
and a memory controller coupled to said processor , said main memory , and coupled to receive said plurality of commands from said bus agent , said memory (store data, storing data) controller including a normal priority read queue ;
a normal priority write queue ;
a high priority read and write queue ;
said memory controller to unblock high priority write commands from said bus agent by elevating a priority level for all write commands in either the normal priority write queue or the high priority read and write queue prior to a blocked high priority write command , and to select an available high priority read command over an available high priority write command unless said available high priority write command is a blocked high priority write command .

US9632727B2
CLAIM 8
. The system of claim 7 , further comprising means for providing a storage interface to accept requests to perform storage operations (order r) on the solid-state storage medium in reference to the logical blocks and to accept the message identifying the logical block that is not being used to reference data stored on the solid-state storage medium .
US6092158A
CLAIM 2
. The memory controller of claim 1 wherein said arbitration logic comprises : a read arbiter coupled to reorder r (Small Computer System Interface, data string, storage interface to accept requests to perform storage operations) ead commands from said normal priority read command queue ;
a write and priority arbiter coupled to select commands from said normal priority write command queue and said priority command queue ;
and a command stream arbiter coupled to select commands from said read arbiter and said write and priority arbiter .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor (received write command, memory circuit) coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US6092158A
CLAIM 17
. A method of ordering commands which are received from a graphics accelerator and dispatched to a memory circuit (storage processer, storage processor) , the method comprising the steps of : receiving a plurality of read commands ;
selecting at least one of said plurality of read commands ;
receiving a plurality of write commands ;
receiving a blocked write command which is blocked by said plurality of write commands by : queuing a received write command (storage processer, storage processor) in a queue ;
and testing whether said received write command is blocked when said received write command reaches a head of said queue ;
and unblocking , prior to completing said plurality of read commands , said blocked write command by elevating a priority level for any write commands which are queued prior to said blocked write command , and selecting said write commands which are queued prior to said blocked write command .

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (received write command, memory circuit) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
US6092158A
CLAIM 17
. A method of ordering commands which are received from a graphics accelerator and dispatched to a memory circuit (storage processer, storage processor) , the method comprising the steps of : receiving a plurality of read commands ;
selecting at least one of said plurality of read commands ;
receiving a plurality of write commands ;
receiving a blocked write command which is blocked by said plurality of write commands by : queuing a received write command (storage processer, storage processor) in a queue ;
and testing whether said received write command is blocked when said received write command reaches a head of said queue ;
and unblocking , prior to completing said plurality of read commands , said blocked write command by elevating a priority level for any write commands which are queued prior to said blocked write command , and selecting said write commands which are queued prior to said blocked write command .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer (received write command, memory circuit) is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor (received write command, memory circuit) returns a predetermined data string (order r) .
US6092158A
CLAIM 2
. The memory controller of claim 1 wherein said arbitration logic comprises : a read arbiter coupled to reorder r (Small Computer System Interface, data string, storage interface to accept requests to perform storage operations) ead commands from said normal priority read command queue ;
a write and priority arbiter coupled to select commands from said normal priority write command queue and said priority command queue ;
and a command stream arbiter coupled to select commands from said read arbiter and said write and priority arbiter .

US6092158A
CLAIM 17
. A method of ordering commands which are received from a graphics accelerator and dispatched to a memory circuit (storage processer, storage processor) , the method comprising the steps of : receiving a plurality of read commands ;
selecting at least one of said plurality of read commands ;
receiving a plurality of write commands ;
receiving a blocked write command which is blocked by said plurality of write commands by : queuing a received write command (storage processer, storage processor) in a queue ;
and testing whether said received write command is blocked when said received write command reaches a head of said queue ;
and unblocking , prior to completing said plurality of read commands , said blocked write command by elevating a priority level for any write commands which are queued prior to said blocked write command , and selecting said write commands which are queued prior to said blocked write command .

US9632727B2
CLAIM 16
. The system of claim 15 , wherein data bits of the predetermined data string (order r) have a uniform logic level .
US6092158A
CLAIM 2
. The memory controller of claim 1 wherein said arbitration logic comprises : a read arbiter coupled to reorder r (Small Computer System Interface, data string, storage interface to accept requests to perform storage operations) ead commands from said normal priority read command queue ;
a write and priority arbiter coupled to select commands from said normal priority write command queue and said priority command queue ;
and a command stream arbiter coupled to select commands from said read arbiter and said write and priority arbiter .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
JPH10301719A

Filed: 1997-04-28     Issued: 1998-11-13

ディスクアレイ装置及びそれを用いた情報処理システム

(Original Assignee) Yamaha Corp; ヤマハ株式会社     

Nobukazu Toba, 伸和 鳥羽
US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface (ホスト) , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
JPH10301719A
CLAIM 4
【請求項4】 ホスト (PCI Express bus interface) 装置と、このホスト装置の外部記 憶装置としてのディスクアレイ装置とを備えた情報処理 システムにおいて、 前記ディスクアレイ装置は、複数台のディスク装置に情 報を分散的に記憶させると共にいずれかのディスク装置 が故障したときに他のディスク装置から当該故障したデ ィスク装置に記憶された情報を復元して予備のディスク 装置に記憶し、且ついずれかのディスク装置が故障した ことを知らせる故障情報を前記ホスト装置に通知するた めの故障通知手段を備えたものであり、 前記ホスト装置は、前記故障通知手段から通知された故 障情報に基づいて上位のアプリケーションを起動して管 理者にいずれかのディスク装置が故障したことを通知す るための通知ドライバを備えたものであることを特徴と する情報処理システム。

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one (する情報) or more logical addresses included in the empty-block directive command , the storage processor returns a predetermined data string .
JPH10301719A
CLAIM 4
【請求項4】 ホスト装置と、このホスト装置の外部記 憶装置としてのディスクアレイ装置とを備えた情報処理 システムにおいて、 前記ディスクアレイ装置は、複数台のディスク装置に情 報を分散的に記憶させると共にいずれかのディスク装置 が故障したときに他のディスク装置から当該故障したデ ィスク装置に記憶された情報を復元して予備のディスク 装置に記憶し、且ついずれかのディスク装置が故障した ことを知らせる故障情報を前記ホスト装置に通知するた めの故障通知手段を備えたものであり、 前記ホスト装置は、前記故障通知手段から通知された故 障情報に基づいて上位のアプリケーションを起動して管 理者にいずれかのディスク装置が故障したことを通知す るための通知ドライバを備えたものであることを特徴と する情報 (read request specifying one) 処理システム。




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US5907856A

Filed: 1997-03-31     Issued: 1999-05-25

Moving sectors within a block of information in a flash memory mass storage architecture

(Original Assignee) Lexar Media Inc     (Current Assignee) Micron Technology Inc

Petro Estakhri, Berhau Iman, Ali R. Ganjuei
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium (write operation) in response to requests from a computer system , including storing data (storing information, said memory, more sector) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data (storing information, said memory, more sector) pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US5907856A
CLAIM 1
. A storage device having nonvolatile memory and being coupled to a host for storing information (store data, storing data) , organized in blocks in the nonvolatile memory , each block having associated therewith a logical block address (LBA) and a physical block address (PBA) , the LBA provided by the host to the storage device for identifying a block to be accessed , the PBA developed by the storage device for identifying a free location within the nonvolatile memory wherein the accessed block is be stored , a stored block within the nonvolatile being selectively erasable and further having one or more sector (store data, storing data) s , the storage device comprising : a . a memory device for storing a table defined by n LBA rows , each of the LBA rows being uniquely addressable by an LBA and for storing a virtual PBA for identifying the location of the stored block , a move virtual PBA for identifying the location of a portion of the stored block , and status information including flag means for indicating whether any sectors of the stored block have been moved to the move virtual PBA location within the nonvolatile memory ;
b . means for receiving from the host , a block of information identified by a particular LBA to be stored in the nonvolatile memory , for developing the virtual PBA if the particular LBA is " ;
unused" ;
and for developing the move virtual PBA if the particular LBA is " ;
used" ;
;
wherein portions of a block may be stored in more than one PBA-identified location within the nonvolatile memory to avoid an erase operation each time the host writes to the storage device and to avoid transfer of the entire block to a free location within the nonvolatile memory each time a portion of the block is being re-written .

US5907856A
CLAIM 12
. A storage device as recited in claim 1 wherein said memory (store data, storing data) device is comprised of volatile memory .

US5907856A
CLAIM 14
. In a storage device for use with a host , the storage device having a controller and one or more flash memory devices , a method for accessing information within the flash memory devices under the direction of the controller , the information organized in sectors with one or more sectors defining a block wherein each block is selectively erasable having associated therewith an LBA (Logical Block Address) provided by the host and a PBA (Physical Block Address) developed by the controller for identifying an unused location within the flash memory devices wherein a sector may be stored , the method comprising : (a) allocating a table within the controller defined by rows , each row being individually addressable by an LBA and configured to store a virtual PBA , a moved virtual PBA , and status information for use in determining the location of a sector that has been moved from the virtual PBA to the moved virtual PBA within the flash memory devices ;
(b) providing to the controller , a particular LBA identifying a block being accessed by the host ;
(c) developing a PBA in association with the particular LBA ;
(d) using the particular LBA to address an LBA row ;
(e) storing the PBA associated with the particular LBA in the addressed LBA row ;
(f) upon further access of the block identified by the particular LBA , developing a moved virtual PBA ;
(g) storing the moved virtual PBA in the addressed LBA row ;
and (h) modifying the status information of the addressed LBA row to indicate whether any sectors within the addressed LBA row have been moved ;
wherein sectors of a block are moved to unused locations within the flash memory devices to avoid erase-before-write operation (solid state storage medium) s each time the block is accessed .

US9632727B2
CLAIM 5
. The apparatus of claim 1 , further comprising a garbage collector (logical block address) configured to designate that the physical address previously assigned to the identified logical address comprises data suitable for removal from the solid-state storage medium in response to the message .
US5907856A
CLAIM 1
. A storage device having nonvolatile memory and being coupled to a host for storing information , organized in blocks in the nonvolatile memory , each block having associated therewith a logical block address (garbage collector) (LBA) and a physical block address (PBA) , the LBA provided by the host to the storage device for identifying a block to be accessed , the PBA developed by the storage device for identifying a free location within the nonvolatile memory wherein the accessed block is be stored , a stored block within the nonvolatile being selectively erasable and further having one or more sectors , the storage device comprising : a . a memory device for storing a table defined by n LBA rows , each of the LBA rows being uniquely addressable by an LBA and for storing a virtual PBA for identifying the location of the stored block , a move virtual PBA for identifying the location of a portion of the stored block , and status information including flag means for indicating whether any sectors of the stored block have been moved to the move virtual PBA location within the nonvolatile memory ;
b . means for receiving from the host , a block of information identified by a particular LBA to be stored in the nonvolatile memory , for developing the virtual PBA if the particular LBA is " ;
unused" ;
and for developing the move virtual PBA if the particular LBA is " ;
used" ;
;
wherein portions of a block may be stored in more than one PBA-identified location within the nonvolatile memory to avoid an erase operation each time the host writes to the storage device and to avoid transfer of the entire block to a free location within the nonvolatile memory each time a portion of the block is being re-written .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one (first location) of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
US5907856A
CLAIM 17
. A controller device coupled to a host for storing information in nonvolatile memory , the information being organized in blocks with each block having associated therewith a logical block address (LBA) and a physical block address (PBA) , the LBA being provided by the host to the controller device for identifying a block to be accessed , the PBA being developed by the controller device for identifying a location within the nonvolatile memory wherein the accessed block is to be stored , a stored block within the nonvolatile memory being selectively erasable and further having one or more sectors , comprising : a . a memory device for storing a table defined by n LBA rows , each of the LBA rows being uniquely addressable by an LBA and for storing a virtual PBA for identifying a first location (bus interface comprises one) for storing a block within the nonvolatile memory , a move virtual PBA for identifying a second location for storing one or more sectors of the stored block within the nonvolatile memory , and status information including a flag for indicating whether any sectors of the stored block have been moved to the move virtual PBA location within the nonvolatile memory ;
b . controller means responsive to a command from the host and operative to store a block of information in the nonvolatile memory , the block being identified by a particular LBA , said controller being operative to develop a virtual PBA if the particular LBA is " ;
unused" ;
and to develop a move virtual PBA if the particular LBA is " ;
used" ;
, whereby said controller stores an LBA-identified block that may be accessed more than once by the host prior to erasure thereof , in more than one PBA-identified location within the nonvolatile memory thereby avoiding an erase operation each time the host writes to the controller device and avoiding transfer of an entire block to another location within the nonvolatile memory each time a portion of the block is re-written .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (storing information, said memory, more sector) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
US5907856A
CLAIM 1
. A storage device having nonvolatile memory and being coupled to a host for storing information (store data, storing data) , organized in blocks in the nonvolatile memory , each block having associated therewith a logical block address (LBA) and a physical block address (PBA) , the LBA provided by the host to the storage device for identifying a block to be accessed , the PBA developed by the storage device for identifying a free location within the nonvolatile memory wherein the accessed block is be stored , a stored block within the nonvolatile being selectively erasable and further having one or more sector (store data, storing data) s , the storage device comprising : a . a memory device for storing a table defined by n LBA rows , each of the LBA rows being uniquely addressable by an LBA and for storing a virtual PBA for identifying the location of the stored block , a move virtual PBA for identifying the location of a portion of the stored block , and status information including flag means for indicating whether any sectors of the stored block have been moved to the move virtual PBA location within the nonvolatile memory ;
b . means for receiving from the host , a block of information identified by a particular LBA to be stored in the nonvolatile memory , for developing the virtual PBA if the particular LBA is " ;
unused" ;
and for developing the move virtual PBA if the particular LBA is " ;
used" ;
;
wherein portions of a block may be stored in more than one PBA-identified location within the nonvolatile memory to avoid an erase operation each time the host writes to the storage device and to avoid transfer of the entire block to a free location within the nonvolatile memory each time a portion of the block is being re-written .

US5907856A
CLAIM 12
. A storage device as recited in claim 1 wherein said memory (store data, storing data) device is comprised of volatile memory .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor coupled to the storage interface ;

a flash memory device (flash memory device) coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US5907856A
CLAIM 14
. In a storage device for use with a host , the storage device having a controller and one or more flash memory device (flash memory device) s , a method for accessing information within the flash memory devices under the direction of the controller , the information organized in sectors with one or more sectors defining a block wherein each block is selectively erasable having associated therewith an LBA (Logical Block Address) provided by the host and a PBA (Physical Block Address) developed by the controller for identifying an unused location within the flash memory devices wherein a sector may be stored , the method comprising : (a) allocating a table within the controller defined by rows , each row being individually addressable by an LBA and configured to store a virtual PBA , a moved virtual PBA , and status information for use in determining the location of a sector that has been moved from the virtual PBA to the moved virtual PBA within the flash memory devices ;
(b) providing to the controller , a particular LBA identifying a block being accessed by the host ;
(c) developing a PBA in association with the particular LBA ;
(d) using the particular LBA to address an LBA row ;
(e) storing the PBA associated with the particular LBA in the addressed LBA row ;
(f) upon further access of the block identified by the particular LBA , developing a moved virtual PBA ;
(g) storing the moved virtual PBA in the addressed LBA row ;
and (h) modifying the status information of the addressed LBA row to indicate whether any sectors within the addressed LBA row have been moved ;
wherein sectors of a block are moved to unused locations within the flash memory devices to avoid erase-before-write operations each time the block is accessed .

US9632727B2
CLAIM 13
. The system of claim 12 , wherein the logical-to-physical translation layer is stored in the flash memory device (flash memory device) .
US5907856A
CLAIM 14
. In a storage device for use with a host , the storage device having a controller and one or more flash memory device (flash memory device) s , a method for accessing information within the flash memory devices under the direction of the controller , the information organized in sectors with one or more sectors defining a block wherein each block is selectively erasable having associated therewith an LBA (Logical Block Address) provided by the host and a PBA (Physical Block Address) developed by the controller for identifying an unused location within the flash memory devices wherein a sector may be stored , the method comprising : (a) allocating a table within the controller defined by rows , each row being individually addressable by an LBA and configured to store a virtual PBA , a moved virtual PBA , and status information for use in determining the location of a sector that has been moved from the virtual PBA to the moved virtual PBA within the flash memory devices ;
(b) providing to the controller , a particular LBA identifying a block being accessed by the host ;
(c) developing a PBA in association with the particular LBA ;
(d) using the particular LBA to address an LBA row ;
(e) storing the PBA associated with the particular LBA in the addressed LBA row ;
(f) upon further access of the block identified by the particular LBA , developing a moved virtual PBA ;
(g) storing the moved virtual PBA in the addressed LBA row ;
and (h) modifying the status information of the addressed LBA row to indicate whether any sectors within the addressed LBA row have been moved ;
wherein sectors of a block are moved to unused locations within the flash memory devices to avoid erase-before-write operations each time the block is accessed .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US5961660A

Filed: 1997-03-03     Issued: 1999-10-05

Method and apparatus for optimizing ECC memory performance

(Original Assignee) International Business Machines Corp     (Current Assignee) International Business Machines Corp

Louis Bennie Capps, Jr., Thoi Nguyen
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system (computer system) , including storing data (said memory) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data (said memory) pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US5961660A
CLAIM 1
. A method , implemented in a computer system (computer system) , for providing user selection between ECC memory operation and parity memory operation on the same memory card , comprising the steps of : providing error checking and correction on data from an eight byte memory module in a memory controller in said computer system ;
providing parity checking on said data from said eight byte memory module in said memory (store data, storing data) controller in said computer system ;
enabling user selection between said error checking and correction and said parity checking on said memory controller using a programmable register ;
and executing said user selection on said data from said eight byte memory module using an eight bit byte connected to said memory module .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system (computer system) , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
US5961660A
CLAIM 1
. A method , implemented in a computer system (computer system) , for providing user selection between ECC memory operation and parity memory operation on the same memory card , comprising the steps of : providing error checking and correction on data from an eight byte memory module in a memory controller in said computer system ;
providing parity checking on said data from said eight byte memory module in said memory controller in said computer system ;
enabling user selection between said error checking and correction and said parity checking on said memory controller using a programmable register ;
and executing said user selection on said data from said eight byte memory module using an eight bit byte connected to said memory module .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (said memory) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
US5961660A
CLAIM 1
. A method , implemented in a computer system , for providing user selection between ECC memory operation and parity memory operation on the same memory card , comprising the steps of : providing error checking and correction on data from an eight byte memory module in a memory controller in said computer system ;
providing parity checking on said data from said eight byte memory module in said memory (store data, storing data) controller in said computer system ;
enabling user selection between said error checking and correction and said parity checking on said memory controller using a programmable register ;
and executing said user selection on said data from said eight byte memory module using an eight bit byte connected to said memory module .

US9632727B2
CLAIM 8
. The system of claim 7 , further comprising means for providing a storage interface (initial program) to accept requests to perform storage operations on the solid-state storage medium in reference to the logical blocks and to accept the message identifying the logical block that is not being used to reference data stored on the solid-state storage medium .
US5961660A
CLAIM 3
. The method of claim 2 wherein the step of inputting selection data further comprises : storing the configuration register on said memory controller in an NVRAM ;
and using the stored configuration register in said NVRAM to enable the memory controller for ECC or parity operation during initial program (storage interface) load of said computer system .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface (initial program) configured to communicate with a storage client ;

a storage processor coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US5961660A
CLAIM 3
. The method of claim 2 wherein the step of inputting selection data further comprises : storing the configuration register on said memory controller in an NVRAM ;
and using the stored configuration register in said NVRAM to enable the memory controller for ECC or parity operation during initial program (storage interface) load of said computer system .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request (same memory) specifying one or more logical addresses included in the empty-block directive command , the storage processor returns a predetermined data string .
US5961660A
CLAIM 1
. A method , implemented in a computer system , for providing user selection between ECC memory operation and parity memory operation on the same memory (read request) card , comprising the steps of : providing error checking and correction on data from an eight byte memory module in a memory controller in said computer system ;
providing parity checking on said data from said eight byte memory module in said memory controller in said computer system ;
enabling user selection between said error checking and correction and said parity checking on said memory controller using a programmable register ;
and executing said user selection on said data from said eight byte memory module using an eight bit byte connected to said memory module .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US6073232A

Filed: 1997-02-25     Issued: 2000-06-06

Method for minimizing a computer's initial program load time after a system reset or a power-on using non-volatile storage

(Original Assignee) International Business Machines Corp     (Current Assignee) International Business Machines Corp

Richard Mark Kroeker, Richard Henry Mandel, III
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium (hard disk) in response to requests from a computer system (computer system, stored data) , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US6073232A
CLAIM 20
. A method for causing a computer program stored in a data storage element in a peripheral storage apparatus of a computer system (computer system) to be loaded to a host computer , the method comprising the steps of : after power-up or reset , receiving a read command from the host computer for transferring a data record of a computer program stored on the data storage element to the host computer ;
in response to receiving , generating and storing in the peripheral storage apparatus a prefetch table representative of a storage location and length of the data record requested by the initial read command ;
after a subsequent power-on or reset of the peripheral storage apparatus , and during a second power-on or reset of the host computer , accessing by the peripheral storage apparatus the prefetch table to read the data record into the data cache ;
and in response to subsequent read commands from the host computer , determining whether records requested by the subsequent read commands are stored in the data cache , and if so , communicating the records from the data cache to the host computer , and otherwise communicating the records from the data storage element to the host computer .

US6073232A
CLAIM 28
. A disk drive , comprising : one or more read heads for reading from one or more disks of the disk drive ;
a data cache comprising a random access memory (RAM) ;
a controller ;
the controller being operative to execute the following steps after a power-up or reset of the disk drive and a host computer associated with the disk drive : receiving , from the host computer , a read command which requests data records of an application program stored on the one or more disks ;
generating and storing a prefetch table in the disk drive in response to receiving the read command , the prefetch table representing disk storage location and length of the data records requested by the read command ;
the controller being operative to execute the following steps for subsequent power-up or resets of the disk drive and host computer : receiving , from the host computer , a subsequent read command which requests data records stored on the one or more disks ;
prior to receiving the subsequent read command , identifying and locating the data records of the application program on the one or more disks based on the disk storage location and length represented in the prefetch table ;
prior to receiving the subsequent read command , and upon identifying and locating the data records , reading the data records of the application program from the one or more disks and storing them in the data cache ;
and in response to receiving the subsequent read command , communicating the prestored data (computer system) records of the application program from the data cache to the host computer if the subsequent read command requests those data records , and otherwise accessing data records from the one or more disks for communicating .

US6073232A
CLAIM 29
. The disk drive according to claim 28 , wherein the one or more disks comprise one or more hard disk (state storage medium, state storage system, storage processer) s and the disk drive comprises a hard drive .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system (computer system, stored data) , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology (when i) Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
US6073232A
CLAIM 2
. The computer program product of claim 1 , wherein accessing and determining are repeated for each power-on or reset of the host computer , the program means further causing the digital processing apparatus to : increment a read counter when i (Advanced Technology) t is determined that records requested by the subsequent read command are not stored in the data cache .

US6073232A
CLAIM 20
. A method for causing a computer program stored in a data storage element in a peripheral storage apparatus of a computer system (computer system) to be loaded to a host computer , the method comprising the steps of : after power-up or reset , receiving a read command from the host computer for transferring a data record of a computer program stored on the data storage element to the host computer ;
in response to receiving , generating and storing in the peripheral storage apparatus a prefetch table representative of a storage location and length of the data record requested by the initial read command ;
after a subsequent power-on or reset of the peripheral storage apparatus , and during a second power-on or reset of the host computer , accessing by the peripheral storage apparatus the prefetch table to read the data record into the data cache ;
and in response to subsequent read commands from the host computer , determining whether records requested by the subsequent read commands are stored in the data cache , and if so , communicating the records from the data cache to the host computer , and otherwise communicating the records from the data storage element to the host computer .

US6073232A
CLAIM 28
. A disk drive , comprising : one or more read heads for reading from one or more disks of the disk drive ;
a data cache comprising a random access memory (RAM) ;
a controller ;
the controller being operative to execute the following steps after a power-up or reset of the disk drive and a host computer associated with the disk drive : receiving , from the host computer , a read command which requests data records of an application program stored on the one or more disks ;
generating and storing a prefetch table in the disk drive in response to receiving the read command , the prefetch table representing disk storage location and length of the data records requested by the read command ;
the controller being operative to execute the following steps for subsequent power-up or resets of the disk drive and host computer : receiving , from the host computer , a subsequent read command which requests data records stored on the one or more disks ;
prior to receiving the subsequent read command , identifying and locating the data records of the application program on the one or more disks based on the disk storage location and length represented in the prefetch table ;
prior to receiving the subsequent read command , and upon identifying and locating the data records , reading the data records of the application program from the one or more disks and storing them in the data cache ;
and in response to receiving the subsequent read command , communicating the prestored data (computer system) records of the application program from the data cache to the host computer if the subsequent read command requests those data records , and otherwise accessing data records from the one or more disks for communicating .

US9632727B2
CLAIM 8
. The system of claim 7 , further comprising means for providing a storage interface (processing apparatus, following steps, initial program) to accept requests to perform storage operations on the solid-state storage medium in reference to the logical blocks and to accept the message identifying the logical block that is not being used to reference data stored on the solid-state storage medium .
US6073232A
CLAIM 1
. A computer program product for use with a peripheral storage apparatus including at least one data storage element and a data cache , comprising : a computer program storage medium readable by a digital processing apparatus (storage interface) ;
and a program means on the program storage medium and including instructions executable by the digital processing apparatus for causing the digital processing apparatus to copy data stored on the data storage element to the data cache by : after an initial power-up or reset of the peripheral storage apparatus and a host computer associated with the peripheral storage apparatus , receiving a read command from the host computer for transferring to the host computer a data record of a program stored on the data storage element ;
in response to receiving , generating and storing in the peripheral storage apparatus a prefetch table representative of a storage location and length of the data record requested by the initial read command ;
after a subsequent power-on or reset of the peripheral storage apparatus , and during a second power-on or reset of the host computer , accessing by the peripheral storage apparatus the prefetch table to read the data record into the data cache ;
and in response to subsequent read commands from the host computer , determining whether records requested by the subsequent read commands are stored in the data cache , and if so , communicating the records from the data cache to the host computer , and otherwise communicating the records from the data storage element to the host computer .

US6073232A
CLAIM 28
. A disk drive , comprising : one or more read heads for reading from one or more disks of the disk drive ;
a data cache comprising a random access memory (RAM) ;
a controller ;
the controller being operative to execute the following steps (storage interface) after a power-up or reset of the disk drive and a host computer associated with the disk drive : receiving , from the host computer , a read command which requests data records of an application program stored on the one or more disks ;
generating and storing a prefetch table in the disk drive in response to receiving the read command , the prefetch table representing disk storage location and length of the data records requested by the read command ;
the controller being operative to execute the following steps for subsequent power-up or resets of the disk drive and host computer : receiving , from the host computer , a subsequent read command which requests data records stored on the one or more disks ;
prior to receiving the subsequent read command , identifying and locating the data records of the application program on the one or more disks based on the disk storage location and length represented in the prefetch table ;
prior to receiving the subsequent read command , and upon identifying and locating the data records , reading the data records of the application program from the one or more disks and storing them in the data cache ;
and in response to receiving the subsequent read command , communicating the prestored data records of the application program from the data cache to the host computer if the subsequent read command requests those data records , and otherwise accessing data records from the one or more disks for communicating .

US6073232A
CLAIM 32
. A method for reducing an initial program (storage interface) load time with use of a hard drive , the method comprising : after a power-up or reset of the hard drive and a host computer associated therewith , the following steps being performed by and at the hard drive : receiving , from the host computer , a read command which requests data records of an application program stored on one or more hard disks of the hard drive ;
generating and storing a prefetch table in response to receiving the read command , the prefetch table representing disk storage location and length of the data records requested by the read command ;
for subsequent power-up or resets of the hard drive and host computer , the following steps being performed by and at the hard drive : receiving , from the host computer , a subsequent read command which requests data records stored on the one or more hard disks ;
prior to receiving the subsequent read command , identifying and locating the data records of the application program on the one or more hard disks based on the disk storage location and length represented in the prefetch table ;
prior to receiving the subsequent read command , and upon identifying and locating the data records , reading the data records of the application program from the one or more hard disks and storing them in a data cache in the hard drive ;
and in response to receiving the subsequent read command , communicating the prestored data records of the application program from the data cache if the subsequent read command requests those data records , and otherwise accessing data records from the one or more hard disks for communicating .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface (processing apparatus, following steps, initial program) configured to communicate with a storage client ;

a storage processor (data store) coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US6073232A
CLAIM 1
. A computer program product for use with a peripheral storage apparatus including at least one data storage element and a data cache , comprising : a computer program storage medium readable by a digital processing apparatus (storage interface) ;
and a program means on the program storage medium and including instructions executable by the digital processing apparatus for causing the digital processing apparatus to copy data store (storage processor) d on the data storage element to the data cache by : after an initial power-up or reset of the peripheral storage apparatus and a host computer associated with the peripheral storage apparatus , receiving a read command from the host computer for transferring to the host computer a data record of a program stored on the data storage element ;
in response to receiving , generating and storing in the peripheral storage apparatus a prefetch table representative of a storage location and length of the data record requested by the initial read command ;
after a subsequent power-on or reset of the peripheral storage apparatus , and during a second power-on or reset of the host computer , accessing by the peripheral storage apparatus the prefetch table to read the data record into the data cache ;
and in response to subsequent read commands from the host computer , determining whether records requested by the subsequent read commands are stored in the data cache , and if so , communicating the records from the data cache to the host computer , and otherwise communicating the records from the data storage element to the host computer .

US6073232A
CLAIM 28
. A disk drive , comprising : one or more read heads for reading from one or more disks of the disk drive ;
a data cache comprising a random access memory (RAM) ;
a controller ;
the controller being operative to execute the following steps (storage interface) after a power-up or reset of the disk drive and a host computer associated with the disk drive : receiving , from the host computer , a read command which requests data records of an application program stored on the one or more disks ;
generating and storing a prefetch table in the disk drive in response to receiving the read command , the prefetch table representing disk storage location and length of the data records requested by the read command ;
the controller being operative to execute the following steps for subsequent power-up or resets of the disk drive and host computer : receiving , from the host computer , a subsequent read command which requests data records stored on the one or more disks ;
prior to receiving the subsequent read command , identifying and locating the data records of the application program on the one or more disks based on the disk storage location and length represented in the prefetch table ;
prior to receiving the subsequent read command , and upon identifying and locating the data records , reading the data records of the application program from the one or more disks and storing them in the data cache ;
and in response to receiving the subsequent read command , communicating the prestored data records of the application program from the data cache to the host computer if the subsequent read command requests those data records , and otherwise accessing data records from the one or more disks for communicating .

US6073232A
CLAIM 32
. A method for reducing an initial program (storage interface) load time with use of a hard drive , the method comprising : after a power-up or reset of the hard drive and a host computer associated therewith , the following steps being performed by and at the hard drive : receiving , from the host computer , a read command which requests data records of an application program stored on one or more hard disks of the hard drive ;
generating and storing a prefetch table in response to receiving the read command , the prefetch table representing disk storage location and length of the data records requested by the read command ;
for subsequent power-up or resets of the hard drive and host computer , the following steps being performed by and at the hard drive : receiving , from the host computer , a subsequent read command which requests data records stored on the one or more hard disks ;
prior to receiving the subsequent read command , identifying and locating the data records of the application program on the one or more hard disks based on the disk storage location and length represented in the prefetch table ;
prior to receiving the subsequent read command , and upon identifying and locating the data records , reading the data records of the application program from the one or more hard disks and storing them in a data cache in the hard drive ;
and in response to receiving the subsequent read command , communicating the prestored data records of the application program from the data cache if the subsequent read command requests those data records , and otherwise accessing data records from the one or more hard disks for communicating .

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (data store) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
US6073232A
CLAIM 1
. A computer program product for use with a peripheral storage apparatus including at least one data storage element and a data cache , comprising : a computer program storage medium readable by a digital processing apparatus ;
and a program means on the program storage medium and including instructions executable by the digital processing apparatus for causing the digital processing apparatus to copy data store (storage processor) d on the data storage element to the data cache by : after an initial power-up or reset of the peripheral storage apparatus and a host computer associated with the peripheral storage apparatus , receiving a read command from the host computer for transferring to the host computer a data record of a program stored on the data storage element ;
in response to receiving , generating and storing in the peripheral storage apparatus a prefetch table representative of a storage location and length of the data record requested by the initial read command ;
after a subsequent power-on or reset of the peripheral storage apparatus , and during a second power-on or reset of the host computer , accessing by the peripheral storage apparatus the prefetch table to read the data record into the data cache ;
and in response to subsequent read commands from the host computer , determining whether records requested by the subsequent read commands are stored in the data cache , and if so , communicating the records from the data cache to the host computer , and otherwise communicating the records from the data storage element to the host computer .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer (hard disk) is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor (data store) returns a predetermined data string .
US6073232A
CLAIM 1
. A computer program product for use with a peripheral storage apparatus including at least one data storage element and a data cache , comprising : a computer program storage medium readable by a digital processing apparatus ;
and a program means on the program storage medium and including instructions executable by the digital processing apparatus for causing the digital processing apparatus to copy data store (storage processor) d on the data storage element to the data cache by : after an initial power-up or reset of the peripheral storage apparatus and a host computer associated with the peripheral storage apparatus , receiving a read command from the host computer for transferring to the host computer a data record of a program stored on the data storage element ;
in response to receiving , generating and storing in the peripheral storage apparatus a prefetch table representative of a storage location and length of the data record requested by the initial read command ;
after a subsequent power-on or reset of the peripheral storage apparatus , and during a second power-on or reset of the host computer , accessing by the peripheral storage apparatus the prefetch table to read the data record into the data cache ;
and in response to subsequent read commands from the host computer , determining whether records requested by the subsequent read commands are stored in the data cache , and if so , communicating the records from the data cache to the host computer , and otherwise communicating the records from the data storage element to the host computer .

US6073232A
CLAIM 29
. The disk drive according to claim 28 , wherein the one or more disks comprise one or more hard disk (state storage medium, state storage system, storage processer) s and the disk drive comprises a hard drive .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US5802602A

Filed: 1997-01-17     Issued: 1998-09-01

Method and apparatus for performing reads of related data from a set-associative cache memory

(Original Assignee) Intel Corp     (Current Assignee) Intel Corp

Monis Rahman, Mircea Poplingher, Tse-Yu Yeh, Wenliang Chen
US9632727B2
CLAIM 2
. The apparatus of claim 1 , wherein the indexer assigns logical addresses to physical addresses by use of index entries (first entry) , and wherein the indexer removes an index entry corresponding to the identified logical address in response to the message .
US5802602A
CLAIM 7
. A computer-implement method of accessing a set-associative cache memory including first and second ways , wherein each of the first and second ways has first and second entries and wherein the respective first entries together comprise a first set and the respective second entries together comprise a second set , the method comprising the steps of : identifying first and second information units as being related by a probability of being successively read from the cache memory ;
storing the first information unit in the first entry (index entries) of the first way , and the second information unit in the first entry of the second way , so that the first and second information units are stored in the first set ;
indexing both the first entries in each of the first and second ways with a pointer ;
and simultaneously outputting the first and second information units from the first entries of the first and second ways to output selection circuitry .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request (n information) specifying one or more logical addresses included in the empty-block directive command , the storage processor returns a predetermined data string (memory arrangement) .
US5802602A
CLAIM 8
. The method of claim 7 wherein the set-associative cache memory maintains a branch prediction table , and the first information unit is prediction information (read request) relating to a first branch instruction and the second information unit is prediction information relating to a second branch instruction , the method including the steps of : determining whether the prediction information for the first branch instruction indicates the first branch instruction as being not taken ;
if so , then outputting the prediction information for the first and second branch instructions from the output selection circuitry ;
and if not , then outputting only the prediction information for the first branch instruction from the output selection circuitry .

US5802602A
CLAIM 15
. A set-associative cache memory arrangement (data string, data bits) comprising : a set-associative cache memory having first and second ways , wherein each of the first and second ways has first and second entries and wherein the respective first entries together comprise a first set and the respective second entries together comprise a second set ;
allocation circuitry configured to identifying first and second data units , to be stored in the set-associative cache memory , as being related by a probability of being successively read from the cache memory , and to allocate the first data unit to the first entry of the first way , and the second data unit to the first entry of the second way , so that the first and second data units are stored in the first set ;
and retrieval circuitry configured to index the first entries in each of the first and second ways with a pointer , and simultaneously to retrieve the first and second data units from the first entries of the first and second ways .

US9632727B2
CLAIM 16
. The system of claim 15 , wherein data bits (memory arrangement) of the predetermined data string (memory arrangement) have a uniform logic level .
US5802602A
CLAIM 15
. A set-associative cache memory arrangement (data string, data bits) comprising : a set-associative cache memory having first and second ways , wherein each of the first and second ways has first and second entries and wherein the respective first entries together comprise a first set and the respective second entries together comprise a second set ;
allocation circuitry configured to identifying first and second data units , to be stored in the set-associative cache memory , as being related by a probability of being successively read from the cache memory , and to allocate the first data unit to the first entry of the first way , and the second data unit to the first entry of the second way , so that the first and second data units are stored in the first set ;
and retrieval circuitry configured to index the first entries in each of the first and second ways with a pointer , and simultaneously to retrieve the first and second data units from the first entries of the first and second ways .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US6279069B1

Filed: 1996-12-26     Issued: 2001-08-21

Interface for flash EEPROM memory arrays

(Original Assignee) Intel Corp     (Current Assignee) Intel Corp

Kurt B. Robinson, Mark Christopherson, Terry Kendall
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium (write operation) in response to requests from a computer system (computer system) , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US6279069B1
CLAIM 5
. The memory system of claim 1 wherein the output of the status register indicates the availability of a write buffer during the time a write operation (solid state storage medium) is being executed .

US6279069B1
CLAIM 26
. A computer readable media having stored thereon a sequence of commands which when executed by a computer system (computer system) cause the computer system to perform the following : alerting a software driver of an erase parameter of the flash memory device stored in a query memory residing within the flash memory device , the alerting performed in response to a query command decoded by a command interface ;
erasing multiple blocks of flash memory ;
and changing an output of a status register to indicate a status of a particular operation being executed .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system (computer system) , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
US6279069B1
CLAIM 26
. A computer readable media having stored thereon a sequence of commands which when executed by a computer system (computer system) cause the computer system to perform the following : alerting a software driver of an erase parameter of the flash memory device stored in a query memory residing within the flash memory device , the alerting performed in response to a query command decoded by a command interface ;
erasing multiple blocks of flash memory ;
and changing an output of a status register to indicate a status of a particular operation being executed .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US6073218A

Filed: 1996-12-23     Issued: 2000-06-06

Methods and apparatus for coordinating shared multiple raid controller access to common storage devices

(Original Assignee) LSI Corp     (Current Assignee) NetApp Inc

Rodney A. DeKoning, Gerald J. Fredin
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system (computer system) , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data (associating one) pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US6073218A
CLAIM 5
. The method of claim 4 wherein said primary control module is associated with at least one semaphore and wherein the step of awaiting availability includes the steps of : determining that none of said at least one semaphore is associated with said portion of said common shared LUN ;
associating one (store data) of said at least one semaphore with said portion in response to the determination none of said at least one semaphore is associated with said portion ;
and locking the semaphore associated with said portion .

US6073218A
CLAIM 16
. In a system including a plurality of storage control modules connected to a common shared set of storage devices in a storage subsystem , a method operable within said plurality of storage control modules for processing I/O requests directed to said common shared set of storage devices comprising the steps of : designating one of said plurality of storage control modules as a primary control modules ;
receiving a plurality of I/O requests from attached host computer system (computer system) s ;
coordinating temporary exclusive access to identified stripes within said common shared set of storage devices by said distinct control modules , wherein the step of coordinating includes the step of : exchanging exclusive access messages between said primary control module and others of said plurality of storage control modules ;
and processing each of said plurality of I/O requests substantially in parallel within distinct control modules of said plurality of storage control modules .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system (computer system) , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
US6073218A
CLAIM 16
. In a system including a plurality of storage control modules connected to a common shared set of storage devices in a storage subsystem , a method operable within said plurality of storage control modules for processing I/O requests directed to said common shared set of storage devices comprising the steps of : designating one of said plurality of storage control modules as a primary control modules ;
receiving a plurality of I/O requests from attached host computer system (computer system) s ;
coordinating temporary exclusive access to identified stripes within said common shared set of storage devices by said distinct control modules , wherein the step of coordinating includes the step of : exchanging exclusive access messages between said primary control module and others of said plurality of storage control modules ;
and processing each of said plurality of I/O requests substantially in parallel within distinct control modules of said plurality of storage control modules .

US9632727B2
CLAIM 8
. The system of claim 7 , further comprising means for providing a storage interface (designating one) to accept requests to perform storage operations on the solid-state storage medium in reference to the logical blocks and to accept the message identifying the logical block that is not being used to reference data stored on the solid-state storage medium .
US6073218A
CLAIM 1
. In a system including a plurality of RAID control modules connected to a common shared LUN in a RAID storage subsystem , a method operable within said plurality of RAID control modules for coordinating exclusive access by said plurality of control modules to said common shared LUN comprising the steps of : designating one (storage interface) of said plurality of RAID control modules as a primary control module ;
and exchanging access coordination messages between said primary control module and others of said plurality of RAID control modules to coordinate temporary exclusive access by one of said plurality of RAID control modules to identified stripes within said common shared LUN .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface (designating one) configured to communicate with a storage client ;

a storage processor coupled to the storage interface ;

a flash memory device (storage subsystem) coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US6073218A
CLAIM 1
. In a system including a plurality of RAID control modules connected to a common shared LUN in a RAID storage subsystem (flash memory device) , a method operable within said plurality of RAID control modules for coordinating exclusive access by said plurality of control modules to said common shared LUN comprising the steps of : designating one (storage interface) of said plurality of RAID control modules as a primary control module ;
and exchanging access coordination messages between said primary control module and others of said plurality of RAID control modules to coordinate temporary exclusive access by one of said plurality of RAID control modules to identified stripes within said common shared LUN .

US9632727B2
CLAIM 13
. The system of claim 12 , wherein the logical-to-physical translation layer is stored in the flash memory device (storage subsystem) .
US6073218A
CLAIM 1
. In a system including a plurality of RAID control modules connected to a common shared LUN in a RAID storage subsystem (flash memory device) , a method operable within said plurality of RAID control modules for coordinating exclusive access by said plurality of control modules to said common shared LUN comprising the steps of : designating one of said plurality of RAID control modules as a primary control module ;
and exchanging access coordination messages between said primary control module and others of said plurality of RAID control modules to coordinate temporary exclusive access by one of said plurality of RAID control modules to identified stripes within said common shared LUN .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US5867430A

Filed: 1996-12-20     Issued: 1999-02-02

Bank architecture for a non-volatile memory enabling simultaneous reading and writing

(Original Assignee) Fujitsu Ltd; Advanced Micro Devices Inc     (Current Assignee) Spansion LLC ; AMD US Holdings Inc

Johnny C. Chen, Chung K. Chang, Tiao-Hua Kuo, Takao Akaogi
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium (write operation) in response to requests from a computer system , including storing data (said memory) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data (said memory) pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US5867430A
CLAIM 18
. A semiconductor non-volatile memory device , comprising : a first bank of sectors ;
a second bank of sectors , each sector of said first bank and said second bank including non-volatile memory cells ;
first address decode logic , said first address decode logic accessing said first bank ;
and second address decode logic , said second address decode logic accessing said second bank ;
wherein : said memory (store data, storing data) device receives an address input ;
said memory device further including a state machine for performing an embedded method for erasing and programming , said state machine generating a control address ;
said first bank being capable of using a first address from said address input to perform a read while said second bank is using said control address to perform a write ;
said second bank being capable of using said first address to perform a read while said first bank is using said control address to perform a write ;
and said semiconductor non-volatile memory device further comprising , a first sense amplifier circuit receiving read data from said first bank and read data from said second bank , said first sense amplifier circuit selectively using said read data from said first bank and read data from said second bank to generate a read data output , and a second sense amplifier circuit receiving read data from said first bank and read data from said second bank , said second sense amplifier circuit selectively using said read data from said first bank and read data from said second bank to generate verify data .

US5867430A
CLAIM 21
. A method of enabling simultaneous read and write operation (solid state storage medium) s in a flash memory , comprising the steps of : arranging a set of flash memory cells as a plurality of sectors , each sector containing a plurality of said flash memory cells ;
arranging said sectors into two banks of sectors ;
providing independent address decode circuits to each of said banks ;
providing a control circuit for writing to said banks , said control circuitry generating a control address ;
providing a selection circuit selectively coupling said address decode logic to said control address or an external address ;
providing a first sense amplification circuit for reading data from said banks ;
providing a second sense amplification circuit for reading data from said banks , said second sense amplification circuit communicating with said control circuit to verify writes to said banks .

US9632727B2
CLAIM 2
. The apparatus of claim 1 , wherein the indexer assigns logical addresses to physical addresses by use of index entries , and wherein the indexer removes an index entry (d line) corresponding to the identified logical address in response to the message .
US5867430A
CLAIM 4
. A non-volatile memory device capable of simultaneous reading and writing , comprising : a first set of memory cells ;
a second set of memory cells ;
and address logic having outputs including a first set of decoded line (index entry) s and a second set of decoded lines , said address logic selectively using either a first address or a second address to access said first set of memory cells with said first set of decoded lines and selectively using either said first address or said second address to access said second set of memory cells with said second set of decoded lines ;
wherein : said first set of memory cells are flash memory cells ;
said second set of memory cells are flash memory cells ;
said flash memory device receives address and control information , said address input receiving said first address ;
said flash memory device further includes control logic receiving said control information , said control logic generating said second address and said control logic being in communication with said address logic ;
a first sense amplifier circuit receiving read data from said first set of flash memory cells and read data from said second set of flash memory cells , said first sense amplifier circuit selectively using said read data from said first set of flash memory cells and read data from said second set of flash memory cells to generate a read data output ;
and a second sense amplifier circuit receiving read data from said first set of flash memory cells and read data from said second set of flash memory cells , said second sense amplifier circuit selectively using said read data from said first set of flash memory cells and read data from said second set of flash memory cells to generate verify data , said verify data being sent to said control logic .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (address buffer) (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
US5867430A
CLAIM 3
. The flash memory device according to claim 1 , further comprising : an address buffer (Peripheral Component Interconnect) configured to store an address to be read from one of said at least two banks of flash memory cells ;
and an address sequencer configured to sequence a set of addresses to be at least one of programmed and verified in a second of said at least two banks of flash memory cells .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (said memory) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
US5867430A
CLAIM 18
. A semiconductor non-volatile memory device , comprising : a first bank of sectors ;
a second bank of sectors , each sector of said first bank and said second bank including non-volatile memory cells ;
first address decode logic , said first address decode logic accessing said first bank ;
and second address decode logic , said second address decode logic accessing said second bank ;
wherein : said memory (store data, storing data) device receives an address input ;
said memory device further including a state machine for performing an embedded method for erasing and programming , said state machine generating a control address ;
said first bank being capable of using a first address from said address input to perform a read while said second bank is using said control address to perform a write ;
said second bank being capable of using said first address to perform a read while said first bank is using said control address to perform a write ;
and said semiconductor non-volatile memory device further comprising , a first sense amplifier circuit receiving read data from said first bank and read data from said second bank , said first sense amplifier circuit selectively using said read data from said first bank and read data from said second bank to generate a read data output , and a second sense amplifier circuit receiving read data from said first bank and read data from said second bank , said second sense amplifier circuit selectively using said read data from said first bank and read data from said second bank to generate verify data .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
JPH10154101A

Filed: 1996-11-26     Issued: 1998-06-09

データ記憶システム及び同システムに適用するキャッシュ制御方法

(Original Assignee) Toshiba Corp; 株式会社東芝     

Hiroshi Sukegawa, 博 助川
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations (保存機能) on the solid state storage medium in response to requests from a computer system , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
JPH10154101A
CLAIM 1
【請求項1】 コンピュータシステムに適用し、磁気デ ィスク装置及びフラッシュEEPROMから構成される 半導体ディスク装置の各外部記憶装置を使用したデータ 記憶システムであって、 前記磁気ディスク装置及び前記半導体ディスク装置のそ れぞれのデータ入出力を制御し、前記半導体ディスク装 置を前記磁気ディスク装置のキャッシュメモリとして機 能させるキャッシュ制御手段を有し、 前記キャッシュ制御手段は、前記キャッシュメモリに対 するデータ保存機能 (storage operations) の設定開始から解除するまでに、前 記磁気ディスク装置に保存されている情報の中から読出 された全ての情報定又は指定された特定情報を読出し て、前記半導体ディスク装置の指定領域に保存する手段 を具備したことを特徴とするデータ記憶システム。

US9632727B2
CLAIM 8
. The system of claim 7 , further comprising means for providing a storage interface to accept requests to perform storage operations (保存機能) on the solid-state storage medium in reference to the logical blocks and to accept the message identifying the logical block that is not being used to reference data stored on the solid-state storage medium .
JPH10154101A
CLAIM 1
【請求項1】 コンピュータシステムに適用し、磁気デ ィスク装置及びフラッシュEEPROMから構成される 半導体ディスク装置の各外部記憶装置を使用したデータ 記憶システムであって、 前記磁気ディスク装置及び前記半導体ディスク装置のそ れぞれのデータ入出力を制御し、前記半導体ディスク装 置を前記磁気ディスク装置のキャッシュメモリとして機 能させるキャッシュ制御手段を有し、 前記キャッシュ制御手段は、前記キャッシュメモリに対 するデータ保存機能 (storage operations) の設定開始から解除するまでに、前 記磁気ディスク装置に保存されている情報の中から読出 された全ての情報定又は指定された特定情報を読出し て、前記半導体ディスク装置の指定領域に保存する手段 を具備したことを特徴とするデータ記憶システム。

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor (メモリ) coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
JPH10154101A
CLAIM 1
【請求項1】 コンピュータシステムに適用し、磁気デ ィスク装置及びフラッシュEEPROMから構成される 半導体ディスク装置の各外部記憶装置を使用したデータ 記憶システムであって、 前記磁気ディスク装置及び前記半導体ディスク装置のそ れぞれのデータ入出力を制御し、前記半導体ディスク装 置を前記磁気ディスク装置のキャッシュメモリ (storage processor) として機 能させるキャッシュ制御手段を有し、 前記キャッシュ制御手段は、前記キャッシュメモリに対 するデータ保存機能の設定開始から解除するまでに、前 記磁気ディスク装置に保存されている情報の中から読出 された全ての情報定又は指定された特定情報を読出し て、前記半導体ディスク装置の指定領域に保存する手段 を具備したことを特徴とするデータ記憶システム。

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (メモリ) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
JPH10154101A
CLAIM 1
【請求項1】 コンピュータシステムに適用し、磁気デ ィスク装置及びフラッシュEEPROMから構成される 半導体ディスク装置の各外部記憶装置を使用したデータ 記憶システムであって、 前記磁気ディスク装置及び前記半導体ディスク装置のそ れぞれのデータ入出力を制御し、前記半導体ディスク装 置を前記磁気ディスク装置のキャッシュメモリ (storage processor) として機 能させるキャッシュ制御手段を有し、 前記キャッシュ制御手段は、前記キャッシュメモリに対 するデータ保存機能の設定開始から解除するまでに、前 記磁気ディスク装置に保存されている情報の中から読出 された全ての情報定又は指定された特定情報を読出し て、前記半導体ディスク装置の指定領域に保存する手段 を具備したことを特徴とするデータ記憶システム。

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor (メモリ) returns a predetermined data string .
JPH10154101A
CLAIM 1
【請求項1】 コンピュータシステムに適用し、磁気デ ィスク装置及びフラッシュEEPROMから構成される 半導体ディスク装置の各外部記憶装置を使用したデータ 記憶システムであって、 前記磁気ディスク装置及び前記半導体ディスク装置のそ れぞれのデータ入出力を制御し、前記半導体ディスク装 置を前記磁気ディスク装置のキャッシュメモリ (storage processor) として機 能させるキャッシュ制御手段を有し、 前記キャッシュ制御手段は、前記キャッシュメモリに対 するデータ保存機能の設定開始から解除するまでに、前 記磁気ディスク装置に保存されている情報の中から読出 された全ての情報定又は指定された特定情報を読出し て、前記半導体ディスク装置の指定領域に保存する手段 を具備したことを特徴とするデータ記憶システム。




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US5890192A

Filed: 1996-11-05     Issued: 1999-03-30

Concurrent write of multiple chunks of data into multiple subarrays of flash EEPROM

(Original Assignee) SanDisk Corp     (Current Assignee) SanDisk Technologies LLC

Douglas J. Lee, Mehrdad Mofidi, Sanjay Mehrotra, Raul-Adrian Cernea
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system (stored data) , including storing data (storing data) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US5890192A
CLAIM 1
. A circuit for concurrently writing data into selected memory locations of a plurality of EEPROM subarrays , comprising : a plurality of address latches , a plurality of data registers individually coupled to a corresponding one of said plurality of EEPROM subarrays , means for storing subarray addresses into selected ones of said plurality of address latches , wherein individual ones of said plurality of subarray addresses are coded such that a first plurality of bits indicates the subarray in which the subarray location indicated by said subarray address resides , a second plurality of bits indicates a row address and a third plurality of bits indicates a column address of the subarray indicated by said first plurality of bits , and for storing data (storing data) to be written into subarray locations indicated by said subarray addresses , into selected ones of said plurality of data registers , said storing means including means for decoding said first plurality of bits to generate a signal to enable the data register coupled to the subarray indicated by said first plurality of bits , said plurality of address latches including a plurality of row address latches and a plurality of column address latches for respectively latching said row addresses indicated by said second plurality of bits and said column addresses indicated by said third plurality of bits , wherein said storing means additionally includes means for generating a plurality of signals to enable the pluralities of row and column address latches for storing said row and column addresses indicated by said second and third plurality of bits , and means for concurrently writing said data stored in said plurality of data registers into the subarray locations indicated by said subarray addresses stored in said plurality of address latches .

US5890192A
CLAIM 13
. The method as recited in either of claims 11 or 12 , wherein the step of writing the stored data (computer system) into the subarray includes programming individual memory cells of the subarray into one of more than two programmable states in order to store more than one bit of data per cell .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system (stored data) , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface (third plurality) .
US5890192A
CLAIM 1
. A circuit for concurrently writing data into selected memory locations of a plurality of EEPROM subarrays , comprising : a plurality of address latches , a plurality of data registers individually coupled to a corresponding one of said plurality of EEPROM subarrays , means for storing subarray addresses into selected ones of said plurality of address latches , wherein individual ones of said plurality of subarray addresses are coded such that a first plurality of bits indicates the subarray in which the subarray location indicated by said subarray address resides , a second plurality of bits indicates a row address and a third plurality (Fibre Channel interface) of bits indicates a column address of the subarray indicated by said first plurality of bits , and for storing data to be written into subarray locations indicated by said subarray addresses , into selected ones of said plurality of data registers , said storing means including means for decoding said first plurality of bits to generate a signal to enable the data register coupled to the subarray indicated by said first plurality of bits , said plurality of address latches including a plurality of row address latches and a plurality of column address latches for respectively latching said row addresses indicated by said second plurality of bits and said column addresses indicated by said third plurality of bits , wherein said storing means additionally includes means for generating a plurality of signals to enable the pluralities of row and column address latches for storing said row and column addresses indicated by said second and third plurality of bits , and means for concurrently writing said data stored in said plurality of data registers into the subarray locations indicated by said subarray addresses stored in said plurality of address latches .

US5890192A
CLAIM 13
. The method as recited in either of claims 11 or 12 , wherein the step of writing the stored data (computer system) into the subarray includes programming individual memory cells of the subarray into one of more than two programmable states in order to store more than one bit of data per cell .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (storing data) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
US5890192A
CLAIM 1
. A circuit for concurrently writing data into selected memory locations of a plurality of EEPROM subarrays , comprising : a plurality of address latches , a plurality of data registers individually coupled to a corresponding one of said plurality of EEPROM subarrays , means for storing subarray addresses into selected ones of said plurality of address latches , wherein individual ones of said plurality of subarray addresses are coded such that a first plurality of bits indicates the subarray in which the subarray location indicated by said subarray address resides , a second plurality of bits indicates a row address and a third plurality of bits indicates a column address of the subarray indicated by said first plurality of bits , and for storing data (storing data) to be written into subarray locations indicated by said subarray addresses , into selected ones of said plurality of data registers , said storing means including means for decoding said first plurality of bits to generate a signal to enable the data register coupled to the subarray indicated by said first plurality of bits , said plurality of address latches including a plurality of row address latches and a plurality of column address latches for respectively latching said row addresses indicated by said second plurality of bits and said column addresses indicated by said third plurality of bits , wherein said storing means additionally includes means for generating a plurality of signals to enable the pluralities of row and column address latches for storing said row and column addresses indicated by said second and third plurality of bits , and means for concurrently writing said data stored in said plurality of data registers into the subarray locations indicated by said subarray addresses stored in said plurality of address latches .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor (data store) coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US5890192A
CLAIM 1
. A circuit for concurrently writing data into selected memory locations of a plurality of EEPROM subarrays , comprising : a plurality of address latches , a plurality of data registers individually coupled to a corresponding one of said plurality of EEPROM subarrays , means for storing subarray addresses into selected ones of said plurality of address latches , wherein individual ones of said plurality of subarray addresses are coded such that a first plurality of bits indicates the subarray in which the subarray location indicated by said subarray address resides , a second plurality of bits indicates a row address and a third plurality of bits indicates a column address of the subarray indicated by said first plurality of bits , and for storing data to be written into subarray locations indicated by said subarray addresses , into selected ones of said plurality of data registers , said storing means including means for decoding said first plurality of bits to generate a signal to enable the data register coupled to the subarray indicated by said first plurality of bits , said plurality of address latches including a plurality of row address latches and a plurality of column address latches for respectively latching said row addresses indicated by said second plurality of bits and said column addresses indicated by said third plurality of bits , wherein said storing means additionally includes means for generating a plurality of signals to enable the pluralities of row and column address latches for storing said row and column addresses indicated by said second and third plurality of bits , and means for concurrently writing said data store (storage processor) d in said plurality of data registers into the subarray locations indicated by said subarray addresses stored in said plurality of address latches .

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (data store) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
US5890192A
CLAIM 1
. A circuit for concurrently writing data into selected memory locations of a plurality of EEPROM subarrays , comprising : a plurality of address latches , a plurality of data registers individually coupled to a corresponding one of said plurality of EEPROM subarrays , means for storing subarray addresses into selected ones of said plurality of address latches , wherein individual ones of said plurality of subarray addresses are coded such that a first plurality of bits indicates the subarray in which the subarray location indicated by said subarray address resides , a second plurality of bits indicates a row address and a third plurality of bits indicates a column address of the subarray indicated by said first plurality of bits , and for storing data to be written into subarray locations indicated by said subarray addresses , into selected ones of said plurality of data registers , said storing means including means for decoding said first plurality of bits to generate a signal to enable the data register coupled to the subarray indicated by said first plurality of bits , said plurality of address latches including a plurality of row address latches and a plurality of column address latches for respectively latching said row addresses indicated by said second plurality of bits and said column addresses indicated by said third plurality of bits , wherein said storing means additionally includes means for generating a plurality of signals to enable the pluralities of row and column address latches for storing said row and column addresses indicated by said second and third plurality of bits , and means for concurrently writing said data store (storage processor) d in said plurality of data registers into the subarray locations indicated by said subarray addresses stored in said plurality of address latches .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request (corresponding data) specifying one or more logical addresses included in the empty-block directive command , the storage processor (data store) returns a predetermined data string .
US5890192A
CLAIM 1
. A circuit for concurrently writing data into selected memory locations of a plurality of EEPROM subarrays , comprising : a plurality of address latches , a plurality of data registers individually coupled to a corresponding one of said plurality of EEPROM subarrays , means for storing subarray addresses into selected ones of said plurality of address latches , wherein individual ones of said plurality of subarray addresses are coded such that a first plurality of bits indicates the subarray in which the subarray location indicated by said subarray address resides , a second plurality of bits indicates a row address and a third plurality of bits indicates a column address of the subarray indicated by said first plurality of bits , and for storing data to be written into subarray locations indicated by said subarray addresses , into selected ones of said plurality of data registers , said storing means including means for decoding said first plurality of bits to generate a signal to enable the data register coupled to the subarray indicated by said first plurality of bits , said plurality of address latches including a plurality of row address latches and a plurality of column address latches for respectively latching said row addresses indicated by said second plurality of bits and said column addresses indicated by said third plurality of bits , wherein said storing means additionally includes means for generating a plurality of signals to enable the pluralities of row and column address latches for storing said row and column addresses indicated by said second and third plurality of bits , and means for concurrently writing said data store (storage processor) d in said plurality of data registers into the subarray locations indicated by said subarray addresses stored in said plurality of address latches .

US5890192A
CLAIM 11
. A method of concurrently writing a plurality of data chunks into an EEPROM , comprising the steps of : sequentially storing said plurality of data chunks into a plurality of data storage means respectively coupled to corresponding subarrays of said EEPROM , including the steps of : sequentially receiving a plurality of subarray addresses indicative of subarray locations wherein corresponding data (read request) chunks of said plurality of data chunks are to be written ;
and sequentially storing said corresponding data chunks into said plurality of data storage means such that individual ones of said corresponding data chunks are stored in the data storage means coupled to the subarray including the subarray location indicated by the subarray address corresponding to said individual one data chunk ;
providing row and column select signals to row and column decoder means coupled to said corresponding subarrays of said EEPROM ;
and concurrently writing said plurality of data chunks stored in said plurality of data storage means into subarray locations of said corresponding subarrays of said EEPROM as indicated by said row and column select signals .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US5754567A

Filed: 1996-10-15     Issued: 1998-05-19

Write reduction in flash memory systems through ECC usage

(Original Assignee) Micron Quantum Devices Inc     (Current Assignee) Micron Technology Inc

Robert D. Norman
US9632727B2
CLAIM 9
. The system of claim 7 , wherein unmapping the identified logical block comprises invalidating an entry of the logical-to-physical mappings , the entry indicating a mapping between the identified logical block and the particular storage (confirmation signal) block .
US5754567A
CLAIM 41
. The computer system of claim 40 wherein the control engine asserts a confirmation signal (particular storage) to the host processor interface in response to the at least one of the control signals and the ECC comparison signal being in the first state , the comparison signal indicating that the first state of data has been written into the array .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor (data store) coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US5754567A
CLAIM 6
. A nonvolatile memory system comprising : an array of nonvolatile memory cells organized into sets , each set having sufficient memory cells to store a set of data ;
a buffer for storing a first set of data to be written to the array ;
error correction code (ECC) circuitry receiving the first set of data and calculating first ECC check bits representative of the first set of data ;
and ECC comparison circuitry for comparing the first ECC check bits with second ECC check bits representative of a second set of data store (storage processor) d in the array to generate an ECC comparison signal having a first state indicative of a match between the first and second ECC check bits and a second state indicative of a miscomparison between the first and second ECC check bits .

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (data store) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
US5754567A
CLAIM 6
. A nonvolatile memory system comprising : an array of nonvolatile memory cells organized into sets , each set having sufficient memory cells to store a set of data ;
a buffer for storing a first set of data to be written to the array ;
error correction code (ECC) circuitry receiving the first set of data and calculating first ECC check bits representative of the first set of data ;
and ECC comparison circuitry for comparing the first ECC check bits with second ECC check bits representative of a second set of data store (storage processor) d in the array to generate an ECC comparison signal having a first state indicative of a match between the first and second ECC check bits and a second state indicative of a miscomparison between the first and second ECC check bits .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor (data store) returns a predetermined data string .
US5754567A
CLAIM 6
. A nonvolatile memory system comprising : an array of nonvolatile memory cells organized into sets , each set having sufficient memory cells to store a set of data ;
a buffer for storing a first set of data to be written to the array ;
error correction code (ECC) circuitry receiving the first set of data and calculating first ECC check bits representative of the first set of data ;
and ECC comparison circuitry for comparing the first ECC check bits with second ECC check bits representative of a second set of data store (storage processor) d in the array to generate an ECC comparison signal having a first state indicative of a match between the first and second ECC check bits and a second state indicative of a miscomparison between the first and second ECC check bits .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US5798968A

Filed: 1996-09-24     Issued: 1998-08-25

Plane decode/virtual sector architecture

(Original Assignee) SanDisk Corp     (Current Assignee) SanDisk Technologies LLC

Douglas J. Lee, Sanjay Mehrotra, Mehrdad Mofidi, Daniel C. Guterman
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations (control gate) on the solid state storage medium in response to requests from a computer system , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US5798968A
CLAIM 1
. An EEPROM device including a plurality of EEPROM cells organized into first and second subarrays individually having rows and columns , comprising : a row decoder circuit coupled through a plurality of word lines to the control gate (storage operations) s of EEPROM cells of corresponding rows of said first and second subarrays , wherein said row decoder circuit comprises lower and upper row decoder circuits respectively coupled to alternating groupings of said plurality of word lines ;
a first erase circuit coupled through a first plurality of erase lines to the erase gates of EEPROM cells of corresponding rows of said first subarray ;
and a second erase circuit coupled through a second plurality of erase lines to the erase gates of EEPROM cells of corresponding rows of said second subarray .

US9632727B2
CLAIM 2
. The apparatus of claim 1 , wherein the indexer assigns logical addresses to physical addresses by use of index entries , and wherein the indexer removes an index entry (d line) corresponding to the identified logical address in response to the message .
US5798968A
CLAIM 1
. An EEPROM device including a plurality of EEPROM cells organized into first and second subarrays individually having rows and columns , comprising : a row decoder circuit coupled through a plurality of word line (index entry) s to the control gates of EEPROM cells of corresponding rows of said first and second subarrays , wherein said row decoder circuit comprises lower and upper row decoder circuits respectively coupled to alternating groupings of said plurality of word lines ;
a first erase circuit coupled through a first plurality of erase lines to the erase gates of EEPROM cells of corresponding rows of said first subarray ;
and a second erase circuit coupled through a second plurality of erase lines to the erase gates of EEPROM cells of corresponding rows of said second subarray .

US9632727B2
CLAIM 5
. The apparatus of claim 1 , further comprising a garbage collector (opposite side) configured to designate that the physical address previously assigned to the identified logical address comprises data suitable for removal from the solid-state storage medium in response to the message .
US5798968A
CLAIM 9
. The EEPROM device as recited in claim 8 , wherein said lower and upper switch circuits of said plurality of switch circuits are respectively positioned on opposite side (garbage collector) s of said first subarray .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface (third plurality) .
US5798968A
CLAIM 25
. The flash EEPROM structure as recited in claim 24 , further comprising a third plurality (Fibre Channel interface) of conductive strips respectively connected to corresponding ones of said first and second plurality of EEPROM cells , and extending in said second direction on said semiconductor substrate .

US9632727B2
CLAIM 8
. The system of claim 7 , further comprising means for providing a storage interface to accept requests to perform storage operations (control gate) on the solid-state storage medium in reference to the logical blocks and to accept the message identifying the logical block that is not being used to reference data stored on the solid-state storage medium .
US5798968A
CLAIM 1
. An EEPROM device including a plurality of EEPROM cells organized into first and second subarrays individually having rows and columns , comprising : a row decoder circuit coupled through a plurality of word lines to the control gate (storage operations) s of EEPROM cells of corresponding rows of said first and second subarrays , wherein said row decoder circuit comprises lower and upper row decoder circuits respectively coupled to alternating groupings of said plurality of word lines ;
a first erase circuit coupled through a first plurality of erase lines to the erase gates of EEPROM cells of corresponding rows of said first subarray ;
and a second erase circuit coupled through a second plurality of erase lines to the erase gates of EEPROM cells of corresponding rows of said second subarray .

US9632727B2
CLAIM 9
. The system of claim 7 , wherein unmapping the identified logical block comprises invalidating an entry of the logical-to-physical mappings , the entry indicating a mapping between the identified logical block and the particular storage block (address decoder) .
US5798968A
CLAIM 4
. The EEPROM device as recited in claim 3 , wherein individual ones of said plurality of erase voltage generating means comprises : an address decoder (particular storage block) circuit receiving an address indicative of one of said first and second pluralities of erase lines , and activating a decoder output if said received address indicates one of the erase lines of the set of said first plurality of erase lines corresponding to said individual erase voltage generating means ;
and a charge pump circuit coupled to said decoder output to generate said erase voltage when said decoder output is activated .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor coupled to the storage interface ;

a flash memory device (common bit) coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US5798968A
CLAIM 13
. A flash of EEPROM structure formed on a semiconductor substrate , comprising : first and second subarays of EEPROM cells formed on said semiconductor substrate such that corresponding columns of said first and second subarrays of EEPROM cells are connected to common bit (flash memory device) lines , and said first and second subarrays of EEPROM cells are separated by an elongated area extending in a first direction substantially perpendicular to said common bit lines ;
and means substantially formed along a line extending in said first direction and through said elongated area , for switchably connecting an erase voltage to selected rows of said first subarray of EEPROM cells .

US9632727B2
CLAIM 13
. The system of claim 12 , wherein the logical-to-physical translation layer is stored in the flash memory device (common bit) .
US5798968A
CLAIM 13
. A flash of EEPROM structure formed on a semiconductor substrate , comprising : first and second subarays of EEPROM cells formed on said semiconductor substrate such that corresponding columns of said first and second subarrays of EEPROM cells are connected to common bit (flash memory device) lines , and said first and second subarrays of EEPROM cells are separated by an elongated area extending in a first direction substantially perpendicular to said common bit lines ;
and means substantially formed along a line extending in said first direction and through said elongated area , for switchably connecting an erase voltage to selected rows of said first subarray of EEPROM cells .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US6014724A

Filed: 1996-09-17     Issued: 2000-01-11

Flash translation layer block indication map revision system and method

(Original Assignee) SCM Microsystems US Inc     (Current Assignee) Samsung Electronics Co Ltd

Detlef Jenett
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system , including storing data (storing data) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US6014724A
CLAIM 11
. Method of storing data (storing data) in a flash memory system , the method comprising : providing a flash memory having a plurality of sectors ;
storing status information in the flash memory indicating the status of said plurality of sectors ;
storing a set of file information on said flash memory in a storage location residing within said flash memory , including mapping information , in the form of a file indication map residing in a file system used by an operating system controlling said storing of the file information , for mapping a file to one or more of said sectors ;
and receiving a set of updated file information from said file system , and determining whether there is a difference between said updated file information and said file information , and if so , altering the status information for selected sectors of said flash memory to reflect said difference , wherein a copy of the file indication map residing in the file system used by the operating system is made in a flash translation layer separately from said file indication map residing in the file system , thereby providing a status record of a former file indicator map for comparison against subsequent modifications of the file indication map residing in the file system used by the operating system .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (storing data) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
US6014724A
CLAIM 11
. Method of storing data (storing data) in a flash memory system , the method comprising : providing a flash memory having a plurality of sectors ;
storing status information in the flash memory indicating the status of said plurality of sectors ;
storing a set of file information on said flash memory in a storage location residing within said flash memory , including mapping information , in the form of a file indication map residing in a file system used by an operating system controlling said storing of the file information , for mapping a file to one or more of said sectors ;
and receiving a set of updated file information from said file system , and determining whether there is a difference between said updated file information and said file information , and if so , altering the status information for selected sectors of said flash memory to reflect said difference , wherein a copy of the file indication map residing in the file system used by the operating system is made in a flash translation layer separately from said file indication map residing in the file system , thereby providing a status record of a former file indicator map for comparison against subsequent modifications of the file indication map residing in the file system used by the operating system .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor coupled to the storage interface ;

a flash memory device (said determination) coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US6014724A
CLAIM 21
. Method of storing data in a flash memory system , the method comprising : providing a flash memory having a plurality of sectors ;
storing status information , including a block allocation map , in the flash memory indicating the status of said plurality of sectors ;
storing a set of file information on said flash memory in a storage location residing within said flash memory , including mapping information , in the form of a file indication map residing in a file system used by an operating system controlling said storing of the file information , for mapping a file to one or more of said sectors ;
and receiving a set of updated file information from said file system , and determining whether there is a difference between said updated file information and said file information , and if so , altering the status information for selected sectors of said flash memory to reflect said difference , wherein if a discrepancy is noted between the mapping information residing within the flash memory and said file indication map , updating the block allocation map to delete the association between a physical location at which the identified deleted file was stored and a virtual address formerly connected with the particular physical location , said particular physical location associated with physical sectors of the flash medium with a related virtual address , after a file is deleted , the sector of flash memory referred to in the block allocation map is indicated as other than valid , preventing preservation by transfer out to a transfer unit prior to erase , thereby resulting in complete erasure of said sector during the erase operation , said determination (flash memory device) made by comparing the mapping information residing within the flash memory and said file indication map , and replacement is made after said comparison , and a copy of the file indication map residing in the file system used by the operating system is made in a flash translation layer separately from said file indication map residing in the file syst m , thereby providing a status record of a former file indication map for comparison against subsequent modifications of the file indication map residing in the file system used by the operating system .

US9632727B2
CLAIM 13
. The system of claim 12 , wherein the logical-to-physical translation layer is stored in the flash memory device (said determination) .
US6014724A
CLAIM 21
. Method of storing data in a flash memory system , the method comprising : providing a flash memory having a plurality of sectors ;
storing status information , including a block allocation map , in the flash memory indicating the status of said plurality of sectors ;
storing a set of file information on said flash memory in a storage location residing within said flash memory , including mapping information , in the form of a file indication map residing in a file system used by an operating system controlling said storing of the file information , for mapping a file to one or more of said sectors ;
and receiving a set of updated file information from said file system , and determining whether there is a difference between said updated file information and said file information , and if so , altering the status information for selected sectors of said flash memory to reflect said difference , wherein if a discrepancy is noted between the mapping information residing within the flash memory and said file indication map , updating the block allocation map to delete the association between a physical location at which the identified deleted file was stored and a virtual address formerly connected with the particular physical location , said particular physical location associated with physical sectors of the flash medium with a related virtual address , after a file is deleted , the sector of flash memory referred to in the block allocation map is indicated as other than valid , preventing preservation by transfer out to a transfer unit prior to erase , thereby resulting in complete erasure of said sector during the erase operation , said determination (flash memory device) made by comparing the mapping information residing within the flash memory and said file indication map , and replacement is made after said comparison , and a copy of the file indication map residing in the file system used by the operating system is made in a flash translation layer separately from said file indication map residing in the file syst m , thereby providing a status record of a former file indication map for comparison against subsequent modifications of the file indication map residing in the file system used by the operating system .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US5996054A

Filed: 1996-09-12     Issued: 1999-11-30

Efficient virtualized mapping space for log device data storage system

(Original Assignee) Veritas Software Corp     (Current Assignee) Veritas Technologies LLC

Joel E. Ledain, John A. Colgrove, Dan Koren
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system (computer system) , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US5996054A
CLAIM 1
. A log device system coupleable to a computer system (computer system) that executes an operating system that includes a filesystem , said computer system further including (i) a primary storage device , including a first rotating media controller , having a first data storage space provided on a first non-volatile rotating media , said filesystem directing the storage of filesystem data blocks within said first data storage space , and (ii) a primary device driver , executable by said computer system in connection with the execution of said operating system , that manages the transfer of filesystem data blocks with respect to said primary data storage device within a first real addressable storage space , said log device system comprising : a) a log storage device including a second rotating media controller , having a second data storage space provided on a second non-volatile rotating media , said second data storage space providing for the storage of data segments within a second real addressable storage space ;
and b) a log device driver , executable by said computer system in connection with the execution of said operating system , that manages the transfer of data with respect to said log storage device , said log device driver implementing a virtual address storage space that corresponds to said first real addressable storage space and utilizing a translation map relating a predetermined set of addresses within said first real addressable storage space with a predetermined address within said second real addressable storage space , said log device driver providing for predetermined filesystem data blocks to be stored with data defining a corresponding portion of said virtual address storage space and for said predetermined filesystem data blocks to be stored within a predetermined data segment , said log device driver being coupleable to said filesystem and to said primary device driver to transfer filesystem data blocks thereinbetween upon reference to said first real addressable storage space by said filesystem .

US9632727B2
CLAIM 2
. The apparatus of claim 1 , wherein the indexer assigns logical addresses to physical addresses by use of index entries , and wherein the indexer removes an index entry (data blocks storing data) corresponding to the identified logical address in response to the message .
US5996054A
CLAIM 2
. The log device system of claim 1 wherein said log device driver provides for the storage of filesystem data blocks and log device data blocks within said predetermined data segment , said log device data blocks storing data (index entry) permitting said log device driver to reference said predetermined filesystem data blocks by reference to said predetermined data segment .

US9632727B2
CLAIM 3
. The apparatus of claim 1 , wherein the indexer assigns logical addresses to physical addresses by use of index metadata (primary data) maintained in a memory of the storage controller .
US5996054A
CLAIM 1
. A log device system coupleable to a computer system that executes an operating system that includes a filesystem , said computer system further including (i) a primary storage device , including a first rotating media controller , having a first data storage space provided on a first non-volatile rotating media , said filesystem directing the storage of filesystem data blocks within said first data storage space , and (ii) a primary device driver , executable by said computer system in connection with the execution of said operating system , that manages the transfer of filesystem data blocks with respect to said primary data (index metadata) storage device within a first real addressable storage space , said log device system comprising : a) a log storage device including a second rotating media controller , having a second data storage space provided on a second non-volatile rotating media , said second data storage space providing for the storage of data segments within a second real addressable storage space ;
and b) a log device driver , executable by said computer system in connection with the execution of said operating system , that manages the transfer of data with respect to said log storage device , said log device driver implementing a virtual address storage space that corresponds to said first real addressable storage space and utilizing a translation map relating a predetermined set of addresses within said first real addressable storage space with a predetermined address within said second real addressable storage space , said log device driver providing for predetermined filesystem data blocks to be stored with data defining a corresponding portion of said virtual address storage space and for said predetermined filesystem data blocks to be stored within a predetermined data segment , said log device driver being coupleable to said filesystem and to said primary device driver to transfer filesystem data blocks thereinbetween upon reference to said first real addressable storage space by said filesystem .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system (computer system) , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
US5996054A
CLAIM 1
. A log device system coupleable to a computer system (computer system) that executes an operating system that includes a filesystem , said computer system further including (i) a primary storage device , including a first rotating media controller , having a first data storage space provided on a first non-volatile rotating media , said filesystem directing the storage of filesystem data blocks within said first data storage space , and (ii) a primary device driver , executable by said computer system in connection with the execution of said operating system , that manages the transfer of filesystem data blocks with respect to said primary data storage device within a first real addressable storage space , said log device system comprising : a) a log storage device including a second rotating media controller , having a second data storage space provided on a second non-volatile rotating media , said second data storage space providing for the storage of data segments within a second real addressable storage space ;
and b) a log device driver , executable by said computer system in connection with the execution of said operating system , that manages the transfer of data with respect to said log storage device , said log device driver implementing a virtual address storage space that corresponds to said first real addressable storage space and utilizing a translation map relating a predetermined set of addresses within said first real addressable storage space with a predetermined address within said second real addressable storage space , said log device driver providing for predetermined filesystem data blocks to be stored with data defining a corresponding portion of said virtual address storage space and for said predetermined filesystem data blocks to be stored within a predetermined data segment , said log device driver being coupleable to said filesystem and to said primary device driver to transfer filesystem data blocks thereinbetween upon reference to said first real addressable storage space by said filesystem .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US5758118A

Filed: 1995-12-08     Issued: 1998-05-26

Methods and data storage devices for RAID expansion by on-line addition of new DASDs

(Original Assignee) International Business Machines Corp     (Current Assignee) International Business Machines Corp

David Mun-Hien Choy, Jaishankar Moothedath Menon
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium (write operation) in response to requests from a computer system , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US5758118A
CLAIM 5
. The method of claim 1 , further comprising the steps of suspending read/write operation (solid state storage medium) s from being performed upon the DASDs during the modifying step .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer (readable instructions) System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
US5758118A
CLAIM 13
. The method of claim 1 , wherein the stored mapping instructions comprise a program of machine-readable instructions (Small Computer) executable by the controller to identify storage units corresponding to addresses received at the address input .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor (comprise logic) coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US5758118A
CLAIM 11
. The method of claim 1 , wherein the rows comprise logic (storage processor) al rows .

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (comprise logic) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
US5758118A
CLAIM 11
. The method of claim 1 , wherein the rows comprise logic (storage processor) al rows .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor (comprise logic) returns a predetermined data string .
US5758118A
CLAIM 11
. The method of claim 1 , wherein the rows comprise logic (storage processor) al rows .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US5799200A

Filed: 1995-09-28     Issued: 1998-08-25

Power failure responsive apparatus and method having a shadow dram, a flash ROM, an auxiliary battery, and a controller

(Original Assignee) EMC Corp     (Current Assignee) EMC Corp

William A. Brant, Michael E. Nielson, Edde Tin-Shek Tang
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system , including storing data (storing data) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US5799200A
CLAIM 8
. Apparatus for preserving data that is stored in a volatile manner within a data processing system that is enabled by a primary electrical power source of a non-battery type that is subject to a loss of power , the data processing system employing a first volatile dynamic random access memory for storing data (storing data) , the data processing system further employing a second volatile dynamic random access memory that provides backup data storage for the first volatile dynamic random access memory , and the second volatile dynamic random access memory being physically removable from the data processing system , said apparatus comprising : a mounting base physically replacing the second volatile dynamic random access memory ;
a third volatile dynamic random access memory mounted on said mounting base to be carried therewith ;
said third volatile dynamic random access memory providing backup data storage for the first volatile dynamic random access memory ;
a non-volatile Flash ROM mounted on said mounting base together with said third volatile dynamic random access memory to be carried with said mounting base ;
a controller mounted on said mounting base together with said third volatile dynamic random access memory to be carried by said mounting base ;
an auxiliary battery power source mounted on said mounting base together with said third volatile dynamic random access memory and said non-volatile , said auxiliary battery power source connected to selectively provide battery power to said controller , said controller including initializing means and data preservation means ;
said controller initializing means responding to each initial application of power from the primary source to the data processing system for applying an erase signal to said non-volatile Flash ROM for clearing said non-volatile Flash ROM ;
said controller data preservation means including loss of power detecting means for subsequently detecting loss of power from the primary power source ;
said controller data preservation means including transferring means immediately responsive to said loss of power detecting means for transferring data contained in said third volatile dynamic random access memory into said non-volatile Flash ROM ;
said controller data preservation means being responsive to said controller loss of power detecting means for temporarily and immediately applying power from said auxiliary battery power source to said controller until such time as data transfer from said third volatile dynamic random access memory to said non-volatile Flash ROM has been completed .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology (when i) Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
US5799200A
CLAIM 7
. The method in accordance with claim 6 which further includes the steps of ;
storing a signal indicating that said data returning step was initiated , determining that said signal has been previously stored , and preventing a subsequent execution of said data returning step when i (Advanced Technology) t is determined that said signal has been previously stored .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (storing data) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
US5799200A
CLAIM 8
. Apparatus for preserving data that is stored in a volatile manner within a data processing system that is enabled by a primary electrical power source of a non-battery type that is subject to a loss of power , the data processing system employing a first volatile dynamic random access memory for storing data (storing data) , the data processing system further employing a second volatile dynamic random access memory that provides backup data storage for the first volatile dynamic random access memory , and the second volatile dynamic random access memory being physically removable from the data processing system , said apparatus comprising : a mounting base physically replacing the second volatile dynamic random access memory ;
a third volatile dynamic random access memory mounted on said mounting base to be carried therewith ;
said third volatile dynamic random access memory providing backup data storage for the first volatile dynamic random access memory ;
a non-volatile Flash ROM mounted on said mounting base together with said third volatile dynamic random access memory to be carried with said mounting base ;
a controller mounted on said mounting base together with said third volatile dynamic random access memory to be carried by said mounting base ;
an auxiliary battery power source mounted on said mounting base together with said third volatile dynamic random access memory and said non-volatile , said auxiliary battery power source connected to selectively provide battery power to said controller , said controller including initializing means and data preservation means ;
said controller initializing means responding to each initial application of power from the primary source to the data processing system for applying an erase signal to said non-volatile Flash ROM for clearing said non-volatile Flash ROM ;
said controller data preservation means including loss of power detecting means for subsequently detecting loss of power from the primary power source ;
said controller data preservation means including transferring means immediately responsive to said loss of power detecting means for transferring data contained in said third volatile dynamic random access memory into said non-volatile Flash ROM ;
said controller data preservation means being responsive to said controller loss of power detecting means for temporarily and immediately applying power from said auxiliary battery power source to said controller until such time as data transfer from said third volatile dynamic random access memory to said non-volatile Flash ROM has been completed .

US9632727B2
CLAIM 8
. The system of claim 7 , further comprising means for providing a storage interface (said module) to accept requests to perform storage operations on the solid-state storage medium in reference to the logical blocks and to accept the message identifying the logical block that is not being used to reference data stored on the solid-state storage medium .
US5799200A
CLAIM 10
. Modular memory apparatus for a data processing system susceptible to interruption of system power provided by a primary electrical power source , said modular memory apparatus comprising : a module connectable to the data processing system ;
a volatile memory element at least carried by said module (storage interface) , said volatile memory element for storing data accessible during operation of the data processing system ;
a non-volatile memory element at least carried by said module together with said volatile memory element , said non-volatile memory element for storing at least some of the data stored in said volatile memory element ;
an auxiliary battery power source carried by said module together with said volatile memory element and said non-volatile memory element ;
and a controller at least carried by said module together with said volatile memory element , said non-volatile memory element , and said auxiliary battery power source , said module , together with said volatile memory element , said non-volatile memory element , said auxiliary battery power source connectable as a single unit to said data processing system , said controller for detecting the interruption of the system power and , responsive thereto , to effectuate powering of said controller by said auxiliary battery power source , and for effectuating transfer of the data stored in said volatile memory element to said non-volatile memory element .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface (said module) configured to communicate with a storage client ;

a storage processor (data store) coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US5799200A
CLAIM 1
. Apparatus for preserving data that is stored in a volatile manner in a data processing system that is enabled by a primary electrical power source of a non-battery type that is subject to failure , said data processing system employing a first volatile dynamic random access memory for storing said data and a second volatile dynamic random access memory providing backup data storage for said data store (storage processor) d in said first volatile dynamic random access memory , comprising : a non-volatile Flash ROM connectable to the data processing system ;
a controller positioned together with said Flash ROM to be connectable to the data processing system together with connection of said Flash ROM to the data processing system including initializing means and data preservation means ;
said initializing means responding to each initial application of power from the primary source to said data processing system for applying an erase signal to said Flash ROM for clearing said Flash ROM ;
said data preservation means including loss of power detecting means for subsequently detecting loss of power from the primary power source ;
said data preservation means including transferring means immediately responsive to said loss of power detecting means for transferring the data contained in said second dynamic random access memory into said Flash ROM ;
an auxiliary battery power source positioned together with said Flash ROM and said controller ;
and power applying means responsive to said loss of power detecting means for temporarily and immediately applying power from said auxiliary battery power source to said controller until such time as the data transfer from said second dynamic random access memory to said Flash ROM is completed .

US5799200A
CLAIM 10
. Modular memory apparatus for a data processing system susceptible to interruption of system power provided by a primary electrical power source , said modular memory apparatus comprising : a module connectable to the data processing system ;
a volatile memory element at least carried by said module (storage interface) , said volatile memory element for storing data accessible during operation of the data processing system ;
a non-volatile memory element at least carried by said module together with said volatile memory element , said non-volatile memory element for storing at least some of the data stored in said volatile memory element ;
an auxiliary battery power source carried by said module together with said volatile memory element and said non-volatile memory element ;
and a controller at least carried by said module together with said volatile memory element , said non-volatile memory element , and said auxiliary battery power source , said module , together with said volatile memory element , said non-volatile memory element , said auxiliary battery power source connectable as a single unit to said data processing system , said controller for detecting the interruption of the system power and , responsive thereto , to effectuate powering of said controller by said auxiliary battery power source , and for effectuating transfer of the data stored in said volatile memory element to said non-volatile memory element .

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (data store) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
US5799200A
CLAIM 1
. Apparatus for preserving data that is stored in a volatile manner in a data processing system that is enabled by a primary electrical power source of a non-battery type that is subject to failure , said data processing system employing a first volatile dynamic random access memory for storing said data and a second volatile dynamic random access memory providing backup data storage for said data store (storage processor) d in said first volatile dynamic random access memory , comprising : a non-volatile Flash ROM connectable to the data processing system ;
a controller positioned together with said Flash ROM to be connectable to the data processing system together with connection of said Flash ROM to the data processing system including initializing means and data preservation means ;
said initializing means responding to each initial application of power from the primary source to said data processing system for applying an erase signal to said Flash ROM for clearing said Flash ROM ;
said data preservation means including loss of power detecting means for subsequently detecting loss of power from the primary power source ;
said data preservation means including transferring means immediately responsive to said loss of power detecting means for transferring the data contained in said second dynamic random access memory into said Flash ROM ;
an auxiliary battery power source positioned together with said Flash ROM and said controller ;
and power applying means responsive to said loss of power detecting means for temporarily and immediately applying power from said auxiliary battery power source to said controller until such time as the data transfer from said second dynamic random access memory to said Flash ROM is completed .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one (memory apparatus) or more logical addresses included in the empty-block directive command , the storage processor (data store) returns a predetermined data string .
US5799200A
CLAIM 1
. Apparatus for preserving data that is stored in a volatile manner in a data processing system that is enabled by a primary electrical power source of a non-battery type that is subject to failure , said data processing system employing a first volatile dynamic random access memory for storing said data and a second volatile dynamic random access memory providing backup data storage for said data store (storage processor) d in said first volatile dynamic random access memory , comprising : a non-volatile Flash ROM connectable to the data processing system ;
a controller positioned together with said Flash ROM to be connectable to the data processing system together with connection of said Flash ROM to the data processing system including initializing means and data preservation means ;
said initializing means responding to each initial application of power from the primary source to said data processing system for applying an erase signal to said Flash ROM for clearing said Flash ROM ;
said data preservation means including loss of power detecting means for subsequently detecting loss of power from the primary power source ;
said data preservation means including transferring means immediately responsive to said loss of power detecting means for transferring the data contained in said second dynamic random access memory into said Flash ROM ;
an auxiliary battery power source positioned together with said Flash ROM and said controller ;
and power applying means responsive to said loss of power detecting means for temporarily and immediately applying power from said auxiliary battery power source to said controller until such time as the data transfer from said second dynamic random access memory to said Flash ROM is completed .

US5799200A
CLAIM 10
. Modular memory apparatus (read request specifying one) for a data processing system susceptible to interruption of system power provided by a primary electrical power source , said modular memory apparatus comprising : a module connectable to the data processing system ;
a volatile memory element at least carried by said module , said volatile memory element for storing data accessible during operation of the data processing system ;
a non-volatile memory element at least carried by said module together with said volatile memory element , said non-volatile memory element for storing at least some of the data stored in said volatile memory element ;
an auxiliary battery power source carried by said module together with said volatile memory element and said non-volatile memory element ;
and a controller at least carried by said module together with said volatile memory element , said non-volatile memory element , and said auxiliary battery power source , said module , together with said volatile memory element , said non-volatile memory element , said auxiliary battery power source connectable as a single unit to said data processing system , said controller for detecting the interruption of the system power and , responsive thereto , to effectuate powering of said controller by said auxiliary battery power source , and for effectuating transfer of the data stored in said volatile memory element to said non-volatile memory element .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US5835935A

Filed: 1995-09-13     Issued: 1998-11-10

Method of and architecture for controlling system data with automatic wear leveling in a semiconductor non-volatile mass storage memory

(Original Assignee) Lexar Media Inc     (Current Assignee) Micron Technology Inc

Petro Estakhri, Mahmud Assar, Robert Alan Reid, Berhanu Iman
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium (write operation) in response to requests from a computer system , including storing data (said memory, store information, storing data) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data (said memory, store information, storing data) pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US5835935A
CLAIM 1
. A mass storage system comprising : at least one semiconductor non-volatile memory means having a plurality of individually addressable sector storage locations for storing information ;
and a controller circuit coupled to said memory (store data, storing data) means and operative to define a first partition within said memory means having sector storage locations for storing user files , and a second partition within said memory means having sector storage locations for storing system files , the sector storage locations of said second partition being grouped in a plurality of clusters , each said cluster being uniquely identifiable by a predetermined logical block address , said controller circuit being further operative upon initial access of a particular cluster identified by a particular logical block address to store a first system sector information in one of the sector storage locations of the particular cluster , and upon subsequent accesses of the particular cluster identified by the particular logical block address , the controller circuit further being operative to store replacement system sector information into an empty sector storage location of the particular cluster , leaving intact the system sector information previously stored in the particular cluster , said controller circuit further being operative to generate an indication for subsequently identifying the location of the most recently stored sector information within the cluster , thereby avoiding the need to erase the memory means every time a cluster identified by a logical block address is re-accessed .

US5835935A
CLAIM 10
. A memory system for storing data (store data, storing data) comprising : a semiconductor non-volatile mass storage memory partitioned into at least two areas , one of which includes sector storage locations used to store system files , a predetermined plurality of said sector storage locations of said one area being grouped in clusters , each said cluster being uniquely identifiable by a predetermined logical block address , a first sector storage location of a particular cluster being used for storing system sector information upon initial access of the particular cluster , and upon re-accesses of the particular cluster , prior to erasure of the particular cluster' ;
s sector information , subsequent sector storage locations of the particular cluster being used for storing replacement system sector information ;
and a control circuit coupled to the semiconductor non-volatile mass storage memory for controlling the partitioning thereof , for storing system sector information within the cluster , and for storing replacement system sector information within the cluster while leaving intact the system sector information previously stored in the particular cluster , said control circuit further being operative to generate an indication of the location of the most recent sector information stored within the particular cluster , thereby avoiding the need to erase the non-volatile mass storage memory every time a cluster identified by a logical block address is re-accessed .

US5835935A
CLAIM 12
. The memory system as recited in claim 10 wherein a write operation (solid state storage medium) is completed by writing replacement system sector information into an empty sector storage location within the cluster corresponding to an appropriate logical block address .

US5835935A
CLAIM 20
. A method of storing information in a semiconductor nonvolatile mass storage memory adapted to store information (store data, storing data) in sector storage spaces , comprising : partitioning the memory into a first group of sector storage spaces for storing a plurality of user files and a second group of sector storage spaces for storing a plurality of system files ;
combining the sector storage spaces of the second such group into clusters of storage spaces , each such cluster being uniquely identifiable by a logical block address and used for storing a current system sector within one of the sector storage spaces in that cluster ;
storing a system file in a particular one of said clusters ;
determining which sector storage space in the particular cluster is an empty sector storage space ;
writing a replacement system file for the stored system file into the empty sector storage space ;
providing an indication for identifying the location of the most recently written sector storage space of the particular cluster ;
and marking the particular cluster as old when a last sector storage space within the particular cluster is replaced and there is no remaining empty sector storage space within the particular cluster .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (said memory, store information, storing data) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
US5835935A
CLAIM 1
. A mass storage system comprising : at least one semiconductor non-volatile memory means having a plurality of individually addressable sector storage locations for storing information ;
and a controller circuit coupled to said memory (store data, storing data) means and operative to define a first partition within said memory means having sector storage locations for storing user files , and a second partition within said memory means having sector storage locations for storing system files , the sector storage locations of said second partition being grouped in a plurality of clusters , each said cluster being uniquely identifiable by a predetermined logical block address , said controller circuit being further operative upon initial access of a particular cluster identified by a particular logical block address to store a first system sector information in one of the sector storage locations of the particular cluster , and upon subsequent accesses of the particular cluster identified by the particular logical block address , the controller circuit further being operative to store replacement system sector information into an empty sector storage location of the particular cluster , leaving intact the system sector information previously stored in the particular cluster , said controller circuit further being operative to generate an indication for subsequently identifying the location of the most recently stored sector information within the cluster , thereby avoiding the need to erase the memory means every time a cluster identified by a logical block address is re-accessed .

US5835935A
CLAIM 10
. A memory system for storing data (store data, storing data) comprising : a semiconductor non-volatile mass storage memory partitioned into at least two areas , one of which includes sector storage locations used to store system files , a predetermined plurality of said sector storage locations of said one area being grouped in clusters , each said cluster being uniquely identifiable by a predetermined logical block address , a first sector storage location of a particular cluster being used for storing system sector information upon initial access of the particular cluster , and upon re-accesses of the particular cluster , prior to erasure of the particular cluster' ;
s sector information , subsequent sector storage locations of the particular cluster being used for storing replacement system sector information ;
and a control circuit coupled to the semiconductor non-volatile mass storage memory for controlling the partitioning thereof , for storing system sector information within the cluster , and for storing replacement system sector information within the cluster while leaving intact the system sector information previously stored in the particular cluster , said control circuit further being operative to generate an indication of the location of the most recent sector information stored within the particular cluster , thereby avoiding the need to erase the non-volatile mass storage memory every time a cluster identified by a logical block address is re-accessed .

US5835935A
CLAIM 20
. A method of storing information in a semiconductor nonvolatile mass storage memory adapted to store information (store data, storing data) in sector storage spaces , comprising : partitioning the memory into a first group of sector storage spaces for storing a plurality of user files and a second group of sector storage spaces for storing a plurality of system files ;
combining the sector storage spaces of the second such group into clusters of storage spaces , each such cluster being uniquely identifiable by a logical block address and used for storing a current system sector within one of the sector storage spaces in that cluster ;
storing a system file in a particular one of said clusters ;
determining which sector storage space in the particular cluster is an empty sector storage space ;
writing a replacement system file for the stored system file into the empty sector storage space ;
providing an indication for identifying the location of the most recently written sector storage space of the particular cluster ;
and marking the particular cluster as old when a last sector storage space within the particular cluster is replaced and there is no remaining empty sector storage space within the particular cluster .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor coupled to the storage interface ;

a flash memory device (flash memory device) coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US5835935A
CLAIM 2
. The mass storage system as recited in claim 1 wherein the non-volatile memory means includes flash memory device (flash memory device) s .

US9632727B2
CLAIM 13
. The system of claim 12 , wherein the logical-to-physical translation layer is stored in the flash memory device (flash memory device) .
US5835935A
CLAIM 2
. The mass storage system as recited in claim 1 wherein the non-volatile memory means includes flash memory device (flash memory device) s .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US5754563A

Filed: 1995-09-11     Issued: 1998-05-19

Byte-parallel system for implementing reed-solomon error-correcting codes

(Original Assignee) ECC Tech Inc     (Current Assignee) ECC Tech Inc

Philip E. White
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system , including storing data (message bits, said memory) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data (message bits, said memory) pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US5754563A
CLAIM 3
. The parallel encoder of claim 2 wherein : each one of said byte multiplier circuits includes w product bit generator circuits in parallel , each said product bit generator circuit including w bit multiplier circuits , each bit multiplier circuit receiving a different one of w variable bits forming the associated variable message byte and generating an intermediate product bit representing the product of its associated one of the variable message bits (store data, storing data) and an associated one of w constant bits determined by the associated generator byte where each constant bit is predetermined to equal either 0 or 1 ;
and bit adder circuitry associated with the bit multiplier circuits for receiving the intermediate product bits in parallel and for pairing the intermediate product bits for addition in successive bit-additive stages including a final bit-additive stage for generating its associated one of w bits that together form the intermediate byte associated with said one byte multiplier circuit .

US5754563A
CLAIM 21
. An error correcting system including : a parallel encoder for receiving message words , each message word including K message bytes where each of the message bytes includes w binary bits , said parallel encoder generating as its output a code word having N bytes including the message bytes plus R redundant bytes ;
N parallel data channels for receiving the code word in byte parallel fashion and providing a parallel data channel output based on the code word ;
a parallel decoder for receiving the parallel data channel output as a received word and , based on the received word , generating a most-likely error word and a most-likely code word each having N bytes ;
and a failure location system , coupled to receive failure location information from said data channels and further coupled to provide byte failure location information to the parallel decoder , said failure location system including a microprocessing means for sequentially reading every location in the data handling channels and accumulating failure information associated with each of said locations ;
said processor system being adapted to identify at least one of said locations as a failed location based on a sensed frequency of errors at least equal to a predetermined threshold frequency ;
said failure location system further including a memory means for storing a record of failed locations , said memory (store data, storing data) providing the byte failure location information to the parallel decoder .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface (single semiconductor, parallel data) configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial (single semiconductor, parallel data) Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer (processor system) System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface (input bit) .
US5754563A
CLAIM 7
. The parallel encoder of claim 1 , wherein : said redundant byte generators are fabricated on a single semiconductor (bus interface, external Serial, external Serial Advanced Technology Attachment bus interface, external SATA bus interface) chip .

US5754563A
CLAIM 10
. The syndrome generating circuitry of claim 9 , wherein : each one of said byte multiplier circuits includes w product bit generator circuits arranged in parallel , each said product bit generator circuit including w bit multiplier circuits , each bit multiplier circuit receiving a different one of the w variable input bit (Fibre Channel interface) s of the associated variable received word byte and generating an intermediate product bit representing the product of its associated variable input bit and an associated one of w predetermined constant bits of said constant error detection byte ;
and bit adder circuitry associated with the bit multiplier circuits for receiving the intermediate product bits in parallel and for pairing them for addition in successive bit-additive stages including a final bit-additive stage for generating its associated one of w intermediate product bits that together form the intermediate product byte associated with said one byte multiplier circuit .

US5754563A
CLAIM 21
. An error correcting system including : a parallel encoder for receiving message words , each message word including K message bytes where each of the message bytes includes w binary bits , said parallel encoder generating as its output a code word having N bytes including the message bytes plus R redundant bytes ;
N parallel data (bus interface, external Serial, external Serial Advanced Technology Attachment bus interface, external SATA bus interface) channels for receiving the code word in byte parallel fashion and providing a parallel data channel output based on the code word ;
a parallel decoder for receiving the parallel data channel output as a received word and , based on the received word , generating a most-likely error word and a most-likely code word each having N bytes ;
and a failure location system , coupled to receive failure location information from said data channels and further coupled to provide byte failure location information to the parallel decoder , said failure location system including a microprocessing means for sequentially reading every location in the data handling channels and accumulating failure information associated with each of said locations ;
said processor system (Small Computer, uniform logic level) being adapted to identify at least one of said locations as a failed location based on a sensed frequency of errors at least equal to a predetermined threshold frequency ;
said failure location system further including a memory means for storing a record of failed locations , said memory providing the byte failure location information to the parallel decoder .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (message bits, said memory) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
US5754563A
CLAIM 3
. The parallel encoder of claim 2 wherein : each one of said byte multiplier circuits includes w product bit generator circuits in parallel , each said product bit generator circuit including w bit multiplier circuits , each bit multiplier circuit receiving a different one of w variable bits forming the associated variable message byte and generating an intermediate product bit representing the product of its associated one of the variable message bits (store data, storing data) and an associated one of w constant bits determined by the associated generator byte where each constant bit is predetermined to equal either 0 or 1 ;
and bit adder circuitry associated with the bit multiplier circuits for receiving the intermediate product bits in parallel and for pairing the intermediate product bits for addition in successive bit-additive stages including a final bit-additive stage for generating its associated one of w bits that together form the intermediate byte associated with said one byte multiplier circuit .

US5754563A
CLAIM 21
. An error correcting system including : a parallel encoder for receiving message words , each message word including K message bytes where each of the message bytes includes w binary bits , said parallel encoder generating as its output a code word having N bytes including the message bytes plus R redundant bytes ;
N parallel data channels for receiving the code word in byte parallel fashion and providing a parallel data channel output based on the code word ;
a parallel decoder for receiving the parallel data channel output as a received word and , based on the received word , generating a most-likely error word and a most-likely code word each having N bytes ;
and a failure location system , coupled to receive failure location information from said data channels and further coupled to provide byte failure location information to the parallel decoder , said failure location system including a microprocessing means for sequentially reading every location in the data handling channels and accumulating failure information associated with each of said locations ;
said processor system being adapted to identify at least one of said locations as a failed location based on a sensed frequency of errors at least equal to a predetermined threshold frequency ;
said failure location system further including a memory means for storing a record of failed locations , said memory (store data, storing data) providing the byte failure location information to the parallel decoder .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request (n information) specifying one or more logical addresses included in the empty-block directive command , the storage processor returns a predetermined data string .
US5754563A
CLAIM 21
. An error correcting system including : a parallel encoder for receiving message words , each message word including K message bytes where each of the message bytes includes w binary bits , said parallel encoder generating as its output a code word having N bytes including the message bytes plus R redundant bytes ;
N parallel data channels for receiving the code word in byte parallel fashion and providing a parallel data channel output based on the code word ;
a parallel decoder for receiving the parallel data channel output as a received word and , based on the received word , generating a most-likely error word and a most-likely code word each having N bytes ;
and a failure location system , coupled to receive failure location information (read request) from said data channels and further coupled to provide byte failure location information to the parallel decoder , said failure location system including a microprocessing means for sequentially reading every location in the data handling channels and accumulating failure information associated with each of said locations ;
said processor system being adapted to identify at least one of said locations as a failed location based on a sensed frequency of errors at least equal to a predetermined threshold frequency ;
said failure location system further including a memory means for storing a record of failed locations , said memory providing the byte failure location information to the parallel decoder .

US9632727B2
CLAIM 16
. The system of claim 15 , wherein data bits (data bits) of the predetermined data string have a uniform logic level (processor system) .
US5754563A
CLAIM 21
. An error correcting system including : a parallel encoder for receiving message words , each message word including K message bytes where each of the message bytes includes w binary bits , said parallel encoder generating as its output a code word having N bytes including the message bytes plus R redundant bytes ;
N parallel data channels for receiving the code word in byte parallel fashion and providing a parallel data channel output based on the code word ;
a parallel decoder for receiving the parallel data channel output as a received word and , based on the received word , generating a most-likely error word and a most-likely code word each having N bytes ;
and a failure location system , coupled to receive failure location information from said data channels and further coupled to provide byte failure location information to the parallel decoder , said failure location system including a microprocessing means for sequentially reading every location in the data handling channels and accumulating failure information associated with each of said locations ;
said processor system (Small Computer, uniform logic level) being adapted to identify at least one of said locations as a failed location based on a sensed frequency of errors at least equal to a predetermined threshold frequency ;
said failure location system further including a memory means for storing a record of failed locations , said memory providing the byte failure location information to the parallel decoder .

US5754563A
CLAIM 24
. A variable byte multiplier circuit for multiplying two variable data bytes wherein each of the variable data bytes is composed of w data bits (data bits) and w is an integer greater than one ;
said variable-byte multiplier circuit including : w constant byte multipliers in parallel , each one of the constant byte multipliers receiving a first variable byte in parallel and generating a first intermediate byte representing the product of the first variable byte and a constant byte corresponding to said one constant byte multiplier , wherein each of the constant bytes is a predetermined constant element of a finite field ;
w logic sets in parallel for receiving a second variable byte , each of said logic sets receiving a different one of w bits of the second variable byte and further receiving a different one of said first intermediate bytes ;
wherein each one of said logic sets includes w AND logic gates in parallel , each of the AND logic gates receiving as bit inputs (i) the bit of said second variable byte corresponding to said one logic set , and (ii) a different one of w bits of the first intermediate byte that corresponds to said one logic set ;
each of said logic gates performing an AND logic function on its inputs to generate an intermediate bit , with the logic gates of the logic set together generating a second intermediate byte composed of the intermediate bits ;
and byte adder circuitry for receiving the second intermediate bytes from said logic sets in parallel and for pairing said second intermediate bytes in a plurality of successive byte-additive stages including a final byte-additive stage that generates a resultant byte representing a product of the first and second variable bytes .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US5845313A

Filed: 1995-07-31     Issued: 1998-12-01

Direct logical block addressing flash memory mass storage architecture

(Original Assignee) Lexar Media Inc     (Current Assignee) Micron Technology Inc

Petro Estakhri, Mahmud Assar
US9632727B2
CLAIM 5
. The apparatus of claim 1 , further comprising a garbage collector (logical block address) configured to designate that the physical address previously assigned to the identified logical address comprises data suitable for removal from the solid-state storage medium in response to the message .
US5845313A
CLAIM 1
. A mass storage device having nonvolatile memory , the storage device being coupled to an external digital system for storing binary information therefor in the nonvolatile memory , the external digital system including means for generating a plurality of logical block address (garbage collector) es for use in storing or reading data , the storage device comprising : a . a volatile memory device having a plurality of volatile memory locations each of which is uniquely addressable by one of the logical block addresses , and wherein each of the volatile memory locations is configured to store a physical block address without requiring the storage of a corresponding logical block address ;
b . one or more nonvolatile memory devices each having a plurality of nonvolatile data blocks , wherein each block is selectively programmable and erasable and further wherein each data block is uniquely addressable by one of the physical block addresses , and further wherein the plurality of nonvolatile data blocks has a plurality of used/free flags , one stored with each data block in the one or more nonvolatile memory devices for indicating whether a data block contains data ;
and c . a controller for receiving a block of data from the external digital system to be stored in the one or more nonvolatile memory devices , for receiving a target logical block address from the external system , for identifying a free data block within the nonvolatile data blocks having no data stored therein , for storing the physical block address of the free data block in the volatile memory location that corresponds to the target logical block address , and for periodically erasing all data blocks of the nonvolatile memory devices having flags which are set , whereby an erase cycle is not needed each time the external system writes to the storage device ;
wherein the used/free flags stored in the one or more nonvolatile memory devices which correlate to the physical block addresses of the plurality of nonvolatile data blocks are copied to the volatile memory locations during a power-up and a system reset .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor (data store) coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US5845313A
CLAIM 1
. A mass storage device having nonvolatile memory , the storage device being coupled to an external digital system for storing binary information therefor in the nonvolatile memory , the external digital system including means for generating a plurality of logical block addresses for use in storing or reading data , the storage device comprising : a . a volatile memory device having a plurality of volatile memory locations each of which is uniquely addressable by one of the logical block addresses , and wherein each of the volatile memory locations is configured to store a physical block address without requiring the storage of a corresponding logical block address ;
b . one or more nonvolatile memory devices each having a plurality of nonvolatile data blocks , wherein each block is selectively programmable and erasable and further wherein each data block is uniquely addressable by one of the physical block addresses , and further wherein the plurality of nonvolatile data blocks has a plurality of used/free flags , one stored with each data block in the one or more nonvolatile memory devices for indicating whether a data block contains data ;
and c . a controller for receiving a block of data from the external digital system to be stored in the one or more nonvolatile memory devices , for receiving a target logical block address from the external system , for identifying a free data block within the nonvolatile data blocks having no data store (storage processor) d therein , for storing the physical block address of the free data block in the volatile memory location that corresponds to the target logical block address , and for periodically erasing all data blocks of the nonvolatile memory devices having flags which are set , whereby an erase cycle is not needed each time the external system writes to the storage device ;
wherein the used/free flags stored in the one or more nonvolatile memory devices which correlate to the physical block addresses of the plurality of nonvolatile data blocks are copied to the volatile memory locations during a power-up and a system reset .

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (data store) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
US5845313A
CLAIM 1
. A mass storage device having nonvolatile memory , the storage device being coupled to an external digital system for storing binary information therefor in the nonvolatile memory , the external digital system including means for generating a plurality of logical block addresses for use in storing or reading data , the storage device comprising : a . a volatile memory device having a plurality of volatile memory locations each of which is uniquely addressable by one of the logical block addresses , and wherein each of the volatile memory locations is configured to store a physical block address without requiring the storage of a corresponding logical block address ;
b . one or more nonvolatile memory devices each having a plurality of nonvolatile data blocks , wherein each block is selectively programmable and erasable and further wherein each data block is uniquely addressable by one of the physical block addresses , and further wherein the plurality of nonvolatile data blocks has a plurality of used/free flags , one stored with each data block in the one or more nonvolatile memory devices for indicating whether a data block contains data ;
and c . a controller for receiving a block of data from the external digital system to be stored in the one or more nonvolatile memory devices , for receiving a target logical block address from the external system , for identifying a free data block within the nonvolatile data blocks having no data store (storage processor) d therein , for storing the physical block address of the free data block in the volatile memory location that corresponds to the target logical block address , and for periodically erasing all data blocks of the nonvolatile memory devices having flags which are set , whereby an erase cycle is not needed each time the external system writes to the storage device ;
wherein the used/free flags stored in the one or more nonvolatile memory devices which correlate to the physical block addresses of the plurality of nonvolatile data blocks are copied to the volatile memory locations during a power-up and a system reset .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor (data store) returns a predetermined data string .
US5845313A
CLAIM 1
. A mass storage device having nonvolatile memory , the storage device being coupled to an external digital system for storing binary information therefor in the nonvolatile memory , the external digital system including means for generating a plurality of logical block addresses for use in storing or reading data , the storage device comprising : a . a volatile memory device having a plurality of volatile memory locations each of which is uniquely addressable by one of the logical block addresses , and wherein each of the volatile memory locations is configured to store a physical block address without requiring the storage of a corresponding logical block address ;
b . one or more nonvolatile memory devices each having a plurality of nonvolatile data blocks , wherein each block is selectively programmable and erasable and further wherein each data block is uniquely addressable by one of the physical block addresses , and further wherein the plurality of nonvolatile data blocks has a plurality of used/free flags , one stored with each data block in the one or more nonvolatile memory devices for indicating whether a data block contains data ;
and c . a controller for receiving a block of data from the external digital system to be stored in the one or more nonvolatile memory devices , for receiving a target logical block address from the external system , for identifying a free data block within the nonvolatile data blocks having no data store (storage processor) d therein , for storing the physical block address of the free data block in the volatile memory location that corresponds to the target logical block address , and for periodically erasing all data blocks of the nonvolatile memory devices having flags which are set , whereby an erase cycle is not needed each time the external system writes to the storage device ;
wherein the used/free flags stored in the one or more nonvolatile memory devices which correlate to the physical block addresses of the plurality of nonvolatile data blocks are copied to the volatile memory locations during a power-up and a system reset .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US5603001A

Filed: 1995-05-05     Issued: 1997-02-11

Semiconductor disk system having a plurality of flash memories

(Original Assignee) Toshiba Corp     (Current Assignee) Toshiba Corp

Hiroshi Sukegawa, Yasunori Maki, Takashi Inagaki
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium (write operation) in response to requests from a computer system , including storing data (writing means) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US5603001A
CLAIM 6
. A system according to claim 4 , further comprising : writing means (storing data) for writing bad sector information indicating a bad sector designated by said host system into the redundancy area of one of said pages of said flash memory which corresponds to the bad sector .

US5603001A
CLAIM 14
. A semiconductor disk system comprising : a flash memory having a memory cell array which includes a plurality of blocks , each said block consisting of a plurality of pages , each said page including a data storage area and a redundancy area , and in which write count data constituted by an upper bit portion of write count data indicative of a write count of each said block is stored in a predetermined said block , and second write count data constituted by a lower bit portion of write count data corresponding to each said block is stored in the redundancy area of a predetermined said page of each said block , and a data register for holding data of one said page , said flash memory being set , in response to a command , in one of an erase operation mode by which stored contents are erased in units of said blocks , a write operation (solid state storage medium) mode by which data is written in said memory cell array in units of said pages , and a read operation mode by which data is read out from said memory cell array in units of said pages ;
a data buffer for storing write data transferred from a host system and read data read out from said flash memory ;
write count managing means for setting said flash memory in the read operation mode by issuing a read command , reading out the first write count data from said predetermined block , and managing the write count of each said block of said flash memory in accordance with the readout first write count data ;
updating means for setting said flash memory in the read operation mode by issuing a read command , reading out the second write count data from said predetermined page of a write target block designated by a write request , and updating a value of the readout second write count data ;
header table generating means for reading out data stored in a target page other than a write access target page of said write target block into said data buffer , and , on the basis of an address of the readout data in said data buffer and an address of the write data stored in said data buffer , generating a header table which holds address information indicating a storage position , in said data buffer , of each data constituting block data of one said block to be written into said write target block ;
erasing means for setting said flash memory in the erase operation mode by issuing an erase command , and erasing stored contents of said write target block ;
and write access means for reading out the block data in said units of said pages from said data buffer by referring to the address information of said header table , and transferring the readout data to said data register , thereby performing a write access to said flash memory , wherein said write count managing means includes updating means for updating a value of the first write count data corresponding to said write target block , if a carry occurs from the second write count data to the first write count data upon updating the second write count data .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface (read command) , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
US5603001A
CLAIM 14
. A semiconductor disk system comprising : a flash memory having a memory cell array which includes a plurality of blocks , each said block consisting of a plurality of pages , each said page including a data storage area and a redundancy area , and in which write count data constituted by an upper bit portion of write count data indicative of a write count of each said block is stored in a predetermined said block , and second write count data constituted by a lower bit portion of write count data corresponding to each said block is stored in the redundancy area of a predetermined said page of each said block , and a data register for holding data of one said page , said flash memory being set , in response to a command , in one of an erase operation mode by which stored contents are erased in units of said blocks , a write operation mode by which data is written in said memory cell array in units of said pages , and a read operation mode by which data is read out from said memory cell array in units of said pages ;
a data buffer for storing write data transferred from a host system and read data read out from said flash memory ;
write count managing means for setting said flash memory in the read operation mode by issuing a read command (PCI Express bus interface) , reading out the first write count data from said predetermined block , and managing the write count of each said block of said flash memory in accordance with the readout first write count data ;
updating means for setting said flash memory in the read operation mode by issuing a read command , reading out the second write count data from said predetermined page of a write target block designated by a write request , and updating a value of the readout second write count data ;
header table generating means for reading out data stored in a target page other than a write access target page of said write target block into said data buffer , and , on the basis of an address of the readout data in said data buffer and an address of the write data stored in said data buffer , generating a header table which holds address information indicating a storage position , in said data buffer , of each data constituting block data of one said block to be written into said write target block ;
erasing means for setting said flash memory in the erase operation mode by issuing an erase command , and erasing stored contents of said write target block ;
and write access means for reading out the block data in said units of said pages from said data buffer by referring to the address information of said header table , and transferring the readout data to said data register , thereby performing a write access to said flash memory , wherein said write count managing means includes updating means for updating a value of the first write count data corresponding to said write target block , if a carry occurs from the second write count data to the first write count data upon updating the second write count data .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (writing means) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
US5603001A
CLAIM 6
. A system according to claim 4 , further comprising : writing means (storing data) for writing bad sector information indicating a bad sector designated by said host system into the redundancy area of one of said pages of said flash memory which corresponds to the bad sector .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor (data indicative, data store) coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US5603001A
CLAIM 4
. A semiconductor disk system comprising : a flash memory having a memory cell array consisting of a plurality of pages each including a data storage area and a redundancy area , and a data register for holding data of said one said page , data transfer between said data register and said memory cell array being executed in units of pages ;
a data buffer for storing write data transferred from a host system and read data read out from said flash memory ;
error correction code generating means for performing , in response to a write request from said host system , a calculation for the write data store (storage processor) d in said data buffer in units of data strings each said corresponding to a size of the data storage area of each said page , thereby generating an error correction code for each data string ;
and write access means for adding a corresponding error correction code to each data string , in order that each data string and an error correction code corresponding to the data string are written into the data storage area and the redundancy area , respectively , of the same said page , and transferring the data string and the error correction code to said data register , thereby performing a write access to said flash memory .

US5603001A
CLAIM 30
. An access control method in a semiconductor disk system which comprises a flash memory having a memory cell array which includes a plurality of blocks , each said block consisting of a plurality of pages , each said page including a data storage area and a redundancy area , and in which first write count data constituted by an upper bit portion of write count data indicative (storage processor) of a write count of each said block is stored in a predetermined one of said blocks , and second write count data constituted by a lower bit portion of write count data corresponding to each said block is stored in the redundancy area of a predetermined page of said predetermined block , and a data register for holding data of one said page , said flash memory being set , in response to a command , in one of an erase operation mode by which stored contents are erased in units of said blocks , a write operation mode by which data is written in said memory cell array in units of said pages , and a read operation mode by which data is read out from said memory cell array in units of said pages , and a data buffer for storing write data transferred from a host system and read data read out from said flash memory , comprising the steps of : a) setting said flash memory in read operation mode by issuing a read command , reading out the first write count data from said predetermined block , and managing the write count of each said block of said flash memory in accordance with the readout first write count data ;
b) setting said flash memory in the read operation mode by issuing a read command , reading out the second write count data from a predetermined page of a write target block designated by a write request , and updating a value of the readout second write count data ;
c) reading out data stored in a target page other than a write access target page of said write target block into said data buffer , and , on the basis of an address of the readout data in said data buffer and an address of the write data stored in said data buffer , generating a header table which holds address information indicating a storage position , in said data buffer , of each data constituting block data of one of said blocks to be written into said write target block ;
d) setting said flash memory in the erase operation mode by issuing an erase command , and erasing stored contents of said write target block ;
and e) reading out the block data in units of said pages from said data buffer by referring to the address information of said header table , and transferring the read out data to said data register , thereby performing a write access to said flash memory , wherein the step a) includes the step of updating a value of the first write count data corresponding to said write target block , if a carry occurs from the second write count data to the first write count data upon updating the second write count data .

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (data indicative, data store) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
US5603001A
CLAIM 4
. A semiconductor disk system comprising : a flash memory having a memory cell array consisting of a plurality of pages each including a data storage area and a redundancy area , and a data register for holding data of said one said page , data transfer between said data register and said memory cell array being executed in units of pages ;
a data buffer for storing write data transferred from a host system and read data read out from said flash memory ;
error correction code generating means for performing , in response to a write request from said host system , a calculation for the write data store (storage processor) d in said data buffer in units of data strings each said corresponding to a size of the data storage area of each said page , thereby generating an error correction code for each data string ;
and write access means for adding a corresponding error correction code to each data string , in order that each data string and an error correction code corresponding to the data string are written into the data storage area and the redundancy area , respectively , of the same said page , and transferring the data string and the error correction code to said data register , thereby performing a write access to said flash memory .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request (read request) specifying one or more logical addresses included in the empty-block directive command , the storage processor (data indicative, data store) returns a predetermined data string .
US5603001A
CLAIM 4
. A semiconductor disk system comprising : a flash memory having a memory cell array consisting of a plurality of pages each including a data storage area and a redundancy area , and a data register for holding data of said one said page , data transfer between said data register and said memory cell array being executed in units of pages ;
a data buffer for storing write data transferred from a host system and read data read out from said flash memory ;
error correction code generating means for performing , in response to a write request from said host system , a calculation for the write data store (storage processor) d in said data buffer in units of data strings each said corresponding to a size of the data storage area of each said page , thereby generating an error correction code for each data string ;
and write access means for adding a corresponding error correction code to each data string , in order that each data string and an error correction code corresponding to the data string are written into the data storage area and the redundancy area , respectively , of the same said page , and transferring the data string and the error correction code to said data register , thereby performing a write access to said flash memory .

US5603001A
CLAIM 5
. A system according to claim 4 , further comprising : error correction code calculating means for performing a read access to said flash memory in response to a read request (read request) from said host system , calculating an error correction code for each said page to be read out , and executing error detection and correction for each data string of each said page .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US5701434A

Filed: 1995-03-16     Issued: 1997-12-23

Interleave memory controller with a common access queue

(Original Assignee) Hitachi Ltd     (Current Assignee) Hitachi Ltd

Takayuki Nakagawa
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations (said sequence) on the solid state storage medium in response to requests from a computer system , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US5701434A
CLAIM 13
. A computer system according to claim 12 , wherein said sequence (storage operations) assurance circuit reads the memory access requests from said random access queue separately for each of said plurality of banks and keeps the access sequence separately for each of said plurality of banks .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface (single access) , and a Fibre Channel interface .
US5701434A
CLAIM 1
. A memory control circuit comprising : means for receiving access requests entered from outside said memory control circuit and issued to an interleaved memory having a plurality of banks ;
a single access (internet SCSI interface) queue connected to said means and storing the access requests commonly for said plurality of banks ;
and means controlling said access queue for storing the access requests while waiting for said plurality of banks to be taken out of a wait state ;
an access sequencing circuit reading the access requests from said access queue and assuring access sequence of the access requests ;
a circuit for detecting that a first bank identified by a first access request in said means for receiving is idle ;
a circuit for detecting that said access queue contains no access request addressed to said first bank ;
and a bypass responsive to when said first bank is idle and when said access queue contains no access request addressed to said first bank , to transfer the first access request from said means for receiving to said first bank without passing the first access request through said access queue .

US9632727B2
CLAIM 8
. The system of claim 7 , further comprising means for providing a storage interface to accept requests to perform storage operations (said sequence) on the solid-state storage medium in reference to the logical blocks and to accept the message identifying the logical block that is not being used to reference data stored on the solid-state storage medium .
US5701434A
CLAIM 13
. A computer system according to claim 12 , wherein said sequence (storage operations) assurance circuit reads the memory access requests from said random access queue separately for each of said plurality of banks and keeps the access sequence separately for each of said plurality of banks .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US5535328A

Filed: 1995-02-23     Issued: 1996-07-09

Non-volatile memory system card with flash erasable sectors of EEprom cells including a mechanism for substituting defective cells

(Original Assignee) SanDisk Corp     (Current Assignee) SanDisk Technologies LLC

Eliyahou Harari, Robert D. Norman, Sanjay Mehrotra
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system (computer system) , including storing data (storing data, said memory) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data (storing data, said memory) pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US5535328A
CLAIM 1
. A memory card connectable to a computer system (computer system) , said memory (storing data, store data) card comprising : an array of non-volatile floating gate memory cells partitioned into a plurality of sectors that individually include a distinct group of said array of memory cells that are erasable together as a unit , the individual sectors including a user data portion and a spare portion of the group of memory cells , a memory controller for controlling operation of the memory cell array and interfacing the memory cell array with the computer system , means within said memory controller for identifying defective cells within the user data portion of individual ones of said plurality of sectors , and means including said memory controller and responsive to detection of a defective cell within the user data portion of one of said plurality of sectors for substituting therefore a corresponding redundant cell within the spare portion of said one of said plurality of sectors .

US5535328A
CLAIM 5
. A method of operating a computer system including a processor and a memory system , wherein the memory system includes an array of non-volatile floating gate memory cells partitioned into a plurality of sectors that individually include a distinct group of said array of memory cells that are erasable together as a unit , comprising : providing said memory array and a memory controller within a card that is removably connectable to the computer system , said controller being connectable to said processor for controlling operation of the array when the card is connected to the computer system , reserving a portion of the memory cells within the individual sectors as spare cells , remaining cells of the individual sectors being designated for storing data (storing data, store data) , enabling the controller to detect when a cell within the data portion of a sector becomes defective , causing the controller to store an address of such a detected defective cell , and thereafter causing the controller to substitute for the defective cell a redundant cell from the spare cells of the sector in which the defective cell is detected .

US9632727B2
CLAIM 2
. The apparatus of claim 1 , wherein the indexer assigns logical addresses to physical addresses by use of index entries , and wherein the indexer removes an index entry (memory array) corresponding to the identified logical address in response to the message .
US5535328A
CLAIM 5
. A method of operating a computer system including a processor and a memory system , wherein the memory system includes an array of non-volatile floating gate memory cells partitioned into a plurality of sectors that individually include a distinct group of said array of memory cells that are erasable together as a unit , comprising : providing said memory array (index entry) and a memory controller within a card that is removably connectable to the computer system , said controller being connectable to said processor for controlling operation of the array when the card is connected to the computer system , reserving a portion of the memory cells within the individual sectors as spare cells , remaining cells of the individual sectors being designated for storing data , enabling the controller to detect when a cell within the data portion of a sector becomes defective , causing the controller to store an address of such a detected defective cell , and thereafter causing the controller to substitute for the defective cell a redundant cell from the spare cells of the sector in which the defective cell is detected .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system (computer system) , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface (data port) , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
US5535328A
CLAIM 1
. A memory card connectable to a computer system (computer system) , said memory card comprising : an array of non-volatile floating gate memory cells partitioned into a plurality of sectors that individually include a distinct group of said array of memory cells that are erasable together as a unit , the individual sectors including a user data port (external SATA bus interface) ion and a spare portion of the group of memory cells , a memory controller for controlling operation of the memory cell array and interfacing the memory cell array with the computer system , means within said memory controller for identifying defective cells within the user data portion of individual ones of said plurality of sectors , and means including said memory controller and responsive to detection of a defective cell within the user data portion of one of said plurality of sectors for substituting therefore a corresponding redundant cell within the spare portion of said one of said plurality of sectors .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (storing data, said memory) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
US5535328A
CLAIM 1
. A memory card connectable to a computer system , said memory (storing data, store data) card comprising : an array of non-volatile floating gate memory cells partitioned into a plurality of sectors that individually include a distinct group of said array of memory cells that are erasable together as a unit , the individual sectors including a user data portion and a spare portion of the group of memory cells , a memory controller for controlling operation of the memory cell array and interfacing the memory cell array with the computer system , means within said memory controller for identifying defective cells within the user data portion of individual ones of said plurality of sectors , and means including said memory controller and responsive to detection of a defective cell within the user data portion of one of said plurality of sectors for substituting therefore a corresponding redundant cell within the spare portion of said one of said plurality of sectors .

US5535328A
CLAIM 5
. A method of operating a computer system including a processor and a memory system , wherein the memory system includes an array of non-volatile floating gate memory cells partitioned into a plurality of sectors that individually include a distinct group of said array of memory cells that are erasable together as a unit , comprising : providing said memory array and a memory controller within a card that is removably connectable to the computer system , said controller being connectable to said processor for controlling operation of the array when the card is connected to the computer system , reserving a portion of the memory cells within the individual sectors as spare cells , remaining cells of the individual sectors being designated for storing data (storing data, store data) , enabling the controller to detect when a cell within the data portion of a sector becomes defective , causing the controller to store an address of such a detected defective cell , and thereafter causing the controller to substitute for the defective cell a redundant cell from the spare cells of the sector in which the defective cell is detected .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor (data store) coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US5535328A
CLAIM 3
. The memory card of claim 1 , which additionally comprises means within said memory controller for storing and accessing error correction codes in the spare portions of the sectors which are related to data store (storage processor) d in the user data portions of the same sectors .

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (data store) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
US5535328A
CLAIM 3
. The memory card of claim 1 , which additionally comprises means within said memory controller for storing and accessing error correction codes in the spare portions of the sectors which are related to data store (storage processor) d in the user data portions of the same sectors .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor (data store) returns a predetermined data string .
US5535328A
CLAIM 3
. The memory card of claim 1 , which additionally comprises means within said memory controller for storing and accessing error correction codes in the spare portions of the sectors which are related to data store (storage processor) d in the user data portions of the same sectors .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US5566315A

Filed: 1994-12-30     Issued: 1996-10-15

Process of predicting and controlling the use of cache memory in a computer system

(Original Assignee) Oracle StorageTek     (Current Assignee) Oracle StorageTek

Michael S. Milillo, Patrick A. L. De Martine
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system (computer system) , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data (main memory) pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system (first frequency) , the message indicating that the identified logical address is erased .
US5566315A
CLAIM 1
. A process for controlling an amount of free space in a cache memory of a computer system (computer system) having a host computer and a main memory (store data) , comprising the steps of : determining a rate of allocations to the cache memory in response to I/O requests from the host computer , an allocation resulting from the performance of a read or write event in the cache memory in response to an I/O request from the host computer ;
calculating an allocation predictor related to the rate of allocations determined ;
setting a threshold of free space in the cache memory having a predetermined direct relationship to the allocation predictor ;
releasing cache space in the cache memory to change the amount of free space in the cache memory based on the threshold established ;
and performing the aforesaid steps of determining , calculating , setting and releasing at each of predetermined number of repetitive control intervals during continuous operation of the computer system .

US5566315A
CLAIM 4
. A process as defined in claim 3 further comprising the steps of : determining the allocation rate at a first frequency (host operating system) having allocation intervals ;
determining the blockage rate at a second frequency having blockage intervals ;
and establishing the second frequency as different than the first frequency .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system (computer system) , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
US5566315A
CLAIM 1
. A process for controlling an amount of free space in a cache memory of a computer system (computer system) having a host computer and a main memory , comprising the steps of : determining a rate of allocations to the cache memory in response to I/O requests from the host computer , an allocation resulting from the performance of a read or write event in the cache memory in response to an I/O request from the host computer ;
calculating an allocation predictor related to the rate of allocations determined ;
setting a threshold of free space in the cache memory having a predetermined direct relationship to the allocation predictor ;
releasing cache space in the cache memory to change the amount of free space in the cache memory based on the threshold established ;
and performing the aforesaid steps of determining , calculating , setting and releasing at each of predetermined number of repetitive control intervals during continuous operation of the computer system .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US5541886A

Filed: 1994-12-27     Issued: 1996-07-30

Method and apparatus for storing control information in multi-bit non-volatile memory arrays

(Original Assignee) Intel Corp     (Current Assignee) Intel Corp

Robert Hasbun
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state (read only memory) storage medium in response to requests from a computer system , including storing data (storing data) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data (read only memory) pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US5541886A
CLAIM 4
. The apparatus of claim 1 wherein the memory array includes flash electrically-erasable programmable read only memory (solid state, store data) cells .

US5541886A
CLAIM 5
. A memory array comprising : a plurality of nonvolatile memory cells arranged in separately erasable blocks , each block including an area for storing data (storing data) and another area for storing control information associated with the data , wherein the nonvolatile memory cells can store more than one bit per cell ;
and circuitry for accessing the blocks using logical addresses stored as a part of the control information , wherein the circuitry accesses the control information in a single-bit mode and the circuitry accesses the data in a selected one of a single-bit mode and a multi-bit mode .

US9632727B2
CLAIM 2
. The apparatus of claim 1 , wherein the indexer assigns logical addresses to physical addresses by use of index entries , and wherein the indexer removes an index entry (memory array) corresponding to the identified logical address in response to the message .
US5541886A
CLAIM 1
. An apparatus comprising : a memory array (index entry) comprising a plurality of nonvolatile memory cells , wherein each cell can store more than one bit of information ;
control circuitry for accessing the memory array in a selected one of a multi-bit mode and a single-bit mode , wherein the memory array stores data in one portion of the array and control information for the data in another portion of the array , wherein the control circuitry selects the single-bit mode when accessing the control information , wherein the control circuitry selects one of the single-bit mode and the multi-bit mode when accessing the data .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (storing data) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
US5541886A
CLAIM 5
. A memory array comprising : a plurality of nonvolatile memory cells arranged in separately erasable blocks , each block including an area for storing data (storing data) and another area for storing control information associated with the data , wherein the nonvolatile memory cells can store more than one bit per cell ;
and circuitry for accessing the blocks using logical addresses stored as a part of the control information , wherein the circuitry accesses the control information in a single-bit mode and the circuitry accesses the data in a selected one of a single-bit mode and a multi-bit mode .

US9632727B2
CLAIM 9
. The system of claim 7 , wherein unmapping the identified logical block comprises invalidating an entry of the logical-to-physical mappings , the entry indicating a mapping between the identified logical block and the particular storage block (given address) .
US5541886A
CLAIM 8
. A method of accessing a selected set of data from a plurality of sets of data stored in at least one block of memory , comprising the steps of : locating a logical address corresponding to a given address (particular storage block) , wherein the logical address is located in control information stored in one portion of the block of memory , the memory including a plurality of nonvolatile memory cells , the control information stored in a single-bit per cell mode within the one portion of the block of memory ;
accessing control information associated with the logical address in a single-bit per cell mode ;
accessing the selected set of data within the block in accordance with the control information associated with the logical address , wherein the selected set of data is accessed in a multi-bit per cell mode .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor (data store) coupled to the storage interface ;

a flash memory device (nonvolatile memory cells) coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US5541886A
CLAIM 1
. An apparatus comprising : a memory array comprising a plurality of nonvolatile memory cells (flash memory device) , wherein each cell can store more than one bit of information ;
control circuitry for accessing the memory array in a selected one of a multi-bit mode and a single-bit mode , wherein the memory array stores data in one portion of the array and control information for the data in another portion of the array , wherein the control circuitry selects the single-bit mode when accessing the control information , wherein the control circuitry selects one of the single-bit mode and the multi-bit mode when accessing the data .

US5541886A
CLAIM 8
. A method of accessing a selected set of data from a plurality of sets of data store (storage processor) d in at least one block of memory , comprising the steps of : locating a logical address corresponding to a given address , wherein the logical address is located in control information stored in one portion of the block of memory , the memory including a plurality of nonvolatile memory cells , the control information stored in a single-bit per cell mode within the one portion of the block of memory ;
accessing control information associated with the logical address in a single-bit per cell mode ;
accessing the selected set of data within the block in accordance with the control information associated with the logical address , wherein the selected set of data is accessed in a multi-bit per cell mode .

US9632727B2
CLAIM 13
. The system of claim 12 , wherein the logical-to-physical translation layer is stored in the flash memory device (nonvolatile memory cells) .
US5541886A
CLAIM 1
. An apparatus comprising : a memory array comprising a plurality of nonvolatile memory cells (flash memory device) , wherein each cell can store more than one bit of information ;
control circuitry for accessing the memory array in a selected one of a multi-bit mode and a single-bit mode , wherein the memory array stores data in one portion of the array and control information for the data in another portion of the array , wherein the control circuitry selects the single-bit mode when accessing the control information , wherein the control circuitry selects one of the single-bit mode and the multi-bit mode when accessing the data .

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (data store) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
US5541886A
CLAIM 8
. A method of accessing a selected set of data from a plurality of sets of data store (storage processor) d in at least one block of memory , comprising the steps of : locating a logical address corresponding to a given address , wherein the logical address is located in control information stored in one portion of the block of memory , the memory including a plurality of nonvolatile memory cells , the control information stored in a single-bit per cell mode within the one portion of the block of memory ;
accessing control information associated with the logical address in a single-bit per cell mode ;
accessing the selected set of data within the block in accordance with the control information associated with the logical address , wherein the selected set of data is accessed in a multi-bit per cell mode .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor (data store) returns a predetermined data string .
US5541886A
CLAIM 8
. A method of accessing a selected set of data from a plurality of sets of data store (storage processor) d in at least one block of memory , comprising the steps of : locating a logical address corresponding to a given address , wherein the logical address is located in control information stored in one portion of the block of memory , the memory including a plurality of nonvolatile memory cells , the control information stored in a single-bit per cell mode within the one portion of the block of memory ;
accessing control information associated with the logical address in a single-bit per cell mode ;
accessing the selected set of data within the block in accordance with the control information associated with the logical address , wherein the selected set of data is accessed in a multi-bit per cell mode .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US5586291A

Filed: 1994-12-23     Issued: 1996-12-17

Disk controller with volatile and non-volatile cache memories

(Original Assignee) EMC Corp     (Current Assignee) SWAN CHARLES A ; EMC Corp

Jeffrey M. Lasker, James M. McGillis
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium (write operation, one disk) (write operation, one disk) in response to requests from a computer system , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US5586291A
CLAIM 1
. A disk controller coupled between a host computer and a disk drive , the disk controller comprising : a controller microprocessor ;
a cache memory including : at least one volatile memory module ;
and at least one non-volatile memory module ;
a cache memory control circuit coupled to said at least one non-volatile memory module and said at least one volatile memory module wherein in response to a write command received from the host computer , said controller microprocessor allocates a predetermined number of memory blocks in each of said at least one volatile and said at least one non-volatile memory modules for storage of write-data and upon completion of a write operation (solid state storage medium, state storage medium, storage client, state storage system) to said at least one non-volatile memory modules , said cache memory control circuit transfers the write-data from said at least one non-volatile memory module to said at least one volatile memory module .

US5586291A
CLAIM 9
. A disk storage subsystem comprising : at least one disk (solid state storage medium, state storage medium, storage client, state storage system) drive ;
and a disk controller coupled to said disk drive and adapted to couple to a host computer , said disk controller comprising : a controller microprocessor ;
a cache memory including : a plurality of volatile memory modules which form a read-cache ;
a plurality of non-volatile memory modules which form a write-cache ;
and a cache memory control circuit coupled to said non-volatile memory module and said volatile memory module wherein in response a write command received from the host computer , said controller microprocessor allocates a predetermined number of memory blocks in each of said volatile and said non-volatile memory modules for storage of write data and upon completion of a write operation to said non-volatile memory modules , said cache memory control circuit transfers the write data from said non-volatile memory module to said volatile memory module .

US9632727B2
CLAIM 5
. The apparatus of claim 1 , further comprising a garbage collector (memory management) configured to designate that the physical address previously assigned to the identified logical address comprises data suitable for removal from the solid-state storage medium in response to the message .
US5586291A
CLAIM 16
. A method of transferring data to be written from a host computer to at least one disk drive within a disk storage subsystem including a host interface circuit , a disk interface circuit , a controller microprocessor , a cache memory , a cache memory management (garbage collector) circuit and the at least one disk drive , the method comprising the steps of : receiving in the disk storage subsystem a host write-to-disk command ;
allocating a predetermined number of memory blocks in a non-volatile memory module of the cache memory ;
allocating a predetermined number of memory blocks in a volatile memory module of the cache memory ;
storing the data to be written to the at least one disk drive in the allocated memory blocks of the non-volatile memory module of the cache memory ;
and initiating a DMA transfer by the cache memory management circuit , to copy the data to be written to the at least one disk drive from the allocated memory blocks of the non-volatile memory module to the allocated memory blocks of the volatile memory module of the cache memory .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology (represents a) Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA (DMA transfer) bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
US5586291A
CLAIM 3
. The disk controller of claim 2 wherein said cache memory control circuit transfers the write data from said at least one non-volatile memory module to said at least one volatile memory module with a DMA transfer (external SATA, external SATA bus interface) .

US5586291A
CLAIM 4
. The disk controller of claim 3 wherein the list of available memory blocks is provided from a plurality of linked domains wherein each of said plurality of linked domains represents a (Advanced Technology) predetermined number of memory blocks and wherein each of said plurality of domains has associated therewith a valid field and an in-operation field which indicate the status of each memory block in said domain .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client (write operation, one disk) that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
US5586291A
CLAIM 1
. A disk controller coupled between a host computer and a disk drive , the disk controller comprising : a controller microprocessor ;
a cache memory including : at least one volatile memory module ;
and at least one non-volatile memory module ;
a cache memory control circuit coupled to said at least one non-volatile memory module and said at least one volatile memory module wherein in response to a write command received from the host computer , said controller microprocessor allocates a predetermined number of memory blocks in each of said at least one volatile and said at least one non-volatile memory modules for storage of write-data and upon completion of a write operation (solid state storage medium, state storage medium, storage client, state storage system) to said at least one non-volatile memory modules , said cache memory control circuit transfers the write-data from said at least one non-volatile memory module to said at least one volatile memory module .

US5586291A
CLAIM 9
. A disk storage subsystem comprising : at least one disk (solid state storage medium, state storage medium, storage client, state storage system) drive ;
and a disk controller coupled to said disk drive and adapted to couple to a host computer , said disk controller comprising : a controller microprocessor ;
a cache memory including : a plurality of volatile memory modules which form a read-cache ;
a plurality of non-volatile memory modules which form a write-cache ;
and a cache memory control circuit coupled to said non-volatile memory module and said volatile memory module wherein in response a write command received from the host computer , said controller microprocessor allocates a predetermined number of memory blocks in each of said volatile and said non-volatile memory modules for storage of write data and upon completion of a write operation to said non-volatile memory modules , said cache memory control circuit transfers the write data from said non-volatile memory module to said volatile memory module .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client (write operation, one disk) ;

a storage processor (data store) coupled to the storage interface ;

a flash memory device (storage subsystem) coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US5586291A
CLAIM 1
. A disk controller coupled between a host computer and a disk drive , the disk controller comprising : a controller microprocessor ;
a cache memory including : at least one volatile memory module ;
and at least one non-volatile memory module ;
a cache memory control circuit coupled to said at least one non-volatile memory module and said at least one volatile memory module wherein in response to a write command received from the host computer , said controller microprocessor allocates a predetermined number of memory blocks in each of said at least one volatile and said at least one non-volatile memory modules for storage of write-data and upon completion of a write operation (solid state storage medium, state storage medium, storage client, state storage system) to said at least one non-volatile memory modules , said cache memory control circuit transfers the write-data from said at least one non-volatile memory module to said at least one volatile memory module .

US5586291A
CLAIM 9
. A disk storage subsystem (flash memory device) comprising : at least one disk (solid state storage medium, state storage medium, storage client, state storage system) drive ;
and a disk controller coupled to said disk drive and adapted to couple to a host computer , said disk controller comprising : a controller microprocessor ;
a cache memory including : a plurality of volatile memory modules which form a read-cache ;
a plurality of non-volatile memory modules which form a write-cache ;
and a cache memory control circuit coupled to said non-volatile memory module and said volatile memory module wherein in response a write command received from the host computer , said controller microprocessor allocates a predetermined number of memory blocks in each of said volatile and said non-volatile memory modules for storage of write data and upon completion of a write operation to said non-volatile memory modules , said cache memory control circuit transfers the write data from said non-volatile memory module to said volatile memory module .

US5586291A
CLAIM 21
. A method of controlling a cache memory of a disk storage subsystem coupled to a host computer , the method comprising the steps of : establishing a list of available memory blocks in a write-cache ;
in response to a write operation initiated by a host computer , allocating from the list of available memory blocks a predetermined number of memory blocks of the write-cache ;
allocating a like predetermined number of blocks in a read-cache ;
receiving write-data from the host computer ;
storing the write-data in the allocated memory blocks of the write-cache ;
indicating to the host computer that the write-data store (storage processor) d in the read-cache is valid and available for use ;
and transferring the write-data from the allocated memory blocks of the write-cache to the allocated memory blocks of the read-cache .

US9632727B2
CLAIM 13
. The system of claim 12 , wherein the logical-to-physical translation layer is stored in the flash memory device (storage subsystem) .
US5586291A
CLAIM 9
. A disk storage subsystem (flash memory device) comprising : at least one disk drive ;
and a disk controller coupled to said disk drive and adapted to couple to a host computer , said disk controller comprising : a controller microprocessor ;
a cache memory including : a plurality of volatile memory modules which form a read-cache ;
a plurality of non-volatile memory modules which form a write-cache ;
and a cache memory control circuit coupled to said non-volatile memory module and said volatile memory module wherein in response a write command received from the host computer , said controller microprocessor allocates a predetermined number of memory blocks in each of said volatile and said non-volatile memory modules for storage of write data and upon completion of a write operation to said non-volatile memory modules , said cache memory control circuit transfers the write data from said non-volatile memory module to said volatile memory module .

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (data store) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
US5586291A
CLAIM 21
. A method of controlling a cache memory of a disk storage subsystem coupled to a host computer , the method comprising the steps of : establishing a list of available memory blocks in a write-cache ;
in response to a write operation initiated by a host computer , allocating from the list of available memory blocks a predetermined number of memory blocks of the write-cache ;
allocating a like predetermined number of blocks in a read-cache ;
receiving write-data from the host computer ;
storing the write-data in the allocated memory blocks of the write-cache ;
indicating to the host computer that the write-data store (storage processor) d in the read-cache is valid and available for use ;
and transferring the write-data from the allocated memory blocks of the write-cache to the allocated memory blocks of the read-cache .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor (data store) returns a predetermined data string .
US5586291A
CLAIM 21
. A method of controlling a cache memory of a disk storage subsystem coupled to a host computer , the method comprising the steps of : establishing a list of available memory blocks in a write-cache ;
in response to a write operation initiated by a host computer , allocating from the list of available memory blocks a predetermined number of memory blocks of the write-cache ;
allocating a like predetermined number of blocks in a read-cache ;
receiving write-data from the host computer ;
storing the write-data in the allocated memory blocks of the write-cache ;
indicating to the host computer that the write-data store (storage processor) d in the read-cache is valid and available for use ;
and transferring the write-data from the allocated memory blocks of the write-cache to the allocated memory blocks of the read-cache .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
JPH086854A

Filed: 1994-12-21     Issued: 1996-01-12

アウトボードファイルキャッシュ外部処理コンプレックス

(Original Assignee) Unisys Corp; ユニシス コーポレイシヨン     

T Price Felis, F Torgerson James, L Byers Larry, ジェイムズ・エフ・トルガーソン, フェリス・ティー・プライス, ラリー・エル・バイヤーズ
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller (制御信号) configured to implement storage operations on the solid state storage medium in response to requests from a computer system , including storing data (タイミング) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
JPH086854A
CLAIM 6
【請求項6】 前記インデックスプロセッサが、 各々がマイクロプロセッサおよびローカル記憶装置を有 する第1および第2のマイクロシーケンサ装置と、 実行予定の命令を記憶するための制御記憶装置とを含 み、前記制御記憶装置が前記第1および第2のマイクロ シーケンサ装置に結合して前記制御記憶装置に記憶され た同じ命令を前記第1および第2のマイクロシーケンサ 装置の両方に与え、さらに前記第1および第2のマイク ロシーケンサ装置に結合されて前記双方向バス構成から の制御信号 (state storage controller, storage controller) を受ける入力回路と、 前記双方向バス構成に結合された前記第1のマイクロシ ーケンサ装置からの出力回路と、 前記第2のマイクロシーケンサ装置を前記第1のマイク ロシーケンサ装置に結合して、前記第2のマイクロシー ケンサ装置により行われた命令実行の結果を前記第1の マイクロシーケンサ装置に送る相互結合回路とを含み、 それにより前記命令実行の前記結果を比較することによ って動作のエラーチェックが行なわれ得る、請求項1に 記載のアウトボードファイルキャッシュ外部処理コンプ レックス。

JPH086854A
CLAIM 27
【請求項27】 前記クロック分配手段が、前記双方向 バス手段の第1の部分、前記冗長不揮発性ファイルキャ ッシュ記憶手段の第1の部分、前記ファイルキャッシュ 記憶インタフェース手段の第1の部分、前記インデック スプロセッサ手段の第1の部分、および前記ホストイン タフェースアダプタ手段の第1の部分に前記クロック信 号を与えて、これらの動作のタイミング (storing data) をとるように構 成された前記冗長発振器手段および制御回路手段の第1 の組と、前記双方向バス手段の第2の部分、前記冗長不 揮発性キャッシュ記憶手段、ファイルキャッシュ記憶イ ンタフェース手段、インデックスプロセッサ手段、およ びホストインタフェースアダプタ手段にクロック信号を 与えて、これらの動作のタイミングを別々にとるように 構成された前記冗長発振器手段と制御回路手段の第2の 組と、 冗長発振器手段および制御回路手段の前記第1および第 2の組により与えられる前記クロック信号を同期させる ための同期手段とを含む、請求項26に記載のアウトボ ードファイルキャッシュシステム。

US9632727B2
CLAIM 3
. The apparatus of claim 1 , wherein the indexer assigns logical addresses to physical addresses by use of index metadata maintained in a memory of the storage controller (制御信号) .
JPH086854A
CLAIM 6
【請求項6】 前記インデックスプロセッサが、 各々がマイクロプロセッサおよびローカル記憶装置を有 する第1および第2のマイクロシーケンサ装置と、 実行予定の命令を記憶するための制御記憶装置とを含 み、前記制御記憶装置が前記第1および第2のマイクロ シーケンサ装置に結合して前記制御記憶装置に記憶され た同じ命令を前記第1および第2のマイクロシーケンサ 装置の両方に与え、さらに前記第1および第2のマイク ロシーケンサ装置に結合されて前記双方向バス構成から の制御信号 (state storage controller, storage controller) を受ける入力回路と、 前記双方向バス構成に結合された前記第1のマイクロシ ーケンサ装置からの出力回路と、 前記第2のマイクロシーケンサ装置を前記第1のマイク ロシーケンサ装置に結合して、前記第2のマイクロシー ケンサ装置により行われた命令実行の結果を前記第1の マイクロシーケンサ装置に送る相互結合回路とを含み、 それにより前記命令実行の前記結果を比較することによ って動作のエラーチェックが行なわれ得る、請求項1に 記載のアウトボードファイルキャッシュ外部処理コンプ レックス。

US9632727B2
CLAIM 4
. The apparatus of claim 1 , wherein the indexer comprises firmware of the solid-state storage controller (制御信号) .
JPH086854A
CLAIM 6
【請求項6】 前記インデックスプロセッサが、 各々がマイクロプロセッサおよびローカル記憶装置を有 する第1および第2のマイクロシーケンサ装置と、 実行予定の命令を記憶するための制御記憶装置とを含 み、前記制御記憶装置が前記第1および第2のマイクロ シーケンサ装置に結合して前記制御記憶装置に記憶され た同じ命令を前記第1および第2のマイクロシーケンサ 装置の両方に与え、さらに前記第1および第2のマイク ロシーケンサ装置に結合されて前記双方向バス構成から の制御信号 (state storage controller, storage controller) を受ける入力回路と、 前記双方向バス構成に結合された前記第1のマイクロシ ーケンサ装置からの出力回路と、 前記第2のマイクロシーケンサ装置を前記第1のマイク ロシーケンサ装置に結合して、前記第2のマイクロシー ケンサ装置により行われた命令実行の結果を前記第1の マイクロシーケンサ装置に送る相互結合回路とを含み、 それにより前記命令実行の前記結果を比較することによ って動作のエラーチェックが行なわれ得る、請求項1に 記載のアウトボードファイルキャッシュ外部処理コンプ レックス。

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller (制御信号) comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
JPH086854A
CLAIM 6
【請求項6】 前記インデックスプロセッサが、 各々がマイクロプロセッサおよびローカル記憶装置を有 する第1および第2のマイクロシーケンサ装置と、 実行予定の命令を記憶するための制御記憶装置とを含 み、前記制御記憶装置が前記第1および第2のマイクロ シーケンサ装置に結合して前記制御記憶装置に記憶され た同じ命令を前記第1および第2のマイクロシーケンサ 装置の両方に与え、さらに前記第1および第2のマイク ロシーケンサ装置に結合されて前記双方向バス構成から の制御信号 (state storage controller, storage controller) を受ける入力回路と、 前記双方向バス構成に結合された前記第1のマイクロシ ーケンサ装置からの出力回路と、 前記第2のマイクロシーケンサ装置を前記第1のマイク ロシーケンサ装置に結合して、前記第2のマイクロシー ケンサ装置により行われた命令実行の結果を前記第1の マイクロシーケンサ装置に送る相互結合回路とを含み、 それにより前記命令実行の前記結果を比較することによ って動作のエラーチェックが行なわれ得る、請求項1に 記載のアウトボードファイルキャッシュ外部処理コンプ レックス。

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (タイミング) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
JPH086854A
CLAIM 27
【請求項27】 前記クロック分配手段が、前記双方向 バス手段の第1の部分、前記冗長不揮発性ファイルキャ ッシュ記憶手段の第1の部分、前記ファイルキャッシュ 記憶インタフェース手段の第1の部分、前記インデック スプロセッサ手段の第1の部分、および前記ホストイン タフェースアダプタ手段の第1の部分に前記クロック信 号を与えて、これらの動作のタイミング (storing data) をとるように構 成された前記冗長発振器手段および制御回路手段の第1 の組と、前記双方向バス手段の第2の部分、前記冗長不 揮発性キャッシュ記憶手段、ファイルキャッシュ記憶イ ンタフェース手段、インデックスプロセッサ手段、およ びホストインタフェースアダプタ手段にクロック信号を 与えて、これらの動作のタイミングを別々にとるように 構成された前記冗長発振器手段と制御回路手段の第2の 組と、 冗長発振器手段および制御回路手段の前記第1および第 2の組により与えられる前記クロック信号を同期させる ための同期手段とを含む、請求項26に記載のアウトボ ードファイルキャッシュシステム。

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor (メモリ) coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
JPH086854A
CLAIM 1
【請求項1】 ファイルデータ信号を処理するためのホ ストデータ処理システムとともに使用するためのアウト ボードファイルキャッシュ外部処理コンプレックスであ って、 前記ホストデータ処理システムが命令プロセッサ、記憶 コントローラ、ファイルを記憶するためのファイル大容 量記憶装置、前記記憶コントローラに結合された主動作 メモリ (storage processor) 、前記ホストデータ処理システムとの間のファイ ルデータ信号の読出および書込を制御しかつ前記命令プ ロセッサと前記主動作メモリとに結合されたデータムー バシステム、および前記データムーバに結合された伝送 リンクとを有し、 前記アウトボードファイルキャッシュ外部処理コンプレ ックスは、 双方向バス構成と、 ホスト結合端子が前記伝送リンクに結合されて、前記ホ ストデータ処理システムからのファイルデータ信号およ びコマンド信号を受けかつ前記ホストデータ処理システ ムへファイルデータ信号およびコマンド信号を伝送し、 かつバス結合端子が前記双方向バス構成に結合されたホ ストインタフェースアダプタと、 前記双方向バス構成に結合されて、前記双方向バス構成 上の前記ファイルデータ信号およびコマンド信号の伝送 を制御するインデックスプロセッサと、 前記ファイルデータ信号を選択的にキャッシュしかつ前 記データファイル信号を選択的に読出すようになってい るアドレス可能な不揮発性記憶装置と、 前記アドレス可能な不揮発性記憶装置および前記双方向 バス構成に結合されて、前記コマンド信号に応答して前 記ファイルデータ信号上の前記キャッシュ動作および前 記読出動作を制御する記憶インタフェース制御回路とを 含み、 それによってアウトボードファイルキャッシングおよび 制御が前記ホストデータ処理システムに密接に結合され かつ前記ホストデータ処理システムにより行なわれるフ ァイルデータ処理および関連の制御機能と並行して行な われる、アウトボードファイルキャッシュ外部処理コン プレックス。

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (メモリ) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
JPH086854A
CLAIM 1
【請求項1】 ファイルデータ信号を処理するためのホ ストデータ処理システムとともに使用するためのアウト ボードファイルキャッシュ外部処理コンプレックスであ って、 前記ホストデータ処理システムが命令プロセッサ、記憶 コントローラ、ファイルを記憶するためのファイル大容 量記憶装置、前記記憶コントローラに結合された主動作 メモリ (storage processor) 、前記ホストデータ処理システムとの間のファイ ルデータ信号の読出および書込を制御しかつ前記命令プ ロセッサと前記主動作メモリとに結合されたデータムー バシステム、および前記データムーバに結合された伝送 リンクとを有し、 前記アウトボードファイルキャッシュ外部処理コンプレ ックスは、 双方向バス構成と、 ホスト結合端子が前記伝送リンクに結合されて、前記ホ ストデータ処理システムからのファイルデータ信号およ びコマンド信号を受けかつ前記ホストデータ処理システ ムへファイルデータ信号およびコマンド信号を伝送し、 かつバス結合端子が前記双方向バス構成に結合されたホ ストインタフェースアダプタと、 前記双方向バス構成に結合されて、前記双方向バス構成 上の前記ファイルデータ信号およびコマンド信号の伝送 を制御するインデックスプロセッサと、 前記ファイルデータ信号を選択的にキャッシュしかつ前 記データファイル信号を選択的に読出すようになってい るアドレス可能な不揮発性記憶装置と、 前記アドレス可能な不揮発性記憶装置および前記双方向 バス構成に結合されて、前記コマンド信号に応答して前 記ファイルデータ信号上の前記キャッシュ動作および前 記読出動作を制御する記憶インタフェース制御回路とを 含み、 それによってアウトボードファイルキャッシングおよび 制御が前記ホストデータ処理システムに密接に結合され かつ前記ホストデータ処理システムにより行なわれるフ ァイルデータ処理および関連の制御機能と並行して行な われる、アウトボードファイルキャッシュ外部処理コン プレックス。

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor (メモリ) returns a predetermined data string .
JPH086854A
CLAIM 1
【請求項1】 ファイルデータ信号を処理するためのホ ストデータ処理システムとともに使用するためのアウト ボードファイルキャッシュ外部処理コンプレックスであ って、 前記ホストデータ処理システムが命令プロセッサ、記憶 コントローラ、ファイルを記憶するためのファイル大容 量記憶装置、前記記憶コントローラに結合された主動作 メモリ (storage processor) 、前記ホストデータ処理システムとの間のファイ ルデータ信号の読出および書込を制御しかつ前記命令プ ロセッサと前記主動作メモリとに結合されたデータムー バシステム、および前記データムーバに結合された伝送 リンクとを有し、 前記アウトボードファイルキャッシュ外部処理コンプレ ックスは、 双方向バス構成と、 ホスト結合端子が前記伝送リンクに結合されて、前記ホ ストデータ処理システムからのファイルデータ信号およ びコマンド信号を受けかつ前記ホストデータ処理システ ムへファイルデータ信号およびコマンド信号を伝送し、 かつバス結合端子が前記双方向バス構成に結合されたホ ストインタフェースアダプタと、 前記双方向バス構成に結合されて、前記双方向バス構成 上の前記ファイルデータ信号およびコマンド信号の伝送 を制御するインデックスプロセッサと、 前記ファイルデータ信号を選択的にキャッシュしかつ前 記データファイル信号を選択的に読出すようになってい るアドレス可能な不揮発性記憶装置と、 前記アドレス可能な不揮発性記憶装置および前記双方向 バス構成に結合されて、前記コマンド信号に応答して前 記ファイルデータ信号上の前記キャッシュ動作および前 記読出動作を制御する記憶インタフェース制御回路とを 含み、 それによってアウトボードファイルキャッシングおよび 制御が前記ホストデータ処理システムに密接に結合され かつ前記ホストデータ処理システムにより行なわれるフ ァイルデータ処理および関連の制御機能と並行して行な われる、アウトボードファイルキャッシュ外部処理コン プレックス。




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
JPH08153014A

Filed: 1994-11-30     Issued: 1996-06-11

クライアントサーバシステム

(Original Assignee) Hitachi Ltd; 株式会社日立製作所     

Norihiro Gotou, Takahisa Miyamoto, Shuji Ono, Riichi Yasue, 修司 大野, 利一 安江, 貴久 宮本, 法宏 後藤
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system (行うこと) , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
JPH08153014A
CLAIM 1
【請求項1】 サービス処理中のサーバマシンに障害が 発生したとき、同等のサービスを提供可能な他のサーバ マシンに当該サービス処理を代替させるクライアントサ ーバシステムにおいて、 各々のサーバマシンに属するハードディスク装置(HD D)よりも高速な入出力アクセスが可能でバッテリバッ クアップ機能を有するソリッド・ステート・ディスク装 置(SSD)を具備し、 サーバマシンは前記HDDから前記SSDに複写された ファイルシステムを用いてサービス処理を行うこと (computer system) を特 徴とするクライアントサーバシステム。

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface (入出力インタフェース) configured to communicatively couple the solid-state storage controller to the computer system (行うこと) , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
JPH08153014A
CLAIM 1
【請求項1】 サービス処理中のサーバマシンに障害が 発生したとき、同等のサービスを提供可能な他のサーバ マシンに当該サービス処理を代替させるクライアントサ ーバシステムにおいて、 各々のサーバマシンに属するハードディスク装置(HD D)よりも高速な入出力アクセスが可能でバッテリバッ クアップ機能を有するソリッド・ステート・ディスク装 置(SSD)を具備し、 サーバマシンは前記HDDから前記SSDに複写された ファイルシステムを用いてサービス処理を行うこと (computer system) を特 徴とするクライアントサーバシステム。

JPH08153014A
CLAIM 3
【請求項3】 前記SSDに対するデータの入出力は、 前記共用入出力インタフェース (bus interface, storage interface, state storage system) を介して接続された各々 のサーバマシンとの間でやり取りされる入出力要求フレ ームおよび入出力応答フレームに基づいて一括的に行わ れることを特徴とする請求項1または2記載のクライア ントサーバシステム。

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client (サーバシステム) that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
JPH08153014A
CLAIM 1
【請求項1】 サービス処理中のサーバマシンに障害が 発生したとき、同等のサービスを提供可能な他のサーバ マシンに当該サービス処理を代替させるクライアントサ ーバシステムにおいて、 各々のサーバマシンに属するハードディスク装置(HD D)よりも高速な入出力アクセスが可能でバッテリバッ クアップ機能を有するソリッド・ステート・ディスク装 置(SSD)を具備し、 サーバマシンは前記HDDから前記SSDに複写された ファイルシステムを用いてサービス処理を行うことを特 徴とするクライアントサーバシステム (storage client)

US9632727B2
CLAIM 8
. The system of claim 7 , further comprising means for providing a storage interface (入出力インタフェース) to accept requests to perform storage operations on the solid-state storage medium in reference to the logical blocks and to accept the message identifying the logical block that is not being used to reference data stored on the solid-state storage medium .
JPH08153014A
CLAIM 3
【請求項3】 前記SSDに対するデータの入出力は、 前記共用入出力インタフェース (bus interface, storage interface, state storage system) を介して接続された各々 のサーバマシンとの間でやり取りされる入出力要求フレ ームおよび入出力応答フレームに基づいて一括的に行わ れることを特徴とする請求項1または2記載のクライア ントサーバシステム。

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface (入出力インタフェース) configured to communicate with a storage client (サーバシステム) ;

a storage processor (メモリ) coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
JPH08153014A
CLAIM 1
【請求項1】 サービス処理中のサーバマシンに障害が 発生したとき、同等のサービスを提供可能な他のサーバ マシンに当該サービス処理を代替させるクライアントサ ーバシステムにおいて、 各々のサーバマシンに属するハードディスク装置(HD D)よりも高速な入出力アクセスが可能でバッテリバッ クアップ機能を有するソリッド・ステート・ディスク装 置(SSD)を具備し、 サーバマシンは前記HDDから前記SSDに複写された ファイルシステムを用いてサービス処理を行うことを特 徴とするクライアントサーバシステム (storage client)

JPH08153014A
CLAIM 2
【請求項2】 前記SSDは、キャッシュメモリ (storage processor) を用い ずに直接的にデータの入出力が行われる共用入出力イン タフェースを介して各々のサーバマシン間で共用される ことを特徴とする請求項1記載のクライアントサーバシ ステム。

JPH08153014A
CLAIM 3
【請求項3】 前記SSDに対するデータの入出力は、 前記共用入出力インタフェース (bus interface, storage interface, state storage system) を介して接続された各々 のサーバマシンとの間でやり取りされる入出力要求フレ ームおよび入出力応答フレームに基づいて一括的に行わ れることを特徴とする請求項1または2記載のクライア ントサーバシステム。

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (メモリ) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
JPH08153014A
CLAIM 2
【請求項2】 前記SSDは、キャッシュメモリ (storage processor) を用い ずに直接的にデータの入出力が行われる共用入出力イン タフェースを介して各々のサーバマシン間で共用される ことを特徴とする請求項1記載のクライアントサーバシ ステム。

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor (メモリ) returns a predetermined data string .
JPH08153014A
CLAIM 2
【請求項2】 前記SSDは、キャッシュメモリ (storage processor) を用い ずに直接的にデータの入出力が行われる共用入出力イン タフェースを介して各々のサーバマシン間で共用される ことを特徴とする請求項1記載のクライアントサーバシ ステム。




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US6002411A

Filed: 1994-11-16     Issued: 1999-12-14

Integrated video and memory controller with data processing and graphical processing capabilities

(Original Assignee) Interactive Silicon Inc     (Current Assignee) Intellectual Ventures I LLC

Thomas Anthony Dye
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller (control unit) configured to implement storage operations on the solid state storage medium in response to requests from a computer system (bus interface) , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US6002411A
CLAIM 10
. The computer system of claim 1 , wherein said computer system includes a bus coupled between said CPU and said memory controller ;
wherein said memory controller comprises : a bus interface (computer system, bus interface) coupled to said bus ;
a graphics engine coupled to said bus interface ;
one or more memory control unit (state storage controller, storage controller) s coupled to said graphics engine and also coupled to said system memory ;
a window assembler coupled to said one or more memory control units ;
a display storage buffer coupled to said video assembly unit for storing video data ;
and one or more video output ports coupled to said window assembler for transferring said video data to said display device .

US9632727B2
CLAIM 3
. The apparatus of claim 1 , wherein the indexer assigns logical addresses to physical addresses by use of index metadata maintained in a memory of the storage controller (control unit) .
US6002411A
CLAIM 10
. The computer system of claim 1 , wherein said computer system includes a bus coupled between said CPU and said memory controller ;
wherein said memory controller comprises : a bus interface coupled to said bus ;
a graphics engine coupled to said bus interface ;
one or more memory control unit (state storage controller, storage controller) s coupled to said graphics engine and also coupled to said system memory ;
a window assembler coupled to said one or more memory control units ;
a display storage buffer coupled to said video assembly unit for storing video data ;
and one or more video output ports coupled to said window assembler for transferring said video data to said display device .

US9632727B2
CLAIM 4
. The apparatus of claim 1 , wherein the indexer comprises firmware of the solid-state storage controller (control unit) .
US6002411A
CLAIM 10
. The computer system of claim 1 , wherein said computer system includes a bus coupled between said CPU and said memory controller ;
wherein said memory controller comprises : a bus interface coupled to said bus ;
a graphics engine coupled to said bus interface ;
one or more memory control unit (state storage controller, storage controller) s coupled to said graphics engine and also coupled to said system memory ;
a window assembler coupled to said one or more memory control units ;
a display storage buffer coupled to said video assembly unit for storing video data ;
and one or more video output ports coupled to said window assembler for transferring said video data to said display device .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller (control unit) comprises a bus interface (bus interface) configured to communicatively couple the solid-state storage controller to the computer system (bus interface) , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
US6002411A
CLAIM 10
. The computer system of claim 1 , wherein said computer system includes a bus coupled between said CPU and said memory controller ;
wherein said memory controller comprises : a bus interface (computer system, bus interface) coupled to said bus ;
a graphics engine coupled to said bus interface ;
one or more memory control unit (state storage controller, storage controller) s coupled to said graphics engine and also coupled to said system memory ;
a window assembler coupled to said one or more memory control units ;
a display storage buffer coupled to said video assembly unit for storing video data ;
and one or more video output ports (PCI Express bus interface) coupled to said window assembler for transferring said video data to said display device .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor coupled to the storage interface ;

a flash memory device (storage subsystem) coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US6002411A
CLAIM 14
. The computer system of claim 1 , further comprising : a non-volatile storage subsystem (flash memory device) coupled to said memory controller , wherein said memory controller transfers data between said non-volatile storage subsystem and said system memory .

US9632727B2
CLAIM 13
. The system of claim 12 , wherein the logical-to-physical translation layer is stored in the flash memory device (storage subsystem) .
US6002411A
CLAIM 14
. The computer system of claim 1 , further comprising : a non-volatile storage subsystem (flash memory device) coupled to said memory controller , wherein said memory controller transfers data between said non-volatile storage subsystem and said system memory .

US9632727B2
CLAIM 16
. The system of claim 15 , wherein data bits of the predetermined data string have a uniform logic (non-volatile storage) level .
US6002411A
CLAIM 14
. The computer system of claim 1 , further comprising : a non-volatile storage (uniform logic) subsystem coupled to said memory controller , wherein said memory controller transfers data between said non-volatile storage subsystem and said system memory .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US5504882A

Filed: 1994-06-20     Issued: 1996-04-02

Fault tolerant data storage subsystem employing hierarchically arranged controllers

(Original Assignee) International Business Machines Corp     (Current Assignee) International Business Machines Corp

Philip K. Chai, Chan Y. Ng, John R. Paveza, Lloyd R. Shipman, Jr., Christ J. Xydes
US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface (input ports, output ports, data input) configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface (input ports, output ports, data input) , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA (host processor) bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
US5504882A
CLAIM 1
. A fault tolerant data storage subsystem , said data storage subsystem comprising : a plurality of storage device controllers adapted to emulate a storage device , each storage device controller having a cache memory which includes multiple data input ports (external SATA bus interface, PCI Express bus interface, bus interface, data string, data bits) , multiple data output ports (external SATA bus interface, PCI Express bus interface, bus interface, data string, data bits) and at least one processing element for selectively interconnecting a selected data input (external SATA bus interface, PCI Express bus interface, bus interface, data string, data bits) port with a selected data output port within said cache memory ;
an interconnection for coupling a data output port of said cache memory within a first storage device controller with a data input port of said cache memory within a second storage device controller ;
and a first storage device selectively coupled to a dam output port of said cache memory within said second storage device controller wherein a multipath dynamically alterable hierarchical arrangement of storage device controllers is established .

US5504882A
CLAIM 10
. A data processing system comprising ;
a host processor (external SATA) ;
a plurality of storage device controllers adapted to emulate a storage device , each storage device controller having a cache memory which includes multiple data input ports , multiple data output ports and at least one processing element for selectively interconnecting a selective data input port with a selected data output port within said cache memory ;
a first interconnection for coupling said host processor to a data input port of said cache memory within a first storage device controller ;
a second interconnection for coupling a data output port of said cache memory within said first storage device controller with a data input port of said cache memory within a second storage device controller ;
and a first storage device selectively coupled to a data output port of said cache memory within said second storage device controller wherein a multipath dynamically alterable hierarchical arrangement of storage device controllers is established .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor coupled to the storage interface ;

a flash memory device (storage subsystem) coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US5504882A
CLAIM 1
. A fault tolerant data storage subsystem (flash memory device) , said data storage subsystem comprising : a plurality of storage device controllers adapted to emulate a storage device , each storage device controller having a cache memory which includes multiple data input ports , multiple data output ports and at least one processing element for selectively interconnecting a selected data input port with a selected data output port within said cache memory ;
an interconnection for coupling a data output port of said cache memory within a first storage device controller with a data input port of said cache memory within a second storage device controller ;
and a first storage device selectively coupled to a dam output port of said cache memory within said second storage device controller wherein a multipath dynamically alterable hierarchical arrangement of storage device controllers is established .

US9632727B2
CLAIM 13
. The system of claim 12 , wherein the logical-to-physical translation layer is stored in the flash memory device (storage subsystem) .
US5504882A
CLAIM 1
. A fault tolerant data storage subsystem (flash memory device) , said data storage subsystem comprising : a plurality of storage device controllers adapted to emulate a storage device , each storage device controller having a cache memory which includes multiple data input ports , multiple data output ports and at least one processing element for selectively interconnecting a selected data input port with a selected data output port within said cache memory ;
an interconnection for coupling a data output port of said cache memory within a first storage device controller with a data input port of said cache memory within a second storage device controller ;
and a first storage device selectively coupled to a dam output port of said cache memory within said second storage device controller wherein a multipath dynamically alterable hierarchical arrangement of storage device controllers is established .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor returns a predetermined data string (input ports, output ports, data input) .
US5504882A
CLAIM 1
. A fault tolerant data storage subsystem , said data storage subsystem comprising : a plurality of storage device controllers adapted to emulate a storage device , each storage device controller having a cache memory which includes multiple data input ports (external SATA bus interface, PCI Express bus interface, bus interface, data string, data bits) , multiple data output ports (external SATA bus interface, PCI Express bus interface, bus interface, data string, data bits) and at least one processing element for selectively interconnecting a selected data input (external SATA bus interface, PCI Express bus interface, bus interface, data string, data bits) port with a selected data output port within said cache memory ;
an interconnection for coupling a data output port of said cache memory within a first storage device controller with a data input port of said cache memory within a second storage device controller ;
and a first storage device selectively coupled to a dam output port of said cache memory within said second storage device controller wherein a multipath dynamically alterable hierarchical arrangement of storage device controllers is established .

US9632727B2
CLAIM 16
. The system of claim 15 , wherein data bits (input ports, output ports, data input) of the predetermined data string (input ports, output ports, data input) have a uniform logic level .
US5504882A
CLAIM 1
. A fault tolerant data storage subsystem , said data storage subsystem comprising : a plurality of storage device controllers adapted to emulate a storage device , each storage device controller having a cache memory which includes multiple data input ports (external SATA bus interface, PCI Express bus interface, bus interface, data string, data bits) , multiple data output ports (external SATA bus interface, PCI Express bus interface, bus interface, data string, data bits) and at least one processing element for selectively interconnecting a selected data input (external SATA bus interface, PCI Express bus interface, bus interface, data string, data bits) port with a selected data output port within said cache memory ;
an interconnection for coupling a data output port of said cache memory within a first storage device controller with a data input port of said cache memory within a second storage device controller ;
and a first storage device selectively coupled to a dam output port of said cache memory within said second storage device controller wherein a multipath dynamically alterable hierarchical arrangement of storage device controllers is established .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US5696917A

Filed: 1994-06-03     Issued: 1997-12-09

Method and apparatus for performing burst read operations in an asynchronous nonvolatile memory

(Original Assignee) Intel Corp     (Current Assignee) Intel Corp

Duane R. Mills, Brian Lyn Dipert, Sachidanandan Sambandan, Bruce McCormick, Richard D. Pashley
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system (computer system) , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data (main memory) pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US5696917A
CLAIM 7
. A computer system (computer system) comprising : a processor for initiating a burst read for a range of memory defined by a start address and a plurality of subsequent consecutive addresses ;
an asynchronous main memory (store data) bus coupled to the processor ;
a nonvolatile memory comprising a plurality of individual memory components , wherein consecutive addresses within the nonvolatile memory are not located in a same individual memory component ;
a fully programmable gate array (FPGA) coupled to the asynchronous main memory bus and the nonvolatile memory , wherein for each selected address of the memory range , the FPGA selects a page of the nonvolatile memory in accordance with m higher order bits of the selected address , wherein the FPGA enables the output of one of the individual memory components in accordance with n lower order bits of the selected address to provide data to the processor , wherein no wait states are generated as long as the selected address and a preceding address identify a same page of the nonvolatile memory .

US9632727B2
CLAIM 2
. The apparatus of claim 1 , wherein the indexer assigns logical addresses to physical addresses by use of index entries (chip enable) , and wherein the indexer removes an index entry corresponding to the identified logical address in response to the message .
US5696917A
CLAIM 3
. The method of claim 1 wherein step a) includes the step of : i) providing a chip enable (index entries) signal to the plurality of individual memory components .

US9632727B2
CLAIM 5
. The apparatus of claim 1 , further comprising a garbage collector (nonvolatile memory) configured to designate that the physical address previously assigned to the identified logical address comprises data suitable for removal from the solid-state storage medium in response to the message .
US5696917A
CLAIM 1
. A method of performing a burst read operation in an asynchronous non-volatile memory having a plurality of individual memory components , comprising the steps of : a) providing a first address as a current address to the plurality of individual memory components , wherein consecutive addresses are not located in a same memory component ;
b) selecting a current page of the asynchronous nonvolatile memory (garbage collector) identified by m higher order bits of the current address , wherein each of the individual memory components senses a location identified by the m higher order bits of the current address substantially simultaneously ;
c) enabling the output of a selected individual memory component in accordance with n lower bits of the current address to provide data associated with the current address ;
d) providing a consecutive subsequent address , wherein the current address becomes a preceding address , wherein the consecutive subsequent address becomes the current address ;
e) enabling the output of another selected individual memory component identified by n lower order bits of the current address without generating wait states to provide data associated with the current address , if the current and preceding addresses identify a same page ;
f) repeating steps d) thru e) as long as the current and preceding addresses identify the same page .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system (computer system) , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
US5696917A
CLAIM 7
. A computer system (computer system) comprising : a processor for initiating a burst read for a range of memory defined by a start address and a plurality of subsequent consecutive addresses ;
an asynchronous main memory bus coupled to the processor ;
a nonvolatile memory comprising a plurality of individual memory components , wherein consecutive addresses within the nonvolatile memory are not located in a same individual memory component ;
a fully programmable gate array (FPGA) coupled to the asynchronous main memory bus and the nonvolatile memory , wherein for each selected address of the memory range , the FPGA selects a page of the nonvolatile memory in accordance with m higher order bits of the selected address , wherein the FPGA enables the output of one of the individual memory components in accordance with n lower order bits of the selected address to provide data to the processor , wherein no wait states are generated as long as the selected address and a preceding address identify a same page of the nonvolatile memory .

US9632727B2
CLAIM 8
. The system of claim 7 , further comprising means for providing a storage interface (following steps) to accept requests to perform storage operations on the solid-state storage medium in reference to the logical blocks and to accept the message identifying the logical block that is not being used to reference data stored on the solid-state storage medium .
US5696917A
CLAIM 2
. The method of claim 1 further comprising the steps of : g) performing the following steps (storage interface) if the current and preceding addresses do not identify the same page : i) generating wait states ;
ii) selecting another page as the current page of the asynchronous nonvolatile memory , wherein the another page is identified by m higher order bits of the current address ;
h) returning to step c) .

US9632727B2
CLAIM 9
. The system of claim 7 , wherein unmapping the identified logical block comprises invalidating an entry of the logical-to-physical mappings , the entry indicating a mapping between the identified logical block and the particular storage block (memory components) .
US5696917A
CLAIM 1
. A method of performing a burst read operation in an asynchronous non-volatile memory having a plurality of individual memory components (particular storage block) , comprising the steps of : a) providing a first address as a current address to the plurality of individual memory components , wherein consecutive addresses are not located in a same memory component ;
b) selecting a current page of the asynchronous nonvolatile memory identified by m higher order bits of the current address , wherein each of the individual memory components senses a location identified by the m higher order bits of the current address substantially simultaneously ;
c) enabling the output of a selected individual memory component in accordance with n lower bits of the current address to provide data associated with the current address ;
d) providing a consecutive subsequent address , wherein the current address becomes a preceding address , wherein the consecutive subsequent address becomes the current address ;
e) enabling the output of another selected individual memory component identified by n lower order bits of the current address without generating wait states to provide data associated with the current address , if the current and preceding addresses identify a same page ;
f) repeating steps d) thru e) as long as the current and preceding addresses identify the same page .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface (following steps) configured to communicate with a storage client ;

a storage processor coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US5696917A
CLAIM 2
. The method of claim 1 further comprising the steps of : g) performing the following steps (storage interface) if the current and preceding addresses do not identify the same page : i) generating wait states ;
ii) selecting another page as the current page of the asynchronous nonvolatile memory , wherein the another page is identified by m higher order bits of the current address ;
h) returning to step c) .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request (same memory) specifying one or more logical addresses included in the empty-block directive command , the storage processor returns a predetermined data string .
US5696917A
CLAIM 1
. A method of performing a burst read operation in an asynchronous non-volatile memory having a plurality of individual memory components , comprising the steps of : a) providing a first address as a current address to the plurality of individual memory components , wherein consecutive addresses are not located in a same memory (read request) component ;
b) selecting a current page of the asynchronous nonvolatile memory identified by m higher order bits of the current address , wherein each of the individual memory components senses a location identified by the m higher order bits of the current address substantially simultaneously ;
c) enabling the output of a selected individual memory component in accordance with n lower bits of the current address to provide data associated with the current address ;
d) providing a consecutive subsequent address , wherein the current address becomes a preceding address , wherein the consecutive subsequent address becomes the current address ;
e) enabling the output of another selected individual memory component identified by n lower order bits of the current address without generating wait states to provide data associated with the current address , if the current and preceding addresses identify a same page ;
f) repeating steps d) thru e) as long as the current and preceding addresses identify the same page .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US5809527A

Filed: 1993-12-23     Issued: 1998-09-15

Outboard file cache system

(Original Assignee) Unisys Corp     (Current Assignee) Unisys Corp

Thomas P. Cooper, Robert E. Swenson
US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA (first host) bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface (file data) , and a Fibre Channel interface .
US5809527A
CLAIM 11
. A data processing system comprising : a first host (external SATA) processor for issuing file access commands , wherein each file access command defines an operation to be performed on a selectable one of one or more files and includes a file-identifier referencing one file of said one or more files and a logical offset referencing a selected portion of said one file , wherein one of said file access commands is a lock command , said first host processor including an input-output logic section which provides an interface for input of data to said first host processor and output of data from said first host processor ;
a second host processor for issuing file access commands wherein said one or more files are accessible by each of said first and said second host processor , said second host processor including an input-output logic section which provides an interface for input of data to said second host processor and output of data from said second host processor ;
an outboard file cache coupled to said input-output logic section of said first host processor and coupled to said input-output logic section of said second host processor and responsive to said file access commands from said first host processor and said second host processor , wherein said outboard file cache provides cache storage for said one or more files ;
said outboard file cache comprising , a cache memory , wherein said cache memory provides random access storage for selectable portions of said one or more files ;
a file descriptor table , wherein said file descriptor table provides storage for file-identifiers and offsets which are indicative of portions of said one or more files which are present in said cache memory ;
cache detection control interfaced with said file descriptor table and responsive to said file access commands , wherein said cache detection control detects whether said selected portion is present in said cache memory and provides a hit code if said selectable portion is present in said cache memory ;
and cache access control responsive to said hit code and interfaced with said cache memory , wherein said cache access control provides access to said one or more requested segments if said hit code is provided .

US5809527A
CLAIM 25
. The method of claim 16 , wherein said file access command further comprises a file type which designates whether said selected file is a normal file or a resident file ;
and further comprising the steps of : if said file type indicates a normal file and said selected portion of said selected file is not present in the outboard file cache , performing steps (a) , (b) , and (c) ;
(a) selecting a first portion of cache memory which is unused or presently assigned to a normal file for assignment to said selected portion of said selected file ;
(b) destaging said first portion of cache memory if the file data (internet SCSI interface) stored therein has been written ;
and (c) assigning said first portion of cache memory for storage of said selected portion of said selected file ;
if said file type indicates a resident file and said selected portion of said selected file is not present in the outboard file cache , performing steps (d) and (e) ;
(d) selecting an unused portion of cache memory in the outboard file cache for storing said selected portion of said selected file ;
and (e) assigning said unused portion of cache memory for storage of said selected portion of said selected file .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor (data store) coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US5809527A
CLAIM 25
. The method of claim 16 , wherein said file access command further comprises a file type which designates whether said selected file is a normal file or a resident file ;
and further comprising the steps of : if said file type indicates a normal file and said selected portion of said selected file is not present in the outboard file cache , performing steps (a) , (b) , and (c) ;
(a) selecting a first portion of cache memory which is unused or presently assigned to a normal file for assignment to said selected portion of said selected file ;
(b) destaging said first portion of cache memory if the file data store (storage processor) d therein has been written ;
and (c) assigning said first portion of cache memory for storage of said selected portion of said selected file ;
if said file type indicates a resident file and said selected portion of said selected file is not present in the outboard file cache , performing steps (d) and (e) ;
(d) selecting an unused portion of cache memory in the outboard file cache for storing said selected portion of said selected file ;
and (e) assigning said unused portion of cache memory for storage of said selected portion of said selected file .

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (data store) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
US5809527A
CLAIM 25
. The method of claim 16 , wherein said file access command further comprises a file type which designates whether said selected file is a normal file or a resident file ;
and further comprising the steps of : if said file type indicates a normal file and said selected portion of said selected file is not present in the outboard file cache , performing steps (a) , (b) , and (c) ;
(a) selecting a first portion of cache memory which is unused or presently assigned to a normal file for assignment to said selected portion of said selected file ;
(b) destaging said first portion of cache memory if the file data store (storage processor) d therein has been written ;
and (c) assigning said first portion of cache memory for storage of said selected portion of said selected file ;
if said file type indicates a resident file and said selected portion of said selected file is not present in the outboard file cache , performing steps (d) and (e) ;
(d) selecting an unused portion of cache memory in the outboard file cache for storing said selected portion of said selected file ;
and (e) assigning said unused portion of cache memory for storage of said selected portion of said selected file .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor (data store) returns a predetermined data string .
US5809527A
CLAIM 25
. The method of claim 16 , wherein said file access command further comprises a file type which designates whether said selected file is a normal file or a resident file ;
and further comprising the steps of : if said file type indicates a normal file and said selected portion of said selected file is not present in the outboard file cache , performing steps (a) , (b) , and (c) ;
(a) selecting a first portion of cache memory which is unused or presently assigned to a normal file for assignment to said selected portion of said selected file ;
(b) destaging said first portion of cache memory if the file data store (storage processor) d therein has been written ;
and (c) assigning said first portion of cache memory for storage of said selected portion of said selected file ;
if said file type indicates a resident file and said selected portion of said selected file is not present in the outboard file cache , performing steps (d) and (e) ;
(d) selecting an unused portion of cache memory in the outboard file cache for storing said selected portion of said selected file ;
and (e) assigning said unused portion of cache memory for storage of said selected portion of said selected file .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US5337275A

Filed: 1993-11-01     Issued: 1994-08-09

Method for releasing space in flash EEPROM memory array to allow the storage of compressed data

(Original Assignee) Intel Corp     (Current Assignee) Intel Corp

Richard P. Garner
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data (allocation table, logical sector) pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US5337275A
CLAIM 1
. A process for releasing sectors of a flash EEPROM memory array in which data furnished by a host computer is stored in compressed form so that memory space used for the sectors may be used to store new data , the flash EEPROM memory array including a plurality of individually erasable blocks and storing sectors of data in such blocks with a header providing a logical sector (store data, index entry) number , an indication of validity of data stored , the process comprising the steps of : storing a list of files and sectors which have been deleted by a host computer in a first table in host memory , storing a value indicating an amount of free space remaining in the flash EEPROM memory array , providing a first signal to the host computer when the value indicating the amount of free space falls below a first predetermined value to indicate that sectors listed in the first table should be released , and providing a second signal when the value indicating the amount of free space falls below a second predetermined value .

US5337275A
CLAIM 14
. A process for releasing sectors of a flash EEPROM memory array as claimed in claim 1 in which the step of storing a list of files and sectors which have been deleted by a host computer in a first table in host memory comprises listing all files and sectors of files indicated to be deleted in a host file allocation table (store data, index entry) .

US9632727B2
CLAIM 2
. The apparatus of claim 1 , wherein the indexer assigns logical addresses to physical addresses by use of index entries , and wherein the indexer removes an index entry (allocation table, logical sector) corresponding to the identified logical address in response to the message .
US5337275A
CLAIM 1
. A process for releasing sectors of a flash EEPROM memory array in which data furnished by a host computer is stored in compressed form so that memory space used for the sectors may be used to store new data , the flash EEPROM memory array including a plurality of individually erasable blocks and storing sectors of data in such blocks with a header providing a logical sector (store data, index entry) number , an indication of validity of data stored , the process comprising the steps of : storing a list of files and sectors which have been deleted by a host computer in a first table in host memory , storing a value indicating an amount of free space remaining in the flash EEPROM memory array , providing a first signal to the host computer when the value indicating the amount of free space falls below a first predetermined value to indicate that sectors listed in the first table should be released , and providing a second signal when the value indicating the amount of free space falls below a second predetermined value .

US5337275A
CLAIM 14
. A process for releasing sectors of a flash EEPROM memory array as claimed in claim 1 in which the step of storing a list of files and sectors which have been deleted by a host computer in a first table in host memory comprises listing all files and sectors of files indicated to be deleted in a host file allocation table (store data, index entry) .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface (new data) , and a Fibre Channel interface .
US5337275A
CLAIM 1
. A process for releasing sectors of a flash EEPROM memory array in which data furnished by a host computer is stored in compressed form so that memory space used for the sectors may be used to store new data (internet SCSI interface) , the flash EEPROM memory array including a plurality of individually erasable blocks and storing sectors of data in such blocks with a header providing a logical sector number , an indication of validity of data stored , the process comprising the steps of : storing a list of files and sectors which have been deleted by a host computer in a first table in host memory , storing a value indicating an amount of free space remaining in the flash EEPROM memory array , providing a first signal to the host computer when the value indicating the amount of free space falls below a first predetermined value to indicate that sectors listed in the first table should be released , and providing a second signal when the value indicating the amount of free space falls below a second predetermined value .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor (data store) coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US5337275A
CLAIM 1
. A process for releasing sectors of a flash EEPROM memory array in which data furnished by a host computer is stored in compressed form so that memory space used for the sectors may be used to store new data , the flash EEPROM memory array including a plurality of individually erasable blocks and storing sectors of data in such blocks with a header providing a logical sector number , an indication of validity of data store (storage processor) d , the process comprising the steps of : storing a list of files and sectors which have been deleted by a host computer in a first table in host memory , storing a value indicating an amount of free space remaining in the flash EEPROM memory array , providing a first signal to the host computer when the value indicating the amount of free space falls below a first predetermined value to indicate that sectors listed in the first table should be released , and providing a second signal when the value indicating the amount of free space falls below a second predetermined value .

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (data store) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
US5337275A
CLAIM 1
. A process for releasing sectors of a flash EEPROM memory array in which data furnished by a host computer is stored in compressed form so that memory space used for the sectors may be used to store new data , the flash EEPROM memory array including a plurality of individually erasable blocks and storing sectors of data in such blocks with a header providing a logical sector number , an indication of validity of data store (storage processor) d , the process comprising the steps of : storing a list of files and sectors which have been deleted by a host computer in a first table in host memory , storing a value indicating an amount of free space remaining in the flash EEPROM memory array , providing a first signal to the host computer when the value indicating the amount of free space falls below a first predetermined value to indicate that sectors listed in the first table should be released , and providing a second signal when the value indicating the amount of free space falls below a second predetermined value .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor (data store) returns a predetermined data string .
US5337275A
CLAIM 1
. A process for releasing sectors of a flash EEPROM memory array in which data furnished by a host computer is stored in compressed form so that memory space used for the sectors may be used to store new data , the flash EEPROM memory array including a plurality of individually erasable blocks and storing sectors of data in such blocks with a header providing a logical sector number , an indication of validity of data store (storage processor) d , the process comprising the steps of : storing a list of files and sectors which have been deleted by a host computer in a first table in host memory , storing a value indicating an amount of free space remaining in the flash EEPROM memory array , providing a first signal to the host computer when the value indicating the amount of free space falls below a first predetermined value to indicate that sectors listed in the first table should be released , and providing a second signal when the value indicating the amount of free space falls below a second predetermined value .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US5485595A

Filed: 1993-10-04     Issued: 1996-01-16

Flash memory mass storage architecture incorporating wear leveling technique without using cam cells

(Original Assignee) Cirrus Logic Inc     (Current Assignee) Micron Technology Inc

Mahmud Assar, Petro Estakhri, Siamack Nemazie, Mahmood Mozaffari
US9632727B2
CLAIM 2
. The apparatus of claim 1 , wherein the indexer assigns logical addresses to physical addresses by use of index entries (logical blocks) , and wherein the indexer removes an index entry corresponding to the identified logical address in response to the message .
US5485595A
CLAIM 1
. A non-volatile semiconductor mass storage device comprising : a . a plurality of non-volatile data blocks , wherein each one of the plurality of non-volatile data blocks is selectively programmable and erasable and further wherein only those of the plurality of non-volatile data blocks that contain no data can be programmed ;
b . a plurality of non-volatile information blocks for storing status information , each of said plurality of non-volatile information blocks directly corresponding to an appropriate one of the plurality of non-volatile data blocks , each of said plurality of non-volatile information blocks including a first flag which is indicative that a corresponding appropriate one of the plurality of non-volatile data blocks has been programmed , and further wherein an address of each one of a plurality of logical blocks (index entries) corresponds to a physical address of the appropriate one of the plurality of non-volatile data blocks ;
c . a comparator coupled to the plurality of non-volatile information blocks for determining whether any unprogrammed one of the plurality of non-volatile data blocks remain ;
d . a controller coupled to the comparator for setting a first flag ;
e . the controller for periodically erasing all of the plurality of non-volatile data blocks having first flags which are set ;
f . a storage programmer for storing a logical block address associated with each one of the plurality of non-volatile data blocks within an appropriate one of the plurality of non-volatile information blocks forming a stored logical block address , whereby an erase cycle is not needed each time an updated block replaces a superseded data block ;
and g . means for reading the non-volatile semiconductor mass storage device , comprising means for coupling a desired logical block address to the non-volatile semiconductor mass storage device and means for sequentially comparing the desired logical block address to each of the stored logical block addresses .

US9632727B2
CLAIM 5
. The apparatus of claim 1 , further comprising a garbage collector (logical block address) configured to designate that the physical address previously assigned to the identified logical address comprises data suitable for removal from the solid-state storage medium in response to the message .
US5485595A
CLAIM 1
. A non-volatile semiconductor mass storage device comprising : a . a plurality of non-volatile data blocks , wherein each one of the plurality of non-volatile data blocks is selectively programmable and erasable and further wherein only those of the plurality of non-volatile data blocks that contain no data can be programmed ;
b . a plurality of non-volatile information blocks for storing status information , each of said plurality of non-volatile information blocks directly corresponding to an appropriate one of the plurality of non-volatile data blocks , each of said plurality of non-volatile information blocks including a first flag which is indicative that a corresponding appropriate one of the plurality of non-volatile data blocks has been programmed , and further wherein an address of each one of a plurality of logical blocks corresponds to a physical address of the appropriate one of the plurality of non-volatile data blocks ;
c . a comparator coupled to the plurality of non-volatile information blocks for determining whether any unprogrammed one of the plurality of non-volatile data blocks remain ;
d . a controller coupled to the comparator for setting a first flag ;
e . the controller for periodically erasing all of the plurality of non-volatile data blocks having first flags which are set ;
f . a storage programmer for storing a logical block address (garbage collector) associated with each one of the plurality of non-volatile data blocks within an appropriate one of the plurality of non-volatile information blocks forming a stored logical block address , whereby an erase cycle is not needed each time an updated block replaces a superseded data block ;
and g . means for reading the non-volatile semiconductor mass storage device , comprising means for coupling a desired logical block address to the non-volatile semiconductor mass storage device and means for sequentially comparing the desired logical block address to each of the stored logical block addresses .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA (maximum count) bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
US5485595A
CLAIM 10
. The non-volatile semiconductor mass storage device according to claim 9 further comprising means for setting a predetermined maximum count (external SATA, external SATA bus interface) value for each of the plurality of non-volatile information blocks and means for storing a count value in each information block for preventing one of the plurality of non-volatile data blocks from being programmed more than a maximum number of times relative to all other of the plurality of non-volatile data blocks , and an erase inhibit flag in each information block coupled to the means for setting a predetermined maximum count value , the erase inhibit flag having one of a set condition and an unset condition for each block for preventing further erases to a block having its erase inhibit flag in the set condition .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US5592641A

Filed: 1993-06-30     Issued: 1997-01-07

Method and device for selectively locking write access to blocks in a memory array using write protect inputs and block enabled status

(Original Assignee) Intel Corp     (Current Assignee) Intel Corp

Mickey L. Fandrich, Salim B. Fedel, Thomas C. Price, Richard J. Durante, Geoffrey A. Gould, Timothy W. Goodell, Scott M. Doyle
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data (main memory) pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US5592641A
CLAIM 21
. A computer system , comprising : main memory (store data) means storing a set of write data for a program operation ;
central processing means reading the write data from the main memory means and transferring a write command and the write data over a host bus ;
circuit for inhibiting the program operation to a block of a non-volatile memory cell array by maintaining a lock cell , the circuit for inhibiting comprising : circuit for sensing a write protect input from a write protect pin coupled to the host bus , the write protect input indicating whether the write access lock is enabled or disabled ;
circuit for reading a lock bit from the lock cell and storing the lock bit into a block enabled status bit in a block status register corresponding to the block if the write protect input indicates that the write access lock is enabled , and if the block enabled status bit in the block status register corresponding to the block indicates that the block has the write access lock .

US9632727B2
CLAIM 2
. The apparatus of claim 1 , wherein the indexer assigns logical addresses to physical addresses by use of index entries , and wherein the indexer removes an index entry (memory array) corresponding to the identified logical address in response to the message .
US5592641A
CLAIM 34
. A method for detecting whether a block in a memory array (index entry) is write protected , the method comprising the steps of : testing a flag to determine if the flag indicates that the block is write protected , the flag indicating that the block is write protected if a block enabled bit in a block Status register indicates the block is write protected and a write protect input is enabled ;
if the flag indicates that the block is write protected , then reading a block status from the memory array ;
updating the block enabled bit in the block status register from the block status ;
testing the flag to determine if the block is write protected ;
and signaling an error if the block is write protected .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface (available block) , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
US5592641A
CLAIM 1
. A method for selectively locking write access to a block of a flash cell array in a flash memory device , comprising the steps of : receiving a lock command over a host bus , the lock command specifying the block of the flash cell array from among at least one available block (InfiniBand interface) in the flash cell array ;
disabling a block data row decoder for a block data area of the block , and enabling a block status row decoder for a block status area of the block ;
programming a lock cell in the block status area to a first logic state , such that the first logic state of the lock cell indicates that the block has a write access lock ;
receiving a write command targeted for the block , the write command to specifying a program or erase operation on the block ;
sensing a write protect input from a write protect pin of the flash memory device , the write protect input indicating whether the write access lock is enabled or disabled ;
if the write protect input indicates that the write access lock is enabled , and if a block enabled status bit in a block status register corresponding to the block indicates that the block has the write access lock , then reading a lock bit from the lock cell and storing the lock bit into the block enabled status bit in the block status register corresponding to the block ;
sensing the write protect input from the write protect pin of the flash memory device ;
if the write protect input indicate that the write access lock is enabled , and if the block enabled status bit in the block status register corresponding to the block indicates that the block has the write access lock , then signaling an error .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor coupled to the storage interface ;

a flash memory device (program operations, array controller) coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US5592641A
CLAIM 15
. A flash memory device , comprising : a flash cell array comprising a block , the block comprising a block data area and a block status area , the block status area comprising a lock cell indicating whether the block has a write access lock ;
a block status register circuit comprising a block status register , the block status register storing a block enabled status bit for the block ;
a circuit for sensing a write protect input from a write protect pin of the flash memory device the write protect input indicating whether the write access lock is enabled or disabled : a flash array controller (flash memory device) circuit receiving a program or erase command over a host bus targeted for the block , the flash array controller circuit reading a lock bit from the lock cell and storing the lock bit into the block enabled status bit in the block status register for the block after receiving the program or erase command , the flash array controller signaling an error if the write protect input indicates that the write access lock is enabled and if the block enabled status bit in the block status register for the block indicates that the block has the write access lock .

US5592641A
CLAIM 19
. The flash memory device of claim 15 , wherein the block status area further comprises a set of status cells storing a cycle count indicating a number of program operations (flash memory device) on the block .

US9632727B2
CLAIM 13
. The system of claim 12 , wherein the logical-to-physical translation layer is stored in the flash memory device (program operations, array controller) .
US5592641A
CLAIM 15
. A flash memory device , comprising : a flash cell array comprising a block , the block comprising a block data area and a block status area , the block status area comprising a lock cell indicating whether the block has a write access lock ;
a block status register circuit comprising a block status register , the block status register storing a block enabled status bit for the block ;
a circuit for sensing a write protect input from a write protect pin of the flash memory device the write protect input indicating whether the write access lock is enabled or disabled : a flash array controller (flash memory device) circuit receiving a program or erase command over a host bus targeted for the block , the flash array controller circuit reading a lock bit from the lock cell and storing the lock bit into the block enabled status bit in the block status register for the block after receiving the program or erase command , the flash array controller signaling an error if the write protect input indicates that the write access lock is enabled and if the block enabled status bit in the block status register for the block indicates that the block has the write access lock .

US5592641A
CLAIM 19
. The flash memory device of claim 15 , wherein the block status area further comprises a set of status cells storing a cycle count indicating a number of program operations (flash memory device) on the block .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US5325509A

Filed: 1993-06-21     Issued: 1994-06-28

Method of operating a cache memory including determining desirability of cache ahead or cache behind based on a number of available I/O operations

(Original Assignee) Zitel Corp     (Current Assignee) Zitel Corp

Marvin Lautzenheiser
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system , including storing data (more sector) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US5325509A
CLAIM 1
. A method for operating a cache memory system serving a host computer , said cache memory system including a mass storage device and a cache memory having a plurality of logical blocks , each logical block having a beginning and an end , and each logical block containing one or more sector (storing data) s , said method comprising the steps of : providing a first logical block of said cache memory for containing data accessed by said host ;
and performing a cache ahead operation comprising the steps of : determining that there is no second logical block of said cache memory which contains data that is stored at one or more locations within said mass storage device adjacent a first side of data stored in said first logical block of said cache memory , said first side being selected as a first one of the beginning and the end of data stored in said first logical block ;
determining a first distance measured in sectors between a first side of the data accessed by said host which is stored within said cache memory and a first side of said first logical block of said cache memory , said first side of said first logical block being selected as one of the beginning and the end of said first logical block ;
based on the size of the current host I/O operation , measured in sectors , determining the number of sequential host I/O operations required to transfer to said host computer data located within said cache memory between said data accessed by said host and said first side of said first logical block ;
determining if said number of host I/O operations required is less than a first preselected number ;
and if said number of host I/O operations required is less than said first preselected number , copying into a second logical block of said cache memory data which is stored at one or more locations within said mass storage device adjacent data corresponding to data stored at said first side of said first logical block of said cache memory .

US9632727B2
CLAIM 2
. The apparatus of claim 1 , wherein the indexer assigns logical addresses to physical addresses by use of index entries (logical blocks) , and wherein the indexer removes an index entry corresponding to the identified logical address in response to the message .
US5325509A
CLAIM 1
. A method for operating a cache memory system serving a host computer , said cache memory system including a mass storage device and a cache memory having a plurality of logical blocks (index entries) , each logical block having a beginning and an end , and each logical block containing one or more sectors , said method comprising the steps of : providing a first logical block of said cache memory for containing data accessed by said host ;
and performing a cache ahead operation comprising the steps of : determining that there is no second logical block of said cache memory which contains data that is stored at one or more locations within said mass storage device adjacent a first side of data stored in said first logical block of said cache memory , said first side being selected as a first one of the beginning and the end of data stored in said first logical block ;
determining a first distance measured in sectors between a first side of the data accessed by said host which is stored within said cache memory and a first side of said first logical block of said cache memory , said first side of said first logical block being selected as one of the beginning and the end of said first logical block ;
based on the size of the current host I/O operation , measured in sectors , determining the number of sequential host I/O operations required to transfer to said host computer data located within said cache memory between said data accessed by said host and said first side of said first logical block ;
determining if said number of host I/O operations required is less than a first preselected number ;
and if said number of host I/O operations required is less than said first preselected number , copying into a second logical block of said cache memory data which is stored at one or more locations within said mass storage device adjacent data corresponding to data stored at said first side of said first logical block of said cache memory .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (more sector) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
US5325509A
CLAIM 1
. A method for operating a cache memory system serving a host computer , said cache memory system including a mass storage device and a cache memory having a plurality of logical blocks , each logical block having a beginning and an end , and each logical block containing one or more sector (storing data) s , said method comprising the steps of : providing a first logical block of said cache memory for containing data accessed by said host ;
and performing a cache ahead operation comprising the steps of : determining that there is no second logical block of said cache memory which contains data that is stored at one or more locations within said mass storage device adjacent a first side of data stored in said first logical block of said cache memory , said first side being selected as a first one of the beginning and the end of data stored in said first logical block ;
determining a first distance measured in sectors between a first side of the data accessed by said host which is stored within said cache memory and a first side of said first logical block of said cache memory , said first side of said first logical block being selected as one of the beginning and the end of said first logical block ;
based on the size of the current host I/O operation , measured in sectors , determining the number of sequential host I/O operations required to transfer to said host computer data located within said cache memory between said data accessed by said host and said first side of said first logical block ;
determining if said number of host I/O operations required is less than a first preselected number ;
and if said number of host I/O operations required is less than said first preselected number , copying into a second logical block of said cache memory data which is stored at one or more locations within said mass storage device adjacent data corresponding to data stored at said first side of said first logical block of said cache memory .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor (data store) coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US5325509A
CLAIM 1
. A method for operating a cache memory system serving a host computer , said cache memory system including a mass storage device and a cache memory having a plurality of logical blocks , each logical block having a beginning and an end , and each logical block containing one or more sectors , said method comprising the steps of : providing a first logical block of said cache memory for containing data accessed by said host ;
and performing a cache ahead operation comprising the steps of : determining that there is no second logical block of said cache memory which contains data that is stored at one or more locations within said mass storage device adjacent a first side of data store (storage processor) d in said first logical block of said cache memory , said first side being selected as a first one of the beginning and the end of data stored in said first logical block ;
determining a first distance measured in sectors between a first side of the data accessed by said host which is stored within said cache memory and a first side of said first logical block of said cache memory , said first side of said first logical block being selected as one of the beginning and the end of said first logical block ;
based on the size of the current host I/O operation , measured in sectors , determining the number of sequential host I/O operations required to transfer to said host computer data located within said cache memory between said data accessed by said host and said first side of said first logical block ;
determining if said number of host I/O operations required is less than a first preselected number ;
and if said number of host I/O operations required is less than said first preselected number , copying into a second logical block of said cache memory data which is stored at one or more locations within said mass storage device adjacent data corresponding to data stored at said first side of said first logical block of said cache memory .

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (data store) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
US5325509A
CLAIM 1
. A method for operating a cache memory system serving a host computer , said cache memory system including a mass storage device and a cache memory having a plurality of logical blocks , each logical block having a beginning and an end , and each logical block containing one or more sectors , said method comprising the steps of : providing a first logical block of said cache memory for containing data accessed by said host ;
and performing a cache ahead operation comprising the steps of : determining that there is no second logical block of said cache memory which contains data that is stored at one or more locations within said mass storage device adjacent a first side of data store (storage processor) d in said first logical block of said cache memory , said first side being selected as a first one of the beginning and the end of data stored in said first logical block ;
determining a first distance measured in sectors between a first side of the data accessed by said host which is stored within said cache memory and a first side of said first logical block of said cache memory , said first side of said first logical block being selected as one of the beginning and the end of said first logical block ;
based on the size of the current host I/O operation , measured in sectors , determining the number of sequential host I/O operations required to transfer to said host computer data located within said cache memory between said data accessed by said host and said first side of said first logical block ;
determining if said number of host I/O operations required is less than a first preselected number ;
and if said number of host I/O operations required is less than said first preselected number , copying into a second logical block of said cache memory data which is stored at one or more locations within said mass storage device adjacent data corresponding to data stored at said first side of said first logical block of said cache memory .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor (data store) returns a predetermined data string .
US5325509A
CLAIM 1
. A method for operating a cache memory system serving a host computer , said cache memory system including a mass storage device and a cache memory having a plurality of logical blocks , each logical block having a beginning and an end , and each logical block containing one or more sectors , said method comprising the steps of : providing a first logical block of said cache memory for containing data accessed by said host ;
and performing a cache ahead operation comprising the steps of : determining that there is no second logical block of said cache memory which contains data that is stored at one or more locations within said mass storage device adjacent a first side of data store (storage processor) d in said first logical block of said cache memory , said first side being selected as a first one of the beginning and the end of data stored in said first logical block ;
determining a first distance measured in sectors between a first side of the data accessed by said host which is stored within said cache memory and a first side of said first logical block of said cache memory , said first side of said first logical block being selected as one of the beginning and the end of said first logical block ;
based on the size of the current host I/O operation , measured in sectors , determining the number of sequential host I/O operations required to transfer to said host computer data located within said cache memory between said data accessed by said host and said first side of said first logical block ;
determining if said number of host I/O operations required is less than a first preselected number ;
and if said number of host I/O operations required is less than said first preselected number , copying into a second logical block of said cache memory data which is stored at one or more locations within said mass storage device adjacent data corresponding to data stored at said first side of said first logical block of said cache memory .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US5544347A

Filed: 1993-04-23     Issued: 1996-08-06

Data storage system controlled remote data mirroring with respectively maintained data indices

(Original Assignee) EMC Corp     (Current Assignee) EMC Corp

Moshe Yanai, Natan Vishlitzky, Bruno Alterescu, Daniel Castel, Gadi Shklarsky
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system , including storing data (storing data) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US5544347A
CLAIM 1
. A system for automatically providing and maintaining data , said system comprising : a host computer located in a first geographic location ;
a first data storage system located in a first geographic location and coupled to said host computer , for storing data (storing data) to be accessed by at least said host computer ;
a second data storage system located in a second geographic location geographically remote from said first location , coupled to said first data storage system , for receiving at least data from said first data storage system ;
and said first data storage system enabling transfer of said data to said second data storage system , concurrently with said data received from said host computer , so as to nearly simultaneously maintain a concurrent copy of data stored on said first data storage system and on said second data storage system wherein both said first and said second data storage systems maintain an index , said index including at least a first indicator providing an indication of whether a predetermined data element stored on said first data storage system is valid , and at least a second indicator providing an indication of whether said predetermined data element stored on said second data storage system is valid .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one (first location) of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface (communication link) , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA (first host) bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
US5544347A
CLAIM 1
. A system for automatically providing and maintaining data , said system comprising : a host computer located in a first geographic location ;
a first data storage system located in a first geographic location and coupled to said host computer , for storing data to be accessed by at least said host computer ;
a second data storage system located in a second geographic location geographically remote from said first location (bus interface comprises one) , coupled to said first data storage system , for receiving at least data from said first data storage system ;
and said first data storage system enabling transfer of said data to said second data storage system , concurrently with said data received from said host computer , so as to nearly simultaneously maintain a concurrent copy of data stored on said first data storage system and on said second data storage system wherein both said first and said second data storage systems maintain an index , said index including at least a first indicator providing an indication of whether a predetermined data element stored on said first data storage system is valid , and at least a second indicator providing an indication of whether said predetermined data element stored on said second data storage system is valid .

US5544347A
CLAIM 2
. The system of claim 1 , wherein said first data storage system and said second data storage system are coupled by a high speed communication link (PCI Express bus interface) .

US5544347A
CLAIM 4
. The system of claim 1 , further including a second host computer , located in said second geographic location geographically remote from said first location , and coupled to at least said second data storage system , for storing a second quantity of data to be accessed by at least said second host computer , and for at least retrieving said data stored on said second data storage system and copied from said data on said first data storage system upon failure of said first host (external SATA) and said first data storage system .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (storing data) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
US5544347A
CLAIM 1
. A system for automatically providing and maintaining data , said system comprising : a host computer located in a first geographic location ;
a first data storage system located in a first geographic location and coupled to said host computer , for storing data (storing data) to be accessed by at least said host computer ;
a second data storage system located in a second geographic location geographically remote from said first location , coupled to said first data storage system , for receiving at least data from said first data storage system ;
and said first data storage system enabling transfer of said data to said second data storage system , concurrently with said data received from said host computer , so as to nearly simultaneously maintain a concurrent copy of data stored on said first data storage system and on said second data storage system wherein both said first and said second data storage systems maintain an index , said index including at least a first indicator providing an indication of whether a predetermined data element stored on said first data storage system is valid , and at least a second indicator providing an indication of whether said predetermined data element stored on said second data storage system is valid .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor (data store) coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US5544347A
CLAIM 1
. A system for automatically providing and maintaining data , said system comprising : a host computer located in a first geographic location ;
a first data storage system located in a first geographic location and coupled to said host computer , for storing data to be accessed by at least said host computer ;
a second data storage system located in a second geographic location geographically remote from said first location , coupled to said first data storage system , for receiving at least data from said first data storage system ;
and said first data storage system enabling transfer of said data to said second data storage system , concurrently with said data received from said host computer , so as to nearly simultaneously maintain a concurrent copy of data store (storage processor) d on said first data storage system and on said second data storage system wherein both said first and said second data storage systems maintain an index , said index including at least a first indicator providing an indication of whether a predetermined data element stored on said first data storage system is valid , and at least a second indicator providing an indication of whether said predetermined data element stored on said second data storage system is valid .

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (data store) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
US5544347A
CLAIM 1
. A system for automatically providing and maintaining data , said system comprising : a host computer located in a first geographic location ;
a first data storage system located in a first geographic location and coupled to said host computer , for storing data to be accessed by at least said host computer ;
a second data storage system located in a second geographic location geographically remote from said first location , coupled to said first data storage system , for receiving at least data from said first data storage system ;
and said first data storage system enabling transfer of said data to said second data storage system , concurrently with said data received from said host computer , so as to nearly simultaneously maintain a concurrent copy of data store (storage processor) d on said first data storage system and on said second data storage system wherein both said first and said second data storage systems maintain an index , said index including at least a first indicator providing an indication of whether a predetermined data element stored on said first data storage system is valid , and at least a second indicator providing an indication of whether said predetermined data element stored on said second data storage system is valid .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request (corresponding data) specifying one or more logical addresses included in the empty-block directive command , the storage processor (data store) returns a predetermined data string .
US5544347A
CLAIM 1
. A system for automatically providing and maintaining data , said system comprising : a host computer located in a first geographic location ;
a first data storage system located in a first geographic location and coupled to said host computer , for storing data to be accessed by at least said host computer ;
a second data storage system located in a second geographic location geographically remote from said first location , coupled to said first data storage system , for receiving at least data from said first data storage system ;
and said first data storage system enabling transfer of said data to said second data storage system , concurrently with said data received from said host computer , so as to nearly simultaneously maintain a concurrent copy of data store (storage processor) d on said first data storage system and on said second data storage system wherein both said first and said second data storage systems maintain an index , said index including at least a first indicator providing an indication of whether a predetermined data element stored on said first data storage system is valid , and at least a second indicator providing an indication of whether said predetermined data element stored on said second data storage system is valid .

US5544347A
CLAIM 9
. The system of claim 1 wherein said first indicator provides an indication of whether data stored in a predetermined data element storage location on said first data storage system is valid , and wherein said second indicator provides an indication of whether corresponding data (read request) stored in a corresponding data element storage location on said second data storage system is valid .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US5388083A

Filed: 1993-03-26     Issued: 1995-02-07

Flash memory mass storage architecture

(Original Assignee) Cirrus Logic Inc     (Current Assignee) Micron Technology Inc

Mahmud Assar, Siamack Nemazie, Petro Estakhri
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data (store data) pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US5388083A
CLAIM 1
. A non-volatile semiconductor mass storage device comprising : a . a plurality of non-volatile storage blocks , wherein each block is selectively programmable to store data (store data, storage client) and is selectively erasable and further wherein each block has a finite number of erase cycle lifetimes ;
and b . means for ensuring no block is subjected to more than a predetermined larger number of erase cycles than any other block .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology (represents a) Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
US5388083A
CLAIM 4
. The device according to claim 2 wherein the counter includes a plurality of bits programmed by sequentially programming each bit , one at a time , wherein each programmed bit represents a (Advanced Technology) count of one .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client (store data) that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
US5388083A
CLAIM 1
. A non-volatile semiconductor mass storage device comprising : a . a plurality of non-volatile storage blocks , wherein each block is selectively programmable to store data (store data, storage client) and is selectively erasable and further wherein each block has a finite number of erase cycle lifetimes ;
and b . means for ensuring no block is subjected to more than a predetermined larger number of erase cycles than any other block .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client (store data) ;

a storage processor coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US5388083A
CLAIM 1
. A non-volatile semiconductor mass storage device comprising : a . a plurality of non-volatile storage blocks , wherein each block is selectively programmable to store data (store data, storage client) and is selectively erasable and further wherein each block has a finite number of erase cycle lifetimes ;
and b . means for ensuring no block is subjected to more than a predetermined larger number of erase cycles than any other block .

US9632727B2
CLAIM 16
. The system of claim 15 , wherein data bits of the predetermined data string have a uniform logic (non-volatile storage) level .
US5388083A
CLAIM 1
. A non-volatile semiconductor mass storage device comprising : a . a plurality of non-volatile storage (uniform logic) blocks , wherein each block is selectively programmable to store data and is selectively erasable and further wherein each block has a finite number of erase cycle lifetimes ;
and b . means for ensuring no block is subjected to more than a predetermined larger number of erase cycles than any other block .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US5479638A

Filed: 1993-03-26     Issued: 1995-12-26

Flash memory mass storage architecture incorporation wear leveling technique

(Original Assignee) Cirrus Logic Inc     (Current Assignee) Micron Technology Inc

Mahmud Assar, Siamack Nemazie, Petro Estakhri
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system , including storing data (storing data) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data (store data) pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US5479638A
CLAIM 27
. A non-volatile semiconductor mass storage device comprising : a . a plurality of non-volatile storage blocks , wherein each block is selectively programmable to store data (store data, storage client) and is selectively erasable ;
b . a plurality of first flags , one first flag for each block , each first flag having a first logic state to indicate that a block has not been programmed with data and a second logic state to indicate that the block has been programmed with data ;
c . a selecting element coupled to the storage blocks and to the plurality of first flags for identifying an empty storage block having a first flag in the first logic state where new and updated data may be stored ;
d . a plurality of second flags that can only be changed in a block having its first flag in the second logic state , one second flag for each block , each second flag having a third logic state to indicate that the data in a block is valid and a fourth logic state to indicate that the data in the block has been superseded ;
e . a content addressable memory for storing a logical address assigned to a block of superseded data and a physical address of a block of updated data corresponding to the superseded data ;
and f . an erasing circuit coupled to each of the storage blocks for selectively erasing all blocks having a second flag in the fourth logic state , wherein the erasing circuit is not activated each time data is stored in a storage block ;
and g . means for directly correlating coupled to the storage blocks and to content addressable memory , for correlating a logical address assigned to the superseded data to a physical address of updated data .

US5479638A
CLAIM 37
. A method of storing data (storing data) into a non-volatile semiconductor mass storage device having a plurality of non-volatile storage blocks , wherein each block is selectively programmable and erasable wherein only blocks containing no data may be programmed , the method comprising the steps of : a . determining whether any unprogrammed blocks remain ;
b . replacing superseded data with updated data by ignoring blocks having superseded data and programming the updated data into a block containing no data without erasing the superseded data ;
and c . periodically and selectively erasing all blocks having superseded data ;
d . directly correlating a logical address assigned to a block of superseded data to a physical address of a corresponding block of updated data .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology (represents a) Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA (first controller, maximum count) bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface (new data) , and a Fibre Channel interface .
US5479638A
CLAIM 7
. The device according to claim 6 wherein the means for ensuring further comprises means for setting a predetermined maximum count (external SATA, external SATA bus interface) value coupled to each of the storage blocks , and an erase inhibit flag for each of the storage blocks coupled to a counter of a respective storage block , the erase inhibit flag having a set condition and an unset condition for each storage block , for preventing further erases to a block having its erase inhibit flag in the set condition .

US5479638A
CLAIM 9
. The device according to claim 7 wherein the counter for each block includes a plurality of bits programmed by sequentially programming each bit , one at a time , wherein each programmed bit represents a (Advanced Technology) count of one .

US5479638A
CLAIM 14
. A non-volatile semiconductor mass storage device comprising : a . a plurality of non-volatile storage blocks , wherein each block is selectively programmable and erasable ;
b . a first indicating element to provide a first indicia whether each block has been programmed with a data file ;
c . a second indicating element to provide a second indicia whether the data file of each programmed block is superseded ;
d . a programming element to program a new data (internet SCSI interface) file into an empty block ;
and e . a periodically activated erasing circuit coupled to each of the storage blocks for selectively erasing all blocks in which the data file is superseded , wherein the erasing circuit is not activated each time data is stored in one of the storage blocks ;
f . means for correlating coupled to the storage blocks and to the programming element for directly correlating a logical address assigned to superseded data to a physical address of updated data wherein the first indicating element , the second indicating element and the logical address are stored in a nonvolatile content addressable memory .

US5479638A
CLAIM 18
. The device according to claim 15 further comprising a first controller (external SATA, external SATA bus interface) coupled to the storage blocks and to the erasing circuit for ensuring that no block is subjected to more than a predetermined number of erase cycles relative to all other blocks .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (storing data) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client (store data) that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
US5479638A
CLAIM 27
. A non-volatile semiconductor mass storage device comprising : a . a plurality of non-volatile storage blocks , wherein each block is selectively programmable to store data (store data, storage client) and is selectively erasable ;
b . a plurality of first flags , one first flag for each block , each first flag having a first logic state to indicate that a block has not been programmed with data and a second logic state to indicate that the block has been programmed with data ;
c . a selecting element coupled to the storage blocks and to the plurality of first flags for identifying an empty storage block having a first flag in the first logic state where new and updated data may be stored ;
d . a plurality of second flags that can only be changed in a block having its first flag in the second logic state , one second flag for each block , each second flag having a third logic state to indicate that the data in a block is valid and a fourth logic state to indicate that the data in the block has been superseded ;
e . a content addressable memory for storing a logical address assigned to a block of superseded data and a physical address of a block of updated data corresponding to the superseded data ;
and f . an erasing circuit coupled to each of the storage blocks for selectively erasing all blocks having a second flag in the fourth logic state , wherein the erasing circuit is not activated each time data is stored in a storage block ;
and g . means for directly correlating coupled to the storage blocks and to content addressable memory , for correlating a logical address assigned to the superseded data to a physical address of updated data .

US5479638A
CLAIM 37
. A method of storing data (storing data) into a non-volatile semiconductor mass storage device having a plurality of non-volatile storage blocks , wherein each block is selectively programmable and erasable wherein only blocks containing no data may be programmed , the method comprising the steps of : a . determining whether any unprogrammed blocks remain ;
b . replacing superseded data with updated data by ignoring blocks having superseded data and programming the updated data into a block containing no data without erasing the superseded data ;
and c . periodically and selectively erasing all blocks having superseded data ;
d . directly correlating a logical address assigned to a block of superseded data to a physical address of a corresponding block of updated data .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client (store data) ;

a storage processor coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US5479638A
CLAIM 27
. A non-volatile semiconductor mass storage device comprising : a . a plurality of non-volatile storage blocks , wherein each block is selectively programmable to store data (store data, storage client) and is selectively erasable ;
b . a plurality of first flags , one first flag for each block , each first flag having a first logic state to indicate that a block has not been programmed with data and a second logic state to indicate that the block has been programmed with data ;
c . a selecting element coupled to the storage blocks and to the plurality of first flags for identifying an empty storage block having a first flag in the first logic state where new and updated data may be stored ;
d . a plurality of second flags that can only be changed in a block having its first flag in the second logic state , one second flag for each block , each second flag having a third logic state to indicate that the data in a block is valid and a fourth logic state to indicate that the data in the block has been superseded ;
e . a content addressable memory for storing a logical address assigned to a block of superseded data and a physical address of a block of updated data corresponding to the superseded data ;
and f . an erasing circuit coupled to each of the storage blocks for selectively erasing all blocks having a second flag in the fourth logic state , wherein the erasing circuit is not activated each time data is stored in a storage block ;
and g . means for directly correlating coupled to the storage blocks and to content addressable memory , for correlating a logical address assigned to the superseded data to a physical address of updated data .

US9632727B2
CLAIM 16
. The system of claim 15 , wherein data bits of the predetermined data string have a uniform logic (non-volatile storage) level .
US5479638A
CLAIM 1
. A non-volatile semiconductor mass storage device comprising : a . a plurality of non-volatile storage (uniform logic) blocks , wherein each block is selectively programmable and erasable and only blocks containing no data may be programmed ;
b . means for determining whether any unprogrammed blocks remain ;
c . means for replacing superseded data with updated data , the means for replacing including nonvolatile flag means , corresponding to each of the storage blocks , and programming means , wherein the nonvolatile flag means is set for blocks having superseded data and further wherein the programming means stores updated data into a block containing no data ;
and d . means for periodically and selectively erasing all blocks having nonvolatile flag means which are set , whereby an erase cycle is not needed each time data is stored into one of the blocks ;
e . means for correlating coupled to the storage blocks and to the means for replacing for directly correlating a logical address assigned to superseded data to a physical address of updated data wherein the non-volatile flag means and a logical address of each of the storage blocks are stored in a nonvolatile content addressable memory .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US5404485A

Filed: 1993-03-08     Issued: 1995-04-04

Flash file system

(Original Assignee) SanDisk IL Ltd     (Current Assignee) SanDisk IL Ltd

Amir Ban
US9632727B2
CLAIM 5
. The apparatus of claim 1 , further comprising a garbage collector (memory management) configured to designate that the physical address previously assigned to the identified logical address comprises data suitable for removal from the solid-state storage medium in response to the message .
US5404485A
CLAIM 1
. A memory management (garbage collector) method for a memory in which data can be written only in unwritten physical memory locations and in which a zone of contiguous memory locations can be simultaneously erased , comprising the steps of : organizing the memory into a plurality of units ;
organizing each unit into a plurality of blocks , each of said blocks made up of a plurality of contiguous physical memory locations ;
establishing an allocation map for each unit which indicates the status of each block in a unit as written , unwritten or deleted ;
establishing a virtual map to map virtual addresses to physical addresses ;
in writing data to said memory at a virtual address : (a) mapping said virtual address to a physical block address using said virtual map ;
(b) examining said allocation map for said unit to which said virtual address has been mapped in step (a) to determine the status of a block at said physical block address as written , unwritten or deleted ;
(c) if said block at said physical block address is in written or deleted status : (1) examining said allocation map for at least one of said units to identify an unwritten block address ;
(2) writing said data into said memory to said unwritten block address ;
(3) changing said allocation map for a block in a unit in which said data have been written in paragraph (c)(2) to indicate as written said previously unwritten block address where said data have been written ;
(4) changing said virtual map to map virtual addresses to physical addresses within a unit so that said virtual map maps said virtual address to the physical address of said previously unwritten block in which said data have been written in step (c)(2) ;
establishing a transfer unit in said memory in which all blocks are in unwritten status , said transfer unit including a transfer unit allocation map ;
periodically identifying a selected unit , other than said transfer unit , to be erased ;
reading each written block in said selected unit ;
writing each written block in said selected unit into said transfer unit ;
updating said transfer unit allocation map to indicate as written the status of blocks that have been written in the just previous writing step ;
erasing said selected unit ;
updating said virtual map to reflect the above-described movement of said written blocks .

US9632727B2
CLAIM 8
. The system of claim 7 , further comprising means for providing a storage interface (virtual addresses) to accept requests to perform storage operations on the solid-state storage medium in reference to the logical blocks and to accept the message identifying the logical block that is not being used to reference data stored on the solid-state storage medium .
US5404485A
CLAIM 1
. A memory management method for a memory in which data can be written only in unwritten physical memory locations and in which a zone of contiguous memory locations can be simultaneously erased , comprising the steps of : organizing the memory into a plurality of units ;
organizing each unit into a plurality of blocks , each of said blocks made up of a plurality of contiguous physical memory locations ;
establishing an allocation map for each unit which indicates the status of each block in a unit as written , unwritten or deleted ;
establishing a virtual map to map virtual addresses (storage interface) to physical addresses ;
in writing data to said memory at a virtual address : (a) mapping said virtual address to a physical block address using said virtual map ;
(b) examining said allocation map for said unit to which said virtual address has been mapped in step (a) to determine the status of a block at said physical block address as written , unwritten or deleted ;
(c) if said block at said physical block address is in written or deleted status : (1) examining said allocation map for at least one of said units to identify an unwritten block address ;
(2) writing said data into said memory to said unwritten block address ;
(3) changing said allocation map for a block in a unit in which said data have been written in paragraph (c)(2) to indicate as written said previously unwritten block address where said data have been written ;
(4) changing said virtual map to map virtual addresses to physical addresses within a unit so that said virtual map maps said virtual address to the physical address of said previously unwritten block in which said data have been written in step (c)(2) ;
establishing a transfer unit in said memory in which all blocks are in unwritten status , said transfer unit including a transfer unit allocation map ;
periodically identifying a selected unit , other than said transfer unit , to be erased ;
reading each written block in said selected unit ;
writing each written block in said selected unit into said transfer unit ;
updating said transfer unit allocation map to indicate as written the status of blocks that have been written in the just previous writing step ;
erasing said selected unit ;
updating said virtual map to reflect the above-described movement of said written blocks .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface (virtual addresses) configured to communicate with a storage client ;

a storage processor coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US5404485A
CLAIM 1
. A memory management method for a memory in which data can be written only in unwritten physical memory locations and in which a zone of contiguous memory locations can be simultaneously erased , comprising the steps of : organizing the memory into a plurality of units ;
organizing each unit into a plurality of blocks , each of said blocks made up of a plurality of contiguous physical memory locations ;
establishing an allocation map for each unit which indicates the status of each block in a unit as written , unwritten or deleted ;
establishing a virtual map to map virtual addresses (storage interface) to physical addresses ;
in writing data to said memory at a virtual address : (a) mapping said virtual address to a physical block address using said virtual map ;
(b) examining said allocation map for said unit to which said virtual address has been mapped in step (a) to determine the status of a block at said physical block address as written , unwritten or deleted ;
(c) if said block at said physical block address is in written or deleted status : (1) examining said allocation map for at least one of said units to identify an unwritten block address ;
(2) writing said data into said memory to said unwritten block address ;
(3) changing said allocation map for a block in a unit in which said data have been written in paragraph (c)(2) to indicate as written said previously unwritten block address where said data have been written ;
(4) changing said virtual map to map virtual addresses to physical addresses within a unit so that said virtual map maps said virtual address to the physical address of said previously unwritten block in which said data have been written in step (c)(2) ;
establishing a transfer unit in said memory in which all blocks are in unwritten status , said transfer unit including a transfer unit allocation map ;
periodically identifying a selected unit , other than said transfer unit , to be erased ;
reading each written block in said selected unit ;
writing each written block in said selected unit into said transfer unit ;
updating said transfer unit allocation map to indicate as written the status of blocks that have been written in the just previous writing step ;
erasing said selected unit ;
updating said virtual map to reflect the above-described movement of said written blocks .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
JPH0628108A

Filed: 1992-07-09     Issued: 1994-02-04

データ記憶システム

(Original Assignee) Hitachi Ltd; 株式会社日立製作所     

賢一 ▲高▼本, Makoto Kogai, Kazuo Nakakoshi, Naoya Takahashi, Kenichi Takamoto, Minoru Yoshida, 和夫 中越, 稔 吉田, 眞 小貝, 直也 高橋
US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface (ホスト) , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
JPH0628108A
CLAIM 1
【請求項1】 チャネルアダプタ及びディスクアダプタ を介してホスト (PCI Express bus interface) コンピュータに接続される複数の小型デ ィスク装置を備え、前記ディスク装置はそれぞれ小型デ ィスクドライブ装置とそのコントローラとを有するデー タ記憶システムにおいて、前記コントローラ内に不揮発 性キャッシュメモリを設けたことを特徴とするデータ記 憶システム。

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor (メモリ) coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
JPH0628108A
CLAIM 1
【請求項1】 チャネルアダプタ及びディスクアダプタ を介してホストコンピュータに接続される複数の小型デ ィスク装置を備え、前記ディスク装置はそれぞれ小型デ ィスクドライブ装置とそのコントローラとを有するデー タ記憶システムにおいて、前記コントローラ内に不揮発 性キャッシュメモリ (storage processor) を設けたことを特徴とするデータ記 憶システム。

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (メモリ) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
JPH0628108A
CLAIM 1
【請求項1】 チャネルアダプタ及びディスクアダプタ を介してホストコンピュータに接続される複数の小型デ ィスク装置を備え、前記ディスク装置はそれぞれ小型デ ィスクドライブ装置とそのコントローラとを有するデー タ記憶システムにおいて、前記コントローラ内に不揮発 性キャッシュメモリ (storage processor) を設けたことを特徴とするデータ記 憶システム。

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor (メモリ) returns a predetermined data string .
JPH0628108A
CLAIM 1
【請求項1】 チャネルアダプタ及びディスクアダプタ を介してホストコンピュータに接続される複数の小型デ ィスク装置を備え、前記ディスク装置はそれぞれ小型デ ィスクドライブ装置とそのコントローラとを有するデー タ記憶システムにおいて、前記コントローラ内に不揮発 性キャッシュメモリ (storage processor) を設けたことを特徴とするデータ記 憶システム。




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US5394531A

Filed: 1991-11-18     Issued: 1995-02-28

Dynamic storage allocation system for a prioritized cache

(Original Assignee) International Business Machines Corp     (Current Assignee) LSI Corp

Kevin F. Smith
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium (write operation) in response to requests from a computer system , including storing data (storing data) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US5394531A
CLAIM 1
. A computer-implemented method for managing a Least Recently Used (LRU) cache having storage space occupied by data contents defined over a priority class range 1 . . . N , said cache being located in a predetermined echelon of a CPU-coupled , multi-echelon , staged data storage system , data in said cache being referenced by read and write operation (solid state storage medium) s in a cycle , the time rate of said read and write references to said cache data being termed the hit rate , said method comprising the steps of : initially partitioning said cache into a plurality of cache partitions and assigning a hit rate estimate and a data storage space allocation to each said cache partition ;
and during each cycle of a plurality of consecutive cycles , performing the steps of : ascertaining a hit rate slope for each said cache partition , said hit rate slope corresponding to the ratio of a change in the hit rate in said each partition to a corresponding change in cache data storage space allocated to said each partition , and adjusting said cache data storage space allocation assigned to each said cache partition to render the respective hit rate slopes substantially equal among all said cache partitions .

US5394531A
CLAIM 7
. In a CPU-coupled , multi-echelon , staged data storage system , a computer-implemented method for managing a partitioned cache located at a predetermined echelon of said data storage system , said cache for storing data (storing data) for immediate reference by CPU read and write operations , said method comprising the steps of : initially partitioning said cache into a plurality of cache partitions ;
for each cache partition : initially assigning a cache storage space allocation , and ascertaining a cache hit rate slope that corresponds to a ratio of a change in a reference hit rate to the corresponding change in said storage space allocation necessary to create said change in reference hit rate , said reference hit rate corresponding to the time rate at which references are made to data which is in said each cache partition ;
comparing the cache hit rate slope of a first cache partition with the cache hit rate slope of a second cache partition ;
if the cache hit rate slope of said first cache partition is less than the cache hit rate slope of said second cache , deleting cache storage space from said first cache partition and adding it to the cache storage space allocated to said second partition ;
otherwise , repeating the comparing and deleting steps .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (storing data) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
US5394531A
CLAIM 7
. In a CPU-coupled , multi-echelon , staged data storage system , a computer-implemented method for managing a partitioned cache located at a predetermined echelon of said data storage system , said cache for storing data (storing data) for immediate reference by CPU read and write operations , said method comprising the steps of : initially partitioning said cache into a plurality of cache partitions ;
for each cache partition : initially assigning a cache storage space allocation , and ascertaining a cache hit rate slope that corresponds to a ratio of a change in a reference hit rate to the corresponding change in said storage space allocation necessary to create said change in reference hit rate , said reference hit rate corresponding to the time rate at which references are made to data which is in said each cache partition ;
comparing the cache hit rate slope of a first cache partition with the cache hit rate slope of a second cache partition ;
if the cache hit rate slope of said first cache partition is less than the cache hit rate slope of said second cache , deleting cache storage space from said first cache partition and adding it to the cache storage space allocated to said second partition ;
otherwise , repeating the comparing and deleting steps .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US5438671A

Filed: 1991-07-19     Issued: 1995-08-01

Method and system for transferring compressed bytes of information between separate hard disk drive units

(Original Assignee) Dell USA LP     (Current Assignee) Dell USA LP

John C. Miles
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium (one disk, hard disk) in response to requests from a computer system , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US5438671A
CLAIM 1
. A method , comprising the steps of : (a .) providing a first personal computer , comprising a first CPU , a first hard disk (storage client, state storage medium, state storage system, storage processer, solid state storage medium) drive , from which data is desired to be copied , and a first parallel port ;
(b .) providing a second personal computer containing a second CPU , a second hard disk drive , onto which data is desired to be copied , and a second parallel port ;
(c .) connecting said first and second parallel ports together by a multi-strand cable ;
(d .) running a software process on said first CPU which reads out raw data from each respective individual sector of said first drive , compresses said raw data into substantially non-repeated bytes of compressed data , and transmits said compressed data through said first parallel port ;
(e .) running a software process on said second CPU which receives said compressed data through said second parallel port , decompresses said compressed data to reproduce said raw data , and writes said raw data into individual sectors of said second drive which exactly correspond to said respective sectors of said first drive ;
and (f .) continuing said steps (d .) and (e .) , substantially simultaneously on said first and second CPUs , until substantially all of said first drive has been imaged onto said second drive .

US5438671A
CLAIM 16
. A system , comprising : a portable personal computer , comprising a CPU , at least one disk (storage client, state storage medium, state storage system, storage processer, solid state storage medium) drive , a serial port , a parallel port and software , stored in a nonvolatile medium , which can control said CPU so that : in response to a first user command sequence , said CPU executes instructions from said software to read out raw data from substantially all respective individual sectors of said drive , to compress said raw data into substantially non-repeated bytes of compressed data , and to transmit in parallel said compressed data through said parallel port ;
in response to a second user command sequence , said CPU executes instructions from said software to receive in parallel data through said parallel port , to decompress said data according to a substantially predetermined algorithm to produce corresponding uncompressed data , and to overwrite said substantially all individual sectors of said drive with said decompressed data , without regard to the file structure of said drive .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface (parallel data, first serial) configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial (parallel data, first serial) Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (Integrated Drive Electronics) (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
US5438671A
CLAIM 5
. The method of claim 1 , wherein said first computer also comprises a first serial (external Serial, bus interface, external Serial Advanced Technology Attachment bus interface, external SATA bus interface, external SATA) port ;
and wherein said first process can branch , in accordance with user command input , to send said compressed data over said first serial port .

US5438671A
CLAIM 6
. The method of claim 1 , wherein said first drive presents a respective Integrated Drive Electronics (Integrated Drive Electronics) (IDE) interface to said first CPU , and said second drive presents a respective Integrated Drive Electronics (IDE) interface to said second CPU .

US5438671A
CLAIM 16
. A system , comprising : a portable personal computer , comprising a CPU , at least one disk drive , a serial port , a parallel port and software , stored in a nonvolatile medium , which can control said CPU so that : in response to a first user command sequence , said CPU executes instructions from said software to read out raw data from substantially all respective individual sectors of said drive , to compress said raw data into substantially non-repeated bytes of compressed data , and to transmit in parallel said compressed data through said parallel port ;
in response to a second user command sequence , said CPU executes instructions from said software to receive in parallel data (external Serial, bus interface, external Serial Advanced Technology Attachment bus interface, external SATA bus interface, external SATA) through said parallel port , to decompress said data according to a substantially predetermined algorithm to produce corresponding uncompressed data , and to overwrite said substantially all individual sectors of said drive with said decompressed data , without regard to the file structure of said drive .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client (one disk, hard disk) that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
US5438671A
CLAIM 1
. A method , comprising the steps of : (a . ) providing a first personal computer , comprising a first CPU , a first hard disk (storage client, state storage medium, state storage system, storage processer, solid state storage medium) drive , from which data is desired to be copied , and a first parallel port ;
(b . ) providing a second personal computer containing a second CPU , a second hard disk drive , onto which data is desired to be copied , and a second parallel port ;
(c . ) connecting said first and second parallel ports together by a multi-strand cable ;
(d . ) running a software process on said first CPU which reads out raw data from each respective individual sector of said first drive , compresses said raw data into substantially non-repeated bytes of compressed data , and transmits said compressed data through said first parallel port ;
(e . ) running a software process on said second CPU which receives said compressed data through said second parallel port , decompresses said compressed data to reproduce said raw data , and writes said raw data into individual sectors of said second drive which exactly correspond to said respective sectors of said first drive ;
and (f . ) continuing said steps (d . ) and (e . ) , substantially simultaneously on said first and second CPUs , until substantially all of said first drive has been imaged onto said second drive .

US5438671A
CLAIM 16
. A system , comprising : a portable personal computer , comprising a CPU , at least one disk (storage client, state storage medium, state storage system, storage processer, solid state storage medium) drive , a serial port , a parallel port and software , stored in a nonvolatile medium , which can control said CPU so that : in response to a first user command sequence , said CPU executes instructions from said software to read out raw data from substantially all respective individual sectors of said drive , to compress said raw data into substantially non-repeated bytes of compressed data , and to transmit in parallel said compressed data through said parallel port ;
in response to a second user command sequence , said CPU executes instructions from said software to receive in parallel data through said parallel port , to decompress said data according to a substantially predetermined algorithm to produce corresponding uncompressed data , and to overwrite said substantially all individual sectors of said drive with said decompressed data , without regard to the file structure of said drive .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client (one disk, hard disk) ;

a storage processor coupled to the storage interface ;

a flash memory device (storage capacity) coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US5438671A
CLAIM 1
. A method , comprising the steps of : (a . ) providing a first personal computer , comprising a first CPU , a first hard disk (storage client, state storage medium, state storage system, storage processer, solid state storage medium) drive , from which data is desired to be copied , and a first parallel port ;
(b . ) providing a second personal computer containing a second CPU , a second hard disk drive , onto which data is desired to be copied , and a second parallel port ;
(c . ) connecting said first and second parallel ports together by a multi-strand cable ;
(d . ) running a software process on said first CPU which reads out raw data from each respective individual sector of said first drive , compresses said raw data into substantially non-repeated bytes of compressed data , and transmits said compressed data through said first parallel port ;
(e . ) running a software process on said second CPU which receives said compressed data through said second parallel port , decompresses said compressed data to reproduce said raw data , and writes said raw data into individual sectors of said second drive which exactly correspond to said respective sectors of said first drive ;
and (f . ) continuing said steps (d . ) and (e . ) , substantially simultaneously on said first and second CPUs , until substantially all of said first drive has been imaged onto said second drive .

US5438671A
CLAIM 8
. The method of claim 1 , wherein said second computer further comprises a third disk , which has more than three times the storage capacity (flash memory device) of said second disk .

US5438671A
CLAIM 16
. A system , comprising : a portable personal computer , comprising a CPU , at least one disk (storage client, state storage medium, state storage system, storage processer, solid state storage medium) drive , a serial port , a parallel port and software , stored in a nonvolatile medium , which can control said CPU so that : in response to a first user command sequence , said CPU executes instructions from said software to read out raw data from substantially all respective individual sectors of said drive , to compress said raw data into substantially non-repeated bytes of compressed data , and to transmit in parallel said compressed data through said parallel port ;
in response to a second user command sequence , said CPU executes instructions from said software to receive in parallel data through said parallel port , to decompress said data according to a substantially predetermined algorithm to produce corresponding uncompressed data , and to overwrite said substantially all individual sectors of said drive with said decompressed data , without regard to the file structure of said drive .

US9632727B2
CLAIM 13
. The system of claim 12 , wherein the logical-to-physical translation layer is stored in the flash memory device (storage capacity) .
US5438671A
CLAIM 8
. The method of claim 1 , wherein said second computer further comprises a third disk , which has more than three times the storage capacity (flash memory device) of said second disk .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer (one disk, hard disk) is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor returns a predetermined data string .
US5438671A
CLAIM 1
. A method , comprising the steps of : (a . ) providing a first personal computer , comprising a first CPU , a first hard disk (storage client, state storage medium, state storage system, storage processer, solid state storage medium) drive , from which data is desired to be copied , and a first parallel port ;
(b . ) providing a second personal computer containing a second CPU , a second hard disk drive , onto which data is desired to be copied , and a second parallel port ;
(c . ) connecting said first and second parallel ports together by a multi-strand cable ;
(d . ) running a software process on said first CPU which reads out raw data from each respective individual sector of said first drive , compresses said raw data into substantially non-repeated bytes of compressed data , and transmits said compressed data through said first parallel port ;
(e . ) running a software process on said second CPU which receives said compressed data through said second parallel port , decompresses said compressed data to reproduce said raw data , and writes said raw data into individual sectors of said second drive which exactly correspond to said respective sectors of said first drive ;
and (f . ) continuing said steps (d . ) and (e . ) , substantially simultaneously on said first and second CPUs , until substantially all of said first drive has been imaged onto said second drive .

US5438671A
CLAIM 16
. A system , comprising : a portable personal computer , comprising a CPU , at least one disk (storage client, state storage medium, state storage system, storage processer, solid state storage medium) drive , a serial port , a parallel port and software , stored in a nonvolatile medium , which can control said CPU so that : in response to a first user command sequence , said CPU executes instructions from said software to read out raw data from substantially all respective individual sectors of said drive , to compress said raw data into substantially non-repeated bytes of compressed data , and to transmit in parallel said compressed data through said parallel port ;
in response to a second user command sequence , said CPU executes instructions from said software to receive in parallel data through said parallel port , to decompress said data according to a substantially predetermined algorithm to produce corresponding uncompressed data , and to overwrite said substantially all individual sectors of said drive with said decompressed data , without regard to the file structure of said drive .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US5274799A

Filed: 1991-01-04     Issued: 1993-12-28

Storage device array architecture with copyback cache

(Original Assignee) Array Tech Corp     (Current Assignee) EMC Corp

William A. Brant, David C. Stallmo, Mark Walker, Albert Lui
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system , including storing data (storing data) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data (storing information) pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US5274799A
CLAIM 1
. A fault-tolerant storage device array including : a . a plurality of failure independent storage units for storing information (store data) as stripes of blocks , including at least data blocks and associated error-correction blocks ;
b . at least one copyback cache storage unit for temporarily storing data (storing data) blocks ;
c . a storage unit controller , coupled to the plurality of storage units and to the at least one copyback cache storage unit , including control means for : (1) writing received data blocks initially onto the at least one copyback cache storage unit as pending data blocks ;
(2) during idle time of at least some of the plurality of storage units : (a) reading at least one pending data block from at least one copyback cache storage unit ;
(b) accessing the storage units and reading information corresponding to each read pending data block ;
(c) generating an associated error-correction block from the read information and each read pending data block ;
(d) writing each such read pending data block and associated error-correction block to a corresponding stripe of the idle storage units ;
(3) reading requested data blocks from at least one copyback cache storage unit when such requested data blocks have not been written to the plurality of storage units , otherwise from the plurality of storage units .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (storing data) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
US5274799A
CLAIM 1
. A fault-tolerant storage device array including : a . a plurality of failure independent storage units for storing information as stripes of blocks , including at least data blocks and associated error-correction blocks ;
b . at least one copyback cache storage unit for temporarily storing data (storing data) blocks ;
c . a storage unit controller , coupled to the plurality of storage units and to the at least one copyback cache storage unit , including control means for : (1) writing received data blocks initially onto the at least one copyback cache storage unit as pending data blocks ;
(2) during idle time of at least some of the plurality of storage units : (a) reading at least one pending data block from at least one copyback cache storage unit ;
(b) accessing the storage units and reading information corresponding to each read pending data block ;
(c) generating an associated error-correction block from the read information and each read pending data block ;
(d) writing each such read pending data block and associated error-correction block to a corresponding stripe of the idle storage units ;
(3) reading requested data blocks from at least one copyback cache storage unit when such requested data blocks have not been written to the plurality of storage units , otherwise from the plurality of storage units .

US9632727B2
CLAIM 8
. The system of claim 7 , further comprising means for providing a storage interface to accept requests to perform storage operations (such request) on the solid-state storage medium in reference to the logical blocks and to accept the message identifying the logical block that is not being used to reference data stored on the solid-state storage medium .
US5274799A
CLAIM 1
. A fault-tolerant storage device array including : a . a plurality of failure independent storage units for storing information as stripes of blocks , including at least data blocks and associated error-correction blocks ;
b . at least one copyback cache storage unit for temporarily storing data blocks ;
c . a storage unit controller , coupled to the plurality of storage units and to the at least one copyback cache storage unit , including control means for : (1) writing received data blocks initially onto the at least one copyback cache storage unit as pending data blocks ;
(2) during idle time of at least some of the plurality of storage units : (a) reading at least one pending data block from at least one copyback cache storage unit ;
(b) accessing the storage units and reading information corresponding to each read pending data block ;
(c) generating an associated error-correction block from the read information and each read pending data block ;
(d) writing each such read pending data block and associated error-correction block to a corresponding stripe of the idle storage units ;
(3) reading requested data blocks from at least one copyback cache storage unit when such request (storage interface to accept requests to perform storage operations) ed data blocks have not been written to the plurality of storage units , otherwise from the plurality of storage units .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request (corresponding data) specifying one or more logical addresses included in the empty-block directive command , the storage processor returns a predetermined data string .
US5274799A
CLAIM 15
. The storage device array of claim 11 , further including means for reading selected data blocks from the at least one copyback cache storage unit and writing such selected data blocks to the plurality of storage units upon a failure of the storage unit controller to write all corresponding data (read request) blocks from the buffer memory to the plurality of storage units .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US5307497A

Filed: 1990-06-25     Issued: 1994-04-26

Disk operating system loadable from read only memory using installable file system interface

(Original Assignee) International Business Machines Corp     (Current Assignee) Lenovo Singapore Pte Ltd

Barry A. Feigenbaum, Rodney P. Springhetti
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state (read only memory, allocation table, said memory) storage medium in response to requests from a computer system , including storing data (read only memory, allocation table, said memory) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data (read only memory, allocation table, said memory) pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system (dent portion) , the message indicating that the identified logical address is erased .
US5307497A
CLAIM 1
. A personal computer comprising : a disk drive for storing files in clusters of sectors , said disk drive haivng a disk based file system that comrpises a file allocation table (solid state, store data, index entry, storing data) (FAT) and directory means for locating and accessing said files ;
a microprocessor that operates in a real mode and in a protected mode ;
a memory system comprising a random access memory (RAM) , a first read only memory (solid state, store data, index entry, storing data) (ROM) , and a second ROM , said memory (solid state, store data, index entry, storing data) system having a memory address space including a first region , which is accessible when said microprocessor operates in either one of said modes , and a second region which is accessible only when said microprocessor operates in said protected mode ;
said first ROM and said RAM are located in said first region , and said second ROM is located in said second region , of said memory address space ;
said first ROM storing a power-on self test (POST) program ;
said second ROM storing a ROM disk operating system (DOS) comprising DOS kernal programs for providing minimum operating system support for operating said personal computer , said DOS kernal programs further comprising initialization code for setting up said personal computer and a RAM loader program for loading programs from said second ROM into said RAM , additional DOS programs for providing , in conjunction with said DOS kernel programs , full operating system support for operation of said personal computer , and a bootstrap record containing information for accessing said DOS programs in said second ROM , and a ROMBOOT program for loading said DOS kernel ;
and boot-up means , including said microprocessor , for booting said personal computer in response to said personal computer being powered on , said boot-up means being operative to execute said POST program to thereby test said personal computer , to load said bootstrap record from said second ROM into said RAM , to execute said ROMBOOT program and load said DOS kernel programs into said RAM from said second ROM , and to execute said initialization code to thereby set up said personal computer for further operation under said ROM DOS .

US5307497A
CLAIM 6
. A personal computer in accordance with claim 4 , comprising : a display connected to said microprocessor for providing a user with a visual output from said personal computer system , said display requiring a warmup period (state storage medium) immediately after said computer system has been turned on in order to present a visually perceptible screen ;
and a graphical user interface program stored in said ROM for creating a graphical user interface comprising at least one screen ;
said microprocessor also being operative to load said graphical user interface program from said ROM into said RAM and then execute it to output said one screen at the end of said warmup period and provide an appearance , to the user , of an instant startup of said personal computer .

US5307497A
CLAIM 12
. A PCS in accordance with claim 11 comprising : an AUTOEXEC . BAT file and a CONFIG . SYS file stored in said ROM ;
said boot-up means being operative to load said AUTOEXEC . BAT file and said CONFIG . SYS file from ROM into RAM along with said DOS programs , and to process said AUTOEXEC . BAT file and said CONFIG . SYS file ;
and said graphical user interface program comprising a first resident portion (host operating system) loaded into said RAM while processing said CONFIG . SYS file and a second transient portion loaded into said RAM while processing said ATUOEXEC . BAT file .

US9632727B2
CLAIM 2
. The apparatus of claim 1 , wherein the indexer assigns logical addresses to physical addresses by use of index entries , and wherein the indexer removes an index entry (read only memory, allocation table, said memory) corresponding to the identified logical address in response to the message .
US5307497A
CLAIM 1
. A personal computer comprising : a disk drive for storing files in clusters of sectors , said disk drive haivng a disk based file system that comrpises a file allocation table (solid state, store data, index entry, storing data) (FAT) and directory means for locating and accessing said files ;
a microprocessor that operates in a real mode and in a protected mode ;
a memory system comprising a random access memory (RAM) , a first read only memory (solid state, store data, index entry, storing data) (ROM) , and a second ROM , said memory (solid state, store data, index entry, storing data) system having a memory address space including a first region , which is accessible when said microprocessor operates in either one of said modes , and a second region which is accessible only when said microprocessor operates in said protected mode ;
said first ROM and said RAM are located in said first region , and said second ROM is located in said second region , of said memory address space ;
said first ROM storing a power-on self test (POST) program ;
said second ROM storing a ROM disk operating system (DOS) comprising DOS kernal programs for providing minimum operating system support for operating said personal computer , said DOS kernal programs further comprising initialization code for setting up said personal computer and a RAM loader program for loading programs from said second ROM into said RAM , additional DOS programs for providing , in conjunction with said DOS kernel programs , full operating system support for operation of said personal computer , and a bootstrap record containing information for accessing said DOS programs in said second ROM , and a ROMBOOT program for loading said DOS kernel ;
and boot-up means , including said microprocessor , for booting said personal computer in response to said personal computer being powered on , said boot-up means being operative to execute said POST program to thereby test said personal computer , to load said bootstrap record from said second ROM into said RAM , to execute said ROMBOOT program and load said DOS kernel programs into said RAM from said second ROM , and to execute said initialization code to thereby set up said personal computer for further operation under said ROM DOS .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface (personal computer system, self test) configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
US5307497A
CLAIM 1
. A personal computer comprising : a disk drive for storing files in clusters of sectors , said disk drive haivng a disk based file system that comrpises a file allocation table (FAT) and directory means for locating and accessing said files ;
a microprocessor that operates in a real mode and in a protected mode ;
a memory system comprising a random access memory (RAM) , a first read only memory (ROM) , and a second ROM , said memory system having a memory address space including a first region , which is accessible when said microprocessor operates in either one of said modes , and a second region which is accessible only when said microprocessor operates in said protected mode ;
said first ROM and said RAM are located in said first region , and said second ROM is located in said second region , of said memory address space ;
said first ROM storing a power-on self test (bus interface) (POST) program ;
said second ROM storing a ROM disk operating system (DOS) comprising DOS kernal programs for providing minimum operating system support for operating said personal computer , said DOS kernal programs further comprising initialization code for setting up said personal computer and a RAM loader program for loading programs from said second ROM into said RAM , additional DOS programs for providing , in conjunction with said DOS kernel programs , full operating system support for operation of said personal computer , and a bootstrap record containing information for accessing said DOS programs in said second ROM , and a ROMBOOT program for loading said DOS kernel ;
and boot-up means , including said microprocessor , for booting said personal computer in response to said personal computer being powered on , said boot-up means being operative to execute said POST program to thereby test said personal computer , to load said bootstrap record from said second ROM into said RAM , to execute said ROMBOOT program and load said DOS kernel programs into said RAM from said second ROM , and to execute said initialization code to thereby set up said personal computer for further operation under said ROM DOS .

US5307497A
CLAIM 6
. A personal computer in accordance with claim 4 , comprising : a display connected to said microprocessor for providing a user with a visual output from said personal computer system (bus interface) , said display requiring a warmup period immediately after said computer system has been turned on in order to present a visually perceptible screen ;
and a graphical user interface program stored in said ROM for creating a graphical user interface comprising at least one screen ;
said microprocessor also being operative to load said graphical user interface program from said ROM into said RAM and then execute it to output said one screen at the end of said warmup period and provide an appearance , to the user , of an instant startup of said personal computer .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (read only memory, allocation table, said memory) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
US5307497A
CLAIM 1
. A personal computer comprising : a disk drive for storing files in clusters of sectors , said disk drive haivng a disk based file system that comrpises a file allocation table (solid state, store data, index entry, storing data) (FAT) and directory means for locating and accessing said files ;
a microprocessor that operates in a real mode and in a protected mode ;
a memory system comprising a random access memory (RAM) , a first read only memory (solid state, store data, index entry, storing data) (ROM) , and a second ROM , said memory (solid state, store data, index entry, storing data) system having a memory address space including a first region , which is accessible when said microprocessor operates in either one of said modes , and a second region which is accessible only when said microprocessor operates in said protected mode ;
said first ROM and said RAM are located in said first region , and said second ROM is located in said second region , of said memory address space ;
said first ROM storing a power-on self test (POST) program ;
said second ROM storing a ROM disk operating system (DOS) comprising DOS kernal programs for providing minimum operating system support for operating said personal computer , said DOS kernal programs further comprising initialization code for setting up said personal computer and a RAM loader program for loading programs from said second ROM into said RAM , additional DOS programs for providing , in conjunction with said DOS kernel programs , full operating system support for operation of said personal computer , and a bootstrap record containing information for accessing said DOS programs in said second ROM , and a ROMBOOT program for loading said DOS kernel ;
and boot-up means , including said microprocessor , for booting said personal computer in response to said personal computer being powered on , said boot-up means being operative to execute said POST program to thereby test said personal computer , to load said bootstrap record from said second ROM into said RAM , to execute said ROMBOOT program and load said DOS kernel programs into said RAM from said second ROM , and to execute said initialization code to thereby set up said personal computer for further operation under said ROM DOS .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US5193184A

Filed: 1990-06-18     Issued: 1993-03-09

Deleted data file space release system for a dynamically mapped virtual data storage subsystem

(Original Assignee) Oracle StorageTek     (Current Assignee) Oracle StorageTek

Jay S. Belsan, George A. Rudeseal, Charles A. Milligan, Mogens H. Pedersen, John F. Kitchen, Henry S. Ludlam
US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer (transmitting means) System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
US5193184A
CLAIM 1
. A dynamically mapped virtual memory data storage subsystem , that includes a plurality of data storage devices and that is connected to at least one host processor for storing data files for access by said host processor using a virtual address assigned by said host processor to each said data file and that deletes data files from said data storage devices independent of said host processor , wherein said host processor transmits predefined commands , each of which includes a set of parameters , to said data storage subsystem to activate said data storage subsystem to read and write data files on said data storage devices , comprising : means , responsive to said host processor transmitting a data file to said data storage subsystem for storage therein , for mapping a virtual address assigned by said host processor to said transmitted data file into an address which defines a physical memory location on one of said data storage devices ;
means for writing said transmitted data file to said defined physical memory location on said data storage device ;
means for storing data , including said address , indicative of said virtual address to physical memory location mapping for each of said data files stored on said data storage devices ;
means , in said host processor , responsive to said host processor generating controls signals to scratch one of said data files , for transmitting commands to said data storage subsystem , independent of said host processor , identifying said scratched data file , comprising : means for generating one of said predefined commands , independent of said host processor ;
means for altering at least one of said set of predefined parameters in said one generated predefined command to indicate to said data storage subsystem that said one command containing said altered parameters originates from said transmitting means (Small Computer) rather than said host processor ;
means for forwarding said altered command to said data storage system ;
and means , responsive to said scratched data file identifying commands , for expunging said data indicative of said virtual address to said physical memory location mapping from said storing means for said identified scratched data file .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client (predefined commands) that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
US5193184A
CLAIM 1
. A dynamically mapped virtual memory data storage subsystem , that includes a plurality of data storage devices and that is connected to at least one host processor for storing data files for access by said host processor using a virtual address assigned by said host processor to each said data file and that deletes data files from said data storage devices independent of said host processor , wherein said host processor transmits predefined commands (storage client) , each of which includes a set of parameters , to said data storage subsystem to activate said data storage subsystem to read and write data files on said data storage devices , comprising : means , responsive to said host processor transmitting a data file to said data storage subsystem for storage therein , for mapping a virtual address assigned by said host processor to said transmitted data file into an address which defines a physical memory location on one of said data storage devices ;
means for writing said transmitted data file to said defined physical memory location on said data storage device ;
means for storing data , including said address , indicative of said virtual address to physical memory location mapping for each of said data files stored on said data storage devices ;
means , in said host processor , responsive to said host processor generating controls signals to scratch one of said data files , for transmitting commands to said data storage subsystem , independent of said host processor , identifying said scratched data file , comprising : means for generating one of said predefined commands , independent of said host processor ;
means for altering at least one of said set of predefined parameters in said one generated predefined command to indicate to said data storage subsystem that said one command containing said altered parameters originates from said transmitting means rather than said host processor ;
means for forwarding said altered command to said data storage system ;
and means , responsive to said scratched data file identifying commands , for expunging said data indicative of said virtual address to said physical memory location mapping from said storing means for said identified scratched data file .

US9632727B2
CLAIM 9
. The system of claim 7 , wherein unmapping the identified logical block comprises invalidating an entry of the logical-to-physical mappings , the entry indicating a mapping between the identified logical block and the particular storage (two disk) block .
US5193184A
CLAIM 10
. A dynamically mapped virtual memory data storage subsystem that includes a plurality of disk drives , a subset of said plurality of disk drives being assigned into at least two redundancy groups , each redundancy group consisting of at least two disk (particular storage) drives , and which data storage subsystem is connected to at least one host processor for storing data files for access by said host processor using a virtual address assigned by said host processor to each said data file , and which data storage subsystem deletes data files from said redundancy groups independent of said host processor comprising : means , responsive to the receipt of a data file from said host processor for selecting one of said redundancy groups to store said received data file thereon ;
means for mapping a virtual address , assigned by said host processor to said received data file , into an address which defines a physical memory location on said disk drives in said selected redundancy group ;
means for writing said received data file and redundancy data associated with said received data file to said defined physical memory location in said selected redundancy group ;
mean for storing data indicative of said virtual address to physical memory location mapping for each of said data files stored on said redundancy groups ;
means in said host processor , responsive to said host processor generating control signals to scratch one of said data files , for transmitting commands to said data storage subsystem independent of said host processor identifying said scratched data file ;
means , responsive to said scratched data file identifying commands , for expunging said data indicative of said virtual address to physical memory location mapping from said storing means for said identified scratched data file .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client (predefined commands) ;

a storage processor (data indicative) coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US5193184A
CLAIM 1
. A dynamically mapped virtual memory data storage subsystem , that includes a plurality of data storage devices and that is connected to at least one host processor for storing data files for access by said host processor using a virtual address assigned by said host processor to each said data file and that deletes data files from said data storage devices independent of said host processor , wherein said host processor transmits predefined commands (storage client) , each of which includes a set of parameters , to said data storage subsystem to activate said data storage subsystem to read and write data files on said data storage devices , comprising : means , responsive to said host processor transmitting a data file to said data storage subsystem for storage therein , for mapping a virtual address assigned by said host processor to said transmitted data file into an address which defines a physical memory location on one of said data storage devices ;
means for writing said transmitted data file to said defined physical memory location on said data storage device ;
means for storing data , including said address , indicative of said virtual address to physical memory location mapping for each of said data files stored on said data storage devices ;
means , in said host processor , responsive to said host processor generating controls signals to scratch one of said data files , for transmitting commands to said data storage subsystem , independent of said host processor , identifying said scratched data file , comprising : means for generating one of said predefined commands , independent of said host processor ;
means for altering at least one of said set of predefined parameters in said one generated predefined command to indicate to said data storage subsystem that said one command containing said altered parameters originates from said transmitting means rather than said host processor ;
means for forwarding said altered command to said data storage system ;
and means , responsive to said scratched data file identifying commands , for expunging said data indicative (storage processor) of said virtual address to said physical memory location mapping from said storing means for said identified scratched data file .

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (data indicative) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
US5193184A
CLAIM 1
. A dynamically mapped virtual memory data storage subsystem , that includes a plurality of data storage devices and that is connected to at least one host processor for storing data files for access by said host processor using a virtual address assigned by said host processor to each said data file and that deletes data files from said data storage devices independent of said host processor , wherein said host processor transmits predefined commands , each of which includes a set of parameters , to said data storage subsystem to activate said data storage subsystem to read and write data files on said data storage devices , comprising : means , responsive to said host processor transmitting a data file to said data storage subsystem for storage therein , for mapping a virtual address assigned by said host processor to said transmitted data file into an address which defines a physical memory location on one of said data storage devices ;
means for writing said transmitted data file to said defined physical memory location on said data storage device ;
means for storing data , including said address , indicative of said virtual address to physical memory location mapping for each of said data files stored on said data storage devices ;
means , in said host processor , responsive to said host processor generating controls signals to scratch one of said data files , for transmitting commands to said data storage subsystem , independent of said host processor , identifying said scratched data file , comprising : means for generating one of said predefined commands , independent of said host processor ;
means for altering at least one of said set of predefined parameters in said one generated predefined command to indicate to said data storage subsystem that said one command containing said altered parameters originates from said transmitting means rather than said host processor ;
means for forwarding said altered command to said data storage system ;
and means , responsive to said scratched data file identifying commands , for expunging said data indicative (storage processor) of said virtual address to said physical memory location mapping from said storing means for said identified scratched data file .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor (data indicative) returns a predetermined data string .
US5193184A
CLAIM 1
. A dynamically mapped virtual memory data storage subsystem , that includes a plurality of data storage devices and that is connected to at least one host processor for storing data files for access by said host processor using a virtual address assigned by said host processor to each said data file and that deletes data files from said data storage devices independent of said host processor , wherein said host processor transmits predefined commands , each of which includes a set of parameters , to said data storage subsystem to activate said data storage subsystem to read and write data files on said data storage devices , comprising : means , responsive to said host processor transmitting a data file to said data storage subsystem for storage therein , for mapping a virtual address assigned by said host processor to said transmitted data file into an address which defines a physical memory location on one of said data storage devices ;
means for writing said transmitted data file to said defined physical memory location on said data storage device ;
means for storing data , including said address , indicative of said virtual address to physical memory location mapping for each of said data files stored on said data storage devices ;
means , in said host processor , responsive to said host processor generating controls signals to scratch one of said data files , for transmitting commands to said data storage subsystem , independent of said host processor , identifying said scratched data file , comprising : means for generating one of said predefined commands , independent of said host processor ;
means for altering at least one of said set of predefined parameters in said one generated predefined command to indicate to said data storage subsystem that said one command containing said altered parameters originates from said transmitting means rather than said host processor ;
means for forwarding said altered command to said data storage system ;
and means , responsive to said scratched data file identifying commands , for expunging said data indicative (storage processor) of said virtual address to said physical memory location mapping from said storing means for said identified scratched data file .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US5261068A

Filed: 1990-05-25     Issued: 1993-11-09

Dual path memory retrieval system for an interleaved dynamic RAM memory unit

(Original Assignee) Dell USA LP     (Current Assignee) Dell USA LP

Darius D. Gaskins, Thomas H. Holman, Jr., Michael L. Longwell, Keith D. Matteson, Terry J. Parks
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system , including storing data (said memory) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data (said memory) pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US5261068A
CLAIM 1
. A digital computer having a system for reading data from a memory unit of the type having first and second interleaved memory banks , each said memory (store data, storing data) bank having a plurality of memory locations , comprising : means for asserting and deasserting an access signal to specified locations of said first and second memory banks , each of said first and second memory banks outputting data stored at a first location in response to a first assertion of said access signal ;
a multiplexer having first , second and third input channels and configured to alternately receive data from said input channels , said first input channel tied directly to the output of said first memory bank ;
a first latch having an input tied to the output of said first memory bank and an output tied to said second input channel ;
and a second latch having an input tied to the output of said second memory bank and an output tied to said third input channel , said first and second latches closing in response to a first deassertion of said access signal .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface (second latches, parallel data, channel up) configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial (second latches, parallel data, channel up) Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
US5261068A
CLAIM 1
. A digital computer having a system for reading data from a memory unit of the type having first and second interleaved memory banks , each said memory bank having a plurality of memory locations , comprising : means for asserting and deasserting an access signal to specified locations of said first and second memory banks , each of said first and second memory banks outputting data stored at a first location in response to a first assertion of said access signal ;
a multiplexer having first , second and third input channels and configured to alternately receive data from said input channels , said first input channel tied directly to the output of said first memory bank ;
a first latch having an input tied to the output of said first memory bank and an output tied to said second input channel ;
and a second latch having an input tied to the output of said second memory bank and an output tied to said third input channel , said first and second latches (bus interface, PCI Express bus interface, bus interface comprises one, external Serial, external Serial Advanced Technology Attachment bus interface, external SATA bus interface) closing in response to a first deassertion of said access signal .

US5261068A
CLAIM 3
. A computer as set forth in claim 2 wherein said multiplexer switches from receiving data stored at said first location of said first memory bank from said first channel to receiving data stored at said first location of said first memory bank from said second input channel up (bus interface, PCI Express bus interface, bus interface comprises one, external Serial, external Serial Advanced Technology Attachment bus interface, external SATA bus interface) on said first deassertion of said access signal .

US5261068A
CLAIM 11
. A digital computer having a system for reading data from a memory unit of the type having a plurality of interleaved memory banks , each said interleaved memory bank having a plurality of locations for storage of information therein , comprising : means for simultaneously accessing a first series of memory locations , one of said locations in each of said interleaved memory banks , to commence reading data stored therein and for selectively latching said data ;
a multiplexer having a pair of input channels for each of said interleaved memory banks ;
and parallel data (bus interface, PCI Express bus interface, bus interface comprises one, external Serial, external Serial Advanced Technology Attachment bus interface, external SATA bus interface) transfer paths from each of said interleaved memory banks to said multiplexer , each of said parallel data transfer paths including a direct path from each of said interleaved memory banks to one of said pair of multiplexer input channels corresponding to that interleaved memory bank and a latched path from each of said interleaved memory banks to the other of said pair of multiplexer input channels corresponding to that bank .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (said memory) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
US5261068A
CLAIM 1
. A digital computer having a system for reading data from a memory unit of the type having first and second interleaved memory banks , each said memory (store data, storing data) bank having a plurality of memory locations , comprising : means for asserting and deasserting an access signal to specified locations of said first and second memory banks , each of said first and second memory banks outputting data stored at a first location in response to a first assertion of said access signal ;
a multiplexer having first , second and third input channels and configured to alternately receive data from said input channels , said first input channel tied directly to the output of said first memory bank ;
a first latch having an input tied to the output of said first memory bank and an output tied to said second input channel ;
and a second latch having an input tied to the output of said second memory bank and an output tied to said third input channel , said first and second latches closing in response to a first deassertion of said access signal .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor (first output signal) coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US5261068A
CLAIM 13
. A computer as set forth in claim 12 further comprising : a control circuit for controlling said multiplexer switching , said control circuit generating first and second output signals to said multiplexer ;
wherein said first output signal (storage processor) controls whether said multiplexer receives data from said direct paths or said latched paths and said second output signal selects the order in which said interleaved memory banks transmit data to said multiplexer .

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (first output signal) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
US5261068A
CLAIM 13
. A computer as set forth in claim 12 further comprising : a control circuit for controlling said multiplexer switching , said control circuit generating first and second output signals to said multiplexer ;
wherein said first output signal (storage processor) controls whether said multiplexer receives data from said direct paths or said latched paths and said second output signal selects the order in which said interleaved memory banks transmit data to said multiplexer .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor (first output signal) returns a predetermined data string .
US5261068A
CLAIM 13
. A computer as set forth in claim 12 further comprising : a control circuit for controlling said multiplexer switching , said control circuit generating first and second output signals to said multiplexer ;
wherein said first output signal (storage processor) controls whether said multiplexer receives data from said direct paths or said latched paths and said second output signal selects the order in which said interleaved memory banks transmit data to said multiplexer .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US5124987A

Filed: 1990-04-16     Issued: 1992-06-23

Logical track write scheduling system for a parallel disk drive array data storage subsystem

(Original Assignee) Oracle StorageTek     (Current Assignee) Oracle StorageTek

Charles A. Milligan, George A. Rudeseal
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system , including storing data (writing means) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US5124987A
CLAIM 1
. A disk memory system for storing data records for at least one associated data processor comprising : a plurality of disk drives , a subset of said plurality of disk drives being configured into at lest two redundancy groups , each redundancy group consisting of at lest two disk drives ;
means , responsive to the receipt of a stream of data records from said associated data processor , for selecting first available memory space in one of said redundancy groups to store said received stream of data records thereon ;
means for writing said received stream of data records and redundancy data associated with said received stream of data records in said selected first available memory space in said selected redundancy group ;
means , responsive to the subsequent receipt of modifications to one of said data records stored in said first available memory space in said selected redundancy group from said associated data processor , for writing said modified data record , exclusive of the rest of said received stream of data records and said redundancy data associated with said received stream of data records written in said first available memory space , in second available memory space in one of said redundancy groups by including said modified data record with a stream of data records subsequently received by said writing means (storing data) ;
and means for converting said first available memory space used to store said originally received data record to available memory space .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (writing means) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
US5124987A
CLAIM 1
. A disk memory system for storing data records for at least one associated data processor comprising : a plurality of disk drives , a subset of said plurality of disk drives being configured into at lest two redundancy groups , each redundancy group consisting of at lest two disk drives ;
means , responsive to the receipt of a stream of data records from said associated data processor , for selecting first available memory space in one of said redundancy groups to store said received stream of data records thereon ;
means for writing said received stream of data records and redundancy data associated with said received stream of data records in said selected first available memory space in said selected redundancy group ;
means , responsive to the subsequent receipt of modifications to one of said data records stored in said first available memory space in said selected redundancy group from said associated data processor , for writing said modified data record , exclusive of the rest of said received stream of data records and said redundancy data associated with said received stream of data records written in said first available memory space , in second available memory space in one of said redundancy groups by including said modified data record with a stream of data records subsequently received by said writing means (storing data) ;
and means for converting said first available memory space used to store said originally received data record to available memory space .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor (data indicative) coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US5124987A
CLAIM 8
. The system of claim 1 further including : means for maintaining data indicative (storage processor) of the correspondence between each said received stream of data records and the identity of the one of said at least two disk drives in said selected redundancy group on which said received stream of data records is stored .

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (data indicative) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
US5124987A
CLAIM 8
. The system of claim 1 further including : means for maintaining data indicative (storage processor) of the correspondence between each said received stream of data records and the identity of the one of said at least two disk drives in said selected redundancy group on which said received stream of data records is stored .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor (data indicative) returns a predetermined data string .
US5124987A
CLAIM 8
. The system of claim 1 further including : means for maintaining data indicative (storage processor) of the correspondence between each said received stream of data records and the identity of the one of said at least two disk drives in said selected redundancy group on which said received stream of data records is stored .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US5197130A

Filed: 1989-12-29     Issued: 1993-03-23

Cluster architecture for a highly parallel scalar/vector multiprocessor system

(Original Assignee) Supercomputer Systems LP     (Current Assignee) Morgan Stanley and Co LLC ; Hewlett Packard Enterprise Development LP ; IBM Holdings Inc

Steve S. Chen, Frederick J. Simmons, George A. Spix, Jimmie R. Wilson, Edward C. Miller, Roger E. Eckert, Douglas R. Beard
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations (logical address space) on the solid state storage medium in response to requests from a computer system , including storing data (said memory, main memory) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data (said memory, main memory) pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system (shared resources, interrupt signal) , the message indicating that the identified logical address is erased .
US5197130A
CLAIM 1
. A high parallel computer processing system , comprising : C multiprocessor clusters operably connected to one another , where C is an integer between 2 and 256 , inclusive , each multiprocessor cluster comprising : a shared memory means for physically storing and retrieving data and instructions to be executed by the computer processing system as part of a single common logical address space (storage operations, storage interface) without duplicate address spaces that includes all of said shared memory means of all of said C multiprocessor clusters ;
P processors means for executing said instructions and directly operating on said data in said shared memory means of any of said C multiprocessor clusters , where P is an integer between 4 and 256 , inclusive ;
Q distributed external interface means for transferring said data and said instructions between said shared memory means and one or more external data sources , where Q is an integer between 2 and 256 , inclusive ;
Z arbitration node means , each arbitration node means having one or more unique direct connection paths between said shared memory means in this multiprocessor cluster and a unique two or more of said processor means , and a unique one or more of said distributed external interface means , for symmetrically multiplexing said processor means and said distributed external interface means with said shared memory means , where Z is an integer between 2 and 128 , inclusive ;
and remote cluster adapter means operably connected to each of said Z arbitration node means and to said shared memory means in this multiprocessor cluster and to a remote cluster adpater means in all other of said multiprocessor clusters for allowing said Z arbitration node means of this multiprocessor cluster to access said shared memory means of all other of said multiprocessor clusters and for allowing all other of said multiprocessors to access said shared memory means of this multiprocessor cluster .

US5197130A
CLAIM 3
. The computer processing system of claim 1 wherein said shared memory means for each multiprocessor cluster comprises : S sections of main memory (store data, storing data) , each section having a separate direct connection path with each of said Z arbitration node means in this multiprocessor cluster for storing and retrieving said data and said instructions , where S is an integer between 2 and 256 , inclusive .

US5197130A
CLAIM 6
. The computer processing system of claim 1 wherein each multiprocessor cluster further comprises : global register means uniquely connected to each of said arbitration node means and said remote cluster adapter means in this multiprocessor cluster for storing and retrieving data and including an arithmetic and logic unit means for operating on said data separate from any operations performed by said processor means ;
and interrupt means uniquely connected to each of said arbitration node means and said remote cluster adapter means in this multiprocessor cluster for receiving and sending interrupt signal (state storage controller, host operating system) s , such that said shared memory means , said global register means and said interrupt means together comprise a set of shared resources (state storage controller, host operating system) which are symmetrically accessible to all of said processor means in this multiprocessor cluster , as well as all of said processor means in all other of said multiprocessor clusters .

US5197130A
CLAIM 18
. The highly parallel computer processing system of claim 14 wherein each multiprocessor cluster further comprises : global register means uniquely connected to each of said arbitration node means and said remote cluster adapter means in this multiprocessor cluster for storing , manipulating and retrieving data ;
and interrupt means uniquely connected to each of said arbitration node means and said remote cluster adapter means in this multiprocessor cluster for receiving and sending interrupt signals , such that said memory (store data, storing data) means , said global register means and said interrupt means together comprise a set of shared resources which are symmetrically accessible to all of said processor means in this multiprocessor cluster , as well as all of said processor means in all other of said multiprocessor clusters .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one (said instructions) of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
US5197130A
CLAIM 1
. A high parallel computer processing system , comprising : C multiprocessor clusters operably connected to one another , where C is an integer between 2 and 256 , inclusive , each multiprocessor cluster comprising : a shared memory means for physically storing and retrieving data and instructions to be executed by the computer processing system as part of a single common logical address space without duplicate address spaces that includes all of said shared memory means of all of said C multiprocessor clusters ;
P processors means for executing said instructions (bus interface comprises one) and directly operating on said data in said shared memory means of any of said C multiprocessor clusters , where P is an integer between 4 and 256 , inclusive ;
Q distributed external interface means for transferring said data and said instructions between said shared memory means and one or more external data sources , where Q is an integer between 2 and 256 , inclusive ;
Z arbitration node means , each arbitration node means having one or more unique direct connection paths between said shared memory means in this multiprocessor cluster and a unique two or more of said processor means , and a unique one or more of said distributed external interface means , for symmetrically multiplexing said processor means and said distributed external interface means with said shared memory means , where Z is an integer between 2 and 128 , inclusive ;
and remote cluster adapter means operably connected to each of said Z arbitration node means and to said shared memory means in this multiprocessor cluster and to a remote cluster adpater means in all other of said multiprocessor clusters for allowing said Z arbitration node means of this multiprocessor cluster to access said shared memory means of all other of said multiprocessor clusters and for allowing all other of said multiprocessors to access said shared memory means of this multiprocessor cluster .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (said memory, main memory) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
US5197130A
CLAIM 3
. The computer processing system of claim 1 wherein said shared memory means for each multiprocessor cluster comprises : S sections of main memory (store data, storing data) , each section having a separate direct connection path with each of said Z arbitration node means in this multiprocessor cluster for storing and retrieving said data and said instructions , where S is an integer between 2 and 256 , inclusive .

US5197130A
CLAIM 18
. The highly parallel computer processing system of claim 14 wherein each multiprocessor cluster further comprises : global register means uniquely connected to each of said arbitration node means and said remote cluster adapter means in this multiprocessor cluster for storing , manipulating and retrieving data ;
and interrupt means uniquely connected to each of said arbitration node means and said remote cluster adapter means in this multiprocessor cluster for receiving and sending interrupt signals , such that said memory (store data, storing data) means , said global register means and said interrupt means together comprise a set of shared resources which are symmetrically accessible to all of said processor means in this multiprocessor cluster , as well as all of said processor means in all other of said multiprocessor clusters .

US9632727B2
CLAIM 8
. The system of claim 7 , further comprising means for providing a storage interface (logical address space) to accept requests to perform storage operations (logical address space) on the solid-state storage medium in reference to the logical blocks and to accept the message identifying the logical block that is not being used to reference data stored on the solid-state storage medium .
US5197130A
CLAIM 1
. A high parallel computer processing system , comprising : C multiprocessor clusters operably connected to one another , where C is an integer between 2 and 256 , inclusive , each multiprocessor cluster comprising : a shared memory means for physically storing and retrieving data and instructions to be executed by the computer processing system as part of a single common logical address space (storage operations, storage interface) without duplicate address spaces that includes all of said shared memory means of all of said C multiprocessor clusters ;
P processors means for executing said instructions and directly operating on said data in said shared memory means of any of said C multiprocessor clusters , where P is an integer between 4 and 256 , inclusive ;
Q distributed external interface means for transferring said data and said instructions between said shared memory means and one or more external data sources , where Q is an integer between 2 and 256 , inclusive ;
Z arbitration node means , each arbitration node means having one or more unique direct connection paths between said shared memory means in this multiprocessor cluster and a unique two or more of said processor means , and a unique one or more of said distributed external interface means , for symmetrically multiplexing said processor means and said distributed external interface means with said shared memory means , where Z is an integer between 2 and 128 , inclusive ;
and remote cluster adapter means operably connected to each of said Z arbitration node means and to said shared memory means in this multiprocessor cluster and to a remote cluster adpater means in all other of said multiprocessor clusters for allowing said Z arbitration node means of this multiprocessor cluster to access said shared memory means of all other of said multiprocessor clusters and for allowing all other of said multiprocessors to access said shared memory means of this multiprocessor cluster .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface (logical address space) configured to communicate with a storage client ;

a storage processor (more processors) coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
US5197130A
CLAIM 1
. A high parallel computer processing system , comprising : C multiprocessor clusters operably connected to one another , where C is an integer between 2 and 256 , inclusive , each multiprocessor cluster comprising : a shared memory means for physically storing and retrieving data and instructions to be executed by the computer processing system as part of a single common logical address space (storage operations, storage interface) without duplicate address spaces that includes all of said shared memory means of all of said C multiprocessor clusters ;
P processors means for executing said instructions and directly operating on said data in said shared memory means of any of said C multiprocessor clusters , where P is an integer between 4 and 256 , inclusive ;
Q distributed external interface means for transferring said data and said instructions between said shared memory means and one or more external data sources , where Q is an integer between 2 and 256 , inclusive ;
Z arbitration node means , each arbitration node means having one or more unique direct connection paths between said shared memory means in this multiprocessor cluster and a unique two or more of said processor means , and a unique one or more of said distributed external interface means , for symmetrically multiplexing said processor means and said distributed external interface means with said shared memory means , where Z is an integer between 2 and 128 , inclusive ;
and remote cluster adapter means operably connected to each of said Z arbitration node means and to said shared memory means in this multiprocessor cluster and to a remote cluster adpater means in all other of said multiprocessor clusters for allowing said Z arbitration node means of this multiprocessor cluster to access said shared memory means of all other of said multiprocessor clusters and for allowing all other of said multiprocessors to access said shared memory means of this multiprocessor cluster .

US5197130A
CLAIM 8
. A highly parallel computer processing system comprising : a single shared memory means for storing and retrieving data and instructions to be executed by the computer processing system as part of one common logical address space without duplicate address spaces ;
P processor means for executing said instructions and operating directly on said data in said shared memory means , where P is an integer between 4 and 256 , inclusive ;
and Z arbitration node means , each arbitration node means having two or more unique unidirectional direct connection paths between said shared memory means and a unique two or more of said processor means for symmetrically multiplexing said unique two or more processors (storage processor) with said shared memory means , where Z is an integer between 2 and 128 , inclusive .

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (more processors) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
US5197130A
CLAIM 8
. A highly parallel computer processing system comprising : a single shared memory means for storing and retrieving data and instructions to be executed by the computer processing system as part of one common logical address space without duplicate address spaces ;
P processor means for executing said instructions and operating directly on said data in said shared memory means , where P is an integer between 4 and 256 , inclusive ;
and Z arbitration node means , each arbitration node means having two or more unique unidirectional direct connection paths between said shared memory means and a unique two or more of said processor means for symmetrically multiplexing said unique two or more processors (storage processor) with said shared memory means , where Z is an integer between 2 and 128 , inclusive .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer (logic unit) is configured such that , responsive to receiving a read request (transferring said data) specifying one or more logical addresses included in the empty-block directive command , the storage processor (more processors) returns a predetermined data string .
US5197130A
CLAIM 1
. A high parallel computer processing system , comprising : C multiprocessor clusters operably connected to one another , where C is an integer between 2 and 256 , inclusive , each multiprocessor cluster comprising : a shared memory means for physically storing and retrieving data and instructions to be executed by the computer processing system as part of a single common logical address space without duplicate address spaces that includes all of said shared memory means of all of said C multiprocessor clusters ;
P processors means for executing said instructions and directly operating on said data in said shared memory means of any of said C multiprocessor clusters , where P is an integer between 4 and 256 , inclusive ;
Q distributed external interface means for transferring said data (read request) and said instructions between said shared memory means and one or more external data sources , where Q is an integer between 2 and 256 , inclusive ;
Z arbitration node means , each arbitration node means having one or more unique direct connection paths between said shared memory means in this multiprocessor cluster and a unique two or more of said processor means , and a unique one or more of said distributed external interface means , for symmetrically multiplexing said processor means and said distributed external interface means with said shared memory means , where Z is an integer between 2 and 128 , inclusive ;
and remote cluster adapter means operably connected to each of said Z arbitration node means and to said shared memory means in this multiprocessor cluster and to a remote cluster adpater means in all other of said multiprocessor clusters for allowing said Z arbitration node means of this multiprocessor cluster to access said shared memory means of all other of said multiprocessor clusters and for allowing all other of said multiprocessors to access said shared memory means of this multiprocessor cluster .

US5197130A
CLAIM 6
. The computer processing system of claim 1 wherein each multiprocessor cluster further comprises : global register means uniquely connected to each of said arbitration node means and said remote cluster adapter means in this multiprocessor cluster for storing and retrieving data and including an arithmetic and logic unit (storage processer) means for operating on said data separate from any operations performed by said processor means ;
and interrupt means uniquely connected to each of said arbitration node means and said remote cluster adapter means in this multiprocessor cluster for receiving and sending interrupt signals , such that said shared memory means , said global register means and said interrupt means together comprise a set of shared resources which are symmetrically accessible to all of said processor means in this multiprocessor cluster , as well as all of said processor means in all other of said multiprocessor clusters .

US5197130A
CLAIM 8
. A highly parallel computer processing system comprising : a single shared memory means for storing and retrieving data and instructions to be executed by the computer processing system as part of one common logical address space without duplicate address spaces ;
P processor means for executing said instructions and operating directly on said data in said shared memory means , where P is an integer between 4 and 256 , inclusive ;
and Z arbitration node means , each arbitration node means having two or more unique unidirectional direct connection paths between said shared memory means and a unique two or more of said processor means for symmetrically multiplexing said unique two or more processors (storage processor) with said shared memory means , where Z is an integer between 2 and 128 , inclusive .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
US5371885A

Filed: 1989-08-29     Issued: 1994-12-06

High performance file system

(Original Assignee) Microsoft Corp     (Current Assignee) Microsoft Technology Licensing LLC

James G. Letwin
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data (storing information) pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
US5371885A
CLAIM 17
. A method in a computer system for organizing files in a hierarchical manner on a storage device , the hierarchy of files comprising a plurality of directories and files , the storage device having a plurality of logically contiguous sectors , each sector having a plurality of logically contiguous locations , the method comprising the steps of : allocating a descriptive block portion of the storage device , the descriptive block portion having a file system information portion and a sector allocation portion , the file system information portion having a pointer to a root directory , the sector allocation portion containing information describing the allocation of the sectors ;
for each directory , allocating a directory portion of the storage device for storing information (store data) relating to the directory , the directory portion having a directory FNODE portion and a directory block portion , the directory FNODE portion containing information describing the directory , the directory block portion containing entries describing each directory and file within the directory ;
and for each file , allocating a file portion of the storage device for storing information relating to the file , the file portion having a file FNODE portion and a data portion , the file FNODE portion containing information identifying the file and a plurality of run indicators , each run indicator identifying a run of a plurality of logically contiguous locations , the data portion comprising a plurality of runs .

US9632727B2
CLAIM 2
. The apparatus of claim 1 , wherein the indexer assigns logical addresses to physical addresses by use of index entries (directory entry) , and wherein the indexer removes an index entry corresponding to the identified logical address in response to the message .
US5371885A
CLAIM 11
. A method in a computer system of maintaining a directory hierarchy on a file storage device , the method comprising the steps of : for each directory , allocating a directory FNODE , each directory FNODE having a pointer to a directory structure ;
and allocating a directory structure , the directory structure comprising a plurality of directory entries , each directory entry (index entries) having a pointer to a file FNODE or a directory FNODE .

US9632727B2
CLAIM 5
. The apparatus of claim 1 , further comprising a garbage collector (allocating memory) configured to designate that the physical address previously assigned to the identified logical address comprises data suitable for removal from the solid-state storage medium in response to the message .
US5371885A
CLAIM 6
. A method in a computer system for tracking the allocation of memory locations to a file , the computer system having a memory with a plurality of memory locations , the method comprising the steps of : allocating memory (garbage collector) locations for a file FNODE , the file FNODE having memory locations for storing indicators of variable-length runs of logically contiguous memory locations allocated to the file ;
allocating a plurality of variable-length runs of logically contiguous memory locations to the file ;
for each run allocated to the file , setting an indicator in the file FNODE to identify a location and length of the run ;
and when the number of runs exceeds the capacity of the file FNODE for storing indicators of runs , storing in the file FNODE pointers to portions of memory locations , the portions for storing indicators of the runs allocated to the file .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface (data port) , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
US5371885A
CLAIM 17
. A method in a computer system for organizing files in a hierarchical manner on a storage device , the hierarchy of files comprising a plurality of directories and files , the storage device having a plurality of logically contiguous sectors , each sector having a plurality of logically contiguous locations , the method comprising the steps of : allocating a descriptive block portion of the storage device , the descriptive block portion having a file system information portion and a sector allocation portion , the file system information portion having a pointer to a root directory , the sector allocation portion containing information describing the allocation of the sectors ;
for each directory , allocating a directory portion of the storage device for storing information relating to the directory , the directory portion having a directory FNODE portion and a directory block portion , the directory FNODE portion containing information describing the directory , the directory block portion containing entries describing each directory and file within the directory ;
and for each file , allocating a file portion of the storage device for storing information relating to the file , the file portion having a file FNODE portion and a data port (external SATA bus interface) ion , the file FNODE portion containing information identifying the file and a plurality of run indicators , each run indicator identifying a run of a plurality of logically contiguous locations , the data portion comprising a plurality of runs .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request (read request) specifying one or more logical addresses included in the empty-block directive command , the storage processor returns a predetermined data string .
US5371885A
CLAIM 25
. The method of claim 24 including the steps of : when a read request (read request) is directed to a bad sector , mapping the bad sector to the good sector based on the hot fix map ;
and redirecting the read request to the good sector .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
WO2006124718A2

Filed: 2006-05-15     Issued: 2006-11-23

Method and system for closing an rdma connection

(Original Assignee) Microsoft Corporation     

Shuangtong Feng, James T. Pinkerton
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system , including storing data (computer readable medium) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
WO2006124718A2
CLAIM 18
. The computer readable medium (storing data) of claim 17 wherein the method further comprises : receiving an abortive disconnect request ;
performing an abortive packet stream disconnect ;
and setting the state of the QP to an error state .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (computer readable medium) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
WO2006124718A2
CLAIM 18
. The computer readable medium (storing data) of claim 17 wherein the method further comprises : receiving an abortive disconnect request ;
performing an abortive packet stream disconnect ;
and setting the state of the QP to an error state .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor coupled to the storage interface ;

a flash memory device (interface card) coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
WO2006124718A2
CLAIM 3
. The system of claim 1 wherein a host operating system comprises the disconnect request handler ;
and wherein the network I/O driver is associated with a network interface card (flash memory device) .

US9632727B2
CLAIM 13
. The system of claim 12 , wherein the logical-to-physical translation layer is stored in the flash memory device (interface card) .
WO2006124718A2
CLAIM 3
. The system of claim 1 wherein a host operating system comprises the disconnect request handler ;
and wherein the network I/O driver is associated with a network interface card (flash memory device) .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer (remote direct memory access) is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor returns a predetermined data string .
WO2006124718A2
CLAIM 1
. In a networking environment , a system for terminating a remote direct memory access (storage processer) (RDMA) connection , the RDMA connection carried over a packet stream , the system comprising : a disconnect request handler for the packet stream , the disconnect request handler configured for issuing a graceful disconnect request ;
and a driver for a network input/output (I/O) adapter that supports the packet stream , the network I/O driver configured for : receiving the graceful disconnect request ;
determining whether a condition of a queue pair (QP) allows for a graceful packet stream disconnect ;
and if the condition of the QP allows for a graceful disconnect , then gracefully disconnecting the packet stream , else performing an abortive packet stream disconnect , resetting the packet stream , and setting a state of the QP to an error state .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
WO2006076993A1

Filed: 2005-12-12     Issued: 2006-07-27

RNIC-BASED OFFLOAD OF iSCSI DATA MOVEMENT FUNCTION BY TARGET

(Original Assignee) International Business Machines Corporation; Ibm United Kingdom Limited     

Vadim Makhervaks, Giora Biran, Kalman Zvi Meth, Renato Recio, Zorik Machulsky
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium (write operation) in response to requests from a computer system , including storing data (computer program) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
WO2006076993A1
CLAIM 3
. The method according to claim 1 , wherein implementing the iSCSI offload target function comprises remote direct data placement of Data-Out payload to preregistered SCSI buffers in any order to any SCSI buffer offset using logic of an RDMA write operation (solid state storage medium) .

WO2006076993A1
CLAIM 11
. A computer program (storing data) product comprising : instructions for implementing an iSCSI offload target function with RNIC mechanisms used for RDMA functions .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (Small Computer System Interface) (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
WO2006076993A1
CLAIM 1
. A method comprising : implementing an iSCSI (Internet Small Computer System Interface (Small Computer System Interface) ) offload target function with RNIC (Remote-direct-memory-access-enabled Network Interface Controller) mechanisms used for RDMA (Remote Direct Memory Access) functions .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (computer program) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
WO2006076993A1
CLAIM 11
. A computer program (storing data) product comprising : instructions for implementing an iSCSI offload target function with RNIC mechanisms used for RDMA functions .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
WO2006065626A1

Filed: 2005-12-07     Issued: 2006-06-22

Rendering disk data unrecoverable using encryption

(Original Assignee) Network Appliance, Inc.     

William P. Mcgovern
US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface (graphic data) configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology (represents a) Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
WO2006065626A1
CLAIM 9
. The method of claim 1 , wherein the set of blocks represents a (Advanced Technology) file .

WO2006065626A1
CLAIM 17
. The system of claim 14 , wherein the cryptographic data (bus interface, PCI Express bus interface, bus interface comprises one) base is encrypted using a master key .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor (data store) coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
WO2006065626A1
CLAIM 1
. A method of disk sanitization comprising : encrypting data store (storage processor) d on a disk , including a set of blocks , by using a first encryption key ;
and in response to a request to delete the set of blocks , re-encrypting blocks stored on the disk other than the set of blocks , by using a second encryption key , and not re-encrypting the set of blocks ;
and deleting the first encryption key .

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (data store) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
WO2006065626A1
CLAIM 1
. A method of disk sanitization comprising : encrypting data store (storage processor) d on a disk , including a set of blocks , by using a first encryption key ;
and in response to a request to delete the set of blocks , re-encrypting blocks stored on the disk other than the set of blocks , by using a second encryption key , and not re-encrypting the set of blocks ;
and deleting the first encryption key .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor (data store) returns a predetermined data string .
WO2006065626A1
CLAIM 1
. A method of disk sanitization comprising : encrypting data store (storage processor) d on a disk , including a set of blocks , by using a first encryption key ;
and in response to a request to delete the set of blocks , re-encrypting blocks stored on the disk other than the set of blocks , by using a second encryption key , and not re-encrypting the set of blocks ;
and deleting the first encryption key .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
WO2006050455A2

Filed: 2005-11-04     Issued: 2006-05-11

Dynamically expandable and contractible fault-tolerant storage system with virtual hot spare

(Original Assignee) Trusted Data Corporation     

Geoffrey S. Barrall, Julian M. Terry, Kenneth Rosen
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system , including storing data (storing data) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
WO2006050455A2
CLAIM 1
. A method of storing data (storing data) in a plurality of storage devices so as to permit recovery from loss of one of the storage devices without data loss , the method comprising : storing data on the plurality of storage devices using at least one redundancy scheme in order to provide fault tolerance ;
and on loss of a first storage device , automatically reconfiguring the one or more remaining storage devices to restore fault tolerance for the data .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface (data loss) configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
WO2006050455A2
CLAIM 1
. A method of storing data in a plurality of storage devices so as to permit recovery from loss of one of the storage devices without data loss (bus interface) , the method comprising : storing data on the plurality of storage devices using at least one redundancy scheme in order to provide fault tolerance ;
and on loss of a first storage device , automatically reconfiguring the one or more remaining storage devices to restore fault tolerance for the data .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (storing data) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
WO2006050455A2
CLAIM 1
. A method of storing data (storing data) in a plurality of storage devices so as to permit recovery from loss of one of the storage devices without data loss , the method comprising : storing data on the plurality of storage devices using at least one redundancy scheme in order to provide fault tolerance ;
and on loss of a first storage device , automatically reconfiguring the one or more remaining storage devices to restore fault tolerance for the data .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor coupled to the storage interface ;

a flash memory device (storage capacity) coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
WO2006050455A2
CLAIM 14
. A method according to claim 12 , wherein the plurality of storage devices are installed in an array having a plurality of slots , and wherein generating a signal comprises : determining which slot in the array should be populated with additional storage capacity (flash memory device) and indicating said slot .

US9632727B2
CLAIM 13
. The system of claim 12 , wherein the logical-to-physical translation layer is stored in the flash memory device (storage capacity) .
WO2006050455A2
CLAIM 14
. A method according to claim 12 , wherein the plurality of storage devices are installed in an array having a plurality of slots , and wherein generating a signal comprises : determining which slot in the array should be populated with additional storage capacity (flash memory device) and indicating said slot .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
KR20050057185A

Filed: 2005-03-04     Issued: 2005-06-16

리모트 다이렉트 메모리 액세스가 가능한 네트워크 인터페이스 콘트롤러 스위치오버 및 스위치백 지원 장치 및 방법

(Original Assignee) 인터내셔널 비지네스 머신즈 코포레이션     

윌리엄 토드 보이드, 더글라스 조셉, 마이클 앤소니 코, 레나토 존 레시오
US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (프로그램) (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
KR20050057185A
CLAIM 9
컴퓨터 시스템에 로딩되어 실행될 때 컴퓨터로 하여금 제1항 내지 제8항 중 어느 한 항에 따른 방법의 단계들을 수행하게 하는 컴퓨터 프로그램 (Small Computer System Interface) 코드 성분들을 포함하는 컴퓨터 프로그램 .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses (어드레스) (어드레스) of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
KR20050057185A
CLAIM 5
제1항 내지 제4항 중 어느 한 항에 있어서 , 상기 대기열쌍의 취급을 상기 1차 RNIC로부터 상기 대체 RNIC로 스위치오버하는 단계는 , 상기 1차 RNIC에 대한 어드레스 (respective physical block addresses, physical block addresses) 를 상기 대체 RNIC의 어드레스 테이블에 추가하는 단계와 ;
상기 1차 RNIC를 상기 1차 RNIC 및 상기 대체 RNIC에 접속된 스위치에 액세스 불가능하게 하는 단계와 ;
상기 스위치에서 상기 1차 RNIC의 어드레스를 상기 대체 RNIC에 대한 어드레스로서 인식 가능하게 하는 단계를 포함하는 것인 스위치오버 수행 방법 .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
WO2006062511A1

Filed: 2004-12-06     Issued: 2006-06-15

System and method of erasing non-volatile recording media

(Original Assignee) Teac Aerospace Technologies, Inc.     

Peter Jensen
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state (solid state) storage medium in response to requests from a computer system (stored data) , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
WO2006062511A1
CLAIM 11
Claim 11 . The method of claim 1 , wherein the non-volatile recording medium is a hard disk (state storage medium, state storage system, storage processer) .

WO2006062511A1
CLAIM 12
Claim 12 . The method of claim 1 , wherein the non-volatile recording medium is a solid state (solid state) PROM memory .

WO2006062511A1
CLAIM 17
Claim 17 . A method of securely erasing data from a non-volatile recording medium , comprising : transmitting an erasure command from a processor in a computing device to a non-volatile recording medium controller , wherein the non-volatile recording medium controller is operably connected with the non-volatile recording medium ;
and , constructing a plurality of instructions to overwrite a plurality of memory locations corresponding to an erasure area identified by a pre-stored erasure area identifier , each of the instructions writing at least one of the memory locations in the erasure area identified by the pre-stored erasure area identifier with a pre-stored data (computer system) pattern .

US9632727B2
CLAIM 5
. The apparatus of claim 1 , further comprising a garbage collector (logical block address) configured to designate that the physical address previously assigned to the identified logical address comprises data suitable for removal from the solid-state storage medium in response to the message .
WO2006062511A1
CLAIM 6
Claim 6 . The method of claim 1 , wherein the erasure area identifier defines the erasure area according to a logical block address (garbage collector) ing scheme .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system (stored data) , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
WO2006062511A1
CLAIM 17
Claim 17 . A method of securely erasing data from a non-volatile recording medium , comprising : transmitting an erasure command from a processor in a computing device to a non-volatile recording medium controller , wherein the non-volatile recording medium controller is operably connected with the non-volatile recording medium ;
and , constructing a plurality of instructions to overwrite a plurality of memory locations corresponding to an erasure area identified by a pre-stored erasure area identifier , each of the instructions writing at least one of the memory locations in the erasure area identified by the pre-stored erasure area identifier with a pre-stored data (computer system) pattern .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer (hard disk) is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor returns a predetermined data string .
WO2006062511A1
CLAIM 11
Claim 11 . The method of claim 1 , wherein the non-volatile recording medium is a hard disk (state storage medium, state storage system, storage processer) .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
WO2005013143A2

Filed: 2004-07-23     Issued: 2005-02-10

A single chip protocol converter

(Original Assignee) International Business Machines Corporation     

Christos J. Georgiou, Victor L. Gregurick, Indira Nair, Valentina Salapura
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state (first function) storage medium in response to requests from a computer system (bus interface) , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data (memory storage) pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system (multiple processors) , the message indicating that the identified logical address is erased .
WO2005013143A2
CLAIM 9
. The microprocessor subsystem as claimed in Claim 1 , wherein said local memory storage (store data) device associated with said two or more microprocessor devices in said sub-system includes one or more of : a local SRAM memory , a memory cache , and an I-cache .

WO2005013143A2
CLAIM 20
. A system-on-chip (SoC) processor Integrated Circuit (IC) architecture comprising : a processor core for controlling SoC processing functions among a plurality of SoC component devices ;
an SoC local system bus device for enabling communications among said SoC component devices , one SoC component device comprising a single independent multiprocessor subsystem core comprising : a plurality of multiple processors (uniform logic, host operating system, storage processor, uniform logic level) , each multiple processor having a local memory associated therewith fonning a processor cluster ;
and a switch fabric means connecting each processor cluster within said SoC IC , wherein said single SoC multiprocessor subsystem core is capable of performing multithreading operation processing .

WO2005013143A2
CLAIM 35
. The single chip protocol converter IC as claimed in Claim 27 , wherein the SoC IC comprises components including a processor element , a memory storage element , a local communications bus and an I/O interface , said single chip protocol converter core further including a bus interface (computer system, bus interface) device for enabling communications between said single chip protocol converter core and said components of said SoC IC via said local communications bus .

WO2005013143A2
CLAIM 49
. A semiconductor integrated circuit chip (IC) comprising : one or more processor core assemblies , each core assembly comprising two or more microprocessor devices capable of performing operations according to a first function (solid state) ;
a local memory storage device associated with said two or more microprocessor devices for storing at least one of data and instructions in each processor core assembly ;
one or more interface devices enabling receipt and transmission of communications packets according to a communications protocol ;
and an interconnect means residing in said semiconductor IC for enabling communication between said two or more microprocessor devices and said interfa-ce devices , said IC capable of receiving and processing said packets according to a first operating function , and adapted to be re-configured for receiving and processing packets according to an entirely --tew- operating uro^

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface (bus interface) configured to communicatively couple the solid-state storage controller to the computer system (bus interface) , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface (bridge device, DMA controller) , an InfiniBand interface , an Integrated Drive Electronics (Integrated Circuit) (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA (bridge device, DMA controller) bus interface (bridge device, DMA controller) , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface (direct memory access) , and a Fibre Channel interface .
WO2005013143A2
CLAIM 5
. The microprocessor subsystem as claimed in Claim 4 , wherein components of said network processor assembly include one or more selected from the group comprising : an SRAM , a DDR controller , a PCI-X bridge , a direct memory access (internet SCSI interface) DMA device , a DMA controller (PCI Express bus interface, external SATA bus interface, external SATA) , an on-chip peripheral bus (OPB) for interfacing with external components via one or more I/O interface devices , and a Medium Access Control (MAC) protocol device employed to provide a data link layer interface to an Ethernet local area network (LAN) system .

WO2005013143A2
CLAIM 6
. The microprocessor-subsystem- as-claimed mdainri- , wherehrsaid smgfe-prσcessor core assembly further comprises a programmable processor local bus bridge device (PCI Express bus interface, external SATA bus interface, external SATA) for enabling data flow between the microprocessor subsystem and said communications bus device of said SoC IC .

WO2005013143A2
CLAIM 11
. A system-on-chip (SoC) Integrated Circuit (Drive Electronics, Integrated Drive Electronics) (IC) network processor architecture comprising : a network processor core for controlling SoC network processor functions among a plurality of network processor components ;
an SoC local system bus device for enabling communications among said SoC network processor components , one SoC network processor component comprising an independent multiprocessor subsystem core comprising : i-)-at-leastOne- mcroproces-ror4^ ii) at least one memory storage device for storing at least one of data and instructions ;
and iii) interconnect means for enabling high-speed communication between two or more microprocessor devices and said SoC IC local system bus device , wherein said single SoC multiprocessor subsystem core provides multi-threading network processing capability .

WO2005013143A2
CLAIM 35
. The single chip protocol converter IC as claimed in Claim 27 , wherein the SoC IC comprises components including a processor element , a memory storage element , a local communications bus and an I/O interface , said single chip protocol converter core further including a bus interface (computer system, bus interface) device for enabling communications between said single chip protocol converter core and said components of said SoC IC via said local communications bus .

US9632727B2
CLAIM 8
. The system of claim 7 , further comprising means for providing a storage interface (more processor) to accept requests to perform storage operations on the solid-state storage medium in reference to the logical blocks and to accept the message identifying the logical block that is not being used to reference data stored on the solid-state storage medium .
WO2005013143A2
CLAIM 27
. The single chip protocol converter integrated circuit (IC) as claimed in Claim 26 , said chip comprising : one or more processor (storage interface) core assemblies , each comprising two or more microprocessor devices capable of perfoπning operations to implement protocol conversion capability ;
a local storage device associated with said two or more microprocessor devices for storing at least one of data and instructions in each processor core assembly ;
one or more interface devices enabling receipt and transmission of communications packets according to one or more communications protocols ;
and an interconnect means residing in said protocol converter for enabling communication between said two or more microprocessor devices and said interface devices .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface (more processor) configured to communicate with a storage client ;

a storage processor (multiple processors) coupled to the storage interface ;

a flash memory device (arithmetic logic) coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
WO2005013143A2
CLAIM 20
. A system-on-chip (SoC) processor Integrated Circuit (IC) architecture comprising : a processor core for controlling SoC processing functions among a plurality of SoC component devices ;
an SoC local system bus device for enabling communications among said SoC component devices , one SoC component device comprising a single independent multiprocessor subsystem core comprising : a plurality of multiple processors (uniform logic, host operating system, storage processor, uniform logic level) , each multiple processor having a local memory associated therewith fonning a processor cluster ;
and a switch fabric means connecting each processor cluster within said SoC IC , wherein said single SoC multiprocessor subsystem core is capable of performing multithreading operation processing .

WO2005013143A2
CLAIM 23
. The system-on-chip (SoC) processor Integrated Circuit (IC) architecture as claimed in Claim 22 , wherein each of said plurality of multiple processors includes a local SRAM memory , one of an arithmetic logic (flash memory device) unit (ALU) or floating point unit (FPU) and corresponding data cache , and , an instruction cache (I-cache) .

WO2005013143A2
CLAIM 27
. The single chip protocol converter integrated circuit (IC) as claimed in Claim 26 , said chip comprising : one or more processor (storage interface) core assemblies , each comprising two or more microprocessor devices capable of perfoπning operations to implement protocol conversion capability ;
a local storage device associated with said two or more microprocessor devices for storing at least one of data and instructions in each processor core assembly ;
one or more interface devices enabling receipt and transmission of communications packets according to one or more communications protocols ;
and an interconnect means residing in said protocol converter for enabling communication between said two or more microprocessor devices and said interface devices .

US9632727B2
CLAIM 13
. The system of claim 12 , wherein the logical-to-physical translation layer is stored in the flash memory device (arithmetic logic) .
WO2005013143A2
CLAIM 23
. The system-on-chip (SoC) processor Integrated Circuit (IC) architecture as claimed in Claim 22 , wherein each of said plurality of multiple processors includes a local SRAM memory , one of an arithmetic logic (flash memory device) unit (ALU) or floating point unit (FPU) and corresponding data cache , and , an instruction cache (I-cache) .

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (multiple processors) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
WO2005013143A2
CLAIM 20
. A system-on-chip (SoC) processor Integrated Circuit (IC) architecture comprising : a processor core for controlling SoC processing functions among a plurality of SoC component devices ;
an SoC local system bus device for enabling communications among said SoC component devices , one SoC component device comprising a single independent multiprocessor subsystem core comprising : a plurality of multiple processors (uniform logic, host operating system, storage processor, uniform logic level) , each multiple processor having a local memory associated therewith fonning a processor cluster ;
and a switch fabric means connecting each processor cluster within said SoC IC , wherein said single SoC multiprocessor subsystem core is capable of performing multithreading operation processing .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer (logic unit) is configured such that , responsive to receiving a read request (corresponding data) specifying one or more logical addresses included in the empty-block directive command , the storage processor (multiple processors) returns a predetermined data string .
WO2005013143A2
CLAIM 20
. A system-on-chip (SoC) processor Integrated Circuit (IC) architecture comprising : a processor core for controlling SoC processing functions among a plurality of SoC component devices ;
an SoC local system bus device for enabling communications among said SoC component devices , one SoC component device comprising a single independent multiprocessor subsystem core comprising : a plurality of multiple processors (uniform logic, host operating system, storage processor, uniform logic level) , each multiple processor having a local memory associated therewith fonning a processor cluster ;
and a switch fabric means connecting each processor cluster within said SoC IC , wherein said single SoC multiprocessor subsystem core is capable of performing multithreading operation processing .

WO2005013143A2
CLAIM 23
. The system-on-chip (SoC) processor Integrated Circuit (IC) architecture as claimed in Claim 22 , wherein each of said plurality of multiple processors includes a local SRAM memory , one of an arithmetic logic unit (storage processer) (ALU) or floating point unit (FPU) and corresponding data (read request) cache , and , an instruction cache (I-cache) .

US9632727B2
CLAIM 16
. The system of claim 15 , wherein data bits of the predetermined data string have a uniform logic (multiple processors) level .
WO2005013143A2
CLAIM 20
. A system-on-chip (SoC) processor Integrated Circuit (IC) architecture comprising : a processor core for controlling SoC processing functions among a plurality of SoC component devices ;
an SoC local system bus device for enabling communications among said SoC component devices , one SoC component device comprising a single independent multiprocessor subsystem core comprising : a plurality of multiple processors (uniform logic, host operating system, storage processor, uniform logic level) , each multiple processor having a local memory associated therewith fonning a processor cluster ;
and a switch fabric means connecting each processor cluster within said SoC IC , wherein said single SoC multiprocessor subsystem core is capable of performing multithreading operation processing .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
EP1498822A2

Filed: 2004-07-16     Issued: 2005-01-19

State migration in multiple NIC RDMA enabled devices

(Original Assignee) Microsoft Corp     (Current Assignee) Microsoft Corp

Khawar M. Zuberi
US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface (network interfaces) , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
EP1498822A2
CLAIM 1
A method for transferring control between a first network interface and at least a second network interface in a multiple network interface device , after the first network interfaces (InfiniBand interface) transmits an identifier generated by the first network interface , the identifier associated with a memory location in the multiple network interface device to a second device , the identifier and an associated data field capable of being received by the second network interface , the method comprising : receiving a message from the second network interface to a program component , the message indicating the reception of the identifier from the second device ;
querying the first network interface to supply the program component with the a list of identifiers generated by the first network interface and associated memory locations in multiple network interface device memory ;
and transmitting a memory location associated with the identifier to the second network interface , the second network interface capable of transmitting the associated data field to the memory location associated with the identifier .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer (remote direct memory access) is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor returns a predetermined data string .
EP1498822A2
CLAIM 6
The method of claim 1 wherein the first network interface and the second network interface operate under a remote direct memory access (storage processer) (RDMA) protocol .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
KR20050009685A

Filed: 2004-07-16     Issued: 2005-01-25

다수의 nic rdma가 가능한 장치의 상태 이동

(Original Assignee) 마이크로소프트 코포레이션     

즈베리카워엠.
US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial (인터페이스를) Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface (프로토콜) , and a Fibre Channel interface .
KR20050009685A
CLAIM 6
제1항에 있어서 , 상기 제1 네트워크 인터페이스 및 상기 제2 네트워크 인터페이스는 원격 직접 메모리 액세스(RDMA) 프로토콜 (internet SCSI interface) 하에서 동작하는 방법 .

KR20050009685A
CLAIM 8
제1 네트워크 인터페이스 및 제2 네트워크 인터페이스를 (external Serial) 포함하는 호스팅 컴퓨터에서 상기 제1 네트워크 인터페이스 및 적어도 상기 제2 네트워크 인터페이스 사이의 제어를 전송하는 방법에 있어서 , 원격 컴퓨터로부터 식별자를 수신하는 단계 - 상기 식별자는 상기 제1 네트워크 인터페이스에 의해 생성되고 상기 호스트 컴퓨터 내의 메모리 위치와 관련됨 - ;
상기 식별자의 수신을 표시하는 메시지를 프로그램 컴포넌트로 송신하는 단계 - 상기 프로그램 컴포넌트는 상기 제1 네트워크 인터페이스에 의해 생성된 식별자들의 리스트 및 상기 호스트 컴퓨터 내의 관련 메모리 위치에 대하여 상기 제1 네트워크 인터페이스에 쿼리하도록 구성됨 - ;
상기 식별자들의 리스트가 상기 원격 컴퓨터로부터의 식별자를 포함하면 , 상기 식별자와 관련된 메모리 위치를 수신하는 단계 ;
및 상기 식별자들의 리스트가 상기 원격 컴퓨터로부터의 식별자를 포함하지 않으면 , 상기 원격 컴퓨터로부터의 상기 식별자를 무효화하는 단계 를 포함하는 방법 .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data referenced by logical blocks of a logical address space on physical storage (관련되고) blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
KR20050009685A
CLAIM 1
다수 네트워크 인터페이스 장치에서 , 제1 네트워크 인터페이스가 제1 네트워크 인터페이스에 의해 생성된 식별자를 제2 장치에 송신한 후 , 상기 제1 네트워크 인터페이스 및 적어도 제2 네트워크 인터페이스 사이의 제어를 전송하는 방법 - 상기 식별자는 상기 다수 네트워크 인터페이스 장치 내의 메모리 위치와 관련되고 (physical storage) , 상기 식별자와 관련 데이터 필드는 상기 제2 네트워크 인터페이스에 의해 수신될 수 있음 - 에 있어서 , 상기 제2 네트워크 인터페이스로부터 프로그램 컴포넌트로 메시지를 수신하는 단계 - 상기 메시지는 상기 제2 장치로부터의 상기 식별자의 수신을 표시함 - ;
상기 제1 네트워크 인터페이스에 쿼리(query)하여 상기 프로그램 컴포넌트에 상기 제1 네트워크 인터페이스에 의해 생성된 식별자들의 리스트 및 다수 네트워크 인터페이스 장치 메모리 내의 관련 메모리 위치를 공급하는 단계 ;
및 상기 식별자와 관련된 메모리 위치를 상기 제2 네트워크 인터페이스로 송신하는 단계 - 상기 제2 네트워크 인터페이스는 상기 식별자와 관련된 상기 메모리 위치에 상기 관련 데이터 필드를 송신할 수 있음 - 를 포함하는 방법 .

US9632727B2
CLAIM 10
. The system of claim 7 , further comprising means for indicating that data stored on the particular physical storage (관련되고) block can be erased from the solid-state storage medium .
KR20050009685A
CLAIM 1
다수 네트워크 인터페이스 장치에서 , 제1 네트워크 인터페이스가 제1 네트워크 인터페이스에 의해 생성된 식별자를 제2 장치에 송신한 후 , 상기 제1 네트워크 인터페이스 및 적어도 제2 네트워크 인터페이스 사이의 제어를 전송하는 방법 - 상기 식별자는 상기 다수 네트워크 인터페이스 장치 내의 메모리 위치와 관련되고 (physical storage) , 상기 식별자와 관련 데이터 필드는 상기 제2 네트워크 인터페이스에 의해 수신될 수 있음 - 에 있어서 , 상기 제2 네트워크 인터페이스로부터 프로그램 컴포넌트로 메시지를 수신하는 단계 - 상기 메시지는 상기 제2 장치로부터의 상기 식별자의 수신을 표시함 - ;
상기 제1 네트워크 인터페이스에 쿼리(query)하여 상기 프로그램 컴포넌트에 상기 제1 네트워크 인터페이스에 의해 생성된 식별자들의 리스트 및 다수 네트워크 인터페이스 장치 메모리 내의 관련 메모리 위치를 공급하는 단계 ;
및 상기 식별자와 관련된 메모리 위치를 상기 제2 네트워크 인터페이스로 송신하는 단계 - 상기 제2 네트워크 인터페이스는 상기 식별자와 관련된 상기 메모리 위치에 상기 관련 데이터 필드를 송신할 수 있음 - 를 포함하는 방법 .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
CN1771495A

Filed: 2004-05-06     Issued: 2006-05-10

分布式文件服务体系结构系统

(Original Assignee) 国际商业机器公司     

理查德·V·基斯利, 菲利普·D·奈特
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller (保持存储) configured to implement storage operations (的操作) on the solid state storage medium in response to requests from a computer system , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
CN1771495A
CLAIM 10
. 如权利要求9所述的主机,其中所述RDMA传输层通过保持存储 (state storage controller, storage controller) 器地址映射直到数据服务器的RDMA传输地址被验证为止来验证存储器存取。

CN1771495A
CLAIM 28
. 如权利要求24所述的数据服务器,其中所述处理器利用主机处的操作 (storage operations) 系统的最小处理开销,直接在主机的存储器地址和至少一个存储装置之间传送由所接收的输入/输出操作细节涉及的文件-块数据。

US9632727B2
CLAIM 3
. The apparatus of claim 1 , wherein the indexer assigns logical addresses to physical addresses by use of index metadata (相关联的数据) maintained in a memory of the storage controller (保持存储) .
CN1771495A
CLAIM 1
. 一种主机,包括:用于在其上运行应用程序的中央处理单元;用于在其中存储数据的存储器;以及耦合至所述存储器的主机总线适配器,所述主机总线适配器包括适配器处理器,其被设置为用于向元数据服务器发布输入/输出请求,并且用于允许直接在存储器和数据服务器之间进行与所述输入/输出请求相关联的数据 (index metadata) 的直接存储器存取传送。

CN1771495A
CLAIM 10
. 如权利要求9所述的主机,其中所述RDMA传输层通过保持存储 (state storage controller, storage controller) 器地址映射直到数据服务器的RDMA传输地址被验证为止来验证存储器存取。

US9632727B2
CLAIM 4
. The apparatus of claim 1 , wherein the indexer comprises firmware of the solid-state storage controller (保持存储) .
CN1771495A
CLAIM 10
. 如权利要求9所述的主机,其中所述RDMA传输层通过保持存储 (state storage controller, storage controller) 器地址映射直到数据服务器的RDMA传输地址被验证为止来验证存储器存取。

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller (保持存储) comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (体系结构) (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface (DMA传送) , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
CN1771495A
CLAIM 10
. 如权利要求9所述的主机,其中所述RDMA传输层通过保持存储 (state storage controller, storage controller) 器地址映射直到数据服务器的RDMA传输地址被验证为止来验证存储器存取。

CN1771495A
CLAIM 13
. 如权利要求1所述的主机,还包括智能RDMA部件,用于控制文件-块数据在主机存储器和存储装置之间的RDMA传送 (external SATA bus interface)

CN1771495A
CLAIM 30
. 一种可由计算机读取的程序存储装置,所述介质有形地包含可由计算机执行的一个或多个指令程序,以便执行用于在具有元数据存储虚拟化的分布式文件服务体系结构 (Integrated Drive Electronics) 中以数据服务器连接速度进行数据存取的方法,所述方法包括如下步骤:向元数据服务器发布输入/输出请求;以及直接在所述存储器和数据服务器之间传送与输入/输出请求相关联的数据。

US9632727B2
CLAIM 8
. The system of claim 7 , further comprising means for providing a storage interface to accept requests to perform storage operations (的操作) on the solid-state storage medium in reference to the logical blocks and to accept the message identifying the logical block that is not being used to reference data stored on the solid-state storage medium .
CN1771495A
CLAIM 28
. 如权利要求24所述的数据服务器,其中所述处理器利用主机处的操作 (storage operations) 系统的最小处理开销,直接在主机的存储器地址和至少一个存储装置之间传送由所接收的输入/输出操作细节涉及的文件-块数据。

US9632727B2
CLAIM 16
. The system of claim 15 , wherein data bits of the predetermined data string have a uniform logic (逻辑单元) level .
CN1771495A
CLAIM 26
. 如权利要求24所述的数据服务器,其中所述处理器还包括存储控制器,用于作为逻辑单元 (uniform logic) 号来给出至少一个存储装置,并且用于通过处理主机的存储器地址和至少一个存储装置之间的文件-块数据来满足所述输入/输出请求。




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
WO2004099989A2

Filed: 2004-05-06     Issued: 2004-11-18

Distributed file serving architecture system

(Original Assignee) International Business Machines Corporation; Ibm United Kingdom Limited     

Richard Victor Kisley, Philip Douglas Knight
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller (storage controller) configured to implement storage operations on the solid state storage medium in response to requests from a computer system , including storing data (storing data) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
WO2004099989A2
CLAIM 1
. A host , comprising : a central processing unit for running an application thereon ;
memory for storing data (storing data) therein ;
and a host bus adapter , coupled to the memory , the host bus adapter including an adapter processor configured for issuing an input/output request to a metadata server and for enabling direct memory access transfer of data associated with the input/output request directly between the memory and a data server .

WO2004099989A2
CLAIM 26
. The data server of claim 24 , wherein the processor further comprises a storage controller (storage controller) for presenting the at least one storage device as logical unit numbers and for satisfying the input/output request by processing file-block data between the memory address of the host and the at least one storage device .

US9632727B2
CLAIM 3
. The apparatus of claim 1 , wherein the indexer assigns logical addresses to physical addresses by use of index metadata maintained in a memory of the storage controller (storage controller) .
WO2004099989A2
CLAIM 26
. The data server of claim 24 , wherein the processor further comprises a storage controller (storage controller) for presenting the at least one storage device as logical unit numbers and for satisfying the input/output request by processing file-block data between the memory address of the host and the at least one storage device .

US9632727B2
CLAIM 4
. The apparatus of claim 1 , wherein the indexer comprises firmware of the solid-state storage controller (storage controller) .
WO2004099989A2
CLAIM 26
. The data server of claim 24 , wherein the processor further comprises a storage controller (storage controller) for presenting the at least one storage device as logical unit numbers and for satisfying the input/output request by processing file-block data between the memory address of the host and the at least one storage device .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller (storage controller) comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA (DMA transfer) bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface (central processing unit, logical unit number) , and a Fibre Channel interface (central processing unit, logical unit number) .
WO2004099989A2
CLAIM 1
. A host , comprising : a central processing unit (internet SCSI interface, Fibre Channel interface) for running an application thereon ;
memory for storing data therein ;
and a host bus adapter , coupled to the memory , the host bus adapter including an adapter processor configured for issuing an input/output request to a metadata server and for enabling direct memory access transfer of data associated with the input/output request directly between the memory and a data server .

WO2004099989A2
CLAIM 13
. The host of claim 1 further comprising an intelligent RDMA component for controlling the RDMA transfer (external SATA, external SATA bus interface) of file-block data between the memory of the host and the storage device .

WO2004099989A2
CLAIM 26
. The data server of claim 24 , wherein the processor further comprises a storage controller (storage controller) for presenting the at least one storage device as logical unit number (internet SCSI interface, Fibre Channel interface) s and for satisfying the input/output request by processing file-block data between the memory address of the host and the at least one storage device .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (storing data) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client (access request) that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
WO2004099989A2
CLAIM 1
. A host , comprising : a central processing unit for running an application thereon ;
memory for storing data (storing data) therein ;
and a host bus adapter , coupled to the memory , the host bus adapter including an adapter processor configured for issuing an input/output request to a metadata server and for enabling direct memory access transfer of data associated with the input/output request directly between the memory and a data server .

WO2004099989A2
CLAIM 12
. The host of claim 1 , wherein the input/output request comprises a file access request (storage client, storage interface to accept requests to perform storage operations) with data target locations .

US9632727B2
CLAIM 8
. The system of claim 7 , further comprising means for providing a storage interface to accept requests to perform storage operations (access request) on the solid-state storage medium in reference to the logical blocks and to accept the message identifying the logical block that is not being used to reference data stored on the solid-state storage medium .
WO2004099989A2
CLAIM 12
. The host of claim 1 , wherein the input/output request comprises a file access request (storage client, storage interface to accept requests to perform storage operations) with data target locations .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client (access request) ;

a storage processor coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
WO2004099989A2
CLAIM 12
. The host of claim 1 , wherein the input/output request comprises a file access request (storage client, storage interface to accept requests to perform storage operations) with data target locations .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer (remote direct memory access) is configured such that , responsive to receiving a read request (n information) specifying one or more logical addresses included in the empty-block directive command , the storage processor returns a predetermined data string .
WO2004099989A2
CLAIM 6
. The host of claim 1 , wherein the adapter processor is further configured for receiving data block location information (read request) from the metadata server in response to issuing the input/output request .

WO2004099989A2
CLAIM 33
. A program storage device readable by a computer , the medium tangibly embodying one or more programs of instructions executable by the computer to perform a method for providing a distributed file serving architecture with metadata storage virtualization and data access at data server connection speed , the method comprising : issuing from a host a file access request including data target locations ;
processing the file access request including data target locations ;
issuing a remote direct memory access (storage processer) channel endpoint connection in response to the processing the file access request including data target locations ;
and transferring file-block data associated with the file access request directly between a memory at the host and a data server .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
EP1465203A1

Filed: 2004-03-30     Issued: 2004-10-06

Nonvolatile memory with page copy capability and method thereof

(Original Assignee) Samsung Electronics Co Ltd     (Current Assignee) Samsung Electronics Co Ltd

Jin-Yub Lee
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system , including storing data (storing data) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data (store data) pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
EP1465203A1
CLAIM 1
A nonvolatile memory comprising : a plurality of pages storing data (storing data) ;
a page buffer temporarily storing data by the page ;
a correction circuit for correct a bit error of source data of a specific one of the pages ;
a transferring circuit configured to provide the source data to the correction circuit and to provide amended data to the page buffer from the correction circuit ;
and a replicating circuit configured to copy the source data into the page buffer and to store the amended data into another page from the page buffer .

EP1465203A1
CLAIM 15
A method of transferring source data of a specific page to another page in a nonvolatile memory having a page buffer structured to temporarily store data (store data, storage client) by the page , the source data containing old parities , the method comprising : storing the source data into the page buffer ;
generating new parities from the source data stored in the page buffer ;
comparing the old parities with the new parities ;
creating modified data from the source data in response to a result of the comparing ;
and moving the modified data to the another page through the page buffer .

US9632727B2
CLAIM 2
. The apparatus of claim 1 , wherein the indexer assigns logical addresses to physical addresses by use of index entries , and wherein the indexer removes an index entry (d line) corresponding to the identified logical address in response to the message .
EP1465203A1
CLAIM 7
The nonvolatile memory of claim 5 or 6 , wherein the second parities comprise column parities and line (index entry) parities .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (storing data) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client (store data) that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
EP1465203A1
CLAIM 1
A nonvolatile memory comprising : a plurality of pages storing data (storing data) ;
a page buffer temporarily storing data by the page ;
a correction circuit for correct a bit error of source data of a specific one of the pages ;
a transferring circuit configured to provide the source data to the correction circuit and to provide amended data to the page buffer from the correction circuit ;
and a replicating circuit configured to copy the source data into the page buffer and to store the amended data into another page from the page buffer .

EP1465203A1
CLAIM 15
A method of transferring source data of a specific page to another page in a nonvolatile memory having a page buffer structured to temporarily store data (store data, storage client) by the page , the source data containing old parities , the method comprising : storing the source data into the page buffer ;
generating new parities from the source data stored in the page buffer ;
comparing the old parities with the new parities ;
creating modified data from the source data in response to a result of the comparing ;
and moving the modified data to the another page through the page buffer .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client (store data) ;

a storage processor (data store) coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
EP1465203A1
CLAIM 5
A nonvolatile memory comprising : a data field composed of a plurality of pages for storing data ;
a first storage configured to store first parities in a predetermined region of the data field , the first parities being generated during a programming operation for the page ;
a page buffer for temporarily storing data by the page ;
a moving circuit configured to copy source data store (storage processor) d in a specific one of the pages into the page buffer ;
a parity circuit configured to generate second parities from the source data stored in the page buffer ;
and a transfer circuit configured to transfer modified data of the source data to the page buffer in response to a result of comparing the first parities with the second parities .

EP1465203A1
CLAIM 15
A method of transferring source data of a specific page to another page in a nonvolatile memory having a page buffer structured to temporarily store data (store data, storage client) by the page , the source data containing old parities , the method comprising : storing the source data into the page buffer ;
generating new parities from the source data stored in the page buffer ;
comparing the old parities with the new parities ;
creating modified data from the source data in response to a result of the comparing ;
and moving the modified data to the another page through the page buffer .

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (data store) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
EP1465203A1
CLAIM 5
A nonvolatile memory comprising : a data field composed of a plurality of pages for storing data ;
a first storage configured to store first parities in a predetermined region of the data field , the first parities being generated during a programming operation for the page ;
a page buffer for temporarily storing data by the page ;
a moving circuit configured to copy source data store (storage processor) d in a specific one of the pages into the page buffer ;
a parity circuit configured to generate second parities from the source data stored in the page buffer ;
and a transfer circuit configured to transfer modified data of the source data to the page buffer in response to a result of comparing the first parities with the second parities .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor (data store) returns a predetermined data string .
EP1465203A1
CLAIM 5
A nonvolatile memory comprising : a data field composed of a plurality of pages for storing data ;
a first storage configured to store first parities in a predetermined region of the data field , the first parities being generated during a programming operation for the page ;
a page buffer for temporarily storing data by the page ;
a moving circuit configured to copy source data store (storage processor) d in a specific one of the pages into the page buffer ;
a parity circuit configured to generate second parities from the source data stored in the page buffer ;
and a transfer circuit configured to transfer modified data of the source data to the page buffer in response to a result of comparing the first parities with the second parities .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
JP2005223753A

Filed: 2004-02-06     Issued: 2005-08-18

移動体通信用ネットワークのモビリティ管理方法及びハンドオーバ制御方法

(Original Assignee) Nippon Telegr & Teleph Corp <Ntt>; 日本電信電話株式会社     

Katsu Iwashita, Takeshi Kinoshita, Masahiro Kobayashi, Tomoko Miyano, とも子 宮野, 正啓 小林, 克 岩下, 健史 木下
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system (行うこと) , including storing data (タイミング) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
JP2005223753A
CLAIM 3
移動端末と、前記移動端末にネットワークヘの接続手段を与えるアクセスポイントと、フィルタリングデータベースを備え、前記フィルタリングデータベースの検索結果とフレームに含まれるレイヤ2情報とに基づいて、前記フレームを適切なポートに転送するレイヤ2スイッチとから成る移動体通信用ネットワークのモビリティ管理方法において、 相互に接続されたレイヤ2スイッチ間においては、双方向又は片方向に、ある時間間隔で自身のフィルタリングデータベースの必要な部分の情報を伝送し、 前記移動端末が前記アクセスポイントとの間の無線リンクを新たに確立した場合は、新たなアクセスポイントから、それが接続されたレイヤ2スイッチにその事実を伝送し、 前記レイヤ2スイッチにおいては、前記事実の確認を契機として、前記移動端末に一意に関連付けられるが、無線リンクでの通信には用いられないレイヤ2ラベルに係わるフィルタリングデータベースの更新を行うこと (computer system) によって、前記移動端末にユーザフレームを転送するポートを把握することを特徴とするモビリティ管理方法。

JP2005223753A
CLAIM 6
移動端末と、前記移動端末にネットワークヘの接続手段を与えるアクセスポイントと、フィルタリングデータベースを備え、前記フィルタリングデータベースの検索結果とフレームに含まれるレイヤ2情報とに基づいて、前記フレームを適切なポートに転送するレイヤ2スイッチとから成る移動体通信用ネットワークのハンドオーバ制御方法において、 上位にあるレイヤ2スイッチは、自身の保有するフィルタリングデータベースにおける移動端末のレイヤ2情報に関連するデータを利用することにより、前記移動端末が新しいアクセスポイントに無線リンクを切り替えるべきタイミング (storing data) と、次に前記動端末の通信に使用すべきポートを把握し、 前記レイヤ2スイッチが自身の下位にあるレイヤ2スイッチだけでは次に起こる切り替えの処理を完了できないと判断した場合は、その時点において、前記移動端末の通信に使用しているポートから、下位にあるレイヤ2スイッチと1つ上位にあるレイヤ2スイッチに向けて切り替え処理開始指示を出力し、 前記レイヤ2スイッチと同一階層に属し、かつ次に使用されるべきポートを有する他のレイヤ2スイッチに、これら2つの当該レイヤ2スイッチ間を結ぶ横方向リンクを介して切り替え予告を伝送し、 新しい無線リンクが確立した事実を、新しく前記移動端末の通信に使用されるいくつかのレイヤ2スイッチのポートと、上記横方向リンクの両端のポートを順次経由して、最初に切り替え開始処理を出力したレイヤ2スイッチと、その1つ上位にあるレイヤ2スイッチに達するまで転送することを特徴とする移動体通信用ネットワークのハンドオーバ制御方法。

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system (行うこと) , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
JP2005223753A
CLAIM 3
移動端末と、前記移動端末にネットワークヘの接続手段を与えるアクセスポイントと、フィルタリングデータベースを備え、前記フィルタリングデータベースの検索結果とフレームに含まれるレイヤ2情報とに基づいて、前記フレームを適切なポートに転送するレイヤ2スイッチとから成る移動体通信用ネットワークのモビリティ管理方法において、 相互に接続されたレイヤ2スイッチ間においては、双方向又は片方向に、ある時間間隔で自身のフィルタリングデータベースの必要な部分の情報を伝送し、 前記移動端末が前記アクセスポイントとの間の無線リンクを新たに確立した場合は、新たなアクセスポイントから、それが接続されたレイヤ2スイッチにその事実を伝送し、 前記レイヤ2スイッチにおいては、前記事実の確認を契機として、前記移動端末に一意に関連付けられるが、無線リンクでの通信には用いられないレイヤ2ラベルに係わるフィルタリングデータベースの更新を行うこと (computer system) によって、前記移動端末にユーザフレームを転送するポートを把握することを特徴とするモビリティ管理方法。

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (タイミング) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
JP2005223753A
CLAIM 6
移動端末と、前記移動端末にネットワークヘの接続手段を与えるアクセスポイントと、フィルタリングデータベースを備え、前記フィルタリングデータベースの検索結果とフレームに含まれるレイヤ2情報とに基づいて、前記フレームを適切なポートに転送するレイヤ2スイッチとから成る移動体通信用ネットワークのハンドオーバ制御方法において、 上位にあるレイヤ2スイッチは、自身の保有するフィルタリングデータベースにおける移動端末のレイヤ2情報に関連するデータを利用することにより、前記移動端末が新しいアクセスポイントに無線リンクを切り替えるべきタイミング (storing data) と、次に前記動端末の通信に使用すべきポートを把握し、 前記レイヤ2スイッチが自身の下位にあるレイヤ2スイッチだけでは次に起こる切り替えの処理を完了できないと判断した場合は、その時点において、前記移動端末の通信に使用しているポートから、下位にあるレイヤ2スイッチと1つ上位にあるレイヤ2スイッチに向けて切り替え処理開始指示を出力し、 前記レイヤ2スイッチと同一階層に属し、かつ次に使用されるべきポートを有する他のレイヤ2スイッチに、これら2つの当該レイヤ2スイッチ間を結ぶ横方向リンクを介して切り替え予告を伝送し、 新しい無線リンクが確立した事実を、新しく前記移動端末の通信に使用されるいくつかのレイヤ2スイッチのポートと、上記横方向リンクの両端のポートを順次経由して、最初に切り替え開始処理を出力したレイヤ2スイッチと、その1つ上位にあるレイヤ2スイッチに達するまで転送することを特徴とする移動体通信用ネットワークのハンドオーバ制御方法。

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor coupled to the storage interface ;

a flash memory device (アドレス) coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
JP2005223753A
CLAIM 1
移動端末と、前記移動端末にネットワークヘの接続手段を与えるアクセスポイントと、フィルタリングデータベースを備え、前記フィルタリングデータベースの検索結果とフレームに含まれるレイヤ2情報とに基づいて、前記フレームを適切なポートに転送するレイヤ2スイッチとから成る移動体通信用ネットワークのモビリティ管理方法において、 相互に接続されたレイヤ2スイッチ間において、双方向又は片方向に、ある時間間隔で自身のフィルタリングデータベースの必要な部分の情報を伝送し、 前記移動端末がアクセスポイントとの間の無線リンクを新たに確立した場合は、新たなアクセスポイントから、それが接続されたレイヤ2スイッチにその事実を伝送し、 前記事実を受信した前記レイヤ2スイッチは、前記事実の確認を契機として、前記移動端末固有の物理アドレス (flash memory device) に係わるフィルタリングデータベースの更新を行って、前記移動端末にユーザフレームを転送するポートを把握することを特徴とする移動体通信用ネットワークのモビリティ管理方法。

US9632727B2
CLAIM 13
. The system of claim 12 , wherein the logical-to-physical translation layer is stored in the flash memory device (アドレス) .
JP2005223753A
CLAIM 1
移動端末と、前記移動端末にネットワークヘの接続手段を与えるアクセスポイントと、フィルタリングデータベースを備え、前記フィルタリングデータベースの検索結果とフレームに含まれるレイヤ2情報とに基づいて、前記フレームを適切なポートに転送するレイヤ2スイッチとから成る移動体通信用ネットワークのモビリティ管理方法において、 相互に接続されたレイヤ2スイッチ間において、双方向又は片方向に、ある時間間隔で自身のフィルタリングデータベースの必要な部分の情報を伝送し、 前記移動端末がアクセスポイントとの間の無線リンクを新たに確立した場合は、新たなアクセスポイントから、それが接続されたレイヤ2スイッチにその事実を伝送し、 前記事実を受信した前記レイヤ2スイッチは、前記事実の確認を契機として、前記移動端末固有の物理アドレス (flash memory device) に係わるフィルタリングデータベースの更新を行って、前記移動端末にユーザフレームを転送するポートを把握することを特徴とする移動体通信用ネットワークのモビリティ管理方法。




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
WO2004077214A2

Filed: 2004-01-29     Issued: 2004-09-10

System and method for scheduling server functions irrespective of server functionality

(Original Assignee) Vaman Technologies (R & D) Limited     

Vinayak K. Rao
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system , including storing data (said memory) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data (said memory) pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
WO2004077214A2
CLAIM 1
. A computing system for scheduling instructions based on availability and utilization of resources across disparate functional servers , comprising : a command analyzer to receive said instructions and determine the optimum sequence of execution of said instructions received ;
a resource analyzer to allocate said resources optimally for execution ;
and a memory store to maintain historical and progressive data of said resource utilization to predict said allocation of resources whereby said computing system optimizes scheduling of instructions based on results received from said command analyzer and said resource analyzer in combination with said memory (store data, storing data) store .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface (finite state) , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
WO2004077214A2
CLAIM 5
. The computing system as recited in claim 1 is implemented using a finite state (PCI Express bus interface) machine model wherein the application is capable of deciding its own functional flow based on the instructions received rather than the user or the programmer by executing relevant functions dynamically as dictated by said kernel without having to traverse through unnecessary validation code .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (said memory) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
WO2004077214A2
CLAIM 1
. A computing system for scheduling instructions based on availability and utilization of resources across disparate functional servers , comprising : a command analyzer to receive said instructions and determine the optimum sequence of execution of said instructions received ;
a resource analyzer to allocate said resources optimally for execution ;
and a memory store to maintain historical and progressive data of said resource utilization to predict said allocation of resources whereby said computing system optimizes scheduling of instructions based on results received from said command analyzer and said resource analyzer in combination with said memory (store data, storing data) store .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
EP1418502A2

Filed: 2003-10-28     Issued: 2004-05-12

Unusable block management within a non-volatile memory system

(Original Assignee) SanDisk Corp     (Current Assignee) SanDisk Technologies LLC

Robert C Chang, Bahman Qawami, Farshid Sabet-Sharghi
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system , including storing data (store information) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
EP1418502A2
CLAIM 43
A method for managing blocks within a non-volatile memory system , the method comprising : determining when a first physical block within a non-volatile memory of the non-volatile memory system has a factory defect ;
storing a first signature in a data structure associated with the non-volatile memory which identifies the first physical block as having the factory defect when it is determined that the first physical block has the factory defect ;
substantially preventing the first physical block from being used to store information (storing data) when it is determined that the first physical block has the factory defect ;
determining when a second physical block within the non-volatile memory has a growing defect ;
storing a second signature in the data structure which identifies the second physical block as having the growing defect when it is determined that the second physical block has the growing defect ;
and substantially preventing the second physical block from being used to store information when it is determined that the first physical block has the growing defect .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (store information) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
EP1418502A2
CLAIM 43
A method for managing blocks within a non-volatile memory system , the method comprising : determining when a first physical block within a non-volatile memory of the non-volatile memory system has a factory defect ;
storing a first signature in a data structure associated with the non-volatile memory which identifies the first physical block as having the factory defect when it is determined that the first physical block has the factory defect ;
substantially preventing the first physical block from being used to store information (storing data) when it is determined that the first physical block has the factory defect ;
determining when a second physical block within the non-volatile memory has a growing defect ;
storing a second signature in the data structure which identifies the second physical block as having the growing defect when it is determined that the second physical block has the growing defect ;
and substantially preventing the second physical block from being used to store information when it is determined that the first physical block has the growing defect .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor coupled to the storage interface ;

a flash memory device (storage elements) coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
EP1418502A2
CLAIM 9
A method of managing unusable physical storage elements (flash memory device) within a non-volatile memory , the method comprising : determining when a first physical storage element is identified as being defective ;
substantially removing the first physical storage element from a pool of usable physical storage elements when it is determined that the first physical storage element is defective ;
and storing a first signature into a data structure in the non-volatile memory , the first signature being arranged to identify the first physical storage element as being defective .

US9632727B2
CLAIM 13
. The system of claim 12 , wherein the logical-to-physical translation layer is stored in the flash memory device (storage elements) .
EP1418502A2
CLAIM 9
A method of managing unusable physical storage elements (flash memory device) within a non-volatile memory , the method comprising : determining when a first physical storage element is identified as being defective ;
substantially removing the first physical storage element from a pool of usable physical storage elements when it is determined that the first physical storage element is defective ;
and storing a first signature into a data structure in the non-volatile memory , the first signature being arranged to identify the first physical storage element as being defective .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
CN1701309A

Filed: 2003-09-10     Issued: 2005-11-23

非易失性存储系统中的损耗平衡

(Original Assignee) 桑迪士克股份有限公司     

罗伯特·张, 巴赫曼·卡瓦迈, 法施德·萨伯特-沙吉
US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface (成多个) configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer (一个擦) System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
CN1701309A
CLAIM 1
. 一种用于分配非易失性存储器的方法,所述非易失性存储器基本上被划分成多个 (bus interface, PCI Express bus interface, bus interface comprises one) 元件,所述方法包括:将所述元件分组为至少一第一组、一第二组和一第三组,其中所述第一组包括具有相对低损耗的擦除元件且所述第二组包括具有相对高损耗的擦除元件;判定何时包括于所述第一组中的一第二元件基本上取代包括于所述第三组中的一第一元件;当判定所述第一元件将基本上被所述第二元件取代时,将与所述第一元件相关联的内容复制到从所述第一组获得的所述第二元件中;从所述第一元件中擦除所述第一元件的内容;和使所述第二元件与所述第三组产生关联,其中使所述第二元件与所述第三组产生关联包括基本上解除所述第一组与所述第二元件的关联。

CN1701309A
CLAIM 2
. 根据权利要求1所述的方法,其中将所述元件分为所述第一组、所述第二组和所述第三组包括基于与每个元件相关联的一个擦 (Small Computer) 除计数来分组所述元件。

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor coupled to the storage interface ;

a flash memory device (以访问) coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
CN1701309A
CLAIM 51
. 一种存储器管理系统,所述存储器管理系统经配置以管理非易失性存储元件的分配,所述存储器管理系统包括:用于将与一第一存储元件相关联的内容与经配置用以取代与所述第一存储元件相关联的所述内容的新内容之一复制到一第二存储元件中的代码装置,所述第二存储元件具有一个小于与所述第一存储元件相关联的一擦除计数的擦除计数,所述第二存储元件与一第一数据结构相关联,所述第一数据结构经配置含有一第一组存储元件;用于使所述第二存储元件与一第二数据结构产生关联的代码装置,所述第二数据结构经配置含有一第二组存储元件,其中用于使所述第二存储元件与所述第一数据结构产生关联的所述代码装置包括用于解除所述第一数据结构与所述第二存储元件的关联的代码装置;用于从所述第一存储元件中擦除与所述第一存储元件相关联的所述内容的代码装置;用于判定何时使所述第一存储元件与所述第一数据结构产生关联的代码装置;用于在判定所述第一存储元件将与所述第一数据结构产生关联时使所述第一存储元件与所述第一数据结构产生关联的代码装置,其中用于使所述第一存储元件与所述第一数据结构产生关联的所述代码装置包括用于解除所述第二数据结构与所述第一存储元件的关联的代码装置;用于在判定所述第一存储元件将不与所述第一数据结构产生关联时使所述第一存储元件与一第三数据结构产生关联的代码装置,所述第三数据结构经配置含有一第三组存储元件;一用于存储所述代码装置的存储器;和一经配置以访问 (flash memory device) 所述代码装置的处理器。

US9632727B2
CLAIM 13
. The system of claim 12 , wherein the logical-to-physical translation layer is stored in the flash memory device (以访问) .
CN1701309A
CLAIM 51
. 一种存储器管理系统,所述存储器管理系统经配置以管理非易失性存储元件的分配,所述存储器管理系统包括:用于将与一第一存储元件相关联的内容与经配置用以取代与所述第一存储元件相关联的所述内容的新内容之一复制到一第二存储元件中的代码装置,所述第二存储元件具有一个小于与所述第一存储元件相关联的一擦除计数的擦除计数,所述第二存储元件与一第一数据结构相关联,所述第一数据结构经配置含有一第一组存储元件;用于使所述第二存储元件与一第二数据结构产生关联的代码装置,所述第二数据结构经配置含有一第二组存储元件,其中用于使所述第二存储元件与所述第一数据结构产生关联的所述代码装置包括用于解除所述第一数据结构与所述第二存储元件的关联的代码装置;用于从所述第一存储元件中擦除与所述第一存储元件相关联的所述内容的代码装置;用于判定何时使所述第一存储元件与所述第一数据结构产生关联的代码装置;用于在判定所述第一存储元件将与所述第一数据结构产生关联时使所述第一存储元件与所述第一数据结构产生关联的代码装置,其中用于使所述第一存储元件与所述第一数据结构产生关联的所述代码装置包括用于解除所述第二数据结构与所述第一存储元件的关联的代码装置;用于在判定所述第一存储元件将不与所述第一数据结构产生关联时使所述第一存储元件与一第三数据结构产生关联的代码装置,所述第三数据结构经配置含有一第三组存储元件;一用于存储所述代码装置的存储器;和一经配置以访问 (flash memory device) 所述代码装置的处理器。




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
WO2004040459A1

Filed: 2003-09-10     Issued: 2004-05-13

Tracking the least frequently erased blocks in non-volatile memory systems

(Original Assignee) Sandisk Corporation     

Robert C. Chang, Bahman Qawami, Farshid Sabet-Sharghi
US9632727B2
CLAIM 5
. The apparatus of claim 1 , further comprising a garbage collector (nonvolatile memory, memory management) configured to designate that the physical address previously assigned to the identified logical address comprises data suitable for removal from the solid-state storage medium in response to the message .
WO2004040459A1
CLAIM 34
. The memory system of claim 26 wherein the memory elements are nonvolatile memory (garbage collector) blocks .

WO2004040459A1
CLAIM 38
. A memory management (garbage collector) system comprising : code devices for obtaining erase counts associated with a plurality of elements , wherein each element included in the plurality of elements has an associated erase count , the associated erase count of each element being arranged to indicate a number of times the element has been erased ;
code devices for grouping a number of elements included in the plurality of elements into a first set , wherein the code devices for grouping the number of elements into the first set includes code devices for selecting erased elements included in the plurality of elements which have the lowest associated erase counts of the erase counts associated with the plurality of erased elements ;
and code devices for storing the erase counts associated with the first set substantially into a table in a memory component .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology (when i) Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface (system memory) , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
WO2004040459A1
CLAIM 19
. The method of claim 17 further including : determining when an associated erase count of a second element not included in is to be erased ;
removing the first element from the first set when i (Advanced Technology) t is determined that the second element is to be erased ;
copying one of contents of the second element and new contents to replace the contents of the second element into the first element ;
erasing the contents from the second element ;
and adding the second element to the first set .

WO2004040459A1
CLAIM 26
. A memory system comprising : memory elements ;
a system memory (PCI Express bus interface) component ;
means for identifying a first set of the erased memory elements , wherein the memory elements mcluded in the first set of memory elements are less worn than the erased memory elements not included in the first set of memory elements ;
means for placing entries associated with the first set of memory elements into a data structure associated with the system memory component ;
means for sorting the entries within the data structure ;
and means identifying a first memory element within the first set of memory elements using the sorted entries , wherein the first memory element is less worn than other erased memory elements included in the first set of memory elements .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor coupled to the storage interface ;

a flash memory device (storage elements) coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
WO2004040459A1
CLAIM 13
. A memory system comprising : a first memory , the first memory being arranged to store a table , the table being arranged to include entries associated with a first set of erased storage elements (flash memory device) which have associated erase counters that are less than an average erase count associated with the memory system , the associated erase counter for each storage element of the first set of storage elements being arranged to substantially indicate a number of times the storage element has been erased ;
a second memory , the second memory being arranged to include a plurality of erased storage elements , the plurality of storage elements including the first set of storage elements , wherein the average erase count is determined using erase counters associated with the plurality of storage elements ;
and a processor , the processor being arranged to access the first memory and the second memory .

US9632727B2
CLAIM 13
. The system of claim 12 , wherein the logical-to-physical translation layer is stored in the flash memory device (storage elements) .
WO2004040459A1
CLAIM 13
. A memory system comprising : a first memory , the first memory being arranged to store a table , the table being arranged to include entries associated with a first set of erased storage elements (flash memory device) which have associated erase counters that are less than an average erase count associated with the memory system , the associated erase counter for each storage element of the first set of storage elements being arranged to substantially indicate a number of times the storage element has been erased ;
a second memory , the second memory being arranged to include a plurality of erased storage elements , the plurality of storage elements including the first set of storage elements , wherein the average erase count is determined using erase counters associated with the plurality of storage elements ;
and a processor , the processor being arranged to access the first memory and the second memory .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
EP1552409A1

Filed: 2003-08-19     Issued: 2005-07-13

One-shot rdma

(Original Assignee) Broadcom Corp     (Current Assignee) Broadcom Corp

Uri Elzur, Scott S. Mcdaniel
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium (write operation) in response to requests from a computer system , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
EP1552409A1
CLAIM 24
. A method for transferring data over an RDMA network , comprising : initiating an RDMA write operation (solid state storage medium) using a one-shot initiation process between a driver and a NIC ;
inserting an STag value in a first field of a DDP or RDMA header of an RDMA send message ;
and validating the STag value in the first field with a bit flag or other specified value in a second field of the DDP or RDMA header .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface (own memory) configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface (own memory) , and a Fibre Channel interface .
EP1552409A1
CLAIM 3
. The system according to claim 2 , wherein the single command message comprises a command to describe pinned-down memory (bus interface, PCI Express bus interface, external SATA bus interface, internet SCSI interface, bus interface comprises one) buffers of the host .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client (send message) that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
EP1552409A1
CLAIM 24
. A method for transferring data over an RDMA network , comprising : initiating an RDMA write operation using a one-shot initiation process between a driver and a NIC ;
inserting an STag value in a first field of a DDP or RDMA header of an RDMA send message (storage client) ;
and validating the STag value in the first field with a bit flag or other specified value in a second field of the DDP or RDMA header .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client (send message) ;

a storage processor coupled to the storage interface ;

a flash memory device (interface card) coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
EP1552409A1
CLAIM 1
. A system for transferring data over a remote direct memory access (RDMA) network , comprising : a host comprising a driver and a network interface card (flash memory device) (NIC) , the driver being coupled to the NIC , wherein the driver and the NIC perform a one-shot initiation process of an RDMA operation .

EP1552409A1
CLAIM 24
. A method for transferring data over an RDMA network , comprising : initiating an RDMA write operation using a one-shot initiation process between a driver and a NIC ;
inserting an STag value in a first field of a DDP or RDMA header of an RDMA send message (storage client) ;
and validating the STag value in the first field with a bit flag or other specified value in a second field of the DDP or RDMA header .

US9632727B2
CLAIM 13
. The system of claim 12 , wherein the logical-to-physical translation layer is stored in the flash memory device (interface card) .
EP1552409A1
CLAIM 1
. A system for transferring data over a remote direct memory access (RDMA) network , comprising : a host comprising a driver and a network interface card (flash memory device) (NIC) , the driver being coupled to the NIC , wherein the driver and the NIC perform a one-shot initiation process of an RDMA operation .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer (remote direct memory access) is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor returns a predetermined data string .
EP1552409A1
CLAIM 1
. A system for transferring data over a remote direct memory access (storage processer) (RDMA) network , comprising : a host comprising a driver and a network interface card (NIC) , the driver being coupled to the NIC , wherein the driver and the NIC perform a one-shot initiation process of an RDMA operation .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
WO2004017220A1

Filed: 2003-08-19     Issued: 2004-02-26

One-shot rdma

(Original Assignee) Broadcom Corporation     

Scott S. Mcdaniel, Uri Elzur
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium (write operation) in response to requests from a computer system , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
WO2004017220A1
CLAIM 24
. A method for transferring data over an RDMA network , comprising : initiating an RDMA write operation (solid state storage medium) using a one-shot initiation process between a driver and a NIC ;
inserting an STag value in a first field of a DDP or RDMA header of an RDMA send message ;
and validating the STag value in the first field with a bit flag or other specified value in a second field of the DDP or RDMA header .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface (own memory) configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface (own memory) , and a Fibre Channel interface .
WO2004017220A1
CLAIM 3
. The system according to claim 2 , wherein the single command message comprises a command to describe pinned-down memory (bus interface, PCI Express bus interface, external SATA bus interface, internet SCSI interface, bus interface comprises one) buffers of the host .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client (send message) that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
WO2004017220A1
CLAIM 24
. A method for transferring data over an RDMA network , comprising : initiating an RDMA write operation using a one-shot initiation process between a driver and a NIC ;
inserting an STag value in a first field of a DDP or RDMA header of an RDMA send message (storage client) ;
and validating the STag value in the first field with a bit flag or other specified value in a second field of the DDP or RDMA header .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client (send message) ;

a storage processor coupled to the storage interface ;

a flash memory device (interface card) coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
WO2004017220A1
CLAIM 1
. A system for transferring data over a remote direct memory access (RDMA) network , comprising : a host comprising a driver and a network interface card (flash memory device) (NIC) , the driver being coupled to the NIC , wherein the driver and the NIC perform a one-shot initiation process of an RDMA operation .

WO2004017220A1
CLAIM 24
. A method for transferring data over an RDMA network , comprising : initiating an RDMA write operation using a one-shot initiation process between a driver and a NIC ;
inserting an STag value in a first field of a DDP or RDMA header of an RDMA send message (storage client) ;
and validating the STag value in the first field with a bit flag or other specified value in a second field of the DDP or RDMA header .

US9632727B2
CLAIM 13
. The system of claim 12 , wherein the logical-to-physical translation layer is stored in the flash memory device (interface card) .
WO2004017220A1
CLAIM 1
. A system for transferring data over a remote direct memory access (RDMA) network , comprising : a host comprising a driver and a network interface card (flash memory device) (NIC) , the driver being coupled to the NIC , wherein the driver and the NIC perform a one-shot initiation process of an RDMA operation .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer (remote direct memory access) is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor returns a predetermined data string .
WO2004017220A1
CLAIM 1
. A system for transferring data over a remote direct memory access (storage processer) (RDMA) network , comprising : a host comprising a driver and a network interface card (NIC) , the driver being coupled to the NIC , wherein the driver and the NIC perform a one-shot initiation process of an RDMA operation .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
EP1543422A1

Filed: 2003-08-05     Issued: 2005-06-22

Remote direct memory access enabled network interface controller switchover and switchback support

(Original Assignee) International Business Machines Corp     (Current Assignee) International Business Machines Corp

William Todd Boyd, Douglas Joseph, Michael Anthony Ko, Renato John Recio
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system (computer system) , including storing data (computer program) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
EP1543422A1
CLAIM 9
. A a computer program (storing data) comprising computer program code elements to , when loaded into a computer system (computer system) and executed thereon , cause said computer to perform the steps of a method according to any preceding claim .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system (computer system) , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
EP1543422A1
CLAIM 9
. A a computer program comprising computer program code elements to , when loaded into a computer system (computer system) and executed thereon , cause said computer to perform the steps of a method according to any preceding claim .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (computer program) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
EP1543422A1
CLAIM 9
. A a computer program (storing data) comprising computer program code elements to , when loaded into a computer system and executed thereon , cause said computer to perform the steps of a method according to any preceding claim .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
WO2004023305A1

Filed: 2003-08-05     Issued: 2004-03-18

Remote direct memory access enabled network interface controller switchover and switchback support

(Original Assignee) International Business Machines Corporation; Ibm United Kingdom Limited     

William Todd Boyd, Douglas Joseph, Michael Anthony Ko, Renato John Recio
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system (computer system) , including storing data (computer program) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
WO2004023305A1
CLAIM 9
. A a computer program (storing data) comprising computer program code elements to , when loaded into a computer system (computer system) and executed thereon , cause said computer to perform the steps of a method according to any preceding claim .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system (computer system) , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
WO2004023305A1
CLAIM 9
. A a computer program comprising computer program code elements to , when loaded into a computer system (computer system) and executed thereon , cause said computer to perform the steps of a method according to any preceding claim .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (computer program) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
WO2004023305A1
CLAIM 9
. A a computer program (storing data) comprising computer program code elements to , when loaded into a computer system and executed thereon , cause said computer to perform the steps of a method according to any preceding claim .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
EP1331548A2

Filed: 2003-01-17     Issued: 2003-07-30

File management of one-time-programmable non volatile memory devices

(Original Assignee) Lexar Media Inc     (Current Assignee) Lexar Media Inc

Petro Estakhri
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system , including storing data (storing information, said memory) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data (storing information, said memory) pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
EP1331548A2
CLAIM 1
A digital equipment system comprising : a . a host for sending commands to read or write files having sectors of information , each sector being modifiable on a bit-by-bit , byte-by-byte or word-by-word basis , said host being operative to receive responses to said commands ;
b . a controller device responsive to said commands , and including ,    one-time-programmable nonvolatile memory for storing information (store data, storing data) organized into sectors based on commands received from the host and upon receiving commands from the host to re-write a sector , the controller device being operable for re-writing said sector on a bit-by-bit , byte-by-byte or word-for-word basis .

EP1331548A2
CLAIM 20
A digital equipment system comprising : a . a host for sending commands to read or write files in portions corresponding to memory sectors , each sector being identifiable on a bit-by-bit , byte-by-byte or word-by-word basis , said host being operable for commanding to re-write a previously written sector ;
and b . a controller device responsive to the host commands and including , one-time-programmable non-volatile memory for storing information organized into sectors based on commands received from the host , said memory (store data, storing data) having stored therein the previously written sector and upon receiving a command from the host to re-write the previously written sector , the controller device being operable for performing partial programming of the previously written sector to write the sector to be re-written on a bit-by-bit , byte-by-byte or word-by-word basis .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface (new data) , and a Fibre Channel interface .
EP1331548A2
CLAIM 25
A memory system comprising : an interface for receiving commands from a host for the writing of data to and reading of data from the memory system ;
a one-time programmable memory having a data area divided into physical sectors ;
a control device responsive to the commands and comprising means for emulating a re-programmable memory whereby logical addresses available to the host are presented to the host as being mapped to re-writable virtual sectors in the emulated memory and are actually mapped to physical addresses in the physical sectors in the one-time-programmable memory ;
the control device comprising a comparator responsive to a command to rewrite a virtual sector with new data (internet SCSI interface) by comparing the new data with contents of a physical sector in which existing data for the virtual sector was previously programmed to identify portions of said new data which are different from the existing data ;
and partial programming means for programming only the identified portions of the new data into previously unprogrammed areas of the memory and for maintaining mapping of the logical addresses for the re-written virtual sector to locations in the memory containing the new data .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (storing information, said memory) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
EP1331548A2
CLAIM 1
A digital equipment system comprising : a . a host for sending commands to read or write files having sectors of information , each sector being modifiable on a bit-by-bit , byte-by-byte or word-by-word basis , said host being operative to receive responses to said commands ;
b . a controller device responsive to said commands , and including ,    one-time-programmable nonvolatile memory for storing information (store data, storing data) organized into sectors based on commands received from the host and upon receiving commands from the host to re-write a sector , the controller device being operable for re-writing said sector on a bit-by-bit , byte-by-byte or word-for-word basis .

EP1331548A2
CLAIM 20
A digital equipment system comprising : a . a host for sending commands to read or write files in portions corresponding to memory sectors , each sector being identifiable on a bit-by-bit , byte-by-byte or word-by-word basis , said host being operable for commanding to re-write a previously written sector ;
and b . a controller device responsive to the host commands and including , one-time-programmable non-volatile memory for storing information organized into sectors based on commands received from the host , said memory (store data, storing data) having stored therein the previously written sector and upon receiving a command from the host to re-write the previously written sector , the controller device being operable for performing partial programming of the previously written sector to write the sector to be re-written on a bit-by-bit , byte-by-byte or word-by-word basis .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
JP2004110436A

Filed: 2002-09-18     Issued: 2004-04-08

メモリのリード/ライト制御回路、無接点メモリカード、リード/ライト装置及び無接点メモリカードのリード/ライトシステム

(Original Assignee) Koatsu Gas Kogyo Co Ltd; Nippon Lsi Card Co Ltd; 日本エルエスアイカード株式会社; 高圧ガス工業株式会社     

Yoshio Iwahashi, Makoto Kimura, Kunji Nagano, Yasuhito Nakajima, Tatsuo Sakai, Hitoshi Tanaka, 中島 康仁, 岩橋 由雄, 木村 真琴, 永野 訓司, 田中 仁, 酒井 龍雄
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller (制御信号) configured to implement storage operations on the solid state storage medium in response to requests from a computer system , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
JP2004110436A
CLAIM 6
アドレスバスとデータバスとが共通化されているタイプのメモリが適応可能な請求項1又は2記載のメモリのリード/ライト制御回路において、 コントロールデータには、アドレスの設定、アドレスセット/データセットの設定、各種制御信号 (state storage controller, storage controller) の出力の有無の各選択(CSのクロック同期出力/常時出力の選択を含む)に関するコードが含まれており、加えて、アドレスセット設定時には、少なくともアドレスマスク有無の選択、アドレスセット数の選択、マスクアドレスの選択に関するコードが、データ設定時には、少なくともメモリ制御の設定、データの変化/固定の設定、R/B信号の主装置への転送の有無の選択に関するコードが含められていることを条件とし、 制御部は、レジスター回路上の各種データに含まれるコントロールデータにアドレスセットに関するコードを含んでいるときには、当該コンロールデータに含まれるアドレスの設定、アドレスマスク有無の選択、アドレスセット数の選択、マスクアドレスの選択及び各種制御信号の出力の有無の各選択(CSのクロック同期出力/常時出力の選択を含む)に関するコードに基づいてメモリに対してアドレスセットを行う一方、データセットに関するコードを含んでいるときには、当該コンロールデータに含まれるアドレスの設定、メモリ制御の設定、データの変化/固定の設定、各種制御信号の出力の有無の各選択(CSのクロック同期出力/常時出力の選択を含む)及びR/B信号の主装置への転送の有無の選択に関するコードに基づいてメモリに対してデータのリード/ライトを行う機能を有した構成となっていることを特徴とするメモリのリード/ライト制御回路。

US9632727B2
CLAIM 3
. The apparatus of claim 1 , wherein the indexer assigns logical addresses to physical addresses by use of index metadata maintained in a memory of the storage controller (制御信号) .
JP2004110436A
CLAIM 6
アドレスバスとデータバスとが共通化されているタイプのメモリが適応可能な請求項1又は2記載のメモリのリード/ライト制御回路において、 コントロールデータには、アドレスの設定、アドレスセット/データセットの設定、各種制御信号 (state storage controller, storage controller) の出力の有無の各選択(CSのクロック同期出力/常時出力の選択を含む)に関するコードが含まれており、加えて、アドレスセット設定時には、少なくともアドレスマスク有無の選択、アドレスセット数の選択、マスクアドレスの選択に関するコードが、データ設定時には、少なくともメモリ制御の設定、データの変化/固定の設定、R/B信号の主装置への転送の有無の選択に関するコードが含められていることを条件とし、 制御部は、レジスター回路上の各種データに含まれるコントロールデータにアドレスセットに関するコードを含んでいるときには、当該コンロールデータに含まれるアドレスの設定、アドレスマスク有無の選択、アドレスセット数の選択、マスクアドレスの選択及び各種制御信号の出力の有無の各選択(CSのクロック同期出力/常時出力の選択を含む)に関するコードに基づいてメモリに対してアドレスセットを行う一方、データセットに関するコードを含んでいるときには、当該コンロールデータに含まれるアドレスの設定、メモリ制御の設定、データの変化/固定の設定、各種制御信号の出力の有無の各選択(CSのクロック同期出力/常時出力の選択を含む)及びR/B信号の主装置への転送の有無の選択に関するコードに基づいてメモリに対してデータのリード/ライトを行う機能を有した構成となっていることを特徴とするメモリのリード/ライト制御回路。

US9632727B2
CLAIM 4
. The apparatus of claim 1 , wherein the indexer comprises firmware of the solid-state storage controller (制御信号) .
JP2004110436A
CLAIM 6
アドレスバスとデータバスとが共通化されているタイプのメモリが適応可能な請求項1又は2記載のメモリのリード/ライト制御回路において、 コントロールデータには、アドレスの設定、アドレスセット/データセットの設定、各種制御信号 (state storage controller, storage controller) の出力の有無の各選択(CSのクロック同期出力/常時出力の選択を含む)に関するコードが含まれており、加えて、アドレスセット設定時には、少なくともアドレスマスク有無の選択、アドレスセット数の選択、マスクアドレスの選択に関するコードが、データ設定時には、少なくともメモリ制御の設定、データの変化/固定の設定、R/B信号の主装置への転送の有無の選択に関するコードが含められていることを条件とし、 制御部は、レジスター回路上の各種データに含まれるコントロールデータにアドレスセットに関するコードを含んでいるときには、当該コンロールデータに含まれるアドレスの設定、アドレスマスク有無の選択、アドレスセット数の選択、マスクアドレスの選択及び各種制御信号の出力の有無の各選択(CSのクロック同期出力/常時出力の選択を含む)に関するコードに基づいてメモリに対してアドレスセットを行う一方、データセットに関するコードを含んでいるときには、当該コンロールデータに含まれるアドレスの設定、メモリ制御の設定、データの変化/固定の設定、各種制御信号の出力の有無の各選択(CSのクロック同期出力/常時出力の選択を含む)及びR/B信号の主装置への転送の有無の選択に関するコードに基づいてメモリに対してデータのリード/ライトを行う機能を有した構成となっていることを特徴とするメモリのリード/ライト制御回路。

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller (制御信号) comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
JP2004110436A
CLAIM 6
アドレスバスとデータバスとが共通化されているタイプのメモリが適応可能な請求項1又は2記載のメモリのリード/ライト制御回路において、 コントロールデータには、アドレスの設定、アドレスセット/データセットの設定、各種制御信号 (state storage controller, storage controller) の出力の有無の各選択(CSのクロック同期出力/常時出力の選択を含む)に関するコードが含まれており、加えて、アドレスセット設定時には、少なくともアドレスマスク有無の選択、アドレスセット数の選択、マスクアドレスの選択に関するコードが、データ設定時には、少なくともメモリ制御の設定、データの変化/固定の設定、R/B信号の主装置への転送の有無の選択に関するコードが含められていることを条件とし、 制御部は、レジスター回路上の各種データに含まれるコントロールデータにアドレスセットに関するコードを含んでいるときには、当該コンロールデータに含まれるアドレスの設定、アドレスマスク有無の選択、アドレスセット数の選択、マスクアドレスの選択及び各種制御信号の出力の有無の各選択(CSのクロック同期出力/常時出力の選択を含む)に関するコードに基づいてメモリに対してアドレスセットを行う一方、データセットに関するコードを含んでいるときには、当該コンロールデータに含まれるアドレスの設定、メモリ制御の設定、データの変化/固定の設定、各種制御信号の出力の有無の各選択(CSのクロック同期出力/常時出力の選択を含む)及びR/B信号の主装置への転送の有無の選択に関するコードに基づいてメモリに対してデータのリード/ライトを行う機能を有した構成となっていることを特徴とするメモリのリード/ライト制御回路。

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor returns a predetermined data string (アクティブ) .
JP2004110436A
CLAIM 7
多種類のメモリが適応可能な請求項1又は2記載のメモリのリード/ライト制御回路において、 適応可能なメモリのうち使用するメモリの種類を設定入力するためのモード切り替え回路と、メモリの種類を設定に基づいて当該メモリの属性を示すデータを生成するアトリビュート入力回路を備えており、 コントロールデータには、少なくともアドレスの設定、データの変化/固定の設定及びメモリ制御の設定以外に各種制御信号の出力の有無の各選択及びメモリの属性を示すデータの主装置への転送の有無の選択に関するコードが含められていることを条件とし、 制御部は、レジスター回路上のコントロールデータに各種制御信号の出力に関するコードを含んでいるときには、前記メモリに出力すべき当該制御信号をアクティブ (data string) にする一方、コントロールデータにメモリの属性を示すデータの主装置への転送に関するコードを含んでいるときには、アトリビュート入力回路にて生成されたデータを主装置に転送させる機能を有した構成となっていることを特徴とするメモリのリード/ライト制御回路。

US9632727B2
CLAIM 16
. The system of claim 15 , wherein data bits (クロック) of the predetermined data string (アクティブ) have a uniform logic level .
JP2004110436A
CLAIM 6
アドレスバスとデータバスとが共通化されているタイプのメモリが適応可能な請求項1又は2記載のメモリのリード/ライト制御回路において、 コントロールデータには、アドレスの設定、アドレスセット/データセットの設定、各種制御信号の出力の有無の各選択(CSのクロック (data bits) 同期出力/常時出力の選択を含む)に関するコードが含まれており、加えて、アドレスセット設定時には、少なくともアドレスマスク有無の選択、アドレスセット数の選択、マスクアドレスの選択に関するコードが、データ設定時には、少なくともメモリ制御の設定、データの変化/固定の設定、R/B信号の主装置への転送の有無の選択に関するコードが含められていることを条件とし、 制御部は、レジスター回路上の各種データに含まれるコントロールデータにアドレスセットに関するコードを含んでいるときには、当該コンロールデータに含まれるアドレスの設定、アドレスマスク有無の選択、アドレスセット数の選択、マスクアドレスの選択及び各種制御信号の出力の有無の各選択(CSのクロック同期出力/常時出力の選択を含む)に関するコードに基づいてメモリに対してアドレスセットを行う一方、データセットに関するコードを含んでいるときには、当該コンロールデータに含まれるアドレスの設定、メモリ制御の設定、データの変化/固定の設定、各種制御信号の出力の有無の各選択(CSのクロック同期出力/常時出力の選択を含む)及びR/B信号の主装置への転送の有無の選択に関するコードに基づいてメモリに対してデータのリード/ライトを行う機能を有した構成となっていることを特徴とするメモリのリード/ライト制御回路。

JP2004110436A
CLAIM 7
多種類のメモリが適応可能な請求項1又は2記載のメモリのリード/ライト制御回路において、 適応可能なメモリのうち使用するメモリの種類を設定入力するためのモード切り替え回路と、メモリの種類を設定に基づいて当該メモリの属性を示すデータを生成するアトリビュート入力回路を備えており、 コントロールデータには、少なくともアドレスの設定、データの変化/固定の設定及びメモリ制御の設定以外に各種制御信号の出力の有無の各選択及びメモリの属性を示すデータの主装置への転送の有無の選択に関するコードが含められていることを条件とし、 制御部は、レジスター回路上のコントロールデータに各種制御信号の出力に関するコードを含んでいるときには、前記メモリに出力すべき当該制御信号をアクティブ (data string) にする一方、コントロールデータにメモリの属性を示すデータの主装置への転送に関するコードを含んでいるときには、アトリビュート入力回路にて生成されたデータを主装置に転送させる機能を有した構成となっていることを特徴とするメモリのリード/ライト制御回路。




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
EP1271332A2

Filed: 2002-03-26     Issued: 2003-01-02

A multifunction semiconductor storage device and a method for booting-up computer host

(Original Assignee) Netac Tech Co Ltd     (Current Assignee) Netac Tech Co Ltd

Xiaohua Cheng, Guoshun 6A Blk. 2 Jindicuiyuan No. 5 Deng, Feng Xiang
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium (boot program, hard disk) in response to requests from a computer system , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
EP1271332A2
CLAIM 11
A multifunction semiconductor storage device as claimed in claim 10 , wherein said storage disk can be a simulated floppy disk drive and floppy diskette , a simulated CD-ROM drive and a CD-ROM , a simulated hard disk (state storage system, state storage medium, storage processer) , a simulate ZIP disk , a simulated MO disk , or a customized storage disk .

EP1271332A2
CLAIM 15
A method for booting up computer using the multifunction semiconductor storage device , comprising the steps of : storing the boot program (state storage system, state storage medium, storage processer) of the operating system and operating system programs into the multifunction semiconductor storage device ;
connecting the multifunction semiconductor storage device with the computer host system through the general-purpose interface ;
identifying the general purpose interface , and controlling and reading/writing the multifunction semiconductor storage device based on BIOS after powered up the computer host system ;
and loading the boot program of the operating system and operating system programs stored in the multifunction semiconductor storage device to computer host system for achieving computer boot-up .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (LED power) (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA (computer host, host system) bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
EP1271332A2
CLAIM 1
A multifunction semiconductor storage device capable of hot plug and play and being removable connected to the host system (external SATA, external SATA bus interface) through the general purpose interface , including a semiconductor storage media module (1) and a controller module (2) , wherein the controller module (2) comprises a general purpose interface control module (21) , a microprocessor and control module (22) , said semiconductor storage device can realize the device class protocol of the floppy disk drive , simulate and implement the storing function of the floppy diskette working on the floppy disk drive , or realize the device class protocol of the CD-ROM drive , simulate and implement the storing function of the CD-ROM working on the CD-ROM drive , or realize the device class protocol of the ZIP disk , simulate and implement the storing function of the ZIP disk , or realize the device class protocol of the MO disk , simulate and implement the storing function of the MO disk .

EP1271332A2
CLAIM 6
A multifunction semiconductor storage device as claimed in claim 1 , wherein further includes a LED indicator (5) comprising one or a plurality of indicator devices which can show the status of the semiconductor storage device , said LED power (Integrated Drive Electronics) indicator (5) is electrically connected to the microprocessor and control module (22) electrically .

EP1271332A2
CLAIM 15
A method for booting up computer using the multifunction semiconductor storage device , comprising the steps of : storing the boot program of the operating system and operating system programs into the multifunction semiconductor storage device ;
connecting the multifunction semiconductor storage device with the computer host (external SATA, external SATA bus interface) system through the general-purpose interface ;
identifying the general purpose interface , and controlling and reading/writing the multifunction semiconductor storage device based on BIOS after powered up the computer host system ;
and loading the boot program of the operating system and operating system programs stored in the multifunction semiconductor storage device to computer host system for achieving computer boot-up .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer (boot program, hard disk) is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor returns a predetermined data string .
EP1271332A2
CLAIM 11
A multifunction semiconductor storage device as claimed in claim 10 , wherein said storage disk can be a simulated floppy disk drive and floppy diskette , a simulated CD-ROM drive and a CD-ROM , a simulated hard disk (state storage system, state storage medium, storage processer) , a simulate ZIP disk , a simulated MO disk , or a customized storage disk .

EP1271332A2
CLAIM 15
A method for booting up computer using the multifunction semiconductor storage device , comprising the steps of : storing the boot program (state storage system, state storage medium, storage processer) of the operating system and operating system programs into the multifunction semiconductor storage device ;
connecting the multifunction semiconductor storage device with the computer host system through the general-purpose interface ;
identifying the general purpose interface , and controlling and reading/writing the multifunction semiconductor storage device based on BIOS after powered up the computer host system ;
and loading the boot program of the operating system and operating system programs stored in the multifunction semiconductor storage device to computer host system for achieving computer boot-up .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
KR20030040817A

Filed: 2001-11-16     Issued: 2003-05-23

플래시 메모리 관리방법

(Original Assignee) 삼성전자주식회사     

백창규
US9632727B2
CLAIM 2
. The apparatus of claim 1 , wherein the indexer assigns logical addresses to physical addresses by use of index entries (테이블의) , and wherein the indexer removes an index entry corresponding to the identified logical address in response to the message .
KR20030040817A
CLAIM 16
플래시 메모리를 관리하는 방법에 있어서 , (a) 상기 플래시 메모리에 저장되며 논리 주소와 물리 주소의 매핑 정보가 저장된 주소 변환 테이블의 (index entries) 변경사항을 메인 메모리에 마련된 정정 테이블에 기록하는 단계 ;
(b) 정정 테이블의 소정 부분이 다 채워졌는지 확인하는 단계 ;
(c) 다 채워진 경우 상기 정정 테이블에 기록된 변경사항을 상기 주소 변환 테이블에 반영하는 단계 ;
및 (d) 상기 정정 테이블에 기록된 내용 중 상기 주소 변환 테이블에 반영된 부분을 삭제하는 단계를 포함하는 것을 특징으로 하는 관리방법 .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor coupled to the storage interface ;

a flash memory device (스캐닝) coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
KR20030040817A
CLAIM 1
플래시 메모리를 관리하는 방법에 있어서 , (a) 상기 플래시 메모리의 데이터 영역에 기록된 데이터의 논리 주소를 대응 스패어 영역에 기록하는 단계 ;
및 (b) 상기 스패어 영역에 기록된 정보를 스캐닝 (flash memory device) 하여 주소 변환 테이블(mapping table)을 생성하는 단계를 포함하는 것을 특징으로 하는 관리방법 .

US9632727B2
CLAIM 13
. The system of claim 12 , wherein the logical-to-physical translation layer is stored in the flash memory device (스캐닝) .
KR20030040817A
CLAIM 1
플래시 메모리를 관리하는 방법에 있어서 , (a) 상기 플래시 메모리의 데이터 영역에 기록된 데이터의 논리 주소를 대응 스패어 영역에 기록하는 단계 ;
및 (b) 상기 스패어 영역에 기록된 정보를 스캐닝 (flash memory device) 하여 주소 변환 테이블(mapping table)을 생성하는 단계를 포함하는 것을 특징으로 하는 관리방법 .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request (사항을) specifying one or more logical addresses included in the empty-block directive command , the storage processor returns a predetermined data string .
KR20030040817A
CLAIM 16
플래시 메모리를 관리하는 방법에 있어서 , (a) 상기 플래시 메모리에 저장되며 논리 주소와 물리 주소의 매핑 정보가 저장된 주소 변환 테이블의 변경사항을 (read request) 메인 메모리에 마련된 정정 테이블에 기록하는 단계 ;
(b) 정정 테이블의 소정 부분이 다 채워졌는지 확인하는 단계 ;
(c) 다 채워진 경우 상기 정정 테이블에 기록된 변경사항을 상기 주소 변환 테이블에 반영하는 단계 ;
및 (d) 상기 정정 테이블에 기록된 내용 중 상기 주소 변환 테이블에 반영된 부분을 삭제하는 단계를 포함하는 것을 특징으로 하는 관리방법 .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
EP1280047A2

Filed: 2001-09-28     Issued: 2003-01-29

A storage system having a plurality of controllers

(Original Assignee) Hitachi Ltd     (Current Assignee) Hitachi Ltd

Naoto Hitachi Ltd. Int. Prop. Group Matsunami, Ikuya Hitachi Ltd. Int. Prop. Group Yagisawa, Manabu Hitachi Ltd. Int. Prop. Group Kitamura, Yoshiki Hitachi Ltd. Int. Prop. Group Kano, Kenichi Hitachi Ltd. Int. Prop. Group Takamoto
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system (computer system) , including storing data (storing data) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data (storing information) pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
EP1280047A2
CLAIM 2
A storage system according to claim 1 , wherein each of said disk controller and said file server comprises a memory for storing information (store data) for accessing a disk drive unit , which allocated respectively to the disk controller and file server , in said plurality of disk drive units .

EP1280047A2
CLAIM 15
A computer system (computer system) comprising : a first computer having a block I/O interface ;
a second computer having a file I/O interface ;
and a storage system connected to said first and second computers and having a plurality of disk drive units for storing data (storing data) used by said first and second computers , said storage system comprising a disk controller connected to said first computer via a Storage Area Network , a file server connected to said second computer via a LAN , a connection unit for connecting said disk controller and said file server to said plurality of disk drive units ;
and a management unit for managing allocation of said plurality of disk drive units to said disk controller and said file server .

US9632727B2
CLAIM 2
. The apparatus of claim 1 , wherein the indexer assigns logical addresses to physical addresses by use of index entries (storage pool) , and wherein the indexer removes an index entry corresponding to the identified logical address in response to the message .
EP1280047A2
CLAIM 7
A storage system according to claim 1 further comprising a management unit for managing a storage pool (index entries) , which is formed by said plurality of disk drive units , and being connected through a network to said disk controllers and said file servers .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system (computer system) , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
EP1280047A2
CLAIM 15
A computer system (computer system) comprising : a first computer having a block I/O interface ;
a second computer having a file I/O interface ;
and a storage system connected to said first and second computers and having a plurality of disk drive units for storing data used by said first and second computers , said storage system comprising a disk controller connected to said first computer via a Storage Area Network , a file server connected to said second computer via a LAN , a connection unit for connecting said disk controller and said file server to said plurality of disk drive units ;
and a management unit for managing allocation of said plurality of disk drive units to said disk controller and said file server .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (storing data) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client (access request) that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
EP1280047A2
CLAIM 15
A computer system comprising : a first computer having a block I/O interface ;
a second computer having a file I/O interface ;
and a storage system connected to said first and second computers and having a plurality of disk drive units for storing data (storing data) used by said first and second computers , said storage system comprising a disk controller connected to said first computer via a Storage Area Network , a file server connected to said second computer via a LAN , a connection unit for connecting said disk controller and said file server to said plurality of disk drive units ;
and a management unit for managing allocation of said plurality of disk drive units to said disk controller and said file server .

EP1280047A2
CLAIM 16
A storage system comprising : a plurality of disk drive units ;
and a controller for processing access request (storage client, storage interface to accept requests to perform storage operations) s from a computer for data stored on said plurality of disk drive units , and having a memory for storing information for accessing those of said plurality of disk drive units allocated to the controller .

US9632727B2
CLAIM 8
. The system of claim 7 , further comprising means for providing a storage interface to accept requests to perform storage operations (access request) on the solid-state storage medium in reference to the logical blocks and to accept the message identifying the logical block that is not being used to reference data stored on the solid-state storage medium .
EP1280047A2
CLAIM 16
A storage system comprising : a plurality of disk drive units ;
and a controller for processing access request (storage client, storage interface to accept requests to perform storage operations) s from a computer for data stored on said plurality of disk drive units , and having a memory for storing information for accessing those of said plurality of disk drive units allocated to the controller .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client (access request) ;

a storage processor (data store) coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
EP1280047A2
CLAIM 16
A storage system comprising : a plurality of disk drive units ;
and a controller for processing access request (storage client, storage interface to accept requests to perform storage operations) s from a computer for data store (storage processor) d on said plurality of disk drive units , and having a memory for storing information for accessing those of said plurality of disk drive units allocated to the controller .

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (data store) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
EP1280047A2
CLAIM 16
A storage system comprising : a plurality of disk drive units ;
and a controller for processing access requests from a computer for data store (storage processor) d on said plurality of disk drive units , and having a memory for storing information for accessing those of said plurality of disk drive units allocated to the controller .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor (data store) returns a predetermined data string .
EP1280047A2
CLAIM 16
A storage system comprising : a plurality of disk drive units ;
and a controller for processing access requests from a computer for data store (storage processor) d on said plurality of disk drive units , and having a memory for storing information for accessing those of said plurality of disk drive units allocated to the controller .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
JP2003036204A

Filed: 2001-07-23     Issued: 2003-02-07

フラッシュ型メモリの更新方法

(Original Assignee) Matsushita Electric Ind Co Ltd; 松下電器産業株式会社     

Yasutsugu Toyoda, 泰嗣 豊田
US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor (メモリ) coupled to the storage interface ;

a flash memory device (アドレス) coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
JP2003036204A
CLAIM 1
【請求項1】 記憶内容を更新する場合、セクタ単位で 消去/書き込みを行う方法で、消去/書き込みか空きセ クタへの追記を判断する手段と、更新する記憶内容をセ クタ単位で分割する手段と、記憶内容を無効にしたセク タから記憶内容を更新したセクタへリンクする手段を備 えるフラッシュ型メモリ (storage processor) の更新方法。

JP2003036204A
CLAIM 2
【請求項2】 請求項1の更新方法であって、記憶内容 を無効にするセクタ有効フラグを有し、無効にしたセク タから更新した記憶内容へリンクする手段としてセクタ リンクアドレス (flash memory device) を有することを特徴とするフラッシュ型 メモリの更新方法。

US9632727B2
CLAIM 13
. The system of claim 12 , wherein the logical-to-physical translation layer is stored in the flash memory device (アドレス) .
JP2003036204A
CLAIM 2
【請求項2】 請求項1の更新方法であって、記憶内容 を無効にするセクタ有効フラグを有し、無効にしたセク タから更新した記憶内容へリンクする手段としてセクタ リンクアドレス (flash memory device) を有することを特徴とするフラッシュ型 メモリの更新方法。

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (メモリ) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
JP2003036204A
CLAIM 1
【請求項1】 記憶内容を更新する場合、セクタ単位で 消去/書き込みを行う方法で、消去/書き込みか空きセ クタへの追記を判断する手段と、更新する記憶内容をセ クタ単位で分割する手段と、記憶内容を無効にしたセク タから記憶内容を更新したセクタへリンクする手段を備 えるフラッシュ型メモリ (storage processor) の更新方法。

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor (メモリ) returns a predetermined data string .
JP2003036204A
CLAIM 1
【請求項1】 記憶内容を更新する場合、セクタ単位で 消去/書き込みを行う方法で、消去/書き込みか空きセ クタへの追記を判断する手段と、更新する記憶内容をセ クタ単位で分割する手段と、記憶内容を無効にしたセク タから記憶内容を更新したセクタへリンクする手段を備 えるフラッシュ型メモリ (storage processor) の更新方法。




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
EP1299800A2

Filed: 2001-05-21     Issued: 2003-04-09

System and method for migrating processes on a network

(Original Assignee) Sun Microsystems Inc     (Current Assignee) Sun Microsystems Inc

Robert Rodriquez, Thomas E. Saulpaugh, Gregory L. Slaughter
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations (virtual machines) on the solid state (more states) storage medium in response to requests from a computer system , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
EP1299800A2
CLAIM 17
. The method of claim 16 , wherein the first virtual machine and the second virtual machine are Java virtual machines (storage operations) .

EP1299800A2
CLAIM 25
. A system for migrating a process between devices , the system comprising : a first device configured to execute the process ;
a memory coupled to the first device , wherein the memory comprises a persistent store ;
and a second device ;
wherein the system is configured to : store one or more states (solid state) ofthe process execution on the first device in the persistent store ;
send a first state ofthe process from the persistent store to the second device ;
receive on the second device the sent first state ofthe process from the first device ;
reconstitute the received first state ofthe process on the second device ;
establish one or more leases to services for the process on the second device ;
and resume the process execution on the second device .

US9632727B2
CLAIM 4
. The apparatus of claim 1 , wherein the indexer comprises firmware (system code) of the solid-state storage controller .
EP1299800A2
CLAIM 7
. The method of claim 1 , wherein the one or more leases to services include one or more leases to system services , wherein a system service comprises system code (indexer comprises firmware) for accessing a resource external to the process , wherein the system code is provided on the device within which the process is cuπently executing .

US9632727B2
CLAIM 8
. The system of claim 7 , further comprising means for providing a storage interface to accept requests to perform storage operations (virtual machines) on the solid-state storage medium in reference to the logical blocks and to accept the message identifying the logical block that is not being used to reference data stored on the solid-state storage medium .
EP1299800A2
CLAIM 17
. The method of claim 16 , wherein the first virtual machine and the second virtual machine are Java virtual machines (storage operations) .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
EP1100001A2

Filed: 2000-10-18     Issued: 2001-05-16

Storage system supporting file-level and block-level accesses

(Original Assignee) Sun Microsystems Inc     (Current Assignee) Sun Microsystems Inc

Yousef A. Khalidi
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system (computer system) , including storing data (storing data) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
EP1100001A2
CLAIM 1
A method for servicing access requests directed to a storage system (120) within a computer system (computer system) , comprising : if the storage system is operating in a first mode of operation , receiving (504) a file system access (401) at the storage system , translating (506) the file system access into a first block-level access (409) , and forwarding (508) the first block-level access to a storage device (130) within the storage system ;
if the storage system is operating in a second mode of operation , receiving 9510) a second block-level access (404) at the storage system , and forwarding (518) the second block-level access to the storage device (130) .

EP1100001A2
CLAIM 15
An apparatus for storing data (storing data) for a computer system (102 ;
103 ;
104) , comprising : a storage system (120) ;
a first communication channel (108 ;
109 ;
110) that couples the storage system to the computer system ;
a storage device within the storage system , including a non-volatile storage medium ;
a second communication channel that couples the storage system to the storage device ;
and a controller (122 ;
123) within the storage system coupled between the first communication channel and the second communication channel , for co-ordinating operation of the storage system ;
wherein during a first mode of operation , the controller is configured to , receive (504) a file system access (401) at the storage system , translate (506) the file system access into a first block-level access (409) , forward (508) the first block-level access to the storage device ;
wherein during a second mode of operation , the controller is configured to , receive (510) a second block-level access (409) at the storage system , and forward (518) the second block-level access to the storage device .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system (computer system) , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface (fiber channel) , and a Fibre Channel interface (fiber channel) .
EP1100001A2
CLAIM 1
A method for servicing access requests directed to a storage system (120) within a computer system (computer system) , comprising : if the storage system is operating in a first mode of operation , receiving (504) a file system access (401) at the storage system , translating (506) the file system access into a first block-level access (409) , and forwarding (508) the first block-level access to a storage device (130) within the storage system ;
if the storage system is operating in a second mode of operation , receiving 9510) a second block-level access (404) at the storage system , and forwarding (518) the second block-level access to the storage device (130) .

EP1100001A2
CLAIM 4
The method of claim 3 , wherein the communication channel conforms to the fiber channel (internet SCSI interface, Fibre Channel interface) standard .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (storing data) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client (access request) that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
EP1100001A2
CLAIM 1
A method for servicing access request (storage client, storage interface to accept requests to perform storage operations) s directed to a storage system (120) within a computer system , comprising : if the storage system is operating in a first mode of operation , receiving (504) a file system access (401) at the storage system , translating (506) the file system access into a first block-level access (409) , and forwarding (508) the first block-level access to a storage device (130) within the storage system ;
if the storage system is operating in a second mode of operation , receiving 9510) a second block-level access (404) at the storage system , and forwarding (518) the second block-level access to the storage device (130) .

EP1100001A2
CLAIM 15
An apparatus for storing data (storing data) for a computer system (102 ;
103 ;
104) , comprising : a storage system (120) ;
a first communication channel (108 ;
109 ;
110) that couples the storage system to the computer system ;
a storage device within the storage system , including a non-volatile storage medium ;
a second communication channel that couples the storage system to the storage device ;
and a controller (122 ;
123) within the storage system coupled between the first communication channel and the second communication channel , for co-ordinating operation of the storage system ;
wherein during a first mode of operation , the controller is configured to , receive (504) a file system access (401) at the storage system , translate (506) the file system access into a first block-level access (409) , forward (508) the first block-level access to the storage device ;
wherein during a second mode of operation , the controller is configured to , receive (510) a second block-level access (409) at the storage system , and forward (518) the second block-level access to the storage device .

US9632727B2
CLAIM 8
. The system of claim 7 , further comprising means for providing a storage interface to accept requests to perform storage operations (access request) on the solid-state storage medium in reference to the logical blocks and to accept the message identifying the logical block that is not being used to reference data stored on the solid-state storage medium .
EP1100001A2
CLAIM 1
A method for servicing access request (storage client, storage interface to accept requests to perform storage operations) s directed to a storage system (120) within a computer system , comprising : if the storage system is operating in a first mode of operation , receiving (504) a file system access (401) at the storage system , translating (506) the file system access into a first block-level access (409) , and forwarding (508) the first block-level access to a storage device (130) within the storage system ;
if the storage system is operating in a second mode of operation , receiving 9510) a second block-level access (404) at the storage system , and forwarding (518) the second block-level access to the storage device (130) .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client (access request) ;

a storage processor coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
EP1100001A2
CLAIM 1
A method for servicing access request (storage client, storage interface to accept requests to perform storage operations) s directed to a storage system (120) within a computer system , comprising : if the storage system is operating in a first mode of operation , receiving (504) a file system access (401) at the storage system , translating (506) the file system access into a first block-level access (409) , and forwarding (508) the first block-level access to a storage device (130) within the storage system ;
if the storage system is operating in a second mode of operation , receiving 9510) a second block-level access (404) at the storage system , and forwarding (518) the second block-level access to the storage device (130) .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
JP2000242434A

Filed: 1999-12-03     Issued: 2000-09-08

記憶装置システム

(Original Assignee) Hitachi Ltd; 株式会社日立製作所     

Yasuyuki Ajimatsu, Naoto Matsunami, Takashi Oeda, Masahiko Sato, Akira Yamamoto, 雅彦 佐藤, 康行 味松, 高 大枝, 山本  彰, 直人 松並
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations (オペレータ) on the solid state storage medium in response to requests from a computer system (前記スイッチ) , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
JP2000242434A
CLAIM 5
【請求項5】前記記憶装置システムは、さらに、前記転 送手段に接続し、オペレータ (storage operations) から記憶装置システムの構 成を定義する構成情報の入力を受け付け、該入力に応答 して、各ノードの前記構成管理テーブルに前記構成情報 を設定する管理プロセッサを有することを特徴とする請 求項1記載の記憶装置システム。

JP2000242434A
CLAIM 15
【請求項15】前記スイッチ (computer system) 装置は、さらに、前記転送 手段に接続し、オペレータから該スイッチ装置及び前記 複数の記憶装置サブシステムを含んで構成される記憶装 置システムの構成を定義する構成情報の入力を受け付 け、該入力に応答して、各ノードの構成管理テーブルに 前記構成情報を設定する管理プロセッサを有することを 特徴とする請求項11記載のスイッチ装置。

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system (前記スイッチ) , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
JP2000242434A
CLAIM 15
【請求項15】前記スイッチ (computer system) 装置は、さらに、前記転送 手段に接続し、オペレータから該スイッチ装置及び前記 複数の記憶装置サブシステムを含んで構成される記憶装 置システムの構成を定義する構成情報の入力を受け付 け、該入力に応答して、各ノードの構成管理テーブルに 前記構成情報を設定する管理プロセッサを有することを 特徴とする請求項11記載のスイッチ装置。

US9632727B2
CLAIM 8
. The system of claim 7 , further comprising means for providing a storage interface to accept requests to perform storage operations (オペレータ) on the solid-state storage medium in reference to the logical blocks and to accept the message identifying the logical block that is not being used to reference data stored on the solid-state storage medium .
JP2000242434A
CLAIM 5
【請求項5】前記記憶装置システムは、さらに、前記転 送手段に接続し、オペレータ (storage operations) から記憶装置システムの構 成を定義する構成情報の入力を受け付け、該入力に応答 して、各ノードの前記構成管理テーブルに前記構成情報 を設定する管理プロセッサを有することを特徴とする請 求項1記載の記憶装置システム。

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one (する情報) or more logical addresses included in the empty-block directive command , the storage processor returns a predetermined data string .
JP2000242434A
CLAIM 6
【請求項6】前記構成情報は、前記計算機から前記複数 の記憶装置サブシステムへのアクセスを制限する情報 (read request specifying one) を 含むことを特徴とする請求項5記載の記憶装置システ ム。

US9632727B2
CLAIM 16
. The system of claim 15 , wherein data bits of the predetermined data string have a uniform logic (論理アドレス) level .
JP2000242434A
CLAIM 4
【請求項4】前記フレームは、前記データ実体部に、前 記計算機により認識されている第1の論理アドレス (uniform logic) 情報 を含み、前記変換手段は、前記構成管理テーブルに保持 された前記構成情報に基づいて、前記第1の論理アドレ ス情報を、該フレームの転送先となる記憶装置サブシス テム内で管理される第2の論理アドレスに変換すること を特徴とする請求項3記載の記憶装置システム。




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
WO9828685A1

Filed: 1997-12-15     Issued: 1998-07-02

Coordinating shared access to common storage

(Original Assignee) Symbios, Inc.     

Rodney A. Dekoning, Gerald J. Fredin
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system (computer system) , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data (associating one) pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
WO9828685A1
CLAIM 5
. The method of claim 4 wherein said primary control module is associated with at least one semaphore and wherein the step of awaiting availability includes the steps of : determining that none of said at least one semaphore is associated with said portion of said common shared LUN ;
associating one (store data) of said at least one semaphore with said portion in response to the determination none of said at least one semaphore is associated with said portion ;
and locking the semaphore associated with said portion .

WO9828685A1
CLAIM 16
. In a system including a plurality of storage control modules connected to a common shared set of storage devices in a storage subsystem , a method operable within said plurality of storage control modules for processing I/O requests directed to said common shared set of storage devices comprising the steps of : receiving a plurality of I/O requests from attached host computer system (computer system) s ;
and processing each of said plurality of I/O requests substantially in parallel within distinct control modules of said plurality of storage control modules .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system (computer system) , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
WO9828685A1
CLAIM 16
. In a system including a plurality of storage control modules connected to a common shared set of storage devices in a storage subsystem , a method operable within said plurality of storage control modules for processing I/O requests directed to said common shared set of storage devices comprising the steps of : receiving a plurality of I/O requests from attached host computer system (computer system) s ;
and processing each of said plurality of I/O requests substantially in parallel within distinct control modules of said plurality of storage control modules .

US9632727B2
CLAIM 8
. The system of claim 7 , further comprising means for providing a storage interface (designating one) to accept requests to perform storage operations on the solid-state storage medium in reference to the logical blocks and to accept the message identifying the logical block that is not being used to reference data stored on the solid-state storage medium .
WO9828685A1
CLAIM 1
. In a system including a plurality of RAID control modules connected to a common shared LUN in a RAID storage subsystem , a method operable within said plurality of RAID control modules for coordinating exclusive access by said plurality of control modules to said common shared LUN comprising the steps of : designating one (storage interface) of said plurality of RAID control modules as a primary control module ;
and exchanging access coordination messages between said primary control module and others of said plurality of RAID control modules to coordinate temporary exclusive access by one of said plurality of RAID control modules to said common shared LUN .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface (designating one) configured to communicate with a storage client ;

a storage processor coupled to the storage interface ;

a flash memory device (storage subsystem) coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
WO9828685A1
CLAIM 1
. In a system including a plurality of RAID control modules connected to a common shared LUN in a RAID storage subsystem (flash memory device) , a method operable within said plurality of RAID control modules for coordinating exclusive access by said plurality of control modules to said common shared LUN comprising the steps of : designating one (storage interface) of said plurality of RAID control modules as a primary control module ;
and exchanging access coordination messages between said primary control module and others of said plurality of RAID control modules to coordinate temporary exclusive access by one of said plurality of RAID control modules to said common shared LUN .

US9632727B2
CLAIM 13
. The system of claim 12 , wherein the logical-to-physical translation layer is stored in the flash memory device (storage subsystem) .
WO9828685A1
CLAIM 1
. In a system including a plurality of RAID control modules connected to a common shared LUN in a RAID storage subsystem (flash memory device) , a method operable within said plurality of RAID control modules for coordinating exclusive access by said plurality of control modules to said common shared LUN comprising the steps of : designating one of said plurality of RAID control modules as a primary control module ;
and exchanging access coordination messages between said primary control module and others of said plurality of RAID control modules to coordinate temporary exclusive access by one of said plurality of RAID control modules to said common shared LUN .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
JPH113290A

Filed: 1997-06-11     Issued: 1999-01-06

メモリ制御方式

(Original Assignee) Hitachi Ltd; 株式会社日立製作所     

Yoshiaki Hisada, Mitsuhiro Kato, Takashi Moriyama, 義明 久田, 充博 加藤, 隆志 森山
US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor (メモリ) coupled to the storage interface ;

a flash memory device (アドレス) coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
JPH113290A
CLAIM 1
【請求項1】メモリ (storage processor) と、ECC制御機能付きメモリコン トローラを有するシステムにおいて、ある一定単位のメ モリ領域において発生した1ビットエラーを数える機能 と、上記エラー数があるしきい値を越えたことを判定 し、しきい値を越えた場合OSに知らせる機能と、上記 OSに、1ビットエラーが発生した場合、該エラーアド レスを取得し、さらに該エラーアドレス (flash memory device) を含む一定のメ モリ領域の全内容を、メモリの他の空き領域にコピー し、コピーが終了したら、当該単位メモリは未使用とす る機能を追加したことを特徴とするメモリ制御方式。

US9632727B2
CLAIM 13
. The system of claim 12 , wherein the logical-to-physical translation layer is stored in the flash memory device (アドレス) .
JPH113290A
CLAIM 1
【請求項1】メモリと、ECC制御機能付きメモリコン トローラを有するシステムにおいて、ある一定単位のメ モリ領域において発生した1ビットエラーを数える機能 と、上記エラー数があるしきい値を越えたことを判定 し、しきい値を越えた場合OSに知らせる機能と、上記 OSに、1ビットエラーが発生した場合、該エラーアド レスを取得し、さらに該エラーアドレス (flash memory device) を含む一定のメ モリ領域の全内容を、メモリの他の空き領域にコピー し、コピーが終了したら、当該単位メモリは未使用とす る機能を追加したことを特徴とするメモリ制御方式。

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (メモリ) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
JPH113290A
CLAIM 1
【請求項1】メモリ (storage processor) と、ECC制御機能付きメモリコン トローラを有するシステムにおいて、ある一定単位のメ モリ領域において発生した1ビットエラーを数える機能 と、上記エラー数があるしきい値を越えたことを判定 し、しきい値を越えた場合OSに知らせる機能と、上記 OSに、1ビットエラーが発生した場合、該エラーアド レスを取得し、さらに該エラーアドレスを含む一定のメ モリ領域の全内容を、メモリの他の空き領域にコピー し、コピーが終了したら、当該単位メモリは未使用とす る機能を追加したことを特徴とするメモリ制御方式。

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor (メモリ) returns a predetermined data string .
JPH113290A
CLAIM 1
【請求項1】メモリ (storage processor) と、ECC制御機能付きメモリコン トローラを有するシステムにおいて、ある一定単位のメ モリ領域において発生した1ビットエラーを数える機能 と、上記エラー数があるしきい値を越えたことを判定 し、しきい値を越えた場合OSに知らせる機能と、上記 OSに、1ビットエラーが発生した場合、該エラーアド レスを取得し、さらに該エラーアドレスを含む一定のメ モリ領域の全内容を、メモリの他の空き領域にコピー し、コピーが終了したら、当該単位メモリは未使用とす る機能を追加したことを特徴とするメモリ制御方式。

US9632727B2
CLAIM 16
. The system of claim 15 , wherein data bits (1ビット) of the predetermined data string have a uniform logic level .
JPH113290A
CLAIM 1
【請求項1】メモリと、ECC制御機能付きメモリコン トローラを有するシステムにおいて、ある一定単位のメ モリ領域において発生した1ビット (data bits) エラーを数える機能 と、上記エラー数があるしきい値を越えたことを判定 し、しきい値を越えた場合OSに知らせる機能と、上記 OSに、1ビットエラーが発生した場合、該エラーアド レスを取得し、さらに該エラーアドレスを含む一定のメ モリ領域の全内容を、メモリの他の空き領域にコピー し、コピーが終了したら、当該単位メモリは未使用とす る機能を追加したことを特徴とするメモリ制御方式。




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
WO9838568A1

Filed: 1997-05-28     Issued: 1998-09-03

Transformational raid for hierarchical storage management system

(Original Assignee) International Business Machines Corporation     

David Alan Styczinski
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium (hard disk) in response to requests from a computer system (computer system) , including storing data (storing data, said memory) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data (storing data, said memory) pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
WO9838568A1
CLAIM 7
. The method for converting a first memory structure to a second memory structure of claim 1 , wherein said data storage devices are rotating magnetic hard disk (state storage medium, state storage system, storage processer) drives .

WO9838568A1
CLAIM 9
. The data storage system of claim 8 , wherein said programmable processor is contained in a controller for attaching to a host computer system (computer system) , said controller including a random access memory for containing said status information .

WO9838568A1
CLAIM 16
. A controller for controlling a data storage system , said data storage system having a plurality of data storage devices for storing data (storing data, store data) , said controller comprising : a programmable processor for controlling the operation of said plurality of data storage devices , said programmable processor executing a control program for converting a first memory structure stored on said plurality of storage devices to a second memory structure stored on said plurality of storage devices ;
and a random access memory for containing status information maintained by said control program ;
wherein said control program , in response to identification of a set of blocks of data to be converted , each block of said set to be converted being stored on a different respective one of said plurality of data storage devices , said set comprising a plurality of pairs of blocks , both blocks of each respective pair containing identical data , (a) updates said status information to designate a first block of said set of blocks as a parity block , and (b) updates said status information to designate a respective block from each pair of blocks of said set which does not include said first block as available for storage of replacement data .

WO9838568A1
CLAIM 24
. A data storage system , comprising : a plurality of data storage devices ;
a programmable processor for controlling the operation of said plurality of data storage devices , said programmable processor executing a control program for controlling the operation of said data storage system ;
wherein data in said plurality of data storage devices is organized into a plurality of sets of blocks , each block of a set being stored on a different respective one of said plurality of data storage devices ;
wherein said control program supports formatting of said sets of blocks according to a plurality of different memory structures , at least one of said memory (storing data, store data) structures being a redundant data format , a first set of blocks and a second set of blocks being formattable independently of each other ;
and a random access memory for storing status information maintained by said control program , said status information including a respective block status for each block and a separate respective set status for said first set of blocks and said second set of blocks , said set status information including identification of the memory structure according to which each respective set of blocks is configured ;
wherein said control program , in response to identification of a set of blocks of data to be converted from a first memory structure to a second memory structure , (a) updates block status information for the blocks of said set of blocks to be converted , and (b) updates set status information for said set of blocks to identify the set as configured according to the second memory structure .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system (computer system) , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
WO9838568A1
CLAIM 9
. The data storage system of claim 8 , wherein said programmable processor is contained in a controller for attaching to a host computer system (computer system) , said controller including a random access memory for containing said status information .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (storing data, said memory) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
WO9838568A1
CLAIM 16
. A controller for controlling a data storage system , said data storage system having a plurality of data storage devices for storing data (storing data, store data) , said controller comprising : a programmable processor for controlling the operation of said plurality of data storage devices , said programmable processor executing a control program for converting a first memory structure stored on said plurality of storage devices to a second memory structure stored on said plurality of storage devices ;
and a random access memory for containing status information maintained by said control program ;
wherein said control program , in response to identification of a set of blocks of data to be converted , each block of said set to be converted being stored on a different respective one of said plurality of data storage devices , said set comprising a plurality of pairs of blocks , both blocks of each respective pair containing identical data , (a) updates said status information to designate a first block of said set of blocks as a parity block , and (b) updates said status information to designate a respective block from each pair of blocks of said set which does not include said first block as available for storage of replacement data .

WO9838568A1
CLAIM 24
. A data storage system , comprising : a plurality of data storage devices ;
a programmable processor for controlling the operation of said plurality of data storage devices , said programmable processor executing a control program for controlling the operation of said data storage system ;
wherein data in said plurality of data storage devices is organized into a plurality of sets of blocks , each block of a set being stored on a different respective one of said plurality of data storage devices ;
wherein said control program supports formatting of said sets of blocks according to a plurality of different memory structures , at least one of said memory (storing data, store data) structures being a redundant data format , a first set of blocks and a second set of blocks being formattable independently of each other ;
and a random access memory for storing status information maintained by said control program , said status information including a respective block status for each block and a separate respective set status for said first set of blocks and said second set of blocks , said set status information including identification of the memory structure according to which each respective set of blocks is configured ;
wherein said control program , in response to identification of a set of blocks of data to be converted from a first memory structure to a second memory structure , (a) updates block status information for the blocks of said set of blocks to be converted , and (b) updates set status information for said set of blocks to identify the set as configured according to the second memory structure .

US9632727B2
CLAIM 8
. The system of claim 7 , further comprising means for providing a storage interface (processing apparatus) to accept requests to perform storage operations on the solid-state storage medium in reference to the logical blocks and to accept the message identifying the logical block that is not being used to reference data stored on the solid-state storage medium .
WO9838568A1
CLAIM 20
. A program storage device readable by a digital processing apparatus (storage interface) and tangibly embodying a control program of instructions executable by the digital processing apparatus for controlling a data storage system , said data storage system having a plurality of data storage devices for storing data , said program performing method steps for converting a first memory structure into a second memory structure , the method steps comprising : (a) receiving the identification of a set of blocks of data to be converted from said first memory structure to said second memory structure , each block of said set to be converted being stored on a different respective one of said plurality of data storage devices , said set comprising a plurality of pairs of blocks , both blocks of each respective pair containing identical data ;
(b) updating status information to designate a first block of said set of blocks as a parity block ;
and (c) updating said status information to designate a respective block from each pair of blocks of said set which does not include said first block as available for storage of replacement data .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface (processing apparatus) configured to communicate with a storage client ;

a storage processor coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
WO9838568A1
CLAIM 20
. A program storage device readable by a digital processing apparatus (storage interface) and tangibly embodying a control program of instructions executable by the digital processing apparatus for controlling a data storage system , said data storage system having a plurality of data storage devices for storing data , said program performing method steps for converting a first memory structure into a second memory structure , the method steps comprising : (a) receiving the identification of a set of blocks of data to be converted from said first memory structure to said second memory structure , each block of said set to be converted being stored on a different respective one of said plurality of data storage devices , said set comprising a plurality of pairs of blocks , both blocks of each respective pair containing identical data ;
(b) updating status information to designate a first block of said set of blocks as a parity block ;
and (c) updating said status information to designate a respective block from each pair of blocks of said set which does not include said first block as available for storage of replacement data .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer (hard disk) is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor returns a predetermined data string .
WO9838568A1
CLAIM 7
. The method for converting a first memory structure to a second memory structure of claim 1 , wherein said data storage devices are rotating magnetic hard disk (state storage medium, state storage system, storage processer) drives .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
WO9737296A1

Filed: 1997-04-02     Issued: 1997-10-09

Memory devices

(Original Assignee) Memory Corporation Plc     

Alan Welsh Sinclair
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations (logical address space) on the solid state storage medium in response to requests from a computer system , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data (second address) pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
WO9737296A1
CLAIM 1
Claims 1 Λ memor\ device compπsing a user interface (18) a controller (46) a store () and address mapping means (44) for mapping a first address trom the user interface to a second address (store data) for accessing the store characterised in that the controller stores control information in successive regions ot the store each time the information is updated 2 Λ memon device according to claim 1 characterised in that the control information comprises the current positions of a write pointer (30) and an erase pointer (32) 3 A memon device according to claim 1 or claim 2 characterised in that said control information is stored at a fixed location in logical address space (storage operations, storage interface) 4 A memory device according to claim 3 characterised in that logical locations at which said control information is stored are barred from access by the host 5 A memory device according to claim 4 characterised in that control information (36) is stored at the highest available logical address (38) and the host is only given an addressable range (40) from the lowest logical address up to the start of the control sector address 6 A memory device according to any one of the preceding claims characterised in that said address mapping means (44) maintains a constant first address for the said information

US9632727B2
CLAIM 5
. The apparatus of claim 1 , further comprising a garbage collector (logical locations) configured to designate that the physical address previously assigned to the identified logical address comprises data suitable for removal from the solid-state storage medium in response to the message .
WO9737296A1
CLAIM 1
Claims 1 Λ memor\ device compπsing a user interface (18) a controller (46) a store () and address mapping means (44) for mapping a first address trom the user interface to a second address for accessing the store characterised in that the controller stores control information in successive regions ot the store each time the information is updated 2 Λ memon device according to claim 1 characterised in that the control information comprises the current positions of a write pointer (30) and an erase pointer (32) 3 A memon device according to claim 1 or claim 2 characterised in that said control information is stored at a fixed location in logical address space 4 A memory device according to claim 3 characterised in that logical locations (garbage collector) at which said control information is stored are barred from access by the host 5 A memory device according to claim 4 characterised in that control information (36) is stored at the highest available logical address (38) and the host is only given an addressable range (40) from the lowest logical address up to the start of the control sector address 6 A memory device according to any one of the preceding claims characterised in that said address mapping means (44) maintains a constant first address for the said information

US9632727B2
CLAIM 8
. The system of claim 7 , further comprising means for providing a storage interface (logical address space) to accept requests to perform storage operations (logical address space) on the solid-state storage medium in reference to the logical blocks and to accept the message identifying the logical block that is not being used to reference data stored on the solid-state storage medium .
WO9737296A1
CLAIM 1
Claims 1 Λ memor\ device compπsing a user interface (18) a controller (46) a store () and address mapping means (44) for mapping a first address trom the user interface to a second address for accessing the store characterised in that the controller stores control information in successive regions ot the store each time the information is updated 2 Λ memon device according to claim 1 characterised in that the control information comprises the current positions of a write pointer (30) and an erase pointer (32) 3 A memon device according to claim 1 or claim 2 characterised in that said control information is stored at a fixed location in logical address space (storage operations, storage interface) 4 A memory device according to claim 3 characterised in that logical locations at which said control information is stored are barred from access by the host 5 A memory device according to claim 4 characterised in that control information (36) is stored at the highest available logical address (38) and the host is only given an addressable range (40) from the lowest logical address up to the start of the control sector address 6 A memory device according to any one of the preceding claims characterised in that said address mapping means (44) maintains a constant first address for the said information

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface (logical address space) configured to communicate with a storage client ;

a storage processor coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
WO9737296A1
CLAIM 1
Claims 1 Λ memor\ device compπsing a user interface (18) a controller (46) a store () and address mapping means (44) for mapping a first address trom the user interface to a second address for accessing the store characterised in that the controller stores control information in successive regions ot the store each time the information is updated 2 Λ memon device according to claim 1 characterised in that the control information comprises the current positions of a write pointer (30) and an erase pointer (32) 3 A memon device according to claim 1 or claim 2 characterised in that said control information is stored at a fixed location in logical address space (storage operations, storage interface) 4 A memory device according to claim 3 characterised in that logical locations at which said control information is stored are barred from access by the host 5 A memory device according to claim 4 characterised in that control information (36) is stored at the highest available logical address (38) and the host is only given an addressable range (40) from the lowest logical address up to the start of the control sector address 6 A memory device according to any one of the preceding claims characterised in that said address mapping means (44) maintains a constant first address for the said information




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
EP0747822A2

Filed: 1996-06-05     Issued: 1996-12-11

External storage system with redundant storage controllers

(Original Assignee) Hitachi Ltd     (Current Assignee) Hitachi Ltd

Yoshiko Matsumoto, Kenji Muraoka
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations (same storage) on the solid state storage medium in response to requests from a computer system , including storing data (said memory, storing data) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data (said memory, storing data) pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
EP0747822A2
CLAIM 1
An external storage system comprising : a storage unit (500) for storing data (store data, storing data) to be transferred to and from an upper level system (100) ;
a plurality of storage controllers (200 , 400) provided between said storage unit and said upper level system for controlling data transfer between said upper level system and said storage unit ;
and a management memory (310) accessible by the plurality of storage controllers for storing management information of the plurality of storage controllers ,    wherein a first storage controller for receiving an input-output request from said upper level system stores said input-output request in said management memory as load distribution information , and a second storage controller refers to said load distribution information and processes said input/output request received by said first storage controller .

EP0747822A2
CLAIM 11
An external storage system according to claim 6 , wherein said management memory has data transfer mode information indicating a timing of a completion report for a write request from said upper level system whether the completion report is issued when data is written in said data buffer or when the data is written in said memory (store data, storing data) unit .

EP0747822A2
CLAIM 20
An external storage system according to claim 14 , wherein : the plurality of storage controllers each have a first mode for data transfer between said data transfer controller and each of the data buffers of the plurality of storage controllers and a second mode for data transfer between said data transfer controller and said data buffer in the same storage (state storage controller, storage operations) controller ;
and when the plurality of storage controllers operate , said first mode is selected , and when only one storage controller operates because one of the storage controllers is disconnected , said second mode is selected .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (said memory, storing data) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
EP0747822A2
CLAIM 1
An external storage system comprising : a storage unit (500) for storing data (store data, storing data) to be transferred to and from an upper level system (100) ;
a plurality of storage controllers (200 , 400) provided between said storage unit and said upper level system for controlling data transfer between said upper level system and said storage unit ;
and a management memory (310) accessible by the plurality of storage controllers for storing management information of the plurality of storage controllers ,    wherein a first storage controller for receiving an input-output request from said upper level system stores said input-output request in said management memory as load distribution information , and a second storage controller refers to said load distribution information and processes said input/output request received by said first storage controller .

EP0747822A2
CLAIM 11
An external storage system according to claim 6 , wherein said management memory has data transfer mode information indicating a timing of a completion report for a write request from said upper level system whether the completion report is issued when data is written in said data buffer or when the data is written in said memory (store data, storing data) unit .

US9632727B2
CLAIM 8
. The system of claim 7 , further comprising means for providing a storage interface to accept requests to perform storage operations (same storage) on the solid-state storage medium in reference to the logical blocks and to accept the message identifying the logical block that is not being used to reference data stored on the solid-state storage medium .
EP0747822A2
CLAIM 20
An external storage system according to claim 14 , wherein : the plurality of storage controllers each have a first mode for data transfer between said data transfer controller and each of the data buffers of the plurality of storage controllers and a second mode for data transfer between said data transfer controller and said data buffer in the same storage (state storage controller, storage operations) controller ;
and when the plurality of storage controllers operate , said first mode is selected , and when only one storage controller operates because one of the storage controllers is disconnected , said second mode is selected .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request (transferring said data, n information) specifying one or more logical addresses included in the empty-block directive command , the storage processor returns a predetermined data string .
EP0747822A2
CLAIM 1
An external storage system comprising : a storage unit (500) for storing data to be transferred to and from an upper level system (100) ;
a plurality of storage controllers (200 , 400) provided between said storage unit and said upper level system for controlling data transfer between said upper level system and said storage unit ;
and a management memory (310) accessible by the plurality of storage controllers for storing management information of the plurality of storage controllers ,    wherein a first storage controller for receiving an input-output request from said upper level system stores said input-output request in said management memory as load distribution information (read request) , and a second storage controller refers to said load distribution information and processes said input/output request received by said first storage controller .

EP0747822A2
CLAIM 14
An external storage system comprising : a storage unit (500) for storing data to be transferred to and from an upper level system (100) ;
a plurality of storage controllers (200 , 400) provided between said storage unit and said upper level system for controlling data transfer between said upper level system and said storage unit , the plurality of storage controllers each including : a data buffer (240 , 440) for temporarily storing the data ;
a data transfer controller (230 , 430) for controlling data transfer between said upper level system and said data buffer and for transferring said data (read request) between said data buffers of said plurality of storage controllers including said data buffer of its own storage controllers ;
and a DRV transfer controller (260 , 460) for controlling data transfer between said data buffer and said storage unit ;
a common management memory (310) accessible by the plurality of storage controllers for storing management information of the plurality of storage controllers ;
and communication means (300) for communicating with the plurality of storage controllers .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
WO9612225A1

Filed: 1994-10-18     Issued: 1996-04-25

Non-volatile solid state random access storage device used in place of a rotating disk drive unit in a computer system

(Original Assignee) Framdrive     

Michael E. Thomas
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations (receiving step) on the solid state (solid state) storage medium in response to requests from a computer system , including storing data (storing data, said memory) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data (storing data, said memory) pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
WO9612225A1
CLAIM 1
. A solid - state , non-volatile random access memory (RAM) pack for emulating a rotating disk drive peripheral device in a host data processing system in response to control signals from the host data processing system , the control signals including stepping and stepping direction signals representing movement from a present location to a desired location ;
the non-volatile random access memory pack using the control signals to address a selected block of solid state (solid state) memory within the memory pack using a given controller specification including the stepping and stepping direction signals and an indexing control signal , said memory (storing data, store data) pack comprising : a removable solid - state non-volatile random access memory means for storing data (storing data, store data) , said random access memory means comprising a plurality of ferroelectric random access memory integrated circuits , each including a ferroelectric film layer underneath a silicon substrate ;
interface means for coupling the random access memory means to said host data processing system , the interface means including : controller means for receiving control signals used for a disk drive peripheral device ;
means for generating from the control signals an address for addressing a section of said random access memory means , said section including a plurality of data storage locations ;
and means for sequentially addressing said data storage locations within the selected section when reading data from the random access memory to the disk drive controller and when writing data to the random access memory means from the disk drive controller ;
and from the host data processing system , including means for providing status signals including an index signal to the host data processing system .

WO9612225A1
CLAIM 19
. The method of Claim 15 , wherein signal are received during said receiving step (storage operations) via a parallel data interface .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface (command signals, parallel data) configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial (command signals, parallel data) Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA (drive controller) bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface (central processing unit) , and a Fibre Channel interface .
WO9612225A1
CLAIM 1
. A solid - state , non-volatile random access memory (RAM) pack for emulating a rotating disk drive peripheral device in a host data processing system in response to control signals from the host data processing system , the control signals including stepping and stepping direction signals representing movement from a present location to a desired location ;
the non-volatile random access memory pack using the control signals to address a selected block of solid state memory within the memory pack using a given controller specification including the stepping and stepping direction signals and an indexing control signal , said memory pack comprising : a removable solid - state non-volatile random access memory means for storing data , said random access memory means comprising a plurality of ferroelectric random access memory integrated circuits , each including a ferroelectric film layer underneath a silicon substrate ;
interface means for coupling the random access memory means to said host data processing system , the interface means including : controller means for receiving control signals used for a disk drive peripheral device ;
means for generating from the control signals an address for addressing a section of said random access memory means , said section including a plurality of data storage locations ;
and means for sequentially addressing said data storage locations within the selected section when reading data from the random access memory to the disk drive controller (external SATA, flash memory device, block directive command) and when writing data to the random access memory means from the disk drive controller ;
and from the host data processing system , including means for providing status signals including an index signal to the host data processing system .

WO9612225A1
CLAIM 3
. Thθ apparatus of Claim 1 , said interface further comprising : a parallel data (bus interface, external Serial, external Serial Advanced Technology Attachment bus interface, external SATA bus interface) interface .

WO9612225A1
CLAIM 13
. A data processing system comprising : central processing unit (internet SCSI interface) means ;
controller means for a peripheral rotating disk drive , the controller means coupled with the central processing unit means ;
mounting means for removably receiving a non-volatile non-rotating solid state ferroelectric random access memory (RAM) memory pack , the mounting means coupling the RAM memory pack for communication to the controller means ;
the RAM memory pack including : a plurality of non-volatile ferroelectric random access memory (RAM) ferroelectric RAM chips mounted on a plurality of printed circuit boards ;
interface means for receiving and sending control , status and data signals between the RAM memory pack and the controller means , the control signals from the controller means including head select , stepping and stepping direction signals representing movement from a present cylinder to a desired cylinder ;
microprocessor means for determining from the head select , stepping and stepping direction signals a predetermined address for a section of memory in the plurality of RAM ferroelectric chips ;
address decoder means for selecting one of said RAM ferroelectric chips and providing a most significant bit address for the section of memory from predetermined address ;
means for generating least significant bit addresses for strobing the section of memory in order to access data stored within the section of memory ;
and means for multiplexing data signals between a selected one of said RAM ferroelectric chips and the interface means .

WO9612225A1
CLAIM 18
. The method of Claim 17 , wherein the step of enabling access to the section of the non-volatile ferroelectric random access memory includes the steps of : selecting a chip , from a plurality of chips comprising the non-volatile ferroelectric random access memory ;
and multiplexing read/write command signals (bus interface, external Serial, external Serial Advanced Technology Attachment bus interface, external SATA bus interface) and data signals to the plurality of chips comprising the non-volatile ferroelectric random access memory .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (storing data, said memory) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
WO9612225A1
CLAIM 1
. A solid - state , non-volatile random access memory (RAM) pack for emulating a rotating disk drive peripheral device in a host data processing system in response to control signals from the host data processing system , the control signals including stepping and stepping direction signals representing movement from a present location to a desired location ;
the non-volatile random access memory pack using the control signals to address a selected block of solid state memory within the memory pack using a given controller specification including the stepping and stepping direction signals and an indexing control signal , said memory (storing data, store data) pack comprising : a removable solid - state non-volatile random access memory means for storing data (storing data, store data) , said random access memory means comprising a plurality of ferroelectric random access memory integrated circuits , each including a ferroelectric film layer underneath a silicon substrate ;
interface means for coupling the random access memory means to said host data processing system , the interface means including : controller means for receiving control signals used for a disk drive peripheral device ;
means for generating from the control signals an address for addressing a section of said random access memory means , said section including a plurality of data storage locations ;
and means for sequentially addressing said data storage locations within the selected section when reading data from the random access memory to the disk drive controller and when writing data to the random access memory means from the disk drive controller ;
and from the host data processing system , including means for providing status signals including an index signal to the host data processing system .

US9632727B2
CLAIM 8
. The system of claim 7 , further comprising means for providing a storage interface to accept requests to perform storage operations (receiving step) on the solid-state storage medium in reference to the logical blocks and to accept the message identifying the logical block that is not being used to reference data stored on the solid-state storage medium .
WO9612225A1
CLAIM 19
. The method of Claim 15 , wherein signal are received during said receiving step (storage operations) via a parallel data interface .

US9632727B2
CLAIM 9
. The system of claim 7 , wherein unmapping the identified logical block comprises invalidating an entry of the logical-to-physical mappings , the entry indicating a mapping between the identified logical block and the particular storage block (address decoder) .
WO9612225A1
CLAIM 9
. A solid-state , non-volatile random access memory pack for emulating a rotating disk drive used as a peripheral device in a host data processing system in response to control signals from the host data processing system , the control signals including head select , stepping and stepping direction signals representing movement from a present position to a desired position ;
said memory pack comprising : a plurality of non-volatile ferroelectric random access memory (RAM) chips mounted in a predetermined manner on a plurality of printed circuit boards ;
interface means for receiving and the sending control signals , and status and data signals between the memory pack and the host data processing system ;
microprocessor means storing a previous position and calculating a new position from the head select , stepping and stepping direction signals ;
the microprocessor means further mapping the new position to a predetermined address for a section of memory in the plurality of ferroelectric RAM chips ;
address decoder (particular storage block) mean for selecting one of said ferroelectric RAM chips and providing a most significant bit address for the section of memory from the predetermined address ;
means for generating least significant bit address for strobing the section of memory in order to access data stored within the section of memory ;
and means for multiplexing data signals between a selected one of said ferroelectric RAM chips and the interface means .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor (data store) coupled to the storage interface ;

a flash memory device (drive controller) coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
WO9612225A1
CLAIM 1
. A solid - state , non-volatile random access memory (RAM) pack for emulating a rotating disk drive peripheral device in a host data processing system in response to control signals from the host data processing system , the control signals including stepping and stepping direction signals representing movement from a present location to a desired location ;
the non-volatile random access memory pack using the control signals to address a selected block of solid state memory within the memory pack using a given controller specification including the stepping and stepping direction signals and an indexing control signal , said memory pack comprising : a removable solid - state non-volatile random access memory means for storing data , said random access memory means comprising a plurality of ferroelectric random access memory integrated circuits , each including a ferroelectric film layer underneath a silicon substrate ;
interface means for coupling the random access memory means to said host data processing system , the interface means including : controller means for receiving control signals used for a disk drive peripheral device ;
means for generating from the control signals an address for addressing a section of said random access memory means , said section including a plurality of data storage locations ;
and means for sequentially addressing said data storage locations within the selected section when reading data from the random access memory to the disk drive controller (external SATA, flash memory device, block directive command) and when writing data to the random access memory means from the disk drive controller ;
and from the host data processing system , including means for providing status signals including an index signal to the host data processing system .

WO9612225A1
CLAIM 9
. A solid-state , non-volatile random access memory pack for emulating a rotating disk drive used as a peripheral device in a host data processing system in response to control signals from the host data processing system , the control signals including head select , stepping and stepping direction signals representing movement from a present position to a desired position ;
said memory pack comprising : a plurality of non-volatile ferroelectric random access memory (RAM) chips mounted in a predetermined manner on a plurality of printed circuit boards ;
interface means for receiving and the sending control signals , and status and data signals between the memory pack and the host data processing system ;
microprocessor means storing a previous position and calculating a new position from the head select , stepping and stepping direction signals ;
the microprocessor means further mapping the new position to a predetermined address for a section of memory in the plurality of ferroelectric RAM chips ;
address decoder mean for selecting one of said ferroelectric RAM chips and providing a most significant bit address for the section of memory from the predetermined address ;
means for generating least significant bit address for strobing the section of memory in order to access data store (storage processor) d within the section of memory ;
and means for multiplexing data signals between a selected one of said ferroelectric RAM chips and the interface means .

US9632727B2
CLAIM 13
. The system of claim 12 , wherein the logical-to-physical translation layer is stored in the flash memory device (drive controller) .
WO9612225A1
CLAIM 1
. A solid - state , non-volatile random access memory (RAM) pack for emulating a rotating disk drive peripheral device in a host data processing system in response to control signals from the host data processing system , the control signals including stepping and stepping direction signals representing movement from a present location to a desired location ;
the non-volatile random access memory pack using the control signals to address a selected block of solid state memory within the memory pack using a given controller specification including the stepping and stepping direction signals and an indexing control signal , said memory pack comprising : a removable solid - state non-volatile random access memory means for storing data , said random access memory means comprising a plurality of ferroelectric random access memory integrated circuits , each including a ferroelectric film layer underneath a silicon substrate ;
interface means for coupling the random access memory means to said host data processing system , the interface means including : controller means for receiving control signals used for a disk drive peripheral device ;
means for generating from the control signals an address for addressing a section of said random access memory means , said section including a plurality of data storage locations ;
and means for sequentially addressing said data storage locations within the selected section when reading data from the random access memory to the disk drive controller (external SATA, flash memory device, block directive command) and when writing data to the random access memory means from the disk drive controller ;
and from the host data processing system , including means for providing status signals including an index signal to the host data processing system .

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (data store) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
WO9612225A1
CLAIM 9
. A solid-state , non-volatile random access memory pack for emulating a rotating disk drive used as a peripheral device in a host data processing system in response to control signals from the host data processing system , the control signals including head select , stepping and stepping direction signals representing movement from a present position to a desired position ;
said memory pack comprising : a plurality of non-volatile ferroelectric random access memory (RAM) chips mounted in a predetermined manner on a plurality of printed circuit boards ;
interface means for receiving and the sending control signals , and status and data signals between the memory pack and the host data processing system ;
microprocessor means storing a previous position and calculating a new position from the head select , stepping and stepping direction signals ;
the microprocessor means further mapping the new position to a predetermined address for a section of memory in the plurality of ferroelectric RAM chips ;
address decoder mean for selecting one of said ferroelectric RAM chips and providing a most significant bit address for the section of memory from the predetermined address ;
means for generating least significant bit address for strobing the section of memory in order to access data store (storage processor) d within the section of memory ;
and means for multiplexing data signals between a selected one of said ferroelectric RAM chips and the interface means .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor (data store) returns a predetermined data string .
WO9612225A1
CLAIM 9
. A solid-state , non-volatile random access memory pack for emulating a rotating disk drive used as a peripheral device in a host data processing system in response to control signals from the host data processing system , the control signals including head select , stepping and stepping direction signals representing movement from a present position to a desired position ;
said memory pack comprising : a plurality of non-volatile ferroelectric random access memory (RAM) chips mounted in a predetermined manner on a plurality of printed circuit boards ;
interface means for receiving and the sending control signals , and status and data signals between the memory pack and the host data processing system ;
microprocessor means storing a previous position and calculating a new position from the head select , stepping and stepping direction signals ;
the microprocessor means further mapping the new position to a predetermined address for a section of memory in the plurality of ferroelectric RAM chips ;
address decoder mean for selecting one of said ferroelectric RAM chips and providing a most significant bit address for the section of memory from the predetermined address ;
means for generating least significant bit address for strobing the section of memory in order to access data store (storage processor) d within the section of memory ;
and means for multiplexing data signals between a selected one of said ferroelectric RAM chips and the interface means .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
WO9420906A1

Filed: 1994-02-28     Issued: 1994-09-15

Flash file system

(Original Assignee) M-Systems Ltd.; M-Systems Inc.     

Amir Ban
US9632727B2
CLAIM 5
. The apparatus of claim 1 , further comprising a garbage collector (memory management) configured to designate that the physical address previously assigned to the identified logical address comprises data suitable for removal from the solid-state storage medium in response to the message .
WO9420906A1
CLAIM 1
. A memory management (garbage collector) method for a memory in which data can be written only in unwritten physical memory locations and in which a zone of contiguous memory locations can be simultaneously erased , comprising the steps of : organizing the memory into a plurality of units with each of the units encompassing at least one zone ;
organizing each unit into a plurality of blocks , each of said blocks comprised of a plurality of contiguous physical memory locations ;
establishing an allocation table for each unit that indicates the status of each block in a unit as active written , unwritten or deleted ;
establishing a table to map virtual addresses to physical addresses to physical addresses within a unit ;
in writing data to said memory at a virtual address : (a) mapping said virtual address to a physical block address in a unit ;
(b) examining said allocation table for said unit to which said virtual address has been mapped in subparagraph (a) to determine the status of a block at said physical block address as active written or unwritten ;
(c) if said block at said physical block address is in an active written status : (1) examining said allocation table for at least one of said units to identify an unwritten block address ;
(2) writing said data into said memory to said unwritten block address ;
(3) changing said allocation table for said unit to which said virtual address has been mapped to indicated as deleted said physical block address ;
(4) changing said allocation table for a unit in which said data has been written in paragraph (c)(2) to indicate as active written said unwritten block address where said data has been written ;
(5) changing said table to map virtual addresses to physical addresses within a unit so that said table maps said virtual address to the physical address of said unwritten block in which said data has been written in step (c)(2) .

US9632727B2
CLAIM 8
. The system of claim 7 , further comprising means for providing a storage interface (virtual addresses) to accept requests to perform storage operations on the solid-state storage medium in reference to the logical blocks and to accept the message identifying the logical block that is not being used to reference data stored on the solid-state storage medium .
WO9420906A1
CLAIM 1
. A memory management method for a memory in which data can be written only in unwritten physical memory locations and in which a zone of contiguous memory locations can be simultaneously erased , comprising the steps of : organizing the memory into a plurality of units with each of the units encompassing at least one zone ;
organizing each unit into a plurality of blocks , each of said blocks comprised of a plurality of contiguous physical memory locations ;
establishing an allocation table for each unit that indicates the status of each block in a unit as active written , unwritten or deleted ;
establishing a table to map virtual addresses (storage interface) to physical addresses to physical addresses within a unit ;
in writing data to said memory at a virtual address : (a) mapping said virtual address to a physical block address in a unit ;
(b) examining said allocation table for said unit to which said virtual address has been mapped in subparagraph (a) to determine the status of a block at said physical block address as active written or unwritten ;
(c) if said block at said physical block address is in an active written status : (1) examining said allocation table for at least one of said units to identify an unwritten block address ;
(2) writing said data into said memory to said unwritten block address ;
(3) changing said allocation table for said unit to which said virtual address has been mapped to indicated as deleted said physical block address ;
(4) changing said allocation table for a unit in which said data has been written in paragraph (c)(2) to indicate as active written said unwritten block address where said data has been written ;
(5) changing said table to map virtual addresses to physical addresses within a unit so that said table maps said virtual address to the physical address of said unwritten block in which said data has been written in step (c)(2) .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface (virtual addresses) configured to communicate with a storage client ;

a storage processor coupled to the storage interface ;

a flash memory device (one zone) coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
WO9420906A1
CLAIM 1
. A memory management method for a memory in which data can be written only in unwritten physical memory locations and in which a zone of contiguous memory locations can be simultaneously erased , comprising the steps of : organizing the memory into a plurality of units with each of the units encompassing at least one zone (flash memory device) ;
organizing each unit into a plurality of blocks , each of said blocks comprised of a plurality of contiguous physical memory locations ;
establishing an allocation table for each unit that indicates the status of each block in a unit as active written , unwritten or deleted ;
establishing a table to map virtual addresses (storage interface) to physical addresses to physical addresses within a unit ;
in writing data to said memory at a virtual address : (a) mapping said virtual address to a physical block address in a unit ;
(b) examining said allocation table for said unit to which said virtual address has been mapped in subparagraph (a) to determine the status of a block at said physical block address as active written or unwritten ;
(c) if said block at said physical block address is in an active written status : (1) examining said allocation table for at least one of said units to identify an unwritten block address ;
(2) writing said data into said memory to said unwritten block address ;
(3) changing said allocation table for said unit to which said virtual address has been mapped to indicated as deleted said physical block address ;
(4) changing said allocation table for a unit in which said data has been written in paragraph (c)(2) to indicate as active written said unwritten block address where said data has been written ;
(5) changing said table to map virtual addresses to physical addresses within a unit so that said table maps said virtual address to the physical address of said unwritten block in which said data has been written in step (c)(2) .

US9632727B2
CLAIM 13
. The system of claim 12 , wherein the logical-to-physical translation layer is stored in the flash memory device (one zone) .
WO9420906A1
CLAIM 1
. A memory management method for a memory in which data can be written only in unwritten physical memory locations and in which a zone of contiguous memory locations can be simultaneously erased , comprising the steps of : organizing the memory into a plurality of units with each of the units encompassing at least one zone (flash memory device) ;
organizing each unit into a plurality of blocks , each of said blocks comprised of a plurality of contiguous physical memory locations ;
establishing an allocation table for each unit that indicates the status of each block in a unit as active written , unwritten or deleted ;
establishing a table to map virtual addresses to physical addresses to physical addresses within a unit ;
in writing data to said memory at a virtual address : (a) mapping said virtual address to a physical block address in a unit ;
(b) examining said allocation table for said unit to which said virtual address has been mapped in subparagraph (a) to determine the status of a block at said physical block address as active written or unwritten ;
(c) if said block at said physical block address is in an active written status : (1) examining said allocation table for at least one of said units to identify an unwritten block address ;
(2) writing said data into said memory to said unwritten block address ;
(3) changing said allocation table for said unit to which said virtual address has been mapped to indicated as deleted said physical block address ;
(4) changing said allocation table for a unit in which said data has been written in paragraph (c)(2) to indicate as active written said unwritten block address where said data has been written ;
(5) changing said table to map virtual addresses to physical addresses within a unit so that said table maps said virtual address to the physical address of said unwritten block in which said data has been written in step (c)(2) .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
EP0544252A2

Filed: 1992-11-25     Issued: 1993-06-02

Data management system for programming-limited type semiconductor memory and IC memory card having the data management system

(Original Assignee) Fujitsu Ltd     (Current Assignee) Fujitsu Ltd

Noriyuki c/o Fujitsu Limited Matsui, Hiroyuki c/o Fujitsu Limited Itoh
US9632727B2
CLAIM 4
. The apparatus of claim 1 , wherein the indexer comprises firmware (data management system) of the solid-state storage controller .
EP0544252A2
CLAIM 1
A data management system (indexer comprises firmware) for a programming-limited type semiconductor memory (M) which is programmable a limited number of times and which includes a plurality of storage areas , characterized in that the data management system comprises :    management means (1) for managing , for each of the storage areas , the number of times that programming has been performed ;
and    control means (2) , coupled to said management means for selecting one of the storage areas for which programming has been performed the smallest number of times and for having input data written into a selected one of the storage areas , so that all the storage areas can be equally programmed .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface (single semiconductor) configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
EP0544252A2
CLAIM 8
The data management system as claimed in claim 1 , characterized in that the storage areas correspond to a plurality of blocks obtained by dividing an entire storage area of a single semiconductor (bus interface) memory chip .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client (semiconductor memory) that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
EP0544252A2
CLAIM 1
A data management system for a programming-limited type semiconductor memory (storage client) (M) which is programmable a limited number of times and which includes a plurality of storage areas , characterized in that the data management system comprises :    management means (1) for managing , for each of the storage areas , the number of times that programming has been performed ;
and    control means (2) , coupled to said management means for selecting one of the storage areas for which programming has been performed the smallest number of times and for having input data written into a selected one of the storage areas , so that all the storage areas can be equally programmed .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client (semiconductor memory) ;

a storage processor (data store) coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
EP0544252A2
CLAIM 1
A data management system for a programming-limited type semiconductor memory (storage client) (M) which is programmable a limited number of times and which includes a plurality of storage areas , characterized in that the data management system comprises :    management means (1) for managing , for each of the storage areas , the number of times that programming has been performed ;
and    control means (2) , coupled to said management means for selecting one of the storage areas for which programming has been performed the smallest number of times and for having input data written into a selected one of the storage areas , so that all the storage areas can be equally programmed .

EP0544252A2
CLAIM 3
The data management system as claimed in claim 1 , characterized in that said control means comprises first means for saving data store (storage processor) d in the selected one of the storage areas into another one of the storage areas and for erasing the data from the selected one of the storage areas before the input data is written into the selected one of the storage areas .

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (data store) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
EP0544252A2
CLAIM 3
The data management system as claimed in claim 1 , characterized in that said control means comprises first means for saving data store (storage processor) d in the selected one of the storage areas into another one of the storage areas and for erasing the data from the selected one of the storage areas before the input data is written into the selected one of the storage areas .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor (data store) returns a predetermined data string .
EP0544252A2
CLAIM 3
The data management system as claimed in claim 1 , characterized in that said control means comprises first means for saving data store (storage processor) d in the selected one of the storage areas into another one of the storage areas and for erasing the data from the selected one of the storage areas before the input data is written into the selected one of the storage areas .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
EP0686976A2

Filed: 1992-11-25     Issued: 1995-12-13

Data management system for programming-limited type semiconductor memory and IC memory card having the data management system

(Original Assignee) Fujitsu Ltd     (Current Assignee) Fujitsu Ltd

Noriyuki C/O Fujitsu Ltd. Matsui, Hiroyuki C/O Fujitsu Ltd. Itoh
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium (write operation) in response to requests from a computer system , including storing data (storing data) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data (storing information) pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
EP0686976A2
CLAIM 1
A flash memory control method characterized in that there are provided the steps of : (a) dividing a memory region of a flash memory (2) into a plurality of sectors , each of said sectors including a logical address part (10) for storing a logical address of the sector , an erasure managing part (11) for storing information (store data) which indicates at least whether or not the sector may be erased , and a data part (12) for storing data (storing data) ;
and (b) making access to an arbitrary sector of the flash memory (2) by specifying the logical address of the arbitrary sector .

EP0686976A2
CLAIM 5
The flash memory control method as claimed in any preceding claim , characterized in that there is further provided the step of : (c) adjusting data or arranging files which have been written into the flash memory (2) using the work block after a write operation (solid state storage medium) with respect to all of the m-1 blocks ends .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (storing data) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
EP0686976A2
CLAIM 1
A flash memory control method characterized in that there are provided the steps of : (a) dividing a memory region of a flash memory (2) into a plurality of sectors , each of said sectors including a logical address part (10) for storing a logical address of the sector , an erasure managing part (11) for storing information which indicates at least whether or not the sector may be erased , and a data part (12) for storing data (storing data) ;
and (b) making access to an arbitrary sector of the flash memory (2) by specifying the logical address of the arbitrary sector .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor (data store) coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
EP0686976A2
CLAIM 6
The flash memory control method as claimed in any preceding claim , characterized in that said step (a) divides the memory region so that each sector further includes an error detection data part (13) for storing information which is used for detecting and correcting an error in the data store (storage processor) d in the data part (12) .

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (data store) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
EP0686976A2
CLAIM 6
The flash memory control method as claimed in any preceding claim , characterized in that said step (a) divides the memory region so that each sector further includes an error detection data part (13) for storing information which is used for detecting and correcting an error in the data store (storage processor) d in the data part (12) .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor (data store) returns a predetermined data string .
EP0686976A2
CLAIM 6
The flash memory control method as claimed in any preceding claim , characterized in that said step (a) divides the memory region so that each sector further includes an error detection data part (13) for storing information which is used for detecting and correcting an error in the data store (storage processor) d in the data part (12) .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
WO9406210A1

Filed: 1992-08-28     Issued: 1994-03-17

Multichip ic design using tdm

(Original Assignee) Prabhakar Goel     

Prabhakar Goel
US9632727B2
CLAIM 8
. The system of claim 7 , further comprising means for providing a storage interface (said module) to accept requests to perform storage operations on the solid-state storage medium in reference to the logical blocks and to accept the message identifying the logical block that is not being used to reference data stored on the solid-state storage medium .
WO9406210A1
CLAIM 11
. The multichip i . e . module of claim 1 wherein said module (storage interface) contains a programmable interconnect chip .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface (said module) configured to communicate with a storage client ;

a storage processor coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
WO9406210A1
CLAIM 11
. The multichip i . e . module of claim 1 wherein said module (storage interface) contains a programmable interconnect chip .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one (shift registers) or more logical addresses included in the empty-block directive command , the storage processor returns a predetermined data string .
WO9406210A1
CLAIM 18
. The method of claim 14 wherein the input and output shift registers (read request specifying one) comprise stages fabricated from items from the group of items comprising flip-flops , edge triggered latches , and pairs of polarity hold latches .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
EP0522780A2

Filed: 1992-07-01     Issued: 1993-01-13

Control method for a computer memory device

(Original Assignee) International Business Machines Corp     (Current Assignee) International Business Machines Corp

Yoshinori Sakaue, Hideto Niijima
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller (control section) configured to implement storage operations on the solid state storage medium in response to requests from a computer system (computer system) , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data (main memory) pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
EP0522780A2
CLAIM 10
An external storage system as claimed in Claim 9 wherein said control section (storage controller) includes a data writing section , data reading section and block erasing section for executing a data writing , reading or erasing process to the corresponding memory block or sector of said semiconductor memory on the basis of said command processing section , and a sector copying section for copying the valid sectors of the memory block to be erased to another memory block .

EP0522780A2
CLAIM 12
An external storage system as claimed in Claim 9 wherein said control section includes :    a command processing section formed on a host processor ,    a block managing table and an address conversion table formed on the RAM of the main memory (store data) ,    a memory controller including a buffer , and    a sector managing table constituting said block managing means along with said block managing table provided on each memory block .

EP0522780A2
CLAIM 13
A computer system (computer system) comprising a host processor , an external storage system including a semiconductor memory which consists of a flash memory and comprises a plurality of memory blocks each including at least one sector , and a host bus for transferring data and a command between said external storage system and said host processor , characterized by :    control means which uses an address conversion means for converting the address from said host processor to the physical address of a particular sector and block managing means for recording the status of each memory block and each sector therein to control the data reading and writing to each sector of said semiconductor memory and the erasure of a memory block in response to said command ,    said control means having means which are responsive to the command from said host processor for executing the process of data writing or reading to the corresponding sector of said semiconductor memory or of erasing a memory block , and for updating the record of the status of each memory block and each sector of said block managing means in connection with such process .

US9632727B2
CLAIM 2
. The apparatus of claim 1 , wherein the indexer assigns logical addresses to physical addresses by use of index entries , and wherein the indexer removes an index entry (address translation table) corresponding to the identified logical address in response to the message .
EP0522780A2
CLAIM 6
A method as claimed in Claim 5 comprising responding to a sector write command from said host processor by writing said data into a free sector of said selected memory block , and if the logical address of said sector write command is equal to the logical address of the valid sector which has already been written , rewriting the record of the status with respect to said valid sector of the memory management table to be invalid , and writing the physical address of said free sector into said address translation table (index entry) .

US9632727B2
CLAIM 3
. The apparatus of claim 1 , wherein the indexer assigns logical addresses to physical addresses by use of index metadata maintained in a memory of the storage controller (control section) .
EP0522780A2
CLAIM 10
An external storage system as claimed in Claim 9 wherein said control section (storage controller) includes a data writing section , data reading section and block erasing section for executing a data writing , reading or erasing process to the corresponding memory block or sector of said semiconductor memory on the basis of said command processing section , and a sector copying section for copying the valid sectors of the memory block to be erased to another memory block .

US9632727B2
CLAIM 4
. The apparatus of claim 1 , wherein the indexer comprises firmware of the solid-state storage controller (control section) .
EP0522780A2
CLAIM 10
An external storage system as claimed in Claim 9 wherein said control section (storage controller) includes a data writing section , data reading section and block erasing section for executing a data writing , reading or erasing process to the corresponding memory block or sector of said semiconductor memory on the basis of said command processing section , and a sector copying section for copying the valid sectors of the memory block to be erased to another memory block .

US9632727B2
CLAIM 5
. The apparatus of claim 1 , further comprising a garbage collector (memory management) configured to designate that the physical address previously assigned to the identified logical address comprises data suitable for removal from the solid-state storage medium in response to the message .
EP0522780A2
CLAIM 6
A method as claimed in Claim 5 comprising responding to a sector write command from said host processor by writing said data into a free sector of said selected memory block , and if the logical address of said sector write command is equal to the logical address of the valid sector which has already been written , rewriting the record of the status with respect to said valid sector of the memory management (garbage collector) table to be invalid , and writing the physical address of said free sector into said address translation table .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller (control section) comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system (computer system) , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface (read command) , an InfiniBand interface (articular region) , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
EP0522780A2
CLAIM 2
A method as claimed in Claim 1 comprising accepting the command of said host processor by interruption , and if said command is a data read command (PCI Express bus interface) , responding thereto to perform the process of reading the data from the corresponding sector of said memory block corresponding to the logical address of said command , and if said command is a write or erase command , holding such command and data in a buffer and executing said write or erase process to said selected memory block or sector when there is no interrupt command from said host processor .

EP0522780A2
CLAIM 10
An external storage system as claimed in Claim 9 wherein said control section (storage controller) includes a data writing section , data reading section and block erasing section for executing a data writing , reading or erasing process to the corresponding memory block or sector of said semiconductor memory on the basis of said command processing section , and a sector copying section for copying the valid sectors of the memory block to be erased to another memory block .

EP0522780A2
CLAIM 13
A computer system (computer system) comprising a host processor , an external storage system including a semiconductor memory which consists of a flash memory and comprises a plurality of memory blocks each including at least one sector , and a host bus for transferring data and a command between said external storage system and said host processor , characterized by :    control means which uses an address conversion means for converting the address from said host processor to the physical address of a particular sector and block managing means for recording the status of each memory block and each sector therein to control the data reading and writing to each sector of said semiconductor memory and the erasure of a memory block in response to said command ,    said control means having means which are responsive to the command from said host processor for executing the process of data writing or reading to the corresponding sector of said semiconductor memory or of erasing a memory block , and for updating the record of the status of each memory block and each sector of said block managing means in connection with such process .

EP0522780A2
CLAIM 16
A semiconductor memory consisting of a flash memory and comprising a plurality of memory blocks each including at least one sector , wherein    a particular region (InfiniBand interface, storage interface, storage interface to accept requests to perform storage operations) is provided in each said memory block for storing the record representing the number of times said memory block was erased and status of each sector .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client (semiconductor memory) that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
EP0522780A2
CLAIM 1
A method for controlling a storage system comprising a semiconductor memory (storage client) of the flash memory type , the memory comprising a plurality of memory blocks each including at least one sector , and a control device for controlling said memory blocks , said storage system being connected to a host processor through a bus for transferring data and a command , the metod comprising ;
   selecting a memory block for which data is to be written or erased on the basis of a memory managing table which has recorded therein the number of times each memory block was erased and the statuses of each memory block and each sector ;
   converting the logical address included in said command of said host processor to a physical address indicating the sector in a particular memory block by reference to an address conversion table ;
   responding to said command to perform a process of data writing or reading to the corresponding sector or memory block erasure ;
   sequentially recording or updating in said memory managing table the status changes of each sector and memory block resulting from the processes ;
and    storing or updating in the address conversion table the relationships between the physical addresses and the logical addresses of the memory block and sector on which said processes were performed .

US9632727B2
CLAIM 8
. The system of claim 7 , further comprising means for providing a storage interface (articular region) to accept requests to perform storage operations on the solid-state storage medium in reference to the logical blocks and to accept the message identifying the logical block that is not being used to reference data stored on the solid-state storage medium .
EP0522780A2
CLAIM 16
A semiconductor memory consisting of a flash memory and comprising a plurality of memory blocks each including at least one sector , wherein    a particular region (InfiniBand interface, storage interface, storage interface to accept requests to perform storage operations) is provided in each said memory block for storing the record representing the number of times said memory block was erased and status of each sector .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface (articular region) configured to communicate with a storage client (semiconductor memory) ;

a storage processor coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
EP0522780A2
CLAIM 1
A method for controlling a storage system comprising a semiconductor memory (storage client) of the flash memory type , the memory comprising a plurality of memory blocks each including at least one sector , and a control device for controlling said memory blocks , said storage system being connected to a host processor through a bus for transferring data and a command , the metod comprising ;
   selecting a memory block for which data is to be written or erased on the basis of a memory managing table which has recorded therein the number of times each memory block was erased and the statuses of each memory block and each sector ;
   converting the logical address included in said command of said host processor to a physical address indicating the sector in a particular memory block by reference to an address conversion table ;
   responding to said command to perform a process of data writing or reading to the corresponding sector or memory block erasure ;
   sequentially recording or updating in said memory managing table the status changes of each sector and memory block resulting from the processes ;
and    storing or updating in the address conversion table the relationships between the physical addresses and the logical addresses of the memory block and sector on which said processes were performed .

EP0522780A2
CLAIM 16
A semiconductor memory consisting of a flash memory and comprising a plurality of memory blocks each including at least one sector , wherein    a particular region (InfiniBand interface, storage interface, storage interface to accept requests to perform storage operations) is provided in each said memory block for storing the record representing the number of times said memory block was erased and status of each sector .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request (n information, data reading) specifying one or more logical addresses included in the empty-block directive command , the storage processor returns a predetermined data string .
EP0522780A2
CLAIM 8
A method as claimed in any preceding claim comprising updating the record of said memory management table on the erasure of a memory block by comparison of the new file allocation information (read request) held by said host processor with the old file allocation information held in the external storage system .

EP0522780A2
CLAIM 10
An external storage system as claimed in Claim 9 wherein said control section includes a data writing section , data reading (read request) section and block erasing section for executing a data writing , reading or erasing process to the corresponding memory block or sector of said semiconductor memory on the basis of said command processing section , and a sector copying section for copying the valid sectors of the memory block to be erased to another memory block .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
JPH05204561A

Filed: 1992-04-20     Issued: 1993-08-13

フラッシュメモリを記憶媒体とした半導体ディスク

(Original Assignee) Hitachi Ltd; 株式会社日立製作所     

Takeshi Furuno, Yoshihiro Hayashi, Koichi Terada, Takashi Tsunehiro, Hajime Yamagami, 毅 古野, 光一 寺田, 一 山上, 隆司 常広, 良裕 林
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state (ロック) storage medium in response to requests from a computer system , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
JPH05204561A
CLAIM 11
【請求項11】フラッシュメモリを記憶媒体とした半導 体ディスクにおいて、 上記フラッシュメモリの書替え単位であるブロック (solid state, state storage medium, solid state storage medium) サイ ズと、上記半導体ディスクに接続されるホストシステム のファイルの処理単位であるセクタサイズとが同一サイ ズであることを特徴とする半導体ディスク。

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface (ホスト) , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
JPH05204561A
CLAIM 11
【請求項11】フラッシュメモリを記憶媒体とした半導 体ディスクにおいて、 上記フラッシュメモリの書替え単位であるブロックサイ ズと、上記半導体ディスクに接続されるホスト (PCI Express bus interface) システム のファイルの処理単位であるセクタサイズとが同一サイ ズであることを特徴とする半導体ディスク。

US9632727B2
CLAIM 8
. The system of claim 7 , further comprising means for providing a storage interface (処理単位) to accept requests to perform storage operations on the solid-state storage medium in reference to the logical blocks and to accept the message identifying the logical block that is not being used to reference data stored on the solid-state storage medium .
JPH05204561A
CLAIM 11
【請求項11】フラッシュメモリを記憶媒体とした半導 体ディスクにおいて、 上記フラッシュメモリの書替え単位であるブロックサイ ズと、上記半導体ディスクに接続されるホストシステム のファイルの処理単位 (storage interface) であるセクタサイズとが同一サイ ズであることを特徴とする半導体ディスク。

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface (処理単位) configured to communicate with a storage client ;

a storage processor coupled to the storage interface ;

a flash memory device (アドレス) coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
JPH05204561A
CLAIM 1
【請求項1】フラッシュメモリを記憶媒体とした半導体 ディスクにおいて、 上記フラッシュメモリは、 データを記憶するデータメモリ領域と、 上記データメモリのエラーとなった領域を代替する代替 メモリ領域と、 上記データメモリのうちエラーとなったデータメモリの 代替メモリのアドレス (flash memory device) をエラー情報として有するエラー 領域とを有し、 上記データメモリ領域と代替メモリ領域とエラーメモリ 領域への読みだし及び書き込みを行うメモリコントロー ラを有することを特徴とする半導体ディスク。

JPH05204561A
CLAIM 11
【請求項11】フラッシュメモリを記憶媒体とした半導 体ディスクにおいて、 上記フラッシュメモリの書替え単位であるブロックサイ ズと、上記半導体ディスクに接続されるホストシステム のファイルの処理単位 (storage interface) であるセクタサイズとが同一サイ ズであることを特徴とする半導体ディスク。

US9632727B2
CLAIM 13
. The system of claim 12 , wherein the logical-to-physical translation layer is stored in the flash memory device (アドレス) .
JPH05204561A
CLAIM 1
【請求項1】フラッシュメモリを記憶媒体とした半導体 ディスクにおいて、 上記フラッシュメモリは、 データを記憶するデータメモリ領域と、 上記データメモリのエラーとなった領域を代替する代替 メモリ領域と、 上記データメモリのうちエラーとなったデータメモリの 代替メモリのアドレス (flash memory device) をエラー情報として有するエラー 領域とを有し、 上記データメモリ領域と代替メモリ領域とエラーメモリ 領域への読みだし及び書き込みを行うメモリコントロー ラを有することを特徴とする半導体ディスク。




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
GB2251324A

Filed: 1991-11-25     Issued: 1992-07-01

File structure for a non-volatile semiconductor memory

(Original Assignee) Intel Corp     (Current Assignee) Intel Corp

Kurt Brian Robinson, Dale K Elbert, Markus A Levy
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations (only memory) on the solid state storage medium in response to requests from a computer system , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data (allocation table) pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
GB2251324A
CLAIM 5
. The non-volatile computer semiconductor of claim 1 , wherein the memory is a electrically flash erasable programmable read-only memory (storage operations) .

GB2251324A
CLAIM 18
. The memory system of claim 11 , wherein the memory for storing a plurality of directory entries further comprises : (A) a boot record containing information concerning a file structure of the non-volatile semiconductor memory ;
(B) a block status table for providing information as to whether a block of the non-volatile semiconductor memory is (1) an active block or a reserve block , (2) free or in use , and (3) defective or not defective ;
and (C) a file allocation table (store data, index entry) .

US9632727B2
CLAIM 2
. The apparatus of claim 1 , wherein the indexer assigns logical addresses to physical addresses by use of index entries , and wherein the indexer removes an index entry (allocation table) corresponding to the identified logical address in response to the message .
GB2251324A
CLAIM 18
. The memory system of claim 11 , wherein the memory for storing a plurality of directory entries further comprises : (A) a boot record containing information concerning a file structure of the non-volatile semiconductor memory ;
(B) a block status table for providing information as to whether a block of the non-volatile semiconductor memory is (1) an active block or a reserve block , (2) free or in use , and (3) defective or not defective ;
and (C) a file allocation table (store data, index entry) .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one (direct memory) of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface (direct memory) , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface (central processing unit) , and a Fibre Channel interface (direct memory) .
GB2251324A
CLAIM 27
. A computer system Domprising : (A) a central processing unit (internet SCSI interface) ;
(B) a non-volatile semiconductor memory that is erasable in blocks , wherein each bit of the non-volatile memory cannot be overwritten from a first logical state to a second logical state without a prior erasure , and wherein each bit of the non-volatile semiconductor memory can be overwritten from a second logical state to a first logical state without a prior erasure , comprising : (1) an active block for storing a first file ;
(2) a reserve block for storing a second file , wherein the second file is a copy of the first file , wherein the copy is made during a clean-up operation prior to an erasure of the active block ;
(3) a directory block comprising a directory entry for identifying the first file . (C) storage means for storing code for controlling the non-volatile semiconductor memory .

GB2251324A
CLAIM 34
. The computer system of claim 27 , wherein the non-volatile semiconductor memory is direct memory (external SATA bus interface, Fibre Channel interface, bus interface comprises one) mapped .

US9632727B2
CLAIM 8
. The system of claim 7 , further comprising means for providing a storage interface to accept requests to perform storage operations (only memory) on the solid-state storage medium in reference to the logical blocks and to accept the message identifying the logical block that is not being used to reference data stored on the solid-state storage medium .
GB2251324A
CLAIM 5
. The non-volatile computer semiconductor of claim 1 , wherein the memory is a electrically flash erasable programmable read-only memory (storage operations) .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
EP0502211A1

Filed: 1991-09-20     Issued: 1992-09-09

System equipped with processor and method of converting addresses in said system

(Original Assignee) Fujitsu Ltd     (Current Assignee) Fujitsu Ltd

Hiromasa Fujitsu Limited Takahashi, Hideyuki Fujitsu Limited Iino
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system , including storing data (address translation) pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data (main memory) pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
EP0502211A1
CLAIM 1
A system comprising a processor (1) and a main memory (store data) (2) for carrying out an address translation (storing data) using a multi-stage translation table in an execution of memory access and a main memory (2) , said processor having first storage means (3 , 12) which store part of said multi-stage translation table , said main memory having second storage means (4 , 13) , wherein said system is characterized in that the translation tables of said second storage means are retrieved using entry addresses obtained from retrieval of the translation tables of said first storage means to thereby carry out an address translation from a logic address (LA , 11) to a physical address (PA , 14) .

US9632727B2
CLAIM 7
. A system , comprising : means for controlling a solid-state storage medium , comprising , means for storing data (address translation) referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium , and means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium ;

and means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium , wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings ;

and wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings .
EP0502211A1
CLAIM 1
A system comprising a processor (1) and a main memory (2) for carrying out an address translation (storing data) using a multi-stage translation table in an execution of memory access and a main memory (2) , said processor having first storage means (3 , 12) which store part of said multi-stage translation table , said main memory having second storage means (4 , 13) , wherein said system is characterized in that the translation tables of said second storage means are retrieved using entry addresses obtained from retrieval of the translation tables of said first storage means to thereby carry out an address translation from a logic address (LA , 11) to a physical address (PA , 14) .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor (data store) coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
EP0502211A1
CLAIM 10
A system in accordance with Claim 8 , wherein said address unit has a counter means (117) which starts counting operation when loading/storing of vector data is started , a register means (118) which stores data in accordance with a length of vector data fetched through an internal bus and means (119) for comparing the value of data store (storage processor) d in said register means and a count value of said counter means , whereby the function of said address unit is stopped according to the result of said comparison when both values of data coincide .

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (data store) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
EP0502211A1
CLAIM 10
A system in accordance with Claim 8 , wherein said address unit has a counter means (117) which starts counting operation when loading/storing of vector data is started , a register means (118) which stores data in accordance with a length of vector data fetched through an internal bus and means (119) for comparing the value of data store (storage processor) d in said register means and a count value of said counter means , whereby the function of said address unit is stopped according to the result of said comparison when both values of data coincide .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor (data store) returns a predetermined data string .
EP0502211A1
CLAIM 10
A system in accordance with Claim 8 , wherein said address unit has a counter means (117) which starts counting operation when loading/storing of vector data is started , a register means (118) which stores data in accordance with a length of vector data fetched through an internal bus and means (119) for comparing the value of data store (storage processor) d in said register means and a count value of said counter means , whereby the function of said address unit is stopped according to the result of said comparison when both values of data coincide .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
GB2251323A

Filed: 1991-09-02     Issued: 1992-07-01

Disk emulation for a non-volatile semiconductor memory

(Original Assignee) Intel Corp     (Current Assignee) Intel Corp

Gerald S Holzhammer, Kurt Brian Robinson
US9632727B2
CLAIM 1
. An apparatus , comprising : a solid-state storage medium ;

a solid-state storage controller configured to implement storage operations (only memory) on the solid state storage medium in response to requests from a computer system (computer system) , including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium ;

and an indexer , comprised within the solid-state storage controller , wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium ;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system , the message indicating that the identified logical address is erased .
GB2251323A
CLAIM 2
. The non-volatile semiconductor memory of claim 1 , wherein the computer memory is a flash electrically erasable programmable read-only memory (storage operations) .

GB2251323A
CLAIM 10
. A computer system (computer system) comprising : (A) a central processing unit ;
(B) a non-volatile semiconductor memory that is erasable in blocks , wherein the non-volatile semiconductor memory is accessed by the central processing unit , and wherein the non-volatile memory comprises : (1) an active block for storing first data ;
64 (2) a reserve block for storing second data , wherein the second data is a copy of the first data , wherein the copy is made during a clean-up operation prior to an erasure of the active block ;
(3) a mapping table for mapping a logical address of an allocation unit to a physical address of a sector within the non-volatile semiconductor memory . (C) storage means for storing code for controlling the non-volatile memory .

US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system (computer system) , wherein the bus interface comprises one (direct memory) of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface (direct memory) , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface (central processing unit) , and a Fibre Channel interface (direct memory) .
GB2251323A
CLAIM 10
. A computer system (computer system) comprising : (A) a central processing unit (internet SCSI interface) ;
(B) a non-volatile semiconductor memory that is erasable in blocks , wherein the non-volatile semiconductor memory is accessed by the central processing unit , and wherein the non-volatile memory comprises : (1) an active block for storing first data ;
64 (2) a reserve block for storing second data , wherein the second data is a copy of the first data , wherein the copy is made during a clean-up operation prior to an erasure of the active block ;
(3) a mapping table for mapping a logical address of an allocation unit to a physical address of a sector within the non-volatile semiconductor memory . (C) storage means for storing code for controlling the non-volatile memory .

GB2251323A
CLAIM 16
. A non-volatile semiconductor-memory substantially as hereinbefore described with reference to the accompanying drawings . 16 . The computer system of claim 10 , wherein the non-volatile semiconductor memory is direct memory (external SATA bus interface, Fibre Channel interface, bus interface comprises one) mapped . 17 . The computer system of claim 10 , further comprising a hardware controller for executing the code for controlling the non-volatile semiconductor memory .

US9632727B2
CLAIM 8
. The system of claim 7 , further comprising means for providing a storage interface to accept requests to perform storage operations (only memory) on the solid-state storage medium in reference to the logical blocks and to accept the message identifying the logical block that is not being used to reference data stored on the solid-state storage medium .
GB2251323A
CLAIM 2
. The non-volatile semiconductor memory of claim 1 , wherein the computer memory is a flash electrically erasable programmable read-only memory (storage operations) .




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
JPH0527924A

Filed: 1991-07-12     Issued: 1993-02-05

半導体メモリを用いた外部記憶システム及びその制御方法

(Original Assignee) Internatl Business Mach Corp <Ibm>; インターナシヨナル・ビジネス・マシーンズ・コーポレイシヨン     

Hideto Niijima, Yoshiisa Sakagami, 好功 坂上, 秀人 新島
US9632727B2
CLAIM 4
. The apparatus of claim 1 , wherein the indexer comprises firmware (記表示) of the solid-state storage controller .
JPH0527924A
CLAIM 18
【請求項18】請求16において、前記コンピュータ・ システムは、ホスト・バスを介してホスト・プロセッサ 及び外部記憶システムに接続された対話型の表示手段を 有し、 前記制御装置は、 前記表示 (indexer comprises firmware) 手段を介した対話によってユーザからフアィル 回復の要否の情報を受取り、 フアィルの回復が必要な とき、コンピュータ・システムが保有するフアィル配置 情報を参照してフアィルの内容を表示し、ユーザの確認 を得て前記フアィルの回復を行う、 ことを特徴とするコンピュータ・システム 。

US9632727B2
CLAIM 8
. The system of claim 7 , further comprising means for providing a storage interface (主記憶装置) to accept requests to perform storage operations on the solid-state storage medium in reference to the logical blocks and to accept the message identifying the logical block that is not being used to reference data stored on the solid-state storage medium .
JPH0527924A
CLAIM 15
【請求項15】請求項12において、前記制御部は、 ホスト・プロセッサ上構成されるコマンド処理部と、 主記憶装置 (storage interface, storage processor) のRAM上に構成されるブロック管理表とア ドレス変換表と、 バッファを含むメモリ・コントローラと、 前記各メモリ・ブロック上に設けられ前記ブロック管理 表と共に前記ブロック管理手段を構成するセクタ管理表 とを備えた、 ことを特徴とする外部記憶システム。

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface (主記憶装置) configured to communicate with a storage client ;

a storage processor (主記憶装置) coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
JPH0527924A
CLAIM 15
【請求項15】請求項12において、前記制御部は、 ホスト・プロセッサ上構成されるコマンド処理部と、 主記憶装置 (storage interface, storage processor) のRAM上に構成されるブロック管理表とア ドレス変換表と、 バッファを含むメモリ・コントローラと、 前記各メモリ・ブロック上に設けられ前記ブロック管理 表と共に前記ブロック管理手段を構成するセクタ管理表 とを備えた、 ことを特徴とする外部記憶システム。

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (主記憶装置) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
JPH0527924A
CLAIM 15
【請求項15】請求項12において、前記制御部は、 ホスト・プロセッサ上構成されるコマンド処理部と、 主記憶装置 (storage interface, storage processor) のRAM上に構成されるブロック管理表とア ドレス変換表と、 バッファを含むメモリ・コントローラと、 前記各メモリ・ブロック上に設けられ前記ブロック管理 表と共に前記ブロック管理手段を構成するセクタ管理表 とを備えた、 ことを特徴とする外部記憶システム。

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor (主記憶装置) returns a predetermined data string .
JPH0527924A
CLAIM 15
【請求項15】請求項12において、前記制御部は、 ホスト・プロセッサ上構成されるコマンド処理部と、 主記憶装置 (storage interface, storage processor) のRAM上に構成されるブロック管理表とア ドレス変換表と、 バッファを含むメモリ・コントローラと、 前記各メモリ・ブロック上に設けられ前記ブロック管理 表と共に前記ブロック管理手段を構成するセクタ管理表 とを備えた、 ことを特徴とする外部記憶システム。

US9632727B2
CLAIM 16
. The system of claim 15 , wherein data bits of the predetermined data string have a uniform logic (論理アドレス) level .
JPH0527924A
CLAIM 1
【請求項1】フラッシュ・メモリで構成され、それぞれ が少なくとも1つのセクタを含む複数のメモリ・ブロッ クから成る外部記憶装置としての半導体メモリと、前記 メモリ・ブロックに対する制御を行う制御部とを備え、 データおよびコマンドを転送するバスを介してホスト・ プロセッサに接続された外部記憶システムにおいて、 前記制御部が、 各メモリ・ブロックの消去回数及び各メモリ・ブロック と各セクタの状況を記録したブロック管理手段の記録に 基づき、データの書込みや消去を行うメモリ・ブロック を選定し、 前記ホスト・プロセッサの前記コマンドに含まれる論理 アドレスをアドレス変換手段によって特定のメモリ・ブ ロック内のセクタを示す物理アドレスに変換し、 前記コマンドに応答して、該当するセクタに対するデー タの書込み、読出しあるいはメモリ・ブロックの消去の 処理を行い、 これらの処理による各セクタやメモリ・ブロックの状況 変化を前記ブロック管理手段に逐次記録しもしくは更新 し、 前記処理がなされたメモリ・ブロックやセクタについて それらの物理アドレスと論理アドレス (uniform logic) との関係を前記ア ドレス変換手段に記憶しもしくは更新する、 ことを特徴とする外部記憶システムの制御方法。




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
JPH052502A

Filed: 1991-01-09     Issued: 1993-01-08

情報処理装置の電圧マージン試験方式

(Original Assignee) Nec Corp; 日本電気株式会社     

Masashi Nagasawa, 正氏 長澤
US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface configured to communicate with a storage client ;

a storage processor (メモリ) coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
JPH052502A
CLAIM 1
【請求項1】 電源電圧を定格値より上下に変動させて 試験プログラムを実行し動作試験を行う情報処理装置の 電圧マージン試験において、前記情報処理装置内の制御 部の制御を受け電源電圧を変動させることが可能な電源 部と、前記制御部からの書込読出しが可能な専用の電源 を持つバッテリバックアップメモリ (storage processor) と、前記情報処理装 置全体の動作監視を行うウォッチドッグタイマ回路とを 前記情報処理装置内に設け、前記制御部は電源電圧を変 動させる試験の実施前に変動後の試験電圧値を前記バッ テリバックアップメモリに書込み、次に前記電源部の電 源電圧を変動させた後前記試験プログラムを実行し、異 常終了およびウォッチドッグタイムアウトの少くなくと もいずれか一方を検出するまで徐徐に電圧を変動させな がら前記試験プログラムを繰り返し実行することを特徴 とする情報処理装置の電圧マージン試験方式。

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (メモリ) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
JPH052502A
CLAIM 1
【請求項1】 電源電圧を定格値より上下に変動させて 試験プログラムを実行し動作試験を行う情報処理装置の 電圧マージン試験において、前記情報処理装置内の制御 部の制御を受け電源電圧を変動させることが可能な電源 部と、前記制御部からの書込読出しが可能な専用の電源 を持つバッテリバックアップメモリ (storage processor) と、前記情報処理装 置全体の動作監視を行うウォッチドッグタイマ回路とを 前記情報処理装置内に設け、前記制御部は電源電圧を変 動させる試験の実施前に変動後の試験電圧値を前記バッ テリバックアップメモリに書込み、次に前記電源部の電 源電圧を変動させた後前記試験プログラムを実行し、異 常終了およびウォッチドッグタイムアウトの少くなくと もいずれか一方を検出するまで徐徐に電圧を変動させな がら前記試験プログラムを繰り返し実行することを特徴 とする情報処理装置の電圧マージン試験方式。

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one (する情報) or more logical addresses included in the empty-block directive command , the storage processor (メモリ) returns a predetermined data string .
JPH052502A
CLAIM 1
【請求項1】 電源電圧を定格値より上下に変動させて 試験プログラムを実行し動作試験を行う情報処理装置の 電圧マージン試験において、前記情報処理装置内の制御 部の制御を受け電源電圧を変動させることが可能な電源 部と、前記制御部からの書込読出しが可能な専用の電源 を持つバッテリバックアップメモリ (storage processor) と、前記情報処理装 置全体の動作監視を行うウォッチドッグタイマ回路とを 前記情報処理装置内に設け、前記制御部は電源電圧を変 動させる試験の実施前に変動後の試験電圧値を前記バッ テリバックアップメモリに書込み、次に前記電源部の電 源電圧を変動させた後前記試験プログラムを実行し、異 常終了およびウォッチドッグタイムアウトの少くなくと もいずれか一方を検出するまで徐徐に電圧を変動させな がら前記試験プログラムを繰り返し実行することを特徴 とする情報 (read request specifying one) 処理装置の電圧マージン試験方式。




US9632727B2

Filed: 2006-12-06     Issued: 2017-04-25

Systems and methods for identifying storage resources that are not in use

(Original Assignee) Longitude Enterprise Flash SARL     (Current Assignee) Unification Technologies LLC

David Flynn, Jonathan Thatcher, Michael Zappe
EP0489204A1

Filed: 1990-12-04     Issued: 1992-06-10

Reprogrammable data storage device

(Original Assignee) Hewlett Packard Ltd     (Current Assignee) Hewlett Packard Ltd

Kevin Lloyd-Jones
US9632727B2
CLAIM 6
. The apparatus of claim 1 , wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system , wherein the bus interface comprises one of a universal serial bus interface , an Institute of Electrical and Electronics Engineers 1394 bus interface , an external Serial Advanced Technology Attachment bus interface , a Peripheral Component Interconnect (PCI) bus interface , a PCI Express bus interface (power up) , an InfiniBand interface , an Integrated Drive Electronics (IDE) bus interface , an AT Attachment (ATA) interface , a Parallel ATA (PATA) interface , a Serial ATA (SATA) bus interface , an external SATA bus interface , a Small Computer System Interface (SCSI) bus interface , an internet SCSI interface , and a Fibre Channel interface .
EP0489204A1
CLAIM 9
A data storage device according to claim 1 , wherein the control and processing means (16) is operative during step (a) to calculate a checksum for the area of the buffer used to store the new program code , this checksum being recalculated as new program code is progressively stored in the buffer (13) , the final checksum being loaded into the flash memory (18) together with the new program code ;
the control and processing means (16) being further operative upon power up (PCI Express bus interface) of the device to recalculate the checksum for the flash memory (18) and compare it with the stored checksum to check the integrity of the program code stored in the flash memory (18) .

US9632727B2
CLAIM 8
. The system of claim 7 , further comprising means for providing a storage interface (following steps) to accept requests to perform storage operations on the solid-state storage medium in reference to the logical blocks and to accept the message identifying the logical block that is not being used to reference data stored on the solid-state storage medium .
EP0489204A1
CLAIM 1
A data storage device of the type comprising : - input/output means (10) for exchanging data between the device and an external data handling system ;
- media read/write means (12) for reading/writing data from/to a storage medium ;
- a data buffer (13) connected between the input/output means (10) and the media read/write means (12) for buffering the transfer of data between the input/output means (10) and the media read/write means ;
and - control and processing means (16)connected to the input/output means (10) , the data buffer (13) and the read/write means (12) , and operative to control the transfer of data via said data buffer (13) between the input/output means (10) and the read/write means (12) and to process said data , said control and processing means (16) including a non-volatile memory (18) for holding program code and a program-controlled processor (17) operative to execute said program code ;
characterised in that at least a portion of said non-volatile memory is a flash memory (18) and the control and processing means (16) is operative to implement the following steps (storage interface) in sequence for the purpose of reprogramming the flash memory (18) with new program code : a) storage of the new program code , received via said input/output means (10) or said media read/write means (12) , into said data buffer (13) ;
b) determination of when all said new program code has been received and stored in the data buffer (13) ;
c) erasure of said flash memory (18) ;
and d) transfer of the new program code from said data buffer (13) to said flash memory (18) .

US9632727B2
CLAIM 12
. A non-volatile solid-state storage system , comprising : a storage interface (following steps) configured to communicate with a storage client ;

a storage processor (data indicative) coupled to the storage interface ;

a flash memory device coupled to the storage processor ;

and a logical-to-physical translation layer maintained by the storage processor , wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device , wherein the storage processor is configured to : receive , from the storage client through the storage interface , an empty-block directive command and a range of logical block addresses , update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved , and store persistent data on the flash memory device , the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client .
EP0489204A1
CLAIM 1
A data storage device of the type comprising : - input/output means (10) for exchanging data between the device and an external data handling system ;
- media read/write means (12) for reading/writing data from/to a storage medium ;
- a data buffer (13) connected between the input/output means (10) and the media read/write means (12) for buffering the transfer of data between the input/output means (10) and the media read/write means ;
and - control and processing means (16)connected to the input/output means (10) , the data buffer (13) and the read/write means (12) , and operative to control the transfer of data via said data buffer (13) between the input/output means (10) and the read/write means (12) and to process said data , said control and processing means (16) including a non-volatile memory (18) for holding program code and a program-controlled processor (17) operative to execute said program code ;
characterised in that at least a portion of said non-volatile memory is a flash memory (18) and the control and processing means (16) is operative to implement the following steps (storage interface) in sequence for the purpose of reprogramming the flash memory (18) with new program code : a) storage of the new program code , received via said input/output means (10) or said media read/write means (12) , into said data buffer (13) ;
b) determination of when all said new program code has been received and stored in the data buffer (13) ;
c) erasure of said flash memory (18) ;
and d) transfer of the new program code from said data buffer (13) to said flash memory (18) .

EP0489204A1
CLAIM 7
A data storage device according to claim 4 , wherein the flash memory (18) holds identification data indicative (storage processor) of the identity of said program code and/or of said device , and wherein the said new program code also includes identification data indicative of the identity of the new program code and/or of the device on which the new program code is intended to run ;
said control and processing means (16) being operative during the said checking step to compare the identification data held in the flash memory (18) with that provided with the new program code to ascertain whether the new program code is compatible with said device .

US9632727B2
CLAIM 14
. The system of claim 12 , further comprising a volatile memory device coupled to the storage processor (data indicative) , wherein the logical-to-physical translation layer is stored in the volatile memory device .
EP0489204A1
CLAIM 7
A data storage device according to claim 4 , wherein the flash memory (18) holds identification data indicative (storage processor) of the identity of said program code and/or of said device , and wherein the said new program code also includes identification data indicative of the identity of the new program code and/or of the device on which the new program code is intended to run ;
said control and processing means (16) being operative during the said checking step to compare the identification data held in the flash memory (18) with that provided with the new program code to ascertain whether the new program code is compatible with said device .

US9632727B2
CLAIM 15
. The system of claim 12 wherein the storage processer is configured such that , responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command , the storage processor (data indicative) returns a predetermined data string .
EP0489204A1
CLAIM 7
A data storage device according to claim 4 , wherein the flash memory (18) holds identification data indicative (storage processor) of the identity of said program code and/or of said device , and wherein the said new program code also includes identification data indicative of the identity of the new program code and/or of the device on which the new program code is intended to run ;
said control and processing means (16) being operative during the said checking step to compare the identification data held in the flash memory (18) with that provided with the new program code to ascertain whether the new program code is compatible with said device .