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KR Prior Art | Ground | Reference | Owner of the Reference | Title | Semantic Mapping | Basis beta | Anticipation beta | Challenged Claims | ||||||||||||||
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| 1 | 2003 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST. : 913-916 2003 (Yoshida, 2003) | Fujitsu Laboratories Limited, Akiruno, Japan | A Design Of A Capacitorless 1T-DRAM Cell Using Gate-induced Drain Leakage (GIDL) Current For Low-power And High-speed Embedded Memory | ▪ second range ≈ write operation ▪ second interlevel dielectric layer ≈ speed operation | X | X | X | ||||||||||||||
| 2 | SOLID-STATE ELECTRONICS. 46 (10): 1525-1530 OCT 2002 (Gonzalez, 2002) | University of California, Berkeley, Micron Technology, Inc. | A Dynamic Source-drain Extension MOSFET Using A Separately Biased Conductive Spacer | ▪ first range, first sub interlevel dielectric layer ≈ drain extension ▪ second etch stop layer, second etch stop layers ≈ gate stack ▪ first etch stop layer ≈ drain side | X | X | X | X | X | X | X | X | X | ||||||||
| 3 | JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B. 18 (2): 695-699 MAR-APR 2000 (Bashir, 2000) | Purdue University, National Semiconductor Corporation | Reduction Of Sidewall Defect Induced Leakage Currents By The Use Of Nitrided Field Oxides In Silicon Selective Epitaxial Growth Isolation For Advanced Ultralarge Scale Integration | ▪ multiple etch, second etch ≈ selective epitaxial ▪ substrate coupling area, metal layer coupling area ≈ thermal stress ▪ substrate material ≈ silicon oxide | X | X | X | X | X | X | X | ||||||||||
| 4 | IEDM - INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST 1996. : 665-668 1996 (Huang, 1996) | University of California, Los Angeles (UCLA) | Epitaxial SiGeC/Si Photodetector With Response In The 1.3-1.55 Mu M Wavelength Range | ▪ interlevel dielectric ≈ low leakage ▪ etching process ≈ high speed | X | X | X | X | X | X | X | X | |||||||||
| 5 | THIN SOLID FILMS. 262 (1-2): 104-119 JUN 15 1995 (Gardner, 1995) | Thin Film Research Center, Hitachi''s Central Research Laboratory, Hitachi, Ibaraki, Japan, Intel Components Research Laboratory, 3065 Bowers Ave. SC1-03, Santa Clara, CA 95052, USA | ENCAPSULATED COPPER INTERCONNECTION DEVICES USING SIDEWALL BARRIERS | ▪ second etch, second interlevel dielectric layer ≈ encapsulation material ▪ metal layer coupling area ≈ thin film | X | X | X | X | X | X | |||||||||||
| 6 | JOURNAL OF THE ELECTROCHEMICAL SOCIETY. 139 (8): 2318-2322 AUG 1992 (Kusters, 1992) | Siemens Aktiengesellschaft | A STACKED CAPACITOR CELL WITH A FULLY SELF-ALIGNED CONTACT PROCESS FOR HIGH-DENSITY DYNAMIC RANDOM-ACCESS MEMORIES | ▪ first etch stop layer ≈ subsequent annealing ▪ interlevel dielectric, second interlevel dielectric ≈ stacked capacitor ▪ etch process ≈ ion implantation | X | X | X | X | X | X | X | X | |||||||||
| 7 | US6441418B1 (Jeffrey A. Shields, 2002) | (Original Assignee) Advanced Micro Devices Inc (Current Assignee) Monterey Research LLC | Spacer narrowed, dual width contact for charge gain reduction | ▪ floating gate ≈ floating gate ▪ interlevel dielectric, second interlevel dielectric ≈ contact hole ▪ second space ≈ second space ▪ second etch ≈ second etch ▪ first space ≈ first space, lower half ▪ contact bottom ≈ top portion ▪ first etch ≈ first etch | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) ▪ 35 U.S.C. 102(e) | ▪ discloses forming the via connector comprises a dual damascene process column… ▪ discloses a device having a conductive lm an insulating lm and a substrate… ▪ teaches a low temperature chlorinated inorganic silicon nitride material TANAKA par… ▪ describes several dry methods including ALD to have more precise control during the deposition of thinner layers and… | X | X | X | X | X | X | X | X | X | X | |||||
| 8 | US20040115914A1 (H. Manning, 2004) | (Original Assignee) Manning H. Montgomery (Current Assignee) Round Rock Research LLC | Method of fabricating integrated circuitry, and method of forming a conductive line | ▪ substrate material ≈ substrate material ▪ second etch ≈ etch stop layer ▪ floating gate ≈ drain region ▪ anti reflective coating ≈ d forming | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) ▪ 35 U.S.C. 102(e) | ▪ discloses the claimed invention with the exception of depositing tantalum and oxidizing the tantalum and depositing the… ▪ discloses doping the rst plurality of active area in the peripheral portion and doping a second plurality of active… ▪ teaches the forming the landing pads and the central landing pad comprises forming a photoresist layer having openings… ▪ teaches that a capacitor is connected to a conductive storage nodeplug in a conventional memory device in order to… | X | X | X | X | X | X | X | X | X | ||||||
| 9 | US20030132526A1 (Jeong-sic Jeon, 2003) | (Original Assignee) Samsung Electronics Co Ltd (Current Assignee) Samsung Electronics Co Ltd | Semiconductor device having a contact window and fabrication method thereof | ▪ etching process ≈ etching process ▪ multiple etch, first etch ≈ wet etch, dry etch | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ teaches that to reduce signal delay at interconnections a lm with a low dielectric is used such as… ▪ discloses a plasma etching method comprising plasma etching a lm… ▪ teaches an insulating lm stress in this range as recited in instant claim… ▪ discloses that using any one of the rare gases noble gases such as… | X | X | X | X | X | X | |||||||||
| 10 | US20020187598A1 (Byung-Jun Park, 2002) | (Original Assignee) Samsung Electronics Co Ltd (Current Assignee) Samsung Electronics Co Ltd | DRAM device and method of manufacturing the same | ▪ second etch stop layers ≈ silicon nitride layer ▪ etch process ≈ silicon oxide layer ▪ interlevel dielectric ≈ bit line contacts, contact plug ▪ second etch ≈ sacrificial layer, etch stop layer ▪ second sub interlevel dielectric layer ≈ oxide material ▪ metal layer coupling area, second interlevel dielectric layer ≈ said plate ▪ anti reflective coating ≈ d forming | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) ▪ 35 U.S.C. 102(e) | ▪ describes wherein the partial SAC etching process is carried out at a pressure of about… ▪ teaches forming a metal layer overlying the dielectric layer and in contact with the portions of the conductive layer… ▪ teaches the openings of the photoresist layer having an elliptical shape column… ▪ discloses a method for manufacturing a semiconductor device as shown below… | X | X | X | X | X | X | X | X | X | X | X | X | |||
| 11 | US20020109229A1 (Jeong-sic Jeon, 2002) | (Original Assignee) Jeon Jeong-Sic; Kim Jae-Woong; Kim Sang-Hee | Semiconductor device with improved metal interconnection and method for forming the metal interconnection | ▪ interlevel dielectric, spacer region ≈ interlevel dielectric ▪ second etch stop layers ≈ silicon nitride layer ▪ first etch, etch process ≈ stop layer ▪ anti reflective coating ≈ d forming | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ teaches an examination management system according to claims… ▪ teaches electronic blood pressure monitor and blood pressure data processing system US… ▪ teaches system and method for evaluating the performance of a scan strategy… ▪ teaches a semiconductor integrated circuit device having both analog and digital devices formed on the same substrate… | X | X | X | X | X | X | X | X | X | X | X | ||||
| 12 | US20020105089A1 (Yoshinori Tanaka, 2002) | (Original Assignee) Mitsubishi Electric Corp (Current Assignee) Renesas Electronics Corp | Semiconductor device and manufacturing method thereof | ▪ second etch, etch process ≈ said second circuit ▪ substrate material ≈ stacking direction, silicon oxide ▪ floating gate ≈ drain regions ▪ interlevel dielectric, second interlevel dielectric ≈ contact hole ▪ anti reflective coating ≈ d forming | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ teaches wherein the plurality of semiconductor structures memory cells form a pattern having a first pitch and wherein… ▪ describes a wet cleaning process to remove an excess material remaining and thereby form a sufficient opening area in… ▪ teaches that titanium nitride is an equivalent material to tungsten aluminum or copper for forming the conductive plug… ▪ teaches that a top surface of the bit line layers is coplanar with a top surface of the substrate… | X | X | X | X | X | X | X | X | X | X | X | X | |||
| 13 | US20030170979A1 (Si Kim, 2003) | (Original Assignee) Samsung Electronics Co Ltd (Current Assignee) Samsung Electronics Co Ltd | Semiconductor device capable of preventing ring defect and method of manufacturing the same | ▪ interlevel dielectric, first sub interlevel dielectric layer ≈ second interface, first interface ▪ etching process ≈ etching process ▪ contact region ≈ second contact ▪ first etch, etch process ≈ etching rate ▪ anti reflective coating ≈ d forming | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ teaches an insulating lm stress in this range as recited in instant claim… ▪ discloses that forming the expanded contact holes comprises anisotropically etching the second insulating layer to… ▪ teaches conventional surface preparation ie roughening of the base layer to ensure proper contamination removal and… ▪ teaches a resin composition which can be utilized to form multi layered circuit boards comprising bismaleimide epoxies… | X | X | X | X | X | X | X | X | X | X | X | X | X | X | |
| 14 | US20020068443A1 (Takahisa Eimori, 2002) | (Original Assignee) Mitsubishi Electric Corp (Current Assignee) Mitsubishi Electric Corp | Semiconductor device and method of fabricating the same | ▪ second etch stop layers ≈ adjacent pair ▪ first etch, etch process ≈ etching rate, high etching ▪ anti reflective coating ≈ d forming | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ discloses that a through c are inherently performed in an integrated processing system because a through c are a… ▪ teaches etching a plurality of contact holes in the overlayer having variations in thickness but does not mention… ▪ discloses an information storage medium which has a data area for recording stream data unit data packets V PCK and data… ▪ discloses a method of forming a dual damascene interconnect module over a deposition enhancing material comprising a… | X | X | X | X | X | X | X | ||||||||
| 15 | US20020079581A1 (Thomas Graettinger, 2002) | (Original Assignee) Graettinger Thomas M.; Gealy F. Daniel | Electrical contact for high dielectric constant capacitors and method for fabricating the same | ▪ spacer region ≈ interlevel dielectric layer ▪ interlevel dielectric, second interlevel dielectric ≈ high dielectric constant, bottom electrode ▪ multiple etch ≈ tungsten nitride ▪ metal layer coupling area ≈ conductive oxide ▪ second sub interlevel dielectric layer ≈ oxide material ▪ second etch stop layer, second etch stop layers ≈ gate stack ▪ anti reflective coating ≈ d forming ▪ first space ≈ said sub | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ discloses the spacing between the gate electrodes as being less than… ▪ discloses a method of making a capacitor contact formed by a self aligned method using insulating spacers formed on both… ▪ teaches a process in which a nitridation process is performed on a transition metal after a silicidation has been… ▪ discloses that the first barrier layer and the second barrier layer including the same material being at least one of… | X | X | X | X | X | X | X | X | X | X | X | X | |||
| 16 | US20020070401A1 (Hideki Takeuchi, 2002) | (Original Assignee) Nippon Steel Corp (Current Assignee) United Microelectronics Corp | Semiconductor storage device and method of fabricating thereof | ▪ metal layer coupling area ≈ upper electrodes, like shape ▪ etching process ≈ film thickness, uniform film | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(e) | ▪ discloses the spacing between the gate electrodes as being less than… ▪ teaches a semiconductor device comprising a first interlayer dielectric layer… ▪ teaches method of filling trenches discloses that etching process under power range of… ▪ discloses that the contact hole further including a bottom side the bottom side being positioned between the first side… | X | X | X | X | |||||||||||
| 17 | US20020093105A1 (Jeong-sic Jeon, 2002) | (Original Assignee) Samsung Electronics Co Ltd (Current Assignee) Samsung Electronics Co Ltd | Semiconductor device having a contact window and fabrication method thereof | ▪ multiple etch, etch process ≈ layer dielectric, wet etch ▪ etching process ≈ etching process ▪ anti reflective coating ≈ d forming | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ teaches that to reduce signal delay at interconnections a lm with a low dielectric is used such as… ▪ discloses a plasma etching method comprising plasma etching a lm… ▪ teaches an insulating lm stress in this range as recited in instant claim… ▪ discloses that using any one of the rare gases noble gases such as… | X | X | X | X | X | X | X | X | |||||||
| 18 | US20020048865A1 (H. Manning, 2002) | (Original Assignee) Manning H. Montgomery (Current Assignee) Round Rock Research LLC | Method of forming a local interconnect | ▪ substrate material ≈ substrate material ▪ second etch ≈ etch stop layer ▪ floating gate ≈ drain region ▪ anti reflective coating ≈ d forming | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) ▪ 35 U.S.C. 102(e) | ▪ discloses the claimed invention with the exception of depositing tantalum and oxidizing the tantalum and depositing the… ▪ discloses doping the rst plurality of active area in the peripheral portion and doping a second plurality of active… ▪ teaches the forming the landing pads and the central landing pad comprises forming a photoresist layer having openings… ▪ teaches that a capacitor is connected to a conductive storage nodeplug in a conventional memory device in order to… | X | X | X | X | X | X | X | X | X | ||||||
| 19 | US20020030219A1 (Masateru Ando, 2002) | (Original Assignee) NEC Corp (Current Assignee) Micron Memory Japan Ltd | Side wall contact structure and method of forming the same | ▪ interlevel dielectric ≈ storage capacitor ▪ floating gate ≈ second insulation ▪ anti reflective coating ≈ d forming | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ discloses the method of forming electrical contact for high dielectric constant capacitors… ▪ teaches a semiconductor structure fabrication method comprising FIG… ▪ discloses that the first barrier layer and the second barrier layer including the same material being at least one of… ▪ teaches an interconnect above the insulating layer and separated by a cavity from the insulating layer at column… | X | X | X | X | X | X | X | X | X | X | |||||
| 20 | US20020119623A1 (Byung-Jun Park, 2002) | (Original Assignee) Samsung Electronics Co Ltd (Current Assignee) Samsung Electronics Co Ltd | Dram device and method of manufacturing the same background of the invention | ▪ second etch stop layers ≈ silicon nitride layer ▪ etch process ≈ silicon oxide layer ▪ interlevel dielectric ≈ bit line contacts, contact plug ▪ second etch ≈ sacrificial layer, etch stop layer ▪ second sub interlevel dielectric layer ≈ oxide material ▪ metal layer coupling area, second interlevel dielectric layer ≈ said plate ▪ anti reflective coating ≈ d forming | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) ▪ 35 U.S.C. 102(e) | ▪ describes wherein the partial SAC etching process is carried out at a pressure of about… ▪ teaches forming a metal layer overlying the dielectric layer and in contact with the portions of the conductive layer… ▪ teaches the openings of the photoresist layer having an elliptical shape column… ▪ discloses a method for manufacturing a semiconductor device as shown below… | X | X | X | X | X | X | X | X | X | X | X | X | |||
| 21 | US20020079536A1 (Takashi Terauchi, 2002) | (Original Assignee) Mitsubishi Electric Corp (Current Assignee) Renesas Electronics Corp | Semiconductor device | ▪ interlevel dielectric, second interlevel dielectric ≈ interlayer insulating film ▪ first sub interlevel dielectric layer ≈ entire surface ▪ second space, floating gate ≈ storage node, drain region ▪ first space ≈ said sub | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ discloses that forming the expanded contact holes comprises anisotropically etching the second insulating layer to… ▪ teaches a low temperature chlorinated inorganic silicon nitride material TANAKA par… ▪ discloses the claimed invention except for the conductive layer made out of platinum but… ▪ teaches a first metal layer making a sourcedrain contact through a dielectric layer… | X | X | X | X | X | X | X | X | |||||||
| 22 | US20010024854A1 (Hideki Takeuchi, 2001) | (Original Assignee) Hideki Takeuchi; Hirohiko Izumi (Current Assignee) United Microelectronics Corp | Semiconductor storage device and method of fabricating thereof | ▪ metal layer coupling area ≈ upper electrodes, like shape ▪ etching process ≈ film thickness, uniform film | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(e) | ▪ discloses the spacing between the gate electrodes as being less than… ▪ teaches a semiconductor device comprising a first interlayer dielectric layer… ▪ teaches method of filling trenches discloses that etching process under power range of… ▪ discloses that the contact hole further including a bottom side the bottom side being positioned between the first side… | X | X | X | X | |||||||||||
| 23 | US20020008323A1 (Kenichi Watanabe, 2002) | (Original Assignee) Fujitsu Ltd (Current Assignee) TRINITY SEMICONDUCTOR RESEARCH GK | Semiconductor device with dual damascene wiring | ▪ metal layer coupling area ≈ cross sectional shape ▪ contact region ≈ second contact ▪ second etch, first etch ≈ hard mask, etch rates ▪ anti reflective coating ≈ d forming | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ discloses that different materials can be used for the etch stop layer and the insulating layers to provide a desired… ▪ teaches using protective metal structures in the scribe line near the corners of the chips… ▪ discloses the features of the claimed invention as discussed above but does not disclose the second insulator has a… ▪ discloses the electric conductive lm contains copper as a main component para… | X | X | X | X | X | X | X | X | X | X | X | X | X | X | |
| 24 | KR20020033881A (전정식, 2002) | (Original Assignee) 윤종용; 삼성전자 주식회사 | 접촉창을 갖는 반도체 장치 및 그 제조 방법 | ▪ second etch ≈ 부산물 ▪ second interlevel dielectric layer ≈ 연막의 | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ teaches that to reduce signal delay at interconnections a lm with a low dielectric is used such as… ▪ discloses a plasma etching method comprising plasma etching a lm… ▪ teaches an insulating lm stress in this range as recited in instant claim… ▪ discloses that using any one of the rare gases noble gases such as… | X | X | X | X | X | ||||||||||
| 25 | US6369446B1 (Yoshinori Tanaka, 2002) | (Original Assignee) Mitsubishi Electric Corp (Current Assignee) Renesas Electronics Corp | Multilayered semiconductor device | ▪ second etch, etch process ≈ said second circuit ▪ substrate material ≈ stacking direction, silicon oxide ▪ floating gate ≈ drain regions | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ teaches wherein the plurality of semiconductor structures memory cells form a pattern having a first pitch and wherein… ▪ describes a wet cleaning process to remove an excess material remaining and thereby form a sufficient opening area in… ▪ teaches that titanium nitride is an equivalent material to tungsten aluminum or copper for forming the conductive plug… ▪ teaches that a top surface of the bit line layers is coplanar with a top surface of the substrate… | X | X | X | X | X | X | |||||||||
| 26 | US6365504B1 (Wu Kuo Chien, 2002) | (Original Assignee) TSMC Acer Semiconductor Manufacturing Inc (Current Assignee) Taiwan Semiconductor Manufacturing Co TSMC Ltd | Self aligned dual damascene method | ▪ second etch stop layers ≈ second etch stop layers ▪ first etch stop layer ≈ first etch stop layer ▪ etching process ≈ etching process ▪ second space ≈ second space ▪ second range ≈ upper part ▪ contact bottom ≈ lower part ▪ anti reflective coating ≈ d forming | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(e) | ▪ teaches a method for forming a semiconductor device comprising forming a dielectric structure… ▪ discloses performing surface treatment on the siliconcontaminated surface portion of the silicon oxide layer using… ▪ teaches elements of the claimed invention above in the rejection of claim… | X | X | X | X | X | X | X | X | X | X | |||||
| 27 | US6083822A (Tze-Liang Lee, 2000) | (Original Assignee) Industrial Technology Research Institute ITRI (Current Assignee) Transpacific IP Ltd | Fabrication process for copper structures | ▪ second etch ≈ etch stop layer ▪ substrate material ≈ active ion ▪ anti reflective coating ≈ d forming | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(e) | ▪ teaches transition layer which has the same material as claimed invention therefore one ordinary in the art could… ▪ discloses a semiconductor structure comprising an insulating material… ▪ discloses various plasma reactors known in the art including capacitively coupled reactors and reactors using magnetic… ▪ teaches applying HF bias power to the lower electrode paragraphs… | X | X | X | X | X | X | |||||||||
| 28 | US6194301B1 (Carl Radens, 2001) | (Original Assignee) International Business Machines Corp (Current Assignee) International Business Machines Corp | Method of fabricating an integrated circuit of logic and memory using damascene gate structure | ▪ second interlevel dielectric layer, interlevel dielectric ≈ second interlevel dielectric layer, first interlevel ▪ first space ≈ trench isolation regions, first space ▪ second etch stop layers, floating gate ≈ second sidewall spacer, first sidewall spacer ▪ second etch, second sub ≈ second thickness ▪ etch process ≈ ion implantation ▪ second space ≈ second space ▪ anti reflective coating ≈ d forming | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ discloses performing a chemical mechanical polishing process CMP planarization… ▪ discloses the claimed invention with the exception of depositing tantalum and oxidizing the tantalum and depositing the… ▪ teaches each transistor having a gate structure with a highk dielectric… ▪ discloses wherein the notched structure of the second sidewall insulating layer is formed by HF cleaning… | X | X | X | X | X | X | X | X | X | X | X | X | |||
| 29 | JP2000340743A (Yoshinori Tanaka, 2000) | (Original Assignee) Mitsubishi Electric Corp; 三菱電機株式会社 | 半導体装置およびその製造方法 | ▪ interlevel dielectric, second interlevel dielectric layer ≈ 誘電体膜 ▪ second range ≈ あること, 境界近傍 ▪ metal layer coupling area ≈ 製造方法 ▪ electrical insulation ≈ の絶縁 ▪ first range ≈ 部近傍 | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ teaches wherein the plurality of semiconductor structures memory cells form a pattern having a first pitch and wherein… ▪ describes a wet cleaning process to remove an excess material remaining and thereby form a sufficient opening area in… ▪ teaches that titanium nitride is an equivalent material to tungsten aluminum or copper for forming the conductive plug… ▪ teaches that a top surface of the bit line layers is coplanar with a top surface of the substrate… | X | X | X | X | X | X | X | X | X | ||||||
| 30 | US6194304B1 (Yukio Morozumi, 2001) | (Original Assignee) Seiko Epson Corp (Current Assignee) Seiko Epson Corp | Semiconductor device and method of fabricating the same | ▪ etch process, multiple etch ≈ silicon oxide layer, layer dielectric ▪ substrate coupling area, metal layer coupling area ≈ silane compound ▪ anti reflective coating ≈ d forming | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(e) | ▪ discloses forming a wetting layer on the dielectric layer forming a metal wiring layer over the wetting layer and… ▪ describes a method of forming silicon and oxygen combined thin lms for superior crack resistance and insulation silicate… ▪ teaches an integrated circuit having formed therein a gap lling sandwich composite dielectric layer construction… ▪ teaches wherein the tensile and compressive stress is introduced by the selection of a known material having a high… | X | X | X | X | X | X | |||||||||
| 31 | US6348709B1 (Thomas M. Graettinger, 2002) | (Original Assignee) Micron Technology Inc (Current Assignee) Micron Technology Inc | Electrical contact for high dielectric constant capacitors and method for fabricating the same | ▪ spacer region ≈ interlevel dielectric layer ▪ interlevel dielectric, second interlevel dielectric ≈ high dielectric constant, bottom electrode ▪ multiple etch ≈ tungsten nitride ▪ metal layer coupling area ≈ conductive oxide ▪ substrate coupling area ≈ conductive bar | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ discloses the spacing between the gate electrodes as being less than… ▪ discloses a method of making a capacitor contact formed by a self aligned method using insulating spacers formed on both… ▪ teaches a process in which a nitridation process is performed on a transition metal after a silicidation has been… ▪ discloses that the first barrier layer and the second barrier layer including the same material being at least one of… | X | X | X | X | X | X | X | X | X | ||||||
| 32 | US6180494B1 (H. Montgomery Manning, 2001) | (Original Assignee) Micron Technology Inc (Current Assignee) Round Rock Research LLC | Integrated circuitry, methods of fabricating integrated circuitry, methods of forming local interconnects, and methods of forming conductive lines | ▪ substrate material ≈ substrate material ▪ anti reflective coating ≈ d forming | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) ▪ 35 U.S.C. 102(e) | ▪ discloses the claimed invention with the exception of depositing tantalum and oxidizing the tantalum and depositing the… ▪ discloses doping the rst plurality of active area in the peripheral portion and doping a second plurality of active… ▪ teaches the forming the landing pads and the central landing pad comprises forming a photoresist layer having openings… ▪ teaches that a capacitor is connected to a conductive storage nodeplug in a conventional memory device in order to… | X | X | X | ||||||||||||
| 33 | US6323557B1 (Thomas A. Figura, 2001) | (Original Assignee) Micron Technology Inc (Current Assignee) Micron Technology Inc | Method and structure for improved alignment tolerance in multiple, singulated plugs | ▪ contact region ≈ contact region, inner plug ▪ second etch stop layers ≈ adjacent pair | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(e) | ▪ teaches wherein the sidewall spacer can be etched in the contact region… ▪ discloses a semiconductor chip package comprising a substrate… ▪ teaches that a semiconductor device interlayer insulating film formed over a gate electrode can comprise silicon oxide… ▪ discloses a critical dimension of the firstlayer contact is substantially similar to a critical dimension of the… | X | X | X | X | X | X | X | X | |||||||
| 34 | US20010012688A1 (Masaki Kawaguchi, 2001) | (Original Assignee) NEC Corp (Current Assignee) NEC Corp | Process for forming miniature contact holes in semiconductor device without short-circuit | ▪ interlevel dielectric, second interlevel dielectric ≈ contact hole ▪ second space, floating gate ≈ storage node | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ teaches the features detailed previously but lack a discussion on method wherein the photolithography process includes… ▪ discloses the isotropic etching is performed using a mixture of oxygen… ▪ discloses the claimed invention except for explicitly showing a MOS transistor… ▪ discloses process of forming closely spaced metallic lines on a semiconductor substrate forming a cap layer on the lines… | X | X | X | X | X | X | X | X | |||||||
| 35 | US6693335B2 (Fernando Gonzalez, 2004) | (Original Assignee) Micron Technology Inc (Current Assignee) Micron Technology Inc | Semiconductor raised source-drain structure | ▪ floating gate ≈ semiconductor structure ▪ etch process ≈ dielectric material ▪ etching process ≈ doped polysilicon | X | X | X | ||||||||||||||
| 36 | US6162676A (Hidemitsu Mori, 2000) | (Original Assignee) NEC Corp (Current Assignee) NEC Electronics Corp | Method of making a semiconductor device with an etching stopper | ▪ second etch stop layer, second interlevel dielectric layer ≈ insulating film ▪ first sub interlevel dielectric layer ≈ entire surface ▪ contact region ≈ second contact ▪ spacer region ≈ inner surfaces ▪ second etch ≈ second etch | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ discloses the claimed invention except for explicitly showing a MOS transistor… ▪ discloses the isotropic etching is performed using a mixture of oxygen… ▪ teaches etching using laser ablation the dielectric layer will be exposed to different temperatures since there are… ▪ discloses wherein the barrier layer ESM has an electrical resistivity less than about… | X | X | X | X | X | X | X | X | X | X | X | ||||
| 37 | US6255686B1 (Hideki Takeuchi, 2001) | (Original Assignee) Nippon Steel Corp (Current Assignee) United Microelectronics Corp | Semiconductor storage device including short circuit avoiding structure and method of fabricating thereof | ▪ first etch, first etch stop layer ≈ isolation structure ▪ metal layer coupling area ≈ upper electrodes, like shape ▪ contact bottom ≈ lower electrode ▪ contact region ≈ second contact | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(e) | ▪ discloses the spacing between the gate electrodes as being less than… ▪ teaches a semiconductor device comprising a first interlayer dielectric layer… ▪ teaches method of filling trenches discloses that etching process under power range of… ▪ discloses that the contact hole further including a bottom side the bottom side being positioned between the first side… | X | X | X | X | X | X | X | X | X | X | X | ||||
| 38 | JPH11168199A (Hideki Takeuchi, 1999) | (Original Assignee) Nippon Steel Corp; 新日本製鐵株式会社 | 半導体記憶装置及びその製造方法 | ▪ interlevel dielectric, second interlevel dielectric layer ≈ キャパシタ, 誘電体膜 ▪ second sub interlevel dielectric layer ≈ 少なくとも ▪ second range ≈ あること ▪ metal layer coupling area ≈ 製造方法 ▪ first space ≈ 前記保 | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(e) | ▪ discloses the spacing between the gate electrodes as being less than… ▪ teaches a semiconductor device comprising a first interlayer dielectric layer… ▪ teaches method of filling trenches discloses that etching process under power range of… ▪ discloses that the contact hole further including a bottom side the bottom side being positioned between the first side… | X | X | X | X | X | X | X | X | X | ||||||
| 39 | JPH1174352A (Michio Asahina, 1999) | (Original Assignee) Seiko Epson Corp; セイコーエプソン株式会社 | 半導体装置およびその製造方法 | ▪ second sub interlevel dielectric layer ≈ 少なくとも ▪ electrical insulation ≈ なる第２ ▪ metal layer coupling area ≈ 製造方法 ▪ substrate coupling area ≈ 前記層 ▪ etching process ≈ １００ | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(e) | ▪ discloses forming a wetting layer on the dielectric layer forming a metal wiring layer over the wetting layer and… ▪ describes a method of forming silicon and oxygen combined thin lms for superior crack resistance and insulation silicate… ▪ teaches an integrated circuit having formed therein a gap lling sandwich composite dielectric layer construction… ▪ teaches wherein the tensile and compressive stress is introduced by the selection of a known material having a high… | X | X | X | X | X | X | X | X | |||||||
| 40 | CN1195192A (荣森贵尚, 1998) | (Original Assignee) 三菱电机株式会社 | 半导体器件及其制造方法 | ▪ etch process, lithography process ≈ 的工艺 ▪ substrate material ≈ 层形成 ▪ contact bottom ≈ 的接触 | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ discloses that a through c are inherently performed in an integrated processing system because a through c are a… ▪ teaches etching a plurality of contact holes in the overlayer having variations in thickness but does not mention… ▪ discloses an information storage medium which has a data area for recording stream data unit data packets V PCK and data… ▪ discloses a method of forming a dual damascene interconnect module over a deposition enhancing material comprising a… | X | X | |||||||||||||
| 41 | US6187671B1 (Mitsugu Irinoda, 2001) | (Original Assignee) Ricoh Co Ltd (Current Assignee) Ricoh Co Ltd | Method of forming semiconductor device having minute contact hole | ▪ etching process ≈ doped polysilicon, uniform thickness ▪ interlevel dielectric, second interlevel dielectric ≈ contact hole ▪ first etch, etch process ≈ etching rate | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ discloses wherein the selectively ablating portions of the barrier layer ESM includes selectively radiating a first… ▪ teaches that it is well known in the art to form a contact plug… ▪ discloses the isotropic etching is performed using a mixture of oxygen… ▪ teaches to control the flow rate ratio of each gas paragraph… | X | X | X | X | X | X | X | X | X | ||||||
| 42 | US20020056913A1 (Takahisa Eimori, 2002) | (Original Assignee) Mitsubishi Electric Corp (Current Assignee) Renesas Electronics Corp | Semiconductor device and method of fabricating the same | ▪ second etch stop layers ≈ adjacent pair ▪ first etch, etch process ≈ etching rate, high etching ▪ anti reflective coating ≈ d forming | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ discloses that a through c are inherently performed in an integrated processing system because a through c are a… ▪ teaches etching a plurality of contact holes in the overlayer having variations in thickness but does not mention… ▪ discloses an information storage medium which has a data area for recording stream data unit data packets V PCK and data… ▪ discloses a method of forming a dual damascene interconnect module over a deposition enhancing material comprising a… | X | X | X | X | X | X | X | ||||||||
| 43 | US5912188A (Mark I. Gardner, 1999) | (Original Assignee) Advanced Micro Devices Inc (Current Assignee) Lone Star Silicon Innovations LLC | Method of forming a contact hole in an interlevel dielectric layer using dual etch stops | ▪ first etch, interlevel dielectric ≈ local interconnect, first etch ▪ second etch ≈ second etch, gate oxide ▪ anti reflective coating ≈ d forming | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ discloses that a through c are inherently performed in an integrated processing system because a through c are a… ▪ teaches a method for fabricating a nitride spacer of a gate structure A rst etch process may be performed using a rst… ▪ teaches wherein the tensile and compressive stress is introduced by the selection of a known material having a high… ▪ discloses use of a lowk material that is an doped oxide is used as an interlayer dielectric layer of a semiconductor… | X | X | X | X | X | X | X | X | X | X | X | ||||
| 44 | US6078073A (Mariko Habu, 2000) | (Original Assignee) Toshiba Corp (Current Assignee) Toshiba Corp | Semiconductor apparatus formed by SAC (self-aligned contact) method and manufacturing method therefor | ▪ first etch stop layer ≈ fourth insulating ▪ spacer region ≈ gate electrodes ▪ first etch, etch process ≈ etching rate ▪ second sub interlevel dielectric layer ≈ second film | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ teaches a method of fabricating a semiconductor device abstract A device isolation region and an active region are… ▪ teaches the above outlined features except for wherein the second insulating layer is a spin on glass layer… ▪ teaches that the method could be used for both positive and negative photoresists column… ▪ discloses conducting the steps of etching the fourth insulator lm to form therein a contact hole by using the sidewall… | X | X | X | X | X | X | X | X | |||||||
| 45 | JPH10270555A (Takahisa Sakaemori, 1998) | (Original Assignee) Mitsubishi Electric Corp; 三菱電機株式会社 | 半導体装置及びその製造方法 | ▪ second sub interlevel dielectric layer ≈ 少なくとも ▪ metal layer coupling area ≈ 製造方法 | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ discloses that a through c are inherently performed in an integrated processing system because a through c are a… ▪ teaches etching a plurality of contact holes in the overlayer having variations in thickness but does not mention… ▪ discloses an information storage medium which has a data area for recording stream data unit data packets V PCK and data… ▪ discloses a method of forming a dual damascene interconnect module over a deposition enhancing material comprising a… | X | X | X | X | X | X | X | ||||||||
| 46 | US5808365A (Hidemitsu Mori, 1998) | (Original Assignee) NEC Corp (Current Assignee) NEC Electronics Corp | Semiconductor device and method of manufacturing the same | ▪ first sub, first sub interlevel dielectric layer ≈ upper surfaces ▪ contact region ≈ second contact ▪ second space, floating gate ≈ storage node ▪ second etch ≈ second etch | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ discloses the claimed invention except for explicitly showing a MOS transistor… ▪ discloses the isotropic etching is performed using a mixture of oxygen… ▪ teaches etching using laser ablation the dielectric layer will be exposed to different temperatures since there are… ▪ discloses wherein the barrier layer ESM has an electrical resistivity less than about… | X | X | X | X | X | X | X | X | X | X | X | X | |||
| 47 | US5726499A (Mitsugu Irinoda, 1998) | (Original Assignee) Ricoh Co Ltd (Current Assignee) Ricoh Co Ltd | Semiconductor device having a minute contact hole | ▪ multiple etch stop insulation layer, multiple etch ≈ second insulating layers, dry etch ▪ substrate coupling area ≈ second conductive layer ▪ etching process ≈ doped polysilicon, etching process ▪ interlevel dielectric, second interlevel dielectric ≈ upper electrode ▪ contact region, spacer region ≈ second regions | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ discloses wherein the selectively ablating portions of the barrier layer ESM includes selectively radiating a first… ▪ teaches that it is well known in the art to form a contact plug… ▪ discloses the isotropic etching is performed using a mixture of oxygen… ▪ teaches to control the flow rate ratio of each gas paragraph… | X | X | X | X | X | X | X | X | X | ||||||
| 48 | JPH09191084A (Hidemitsu Mori, 1997) | (Original Assignee) Nec Corp; 日本電気株式会社 | 半導体装置及びその製造方法 | ▪ substrate material ≈ ウォール ▪ metal layer coupling area ≈ 製造方法 ▪ electrical insulation ≈ の絶縁 | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ discloses the claimed invention except for explicitly showing a MOS transistor… ▪ discloses the isotropic etching is performed using a mixture of oxygen… ▪ teaches etching using laser ablation the dielectric layer will be exposed to different temperatures since there are… ▪ discloses wherein the barrier layer ESM has an electrical resistivity less than about… | X | X | X | X | |||||||||||
| 49 | US5663097A (Masaru Sakamoto, 1997) | (Original Assignee) Canon Inc (Current Assignee) Canon Inc | Method of fabricating a semiconductor device having an insulating side wall | ▪ second etch stop layer, second interlevel dielectric layer ≈ insulating film ▪ first sub interlevel dielectric layer ≈ bottom wall | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ discloses a method for fabricating a MOS transistor in a semiconductor device… ▪ discloses that forming the expanded contact holes comprises anisotropically etching the second insulating layer to… ▪ teaches conventional surface preparation ie roughening of the base layer to ensure proper contamination removal and… ▪ teaches the features detailed previously but fails to teach lling the openings formed in the dielectric layer with a… | X | X | X | X | X | X | X | ||||||||
| 50 | US5317193A (Shinya Watanabe, 1994) | (Original Assignee) Mitsubishi Electric Corp (Current Assignee) Mitsubishi Electric Corp | Contact via for semiconductor device | ▪ interlevel dielectric, second interlevel dielectric ≈ upper electrode ▪ first sub interlevel dielectric layer ≈ entire surface ▪ contact region ≈ second contact ▪ etching process ≈ alloy layer | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(e) | ▪ discloses a method of forming a memory device said method comprising simultaneously forming a series of single memory… ▪ teaches an integrated process ow involving a patterned photoresist layer… ▪ teaches that pressure temperature gas ow and power may be varied for control of the etch rate and etch selectivity see… ▪ teaches of a method of fabricating a semiconductor device wherein a second opening is a tapered opening… | X | X | X | X | X | X | X | X | X | X | X | ||||
| 51 | JPH05315457A (Shinya Watabe, 1993) | (Original Assignee) Mitsubishi Electric Corp; 三菱電機株式会社 | 半導体装置およびその製造方法 | ▪ first sub interlevel dielectric layer ≈ ドライエッチング速度 ▪ metal layer coupling area ≈ 製造方法 ▪ substrate coupling area ≈ 前記層 | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(e) | ▪ discloses a method of forming a memory device said method comprising simultaneously forming a series of single memory… ▪ teaches an integrated process ow involving a patterned photoresist layer… ▪ teaches that pressure temperature gas ow and power may be varied for control of the etch rate and etch selectivity see… ▪ teaches of a method of fabricating a semiconductor device wherein a second opening is a tapered opening… | X | X | X | X | X | X | X | ||||||||
| 52 | US5116779A (Katsuji Iguchi, 1992) | (Original Assignee) Sharp Corp (Current Assignee) Sharp Corp | Process for forming semiconductor device isolation regions | ▪ second interlevel dielectric layer ≈ minimum width ▪ substrate material ≈ silicon oxide ▪ first sub interlevel dielectric layer ≈ bottom wall | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ discloses a method for fabricating STI comprises the steps of using doped polysilicon as conductive material and forming… ▪ teaches alternative gasses it would have been obvious to one of ordinary skill in the art at the time of the invention… | X | X | X | X | X | X | X | ||||||||
| 53 | US20040161923A1 (In-deog Bae, 2004) | (Original Assignee) Samsung Electronics Co Ltd (Current Assignee) Samsung Electronics Co Ltd | Method for forming wire line by damascene process using hard mask formed from contacts | ▪ substrate coupling area ≈ second conductive layer ▪ spacer region ≈ conducting layer ▪ substrate material ≈ silicon oxide ▪ etch process ≈ etch process ▪ anti reflective coating ≈ d forming | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ teaches method of filling trenches discloses that etching process under power range of… ▪ discloses conducting the steps of etching the fourth insulator lm to form therein a contact hole by using the sidewall… ▪ discloses process of forming closely spaced metallic lines on a semiconductor substrate forming a cap layer on the lines… ▪ teaches that it is bene cial to etch the top cap layer on the metallic lines to narrow its width prior to depositing… | X | X | X | X | X | X | X | ||||||||
| 54 | US20040152256A1 (Junji Noguchi, 2004) | (Original Assignee) Renesas Technology Corp (Current Assignee) Renesas Electronics Corp | Semiconductor device manufacturing method | ▪ floating gate ≈ second insulation ▪ second interlevel dielectric, first sub interlevel dielectric layer ≈ bottom electrode ▪ anti reflective coating ≈ d forming | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) ▪ 35 U.S.C. 102(e) | ▪ discloses forming a multilayer dielectric layer over the plug and forming the trench using dual damascene… ▪ teaches wherein the plurality of metal films have a structure in which a cap metal film… ▪ discloses that a through c are inherently performed in an integrated processing system because a through c are a… ▪ discloses a method of forming a dual damascene interconnect module over a deposition enhancing material comprising a… | X | X | X | X | X | X | X | X | X | ||||||
| 55 | CN1519914A (崔亨福, 2004) | (Original Assignee) 海力士半导体有限公司 | 电容器及其制备方法 | ▪ second etch stop layers ≈ 形成一绝缘层 ▪ multiple etch stop insulation layer ≈ 绝缘层上 ▪ contact bottom ≈ 底部区域, 的接触 ▪ first etch stop layer, second etch stop layer ≈ 在第一 ▪ substrate material ≈ 层形成 | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ discloses the polysilicon layer being doped with arsenic to a concentration between about… ▪ discloses the method wherein contouring at least one isolation layer… ▪ discloses all the limitations of claims except for forming conductive material over the substrate comprising conductive… ▪ teaches forming a seam inside the first through hole by causing an overhang at an entrance of the first through hole… | X | X | X | X | X | X | |||||||||
| 56 | US20040155340A1 (Tamotsu Owada, 2004) | (Original Assignee) Fujitsu Ltd | Silicon oxycarbide, growth method of silicon oxycarbide layer, semiconductor device and manufacture method for semiconductor device | ▪ contact bottom ≈ silicon carbide ▪ substrate material ≈ silicon oxide ▪ etching process ≈ copper wiring ▪ anti reflective coating ≈ d forming ▪ multiple etch, etch process ≈ low rate | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(e) | ▪ discloses the claimed invention except for the concentration of carbon and the depth of carbon inside the first… ▪ discloses the structure wherein the dielectric constant of the low dielectric layer… ▪ discloses a method of enhancing interracial adhesion between layers comprising see… ▪ teaches the interlayer insulation film of a conductor layer positioned at an upper layer part… | X | X | X | X | X | X | |||||||||
| 57 | US20040119164A1 (Nobuyuki Kurashima, 2004) | (Original Assignee) Toshiba Corp (Current Assignee) Toshiba Corp | Semiconductor device and its manufacturing method | ▪ contact region, contact bottom ≈ predetermined value, two layers ▪ substrate coupling area, metal layer coupling area ≈ adjacent layers ▪ substrate material ≈ plane view | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ discloses a semiconductor die having a substantially rectangular shape and a scribe region along the outer circumference… ▪ teaches wherein said another insulating film is composed of… ▪ discloses that antireflection layers may be formed from a silicon oxygen carbon and nitrogen… ▪ teaches making a plurality of holes by selectively etching the film to be processed… | X | X | X | X | X | X | X | X | X | ||||||
| 58 | JP2004096080A (Hyun Dam Jeong, 2004) | (Original Assignee) Samsung Electronics Co Ltd; 三星電子株式会社 | 金属間絶縁膜のパターン形成方法 | ▪ first etch ≈ エッチング後 ▪ second range ≈ あること ▪ substrate coupling area ≈ 前記層 ▪ etching process ≈ １００ | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ teaches that after removal of a photoresist implanted with ions KUNIKIYO column… ▪ teaches a broadband ultraviolet ray within a wavelength range from about… ▪ teaches a method for manufacturing a semiconductor device comprising the step of irradiating the damage region with UV… ▪ discloses forming a metal barrier layer on said passivation layer and said insulation layer conformal with said feature… | X | X | X | X | X | X | X | X | X | ||||||
| 59 | US6777291B2 (Paul J. Rudeck, 2004) | (Original Assignee) Micron Technology Inc (Current Assignee) Micron Technology Inc | Methods of forming programmable memory devices comprising tungsten | ▪ contact bottom ≈ two layers ▪ anti reflective coating ≈ d forming | X | X | X | ||||||||||||||
| 60 | US20040046251A1 (Seung-Whan Lee, 2004) | (Original Assignee) Samsung Electronics Co Ltd (Current Assignee) Samsung Electronics Co Ltd | Semiconductor contact structure and method of forming the same | ▪ first range ≈ predetermined region ▪ etching process ≈ undercut region ▪ interlevel dielectric ≈ contact plug ▪ anti reflective coating ≈ d forming ▪ first space ≈ said sub | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ discloses the claimed invention except for the cavity being larger than an aperture of the orifice… ▪ teaches that it is well known in the art to form a contact plug… ▪ teaches said first and second dielectric materials comprise the same or different low k dielectric having a dielectric… ▪ discloses a method of fabricating an integrated circuit chip comprising an integrated circuit and an electrostatic… | X | X | X | X | X | X | X | X | X | X | X | ||||
| 61 | CN1445838A (钵嶺清太, 2003) | (Original Assignee) 株式会社日立制作所; 日立超大规模集成电路系统株式会社 | 半导体器件及其制造方法 | ▪ first etch stop layer ≈ 形成第一 ▪ substrate material ≈ 氮化硅膜 ▪ floating gate ≈ 栅极侧壁 | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) ▪ 35 U.S.C. 102(e) | ▪ teaches the above modification is used to adjust threshold voltage of the device… ▪ discloses several surface and channel orientation combinations col… ▪ discloses all the subject matter claimed except for the limitation wherein a surface of the single crystal semiconductor… ▪ discloses the first dielectric layer comprises multiple layers… | X | X | X | X | X | X | |||||||||
| 62 | US20040157392A1 (Ming-Yin Hao, 2004) | (Original Assignee) United Microelectronics Corp (Current Assignee) United Microelectronics Corp | Capacitor in an interconnect system and method of manufacturing thereof | ▪ floating gate ≈ amorphous silicon layer ▪ substrate coupling area ≈ second conductive layer ▪ second etch stop layer ≈ second etch stop layer ▪ first etch stop layer ≈ first etch stop layer ▪ interlevel dielectric, second interlevel dielectric ≈ capacitor structure, oxide material ▪ etch process ≈ dielectric material ▪ contact bottom ≈ silicon carbide ▪ anti reflective coating ≈ d forming | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ discloses various selective etch methods utilizing an etch chemistry where various layers such as cap dielectrics… ▪ discloses a copper sulfate solution with deposition accelerators is used as electrolyte col… ▪ discloses a capacitor region having a rst aspect ratio and an interconnect region connected thereto and having a second… ▪ teaches that the first and second electrode contacting lines… | X | X | X | X | X | X | X | X | X | X | X | X | X | ||
| 63 | US20040152268A1 (Kwo Chu, 2004) | (Original Assignee) Taiwan Semiconductor Manufacturing Co TSMC Ltd (Current Assignee) Taiwan Semiconductor Manufacturing Co TSMC Ltd | Novel method of fabricating split gate flash memory cell without select gate-to-drain bridging | ▪ second etch stop layer, second etch stop layers ≈ oxide insulating layer, gate stack ▪ etch process ≈ ion implantation ▪ contact region ≈ contact region ▪ etching process ≈ film thickness ▪ substrate material ≈ silicon oxide ▪ floating gate ≈ floating gate, drain regions ▪ isolates guidance ≈ forming two ▪ metal layer coupling area ≈ said stack ▪ anti reflective coating ≈ d forming ▪ first space ≈ said sub | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) ▪ 35 U.S.C. 102(e) | ▪ teaches the nonvolatile semiconductor memory device according to claim… ▪ discloses the shift threshold voltage are calculated based on the two neighboring state see paragraph… | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X |
| 64 | JP2004221104A (Mitsuru Sekiguchi, 2004) | (Original Assignee) Matsushita Electric Ind Co Ltd; 松下電器産業株式会社 | 半導体装置とその製造方法 | ▪ second sub interlevel dielectric layer ≈ 少なくとも ▪ metal layer coupling area ≈ 製造方法 ▪ second range ≈ あること ▪ interlevel dielectric ≈ 膜密度 | X | X | X | X | X | X | X | X | X | ||||||||
| 65 | US20040014278A1 (Sung-Kwon Lee, 2004) | (Original Assignee) SK Hynix Inc (Current Assignee) SK Hynix Inc | Method for fabricating semiconductor device | ▪ substrate coupling area ≈ second conductive layer ▪ second etch stop layers ≈ silicon nitride layer ▪ multiple etch ≈ tungsten nitride ▪ interlevel dielectric, second interlevel dielectric ≈ contact hole, mixed gas ▪ contact bottom ≈ top portion ▪ anti reflective coating ≈ d forming | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(e) | ▪ discloses a method for manufacturing a semiconductor device as shown below… ▪ discloses performing surface treatment on a planarized insulating layer wherein the surface treatment is carried out by… ▪ teaches the occurrence of shorts between the storage node contact plugs and bit lines are greatly reduced and… ▪ discloses forming sidewall protective lm on a sidewall of said separation slot but does not disclose forming a sidewall… | X | X | X | X | X | X | X | X | X | X | |||||
| 66 | JP2003174144A (Roberto Bez, 2003) | (Original Assignee) Ovonyx Inc; Stmicroelectronics Srl; エスティーマイクロエレクトロニクス エス．アール．エル; オヴォニクス インコーポレイテッド | 半導体装置における微小コンタクト領域、高性能相変化メモリセル及びその製造方法 | ▪ contact region ≈ 前記第１方向, 接触面 ▪ second sub interlevel dielectric layer ≈ 少なくとも ▪ first space ≈ モールド ▪ second range ≈ あること ▪ multiple etch stop insulation layer ≈ コレクタ ▪ electrical insulation ≈ の絶縁 ▪ etching process ≈ １００ | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(e) | ▪ discloses wherein the bridge comprises a thin film having a bridge length less than… ▪ discloses forming a top emitter interface on each memory cell… ▪ discloses that the trench has a width that extends over at least respective portion of two cells and has a depth such… ▪ teaches a digital CVD method that uses purge to eliminate process gases from the chamber between steps column… | X | X | X | X | X | X | X | X | X | X | X | ||||
| 67 | JP2003229482A (Choon Kun Ryu, 2003) | (Original Assignee) Hynix Semiconductor Inc; 株式会社ハイニックスセミコンダクター | 半導体素子の銅配線形成方法 | ▪ interlevel dielectric ≈ ハードマスク ▪ other regions ≈ さまた | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ teaches the conventionality of using titanium silicon nitride for titanium nitride… ▪ teaches that a barrier material may be formed between the photoresist and dielectric column… ▪ discloses other layers within a semiconductor device having high aspect ratio gaps of five or more… ▪ teaches a method of forming a trench isolation as described in claim… | X | X | X | X | X | X | X | ||||||||
| 68 | JP2004186452A (Masaru Hisamoto, 2004) | (Original Assignee) Renesas Technology Corp; 株式会社ルネサステクノロジ | 不揮発性半導体記憶装置およびその製造方法 | ▪ multiple etch stop insulation layer ≈ 前記電圧 ▪ second range ≈ あること ▪ first range ≈ 範囲内 | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) ▪ 35 U.S.C. 102(e) | ▪ discloses a silicon oxynitride tunnel layer with a refractive index below… ▪ discloses explicitly wherein the first select gate comprises a second gate conductor layer… ▪ teaches in a very similar device the option to use metal to form a select gate rather than typical polysilicon… ▪ discloses a nonvolatile memory cell having an electrically rewritable memory cell the memory cell has third and fourth… | X | X | X | X | |||||||||||
| 69 | KR20040038422A (이세호, 2004) | (Original Assignee) 삼성전자주식회사 | 상변환 기억소자 및 그 제조방법 | ▪ spacer region ≈ 콘택홀이 ▪ second etch stop layers ≈ low region ▪ second interlevel dielectric layer ≈ 연막의 | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) ▪ 35 U.S.C. 102(e) | ▪ teaches that it was known to use an oxide or nitride as the material for an insulator in a phase change memory device… ▪ discloses a method for manufacturing a phase change memory device comprising the steps of forming a first insulation… ▪ teaches a phase change layer compositionally graded with more than two alloys… ▪ discloses a magnetic memory having a junction area of a nonmagnetic conductive material of… | X | X | X | ||||||||||||
| 70 | JP2004146442A (Takashi Fujimura, 2004) | (Original Assignee) Toshiba Corp; 株式会社東芝 | 薄膜トランジスタ及び薄膜トランジスタの製造方法 | ▪ second sub interlevel dielectric layer ≈ 少なくとも ▪ metal layer coupling area ≈ 製造方法 ▪ substrate coupling area ≈ 前記層 | X | X | X | X | X | X | X | ||||||||||
| 71 | US6777305B2 (Kee-jeung Lee, 2004) | (Original Assignee) SK Hynix Inc (Current Assignee) SK Hynix Inc | Method for fabricating semiconductor device | ▪ etching process, multiple etch ≈ doped polysilicon, hard mask ▪ first sub interlevel dielectric layer ≈ entire surface ▪ interlevel dielectric, second interlevel dielectric ≈ contact hole, opening part ▪ metal layer coupling area ≈ RF power | X | X | X | X | X | X | X | X | X | X | |||||||
| 72 | US6737310B2 (Chaochieh Tsai, 2004) | (Original Assignee) Taiwan Semiconductor Manufacturing Co TSMC Ltd (Current Assignee) Taiwan Semiconductor Manufacturing Co TSMC Ltd | Self-aligned process for a stacked gate RF MOSFET device | ▪ interlevel dielectric, spacer region ≈ interlevel dielectric, first interlevel ▪ second etch stop layers ≈ silicon nitride layer ▪ etch process ≈ silicon oxide layer ▪ floating gate ≈ drain region ▪ contact bottom ≈ top portion ▪ anti reflective coating ≈ d forming | X | X | X | X | X | X | X | X | X | X | X | X | |||||
| 73 | JP2004047873A (Yoshihiro Hayashi, 2004) | (Original Assignee) Nec Corp; 日本電気株式会社 | 有機シロキサン共重合体膜、その製造方法、成長装置、ならびに該共重合体膜を用いた半導体装置 | ▪ etch process ≈ 付ける工程と ▪ second sub interlevel dielectric layer ≈ 少なくとも | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(e) | ▪ discloses a method of forming a silicon oxide layer including using an organosilane gas col… ▪ discloses a substrate exposure sequence comprising splitting the fields of a substrate into an inner portion and an… ▪ discloses that the outer target portions are divided into four groups so that they can be exposed in a particular order… ▪ teaches that viascontacts are part of an integrated circuit and… | X | X | X | X | X | X | X | ||||||||
| 74 | KR20040003948A (서문식, 2004) | (Original Assignee) 주식회사 하이닉스반도체 | 반도체소자의 ｍｏｓ 트랜지스터 제조방법 | ▪ contact region ≈ 반도체소자의 ▪ critical dimension ≈ 페이스는 ▪ spacer region ≈ 산화막을 ▪ floating gate ≈ 절연막 | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ discloses a first transistor has a breakdown voltage that is different from a breakdown voltage of a second transistor… ▪ discloses wherein each of the two gate electrodes comprises a gate electrode stack including a floating gate… ▪ teaches an NMOS transistor as part of a memory device with LDD regions to suppress short channel effects col… | X | X | X | X | X | X | X | X | X | ||||||
| 75 | US20020195686A1 (Do-hyung Kim, 2002) | (Original Assignee) Samsung Electronics Co Ltd (Current Assignee) Samsung Electronics Co Ltd | Semiconductor device having shared contact and fabrication method thereof | ▪ etching process ≈ etching process ▪ first sub interlevel dielectric layer ≈ entire surface ▪ contact region ≈ contact region ▪ substrate material ≈ silicon oxide ▪ floating gate ≈ drain regions ▪ interlevel dielectric, second interlevel dielectric ≈ contact hole ▪ anti reflective coating ≈ d forming | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ teaches polysilicon gate made of grains wherein the first gate electrode… ▪ teaches the method of fabricating semiconductor device of claim… ▪ teaches forming sidewall spacers and forming an LDD region using the isolation layer as a spacer… ▪ discloses a critical dimension of the firstlayer contact is substantially similar to a critical dimension of the… | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X |
| 76 | KR20020067664A (히노요시노리, 2002) | (Original Assignee) 산요 덴키 가부시키가이샤 | 반도체 장치 및 그 제조 방법 | ▪ spacer region ≈ 산화막을 ▪ etch process ≈ 이외의 ▪ second interlevel dielectric layer ≈ 연막의 ▪ floating gate ≈ 절연막 | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(e) | ▪ teaches the acts of depositing comprise sputter deposition col… ▪ teaches conventional thicknesses for barrier layers including WN in integrated circuits… ▪ discloses a critical dimension of the firstlayer contact is substantially similar to a critical dimension of the… ▪ teaches a staggered guard ring structure wherein said IC chip comprises a plurality of lLD lLD interfaces and wherein… | X | X | X | X | X | ||||||||||
| 77 | JP2003188386A (Kazuhide Koyama, 2003) | (Original Assignee) Sony Corp; ソニー株式会社 | 半導体装置およびその製造方法 | ▪ first etch ≈ オーバーエッチング ▪ second range ≈ あること ▪ metal layer coupling area ≈ 製造方法 ▪ substrate material ≈ ウォール ▪ substrate coupling area ≈ 前記層 | X | X | X | X | X | X | X | X | |||||||||
| 78 | JP2002141412A (Barbara Hasler, 2002) | (Original Assignee) Infineon Technologies Ag; インフィネオン テクノロジース アクチエンゲゼルシャフト | 導電性結線の製造法 | ▪ second etch ≈ １．５〜４ ▪ second sub interlevel dielectric layer ≈ 少なくとも ▪ electrical insulation ≈ 絶縁層, の絶縁 | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) ▪ 35 U.S.C. 102(e) | ▪ teaches a device wherein the set of conductive vias includes a padless via padless vias… ▪ teaches the inorganic filler could added in the thermosetting resin see claim… ▪ discloses the exrigid wiring board having all of the claimed features as discussed above with respect claim… ▪ discloses a method for manufacturing a printed circuit board abstract the method comprising preparing a base substrate… | X | X | X | X | X | X | X | ||||||||
| 79 | CN1333568A (八木下淳史, 2002) | (Original Assignee) 株式会社东芝 | 半导体器件及其制造方法 | ▪ etching process ≈ 的半导体衬底 ▪ first etch stop layer ≈ 形成第一 ▪ critical dimension ≈ 肖特基结 ▪ first sub interlevel dielectric layer ≈ 的界面 | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ discloses that nitrogen doped Y stabilized zirconium oxide has anomolously large resistance which is related to… ▪ discloses wherein the gate insulator is a highk dielecitric including titanium dioxide… ▪ discloses after forming the contact sacrificial pattern the method further comprises forming a lightlydoped sourcedrain… ▪ discloses a method for fabricating a semiconductor memory device in and on a semiconductor substrate… | X | X | X | X | X | X | X | X | X | ||||||
| 80 | US6653739B2 (Takashi Terauchi, 2003) | (Original Assignee) Mitsubishi Electric Corp (Current Assignee) Renesas Electronics Corp | Semiconductor device | ▪ interlevel dielectric, second interlevel dielectric ≈ interlayer insulating film ▪ first sub interlevel dielectric layer ≈ entire surface ▪ second space, floating gate ≈ storage node, drain region ▪ first space ≈ said sub | X | X | X | X | X | X | X | X | |||||||||
| 81 | JP2003017664A (Eiji Fujii, 2003) | (Original Assignee) Matsushita Electric Ind Co Ltd; 松下電器産業株式会社 | 半導体装置の製造方法 | ▪ second interlevel dielectric, interlevel dielectric ≈ ペロブスカイト構造, 容量絶縁膜 ▪ second range ≈ あること ▪ metal layer coupling area ≈ 製造方法, ７００ ▪ etching process ≈ 酸化物層 | X | X | X | X | X | X | X | X | X | X | |||||||
| 82 | US6514805B2 (Daniel Xu, 2003) | (Original Assignee) Intel Corp (Current Assignee) Micron Technology Inc | Trench sidewall profile for device isolation | ▪ etch process ≈ dielectric material ▪ floating gate ≈ first trenches ▪ anti reflective coating ≈ d forming | X | X | X | X | |||||||||||||
| 83 | JP2003017467A (Hiroyuki Enomoto, 2003) | (Original Assignee) Thin Film Research Center, Hitachi''s Central Research Laboratory, Hitachi, Ibaraki, Japan; 株式会社日立製作所 | 半導体集積回路装置の製造方法および半導体集積回路装置 | ▪ metal layer coupling area ≈ 製造方法 ▪ first range, first etch stop layer ≈ ０．５ | X | X | X | X | X | X | X | X | |||||||||
| 84 | JP2002289810A (Osamu Arisumi, 2002) | (Original Assignee) Toshiba Corp; 株式会社東芝 | 半導体装置およびその製造方法 | ▪ interlevel dielectric, second interlevel dielectric layer ≈ キャパシタ, 誘電体膜 ▪ second range ≈ あること ▪ metal layer coupling area ≈ 製造方法 ▪ electrical insulation ≈ 前記誘 ▪ etching process ≈ １００ | X | X | X | X | X | X | X | X | X | X | |||||||
| 85 | CN1418374A (P·-E·诺达尔, 2003) | (Original Assignee) 薄膜电子有限公司 | 叠层中的垂直电互连 | ▪ lithography process ≈ 一个或多个 ▪ second etch stop layer, second etch stop layers ≈ 衬底中 ▪ substrate material ≈ 层形成 | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) ▪ 35 U.S.C. 102(e) | ▪ discloses a semiconductor device comprises a semiconductor chip… ▪ discloses the first recess is a slope shape for the purpose of increasing storage capacity within the memory modules… ▪ discloses that a rst substrate layer having an interior region and a peripheral region rst signal paths that extend… ▪ teaches with such structure multiple semiconductor chips can be stacked in layers the size of the semiconductor device… | X | X | X | X | X | X | |||||||||
| 86 | US6383857B2 (Takashi Terauchi, 2002) | (Original Assignee) Mitsubishi Electric Corp (Current Assignee) Mitsubishi Electric Corp | Semiconductor device and method for manufacturing the same | ▪ substrate material ≈ forming contact holes ▪ contact bottom ≈ bottom walls ▪ second etch ≈ second etch ▪ first etch ≈ first etch ▪ anti reflective coating ≈ d forming ▪ metal layer coupling area ≈ film side | X | X | X | X | X | X | X | X | X | ||||||||
| 87 | US20020025669A1 (Min-wk Hwang, 2002) | (Original Assignee) Samsung Electronics Co Ltd (Current Assignee) Samsung Electronics Co Ltd | Methods of forming a contact structure in a semiconductor device | ▪ second etch stop layers ≈ silicon nitride layer ▪ etching process ≈ doped polysilicon ▪ second etch, multiple etch ≈ etch stop layer, gate pattern ▪ first sub interlevel dielectric layer ≈ entire surface ▪ second space, floating gate ≈ storage node, drain region ▪ anti reflective coating ≈ d forming | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ discloses process of forming closely spaced metallic lines on a semiconductor substrate forming a cap layer on the lines… ▪ describes wherein the partial SAC etching process is carried out at a pressure of about… ▪ teaches that it is bene cial to etch the top cap layer on the metallic lines to narrow its width prior to depositing… ▪ discloses conducting the steps of etching the fourth insulator lm to form therein a contact hole by using the sidewall… | X | X | X | X | X | X | X | X | X | X | |||||
| 88 | US6429123B1 (Horng-Huei Tseng, 2002) | (Original Assignee) Vanguard International Semiconductor Corp (Current Assignee) Vanguard International Semiconductor Corp | Method of manufacturing buried metal lines having ultra fine features | ▪ second etch stop layers, floating gate ≈ second sidewall spacer, silicon nitride layer ▪ etch process ≈ etching stop layer ▪ substrate material ≈ silicon oxide | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ discloses a plurality of vernier patterns target patterns for determining positioning error between lithographic fields… ▪ teaches that the spacers can be segmented by the desired architecture paragraph… ▪ discloses wherein said plasma conversion is plasma nitridation and said dielectric metal containing compound is a… ▪ discloses forming a surface treatment layer prior to introducing the copolymer in the opening… | X | X | X | ||||||||||||
| 89 | JP2002064140A (Masayuki Hiroi, 2002) | (Original Assignee) Nec Corp; 日本電気株式会社 | 半導体装置およびその製造方法 | ▪ second range ≈ あること ▪ electrical insulation ≈ の絶縁 | X | X | X | ||||||||||||||
| 90 | US6373123B1 (Darwin A. Clampitt, 2002) | (Original Assignee) Micron Technology Inc (Current Assignee) Micron Technology Inc | Semiconductor structure having more usable substrate area and method for forming same | ▪ floating gate ≈ semiconductor structure ▪ spacer region ≈ monocrystalline silicon ▪ second etch stop layers ≈ adjacent pair ▪ first etch, first etch stop layer ≈ memory array ▪ etching process ≈ second area ▪ second sub ≈ second sub ▪ first sub ≈ first sub | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ discloses substantially the claimed invention except that the analog switch includes… ▪ discloses a semiconductor device comprising a semiconductor layer… ▪ teaches that these protective materials may have applications for many air gap trenches… ▪ discloses the first and second ns A and B as shown in the attached g are capped with a nitride layer… | X | X | X | X | X | X | X | X | X | X | X | ||||
| 91 | JP2001057386A (Takashi Jo, 2001) | (Original Assignee) Samsung Electronics Co Ltd; 三星電子株式会社 | エッチバックを用いた多結晶シリコンコンタクトプラグ形成方法およびこれを用いた半導体素子の製造方法 | ▪ second range ≈ あること ▪ metal layer coupling area ≈ 製造方法 ▪ etching process ≈ １００ | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ discloses that openings in a dielectric layer formed over a semiconductor substrate may be formed A conductive material… ▪ discloses that one skilled in the art of plasma etching and cleaning may vary type of plasma etching RIE HDP plasma… ▪ teaches a semiconductor device comprising a first storage node contact plug… ▪ teaches the use of barium trichloride gases with other halogens to plasma etch dielectrics note col… | X | X | X | X | X | X | |||||||||
| 92 | JP2001326286A (Seiki Ogura, 2001) | (Original Assignee) Halo Lsi Design & Device Technol Inc; Matsushita Electric Ind Co Ltd; ヘイロー エルエスアイ デザイン アンド デバイステクノロジー インコーポレイテッド; 松下電器産業株式会社 | 半導体装置及びその製造方法 | ▪ second sub interlevel dielectric layer ≈ 少なくとも ▪ electrical insulation ≈ なる第２ ▪ second range ≈ あること ▪ metal layer coupling area ≈ 製造方法 | X | X | X | X | X | X | X | X | |||||||||
| 93 | JP2001298154A (Tetsuya Oishi, 2001) | (Original Assignee) Sony Corp; ソニー株式会社 | 半導体装置およびその製造方法 | ▪ interlevel dielectric, second interlevel dielectric ≈ バリアメタル ▪ second sub interlevel dielectric layer ≈ 少なくとも ▪ metal layer coupling area ≈ 製造方法 ▪ substrate material ≈ ウォール ▪ electrical insulation ≈ の絶縁 ▪ first space ≈ 前記保 | X | X | X | X | X | X | X | X | X | ||||||||
| 94 | JP2001291846A (Yuichi Takada, 2001) | (Original Assignee) Nec Corp; 日本電気株式会社 | 半導体記憶装置及びその製造方法 | ▪ metal layer coupling area ≈ 製造方法 ▪ electrical insulation ≈ 絶縁層 | X | X | X | ||||||||||||||
| 95 | US6323130B1 (Stephen Bruce Brodsky, 2001) | (Original Assignee) International Business Machines Corp (Current Assignee) GlobalFoundries Inc | Method for self-aligned formation of silicide contacts using metal silicon alloys for limited silicon consumption and for reduction of bridging | ▪ second interlevel dielectric, second interlevel dielectric layer ≈ oxygen barrier layer ▪ second sub ≈ electronic device ▪ etch process, multiple etch ≈ etch process, wet etch ▪ etching process ≈ alloy layer | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ discloses that gold silver and titanium have a low resistance column… ▪ discloses the step of depositing conducting material and etching the insulating oxide layer by exposing it to plasma… ▪ teaches that it is known to use a chemically inert plasma to remove organic contaminants paragraph… ▪ teaches forming performing a cleaning step forming a metal layer… | X | X | X | X | X | X | X | X | |||||||
| 96 | JP2001223269A (Tatsuya Usami, 2001) | (Original Assignee) Nec Corp; 日本電気株式会社 | 半導体装置およびその製造方法 | ▪ second sub interlevel dielectric layer ≈ 少なくとも ▪ second range ≈ あること ▪ metal layer coupling area ≈ 製造方法 ▪ substrate coupling area ≈ 前記層 | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) ▪ 35 U.S.C. 102(e) | ▪ discloses the claimed method of fabricating at least one damascene opening comprising the steps of providing a structure… ▪ teaches formation of dielectric layer in situ with another layer… ▪ discloses an integrated circuit device that includes a bonding pad area and that the bonding pads are to be used to… ▪ teaches forming a mask and using it to etch the stopper insulating film… | X | X | X | X | X | X | X | X | |||||||
| 97 | US6177318B1 (Seiki Ogura, 2001) | (Original Assignee) Halo LSI Design and Device Technology Inc (Current Assignee) Halo LSI Design and Device Technology Inc | Integration method for sidewall split gate monos transistor | ▪ etch process ≈ ion implantation ▪ floating gate ≈ floating gate ▪ metal layer coupling area ≈ said stack ▪ anti reflective coating ≈ d forming ▪ first space ≈ said sub | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ discloses the non volatile memory comprises a plurality of electrode layers in different height levels ie layer… ▪ teaches a method of forming a film for semiconductor processing… ▪ teaches to simply switch to platinum electroless plating from the copper plating column… ▪ teaches that interconnect layers on semiconductor devices include electrical devices such as memory devices… | X | X | X | X | X | X | X | X | |||||||
| 98 | JP2001053144A (Shinichi Domae, 2001) | (Original Assignee) Matsushita Electronics Industry Corp; 松下電子工業株式会社 | 半導体装置及びその製造方法 | ▪ metal layer coupling area ≈ 製造方法 ▪ electrical insulation ≈ の絶縁 ▪ substrate coupling area ≈ 前記層 | X | X | X | ||||||||||||||
| 99 | US6117725A (Jenn Ming Huang, 2000) | (Original Assignee) Taiwan Semiconductor Manufacturing Co TSMC Ltd (Current Assignee) Taiwan Semiconductor Manufacturing Co TSMC Ltd | Method for making cost-effective embedded DRAM structures compatible with logic circuit processing | ▪ second interlevel dielectric, first sub interlevel dielectric layer ≈ bottom electrode ▪ substrate material ≈ silicon oxide ▪ anti reflective coating ≈ d forming ▪ first space ≈ said sub | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ discloses the semiconductor device including an ohmic contact layer see column… ▪ teaches a method of selectively depositing metal in a dual damascene structure figs… ▪ teaches that the step of forming the pad shaped storage node in the first storage node opening further comprises… ▪ teaches any metal layer can be used to enhance the capacitance of the capacitor see column… | X | X | X | X | X | X | X | X | X | ||||||
| 100 | US6251790B1 (In-kwon Jeong, 2001) | (Original Assignee) Samsung Electronics Co Ltd (Current Assignee) Samsung Electronics Co Ltd | Method for fabricating contacts in a semiconductor device | ▪ etching process ≈ uniform thickness ▪ multiple etch ≈ tungsten nitride ▪ substrate material ≈ silicon oxide ▪ interlevel dielectric, second interlevel dielectric ≈ contact hole, contact plug ▪ contact bottom ≈ top portion ▪ anti reflective coating ≈ d forming | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ discloses a process of fabricating deep submicron structures comprising covering the substrate with a first material… ▪ teaches said first and second dielectric materials comprise the same or different low k dielectric having a dielectric… ▪ discloses that the substrate is etched after a desired size of the spacers is formed… ▪ teaches that this results in patterns with a different pitch and density… | X | X | X | X | X | X | X | X | X | X | X | ||||
| 101 | US6355567B1 (Scott D. Halle, 2002) | (Original Assignee) International Business Machines Corp (Current Assignee) International Business Machines Corp | Retrograde openings in thin films | ▪ etch process ≈ chemical etching ▪ second etch ≈ second etch ▪ first etch ≈ first etch ▪ substrate material ≈ active ion | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(e) | ▪ discloses a process of forming a plated copper layer including forming an adhesion layer… ▪ discloses forming a wire bond in an opening to an interconnecting structure see fig… ▪ teaches away from forming a metallization structure on a surface although this may be true it is not persuasive since… ▪ teaches that an electroplated copper line has an adhesion layer a copper seed layer and an electroplated copper layer… | X | X | X | X | X | X | |||||||||
| 102 | US6074908A (Jenn Ming Huang, 2000) | (Original Assignee) Taiwan Semiconductor Manufacturing Co TSMC Ltd (Current Assignee) Taiwan Semiconductor Manufacturing Co TSMC Ltd | Process for making merged integrated circuits having salicide FETS and embedded DRAM circuits | ▪ spacer region ≈ interlevel dielectric layer ▪ first etch, second etch stop layers ≈ wet etch, silicon oxide layer ▪ interlevel dielectric, second interlevel dielectric ≈ stacked capacitor ▪ etching process ≈ doped polysilicon ▪ second etch ≈ etch stop layer, gate oxide ▪ contact region ≈ second contact ▪ metal layer coupling area ≈ said stack ▪ anti reflective coating ≈ d forming ▪ first space ≈ said sub | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(e) | ▪ teaches a method of selectively depositing metal in a dual damascene structure figs… ▪ teaches that it is known in the art to provide the first circuit including a constant current generator or a constant… ▪ discloses a method for cleaning a capacitor on semiconductor wafer comprising the step of cleaning the wafer with… ▪ discloses the thickness of the buffer layer is a complementary thickness to the dielectric layer such that the thickness… | X | X | X | X | X | X | |||||||||
| 103 | US6096595A (Jenn Ming Huang, 2000) | (Original Assignee) Taiwan Semiconductor Manufacturing Co TSMC Ltd (Current Assignee) Taiwan Semiconductor Manufacturing Co TSMC Ltd | Integration of a salicide process for MOS logic devices, and a self-aligned contact process for MOS memory devices | ▪ first etch ≈ said second polysilicon layer, said first polysilicon layer ▪ second etch stop layers, interlevel dielectric ≈ silicon nitride layer, capacitor structure ▪ etch process ≈ silicon oxide layer, ion implantation ▪ second space, floating gate ≈ storage node ▪ anti reflective coating ≈ d forming | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ teaches a CMOS image sensor integrated with SRAM comprising see figs… ▪ teaches a rst impurity introduced region of relatively low concentration formed in an exposed portion of the main… ▪ teaches forming a DRAM devices region and peripheral device region as shown in gures… ▪ discloses that polysilanephotosensitive silicone polymer can be used as the resist material for easily and quickly… | X | X | X | X | X | X | X | X | |||||||
| 104 | US6043529A (Walter Hartner, 2000) | (Original Assignee) Siemens AG (Current Assignee) Siemens AG ; Qimonda AG | Semiconductor configuration with a protected barrier for a stacked cell | ▪ second etch stop layers ≈ silicon nitride layer ▪ interlevel dielectric, second interlevel dielectric ≈ conductive oxides, contact hole ▪ metal layer coupling area ≈ upper electrodes ▪ contact bottom ≈ lower electrode | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) ▪ 35 U.S.C. 102(e) | ▪ discloses using trimethyl aluminum gas as the aluminum precursor and ozone or… ▪ teaches a thin dielectric layer may be deposited over the sidewall diffusion barrier column… ▪ teaches a semiconductor memory device substantially as claimed including a semiconductor substrate… | X | X | X | X | X | X | X | X | |||||||
| 105 | US6232225B1 (Chil-kun Pong, 2001) | (Original Assignee) Samsung Electronics Co Ltd (Current Assignee) Samsung Electronics Co Ltd | Method of fabricating contact window of semiconductor device | ▪ first sub interlevel dielectric layer ≈ entire surface ▪ multiple etch stop insulation layer, first etch stop layer ≈ wet etch rate, dry etch | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(e) | ▪ discloses a plasma etching method comprising plasma etching a lm… ▪ discloses that using any one of the rare gases noble gases such as… ▪ teaches etching the layer by using oxygen and controlling the electron temperature of the plasma see paragraph… ▪ teaches a process of production of a semiconductor apparatus… | X | X | X | X | X | X | X | X | |||||||
| 106 | US6156648A (Yimin Huang, 2000) | (Original Assignee) United Microelectronics Corp (Current Assignee) United Microelectronics Corp | Method for fabricating dual damascene | ▪ substrate coupling area ≈ second conductive layer ▪ substrate material ≈ active ion | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) ▪ 35 U.S.C. 102(e) | ▪ discloses an interconnect level disposed over an interlevel dielectric layer… ▪ discloses generating the tungsten nucleus using an LRW method including the steps of generating the nucleus by… ▪ teaches a method for forming a semiconductor device comprising forming a dielectric structure… ▪ discloses forming the glue layer in situ or exsitu inherently one of these processes has to be performed… | X | X | X | X | |||||||||||
| 107 | JP2000183313A (Shuji Ikeda, 2000) | (Original Assignee) Thin Film Research Center, Hitachi''s Central Research Laboratory, Hitachi, Ibaraki, Japan; 株式会社日立製作所 | 半導体集積回路装置およびその製造方法 | ▪ interlevel dielectric ≈ メモリ素子 ▪ electrical insulation, multiple etch stop insulation layer ≈ 絶縁材料, なる第２ ▪ second range ≈ あること ▪ substrate coupling area ≈ 前記層 | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(e) | ▪ discloses the step of applying a photoresist on the etchstop layer silicon nitride… ▪ teaches the first and second chemical solutions are phosphoric acid aqueous solution… ▪ discloses a method for cleaning a capacitor on semiconductor wafer comprising the step of cleaning the wafer with… ▪ teaches that such etchants when combined form an etchant wherein the ratio of the etch rate of a silicate glass to the… | X | X | X | X | X | X | X | X | X | ||||||
| 108 | JP2000150516A (Takashi Akahori, 2000) | (Original Assignee) Tokyo Electron Ltd; 東京エレクトロン株式会社 | 半導体装置の製造方法 | ▪ second sub interlevel dielectric layer ≈ 少なくとも ▪ second range ≈ あること ▪ metal layer coupling area ≈ 製造方法 | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ discloses a layer transfer method including forming an insulating film of silicon oxide over a bond substrate by CVD col… ▪ teaches the formation a layered structure comprising an amorphous carbon layer a… ▪ discloses that the outer target portions are divided into four groups so that they can be exposed in a particular order… ▪ teaches a process of improving the formation of these devices… | X | X | X | X | X | X | X | X | |||||||
| 109 | US6255215B1 (Fred Hause, 2001) | (Original Assignee) Advanced Micro Devices Inc (Current Assignee) GlobalFoundries Inc | Semiconductor device having silicide layers formed using a collimated metal layer | ▪ floating gate ≈ drain region ▪ anti reflective coating ≈ d forming | X | X | X | ||||||||||||||
| 110 | US6163059A (Frederick N. Hause, 2000) | (Original Assignee) Advanced Micro Devices Inc (Current Assignee) Advanced Micro Devices Inc | Integrated circuit including source implant self-aligned to contact via | ▪ etch process ≈ silicon dioxide material ▪ second etch stop layers, floating gate ≈ second sidewall spacer, first sidewall spacer ▪ second etch ≈ gate oxide ▪ first etch stop layer ≈ drain side ▪ anti reflective coating ≈ d forming | X | X | X | X | X | X | X | X | X | ||||||||
| 111 | US6127276A (Shih-Yao Lin, 2000) | (Original Assignee) United Microelectronics Corp (Current Assignee) United Microelectronics Corp | Method of formation for a via opening | ▪ lithography process ≈ lithography process ▪ multiple etch, first etch ≈ wet etch, dry etch | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(e) | ▪ teaches that to reduce signal delay at interconnections a lm with a low dielectric is used such as… ▪ teaches etching the layer by using oxygen and controlling the electron temperature of the plasma see paragraph… ▪ teaches forming a dual damascene structure by plasma etching at the pressure of… ▪ discloses a patterning forming method of forming a gate layer on the substrate followed by an insulating layer forming… | X | X | X | X | X | X | |||||||||
| 112 | US6121083A (Takeo Matsuki, 2000) | (Original Assignee) NEC Corp (Current Assignee) Renesas Electronics Corp | Semiconductor device and method of fabricating the same | ▪ interlevel dielectric, second interlevel dielectric ≈ interlayer insulating film, upper electrode ▪ second range ≈ second material ▪ contact bottom ≈ lower electrode ▪ floating gate ≈ drain region | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(e) ▪ 35 U.S.C. 102(b) | ▪ discloses a device comprising a substrate comprising at least one cell a contact region and an encapsulation a thin film… ▪ discloses a product which reasonably appears to be identical with or only slightly different than the product claimed in… ▪ discloses that the passivation layer comprises silicon nitride column… ▪ teaches the invention substantially as claimed and described in claims… | X | X | X | X | X | X | X | X | X | X | |||||
| 113 | US6051462A (Keiichi Ohno, 2000) | (Original Assignee) Sony Corp (Current Assignee) Sony Corp | Process for producing semiconductor device comprising a memory element and a logic element | ▪ first etch stop layer ≈ fourth insulating ▪ interlevel dielectric, second interlevel dielectric ≈ upper electrode, contact hole ▪ contact bottom ≈ lower electrode | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ teaches the method for etching a substrate as discussed above in addressing claim… ▪ teaches everything above except for wherein removing the portion of the conductive layer comprises chemical mechanical… ▪ teaches in FIG I I that for a similar structure the recess region includes a portion of the storage node region below… ▪ discloses a memory device see the entire patent including the… | X | X | X | X | X | X | X | X | |||||||
| 114 | US6066541A (Ming-Teng Hsieh, 2000) | (Original Assignee) Nanya Technology Corp (Current Assignee) Nanya Technology Corp | Method for fabricating a cylindrical capacitor | ▪ substrate coupling area ≈ second conductive layer ▪ interlevel dielectric, second interlevel dielectric ≈ contact hole ▪ second space ≈ second space ▪ floating gate ≈ drain region ▪ first space ≈ first space, said sub ▪ anti reflective coating ≈ d forming | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(e) | ▪ discloses the method substantially as claimed and rejected above but does not disclose the method of a combo HSG process… ▪ teaches a memory element comprising an organic material interposed between two conductive layers and a first and… ▪ discloses that nitride is a suitable material for insulating a contact structure… ▪ teaches the rst conductive layer comprising a polysilicon but lacks having the second conductive material… | X | X | X | X | X | X | X | X | X | X | X | ||||
| 115 | US5899721A (Mark I. Gardner, 1999) | (Original Assignee) Advanced Micro Devices Inc (Current Assignee) Advanced Micro Devices Inc | Method of based spacer formation for ultra-small sapcer geometries | ▪ second etch, etch process ≈ dielectric materials ▪ second space ≈ adjacent sidewall ▪ first sub, first sub interlevel dielectric layer ≈ upper surfaces ▪ floating gate ≈ drain regions | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ teaches a MOS transistor process comprising forming and planarizing an interdielectric layer… ▪ discloses a semiconductor device substantially as claimed and as detailed above for claim… ▪ teaches the benefits of using a silicon oxynitride layer for the gate insulator to prevent diffusion between the gate… ▪ teaches a gate width of a transistor and its threshold voltage have a direct correlation with one another that is if a… | X | X | X | X | X | X | X | X | X | ||||||
| 116 | EP0854508A2 (Nancy Anne Greco, 1998) | (Original Assignee) International Business Machines Corp (Current Assignee) International Business Machines Corp | Method of forming contact structure | ▪ floating gate ≈ semiconductor structure ▪ second etch, etch process ≈ dielectric materials ▪ substrate material ≈ active ion | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ teaches the claim limitations except for the exact ratio or ranges of volume… ▪ discloses a semiconductor device having first and second contact structures… ▪ teaches after the etching of said second dielectric interlayer said resist is removed by an ashing process wherein… ▪ teaches the halo implant raising the doping concentration only on the inside walls of the sourcedrain junctions ie… | X | X | X | X | X | X | X | ||||||||
| 117 | EP0926726A1 (Ubaldo Mastermatteo, 1999) | (Original Assignee) STMicroelectronics SRL; SGS Thomson Microelectronics SRL (Current Assignee) STMicroelectronics SRL ; STMicroelectronics SRL | Fabrication process and electronic device having front-back through contacts for bonding onto boards | ▪ second sub ≈ electronic device ▪ contact region ≈ contact region ▪ second range ≈ support wafer ▪ substrate material ≈ silicon oxide ▪ first range ≈ surface zone ▪ anti reflective coating ≈ d forming ▪ first space ≈ said sub | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ teaches a floating gate memory cell wherein the air tunnel is a vacuum tunnel to provide an ideal dielectric tunnel… ▪ teaches that the ideal dielectric is vacuum gaseous or air with a dielectric constant of approximately unity… ▪ teaches a method for ling a TSV through silicon via with metal comprising a conductive composition that is used to… ▪ teaches watersoluble organic uxes are used in soldering in the electronics industry page… | X | X | X | X | X | X | X | X | X | X | X | X | X | ||
| 118 | EP0847081A1 (Takayuki Niuya, 1998) | (Original Assignee) Texas Instruments Inc (Current Assignee) Texas Instruments Inc | Improvements in or relating to semiconductor devices | ▪ first etch, interlevel dielectric ≈ local interconnect ▪ etching process ≈ doped polysilicon ▪ contact region ≈ second contact ▪ floating gate ≈ drain region ▪ anti reflective coating ≈ d forming | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ discloses a method of fabricating a semiconductor device comprising forming a rst dielectric layer… ▪ teaches that the alloy of silicon and germanium having a chemical formula as… ▪ discloses that it is known in the art for the DRAM device would have two gate patterns… | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X |
| 119 | US5953609A (Kuniaki Koyama, 1999) | (Original Assignee) NEC Corp (Current Assignee) NEC Electronics Corp | Method of manufacturing a semiconductor memory device | ▪ substrate coupling area ≈ second conductive layer ▪ second etch stop layer ≈ zirconium nitride ▪ metal layer coupling area ≈ conductive oxide ▪ substrate material ≈ first metal film ▪ floating gate ≈ drain regions ▪ contact region ≈ said element ▪ second etch ≈ gate oxide | X | X | X | X | X | X | |||||||||||
| 120 | US6740584B2 (Takahisa Eimori, 2004) | (Original Assignee) Mitsubishi Electric Corp (Current Assignee) Renesas Electronics Corp | Semiconductor device and method of fabricating the same | ▪ interlevel dielectric, second interlevel dielectric ≈ interlayer insulating film, contact hole ▪ first sub, first sub interlevel dielectric layer ≈ upper surfaces ▪ substrate material ≈ silicon oxide ▪ first etch, etch process ≈ etching rate | X | X | X | X | X | X | X | X | |||||||||
| 121 | US5989952A (Tean-Sen Jen, 1999) | (Original Assignee) Nanya Technology Corp (Current Assignee) Nanya Technology Corp | Method for fabricating a crown-type capacitor of a DRAM cell | ▪ floating gate ≈ amorphous silicon layer ▪ second etch stop layers ≈ silicon nitride layer ▪ etching process ≈ capacitor region ▪ contact region ≈ contact region | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ discloses polysilicon can be deposited from the decomposition of… ▪ discloses establishing a plurality of communication links within a semipermanent slot in claim… ▪ teaches the method wherein the support material surrounds the individual first capacitor electrodes the second etching… ▪ teaches a means for removing the particles defects or flakes from the main face in the form of ashing in pretreatment… | X | X | X | X | X | X | X | X | X | X | |||||
| 122 | US5972747A (Ki-Gak Hong, 1999) | (Original Assignee) LG Semicon Co Ltd (Current Assignee) SK Hynix Inc | Method of fabricating semiconductor memory device | ▪ spacer region ≈ diffusion regions ▪ first sub interlevel dielectric layer ≈ entire surface ▪ interlevel dielectric, second interlevel dielectric ≈ contact hole ▪ anti reflective coating ≈ d forming | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ discloses the power semiconductor device as set forth in claim… ▪ teaches a nonvolatile memory array comprising nonvolatile onetransistor dielectric charge trapping memory cells FIG… ▪ teaches that an insulating substrate glass substrate is used instead of a bulk semiconductor substrate… | X | X | X | X | X | X | X | X | X | X | |||||
| 123 | US5801082A (Horng-Huei Tseng, 1998) | (Original Assignee) Vanguard International Semiconductor Corp (Current Assignee) Vanguard International Semiconductor Corp | Method for making improved shallow trench isolation with dielectric studs for semiconductor integrated circuits | ▪ first space ≈ trench isolation regions ▪ spacer region ≈ gate electrodes ▪ contact region ≈ raised surface ▪ substrate material ≈ silicon oxide, spin coating ▪ second etch ≈ gate oxide ▪ multiple etch, first etch ≈ wet etch | ▪ 35 U.S.C. 103(a) | ▪ teaches the slurry results in reduced polishing rate at recesses while the abrasive particles maintain high polish… | X | X | X | X | X | X | X | X | X | X | X | X | |||
| 124 | US5883010A (Richard B. Merrill, 1999) | (Original Assignee) National Semiconductor Corp (Current Assignee) National Semiconductor Corp | Method for protecting nonsilicided surfaces from silicide formation using spacer oxide mask | ▪ second etch stop layers ≈ exposed regions ▪ contact region ≈ contact region | ▪ 35 U.S.C. 102(b) | ▪ discloses all the claimed subject matter except for the ends of the resistor having metal contacts… | X | X | X | X | X | X | X | X | |||||||
| 125 | JPH1154724A (Keiichi Ono, 1999) | (Original Assignee) Sony Corp; ソニー株式会社 | 半導体装置の製造方法 | ▪ interlevel dielectric ≈ メモリ素子, キャパシタ ▪ second sub interlevel dielectric layer ≈ 少なくとも ▪ electrical insulation ≈ なる第２ ▪ metal layer coupling area ≈ 製造方法 ▪ substrate material ≈ ウォール, ６工程 | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ teaches the method for etching a substrate as discussed above in addressing claim… ▪ teaches everything above except for wherein removing the portion of the conductive layer comprises chemical mechanical… ▪ teaches in FIG I I that for a similar structure the recess region includes a portion of the storage node region below… ▪ discloses a memory device see the entire patent including the… | X | X | X | X | X | X | X | X | X | ||||||
| 126 | US6097052A (Yoshinori Tanaka, 2000) | (Original Assignee) Mitsubishi Electric Corp (Current Assignee) Renesas Electronics Corp | Semiconductor device and a method of manufacturing thereof | ▪ substrate material ≈ silicon oxide ▪ floating gate ≈ drain regions ▪ first etch, first etch stop layer ≈ layers stack ▪ contact bottom ≈ two layers | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(e) | ▪ discloses where the upper interconnection pattern comprises an upper interconnection capping layer… ▪ teaches the rst conductive layer comprising a polysilicon but lacks having the second conductive material… ▪ discloses that nitride is a suitable material for insulating a contact structure… ▪ discloses all limitation except for arranging a tube to be in contact with the insulating layer and wherein the opening… | X | X | X | X | X | X | |||||||||
| 127 | US5801094A (Tri-Rung Yew, 1998) | (Original Assignee) United Microelectronics Corp (Current Assignee) United Microelectronics Corp | Dual damascene process | ▪ multiple etch, etch process ≈ layer dielectric, hard mask ▪ first sub, first sub interlevel dielectric layer ≈ upper surfaces ▪ substrate material ≈ silicon oxide | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(e) | ▪ teaches using dimethyl sulfoxide or an oxygen plasma to remove photoresist this is a teaching that using dimethyl… ▪ teaches that it is known to selectively plasma etch organic lms… ▪ discloses a method of patterning a dielectric comprising a substrate… ▪ teaches for the removal of the resist layer a substrate is immersed for about ve minutes in an etchant and it is… | X | X | X | X | X | X | X | X | |||||||
| 128 | US5880019A (Chin-Chuan Hsieh, 1999) | (Original Assignee) Taiwan Semiconductor Manufacturing Co TSMC Ltd (Current Assignee) Taiwan Semiconductor Manufacturing Co TSMC Ltd | Insitu contact descum for self-aligned contact process | ▪ floating gate ≈ semiconductor structure ▪ contact region ≈ second contact ▪ etch process ≈ etch process ▪ anti reflective coating ≈ d forming ▪ first space ≈ said sub | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ discloses a method for inline monitoring of viacontact etching process based on a test structure is described… | X | X | X | X | X | X | X | X | X | X | X | X | |||
| 129 | US5935868A (Sychyi Fang, 1999) | (Original Assignee) Intel Corp (Current Assignee) Intel Corp | Interconnect structure and method to achieve unlanded vias for low dielectric constant materials | ▪ contact region, spacer region ≈ second photoresist layer, first photoresist layer ▪ substrate coupling area ≈ second conductive layer ▪ second etch ≈ etch stop layer ▪ contact bottom ≈ top portion ▪ anti reflective coating ≈ d forming | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(e) | ▪ describes via rst dual damascene are conventionally used in semiconductor manufacturing gures… ▪ discloses removing the residue using a fluorine containing wet etch… ▪ describes wherein the partial SAC etching process is carried out at a pressure of about… ▪ discloses a method of manufacturing semiconductor integrated circuit device comprising the steps of forming a first… | X | X | X | X | X | X | X | X | X | X | X | X | X | ||
| 130 | US5757045A (Chaochieh Tsai, 1998) | (Original Assignee) Taiwan Semiconductor Manufacturing Co TSMC Ltd (Current Assignee) Taiwan Semiconductor Manufacturing Co TSMC Ltd | CMOS device structure with reduced risk of salicide bridging and reduced resistance via use of a ultra shallow, junction extension, ion implantation | ▪ floating gate ≈ drain regions ▪ interlevel dielectric, second interlevel dielectric ≈ contact hole, MOS device | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ discloses wherein the surface conditioning layer is selected from titanium titanium nitride tantalum and tantalum… ▪ discloses an alkali free glass composition for the manufacture of TFT type liquid crystal display substrates col… ▪ teaches most of the limitations of these claims as discussed above in paragraph… | X | X | X | X | X | X | X | ||||||||
| 131 | US6077774A (Qi-Zhong Hong, 2000) | (Original Assignee) Texas Instruments Inc (Current Assignee) Texas Instruments Inc | Method of forming ultra-thin and conformal diffusion barriers encapsulating copper | ▪ multiple etch, second etch ≈ tetraethyl orthosilicate ▪ first space ≈ said sub | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) ▪ 35 U.S.C. 102(e) | ▪ discloses that a through c are inherently performed in an integrated processing system because a through c are a… ▪ teaches wherein the plurality of metal films have a structure in which a cap metal film… ▪ discloses a method of forming a dual damascene interconnect module over a deposition enhancing material comprising a… ▪ teaches because it is obvious to substitute the seed layer of… | X | X | X | X | X | X | |||||||||
| 132 | US5789316A (Chih-Yuan Lu, 1998) | (Original Assignee) Vanguard International Semiconductor Corp (Current Assignee) Vanguard International Semiconductor Corp | Self-aligned method for forming a narrow via | ▪ floating gate ≈ semiconductor structure, drain region ▪ spacer region ≈ gate electrodes | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ teaches making a plurality of holes by selectively etching the film to be processed… ▪ teaches a method of forming a semiconductor device see for example abstract… ▪ teaches the thickness of the sidewall film is set at S or more if the minimum width of the first openings is… ▪ discloses etching the hard mask at the periphery of the patterned photoresist so as to define an etch zone etching the… | X | X | X | ||||||||||||
| 133 | US5874358A (Alan M. Myers, 1999) | (Original Assignee) Intel Corp (Current Assignee) Intel Corp | Via hole profile and method of fabrication | ▪ substrate coupling area ≈ second conductive layer ▪ etching process ≈ alloy layer ▪ multiple etch, etch process ≈ wet etch, dry etch ▪ anti reflective coating ≈ d forming ▪ first space ≈ said sub ▪ first range ≈ time t | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ discloses that the use of such a material is well known in the art column… ▪ teaches forming a recess undercuts in the lower portion of the contact hole… ▪ discloses a method of fabricating an interconnect structure the method comprising forming an interconnect feature… ▪ discloses that an interlayer insulating film made of silicon oxide offers the benefits of good electrical and physical… | X | X | X | X | X | X | X | X | X | X | X | ||||
| 134 | US5854104A (Shigeo Onishi, 1998) | (Original Assignee) Sharp Corp (Current Assignee) Sharp Corp | Process for fabricating nonvolatile semiconductor memory device having a ferroelectric capacitor | ▪ interlevel dielectric, second interlevel dielectric ≈ layer insulating film, ferroelectric film ▪ contact bottom ≈ lower electrode ▪ etch process ≈ high etching ▪ second etch ≈ second etch ▪ first etch ≈ first etch ▪ anti reflective coating ≈ d forming | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ teaches an anisotropic etching process being performed with a plasma… ▪ discloses a method for improving the memory characteristic of a dynamic RAM DRAM by providing an electrode having… ▪ teaches an oxygen barrier pattern between a plug and electrode… ▪ teaches that insitu doped poly deposition with CMP etchback was a known method of forming contacts that are coplanar… | X | X | X | X | X | X | X | X | X | X | X | ||||
| 135 | US5874357A (Young-Kwon Jun, 1999) | (Original Assignee) LG Semicon Co Ltd (Current Assignee) SK Hynix Inc | Method of forming wiring structure of semiconductor device | ▪ substrate coupling area ≈ second conductive layer ▪ contact region ≈ second contact ▪ substrate material ≈ silicon oxide ▪ interlevel dielectric, second interlevel dielectric ≈ contact hole ▪ anti reflective coating ≈ d forming ▪ second etch, multiple etch ≈ dry etch, wet etch | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(e) | ▪ discloses a method of forming a memory device substantially as claimed including a memory element and a conductive… ▪ teaches an integrated process ow involving a patterned photoresist layer… ▪ teaches etching a plurality of contact holes in the overlayer having variations in thickness but does not mention… ▪ teaches all the features of the claim as set forth above in claim… | X | X | X | X | X | X | X | X | X | X | X | X | X | X | |
| 136 | US5795823A (Steven Avanzino, 1998) | (Original Assignee) Advanced Micro Devices Inc (Current Assignee) GlobalFoundries Inc | Self aligned via dual damascene | ▪ first space ≈ lower half ▪ contact bottom ≈ two layers | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) ▪ 35 U.S.C. 102(e) | ▪ discloses that a through c are inherently performed in an integrated processing system because a through c are a… ▪ teaches wherein the plurality of metal films have a structure in which a cap metal film… ▪ teaches a method of forming a contact in a dielectric layer… ▪ discloses that it is advantageous to use a sacri cial layer which can be etched selectively to the intermetal dielectric… | X | X | |||||||||||||
| 137 | US6077763A (Hwi-Huang Chen, 2000) | (Original Assignee) United Microelectronics Corp (Current Assignee) United Microelectronics Corp | Process for fabricating a self-aligned contact | ▪ second etch stop layers, floating gate ≈ second sidewall spacer, first sidewall spacer ▪ etch process ≈ silicon oxide layer ▪ first sub, first sub interlevel dielectric layer ≈ upper surfaces, cell unit ▪ anti reflective coating ≈ d forming | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(e) | ▪ discloses that information can be stored by forming a plurality of both enabled TFTs and disabled TFTs abstract… ▪ teaches the rst conductive layer comprising a polysilicon but lacks having the second conductive material… ▪ discloses that the disabled TFTs can be formed by removing at least a portion of the channel col… ▪ discloses that active matrix addressed arrays were known speci cation paragraph… | X | X | X | X | X | X | X | X | X | X | |||||
| 138 | US5677557A (Shou-Gwo Wuu, 1997) | (Original Assignee) Taiwan Semiconductor Manufacturing Co TSMC Ltd (Current Assignee) Taiwan Semiconductor Manufacturing Co TSMC Ltd | Method for forming buried plug contacts on semiconductor integrated circuits | ▪ first etch ≈ said second polysilicon layer, first polysilicon layer ▪ interlevel dielectric, second interlevel dielectric ≈ vertical sidewalls ▪ etching process ≈ doped polysilicon ▪ spacer region ≈ gate electrodes ▪ substrate material ≈ silicon oxide ▪ first space ≈ said sub | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ discloses forming the auxiliary mask layer on or above the gate layer using a material for the auxiliary mask layer from… ▪ teaches a low temperature chlorinated inorganic silicon nitride material TANAKA par… ▪ teaches the forming the landing pads and the central landing pad comprises forming a photoresist layer having openings… ▪ discloses wherein the thermal annealing process is performed for… | X | X | X | X | X | X | X | X | X | X | |||||
| 139 | US5661084A (So Wein Kuo, 1997) | (Original Assignee) Taiwan Semiconductor Manufacturing Co TSMC Ltd (Current Assignee) Taiwan Semiconductor Manufacturing Co TSMC Ltd | Method for contact profile improvement | ▪ spacer region ≈ conducting layer ▪ floating gate ≈ drain regions ▪ second etch ≈ second etch ▪ first etch, multiple etch stop insulation layer ≈ etch rates, first etch ▪ first space ≈ said sub | X | X | X | X | X | X | X | X | X | ||||||||
| 140 | US6033969A (Chue-San Yoo, 2000) | (Original Assignee) Taiwan Semiconductor Manufacturing Co TSMC Ltd (Current Assignee) TSMC China Co Ltd | Method of forming a shallow trench isolation that has rounded and protected corners | ▪ second etch stop layers, multiple etch ≈ silicon nitride layer, wet etch ▪ substrate material ≈ silicon oxide ▪ etching process ≈ second area ▪ anti reflective coating ≈ d forming ▪ first space ≈ said sub | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ teaches the substantially at topography being achieved over the deep trench isolation region… ▪ discloses a shallow trench isolation method where the trench sidewalls… ▪ discloses the thermal oxide having lateral portions with sectional pro le of a bird s beak at an interface with the… ▪ teaches removing the mask after forming the trench and thermally growing an oxide liner… | X | X | X | X | X | X | X | X | X | ||||||
| 141 | US5792687A (Erik S. Jeng, 1998) | (Original Assignee) Vanguard International Semiconductor Corp (Current Assignee) Vanguard International Semiconductor Corp | Method for fabricating high density integrated circuits using oxide and polysilicon spacers | ▪ second etch stop layers, floating gate ≈ second sidewall spacer, first sidewall spacer ▪ spacer region ≈ gate electrodes ▪ substrate material ≈ silicon oxide ▪ second etch ≈ gate oxide ▪ anti reflective coating ≈ d forming ▪ first space ≈ said sub | X | X | X | X | X | X | X | ||||||||||
| 142 | US5994762A (Naokatsu Suwanai, 1999) | (Original Assignee) Thin Film Research Center, Hitachi''s Central Research Laboratory, Hitachi, Ibaraki, Japan (Current Assignee) Hitachi Hokkai Semiconductor Ltd ; Renesas Electronics Corp | Semiconductor integrated circuit device including boron-doped phospho silicate glass layer and manufacturing method thereof | ▪ floating gate ≈ layer insulation film, drain region ▪ contact region, spacer region ≈ first boundary ▪ first sub interlevel dielectric layer ≈ n storage ▪ anti reflective coating ≈ d forming | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) ▪ 35 U.S.C. 102(e) | ▪ teaches forming a memory cell region near a center region of a chip eg memory core and a peripheral region eg muxdemux… ▪ discloses a power semiconductor device package comprising a plurality of power semiconductor chips or memory chips which… ▪ teaches that a ball grid array configuration can help to decrease the size of the device see paragraph… ▪ teaches that integrated circuits include a plurality of devices interconnected by multilevel interconnections… | X | X | X | X | X | X | X | X | X | X | X | X | X | ||
| 143 | US5668052A (Junko Matsumoto, 1997) | (Original Assignee) Mitsubishi Electric Corp (Current Assignee) Renesas Electronics Corp | Method of manufacturing semiconductor device | ▪ second etch stop layer, second interlevel dielectric layer ≈ insulating film, contact hole ▪ first sub interlevel dielectric layer ≈ entire surface ▪ etching process ≈ film thickness | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ discloses everything above except for selecting speci cally one niride materials to be used for the oxidation barrier… ▪ discloses that the contact elements are formed by sputtering… ▪ discloses a method wherein the formation of the passivation layer comprises depositing the passivation layer… ▪ teaches a low temperature chlorinated inorganic silicon nitride material TANAKA par… | X | X | X | X | X | X | X | X | |||||||
| 144 | US5719089A (Meng-Jaw Cherng, 1998) | (Original Assignee) Vanguard International Semiconductor Corp (Current Assignee) Vanguard International Semiconductor Corp | Method for etching polymer-assisted reduced small contacts for ultra large scale integration semiconductor devices | ▪ spacer region ≈ semiconductor substrates ▪ interlevel dielectric, second interlevel dielectric ≈ vertical sidewalls ▪ first etch ≈ remaining portions | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(e) | ▪ discloses a process comprising forming a plurality of dense spacer features over layers on a substrate forming an… ▪ discloses that the photoresist may be used to open a hard mask supplying a fist gas mixture to deposit a polymer… ▪ discloses a method of forming a DRAM capable of avoiding bit line leakage comprising the steps of forming a transistor… ▪ discloses openings with first and second critical dimensions paragraph… | X | X | X | X | X | X | X | X | X | ||||||
| 145 | US5656520A (Takeshi Watanabe, 1997) | (Original Assignee) NEC Corp (Current Assignee) NEC Electronics Corp | Semiconductor device and method of manufacturing the same | ▪ etch process ≈ ion implantation ▪ second etch stop layer, second interlevel dielectric layer ≈ insulating film ▪ anti reflective coating ≈ d forming | X | X | X | X | X | X | X | X | |||||||||
| 146 | US5741735A (Michael P. Violette, 1998) | (Original Assignee) Micron Technology Inc (Current Assignee) Micron Technology Inc | Local ground and VCC connection in an SRAM cell | ▪ second etch stop layers, floating gate ≈ second remaining portions, first sidewall spacer ▪ first range ≈ surface region ▪ first etch, first etch stop layer ≈ ion energy ▪ anti reflective coating ≈ d forming | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ discloses a conventional arrangement of an SRAM cell which includes all the limitations as claimed in claims… ▪ teaches simultaneously forming source drain and grate contacts… ▪ discloses a transistor with electrode regions connected to the SD regions… ▪ discloses wherein the surface of the semiconductor substrate has its parts adjacent to the sidewall insulating film… | X | X | X | X | X | X | X | X | X | X | |||||
| 147 | US5801916A (Daryl C. New, 1998) | (Original Assignee) Micron Technology Inc (Current Assignee) Micron Technology Inc | Pre-patterned contact fill capacitor for dielectric etch protection | ▪ second etch stop layers, interlevel dielectric ≈ silicon nitride layer, capacitor structure ▪ etching process ≈ uniform thickness | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ teaches making a thermal processing of an interlayer insulating layer wherein the thermal process is made in a plasma… ▪ discloses a silicon oxide film and a zirconium oxide film can be equivalently used as an insulating protective film… ▪ teaches of the fabrication of a ferroelectric element having a lower electrode layer a ferroelectric film and an upper… ▪ teaches a semiconductor memory device as claimed including a semiconductor substrate… | X | X | X | X | X | X | X | X | |||||||
| 148 | US5717242A (Mark W. Michael, 1998) | (Original Assignee) Advanced Micro Devices Inc (Current Assignee) Advanced Micro Devices Inc | Integrated circuit having local interconnect for reduing signal cross coupled noise | ▪ etching process ≈ doped polysilicon ▪ multiple etch, etch process ≈ layer dielectric | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) ▪ 35 U.S.C. 102(e) | ▪ discloses the claimed invention except for the width and spacing of active regions being different in separate layers… ▪ teaches that it is desirable for wiring lines in a circuit to have uniform resistance… ▪ discloses a method of manu facturing a semiconductor device with a substrate… ▪ discloses a chip wherein the Y connecting each cluster has a node and three interconnects connecting the node to… | X | X | X | X | |||||||||||
| 149 | US5874364A (Masaaki Nakabayashi, 1999) | (Original Assignee) Fujitsu Ltd (Current Assignee) Fujitsu Semiconductor Ltd | Thin film deposition method, capacitor device and method for fabricating the same, and semiconductor device and method for fabricating the same | ▪ etching process ≈ film thickness ▪ first space ≈ said sub | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(e) | ▪ teaches an anisotropic etching process being performed with a plasma… ▪ discloses forming a layer by a CVD method wherein the separate precursors bubbled in separate bubblers are combined in… ▪ teaches to protect the plug during the subsequent oxidizing heat treatment process see col… ▪ teaches an oxygen barrier pattern between a plug and electrode… | X | X | |||||||||||||
| 150 | US5717250A (Paul J. Schuele, 1998) | (Original Assignee) Micron Technology Inc (Current Assignee) Micron Technology Inc | Sputter and CVD deposited titanium nitride barrier layer between a platinum layer and a polysilicon plug | ▪ contact region, contact bottom ≈ makes electrical contact ▪ second interlevel dielectric ≈ said structure | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ teaches that silicon is the most important material in the semiconductor industry with integrated circuits technology… ▪ discloses a method comprising forming an interlayer dielectric ILD… ▪ teaches that the typical pressure used for plasma etching ranges from… ▪ teaches the bene t of mixing uorinecontaining gases in order to obtain desired results… | X | X | X | X | X | X | X | X | |||||||
| 151 | US5733809A (Charles H. Dennison, 1998) | (Original Assignee) Micron Technology Inc (Current Assignee) Micron Technology Inc | Split-polysilicon CMOS process for multi-megabit dynamic memories incorporating stacked container capacitor cells | ▪ substrate coupling area ≈ second conductive layer ▪ interlevel dielectric, second interlevel dielectric ≈ vertical sidewalls, desired capacitor ▪ etch process ≈ capacitor plates ▪ second space, floating gate ≈ storage node, drain region | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ teaches the rst conductive layer comprising a polysilicon but lacks having the second conductive material… ▪ teaches forming a gate oxidation lm by thermal grown at a temperature of about… ▪ discloses a semiconductor device with an embedded capacitor structure in… | X | X | X | X | X | X | X | X | X | X | |||||
| 152 | US5700706A (Werner Juengling, 1997) | (Original Assignee) Micron Technology Inc (Current Assignee) Micron Technology Inc | Self-aligned isolated polysilicon plugged contacts | ▪ etching process ≈ doped polysilicon ▪ second etch, multiple etch ≈ second etch, dry etch ▪ first etch ≈ first etch ▪ second sub ≈ second sub | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ teaches that this decrease in the space between adjacent element active regions provides a signi cant advantage over… ▪ discloses the method including the steps of forming pair of blocks… ▪ teaches patterning the bit line capping pattern such that it is disposed only on the bit line layerswiring layers for… ▪ discloses that to repair damage done to the gate insulating lm a wet hydrogen oxidation takes place… | X | X | X | X | X | X | X | X | |||||||
| 153 | US5734179A (Kuang-Yeh Chang, 1998) | (Original Assignee) Advanced Micro Devices Inc (Current Assignee) Advanced Micro Devices Inc | SRAM cell having single layer polysilicon thin film transistors | ▪ second etch stop layers ≈ exposed regions ▪ floating gate ≈ drain portion ▪ second etch ≈ gate oxide ▪ metal layer coupling area ≈ thin film | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(e) | ▪ discloses a semiconductor structure comprising at least one nFET… ▪ teaches wherein the channel layer is formed of one of silicon… ▪ teaches wherein the substrate is one of a crystal substrate an aluminum oxide substrate a glass substrate and a… ▪ discloses that its disclosed device could function in an SRAM type memory see paragraph… | X | X | X | X | X | X | X | ||||||||
| 154 | US5731242A (Krishna K. Parat, 1998) | (Original Assignee) Intel Corp (Current Assignee) Intel Corp | Self-aligned contact process in semiconductor fabrication | ▪ substrate coupling area ≈ second conductive layer ▪ floating gate ≈ floating gate ▪ etch process ≈ etch process ▪ second etch ≈ second etch ▪ contact bottom ≈ top portion ▪ isolates guidance ≈ forming two ▪ first etch ≈ first etch ▪ anti reflective coating ≈ d forming | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) ▪ 35 U.S.C. 102(e) | ▪ discloses a manufacturing method of a semiconductor storage device comprising the steps of forming a stacked gate… ▪ teaches to simply switch to platinum electroless plating from the copper plating column… ▪ discloses the step of introducing phosphorus into the oating gate… ▪ discloses that the upper substrate comprises a semiconductor layer paragraph… | X | X | X | X | X | X | X | X | X | X | |||||
| 155 | JPH09102492A (Takeshi Sunada, 1997) | (Original Assignee) Toshiba Corp; 株式会社東芝 | 半導体装置の製造方法および半導体製造装置 | ▪ second range ≈ 温度範囲内 ▪ metal layer coupling area ≈ 製造方法 ▪ electrical insulation ≈ の絶縁 ▪ multiple etch stop insulation layer ≈ 真空中 | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(e) | ▪ discloses use of a lowk material that is an doped oxide is used as an interlayer dielectric layer of a semiconductor… ▪ teaches wherein the tensile and compressive stress is introduced by the selection of a known material having a high… ▪ teaches that the method is for making a semiconductor device… ▪ teaches that roughening the silicon oxide layer improves adhesion of layers deposited on the silicon oxide col… | X | X | X | X | X | ||||||||||
| 156 | US5898006A (Takaharu Kudoh, 1999) | (Original Assignee) NEC Corp (Current Assignee) NEC Electronics Corp | Method of manufacturing a semiconductor device having various types of MOSFETS | ▪ first etch, first sub ≈ non-volatile memory, said sub ▪ second etch stop layer, second interlevel dielectric layer ≈ insulating film ▪ floating gate ≈ drain regions ▪ anti reflective coating ≈ d forming ▪ first range ≈ time t | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ discloses a semiconductor device comprising a semiconductor substrate… ▪ teaches about a conventional method of making a CMOS DRAM of four or sixteen mega bits data storage capacity employing… ▪ discloses and an ion implantation layer is formed in a trench located between each common source region of the plurality… ▪ discloses that such a structure improves the performance of the NMOS and PMOS simultaneously paragraph… | X | X | X | X | X | X | X | X | X | X | X | X | |||
| 157 | US5644166A (Jeffrey Honeycutt, 1997) | (Original Assignee) Micron Technology Inc (Current Assignee) Micron Technology Inc | Sacrificial CVD germanium layer for formation of high aspect ratio submicron VLSI contacts | ▪ second interlevel dielectric, second interlevel dielectric layer ≈ concentration level ▪ etching process ≈ high aspect ratio, silicon wafer | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(a) | ▪ discloses a method of forming a semiconductor structure comprising forming a hemispherical grained semiconductor… ▪ teaches these limitations as they are product by process claims… ▪ teaches invention is highly beneficial in the formation of electrical contacts to devices such as diodes resistors… ▪ discloses that ozone is preferable since it also helps with the desorption of hydrogen and water column… | X | X | |||||||||||||
| 158 | US5589415A (Richard A. Blanchard, 1996) | (Original Assignee) SGS Thomson Microelectronics Inc (Current Assignee) STMicroelectronics lnc USA | Method for forming a semiconductor structure with self-aligned contacts | ▪ interlevel dielectric, spacer region ≈ interlevel dielectric ▪ anti reflective coating ≈ d forming ▪ metal layer coupling area ≈ thin film | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ discloses a power mosfet device comprising a first metal track… ▪ discloses the claimed invention as detailed above except for an impedance matching circuit… ▪ teaches an impedance matching circuit is disposed to the die eg chip for the synthesis of outputs see paragraph… ▪ discloses the limitations of A surface layer with a source region and drain region… | X | X | X | X | X | X | X | X | X | X | X | ||||
| 159 | US5612574A (Scott R. Summerfelt, 1997) | (Original Assignee) Texas Instruments Inc (Current Assignee) Texas Instruments Inc | Semiconductor structures using high-dielectric-constant materials and an adhesion layer | ▪ second etch stop layer ≈ zirconium nitride ▪ second sub ≈ electronic device ▪ multiple etch ≈ tungsten nitride | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(e) | ▪ teaches the use of a borondoped titanium nitride that can substitute a titanium nitride… ▪ teaches an anisotropic etching process being performed with a plasma… ▪ discloses wherein the barrier layer has a thickness in a range of about… ▪ discloses a method for improving the memory characteristic of a dynamic RAM DRAM by providing an electrode having… | X | X | X | X | X | X | X | ||||||||
| 160 | US5596221A (Hiroki Honda, 1997) | (Original Assignee) Mitsubishi Electric Corp (Current Assignee) Mitsubishi Electric Corp | Bipolar transistor with emitter double contact structure | ▪ metal layer coupling area ≈ barrier layers ▪ contact region ≈ second contact ▪ anti reflective coating ≈ d forming | X | X | X | X | X | X | X | X | X | X | |||||||
| 161 | US5504038A (Sun-Chieh Chien, 1996) | (Original Assignee) United Microelectronics Corp (Current Assignee) United Microelectronics Corp | Method for selective tungsten sidewall and bottom contact formation | ▪ etch process ≈ silicon oxide layer ▪ interlevel dielectric, second interlevel dielectric ≈ vertical sidewalls | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(e) | ▪ teaches that this method is effective in etching materials from a substrate and because… ▪ teaches creating a metal silicide layer in a nitrogen containing atmosphere containing either… ▪ discloses a method for manufacturing a thin film transistor comprising forming a thin film transistor including a source… ▪ discloses an apparatus that will form a contact hole in an insulating lm coating amorphous… | X | X | X | X | X | X | X | X | |||||||
| 162 | US5841195A (Yih-Shung Lin, 1998) | (Original Assignee) STMicroelectronics lnc USA (Current Assignee) STMicroelectronics lnc USA | Semiconductor contact via structure | ▪ floating gate ≈ second doping concentration ▪ etching process ≈ planarization layer ▪ interlevel dielectric, second interlevel dielectric ≈ vertical sidewalls ▪ first sub interlevel dielectric layer ≈ inclined angle ▪ second etch ≈ second etch ▪ first etch ≈ first etch | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) ▪ 35 U.S.C. 102(e) | ▪ teaches a microwave or millimeter wave milliwave oscillator device interpreted as a module usable in a receiver… ▪ teaches conventional surface preparation ie roughening of the base layer to ensure proper contamination removal and… ▪ teaches that pressure temperature gas ow and power may be varied for control of the etch rate and etch selectivity see… ▪ teaches trenching techniques for forming vias and channels in multi layer electrical interconnects… | X | X | X | X | X | X | X | X | X | X | |||||
| 163 | US5631184A (Shinichiro Ikemasu, 1997) | (Original Assignee) Fujitsu Ltd (Current Assignee) Fujitsu Ltd | Method of producing a semiconductor device having a fin type capacitor | ▪ interlevel dielectric, second interlevel dielectric ≈ contact hole ▪ substrate material ≈ spin coating ▪ first sub, first space ≈ one second, said sub ▪ first etch ≈ first etch ▪ anti reflective coating ≈ d forming | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ teaches the step of forming a high aspect ratio opening to forming a capacitor for a memory device… ▪ teaches the method wherein the support material surrounds the individual first capacitor electrodes the second etching… ▪ discloses the upper interconnection layer is a tungsten layer col… ▪ teaches that the taught deposition process allows for a deposition rate that is greater than conventional ALD… | X | X | X | X | X | X | X | X | X | X | X | ||||
| 164 | US5569948A (Jae K. Kim, 1996) | (Original Assignee) SK Hynix Inc (Current Assignee) SK Hynix Inc | Semiconductor device having a contact plug and contact pad | ▪ floating gate ≈ second insulation ▪ second etch stop layer, second interlevel dielectric layer ≈ insulating film ▪ contact region ≈ second contact ▪ interlevel dielectric ≈ contact plug | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(e) | ▪ discloses that polysilicon is a conductive material that is widely used as gate electrodes and interconnections in… ▪ teaches all aspects of the invention but fails to teach wherein after forming rst and second spaced apart sourcedrain… ▪ teaches the rst conductive layer comprising a polysilicon but lacks having the second conductive material… ▪ discloses a method for fabricating an aluminum oxide hard mask having the steps of a providing an aluminum oxide layer… | X | X | X | X | X | X | X | X | X | X | X | X | |||
| 165 | US5451804A (Water Lur, 1995) | (Original Assignee) United Microelectronics Corp (Current Assignee) United Microelectronics Corp | VLSI device with global planarization | ▪ spacer region ≈ gate electrodes ▪ contact region ≈ fourth surface ▪ floating gate ≈ drain regions ▪ first space ≈ said sub | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) ▪ 35 U.S.C. 102(e) | ▪ discloses an electronic device comprising a low dielectric constant film… ▪ teaches an integrated circuit as claimed including a semiconductor substrate… ▪ discloses performing surface treatment on the siliconcontaminated surface portion of the silicon oxide layer using… ▪ discloses that the step of forming the protective layer includes the sub steps of o depositing on the dielectric film a… | X | X | X | X | X | X | X | X | X | ||||||
| 166 | US5494841A (Charles H. Dennison, 1996) | (Original Assignee) Micron Semiconductor Inc (Current Assignee) Micron Technology Inc | Split-polysilicon CMOS process for multi-megabit dynamic memories incorporating stacked container capacitor cells | ▪ substrate coupling area ≈ second conductive layer ▪ interlevel dielectric, second interlevel dielectric ≈ vertical sidewalls ▪ etching process ≈ doped polysilicon, silicon wafer ▪ etch process ≈ capacitor plates ▪ floating gate ≈ drain region | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ teaches the rst conductive layer comprising a polysilicon but lacks having the second conductive material… ▪ teaches forming a gate oxidation lm by thermal grown at a temperature of about… ▪ discloses a semiconductor device with an embedded capacitor structure in… | X | X | X | X | X | X | X | X | X | X | X | ||||
| 167 | US5500558A (Yoshio Hayashide, 1996) | (Original Assignee) Mitsubishi Electric Corp (Current Assignee) Mitsubishi Electric Corp | Semiconductor device having a planarized surface | ▪ interlevel dielectric, second interlevel dielectric ≈ interlayer insulating film ▪ substrate material ≈ silicon oxide ▪ first space ≈ said sub | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ discloses forming a transistor having a gate interconnection that extends in one direction on a semiconductor substrate… ▪ teaches the interlayer dielectric is formed by high density plasma chemical vapor deposition to achieve high quality… ▪ teaches a method for designing a semiconductor integrated circuit layout… ▪ discloses a wafer planarization process comprising a substrate having a plurality of protrusions… | X | X | X | X | X | X | X | X | |||||||
| 168 | US5616960A (Kazuhiro Noda, 1997) | (Original Assignee) Sony Corp (Current Assignee) Sony Corp | Multilayered interconnection substrate having a resin wall formed on side surfaces of a contact hole | ▪ floating gate ≈ second insulation ▪ interlevel dielectric, second interlevel dielectric ≈ contact hole | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ discloses a configuration for a microelectronic device and a method of producing the same… ▪ teaches the formation of copolymers derived from equivalent borazine compounds and an organosilicon compound embraced… ▪ teaches wherein the phosphorous based photopolymerization initiator is at least one member selected from the group… ▪ discloses a technique wherein the product mixture is agitated with carbon particles that adsorb the platinum and… | X | X | X | X | X | X | X | X | |||||||
| 169 | US5610099A (E. Henry Stevens, 1997) | (Original Assignee) Ramtron International Corp (Current Assignee) Intellectual Ventures I LLC | Process for fabricating transistors using composite nitride structure | ▪ first etch, interlevel dielectric ≈ local interconnect, second plasma ▪ isolates guidance ≈ sputter deposition ▪ substrate material ≈ silicon oxide | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ teaches creating reacted salicide material over the surface of polysilicon removing the unreacted material and… ▪ teaches A nonvolatile semiconductor memory device comprising nonvolatile memory cells of transistor structures formed… ▪ discloses a RAM for storing the pixels in oating point representation which may be also referred to as a frame buffer as… ▪ discloses the method wherein other metal such as nickel can be used instead cobalt see column… | X | X | X | X | X | X | X | X | |||||||
| 170 | US5451543A (Michael P. Woo, 1995) | (Original Assignee) Motorola Solutions Inc (Current Assignee) NXP USA Inc | Straight sidewall profile contact opening to underlying interconnect and method for making the same | ▪ second etch stop layers ≈ second etch stop layers ▪ first etch stop layer ≈ first etch stop layer ▪ contact bottom ≈ vertical sidewall ▪ substrate material ≈ silicon oxide | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ discloses a method of forming a memory device substantially as claimed including a memory element and a conductive… ▪ teaches an integrated process ow involving a patterned photoresist layer… ▪ discloses the hardening the organic semiconductor material includes an annealing process paragraph… ▪ discloses all the features of the instant claimed invention m use of titanium nitride instead of tantalum nitride as… | X | X | X | X | X | ||||||||||
| 171 | US5532191A (Tadashi Nakano, 1996) | (Original Assignee) Kawasaki Steel Corp (Current Assignee) Kawasaki Microelectronics Inc | Method of chemical mechanical polishing planarization of an insulating film using an etching stop | ▪ substrate material ≈ silicon oxide ▪ first space ≈ said sub | X | X | |||||||||||||||
| 172 | US5362666A (Charles H. Dennison, 1994) | (Original Assignee) Micron Technology Inc (Current Assignee) Micron Technology Inc | Method of producing a self-aligned contact penetrating cell plate | ▪ interlevel dielectric, second interlevel dielectric ≈ stacked capacitor ▪ etch process, multiple etch ≈ etch process, hard mask ▪ anti reflective coating ≈ d forming ▪ first space ≈ said sub | ▪ 35 U.S.C. 103(a) | ▪ discloses a method for forming a container capacitor comprising fabricating a cup shape bottom electrode… ▪ discloses the semiconductor memory device as claimed in claim… | X | X | X | X | X | X | X | X | X | X | X | ||||
| 173 | US5413961A (Jae K. Kim, 1995) | (Original Assignee) SK Hynix Inc (Current Assignee) SK Hynix Inc | Method for forming a contact of a semiconductor device | ▪ substrate coupling area ≈ second conductive layer ▪ first etch stop layer ≈ fourth insulating ▪ interlevel dielectric, second interlevel dielectric ≈ contact hole ▪ anti reflective coating ≈ d forming ▪ first space ≈ said sub | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ discloses a method for manufacturing a semiconductor device as shown below… ▪ teaches the forming the landing pads and the central landing pad comprises forming a photoresist layer having openings… ▪ discloses forming sidewall protective lm on a sidewall of said separation slot but does not disclose forming a sidewall… ▪ discloses that the substrate is an integrated circuit substrate the raised pattern is a pattern of transistor gate… | X | X | X | X | X | X | X | X | X | X | X | ||||
| 174 | US5514822A (Michael C. Scott, 1996) | (Original Assignee) Symetrix Corp (Current Assignee) Symetrix Corp | Precursors and processes for making metal oxides | ▪ etch process ≈ dielectric material ▪ second interlevel dielectric ≈ said structure ▪ second range ≈ boiling point | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ discloses the thin film capacitor having all of the claimed features as discussed above with respect to claim… ▪ teaches that excess bismuth would result in the excellent properties of the film capacitor col… ▪ teaches use of a liquid precursor process to add dopants including bismuth to BST barium strontium titanate lms on… ▪ teaches a method of enlarging an opening in an insulating layer comprising using a wet chemical such as hydrogen… | X | X | X | X | |||||||||||
| 175 | US5330934A (Hideki Shibata, 1994) | (Original Assignee) Toshiba Corp (Current Assignee) Toshiba Corp | Method of fabricating a semiconductor device having miniaturized contact electrode and wiring structure | ▪ first etch, etch process ≈ etching rate ▪ anti reflective coating ≈ d forming | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) ▪ 35 U.S.C. 102(a) | ▪ discloses all of the claimed limitations as mentioned above except the material of the UBM layer… ▪ teaches the step of photolithographically patterning an opening in a photoresist layer but does not expressly teach… ▪ discloses wherein said outer contact layer includes a lower individual layer formed with at least one of aluminum and an… ▪ teaches contact pads as pads for bonding with external electronic devices for the implied andor required connection… | X | X | X | X | X | X | X | ||||||||
| 176 | US5346585A (Trung T. Doan, 1994) | (Original Assignee) Micron Semiconductor Inc (Current Assignee) Micron Technology Inc | Use of a faceted etch process to eliminate stringers | ▪ second range ≈ second material ▪ substrate material ≈ active ion ▪ first space ≈ said sub | X | X | X | ||||||||||||||
| 177 | US5338700A (Charles H. Dennison, 1994) | (Original Assignee) Micron Semiconductor Inc (Current Assignee) Micron Technology Inc | Method of forming a bit line over capacitor array of memory cells | ▪ interlevel dielectric ≈ oxidation barrier layer ▪ first etch, first etch stop layer ≈ remaining portions, memory array ▪ etching process ≈ doped polysilicon ▪ second etch, second sub ≈ second thickness ▪ first range ≈ such oxidation ▪ contact region ≈ second contact | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(e) | ▪ teaches a method of forming transistor structures for cell arrays of DRAM semiconductor components including the steps… ▪ teaches that an advanced electronic fabrication employing a dielectric materials having generally higher dielectric… ▪ teaches a capacitor comprising an electrode comprising polysilicon… ▪ discloses that nitride is a suitable material for insulating a contact structure… | X | X | X | X | X | X | X | X | X | X | |||||
| 178 | US5356834A (Shigeki Sugimoto, 1994) | (Original Assignee) Toshiba Corp (Current Assignee) Toshiba Corp | Method of forming contact windows in semiconductor devices | ▪ multiple etch ≈ said second pattern ▪ anti reflective coating ≈ d forming ▪ first space ≈ said sub | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(e) | ▪ discloses that the second insulating layer is formed by stacking a first insulating layer… ▪ teaches a method of manufacturing a semiconductor device as discussed above in addressing claim… ▪ discloses everything above except for selecting speci cally one niride materials to be used for the oxidation barrier… ▪ discloses a metal of the metal silicide is at least one selected from a group consisting of tantalum cobalt titanium… | X | X | X | X | X | ||||||||||
| 179 | US5279989A (Jeong Kim, 1994) | (Original Assignee) SK Hynix Inc (Current Assignee) SK Hynix Inc | Method for forming miniature contacts of highly integrated semiconductor devices | ▪ first etch ≈ second polysilicon layer, first polysilicon layer ▪ floating gate ≈ second insulation ▪ spacer region ≈ gate electrodes ▪ contact bottom ≈ smoothing layer ▪ interlevel dielectric, second interlevel dielectric ≈ contact hole ▪ second space ≈ mask pattern ▪ second etch ≈ gate oxide ▪ anti reflective coating ≈ d forming | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ discloses the photoelectric conversion apparatus according to claim… ▪ teaches that antireflective layers are commonly formed below photoresist layers to prevent reflection during exposure… ▪ teaches a method of forming a metal line of a semiconductor device substantially as claimed including forming a… ▪ discloses a process comprising forming a material layer on a substrate forming a first hard mask on the material layer… | X | X | X | X | X | X | X | X | X | X | X | X | X | ||
| 180 | US5292677A (Charles H. Dennison, 1994) | (Original Assignee) Micron Technology Inc (Current Assignee) Round Rock Research LLC | Reduced mask CMOS process for fabricating stacked capacitor multi-megabit dynamic random access memories utilizing single etch stop layer for contacts | ▪ first etch stop layer ≈ first etch stop layer ▪ second etch stop layer, second interlevel dielectric layer ≈ insulating film, protective insulating ▪ anti reflective coating ≈ d forming ▪ first space ≈ said sub | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ discloses the method wherein contouring at least one isolation layer… ▪ discloses all the limitations of claims except for forming conductive material over the substrate comprising conductive… ▪ discloses the polysilicon layer being doped with arsenic to a concentration between about… ▪ teaches forming a seam inside the first through hole by causing an overhang at an entrance of the first through hole… | X | X | X | X | X | X | X | X | X | X | |||||
| 181 | US5332924A (Migaku Kobayashi, 1994) | (Original Assignee) NEC Corp (Current Assignee) Micron Memory Japan Ltd | Semiconductor device and production method thereof | ▪ interlevel dielectric ≈ intermediate insulating ▪ second etch stop layer, second interlevel dielectric layer ≈ selective removal, insulating film ▪ anti reflective coating ≈ d forming ▪ contact bottom ≈ open top | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ discloses a method of fabricating a semiconductor device comprising forming a rst dielectric layer… ▪ teaches that a rst etching step may be executed until the insulating lm becomes partially exposed… ▪ teaches wherein depositing the first cap layer and depositing the second cap layer comprises continuing deposition… ▪ teaches that it is common in the plasma processing apparatus to have an upper and lower electrodes applying a first… | X | X | X | X | X | X | X | X | X | X | X | ||||
| 182 | US5275972A (Hisashi Ogawa, 1994) | (Original Assignee) Panasonic Corp (Current Assignee) Panasonic Corp | Method for fabricating a semiconductor integrated circuit device including the self-aligned formation of a contact window | ▪ substrate coupling area ≈ second conductive layer ▪ etch process, lithography process ≈ etching apparatus ▪ first etch stop layer ≈ fourth insulating ▪ first range ≈ surface region ▪ contact region ≈ second contact ▪ first etch ≈ first etch ▪ anti reflective coating ≈ d forming | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ teaches wherein the gate is formed to further comprise a hard mask on a surface of the gate conductive layer column… ▪ teaches the FET is now completed by depositing and patterning a metal layer… ▪ teaches a method for making FET stacked gate electrode structure… ▪ discloses an apparatus comprising a process chamber including a conductor member… | X | X | X | X | X | X | X | X | X | X | X | X | |||
| 183 | US5187638A (Gurtej S. Sandhu, 1993) | (Original Assignee) Micron Technology Inc (Current Assignee) Micron Technology Inc ; Micron Semiconductor Inc | Barrier layers for ferroelectric and pzt dielectric on silicon | ▪ etch process ≈ dielectric material ▪ etching process ≈ doped polysilicon ▪ metal layer coupling area ≈ conductive oxide ▪ anti reflective coating ≈ d forming | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ discloses that the at least one diffusion barrier layer column… ▪ discloses a total resistance of the barrier decreases with the barrier thickness and with the area of the barrier as it… ▪ teaches a process using an iridiumiridium oxide layer as a protective barrier layer on a polysilicon interconnect in a… ▪ discloses a ferroelectric memory device as claimed and as detailed above for claim… | X | X | X | X | X | X | X | ||||||||
| 184 | US5346844A (Hyun-jin Cho, 1994) | (Original Assignee) Samsung Electronics Co Ltd (Current Assignee) Samsung Electronics Co Ltd | Method for fabricating semiconductor memory device | ▪ multiple etch stop insulation layer ≈ second insulating layers ▪ multiple etch ≈ said second pattern ▪ etching process ≈ doped polysilicon ▪ second range ≈ second material ▪ contact region ≈ second contact ▪ first etch, etch process ≈ etching rate ▪ second space ≈ second space ▪ floating gate ≈ drain region ▪ first space ≈ first space, said sub ▪ anti reflective coating ≈ d forming | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(e) | ▪ teaches a semiconductor device wherein via openings have a width between about… ▪ discloses at least one metallization level comprising a rst metallization level comprising a plurality of electrically… ▪ teaches that the cap layer bene cially prevents the diffusion of copper see col… ▪ teaches the use of ONONO films for use as a dielectric between a control and floating gate for EEPROM and… | X | X | X | X | X | X | X | X | X | X | X | X | X | X | X |
| 185 | US5612254A (Xiao-Chun Mu, 1997) | (Original Assignee) Intel Corp (Current Assignee) Intel Corp | Methods of forming an interconnect on a semiconductor substrate | ▪ second etch stop layers ≈ silicon nitride layer ▪ interlevel dielectric ≈ contact plug | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) ▪ 35 U.S.C. 102(e) | ▪ discloses that a through c are inherently performed in an integrated processing system because a through c are a… ▪ discloses depositing a metal film such as gold onto a nanoimprint template in order to provide a barrier layer… ▪ discloses typical ALD process steps of pulsing the reactant gases in inert carrier gas removing excess reactants and… ▪ discloses a method of forming a dual damascene interconnect module over a deposition enhancing material comprising a… | X | X | X | X | X | X | X | ||||||||
| 186 | US5248628A (Naoko Okabe, 1993) | (Original Assignee) Toshiba Corp (Current Assignee) Toshiba Corp | Method of fabricating a semiconductor memory device | ▪ contact region ≈ second electrical conductivity, first electrical conductivity ▪ floating gate, second space ≈ drain regions, storage node ▪ metal layer coupling area, second interlevel dielectric layer ≈ said plate ▪ anti reflective coating ≈ d forming ▪ first space ≈ said sub | ▪ 35 U.S.C. 103(a) ▪ 35 U.S.C. 102(b) | ▪ discloses a semiconductor device substantially as claimed and as detailed above for claim… ▪ discloses that nitride is a suitable material for insulating a contact structure… ▪ discloses that the charge from the photodiode is to be stored in either a trench capacitor… ▪ teaches the rst conductive layer comprising a polysilicon but lacks having the second conductive material… | X | X | X | X | X | X | X | X | X | X | X | ||||
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | 2003 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST. : 913-916 2003 Publication Year: 2003 A Design Of A Capacitorless 1T-DRAM Cell Using Gate-induced Drain Leakage (GIDL) Current For Low-power And High-speed Embedded Memory Fujitsu Laboratories Limited, Akiruno, Japan Yoshida, Tanaka, Ieee, Ieee |
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| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range (write operation) of about 0 . 16 μm to 0 . 18 μm wide . |
A Design Of A Capacitorless 1T-DRAM Cell Using Gate-induced Drain Leakage (GIDL) Current For Low-power And High-speed Embedded Memory . A capacitorless IT-DRAM cell using gate-induced drain leakage (GIDL) current for write operation (second range) was demonstrated for the first time . Compared with the conventional write operation with impact ionization current , write operation with GIDL current provides low-power and high-speed operation . The capacitorless IT-DRAM is the most promising technology for high performance embedded DRAM LSI . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer (speed operation) , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
A Design Of A Capacitorless 1T-DRAM Cell Using Gate-induced Drain Leakage (GIDL) Current For Low-power And High-speed Embedded Memory . A capacitorless IT-DRAM cell using gate-induced drain leakage (GIDL) current for write operation was demonstrated for the first time . Compared with the conventional write operation with impact ionization current , write operation with GIDL current provides low-power and high-speed operation (second interlevel dielectric layer) . The capacitorless IT-DRAM is the most promising technology for high performance embedded DRAM LSI . |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region is a first range of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range (write operation) of about 0 . 16 μm to 0 . 18 μm wide . |
A Design Of A Capacitorless 1T-DRAM Cell Using Gate-induced Drain Leakage (GIDL) Current For Low-power And High-speed Embedded Memory . A capacitorless IT-DRAM cell using gate-induced drain leakage (GIDL) current for write operation (second range) was demonstrated for the first time . Compared with the conventional write operation with impact ionization current , write operation with GIDL current provides low-power and high-speed operation . The capacitorless IT-DRAM is the most promising technology for high performance embedded DRAM LSI . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | SOLID-STATE ELECTRONICS. 46 (10): 1525-1530 OCT 2002 Publication Year: 2002 A Dynamic Source-drain Extension MOSFET Using A Separately Biased Conductive Spacer University of California, Berkeley, Micron Technology, Inc. Gonzalez, Mathew, Chediak |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer (drain side) directly on said substrate in said contact region ; a first sub interlevel dielectric layer (drain extension) over said first etch stop layer ; a second etch stop layer (gate stack) over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
A Dynamic Source-drain Extension MOSFET Using A Separately Biased Conductive Spacer . A new approach to control short-channel effects is demonstrated using a conductive spacer formed over a compensated-channel region . Placed adjacent to (but isolated from) the gate stack (second etch stop layer, second etch stop layers) , the conductive spacer functions as an auxiliary gate and is biased independently from the principal gate . This arrangement is shown to behave as a dynamic source-drain extension (first range, first sub interlevel dielectric layer, etching process) (DSDE) MOSFET . This auxiliary gate is able to invert a portion of the channel adjacent to the LDD on both the source and the drain side (first etch stop layer) , decreasing the effective channel length during the "on" state . Consequently , the transistor appears to have a longer effective gate length during the "ofr' state and a shorter gate length during the "on" state . Using technology computer-aided design simulations , we show four orders of magnitude reduction in I-OFF (at a given I-DSAT) using the conductive spacer device . Conductive spacers provide a useful continuum for scaling transistors to the next generation . It is predicted that nanoscale pass gates with I-OFF values as low as 1 pA/mum are attainable with DSDE MOSFETs . (C) 2002 Elsevier Science Ltd . All rights reserved . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer (drain side) protects removal of a substrate material by an etch process . |
A Dynamic Source-drain Extension MOSFET Using A Separately Biased Conductive Spacer . A new approach to control short-channel effects is demonstrated using a conductive spacer formed over a compensated-channel region . Placed adjacent to (but isolated from) the gate stack , the conductive spacer functions as an auxiliary gate and is biased independently from the principal gate . This arrangement is shown to behave as a dynamic source-drain extension (DSDE) MOSFET . This auxiliary gate is able to invert a portion of the channel adjacent to the LDD on both the source and the drain side (first etch stop layer) , decreasing the effective channel length during the "on" state . Consequently , the transistor appears to have a longer effective gate length during the "ofr' state and a shorter gate length during the "on" state . Using technology computer-aided design simulations , we show four orders of magnitude reduction in I-OFF (at a given I-DSAT) using the conductive spacer device . Conductive spacers provide a useful continuum for scaling transistors to the next generation . It is predicted that nanoscale pass gates with I-OFF values as low as 1 pA/mum are attainable with DSDE MOSFETs . (C) 2002 Elsevier Science Ltd . All rights reserved . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric layer (drain extension) insulates said contact region . |
A Dynamic Source-drain Extension MOSFET Using A Separately Biased Conductive Spacer . A new approach to control short-channel effects is demonstrated using a conductive spacer formed over a compensated-channel region . Placed adjacent to (but isolated from) the gate stack , the conductive spacer functions as an auxiliary gate and is biased independently from the principal gate . This arrangement is shown to behave as a dynamic source-drain extension (first range, first sub interlevel dielectric layer, etching process) (DSDE) MOSFET . This auxiliary gate is able to invert a portion of the channel adjacent to the LDD on both the source and the drain side , decreasing the effective channel length during the "on" state . Consequently , the transistor appears to have a longer effective gate length during the "ofr' state and a shorter gate length during the "on" state . Using technology computer-aided design simulations , we show four orders of magnitude reduction in I-OFF (at a given I-DSAT) using the conductive spacer device . Conductive spacers provide a useful continuum for scaling transistors to the next generation . It is predicted that nanoscale pass gates with I-OFF values as low as 1 pA/mum are attainable with DSDE MOSFETs . (C) 2002 Elsevier Science Ltd . All rights reserved . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch stop layer (gate stack) protects lower layers during an etching process (drain extension) . |
A Dynamic Source-drain Extension MOSFET Using A Separately Biased Conductive Spacer . A new approach to control short-channel effects is demonstrated using a conductive spacer formed over a compensated-channel region . Placed adjacent to (but isolated from) the gate stack (second etch stop layer, second etch stop layers) , the conductive spacer functions as an auxiliary gate and is biased independently from the principal gate . This arrangement is shown to behave as a dynamic source-drain extension (first range, first sub interlevel dielectric layer, etching process) (DSDE) MOSFET . This auxiliary gate is able to invert a portion of the channel adjacent to the LDD on both the source and the drain side , decreasing the effective channel length during the "on" state . Consequently , the transistor appears to have a longer effective gate length during the "ofr' state and a shorter gate length during the "on" state . Using technology computer-aided design simulations , we show four orders of magnitude reduction in I-OFF (at a given I-DSAT) using the conductive spacer device . Conductive spacers provide a useful continuum for scaling transistors to the next generation . It is predicted that nanoscale pass gates with I-OFF values as low as 1 pA/mum are attainable with DSDE MOSFETs . (C) 2002 Elsevier Science Ltd . All rights reserved . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer (drain side) is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer (drain extension) is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer (gate stack) is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
A Dynamic Source-drain Extension MOSFET Using A Separately Biased Conductive Spacer . A new approach to control short-channel effects is demonstrated using a conductive spacer formed over a compensated-channel region . Placed adjacent to (but isolated from) the gate stack (second etch stop layer, second etch stop layers) , the conductive spacer functions as an auxiliary gate and is biased independently from the principal gate . This arrangement is shown to behave as a dynamic source-drain extension (first range, first sub interlevel dielectric layer, etching process) (DSDE) MOSFET . This auxiliary gate is able to invert a portion of the channel adjacent to the LDD on both the source and the drain side (first etch stop layer) , decreasing the effective channel length during the "on" state . Consequently , the transistor appears to have a longer effective gate length during the "ofr' state and a shorter gate length during the "on" state . Using technology computer-aided design simulations , we show four orders of magnitude reduction in I-OFF (at a given I-DSAT) using the conductive spacer device . Conductive spacers provide a useful continuum for scaling transistors to the next generation . It is predicted that nanoscale pass gates with I-OFF values as low as 1 pA/mum are attainable with DSDE MOSFETs . (C) 2002 Elsevier Science Ltd . All rights reserved . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric layer (drain extension) for said contact region is in a first range (drain extension) of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
A Dynamic Source-drain Extension MOSFET Using A Separately Biased Conductive Spacer . A new approach to control short-channel effects is demonstrated using a conductive spacer formed over a compensated-channel region . Placed adjacent to (but isolated from) the gate stack , the conductive spacer functions as an auxiliary gate and is biased independently from the principal gate . This arrangement is shown to behave as a dynamic source-drain extension (first range, first sub interlevel dielectric layer, etching process) (DSDE) MOSFET . This auxiliary gate is able to invert a portion of the channel adjacent to the LDD on both the source and the drain side , decreasing the effective channel length during the "on" state . Consequently , the transistor appears to have a longer effective gate length during the "ofr' state and a shorter gate length during the "on" state . Using technology computer-aided design simulations , we show four orders of magnitude reduction in I-OFF (at a given I-DSAT) using the conductive spacer device . Conductive spacers provide a useful continuum for scaling transistors to the next generation . It is predicted that nanoscale pass gates with I-OFF values as low as 1 pA/mum are attainable with DSDE MOSFETs . (C) 2002 Elsevier Science Ltd . All rights reserved . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer (drain side) and a second etch stop layer (gate stack) wherein said first etch stop layer and said second etch stop layers (gate stack) have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer (drain extension) and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
A Dynamic Source-drain Extension MOSFET Using A Separately Biased Conductive Spacer . A new approach to control short-channel effects is demonstrated using a conductive spacer formed over a compensated-channel region . Placed adjacent to (but isolated from) the gate stack (second etch stop layer, second etch stop layers) , the conductive spacer functions as an auxiliary gate and is biased independently from the principal gate . This arrangement is shown to behave as a dynamic source-drain extension (first range, first sub interlevel dielectric layer, etching process) (DSDE) MOSFET . This auxiliary gate is able to invert a portion of the channel adjacent to the LDD on both the source and the drain side (first etch stop layer) , decreasing the effective channel length during the "on" state . Consequently , the transistor appears to have a longer effective gate length during the "ofr' state and a shorter gate length during the "on" state . Using technology computer-aided design simulations , we show four orders of magnitude reduction in I-OFF (at a given I-DSAT) using the conductive spacer device . Conductive spacers provide a useful continuum for scaling transistors to the next generation . It is predicted that nanoscale pass gates with I-OFF values as low as 1 pA/mum are attainable with DSDE MOSFETs . (C) 2002 Elsevier Science Ltd . All rights reserved . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer (drain side) is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer (drain extension) is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer (gate stack) is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
A Dynamic Source-drain Extension MOSFET Using A Separately Biased Conductive Spacer . A new approach to control short-channel effects is demonstrated using a conductive spacer formed over a compensated-channel region . Placed adjacent to (but isolated from) the gate stack (second etch stop layer, second etch stop layers) , the conductive spacer functions as an auxiliary gate and is biased independently from the principal gate . This arrangement is shown to behave as a dynamic source-drain extension (first range, first sub interlevel dielectric layer, etching process) (DSDE) MOSFET . This auxiliary gate is able to invert a portion of the channel adjacent to the LDD on both the source and the drain side (first etch stop layer) , decreasing the effective channel length during the "on" state . Consequently , the transistor appears to have a longer effective gate length during the "ofr' state and a shorter gate length during the "on" state . Using technology computer-aided design simulations , we show four orders of magnitude reduction in I-OFF (at a given I-DSAT) using the conductive spacer device . Conductive spacers provide a useful continuum for scaling transistors to the next generation . It is predicted that nanoscale pass gates with I-OFF values as low as 1 pA/mum are attainable with DSDE MOSFETs . (C) 2002 Elsevier Science Ltd . All rights reserved . |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region is a first range (drain extension) of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
A Dynamic Source-drain Extension MOSFET Using A Separately Biased Conductive Spacer . A new approach to control short-channel effects is demonstrated using a conductive spacer formed over a compensated-channel region . Placed adjacent to (but isolated from) the gate stack , the conductive spacer functions as an auxiliary gate and is biased independently from the principal gate . This arrangement is shown to behave as a dynamic source-drain extension (first range, first sub interlevel dielectric layer, etching process) (DSDE) MOSFET . This auxiliary gate is able to invert a portion of the channel adjacent to the LDD on both the source and the drain side , decreasing the effective channel length during the "on" state . Consequently , the transistor appears to have a longer effective gate length during the "ofr' state and a shorter gate length during the "on" state . Using technology computer-aided design simulations , we show four orders of magnitude reduction in I-OFF (at a given I-DSAT) using the conductive spacer device . Conductive spacers provide a useful continuum for scaling transistors to the next generation . It is predicted that nanoscale pass gates with I-OFF values as low as 1 pA/mum are attainable with DSDE MOSFETs . (C) 2002 Elsevier Science Ltd . All rights reserved . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B. 18 (2): 695-699 MAR-APR 2000 Publication Year: 2000 Reduction Of Sidewall Defect Induced Leakage Currents By The Use Of Nitrided Field Oxides In Silicon Selective Epitaxial Growth Isolation For Advanced Ultralarge Scale Integration Purdue University, National Semiconductor Corporation Bashir, Su, Sherman, Neudeck, Denton, Obeidat |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area (thermal stress) of said contact region is smaller than a metal layer coupling area (thermal stress) of said contact region ; and a multiple etch (selective epitaxial) stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch (selective epitaxial) stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
Reduction Of Sidewall Defect Induced Leakage Currents By The Use Of Nitrided Field Oxides In Silicon Selective Epitaxial Growth Isolation For Advanced Ultralarge Scale Integration . Defects in the near sidewall region in selective epitaxial (multiple etch, second etch) growth of silicon have prevented its widespread use as a viable dielectric isolation technology . The main cause of these defects has been demonstrated to be thermal stress (substrate coupling area, metal layer coupling area) due to mismatch in the coefficient of thermal expansion between silicon and silicon dioxide . This article presents the detailed electrical characterization of these sidewall defects using P+/N junction diodes fabricated using silicon dioxide and thermally nitrided silicon dioxide as the held insulator . It is shown that the use of field oxide which was nitrided at 1100 degrees C for 60 min in ammonia gas ambient reduced the reverse saturation current density in the diodes by a factor of 6 and also improved the forward recombination and ideality factors when compared to standard thermal field oxide isolated diodes . The improvement of the sidewall quality was attributed to a reduction in thermal stress due to the modification of the coefficient of thermal expansion of nitrided silicon oxide . (C) 2000 American Vacuum Society . [S0734-211X(00)08802-8] . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer protects removal of a substrate material (silicon oxide) by an etch process . |
Reduction Of Sidewall Defect Induced Leakage Currents By The Use Of Nitrided Field Oxides In Silicon Selective Epitaxial Growth Isolation For Advanced Ultralarge Scale Integration . Defects in the near sidewall region in selective epitaxial growth of silicon have prevented its widespread use as a viable dielectric isolation technology . The main cause of these defects has been demonstrated to be thermal stress due to mismatch in the coefficient of thermal expansion between silicon and silicon dioxide . This article presents the detailed electrical characterization of these sidewall defects using P+/N junction diodes fabricated using silicon dioxide and thermally nitrided silicon dioxide as the held insulator . It is shown that the use of field oxide which was nitrided at 1100 degrees C for 60 min in ammonia gas ambient reduced the reverse saturation current density in the diodes by a factor of 6 and also improved the forward recombination and ideality factors when compared to standard thermal field oxide isolated diodes . The improvement of the sidewall quality was attributed to a reduction in thermal stress due to the modification of the coefficient of thermal expansion of nitrided silicon oxide (substrate material) . (C) 2000 American Vacuum Society . [S0734-211X(00)08802-8] . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch (selective epitaxial) stop layer protects lower layers during an etching process . |
Reduction Of Sidewall Defect Induced Leakage Currents By The Use Of Nitrided Field Oxides In Silicon Selective Epitaxial Growth Isolation For Advanced Ultralarge Scale Integration . Defects in the near sidewall region in selective epitaxial (multiple etch, second etch) growth of silicon have prevented its widespread use as a viable dielectric isolation technology . The main cause of these defects has been demonstrated to be thermal stress due to mismatch in the coefficient of thermal expansion between silicon and silicon dioxide . This article presents the detailed electrical characterization of these sidewall defects using P+/N junction diodes fabricated using silicon dioxide and thermally nitrided silicon dioxide as the held insulator . It is shown that the use of field oxide which was nitrided at 1100 degrees C for 60 min in ammonia gas ambient reduced the reverse saturation current density in the diodes by a factor of 6 and also improved the forward recombination and ideality factors when compared to standard thermal field oxide isolated diodes . The improvement of the sidewall quality was attributed to a reduction in thermal stress due to the modification of the coefficient of thermal expansion of nitrided silicon oxide . (C) 2000 American Vacuum Society . [S0734-211X(00)08802-8] . |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area (thermal stress) of said contact region permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area (thermal stress) of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
Reduction Of Sidewall Defect Induced Leakage Currents By The Use Of Nitrided Field Oxides In Silicon Selective Epitaxial Growth Isolation For Advanced Ultralarge Scale Integration . Defects in the near sidewall region in selective epitaxial growth of silicon have prevented its widespread use as a viable dielectric isolation technology . The main cause of these defects has been demonstrated to be thermal stress (substrate coupling area, metal layer coupling area) due to mismatch in the coefficient of thermal expansion between silicon and silicon dioxide . This article presents the detailed electrical characterization of these sidewall defects using P+/N junction diodes fabricated using silicon dioxide and thermally nitrided silicon dioxide as the held insulator . It is shown that the use of field oxide which was nitrided at 1100 degrees C for 60 min in ammonia gas ambient reduced the reverse saturation current density in the diodes by a factor of 6 and also improved the forward recombination and ideality factors when compared to standard thermal field oxide isolated diodes . The improvement of the sidewall quality was attributed to a reduction in thermal stress due to the modification of the coefficient of thermal expansion of nitrided silicon oxide . (C) 2000 American Vacuum Society . [S0734-211X(00)08802-8] . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (selective epitaxial) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
Reduction Of Sidewall Defect Induced Leakage Currents By The Use Of Nitrided Field Oxides In Silicon Selective Epitaxial Growth Isolation For Advanced Ultralarge Scale Integration . Defects in the near sidewall region in selective epitaxial (multiple etch, second etch) growth of silicon have prevented its widespread use as a viable dielectric isolation technology . The main cause of these defects has been demonstrated to be thermal stress due to mismatch in the coefficient of thermal expansion between silicon and silicon dioxide . This article presents the detailed electrical characterization of these sidewall defects using P+/N junction diodes fabricated using silicon dioxide and thermally nitrided silicon dioxide as the held insulator . It is shown that the use of field oxide which was nitrided at 1100 degrees C for 60 min in ammonia gas ambient reduced the reverse saturation current density in the diodes by a factor of 6 and also improved the forward recombination and ideality factors when compared to standard thermal field oxide isolated diodes . The improvement of the sidewall quality was attributed to a reduction in thermal stress due to the modification of the coefficient of thermal expansion of nitrided silicon oxide . (C) 2000 American Vacuum Society . [S0734-211X(00)08802-8] . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch (selective epitaxial) stop insulation layer comprising a first etch stop layer and a second etch (selective epitaxial) stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area (thermal stress) of said contact region is smaller than a metal layer coupling area (thermal stress) of said contact region . |
Reduction Of Sidewall Defect Induced Leakage Currents By The Use Of Nitrided Field Oxides In Silicon Selective Epitaxial Growth Isolation For Advanced Ultralarge Scale Integration . Defects in the near sidewall region in selective epitaxial (multiple etch, second etch) growth of silicon have prevented its widespread use as a viable dielectric isolation technology . The main cause of these defects has been demonstrated to be thermal stress (substrate coupling area, metal layer coupling area) due to mismatch in the coefficient of thermal expansion between silicon and silicon dioxide . This article presents the detailed electrical characterization of these sidewall defects using P+/N junction diodes fabricated using silicon dioxide and thermally nitrided silicon dioxide as the held insulator . It is shown that the use of field oxide which was nitrided at 1100 degrees C for 60 min in ammonia gas ambient reduced the reverse saturation current density in the diodes by a factor of 6 and also improved the forward recombination and ideality factors when compared to standard thermal field oxide isolated diodes . The improvement of the sidewall quality was attributed to a reduction in thermal stress due to the modification of the coefficient of thermal expansion of nitrided silicon oxide . (C) 2000 American Vacuum Society . [S0734-211X(00)08802-8] . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (selective epitaxial) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
Reduction Of Sidewall Defect Induced Leakage Currents By The Use Of Nitrided Field Oxides In Silicon Selective Epitaxial Growth Isolation For Advanced Ultralarge Scale Integration . Defects in the near sidewall region in selective epitaxial (multiple etch, second etch) growth of silicon have prevented its widespread use as a viable dielectric isolation technology . The main cause of these defects has been demonstrated to be thermal stress due to mismatch in the coefficient of thermal expansion between silicon and silicon dioxide . This article presents the detailed electrical characterization of these sidewall defects using P+/N junction diodes fabricated using silicon dioxide and thermally nitrided silicon dioxide as the held insulator . It is shown that the use of field oxide which was nitrided at 1100 degrees C for 60 min in ammonia gas ambient reduced the reverse saturation current density in the diodes by a factor of 6 and also improved the forward recombination and ideality factors when compared to standard thermal field oxide isolated diodes . The improvement of the sidewall quality was attributed to a reduction in thermal stress due to the modification of the coefficient of thermal expansion of nitrided silicon oxide . (C) 2000 American Vacuum Society . [S0734-211X(00)08802-8] . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | IEDM - INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST 1996. : 665-668 1996 Publication Year: 1996 Epitaxial SiGeC/Si Photodetector With Response In The 1.3-1.55 Mu M Wavelength Range University of California, Los Angeles (UCLA) Huang, Thomas, Chu, Wang, Theodore, Ieee |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (low leakage) layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
Epitaxial SiGeC/Si Photodetector With Response In The 1 . 3-1 . 55 Mu M Wavelength Range . We demonstrate a Si-based photodetector with a response in the 1 . 3-1 . 55 mu m wavelength range . The active absorption layer of the pin photodiode consists of a pseudomorphic SiGeC alloy grown on a Si substrate with a Ge content of 55% and a thickness of 800 Angstrom . By using a single-mode fiber butt coupled to the waveguide facet , the external quantum efficiency for a 400-mu m long waveguide is 0 . 2% at 1 . 55 mu m , and 8% at 1 . 3 mu m . The external efficiency can be further improved by using a multiple layer absorber structure . The high efficiency and high speed characteristics together with the low leakage (interlevel dielectric) current density imply potential application of the SiGeC/Si photodetector for optical fiber communications and optical interconnects in the 1 . 3-1 . 55 mu m wavelength range . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (low leakage) layer insulates said contact region . |
Epitaxial SiGeC/Si Photodetector With Response In The 1 . 3-1 . 55 Mu M Wavelength Range . We demonstrate a Si-based photodetector with a response in the 1 . 3-1 . 55 mu m wavelength range . The active absorption layer of the pin photodiode consists of a pseudomorphic SiGeC alloy grown on a Si substrate with a Ge content of 55% and a thickness of 800 Angstrom . By using a single-mode fiber butt coupled to the waveguide facet , the external quantum efficiency for a 400-mu m long waveguide is 0 . 2% at 1 . 55 mu m , and 8% at 1 . 3 mu m . The external efficiency can be further improved by using a multiple layer absorber structure . The high efficiency and high speed characteristics together with the low leakage (interlevel dielectric) current density imply potential application of the SiGeC/Si photodetector for optical fiber communications and optical interconnects in the 1 . 3-1 . 55 mu m wavelength range . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch stop layer protects lower layers during an etching process (high speed) . |
Epitaxial SiGeC/Si Photodetector With Response In The 1 . 3-1 . 55 Mu M Wavelength Range . We demonstrate a Si-based photodetector with a response in the 1 . 3-1 . 55 mu m wavelength range . The active absorption layer of the pin photodiode consists of a pseudomorphic SiGeC alloy grown on a Si substrate with a Ge content of 55% and a thickness of 800 Angstrom . By using a single-mode fiber butt coupled to the waveguide facet , the external quantum efficiency for a 400-mu m long waveguide is 0 . 2% at 1 . 55 mu m , and 8% at 1 . 3 mu m . The external efficiency can be further improved by using a multiple layer absorber structure . The high efficiency and high speed (etching process) characteristics together with the low leakage current density imply potential application of the SiGeC/Si photodetector for optical fiber communications and optical interconnects in the 1 . 3-1 . 55 mu m wavelength range . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (low leakage) layer insulates said contact region . |
Epitaxial SiGeC/Si Photodetector With Response In The 1 . 3-1 . 55 Mu M Wavelength Range . We demonstrate a Si-based photodetector with a response in the 1 . 3-1 . 55 mu m wavelength range . The active absorption layer of the pin photodiode consists of a pseudomorphic SiGeC alloy grown on a Si substrate with a Ge content of 55% and a thickness of 800 Angstrom . By using a single-mode fiber butt coupled to the waveguide facet , the external quantum efficiency for a 400-mu m long waveguide is 0 . 2% at 1 . 55 mu m , and 8% at 1 . 3 mu m . The external efficiency can be further improved by using a multiple layer absorber structure . The high efficiency and high speed characteristics together with the low leakage (interlevel dielectric) current density imply potential application of the SiGeC/Si photodetector for optical fiber communications and optical interconnects in the 1 . 3-1 . 55 mu m wavelength range . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (low leakage) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
Epitaxial SiGeC/Si Photodetector With Response In The 1 . 3-1 . 55 Mu M Wavelength Range . We demonstrate a Si-based photodetector with a response in the 1 . 3-1 . 55 mu m wavelength range . The active absorption layer of the pin photodiode consists of a pseudomorphic SiGeC alloy grown on a Si substrate with a Ge content of 55% and a thickness of 800 Angstrom . By using a single-mode fiber butt coupled to the waveguide facet , the external quantum efficiency for a 400-mu m long waveguide is 0 . 2% at 1 . 55 mu m , and 8% at 1 . 3 mu m . The external efficiency can be further improved by using a multiple layer absorber structure . The high efficiency and high speed characteristics together with the low leakage (interlevel dielectric) current density imply potential application of the SiGeC/Si photodetector for optical fiber communications and optical interconnects in the 1 . 3-1 . 55 mu m wavelength range . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric (low leakage) layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
Epitaxial SiGeC/Si Photodetector With Response In The 1 . 3-1 . 55 Mu M Wavelength Range . We demonstrate a Si-based photodetector with a response in the 1 . 3-1 . 55 mu m wavelength range . The active absorption layer of the pin photodiode consists of a pseudomorphic SiGeC alloy grown on a Si substrate with a Ge content of 55% and a thickness of 800 Angstrom . By using a single-mode fiber butt coupled to the waveguide facet , the external quantum efficiency for a 400-mu m long waveguide is 0 . 2% at 1 . 55 mu m , and 8% at 1 . 3 mu m . The external efficiency can be further improved by using a multiple layer absorber structure . The high efficiency and high speed characteristics together with the low leakage (interlevel dielectric) current density imply potential application of the SiGeC/Si photodetector for optical fiber communications and optical interconnects in the 1 . 3-1 . 55 mu m wavelength range . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (low leakage) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
Epitaxial SiGeC/Si Photodetector With Response In The 1 . 3-1 . 55 Mu M Wavelength Range . We demonstrate a Si-based photodetector with a response in the 1 . 3-1 . 55 mu m wavelength range . The active absorption layer of the pin photodiode consists of a pseudomorphic SiGeC alloy grown on a Si substrate with a Ge content of 55% and a thickness of 800 Angstrom . By using a single-mode fiber butt coupled to the waveguide facet , the external quantum efficiency for a 400-mu m long waveguide is 0 . 2% at 1 . 55 mu m , and 8% at 1 . 3 mu m . The external efficiency can be further improved by using a multiple layer absorber structure . The high efficiency and high speed characteristics together with the low leakage (interlevel dielectric) current density imply potential application of the SiGeC/Si photodetector for optical fiber communications and optical interconnects in the 1 . 3-1 . 55 mu m wavelength range . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (low leakage) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
Epitaxial SiGeC/Si Photodetector With Response In The 1 . 3-1 . 55 Mu M Wavelength Range . We demonstrate a Si-based photodetector with a response in the 1 . 3-1 . 55 mu m wavelength range . The active absorption layer of the pin photodiode consists of a pseudomorphic SiGeC alloy grown on a Si substrate with a Ge content of 55% and a thickness of 800 Angstrom . By using a single-mode fiber butt coupled to the waveguide facet , the external quantum efficiency for a 400-mu m long waveguide is 0 . 2% at 1 . 55 mu m , and 8% at 1 . 3 mu m . The external efficiency can be further improved by using a multiple layer absorber structure . The high efficiency and high speed characteristics together with the low leakage (interlevel dielectric) current density imply potential application of the SiGeC/Si photodetector for optical fiber communications and optical interconnects in the 1 . 3-1 . 55 mu m wavelength range . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | THIN SOLID FILMS. 262 (1-2): 104-119 JUN 15 1995 Publication Year: 1995 ENCAPSULATED COPPER INTERCONNECTION DEVICES USING SIDEWALL BARRIERS Thin Film Research Center, Hitachi''s Central Research Laboratory, Hitachi, Ibaraki, Japan, Intel Components Research Laboratory, 3065 Bowers Ave. SC1-03, Santa Clara, CA 95052, USA Gardner, Onuki, Kudoo, Misawa, Vu |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (thin film) of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch (encapsulation material) stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
ENCAPSULATED COPPER INTERCONNECTION DEVICES USING SIDEWALL BARRIERS . The concept of treating interconnections as a device and designing them while keeping both materials and structures in mind is presented . An example using molybdenum and copper is demonstrated . Copper introduces new problems such as diffusion in addition to the traditional problems for interconnections such as adhesion . A new structure called a sidewall barrier is used as part of a copper interconnection . This structure can be combined with a multilayer thin film (metal layer coupling area) resulting in a completely encapsulated interconnection . The technique is versatile enough that almost any material including dielectrics can be used as the encapsulation material (second etch, second interlevel dielectric layer) and the sidewall barrier can be either on the outside of a feature or the inside of a space . Several potential metals (Mo , TiN , W) for encapsulating copper are examined and molybdenum is chosen and used . Both sputtering and switched-bias sputtering are used to deposit molybdenum sidewall barriers followed by anisotropic etching for patterning . Electromigration measurements of bilayered copper films reveal that there are problems with TiN and tungsten barriers . Copper oxidation , stress , electromigration , hillock growth , resistivity , diffusion and adhesion are all studied . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch (encapsulation material) stop layer protects lower layers during an etching process . |
ENCAPSULATED COPPER INTERCONNECTION DEVICES USING SIDEWALL BARRIERS . The concept of treating interconnections as a device and designing them while keeping both materials and structures in mind is presented . An example using molybdenum and copper is demonstrated . Copper introduces new problems such as diffusion in addition to the traditional problems for interconnections such as adhesion . A new structure called a sidewall barrier is used as part of a copper interconnection . This structure can be combined with a multilayer thin film resulting in a completely encapsulated interconnection . The technique is versatile enough that almost any material including dielectrics can be used as the encapsulation material (second etch, second interlevel dielectric layer) and the sidewall barrier can be either on the outside of a feature or the inside of a space . Several potential metals (Mo , TiN , W) for encapsulating copper are examined and molybdenum is chosen and used . Both sputtering and switched-bias sputtering are used to deposit molybdenum sidewall barriers followed by anisotropic etching for patterning . Electromigration measurements of bilayered copper films reveal that there are problems with TiN and tungsten barriers . Copper oxidation , stress , electromigration , hillock growth , resistivity , diffusion and adhesion are all studied . |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area of said contact region permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area (thin film) of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
ENCAPSULATED COPPER INTERCONNECTION DEVICES USING SIDEWALL BARRIERS . The concept of treating interconnections as a device and designing them while keeping both materials and structures in mind is presented . An example using molybdenum and copper is demonstrated . Copper introduces new problems such as diffusion in addition to the traditional problems for interconnections such as adhesion . A new structure called a sidewall barrier is used as part of a copper interconnection . This structure can be combined with a multilayer thin film (metal layer coupling area) resulting in a completely encapsulated interconnection . The technique is versatile enough that almost any material including dielectrics can be used as the encapsulation material and the sidewall barrier can be either on the outside of a feature or the inside of a space . Several potential metals (Mo , TiN , W) for encapsulating copper are examined and molybdenum is chosen and used . Both sputtering and switched-bias sputtering are used to deposit molybdenum sidewall barriers followed by anisotropic etching for patterning . Electromigration measurements of bilayered copper films reveal that there are problems with TiN and tungsten barriers . Copper oxidation , stress , electromigration , hillock growth , resistivity , diffusion and adhesion are all studied . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (encapsulation material) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
ENCAPSULATED COPPER INTERCONNECTION DEVICES USING SIDEWALL BARRIERS . The concept of treating interconnections as a device and designing them while keeping both materials and structures in mind is presented . An example using molybdenum and copper is demonstrated . Copper introduces new problems such as diffusion in addition to the traditional problems for interconnections such as adhesion . A new structure called a sidewall barrier is used as part of a copper interconnection . This structure can be combined with a multilayer thin film resulting in a completely encapsulated interconnection . The technique is versatile enough that almost any material including dielectrics can be used as the encapsulation material (second etch, second interlevel dielectric layer) and the sidewall barrier can be either on the outside of a feature or the inside of a space . Several potential metals (Mo , TiN , W) for encapsulating copper are examined and molybdenum is chosen and used . Both sputtering and switched-bias sputtering are used to deposit molybdenum sidewall barriers followed by anisotropic etching for patterning . Electromigration measurements of bilayered copper films reveal that there are problems with TiN and tungsten barriers . Copper oxidation , stress , electromigration , hillock growth , resistivity , diffusion and adhesion are all studied . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch (encapsulation material) stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer (encapsulation material) , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (thin film) of said contact region . |
ENCAPSULATED COPPER INTERCONNECTION DEVICES USING SIDEWALL BARRIERS . The concept of treating interconnections as a device and designing them while keeping both materials and structures in mind is presented . An example using molybdenum and copper is demonstrated . Copper introduces new problems such as diffusion in addition to the traditional problems for interconnections such as adhesion . A new structure called a sidewall barrier is used as part of a copper interconnection . This structure can be combined with a multilayer thin film (metal layer coupling area) resulting in a completely encapsulated interconnection . The technique is versatile enough that almost any material including dielectrics can be used as the encapsulation material (second etch, second interlevel dielectric layer) and the sidewall barrier can be either on the outside of a feature or the inside of a space . Several potential metals (Mo , TiN , W) for encapsulating copper are examined and molybdenum is chosen and used . Both sputtering and switched-bias sputtering are used to deposit molybdenum sidewall barriers followed by anisotropic etching for patterning . Electromigration measurements of bilayered copper films reveal that there are problems with TiN and tungsten barriers . Copper oxidation , stress , electromigration , hillock growth , resistivity , diffusion and adhesion are all studied . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (encapsulation material) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
ENCAPSULATED COPPER INTERCONNECTION DEVICES USING SIDEWALL BARRIERS . The concept of treating interconnections as a device and designing them while keeping both materials and structures in mind is presented . An example using molybdenum and copper is demonstrated . Copper introduces new problems such as diffusion in addition to the traditional problems for interconnections such as adhesion . A new structure called a sidewall barrier is used as part of a copper interconnection . This structure can be combined with a multilayer thin film resulting in a completely encapsulated interconnection . The technique is versatile enough that almost any material including dielectrics can be used as the encapsulation material (second etch, second interlevel dielectric layer) and the sidewall barrier can be either on the outside of a feature or the inside of a space . Several potential metals (Mo , TiN , W) for encapsulating copper are examined and molybdenum is chosen and used . Both sputtering and switched-bias sputtering are used to deposit molybdenum sidewall barriers followed by anisotropic etching for patterning . Electromigration measurements of bilayered copper films reveal that there are problems with TiN and tungsten barriers . Copper oxidation , stress , electromigration , hillock growth , resistivity , diffusion and adhesion are all studied . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | JOURNAL OF THE ELECTROCHEMICAL SOCIETY. 139 (8): 2318-2322 AUG 1992 Publication Year: 1992 A STACKED CAPACITOR CELL WITH A FULLY SELF-ALIGNED CONTACT PROCESS FOR HIGH-DENSITY DYNAMIC RANDOM-ACCESS MEMORIES Siemens Aktiengesellschaft Kusters, Sesselmann |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer (subsequent annealing) directly on said substrate in said contact region ; a first sub interlevel dielectric (stacked capacitor) layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
A STACKED CAPACITOR CELL WITH A FULLY SELF-ALIGNED CONTACT PROCESS FOR HIGH-DENSITY DYNAMIC RANDOM-ACCESS MEMORIES . A new , self-aligned contact process has been developed for a stacked capacitor (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) dynamic random access memories (DRAM) cell . The bit line contact is three-f old , self -aligned with respect to the transistor gate , the field oxide , and the upper cell plate of the stacked capacitor . An oxide spacer technique is used to encapsulate the transistor gate . Etching of the overlapping bit line contact is self-aligned by a proper choice of deposited materials and etch selectivities and does not affect the oxide isolation of the transistor gate and the field oxide . In addition , the stacked capacitor cell plate is self-aligned and isolated from the bit line by a selective oxidation process . Using this technique , optimal contact window shaping and improved planarization of the interconnect dielectric isolation is simultaneously achieved . This fully self-aligned contact process allows an increase in cell capacitance by a f actor of about 1 . 4 . No electrical degradation compared to a conventional contact process has been observed . For reduction of contact resistance , a process based on Si+-ion implantation with subsequent annealing (first etch stop layer) has been developed . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer (subsequent annealing) protects removal of a substrate material by an etch process (ion implantation) . |
A STACKED CAPACITOR CELL WITH A FULLY SELF-ALIGNED CONTACT PROCESS FOR HIGH-DENSITY DYNAMIC RANDOM-ACCESS MEMORIES . A new , self-aligned contact process has been developed for a stacked capacitor dynamic random access memories (DRAM) cell . The bit line contact is three-f old , self -aligned with respect to the transistor gate , the field oxide , and the upper cell plate of the stacked capacitor . An oxide spacer technique is used to encapsulate the transistor gate . Etching of the overlapping bit line contact is self-aligned by a proper choice of deposited materials and etch selectivities and does not affect the oxide isolation of the transistor gate and the field oxide . In addition , the stacked capacitor cell plate is self-aligned and isolated from the bit line by a selective oxidation process . Using this technique , optimal contact window shaping and improved planarization of the interconnect dielectric isolation is simultaneously achieved . This fully self-aligned contact process allows an increase in cell capacitance by a f actor of about 1 . 4 . No electrical degradation compared to a conventional contact process has been observed . For reduction of contact resistance , a process based on Si+-ion implantation (etch process) with subsequent annealing (first etch stop layer) has been developed . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (stacked capacitor) layer insulates said contact region . |
A STACKED CAPACITOR CELL WITH A FULLY SELF-ALIGNED CONTACT PROCESS FOR HIGH-DENSITY DYNAMIC RANDOM-ACCESS MEMORIES . A new , self-aligned contact process has been developed for a stacked capacitor (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) dynamic random access memories (DRAM) cell . The bit line contact is three-f old , self -aligned with respect to the transistor gate , the field oxide , and the upper cell plate of the stacked capacitor . An oxide spacer technique is used to encapsulate the transistor gate . Etching of the overlapping bit line contact is self-aligned by a proper choice of deposited materials and etch selectivities and does not affect the oxide isolation of the transistor gate and the field oxide . In addition , the stacked capacitor cell plate is self-aligned and isolated from the bit line by a selective oxidation process . Using this technique , optimal contact window shaping and improved planarization of the interconnect dielectric isolation is simultaneously achieved . This fully self-aligned contact process allows an increase in cell capacitance by a f actor of about 1 . 4 . No electrical degradation compared to a conventional contact process has been observed . For reduction of contact resistance , a process based on Si+-ion implantation with subsequent annealing has been developed . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (stacked capacitor) layer insulates said contact region . |
A STACKED CAPACITOR CELL WITH A FULLY SELF-ALIGNED CONTACT PROCESS FOR HIGH-DENSITY DYNAMIC RANDOM-ACCESS MEMORIES . A new , self-aligned contact process has been developed for a stacked capacitor (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) dynamic random access memories (DRAM) cell . The bit line contact is three-f old , self -aligned with respect to the transistor gate , the field oxide , and the upper cell plate of the stacked capacitor . An oxide spacer technique is used to encapsulate the transistor gate . Etching of the overlapping bit line contact is self-aligned by a proper choice of deposited materials and etch selectivities and does not affect the oxide isolation of the transistor gate and the field oxide . In addition , the stacked capacitor cell plate is self-aligned and isolated from the bit line by a selective oxidation process . Using this technique , optimal contact window shaping and improved planarization of the interconnect dielectric isolation is simultaneously achieved . This fully self-aligned contact process allows an increase in cell capacitance by a f actor of about 1 . 4 . No electrical degradation compared to a conventional contact process has been observed . For reduction of contact resistance , a process based on Si+-ion implantation with subsequent annealing has been developed . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer (subsequent annealing) is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (stacked capacitor) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
A STACKED CAPACITOR CELL WITH A FULLY SELF-ALIGNED CONTACT PROCESS FOR HIGH-DENSITY DYNAMIC RANDOM-ACCESS MEMORIES . A new , self-aligned contact process has been developed for a stacked capacitor (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) dynamic random access memories (DRAM) cell . The bit line contact is three-f old , self -aligned with respect to the transistor gate , the field oxide , and the upper cell plate of the stacked capacitor . An oxide spacer technique is used to encapsulate the transistor gate . Etching of the overlapping bit line contact is self-aligned by a proper choice of deposited materials and etch selectivities and does not affect the oxide isolation of the transistor gate and the field oxide . In addition , the stacked capacitor cell plate is self-aligned and isolated from the bit line by a selective oxidation process . Using this technique , optimal contact window shaping and improved planarization of the interconnect dielectric isolation is simultaneously achieved . This fully self-aligned contact process allows an increase in cell capacitance by a f actor of about 1 . 4 . No electrical degradation compared to a conventional contact process has been observed . For reduction of contact resistance , a process based on Si+-ion implantation with subsequent annealing (first etch stop layer) has been developed . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric (stacked capacitor) layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
A STACKED CAPACITOR CELL WITH A FULLY SELF-ALIGNED CONTACT PROCESS FOR HIGH-DENSITY DYNAMIC RANDOM-ACCESS MEMORIES . A new , self-aligned contact process has been developed for a stacked capacitor (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) dynamic random access memories (DRAM) cell . The bit line contact is three-f old , self -aligned with respect to the transistor gate , the field oxide , and the upper cell plate of the stacked capacitor . An oxide spacer technique is used to encapsulate the transistor gate . Etching of the overlapping bit line contact is self-aligned by a proper choice of deposited materials and etch selectivities and does not affect the oxide isolation of the transistor gate and the field oxide . In addition , the stacked capacitor cell plate is self-aligned and isolated from the bit line by a selective oxidation process . Using this technique , optimal contact window shaping and improved planarization of the interconnect dielectric isolation is simultaneously achieved . This fully self-aligned contact process allows an increase in cell capacitance by a f actor of about 1 . 4 . No electrical degradation compared to a conventional contact process has been observed . For reduction of contact resistance , a process based on Si+-ion implantation with subsequent annealing has been developed . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer (subsequent annealing) and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (stacked capacitor) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
A STACKED CAPACITOR CELL WITH A FULLY SELF-ALIGNED CONTACT PROCESS FOR HIGH-DENSITY DYNAMIC RANDOM-ACCESS MEMORIES . A new , self-aligned contact process has been developed for a stacked capacitor (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) dynamic random access memories (DRAM) cell . The bit line contact is three-f old , self -aligned with respect to the transistor gate , the field oxide , and the upper cell plate of the stacked capacitor . An oxide spacer technique is used to encapsulate the transistor gate . Etching of the overlapping bit line contact is self-aligned by a proper choice of deposited materials and etch selectivities and does not affect the oxide isolation of the transistor gate and the field oxide . In addition , the stacked capacitor cell plate is self-aligned and isolated from the bit line by a selective oxidation process . Using this technique , optimal contact window shaping and improved planarization of the interconnect dielectric isolation is simultaneously achieved . This fully self-aligned contact process allows an increase in cell capacitance by a f actor of about 1 . 4 . No electrical degradation compared to a conventional contact process has been observed . For reduction of contact resistance , a process based on Si+-ion implantation with subsequent annealing (first etch stop layer) has been developed . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer (subsequent annealing) is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (stacked capacitor) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
A STACKED CAPACITOR CELL WITH A FULLY SELF-ALIGNED CONTACT PROCESS FOR HIGH-DENSITY DYNAMIC RANDOM-ACCESS MEMORIES . A new , self-aligned contact process has been developed for a stacked capacitor (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) dynamic random access memories (DRAM) cell . The bit line contact is three-f old , self -aligned with respect to the transistor gate , the field oxide , and the upper cell plate of the stacked capacitor . An oxide spacer technique is used to encapsulate the transistor gate . Etching of the overlapping bit line contact is self-aligned by a proper choice of deposited materials and etch selectivities and does not affect the oxide isolation of the transistor gate and the field oxide . In addition , the stacked capacitor cell plate is self-aligned and isolated from the bit line by a selective oxidation process . Using this technique , optimal contact window shaping and improved planarization of the interconnect dielectric isolation is simultaneously achieved . This fully self-aligned contact process allows an increase in cell capacitance by a f actor of about 1 . 4 . No electrical degradation compared to a conventional contact process has been observed . For reduction of contact resistance , a process based on Si+-ion implantation with subsequent annealing (first etch stop layer) has been developed . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US6441418B1 Filed: 1999-11-01 Issued: 2002-08-27 Spacer narrowed, dual width contact for charge gain reduction (Original Assignee) Advanced Micro Devices Inc (Current Assignee) Monterey Research LLC Jeffrey A. Shields, Bharath Rangarajan |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch (first etch) stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (contact hole) layer over said first etch stop layer ; a second etch (second etch) stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US6441418B1 CLAIM 1 . An integrated circuit comprising : two flash memory gate structures separated by an insulating layer , the insulating layer including an aperture extending from the top of the insulating layer to the bottom of the insulating layer , wherein the aperture defines a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) ; an etch stop layer , the etch stop layer being located in the insulating layer ; a conductive contact , the conductive contact being located in the aperture and having a top portion extending from the top of the aperture to the etch stop layer and a bottom portion extending from the top portion to the bottom of the aperture , wherein the entire bottom portion has a width less than the top portion ; and dielectric spacers , the dielectric spacers being located along side walls of the entire top portion . US6441418B1 CLAIM 3 . The integrated circuit of claim 1 , wherein the aperture is formed by a first and second etch (second etch) , the first etch (first etch) removing material from the insulating layer down to the etch stop layer . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch (first etch) stop layer protects removal of a substrate material by an etch process . |
US6441418B1 CLAIM 3 . The integrated circuit of claim 1 , wherein the aperture is formed by a first and second etch , the first etch (first etch) removing material from the insulating layer down to the etch stop layer . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (contact hole) layer insulates said contact region . |
US6441418B1 CLAIM 1 . An integrated circuit comprising : two flash memory gate structures separated by an insulating layer , the insulating layer including an aperture extending from the top of the insulating layer to the bottom of the insulating layer , wherein the aperture defines a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) ; an etch stop layer , the etch stop layer being located in the insulating layer ; a conductive contact , the conductive contact being located in the aperture and having a top portion extending from the top of the aperture to the etch stop layer and a bottom portion extending from the top portion to the bottom of the aperture , wherein the entire bottom portion has a width less than the top portion ; and dielectric spacers , the dielectric spacers being located along side walls of the entire top portion . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch (second etch) stop layer protects lower layers during an etching process . |
US6441418B1 CLAIM 3 . The integrated circuit of claim 1 , wherein the aperture is formed by a first and second etch (second etch) , the first etch removing material from the insulating layer down to the etch stop layer . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (contact hole) layer insulates said contact region . |
US6441418B1 CLAIM 1 . An integrated circuit comprising : two flash memory gate structures separated by an insulating layer , the insulating layer including an aperture extending from the top of the insulating layer to the bottom of the insulating layer , wherein the aperture defines a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) ; an etch stop layer , the etch stop layer being located in the insulating layer ; a conductive contact , the conductive contact being located in the aperture and having a top portion extending from the top of the aperture to the etch stop layer and a bottom portion extending from the top portion to the bottom of the aperture , wherein the entire bottom portion has a width less than the top portion ; and dielectric spacers , the dielectric spacers being located along side walls of the entire top portion . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch (first etch) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (contact hole) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (second etch) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6441418B1 CLAIM 1 . An integrated circuit comprising : two flash memory gate structures separated by an insulating layer , the insulating layer including an aperture extending from the top of the insulating layer to the bottom of the insulating layer , wherein the aperture defines a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) ; an etch stop layer , the etch stop layer being located in the insulating layer ; a conductive contact , the conductive contact being located in the aperture and having a top portion extending from the top of the aperture to the etch stop layer and a bottom portion extending from the top portion to the bottom of the aperture , wherein the entire bottom portion has a width less than the top portion ; and dielectric spacers , the dielectric spacers being located along side walls of the entire top portion . US6441418B1 CLAIM 3 . The integrated circuit of claim 1 , wherein the aperture is formed by a first and second etch (second etch) , the first etch (first etch) removing material from the insulating layer down to the etch stop layer . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space (first space, lower half) in a portion of said first sub interlevel dielectric (contact hole) layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space (second space) in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US6441418B1 CLAIM 1 . An integrated circuit comprising : two flash memory gate structures separated by an insulating layer , the insulating layer including an aperture extending from the top of the insulating layer to the bottom of the insulating layer , wherein the aperture defines a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) ; an etch stop layer , the etch stop layer being located in the insulating layer ; a conductive contact , the conductive contact being located in the aperture and having a top portion extending from the top of the aperture to the etch stop layer and a bottom portion extending from the top portion to the bottom of the aperture , wherein the entire bottom portion has a width less than the top portion ; and dielectric spacers , the dielectric spacers being located along side walls of the entire top portion . US6441418B1 CLAIM 7 . The integrated circuit of claim 1 , wherein the top portion is located in substantially the upper half of the insulating layer and the bottom portion is located in substantially the lower half (first space) of the insulating layer . US6441418B1 CLAIM 10 . The integrated circuit of claim 8 , wherein the spacers have a first space (first space) r width at the top of the second section and a second space (second space) r width at the bottom of the second section , the first spacer width being less than the second spacer width . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch (first etch) stop layer and a second etch (second etch) stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (contact hole) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom (top portion) , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US6441418B1 CLAIM 1 . An integrated circuit comprising : two flash memory gate structures separated by an insulating layer , the insulating layer including an aperture extending from the top of the insulating layer to the bottom of the insulating layer , wherein the aperture defines a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) ; an etch stop layer , the etch stop layer being located in the insulating layer ; a conductive contact , the conductive contact being located in the aperture and having a top portion (contact bottom) extending from the top of the aperture to the etch stop layer and a bottom portion extending from the top portion to the bottom of the aperture , wherein the entire bottom portion has a width less than the top portion ; and dielectric spacers , the dielectric spacers being located along side walls of the entire top portion . US6441418B1 CLAIM 3 . The integrated circuit of claim 1 , wherein the aperture is formed by a first and second etch (second etch) , the first etch (first etch) removing material from the insulating layer down to the etch stop layer . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch (first etch) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (contact hole) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (second etch) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6441418B1 CLAIM 1 . An integrated circuit comprising : two flash memory gate structures separated by an insulating layer , the insulating layer including an aperture extending from the top of the insulating layer to the bottom of the insulating layer , wherein the aperture defines a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) ; an etch stop layer , the etch stop layer being located in the insulating layer ; a conductive contact , the conductive contact being located in the aperture and having a top portion extending from the top of the aperture to the etch stop layer and a bottom portion extending from the top portion to the bottom of the aperture , wherein the entire bottom portion has a width less than the top portion ; and dielectric spacers , the dielectric spacers being located along side walls of the entire top portion . US6441418B1 CLAIM 3 . The integrated circuit of claim 1 , wherein the aperture is formed by a first and second etch (second etch) , the first etch (first etch) removing material from the insulating layer down to the etch stop layer . |
| US7977797B2 CLAIM 13 . An integrated circuit of claim 11 further comprising a floating gate (floating gate) . |
US6441418B1 CLAIM 8 . An integrated circuit comprising : two gate structures , the gate structures having a control gate and a floating gate (floating gate) ; two insulative layers separating the two gate structures ; an etch stop layer disposed between the two insulative layers ; a first section of conductive material having a first width , the first section being located in an aperture of one of the two insulative layers and extending below the etch stop layer ; a second section of conductive material disposed over the first section and located in an aperture of the other of the two insulative layers and above the etch stop layer , the entire second section having a width greater than the first width ; and spacers along lateral walls of the entire aperture of the second section . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US20040115914A1 Filed: 2003-12-05 Issued: 2004-06-17 Method of fabricating integrated circuitry, and method of forming a conductive line (Original Assignee) Manning H. Montgomery (Current Assignee) Round Rock Research LLC H. Manning |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch (etch stop layer) stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US20040115914A1 CLAIM 39 . A method of fabricating integrated circuitry comprising : forming a gate dielectric layer over a semiconductor substrate ; forming a conductively doped semiconductive layer over the gate dielectric layer ; forming an insulative capping layer over the semiconductive layer ; forming an etch stop layer (second etch) over the insulative capping layer ; patterning and etching the etch stop layer , the capping layer and the semiconductive layer into a plurality of transistor gate lines ; depositing an oxide layer over the substrate and the transistor gate lines to a thickness greater than that of the combined etched etch stop layer , capping layer and semiconductor layer ; chemical mechanical polishing the deposited oxide layer using the etch stop layer as an etch stop ; patterning and etching the polished oxide layer to expose material of the semiconductor substrate in at least two discrete locations proximate different of the plurality of gate lines ; depositing a local interconnect layer into electrical connection with said locations and over said plurality of gate lines ; and etching the local interconnect layer into a local interconnect line overlying at least two of said plurality of gate lines . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer protects removal of a substrate material (substrate material) by an etch process . |
US20040115914A1 CLAIM 23 . A method of forming a local interconnect comprising : forming a pair of transistor gates having respective opposing sidewalls over a semiconductor substrate ; depositing an insulating layer over the substrate and between the pair of transistor gates ; etching a first contact opening into the insulating layer to proximate the substrate between the pair of transistor gates and another contact opening through the insulating layer to proximate the substrate proximate an opposing side of one of the pair of transistor gates ; forming insulating sidewall spacers over the opposing sidewalls of the one transistor gate , the insulating layer being received between at least one of said sidewalls and one of said sidewall spacers ; and forming a local interconnect layer to overlie the one transistor gate and electrically connect with semiconductor substrate material (substrate material) between the pair of transistor gates and semiconductor substrate material proximate the opposing side of the one transistor gate . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch (etch stop layer) stop layer protects lower layers during an etching process . |
US20040115914A1 CLAIM 39 . A method of fabricating integrated circuitry comprising : forming a gate dielectric layer over a semiconductor substrate ; forming a conductively doped semiconductive layer over the gate dielectric layer ; forming an insulative capping layer over the semiconductive layer ; forming an etch stop layer (second etch) over the insulative capping layer ; patterning and etching the etch stop layer , the capping layer and the semiconductive layer into a plurality of transistor gate lines ; depositing an oxide layer over the substrate and the transistor gate lines to a thickness greater than that of the combined etched etch stop layer , capping layer and semiconductor layer ; chemical mechanical polishing the deposited oxide layer using the etch stop layer as an etch stop ; patterning and etching the polished oxide layer to expose material of the semiconductor substrate in at least two discrete locations proximate different of the plurality of gate lines ; depositing a local interconnect layer into electrical connection with said locations and over said plurality of gate lines ; and etching the local interconnect layer into a local interconnect line overlying at least two of said plurality of gate lines . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (etch stop layer) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US20040115914A1 CLAIM 39 . A method of fabricating integrated circuitry comprising : forming a gate dielectric layer over a semiconductor substrate ; forming a conductively doped semiconductive layer over the gate dielectric layer ; forming an insulative capping layer over the semiconductive layer ; forming an etch stop layer (second etch) over the insulative capping layer ; patterning and etching the etch stop layer , the capping layer and the semiconductive layer into a plurality of transistor gate lines ; depositing an oxide layer over the substrate and the transistor gate lines to a thickness greater than that of the combined etched etch stop layer , capping layer and semiconductor layer ; chemical mechanical polishing the deposited oxide layer using the etch stop layer as an etch stop ; patterning and etching the polished oxide layer to expose material of the semiconductor substrate in at least two discrete locations proximate different of the plurality of gate lines ; depositing a local interconnect layer into electrical connection with said locations and over said plurality of gate lines ; and etching the local interconnect layer into a local interconnect line overlying at least two of said plurality of gate lines . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US20040115914A1 CLAIM 9 . The method of claim 1 comprising : forming field isolation material regions and active area regions on the semiconductor substrate before the depositing ; etching a trench into the field isolation material and the insulating layer into a desired local interconnect line configuration ; and forming (anti reflective coating) a local interconnect layer of material over the substrate which at least partially fills the trench and which electrically connects with one of the active area regions . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch (etch stop layer) stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US20040115914A1 CLAIM 39 . A method of fabricating integrated circuitry comprising : forming a gate dielectric layer over a semiconductor substrate ; forming a conductively doped semiconductive layer over the gate dielectric layer ; forming an insulative capping layer over the semiconductive layer ; forming an etch stop layer (second etch) over the insulative capping layer ; patterning and etching the etch stop layer , the capping layer and the semiconductive layer into a plurality of transistor gate lines ; depositing an oxide layer over the substrate and the transistor gate lines to a thickness greater than that of the combined etched etch stop layer , capping layer and semiconductor layer ; chemical mechanical polishing the deposited oxide layer using the etch stop layer as an etch stop ; patterning and etching the polished oxide layer to expose material of the semiconductor substrate in at least two discrete locations proximate different of the plurality of gate lines ; depositing a local interconnect layer into electrical connection with said locations and over said plurality of gate lines ; and etching the local interconnect layer into a local interconnect line overlying at least two of said plurality of gate lines . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (etch stop layer) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US20040115914A1 CLAIM 39 . A method of fabricating integrated circuitry comprising : forming a gate dielectric layer over a semiconductor substrate ; forming a conductively doped semiconductive layer over the gate dielectric layer ; forming an insulative capping layer over the semiconductive layer ; forming an etch stop layer (second etch) over the insulative capping layer ; patterning and etching the etch stop layer , the capping layer and the semiconductive layer into a plurality of transistor gate lines ; depositing an oxide layer over the substrate and the transistor gate lines to a thickness greater than that of the combined etched etch stop layer , capping layer and semiconductor layer ; chemical mechanical polishing the deposited oxide layer using the etch stop layer as an etch stop ; patterning and etching the polished oxide layer to expose material of the semiconductor substrate in at least two discrete locations proximate different of the plurality of gate lines ; depositing a local interconnect layer into electrical connection with said locations and over said plurality of gate lines ; and etching the local interconnect layer into a local interconnect line overlying at least two of said plurality of gate lines . |
| US7977797B2 CLAIM 13 . An integrated circuit of claim 11 further comprising a floating gate (drain region) . |
US20040115914A1 CLAIM 35 . A method of forming a local interconnect comprising : forming at least two transistor gates over a semiconductor substrate ; depositing a local interconnect layer to overlie at least one of the transistor gates and interconnect at least one source/drain region (floating gate) of one of the gates with semiconductor substrate material proximate another of the transistor gates ; implanting conductivity enhancing impurity into the local interconnect layer in at least two implanting steps , one of the two implantings providing a peak implant location which is deeper into the layer than the other ; and diffusing conductivity enhancing impurity from the local interconnect layer into semiconductor substrate material therebeneath . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US20040115914A1 CLAIM 9 . The method of claim 1 comprising : forming field isolation material regions and active area regions on the semiconductor substrate before the depositing ; etching a trench into the field isolation material and the insulating layer into a desired local interconnect line configuration ; and forming (anti reflective coating) a local interconnect layer of material over the substrate which at least partially fills the trench and which electrically connects with one of the active area regions . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US20030132526A1 Filed: 2003-01-13 Issued: 2003-07-17 Semiconductor device having a contact window and fabrication method thereof (Original Assignee) Samsung Electronics Co Ltd (Current Assignee) Samsung Electronics Co Ltd Jeong-sic Jeon, Jae-woong Kim |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch (wet etch, dry etch, low rate) stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch (wet etch, dry etch, low rate) stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch (wet etch, dry etch, low rate) stop layer (wet etch, dry etch, low rate) over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US20030132526A1 CLAIM 2 . The method of claim 1 , wherein the anisotropic etching is performed using a dry etch (multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers, second etch) ing process and the isotropic etching is performed using a wet etch (multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers, second etch) ing process . US20030132526A1 CLAIM 5 . The method of claim 1 , wherein the lower dielectric layer is formed by a process in which a flow rate (multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers, second etch) of O 3 gas decreases and a flow rate of O 2 gas increases . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch (wet etch, dry etch, low rate) stop layer protects removal of a substrate material by an etch process (wet etch, dry etch, low rate) . |
US20030132526A1 CLAIM 2 . The method of claim 1 , wherein the anisotropic etching is performed using a dry etch (multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers, second etch) ing process and the isotropic etching is performed using a wet etch (multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers, second etch) ing process . US20030132526A1 CLAIM 5 . The method of claim 1 , wherein the lower dielectric layer is formed by a process in which a flow rate (multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers, second etch) of O 3 gas decreases and a flow rate of O 2 gas increases . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch (wet etch, dry etch, low rate) stop layer (wet etch, dry etch, low rate) protects lower layers during an etching process (etching process) . |
US20030132526A1 CLAIM 2 . The method of claim 1 , wherein the anisotropic etching is performed using a dry etching process (etching process) and the isotropic etching is performed using a wet etching process . US20030132526A1 CLAIM 5 . The method of claim 1 , wherein the lower dielectric layer is formed by a process in which a flow rate (multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers, second etch) of O 3 gas decreases and a flow rate of O 2 gas increases . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch (wet etch, dry etch, low rate) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (wet etch, dry etch, low rate) stop layer (wet etch, dry etch, low rate) is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US20030132526A1 CLAIM 2 . The method of claim 1 , wherein the anisotropic etching is performed using a dry etch (multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers, second etch) ing process and the isotropic etching is performed using a wet etch (multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers, second etch) ing process . US20030132526A1 CLAIM 5 . The method of claim 1 , wherein the lower dielectric layer is formed by a process in which a flow rate (multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers, second etch) of O 3 gas decreases and a flow rate of O 2 gas increases . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch (wet etch, dry etch, low rate) stop insulation layer comprising a first etch (wet etch, dry etch, low rate) stop layer and a second etch (wet etch, dry etch, low rate) stop layer (wet etch, dry etch, low rate) wherein said first etch stop layer and said second etch stop layers (wet etch, dry etch, low rate) have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US20030132526A1 CLAIM 2 . The method of claim 1 , wherein the anisotropic etching is performed using a dry etch (multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers, second etch) ing process and the isotropic etching is performed using a wet etch (multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers, second etch) ing process . US20030132526A1 CLAIM 5 . The method of claim 1 , wherein the lower dielectric layer is formed by a process in which a flow rate (multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers, second etch) of O 3 gas decreases and a flow rate of O 2 gas increases . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch (wet etch, dry etch, low rate) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (wet etch, dry etch, low rate) stop layer (wet etch, dry etch, low rate) is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US20030132526A1 CLAIM 2 . The method of claim 1 , wherein the anisotropic etching is performed using a dry etch (multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers, second etch) ing process and the isotropic etching is performed using a wet etch (multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers, second etch) ing process . US20030132526A1 CLAIM 5 . The method of claim 1 , wherein the lower dielectric layer is formed by a process in which a flow rate (multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers, second etch) of O 3 gas decreases and a flow rate of O 2 gas increases . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US20020187598A1 Filed: 2002-07-30 Issued: 2002-12-12 DRAM device and method of manufacturing the same (Original Assignee) Samsung Electronics Co Ltd (Current Assignee) Samsung Electronics Co Ltd Byung-Jun Park, Kyu-Hyun Lee |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (said plate) of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (bit line contacts, contact plug) layer over said first etch stop layer ; a second etch (sacrificial layer, etch stop layer) stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US20020187598A1 CLAIM 1 . A method of manufacturing DRAM device comprising : forming MOS transistors on a substrate ; forming at least bit line contact holes by depositing an interlayer insulating layer on the whole surface of said substrate on which said MOS transistors are formed and patterning the interlayer insulating layer ; forming a conductive layer for forming bit lines , a subsidiary silicon oxide layer , and a subsidiary silicon nitride layer over the whole surface of said substrate on which said bit line contacts (interlevel dielectric) are formed ; forming a bit line pattern including enlarged width portions at a portion of a peripheral/core area by patterning said conductive layer , said subsidiary silicon oxide layer , and said subsidiary silicon nitride layer ; forming a bit line interlayer insulating layer of silicon oxide material (second sub interlevel dielectric layer) over the whole surface of said substrate over which said bit line pattern is formed ; planarizing said bit line interlayer insulating layer to expose the upper surface of said subsidiary silicon nitride layer of said bit line pattern ; forming enlarged grooves exposing portions of said conductive layer of said bit line pattern forming bit lines by wet-etching said subsidiary silicon nitride layer of said bit line pattern to form first grooves and then etching isotropically said subsidiary silicon oxide layer and said bit line interlayer insulating layer around said first grooves ; forming a silicon nitride layer over the whole surface of said substrate over which said enlarged grooves are formed ; forming a silicon nitride pattern by etching anisotropically the whole surface of said silicon nitride layer to expose said bit line interlayer insulating layer , said silicon nitride pattern having silicon nitride spacers formed on side walls of said enlarged grooves positioned on said conductive layer of said bit line pattern forming said bit lines at said enlarged width portions of said bit line pattern ; forming storage node contacts , storage nodes , a dielectric layer , and plate electrodes at a cell area ; forming a wiring interlayer insulating layer on the whole surface of said substrate over which said plate (metal layer coupling area, second interlevel dielectric layer) electrodes are formed ; forming metal contact holes exposing at least said conductive layer of said bit line pattern forming said bit lines at said enlarged width portions of said bit line pattern ; and forming plugs filling said metal contact holes by depositing a conductive layer over the whole surface of said substrate over which said metal contact holes are formed . US20020187598A1 CLAIM 2 . The method of manufacturing DRAM device according to claim 1 , wherein forming storage node contacts , storage nodes , a dielectric layer , and plate electrodes at said cell area comprises : forming storage node contact holes by patterning said bit line interlayer insulating layer at the whole surface of said substrate over which said nitride pattern is formed ; forming storage node contact plug (interlevel dielectric) s by depositing a polysilicon layer over the whole surface of said substrate over which said storage node contact holes are formed ; forming storage node holes exposing said storage node contact plugs by depositing a molding oxide layer and patterning it ; forming conformally a polysilicon layer over the whole surface of said substrate over which said storage node holes are formed ; filling residual spaces of said storage node holes with a sacrificial layer (second etch) ; forming cylinder shaped storage nodes by planarizing the whole surface of said substrate over which said sacrificial layer is formed , to remove a portion of said conformal polysilicon layer formed on the upper surface of said molding layer and to divide said storage node ; removing remnants of said sacrificial layer and said molding layer to leave only said storage nodes ; forming conformally a dielectric layer over the whole surface of said substrate over which said storage nodes are left ; and forming plate electrodes by forming a polysilicon layer on said dielectric layer and patterning the polysilicon layer . US20020187598A1 CLAIM 5 . The method of manufacturing a DRAM device according to claim 1 , wherein forming at least bit line contact holes comprises : forming a first interlayer insulating layer on the whole surface of said substrate on which said MOS transistors are formed , patterning said first interlayer insulating layer to expose a portion of an active region in said cell area , forming a polysilicon layer on the whole surface of said substrate on which said portion of said active region is exposed , forming pads for storage node contacts and bit line contacts in said cell area by planarizing said polysilicon layer and said first interlayer insulating layer up to the upper surface of said transistors to divide said pads , forming bit line contact holes exposing a portion of said pads in said cell area and metal contact pad holes exposing a portion of said substrate in said peripheral/core area by depositing a second interlayer insulating layer and an etch stop layer (second etch) of silicon nitride material over the whole surface of said substrate on which said pads are to be formed and patterning them , forming metal contact pads and bit line contact plugs by filling , respectively , said metal contact pad holes and said bit line contact holes , and patterning said etch stop layer to leave only a portion thereof around said metal contact pad ; and wherein when forming metal contact holes , metal contact holes exposing said metal contact pads are formed . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer protects removal of a substrate material by an etch process (silicon oxide layer) . |
US20020187598A1 CLAIM 1 . A method of manufacturing DRAM device comprising : forming MOS transistors on a substrate ; forming at least bit line contact holes by depositing an interlayer insulating layer on the whole surface of said substrate on which said MOS transistors are formed and patterning the interlayer insulating layer ; forming a conductive layer for forming bit lines , a subsidiary silicon oxide layer (etch process) , and a subsidiary silicon nitride layer over the whole surface of said substrate on which said bit line contacts are formed ; forming a bit line pattern including enlarged width portions at a portion of a peripheral/core area by patterning said conductive layer , said subsidiary silicon oxide layer , and said subsidiary silicon nitride layer ; forming a bit line interlayer insulating layer of silicon oxide material over the whole surface of said substrate over which said bit line pattern is formed ; planarizing said bit line interlayer insulating layer to expose the upper surface of said subsidiary silicon nitride layer of said bit line pattern ; forming enlarged grooves exposing portions of said conductive layer of said bit line pattern forming bit lines by wet-etching said subsidiary silicon nitride layer of said bit line pattern to form first grooves and then etching isotropically said subsidiary silicon oxide layer and said bit line interlayer insulating layer around said first grooves ; forming a silicon nitride layer over the whole surface of said substrate over which said enlarged grooves are formed ; forming a silicon nitride pattern by etching anisotropically the whole surface of said silicon nitride layer to expose said bit line interlayer insulating layer , said silicon nitride pattern having silicon nitride spacers formed on side walls of said enlarged grooves positioned on said conductive layer of said bit line pattern forming said bit lines at said enlarged width portions of said bit line pattern ; forming storage node contacts , storage nodes , a dielectric layer , and plate electrodes at a cell area ; forming a wiring interlayer insulating layer on the whole surface of said substrate over which said plate electrodes are formed ; forming metal contact holes exposing at least said conductive layer of said bit line pattern forming said bit lines at said enlarged width portions of said bit line pattern ; and forming plugs filling said metal contact holes by depositing a conductive layer over the whole surface of said substrate over which said metal contact holes are formed . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (bit line contacts, contact plug) layer insulates said contact region . |
US20020187598A1 CLAIM 1 . A method of manufacturing DRAM device comprising : forming MOS transistors on a substrate ; forming at least bit line contact holes by depositing an interlayer insulating layer on the whole surface of said substrate on which said MOS transistors are formed and patterning the interlayer insulating layer ; forming a conductive layer for forming bit lines , a subsidiary silicon oxide layer , and a subsidiary silicon nitride layer over the whole surface of said substrate on which said bit line contacts (interlevel dielectric) are formed ; forming a bit line pattern including enlarged width portions at a portion of a peripheral/core area by patterning said conductive layer , said subsidiary silicon oxide layer , and said subsidiary silicon nitride layer ; forming a bit line interlayer insulating layer of silicon oxide material over the whole surface of said substrate over which said bit line pattern is formed ; planarizing said bit line interlayer insulating layer to expose the upper surface of said subsidiary silicon nitride layer of said bit line pattern ; forming enlarged grooves exposing portions of said conductive layer of said bit line pattern forming bit lines by wet-etching said subsidiary silicon nitride layer of said bit line pattern to form first grooves and then etching isotropically said subsidiary silicon oxide layer and said bit line interlayer insulating layer around said first grooves ; forming a silicon nitride layer over the whole surface of said substrate over which said enlarged grooves are formed ; forming a silicon nitride pattern by etching anisotropically the whole surface of said silicon nitride layer to expose said bit line interlayer insulating layer , said silicon nitride pattern having silicon nitride spacers formed on side walls of said enlarged grooves positioned on said conductive layer of said bit line pattern forming said bit lines at said enlarged width portions of said bit line pattern ; forming storage node contacts , storage nodes , a dielectric layer , and plate electrodes at a cell area ; forming a wiring interlayer insulating layer on the whole surface of said substrate over which said plate electrodes are formed ; forming metal contact holes exposing at least said conductive layer of said bit line pattern forming said bit lines at said enlarged width portions of said bit line pattern ; and forming plugs filling said metal contact holes by depositing a conductive layer over the whole surface of said substrate over which said metal contact holes are formed . US20020187598A1 CLAIM 2 . The method of manufacturing DRAM device according to claim 1 , wherein forming storage node contacts , storage nodes , a dielectric layer , and plate electrodes at said cell area comprises : forming storage node contact holes by patterning said bit line interlayer insulating layer at the whole surface of said substrate over which said nitride pattern is formed ; forming storage node contact plug (interlevel dielectric) s by depositing a polysilicon layer over the whole surface of said substrate over which said storage node contact holes are formed ; forming storage node holes exposing said storage node contact plugs by depositing a molding oxide layer and patterning it ; forming conformally a polysilicon layer over the whole surface of said substrate over which said storage node holes are formed ; filling residual spaces of said storage node holes with a sacrificial layer ; forming cylinder shaped storage nodes by planarizing the whole surface of said substrate over which said sacrificial layer is formed , to remove a portion of said conformal polysilicon layer formed on the upper surface of said molding layer and to divide said storage node ; removing remnants of said sacrificial layer and said molding layer to leave only said storage nodes ; forming conformally a dielectric layer over the whole surface of said substrate over which said storage nodes are left ; and forming plate electrodes by forming a polysilicon layer on said dielectric layer and patterning the polysilicon layer . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch (sacrificial layer, etch stop layer) stop layer protects lower layers during an etching process . |
US20020187598A1 CLAIM 2 . The method of manufacturing DRAM device according to claim 1 , wherein forming storage node contacts , storage nodes , a dielectric layer , and plate electrodes at said cell area comprises : forming storage node contact holes by patterning said bit line interlayer insulating layer at the whole surface of said substrate over which said nitride pattern is formed ; forming storage node contact plugs by depositing a polysilicon layer over the whole surface of said substrate over which said storage node contact holes are formed ; forming storage node holes exposing said storage node contact plugs by depositing a molding oxide layer and patterning it ; forming conformally a polysilicon layer over the whole surface of said substrate over which said storage node holes are formed ; filling residual spaces of said storage node holes with a sacrificial layer (second etch) ; forming cylinder shaped storage nodes by planarizing the whole surface of said substrate over which said sacrificial layer is formed , to remove a portion of said conformal polysilicon layer formed on the upper surface of said molding layer and to divide said storage node ; removing remnants of said sacrificial layer and said molding layer to leave only said storage nodes ; forming conformally a dielectric layer over the whole surface of said substrate over which said storage nodes are left ; and forming plate electrodes by forming a polysilicon layer on said dielectric layer and patterning the polysilicon layer . US20020187598A1 CLAIM 5 . The method of manufacturing a DRAM device according to claim 1 , wherein forming at least bit line contact holes comprises : forming a first interlayer insulating layer on the whole surface of said substrate on which said MOS transistors are formed , patterning said first interlayer insulating layer to expose a portion of an active region in said cell area , forming a polysilicon layer on the whole surface of said substrate on which said portion of said active region is exposed , forming pads for storage node contacts and bit line contacts in said cell area by planarizing said polysilicon layer and said first interlayer insulating layer up to the upper surface of said transistors to divide said pads , forming bit line contact holes exposing a portion of said pads in said cell area and metal contact pad holes exposing a portion of said substrate in said peripheral/core area by depositing a second interlayer insulating layer and an etch stop layer (second etch) of silicon nitride material over the whole surface of said substrate on which said pads are to be formed and patterning them , forming metal contact pads and bit line contact plugs by filling , respectively , said metal contact pad holes and said bit line contact holes , and patterning said etch stop layer to leave only a portion thereof around said metal contact pad ; and wherein when forming metal contact holes , metal contact holes exposing said metal contact pads are formed . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (bit line contacts, contact plug) layer insulates said contact region . |
US20020187598A1 CLAIM 1 . A method of manufacturing DRAM device comprising : forming MOS transistors on a substrate ; forming at least bit line contact holes by depositing an interlayer insulating layer on the whole surface of said substrate on which said MOS transistors are formed and patterning the interlayer insulating layer ; forming a conductive layer for forming bit lines , a subsidiary silicon oxide layer , and a subsidiary silicon nitride layer over the whole surface of said substrate on which said bit line contacts (interlevel dielectric) are formed ; forming a bit line pattern including enlarged width portions at a portion of a peripheral/core area by patterning said conductive layer , said subsidiary silicon oxide layer , and said subsidiary silicon nitride layer ; forming a bit line interlayer insulating layer of silicon oxide material (second sub interlevel dielectric layer) over the whole surface of said substrate over which said bit line pattern is formed ; planarizing said bit line interlayer insulating layer to expose the upper surface of said subsidiary silicon nitride layer of said bit line pattern ; forming enlarged grooves exposing portions of said conductive layer of said bit line pattern forming bit lines by wet-etching said subsidiary silicon nitride layer of said bit line pattern to form first grooves and then etching isotropically said subsidiary silicon oxide layer and said bit line interlayer insulating layer around said first grooves ; forming a silicon nitride layer over the whole surface of said substrate over which said enlarged grooves are formed ; forming a silicon nitride pattern by etching anisotropically the whole surface of said silicon nitride layer to expose said bit line interlayer insulating layer , said silicon nitride pattern having silicon nitride spacers formed on side walls of said enlarged grooves positioned on said conductive layer of said bit line pattern forming said bit lines at said enlarged width portions of said bit line pattern ; forming storage node contacts , storage nodes , a dielectric layer , and plate electrodes at a cell area ; forming a wiring interlayer insulating layer on the whole surface of said substrate over which said plate electrodes are formed ; forming metal contact holes exposing at least said conductive layer of said bit line pattern forming said bit lines at said enlarged width portions of said bit line pattern ; and forming plugs filling said metal contact holes by depositing a conductive layer over the whole surface of said substrate over which said metal contact holes are formed . US20020187598A1 CLAIM 2 . The method of manufacturing DRAM device according to claim 1 , wherein forming storage node contacts , storage nodes , a dielectric layer , and plate electrodes at said cell area comprises : forming storage node contact holes by patterning said bit line interlayer insulating layer at the whole surface of said substrate over which said nitride pattern is formed ; forming storage node contact plug (interlevel dielectric) s by depositing a polysilicon layer over the whole surface of said substrate over which said storage node contact holes are formed ; forming storage node holes exposing said storage node contact plugs by depositing a molding oxide layer and patterning it ; forming conformally a polysilicon layer over the whole surface of said substrate over which said storage node holes are formed ; filling residual spaces of said storage node holes with a sacrificial layer ; forming cylinder shaped storage nodes by planarizing the whole surface of said substrate over which said sacrificial layer is formed , to remove a portion of said conformal polysilicon layer formed on the upper surface of said molding layer and to divide said storage node ; removing remnants of said sacrificial layer and said molding layer to leave only said storage nodes ; forming conformally a dielectric layer over the whole surface of said substrate over which said storage nodes are left ; and forming plate electrodes by forming a polysilicon layer on said dielectric layer and patterning the polysilicon layer . |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area of said contact region permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area (said plate) of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
US20020187598A1 CLAIM 1 . A method of manufacturing DRAM device comprising : forming MOS transistors on a substrate ; forming at least bit line contact holes by depositing an interlayer insulating layer on the whole surface of said substrate on which said MOS transistors are formed and patterning the interlayer insulating layer ; forming a conductive layer for forming bit lines , a subsidiary silicon oxide layer , and a subsidiary silicon nitride layer over the whole surface of said substrate on which said bit line contacts are formed ; forming a bit line pattern including enlarged width portions at a portion of a peripheral/core area by patterning said conductive layer , said subsidiary silicon oxide layer , and said subsidiary silicon nitride layer ; forming a bit line interlayer insulating layer of silicon oxide material over the whole surface of said substrate over which said bit line pattern is formed ; planarizing said bit line interlayer insulating layer to expose the upper surface of said subsidiary silicon nitride layer of said bit line pattern ; forming enlarged grooves exposing portions of said conductive layer of said bit line pattern forming bit lines by wet-etching said subsidiary silicon nitride layer of said bit line pattern to form first grooves and then etching isotropically said subsidiary silicon oxide layer and said bit line interlayer insulating layer around said first grooves ; forming a silicon nitride layer over the whole surface of said substrate over which said enlarged grooves are formed ; forming a silicon nitride pattern by etching anisotropically the whole surface of said silicon nitride layer to expose said bit line interlayer insulating layer , said silicon nitride pattern having silicon nitride spacers formed on side walls of said enlarged grooves positioned on said conductive layer of said bit line pattern forming said bit lines at said enlarged width portions of said bit line pattern ; forming storage node contacts , storage nodes , a dielectric layer , and plate electrodes at a cell area ; forming a wiring interlayer insulating layer on the whole surface of said substrate over which said plate (metal layer coupling area, second interlevel dielectric layer) electrodes are formed ; forming metal contact holes exposing at least said conductive layer of said bit line pattern forming said bit lines at said enlarged width portions of said bit line pattern ; and forming plugs filling said metal contact holes by depositing a conductive layer over the whole surface of said substrate over which said metal contact holes are formed . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (bit line contacts, contact plug) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (sacrificial layer, etch stop layer) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US20020187598A1 CLAIM 1 . A method of manufacturing DRAM device comprising : forming MOS transistors on a substrate ; forming at least bit line contact holes by depositing an interlayer insulating layer on the whole surface of said substrate on which said MOS transistors are formed and patterning the interlayer insulating layer ; forming a conductive layer for forming bit lines , a subsidiary silicon oxide layer , and a subsidiary silicon nitride layer over the whole surface of said substrate on which said bit line contacts (interlevel dielectric) are formed ; forming a bit line pattern including enlarged width portions at a portion of a peripheral/core area by patterning said conductive layer , said subsidiary silicon oxide layer , and said subsidiary silicon nitride layer ; forming a bit line interlayer insulating layer of silicon oxide material (second sub interlevel dielectric layer) over the whole surface of said substrate over which said bit line pattern is formed ; planarizing said bit line interlayer insulating layer to expose the upper surface of said subsidiary silicon nitride layer of said bit line pattern ; forming enlarged grooves exposing portions of said conductive layer of said bit line pattern forming bit lines by wet-etching said subsidiary silicon nitride layer of said bit line pattern to form first grooves and then etching isotropically said subsidiary silicon oxide layer and said bit line interlayer insulating layer around said first grooves ; forming a silicon nitride layer over the whole surface of said substrate over which said enlarged grooves are formed ; forming a silicon nitride pattern by etching anisotropically the whole surface of said silicon nitride layer to expose said bit line interlayer insulating layer , said silicon nitride pattern having silicon nitride spacers formed on side walls of said enlarged grooves positioned on said conductive layer of said bit line pattern forming said bit lines at said enlarged width portions of said bit line pattern ; forming storage node contacts , storage nodes , a dielectric layer , and plate electrodes at a cell area ; forming a wiring interlayer insulating layer on the whole surface of said substrate over which said plate electrodes are formed ; forming metal contact holes exposing at least said conductive layer of said bit line pattern forming said bit lines at said enlarged width portions of said bit line pattern ; and forming plugs filling said metal contact holes by depositing a conductive layer over the whole surface of said substrate over which said metal contact holes are formed . US20020187598A1 CLAIM 2 . The method of manufacturing DRAM device according to claim 1 , wherein forming storage node contacts , storage nodes , a dielectric layer , and plate electrodes at said cell area comprises : forming storage node contact holes by patterning said bit line interlayer insulating layer at the whole surface of said substrate over which said nitride pattern is formed ; forming storage node contact plug (interlevel dielectric) s by depositing a polysilicon layer over the whole surface of said substrate over which said storage node contact holes are formed ; forming storage node holes exposing said storage node contact plugs by depositing a molding oxide layer and patterning it ; forming conformally a polysilicon layer over the whole surface of said substrate over which said storage node holes are formed ; filling residual spaces of said storage node holes with a sacrificial layer (second etch) ; forming cylinder shaped storage nodes by planarizing the whole surface of said substrate over which said sacrificial layer is formed , to remove a portion of said conformal polysilicon layer formed on the upper surface of said molding layer and to divide said storage node ; removing remnants of said sacrificial layer and said molding layer to leave only said storage nodes ; forming conformally a dielectric layer over the whole surface of said substrate over which said storage nodes are left ; and forming plate electrodes by forming a polysilicon layer on said dielectric layer and patterning the polysilicon layer . US20020187598A1 CLAIM 5 . The method of manufacturing a DRAM device according to claim 1 , wherein forming at least bit line contact holes comprises : forming a first interlayer insulating layer on the whole surface of said substrate on which said MOS transistors are formed , patterning said first interlayer insulating layer to expose a portion of an active region in said cell area , forming a polysilicon layer on the whole surface of said substrate on which said portion of said active region is exposed , forming pads for storage node contacts and bit line contacts in said cell area by planarizing said polysilicon layer and said first interlayer insulating layer up to the upper surface of said transistors to divide said pads , forming bit line contact holes exposing a portion of said pads in said cell area and metal contact pad holes exposing a portion of said substrate in said peripheral/core area by depositing a second interlayer insulating layer and an etch stop layer (second etch) of silicon nitride material over the whole surface of said substrate on which said pads are to be formed and patterning them , forming metal contact pads and bit line contact plugs by filling , respectively , said metal contact pad holes and said bit line contact holes , and patterning said etch stop layer to leave only a portion thereof around said metal contact pad ; and wherein when forming metal contact holes , metal contact holes exposing said metal contact pads are formed . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric (bit line contacts, contact plug) layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US20020187598A1 CLAIM 1 . A method of manufacturing DRAM device comprising : forming MOS transistors on a substrate ; forming at least bit line contact holes by depositing an interlayer insulating layer on the whole surface of said substrate on which said MOS transistors are formed and patterning the interlayer insulating layer ; forming a conductive layer for forming bit lines , a subsidiary silicon oxide layer , and a subsidiary silicon nitride layer over the whole surface of said substrate on which said bit line contacts (interlevel dielectric) are formed ; forming a bit line pattern including enlarged width portions at a portion of a peripheral/core area by patterning said conductive layer , said subsidiary silicon oxide layer , and said subsidiary silicon nitride layer ; forming a bit line interlayer insulating layer of silicon oxide material (second sub interlevel dielectric layer) over the whole surface of said substrate over which said bit line pattern is formed ; planarizing said bit line interlayer insulating layer to expose the upper surface of said subsidiary silicon nitride layer of said bit line pattern ; forming enlarged grooves exposing portions of said conductive layer of said bit line pattern forming bit lines by wet-etching said subsidiary silicon nitride layer of said bit line pattern to form first grooves and then etching isotropically said subsidiary silicon oxide layer and said bit line interlayer insulating layer around said first grooves ; forming a silicon nitride layer over the whole surface of said substrate over which said enlarged grooves are formed ; forming a silicon nitride pattern by etching anisotropically the whole surface of said silicon nitride layer to expose said bit line interlayer insulating layer , said silicon nitride pattern having silicon nitride spacers formed on side walls of said enlarged grooves positioned on said conductive layer of said bit line pattern forming said bit lines at said enlarged width portions of said bit line pattern ; forming storage node contacts , storage nodes , a dielectric layer , and plate electrodes at a cell area ; forming a wiring interlayer insulating layer on the whole surface of said substrate over which said plate electrodes are formed ; forming metal contact holes exposing at least said conductive layer of said bit line pattern forming said bit lines at said enlarged width portions of said bit line pattern ; and forming plugs filling said metal contact holes by depositing a conductive layer over the whole surface of said substrate over which said metal contact holes are formed . US20020187598A1 CLAIM 2 . The method of manufacturing DRAM device according to claim 1 , wherein forming storage node contacts , storage nodes , a dielectric layer , and plate electrodes at said cell area comprises : forming storage node contact holes by patterning said bit line interlayer insulating layer at the whole surface of said substrate over which said nitride pattern is formed ; forming storage node contact plug (interlevel dielectric) s by depositing a polysilicon layer over the whole surface of said substrate over which said storage node contact holes are formed ; forming storage node holes exposing said storage node contact plugs by depositing a molding oxide layer and patterning it ; forming conformally a polysilicon layer over the whole surface of said substrate over which said storage node holes are formed ; filling residual spaces of said storage node holes with a sacrificial layer ; forming cylinder shaped storage nodes by planarizing the whole surface of said substrate over which said sacrificial layer is formed , to remove a portion of said conformal polysilicon layer formed on the upper surface of said molding layer and to divide said storage node ; removing remnants of said sacrificial layer and said molding layer to leave only said storage nodes ; forming conformally a dielectric layer over the whole surface of said substrate over which said storage nodes are left ; and forming plate electrodes by forming a polysilicon layer on said dielectric layer and patterning the polysilicon layer . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US20020187598A1 CLAIM 1 . A method of manufacturing DRAM device comprising : forming MOS transistors on a substrate ; forming at least bit line contact holes by depositing an interlayer insulating layer on the whole surface of said substrate on which said MOS transistors are formed and patterning the interlayer insulating layer ; forming a conductive layer for forming bit lines , a subsidiary silicon oxide layer , and a subsidiary silicon nitride layer over the whole surface of said substrate on which said bit line contacts are formed ; forming a bit line pattern including enlarged width portions at a portion of a peripheral/core area by patterning said conductive layer , said subsidiary silicon oxide layer , and said subsidiary silicon nitride layer ; forming a bit line interlayer insulating layer of silicon oxide material over the whole surface of said substrate over which said bit line pattern is formed ; planarizing said bit line interlayer insulating layer to expose the upper surface of said subsidiary silicon nitride layer of said bit line pattern ; forming enlarged grooves exposing portions of said conductive layer of said bit line pattern forming bit lines by wet-etching said subsidiary silicon nitride layer of said bit line pattern to form first grooves and then etching isotropically said subsidiary silicon oxide layer and said bit line interlayer insulating layer around said first grooves ; forming a silicon nitride layer over the whole surface of said substrate over which said enlarged grooves are formed ; forming a silicon nitride pattern by etching anisotropically the whole surface of said silicon nitride layer to expose said bit line interlayer insulating layer , said silicon nitride pattern having silicon nitride spacers formed on side walls of said enlarged grooves positioned on said conductive layer of said bit line pattern forming said bit lines at said enlarged width portions of said bit line pattern ; forming storage node contacts , storage nodes , a dielectric layer , and plate electrodes at a cell area ; forming a wiring interlayer insulating layer on the whole surface of said substrate over which said plate electrodes are formed ; forming metal contact holes exposing at least said conductive layer of said bit line pattern forming said bit lines at said enlarged width portions of said bit line pattern ; and forming (anti reflective coating) plugs filling said metal contact holes by depositing a conductive layer over the whole surface of said substrate over which said metal contact holes are formed . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch (sacrificial layer, etch stop layer) stop layer wherein said first etch stop layer and said second etch stop layers (silicon nitride layer) have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (bit line contacts, contact plug) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (said plate) of said contact region . |
US20020187598A1 CLAIM 1 . A method of manufacturing DRAM device comprising : forming MOS transistors on a substrate ; forming at least bit line contact holes by depositing an interlayer insulating layer on the whole surface of said substrate on which said MOS transistors are formed and patterning the interlayer insulating layer ; forming a conductive layer for forming bit lines , a subsidiary silicon oxide layer , and a subsidiary silicon nitride layer (second etch stop layers) over the whole surface of said substrate on which said bit line contacts (interlevel dielectric) are formed ; forming a bit line pattern including enlarged width portions at a portion of a peripheral/core area by patterning said conductive layer , said subsidiary silicon oxide layer , and said subsidiary silicon nitride layer ; forming a bit line interlayer insulating layer of silicon oxide material (second sub interlevel dielectric layer) over the whole surface of said substrate over which said bit line pattern is formed ; planarizing said bit line interlayer insulating layer to expose the upper surface of said subsidiary silicon nitride layer of said bit line pattern ; forming enlarged grooves exposing portions of said conductive layer of said bit line pattern forming bit lines by wet-etching said subsidiary silicon nitride layer of said bit line pattern to form first grooves and then etching isotropically said subsidiary silicon oxide layer and said bit line interlayer insulating layer around said first grooves ; forming a silicon nitride layer over the whole surface of said substrate over which said enlarged grooves are formed ; forming a silicon nitride pattern by etching anisotropically the whole surface of said silicon nitride layer to expose said bit line interlayer insulating layer , said silicon nitride pattern having silicon nitride spacers formed on side walls of said enlarged grooves positioned on said conductive layer of said bit line pattern forming said bit lines at said enlarged width portions of said bit line pattern ; forming storage node contacts , storage nodes , a dielectric layer , and plate electrodes at a cell area ; forming a wiring interlayer insulating layer on the whole surface of said substrate over which said plate (metal layer coupling area, second interlevel dielectric layer) electrodes are formed ; forming metal contact holes exposing at least said conductive layer of said bit line pattern forming said bit lines at said enlarged width portions of said bit line pattern ; and forming plugs filling said metal contact holes by depositing a conductive layer over the whole surface of said substrate over which said metal contact holes are formed . US20020187598A1 CLAIM 2 . The method of manufacturing DRAM device according to claim 1 , wherein forming storage node contacts , storage nodes , a dielectric layer , and plate electrodes at said cell area comprises : forming storage node contact holes by patterning said bit line interlayer insulating layer at the whole surface of said substrate over which said nitride pattern is formed ; forming storage node contact plug (interlevel dielectric) s by depositing a polysilicon layer over the whole surface of said substrate over which said storage node contact holes are formed ; forming storage node holes exposing said storage node contact plugs by depositing a molding oxide layer and patterning it ; forming conformally a polysilicon layer over the whole surface of said substrate over which said storage node holes are formed ; filling residual spaces of said storage node holes with a sacrificial layer (second etch) ; forming cylinder shaped storage nodes by planarizing the whole surface of said substrate over which said sacrificial layer is formed , to remove a portion of said conformal polysilicon layer formed on the upper surface of said molding layer and to divide said storage node ; removing remnants of said sacrificial layer and said molding layer to leave only said storage nodes ; forming conformally a dielectric layer over the whole surface of said substrate over which said storage nodes are left ; and forming plate electrodes by forming a polysilicon layer on said dielectric layer and patterning the polysilicon layer . US20020187598A1 CLAIM 5 . The method of manufacturing a DRAM device according to claim 1 , wherein forming at least bit line contact holes comprises : forming a first interlayer insulating layer on the whole surface of said substrate on which said MOS transistors are formed , patterning said first interlayer insulating layer to expose a portion of an active region in said cell area , forming a polysilicon layer on the whole surface of said substrate on which said portion of said active region is exposed , forming pads for storage node contacts and bit line contacts in said cell area by planarizing said polysilicon layer and said first interlayer insulating layer up to the upper surface of said transistors to divide said pads , forming bit line contact holes exposing a portion of said pads in said cell area and metal contact pad holes exposing a portion of said substrate in said peripheral/core area by depositing a second interlayer insulating layer and an etch stop layer (second etch) of silicon nitride material over the whole surface of said substrate on which said pads are to be formed and patterning them , forming metal contact pads and bit line contact plugs by filling , respectively , said metal contact pad holes and said bit line contact holes , and patterning said etch stop layer to leave only a portion thereof around said metal contact pad ; and wherein when forming metal contact holes , metal contact holes exposing said metal contact pads are formed . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (bit line contacts, contact plug) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (sacrificial layer, etch stop layer) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US20020187598A1 CLAIM 1 . A method of manufacturing DRAM device comprising : forming MOS transistors on a substrate ; forming at least bit line contact holes by depositing an interlayer insulating layer on the whole surface of said substrate on which said MOS transistors are formed and patterning the interlayer insulating layer ; forming a conductive layer for forming bit lines , a subsidiary silicon oxide layer , and a subsidiary silicon nitride layer over the whole surface of said substrate on which said bit line contacts (interlevel dielectric) are formed ; forming a bit line pattern including enlarged width portions at a portion of a peripheral/core area by patterning said conductive layer , said subsidiary silicon oxide layer , and said subsidiary silicon nitride layer ; forming a bit line interlayer insulating layer of silicon oxide material (second sub interlevel dielectric layer) over the whole surface of said substrate over which said bit line pattern is formed ; planarizing said bit line interlayer insulating layer to expose the upper surface of said subsidiary silicon nitride layer of said bit line pattern ; forming enlarged grooves exposing portions of said conductive layer of said bit line pattern forming bit lines by wet-etching said subsidiary silicon nitride layer of said bit line pattern to form first grooves and then etching isotropically said subsidiary silicon oxide layer and said bit line interlayer insulating layer around said first grooves ; forming a silicon nitride layer over the whole surface of said substrate over which said enlarged grooves are formed ; forming a silicon nitride pattern by etching anisotropically the whole surface of said silicon nitride layer to expose said bit line interlayer insulating layer , said silicon nitride pattern having silicon nitride spacers formed on side walls of said enlarged grooves positioned on said conductive layer of said bit line pattern forming said bit lines at said enlarged width portions of said bit line pattern ; forming storage node contacts , storage nodes , a dielectric layer , and plate electrodes at a cell area ; forming a wiring interlayer insulating layer on the whole surface of said substrate over which said plate electrodes are formed ; forming metal contact holes exposing at least said conductive layer of said bit line pattern forming said bit lines at said enlarged width portions of said bit line pattern ; and forming plugs filling said metal contact holes by depositing a conductive layer over the whole surface of said substrate over which said metal contact holes are formed . US20020187598A1 CLAIM 2 . The method of manufacturing DRAM device according to claim 1 , wherein forming storage node contacts , storage nodes , a dielectric layer , and plate electrodes at said cell area comprises : forming storage node contact holes by patterning said bit line interlayer insulating layer at the whole surface of said substrate over which said nitride pattern is formed ; forming storage node contact plug (interlevel dielectric) s by depositing a polysilicon layer over the whole surface of said substrate over which said storage node contact holes are formed ; forming storage node holes exposing said storage node contact plugs by depositing a molding oxide layer and patterning it ; forming conformally a polysilicon layer over the whole surface of said substrate over which said storage node holes are formed ; filling residual spaces of said storage node holes with a sacrificial layer (second etch) ; forming cylinder shaped storage nodes by planarizing the whole surface of said substrate over which said sacrificial layer is formed , to remove a portion of said conformal polysilicon layer formed on the upper surface of said molding layer and to divide said storage node ; removing remnants of said sacrificial layer and said molding layer to leave only said storage nodes ; forming conformally a dielectric layer over the whole surface of said substrate over which said storage nodes are left ; and forming plate electrodes by forming a polysilicon layer on said dielectric layer and patterning the polysilicon layer . US20020187598A1 CLAIM 5 . The method of manufacturing a DRAM device according to claim 1 , wherein forming at least bit line contact holes comprises : forming a first interlayer insulating layer on the whole surface of said substrate on which said MOS transistors are formed , patterning said first interlayer insulating layer to expose a portion of an active region in said cell area , forming a polysilicon layer on the whole surface of said substrate on which said portion of said active region is exposed , forming pads for storage node contacts and bit line contacts in said cell area by planarizing said polysilicon layer and said first interlayer insulating layer up to the upper surface of said transistors to divide said pads , forming bit line contact holes exposing a portion of said pads in said cell area and metal contact pad holes exposing a portion of said substrate in said peripheral/core area by depositing a second interlayer insulating layer and an etch stop layer (second etch) of silicon nitride material over the whole surface of said substrate on which said pads are to be formed and patterning them , forming metal contact pads and bit line contact plugs by filling , respectively , said metal contact pad holes and said bit line contact holes , and patterning said etch stop layer to leave only a portion thereof around said metal contact pad ; and wherein when forming metal contact holes , metal contact holes exposing said metal contact pads are formed . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US20020187598A1 CLAIM 1 . A method of manufacturing DRAM device comprising : forming MOS transistors on a substrate ; forming at least bit line contact holes by depositing an interlayer insulating layer on the whole surface of said substrate on which said MOS transistors are formed and patterning the interlayer insulating layer ; forming a conductive layer for forming bit lines , a subsidiary silicon oxide layer , and a subsidiary silicon nitride layer over the whole surface of said substrate on which said bit line contacts are formed ; forming a bit line pattern including enlarged width portions at a portion of a peripheral/core area by patterning said conductive layer , said subsidiary silicon oxide layer , and said subsidiary silicon nitride layer ; forming a bit line interlayer insulating layer of silicon oxide material over the whole surface of said substrate over which said bit line pattern is formed ; planarizing said bit line interlayer insulating layer to expose the upper surface of said subsidiary silicon nitride layer of said bit line pattern ; forming enlarged grooves exposing portions of said conductive layer of said bit line pattern forming bit lines by wet-etching said subsidiary silicon nitride layer of said bit line pattern to form first grooves and then etching isotropically said subsidiary silicon oxide layer and said bit line interlayer insulating layer around said first grooves ; forming a silicon nitride layer over the whole surface of said substrate over which said enlarged grooves are formed ; forming a silicon nitride pattern by etching anisotropically the whole surface of said silicon nitride layer to expose said bit line interlayer insulating layer , said silicon nitride pattern having silicon nitride spacers formed on side walls of said enlarged grooves positioned on said conductive layer of said bit line pattern forming said bit lines at said enlarged width portions of said bit line pattern ; forming storage node contacts , storage nodes , a dielectric layer , and plate electrodes at a cell area ; forming a wiring interlayer insulating layer on the whole surface of said substrate over which said plate electrodes are formed ; forming metal contact holes exposing at least said conductive layer of said bit line pattern forming said bit lines at said enlarged width portions of said bit line pattern ; and forming (anti reflective coating) plugs filling said metal contact holes by depositing a conductive layer over the whole surface of said substrate over which said metal contact holes are formed . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US20020109229A1 Filed: 2002-04-15 Issued: 2002-08-15 Semiconductor device with improved metal interconnection and method for forming the metal interconnection (Original Assignee) Jeon Jeong-Sic; Kim Jae-Woong; Kim Sang-Hee Jeong-sic Jeon, Jae-woong Kim, Sang-hee Kim |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region (interlevel dielectric) such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch (stop layer) stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (interlevel dielectric) layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US20020109229A1 CLAIM 1 . A semiconductor device comprising : a substrate including a plurality of conductive areas therein ; an interlevel dielectric (interlevel dielectric, spacer region) (ILD) film having a polished surface , the ILD film covering the substrate and having a via hole through which one of the plurality of the conductive areas is exposed and having a trench with a smaller depth than the via hole ; an anti-short insulating layer formed on sidewalls of the trench ; and a metal interconnection formed in the via hole and on the anti-short insulating layer in the trench . US20020109229A1 CLAIM 9 . The semiconductor device of claim 8 , further comprising a polishing stop layer (first etch, etch process) formed on the surface of the ILD film adjacent to the trench , on the insulating spacer in the trench , and on a bottom of the trench . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch (stop layer) stop layer protects removal of a substrate material by an etch process (stop layer) . |
US20020109229A1 CLAIM 9 . The semiconductor device of claim 8 , further comprising a polishing stop layer (first etch, etch process) formed on the surface of the ILD film adjacent to the trench , on the insulating spacer in the trench , and on a bottom of the trench . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (interlevel dielectric) layer insulates said contact region . |
US20020109229A1 CLAIM 1 . A semiconductor device comprising : a substrate including a plurality of conductive areas therein ; an interlevel dielectric (interlevel dielectric, spacer region) (ILD) film having a polished surface , the ILD film covering the substrate and having a via hole through which one of the plurality of the conductive areas is exposed and having a trench with a smaller depth than the via hole ; an anti-short insulating layer formed on sidewalls of the trench ; and a metal interconnection formed in the via hole and on the anti-short insulating layer in the trench . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (interlevel dielectric) layer insulates said contact region . |
US20020109229A1 CLAIM 1 . A semiconductor device comprising : a substrate including a plurality of conductive areas therein ; an interlevel dielectric (interlevel dielectric, spacer region) (ILD) film having a polished surface , the ILD film covering the substrate and having a via hole through which one of the plurality of the conductive areas is exposed and having a trench with a smaller depth than the via hole ; an anti-short insulating layer formed on sidewalls of the trench ; and a metal interconnection formed in the via hole and on the anti-short insulating layer in the trench . |
| US7977797B2 CLAIM 6 . An integrated circuit of claim 1 wherein said spacer region (interlevel dielectric) insulates said contact region . |
US20020109229A1 CLAIM 1 . A semiconductor device comprising : a substrate including a plurality of conductive areas therein ; an interlevel dielectric (interlevel dielectric, spacer region) (ILD) film having a polished surface , the ILD film covering the substrate and having a via hole through which one of the plurality of the conductive areas is exposed and having a trench with a smaller depth than the via hole ; an anti-short insulating layer formed on sidewalls of the trench ; and a metal interconnection formed in the via hole and on the anti-short insulating layer in the trench . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch (stop layer) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (interlevel dielectric) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US20020109229A1 CLAIM 1 . A semiconductor device comprising : a substrate including a plurality of conductive areas therein ; an interlevel dielectric (interlevel dielectric, spacer region) (ILD) film having a polished surface , the ILD film covering the substrate and having a via hole through which one of the plurality of the conductive areas is exposed and having a trench with a smaller depth than the via hole ; an anti-short insulating layer formed on sidewalls of the trench ; and a metal interconnection formed in the via hole and on the anti-short insulating layer in the trench . US20020109229A1 CLAIM 9 . The semiconductor device of claim 8 , further comprising a polishing stop layer (first etch, etch process) formed on the surface of the ILD film adjacent to the trench , on the insulating spacer in the trench , and on a bottom of the trench . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric (interlevel dielectric) layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US20020109229A1 CLAIM 1 . A semiconductor device comprising : a substrate including a plurality of conductive areas therein ; an interlevel dielectric (interlevel dielectric, spacer region) (ILD) film having a polished surface , the ILD film covering the substrate and having a via hole through which one of the plurality of the conductive areas is exposed and having a trench with a smaller depth than the via hole ; an anti-short insulating layer formed on sidewalls of the trench ; and a metal interconnection formed in the via hole and on the anti-short insulating layer in the trench . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US20020109229A1 CLAIM 15 . A method of forming of a semiconductor device , comprising : preparing a semiconductor substrate including a plurality of conductive areas therein ; forming an interlevel dielectric (ILD) film having a polished surface , on the semiconductor substrate ; etching a portion of the ILD film a depth to form a trench , wherein a selected one of the plurality of conductive areas is not located under the portion of the ILD film ; forming an anti-short insulating layer on the ILD film and in the trench ; etching the anti-short insulating layer and the ILD film to form a via hole through which the selected conductive area is exposed ; and forming (anti reflective coating) a metal interconnection in the trench and the via hole . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch (stop layer) stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers (silicon nitride layer) have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (interlevel dielectric) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US20020109229A1 CLAIM 1 . A semiconductor device comprising : a substrate including a plurality of conductive areas therein ; an interlevel dielectric (interlevel dielectric, spacer region) (ILD) film having a polished surface , the ILD film covering the substrate and having a via hole through which one of the plurality of the conductive areas is exposed and having a trench with a smaller depth than the via hole ; an anti-short insulating layer formed on sidewalls of the trench ; and a metal interconnection formed in the via hole and on the anti-short insulating layer in the trench . US20020109229A1 CLAIM 6 . The semiconductor device of claim 5 , wherein the anti-short insulating layer is a silicon nitride layer (second etch stop layers) or a silicon oxynitride layer . US20020109229A1 CLAIM 9 . The semiconductor device of claim 8 , further comprising a polishing stop layer (first etch, etch process) formed on the surface of the ILD film adjacent to the trench , on the insulating spacer in the trench , and on a bottom of the trench . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch (stop layer) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (interlevel dielectric) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US20020109229A1 CLAIM 1 . A semiconductor device comprising : a substrate including a plurality of conductive areas therein ; an interlevel dielectric (interlevel dielectric, spacer region) (ILD) film having a polished surface , the ILD film covering the substrate and having a via hole through which one of the plurality of the conductive areas is exposed and having a trench with a smaller depth than the via hole ; an anti-short insulating layer formed on sidewalls of the trench ; and a metal interconnection formed in the via hole and on the anti-short insulating layer in the trench . US20020109229A1 CLAIM 9 . The semiconductor device of claim 8 , further comprising a polishing stop layer (first etch, etch process) formed on the surface of the ILD film adjacent to the trench , on the insulating spacer in the trench , and on a bottom of the trench . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US20020109229A1 CLAIM 15 . A method of forming of a semiconductor device , comprising : preparing a semiconductor substrate including a plurality of conductive areas therein ; forming an interlevel dielectric (ILD) film having a polished surface , on the semiconductor substrate ; etching a portion of the ILD film a depth to form a trench , wherein a selected one of the plurality of conductive areas is not located under the portion of the ILD film ; forming an anti-short insulating layer on the ILD film and in the trench ; etching the anti-short insulating layer and the ILD film to form a via hole through which the selected conductive area is exposed ; and forming (anti reflective coating) a metal interconnection in the trench and the via hole . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US20020105089A1 Filed: 2002-04-03 Issued: 2002-08-08 Semiconductor device and manufacturing method thereof (Original Assignee) Mitsubishi Electric Corp (Current Assignee) Renesas Electronics Corp Yoshinori Tanaka |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (contact hole) layer over said first etch stop layer ; a second etch (said second circuit) stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US20020105089A1 CLAIM 1 . A semiconductor device in which first and second circuit elements to be conducted to each other are disposed in such a manner as to be spaced from each other with a specific gap kept therebetween in the stacking direction , said semiconductor device comprising : a first interlayer insulating film formed on said first circuit element ; a conductive pad provided in said first interlayer insulating film in such a manner that one end surface thereof is conducted to said first circuit element and the other end surface thereof is exposed to the surface of said first interlayer insulating film ; a second interlayer insulating film formed on said first interlayer insulating film and said pad ; and a conductive plug provided in said second interlayer insulating film in such a manner that one end surface thereof is in contact with said pad and the other end surface thereof is conducted to said second circuit (second etch, etch process) element ; wherein the surface of said first interlayer insulating film is smoothly continuous to the other end surface of said pad at the same level ; and said plug is smaller in size than said pad and is in contact with the central portion of said pad . US20020105089A1 CLAIM 5 . The method of manufacturing a semiconductor device according to claim 2 , wherein said pad is formed from doped silicon ; and wherein said step of providing said plug comprises the steps of : forming a capacitor side contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) in said second interlayer insulating film , said contact hole being smaller in size than said pad and being opened to the central portion of said pad ; forming a first high melting point metal film suitable for preventing absorption of an impurity from said doped silicon in such a manner that said first high melting point metal film covers the surface of said pad exposed to the interior of said capacitor side contact hole ; forming a silicide film near the boundary between said pad and said plug by reaction between said pad and said first high melting point metal film ; removing said first high melting point metal film remaining after formation of said silicide film ; forming a second high melting point metal film suitable for preventing reaction between said doped silicon and a low resistance metal film to be formed later in such a manner that said second high melting point metal film covers the surface of said pad including said silicide film and the wall surface of said capacitor side contact hole ; and forming said low resistance metal film on said second high melting point metal film . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer protects removal of a substrate material (stacking direction, silicon oxide) by an etch process (said second circuit) . |
US20020105089A1 CLAIM 1 . A semiconductor device in which first and second circuit elements to be conducted to each other are disposed in such a manner as to be spaced from each other with a specific gap kept therebetween in the stacking direction (substrate material) , said semiconductor device comprising : a first interlayer insulating film formed on said first circuit element ; a conductive pad provided in said first interlayer insulating film in such a manner that one end surface thereof is conducted to said first circuit element and the other end surface thereof is exposed to the surface of said first interlayer insulating film ; a second interlayer insulating film formed on said first interlayer insulating film and said pad ; and a conductive plug provided in said second interlayer insulating film in such a manner that one end surface thereof is in contact with said pad and the other end surface thereof is conducted to said second circuit (second etch, etch process) element ; wherein the surface of said first interlayer insulating film is smoothly continuous to the other end surface of said pad at the same level ; and said plug is smaller in size than said pad and is in contact with the central portion of said pad . US20020105089A1 CLAIM 15 . The semiconductor device according to claim 13 , further comprising : a silicon nitride film formed on said third interlayer insulating film ; and a silicon oxide (substrate material) film formed on said silicon nitride film ; wherein said first electrode is a cylindrical electrode formed in an opening provided in said silicon oxide film and said silicon nitride film ; and each of said first electrode , said capacitor side plug and said capacitor side pad is made from doped silicon which is doped with an impurity at an arbitrary concentration . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (contact hole) layer insulates said contact region . |
US20020105089A1 CLAIM 5 . The method of manufacturing a semiconductor device according to claim 2 , wherein said pad is formed from doped silicon ; and wherein said step of providing said plug comprises the steps of : forming a capacitor side contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) in said second interlayer insulating film , said contact hole being smaller in size than said pad and being opened to the central portion of said pad ; forming a first high melting point metal film suitable for preventing absorption of an impurity from said doped silicon in such a manner that said first high melting point metal film covers the surface of said pad exposed to the interior of said capacitor side contact hole ; forming a silicide film near the boundary between said pad and said plug by reaction between said pad and said first high melting point metal film ; removing said first high melting point metal film remaining after formation of said silicide film ; forming a second high melting point metal film suitable for preventing reaction between said doped silicon and a low resistance metal film to be formed later in such a manner that said second high melting point metal film covers the surface of said pad including said silicide film and the wall surface of said capacitor side contact hole ; and forming said low resistance metal film on said second high melting point metal film . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch (said second circuit) stop layer protects lower layers during an etching process . |
US20020105089A1 CLAIM 1 . A semiconductor device in which first and second circuit elements to be conducted to each other are disposed in such a manner as to be spaced from each other with a specific gap kept therebetween in the stacking direction , said semiconductor device comprising : a first interlayer insulating film formed on said first circuit element ; a conductive pad provided in said first interlayer insulating film in such a manner that one end surface thereof is conducted to said first circuit element and the other end surface thereof is exposed to the surface of said first interlayer insulating film ; a second interlayer insulating film formed on said first interlayer insulating film and said pad ; and a conductive plug provided in said second interlayer insulating film in such a manner that one end surface thereof is in contact with said pad and the other end surface thereof is conducted to said second circuit (second etch, etch process) element ; wherein the surface of said first interlayer insulating film is smoothly continuous to the other end surface of said pad at the same level ; and said plug is smaller in size than said pad and is in contact with the central portion of said pad . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (contact hole) layer insulates said contact region . |
US20020105089A1 CLAIM 5 . The method of manufacturing a semiconductor device according to claim 2 , wherein said pad is formed from doped silicon ; and wherein said step of providing said plug comprises the steps of : forming a capacitor side contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) in said second interlayer insulating film , said contact hole being smaller in size than said pad and being opened to the central portion of said pad ; forming a first high melting point metal film suitable for preventing absorption of an impurity from said doped silicon in such a manner that said first high melting point metal film covers the surface of said pad exposed to the interior of said capacitor side contact hole ; forming a silicide film near the boundary between said pad and said plug by reaction between said pad and said first high melting point metal film ; removing said first high melting point metal film remaining after formation of said silicide film ; forming a second high melting point metal film suitable for preventing reaction between said doped silicon and a low resistance metal film to be formed later in such a manner that said second high melting point metal film covers the surface of said pad including said silicide film and the wall surface of said capacitor side contact hole ; and forming said low resistance metal film on said second high melting point metal film . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (contact hole) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (said second circuit) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US20020105089A1 CLAIM 1 . A semiconductor device in which first and second circuit elements to be conducted to each other are disposed in such a manner as to be spaced from each other with a specific gap kept therebetween in the stacking direction , said semiconductor device comprising : a first interlayer insulating film formed on said first circuit element ; a conductive pad provided in said first interlayer insulating film in such a manner that one end surface thereof is conducted to said first circuit element and the other end surface thereof is exposed to the surface of said first interlayer insulating film ; a second interlayer insulating film formed on said first interlayer insulating film and said pad ; and a conductive plug provided in said second interlayer insulating film in such a manner that one end surface thereof is in contact with said pad and the other end surface thereof is conducted to said second circuit (second etch, etch process) element ; wherein the surface of said first interlayer insulating film is smoothly continuous to the other end surface of said pad at the same level ; and said plug is smaller in size than said pad and is in contact with the central portion of said pad . US20020105089A1 CLAIM 5 . The method of manufacturing a semiconductor device according to claim 2 , wherein said pad is formed from doped silicon ; and wherein said step of providing said plug comprises the steps of : forming a capacitor side contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) in said second interlayer insulating film , said contact hole being smaller in size than said pad and being opened to the central portion of said pad ; forming a first high melting point metal film suitable for preventing absorption of an impurity from said doped silicon in such a manner that said first high melting point metal film covers the surface of said pad exposed to the interior of said capacitor side contact hole ; forming a silicide film near the boundary between said pad and said plug by reaction between said pad and said first high melting point metal film ; removing said first high melting point metal film remaining after formation of said silicide film ; forming a second high melting point metal film suitable for preventing reaction between said doped silicon and a low resistance metal film to be formed later in such a manner that said second high melting point metal film covers the surface of said pad including said silicide film and the wall surface of said capacitor side contact hole ; and forming said low resistance metal film on said second high melting point metal film . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric (contact hole) layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US20020105089A1 CLAIM 5 . The method of manufacturing a semiconductor device according to claim 2 , wherein said pad is formed from doped silicon ; and wherein said step of providing said plug comprises the steps of : forming a capacitor side contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) in said second interlayer insulating film , said contact hole being smaller in size than said pad and being opened to the central portion of said pad ; forming a first high melting point metal film suitable for preventing absorption of an impurity from said doped silicon in such a manner that said first high melting point metal film covers the surface of said pad exposed to the interior of said capacitor side contact hole ; forming a silicide film near the boundary between said pad and said plug by reaction between said pad and said first high melting point metal film ; removing said first high melting point metal film remaining after formation of said silicide film ; forming a second high melting point metal film suitable for preventing reaction between said doped silicon and a low resistance metal film to be formed later in such a manner that said second high melting point metal film covers the surface of said pad including said silicide film and the wall surface of said capacitor side contact hole ; and forming said low resistance metal film on said second high melting point metal film . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US20020105089A1 CLAIM 5 . The method of manufacturing a semiconductor device according to claim 2 , wherein said pad is formed from doped silicon ; and wherein said step of providing said plug comprises the steps of : forming a capacitor side contact hole in said second interlayer insulating film , said contact hole being smaller in size than said pad and being opened to the central portion of said pad ; forming a first high melting point metal film suitable for preventing absorption of an impurity from said doped silicon in such a manner that said first high melting point metal film covers the surface of said pad exposed to the interior of said capacitor side contact hole ; forming a silicide film near the boundary between said pad and said plug by reaction between said pad and said first high melting point metal film ; removing said first high melting point metal film remaining after formation of said silicide film ; forming a second high melting point metal film suitable for preventing reaction between said doped silicon and a low resistance metal film to be formed later in such a manner that said second high melting point metal film covers the surface of said pad including said silicide film and the wall surface of said capacitor side contact hole ; and forming (anti reflective coating) said low resistance metal film on said second high melting point metal film . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch (said second circuit) stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (contact hole) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US20020105089A1 CLAIM 1 . A semiconductor device in which first and second circuit elements to be conducted to each other are disposed in such a manner as to be spaced from each other with a specific gap kept therebetween in the stacking direction , said semiconductor device comprising : a first interlayer insulating film formed on said first circuit element ; a conductive pad provided in said first interlayer insulating film in such a manner that one end surface thereof is conducted to said first circuit element and the other end surface thereof is exposed to the surface of said first interlayer insulating film ; a second interlayer insulating film formed on said first interlayer insulating film and said pad ; and a conductive plug provided in said second interlayer insulating film in such a manner that one end surface thereof is in contact with said pad and the other end surface thereof is conducted to said second circuit (second etch, etch process) element ; wherein the surface of said first interlayer insulating film is smoothly continuous to the other end surface of said pad at the same level ; and said plug is smaller in size than said pad and is in contact with the central portion of said pad . US20020105089A1 CLAIM 5 . The method of manufacturing a semiconductor device according to claim 2 , wherein said pad is formed from doped silicon ; and wherein said step of providing said plug comprises the steps of : forming a capacitor side contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) in said second interlayer insulating film , said contact hole being smaller in size than said pad and being opened to the central portion of said pad ; forming a first high melting point metal film suitable for preventing absorption of an impurity from said doped silicon in such a manner that said first high melting point metal film covers the surface of said pad exposed to the interior of said capacitor side contact hole ; forming a silicide film near the boundary between said pad and said plug by reaction between said pad and said first high melting point metal film ; removing said first high melting point metal film remaining after formation of said silicide film ; forming a second high melting point metal film suitable for preventing reaction between said doped silicon and a low resistance metal film to be formed later in such a manner that said second high melting point metal film covers the surface of said pad including said silicide film and the wall surface of said capacitor side contact hole ; and forming said low resistance metal film on said second high melting point metal film . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (contact hole) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (said second circuit) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US20020105089A1 CLAIM 1 . A semiconductor device in which first and second circuit elements to be conducted to each other are disposed in such a manner as to be spaced from each other with a specific gap kept therebetween in the stacking direction , said semiconductor device comprising : a first interlayer insulating film formed on said first circuit element ; a conductive pad provided in said first interlayer insulating film in such a manner that one end surface thereof is conducted to said first circuit element and the other end surface thereof is exposed to the surface of said first interlayer insulating film ; a second interlayer insulating film formed on said first interlayer insulating film and said pad ; and a conductive plug provided in said second interlayer insulating film in such a manner that one end surface thereof is in contact with said pad and the other end surface thereof is conducted to said second circuit (second etch, etch process) element ; wherein the surface of said first interlayer insulating film is smoothly continuous to the other end surface of said pad at the same level ; and said plug is smaller in size than said pad and is in contact with the central portion of said pad . US20020105089A1 CLAIM 5 . The method of manufacturing a semiconductor device according to claim 2 , wherein said pad is formed from doped silicon ; and wherein said step of providing said plug comprises the steps of : forming a capacitor side contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) in said second interlayer insulating film , said contact hole being smaller in size than said pad and being opened to the central portion of said pad ; forming a first high melting point metal film suitable for preventing absorption of an impurity from said doped silicon in such a manner that said first high melting point metal film covers the surface of said pad exposed to the interior of said capacitor side contact hole ; forming a silicide film near the boundary between said pad and said plug by reaction between said pad and said first high melting point metal film ; removing said first high melting point metal film remaining after formation of said silicide film ; forming a second high melting point metal film suitable for preventing reaction between said doped silicon and a low resistance metal film to be formed later in such a manner that said second high melting point metal film covers the surface of said pad including said silicide film and the wall surface of said capacitor side contact hole ; and forming said low resistance metal film on said second high melting point metal film . |
| US7977797B2 CLAIM 13 . An integrated circuit of claim 11 further comprising a floating gate (drain regions) . |
US20020105089A1 CLAIM 7 . The method of manufacturing a semiconductor device according to claim 2 , further comprising the step of : forming a transistor on a silicon substrate , said transistor including two source/drain regions (floating gate) and a gate electrode held therebetween ; wherein said first circuit element is said source/drain region and said second circuit element is a first electrode of a capacitor ; and wherein said step of forming said pad comprises the steps of : forming an interconnection side contact hole opened to each of said source/drain regions in said first interlayer insulating film without interference with said gate electrode , and forming said pad conducted to said source/drain region in said interconnection side contact hole ; and said step of forming said plug comprises the steps of : forming a capacitor side contact hole in said second interlayer insulating film , said contact hole being smaller in size than said pad and being opened to the central portion of said pad , forming said plug conducted to said pad in said capacitor side contact hole , forming a first electrode having a specific shape and conducted to said plug , forming an insulating film on said first electrode , and forming a second electrode on said insulating film . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US20020105089A1 CLAIM 5 . The method of manufacturing a semiconductor device according to claim 2 , wherein said pad is formed from doped silicon ; and wherein said step of providing said plug comprises the steps of : forming a capacitor side contact hole in said second interlayer insulating film , said contact hole being smaller in size than said pad and being opened to the central portion of said pad ; forming a first high melting point metal film suitable for preventing absorption of an impurity from said doped silicon in such a manner that said first high melting point metal film covers the surface of said pad exposed to the interior of said capacitor side contact hole ; forming a silicide film near the boundary between said pad and said plug by reaction between said pad and said first high melting point metal film ; removing said first high melting point metal film remaining after formation of said silicide film ; forming a second high melting point metal film suitable for preventing reaction between said doped silicon and a low resistance metal film to be formed later in such a manner that said second high melting point metal film covers the surface of said pad including said silicide film and the wall surface of said capacitor side contact hole ; and forming (anti reflective coating) said low resistance metal film on said second high melting point metal film . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US20030170979A1 Filed: 2002-03-29 Issued: 2003-09-11 Semiconductor device capable of preventing ring defect and method of manufacturing the same (Original Assignee) Samsung Electronics Co Ltd (Current Assignee) Samsung Electronics Co Ltd Si Kim |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region (second contact) coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch (etching rate) stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (second interface, first interface) layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US20030170979A1 CLAIM 1 . A semiconductor device comprising : a semiconductor substrate having a junction region ; a planarization layer formed on the substrate and having an interface with the substrate and having a first contact hole portion through which the junction region is exposed ; an interlayer dielectric layer formed on the planarization layer and having an interface with the planarization layer , the interlayer dielectric layer having a second contact (contact region) hole portion extended from the first contact hole portion ; and contact spacers formed at sidewalls of the first and second contact hole portions , wherein the contact spacers are formed to cover the interface between the planarization layer and the interlayer dielectric layer and the interface between the planarization layer and the semiconductor substrate . US20030170979A1 CLAIM 7 . The semiconductor device of claim 1 , wherein the interlayer dielectric layer has a slower etching rate (first etch, etch process) than the planarization layer in an etchant used to form the first and second contact hole portions . US20030170979A1 CLAIM 18 . A method of manufacturing a semiconductor device comprising : providing a semiconductor substrate having a junction region ; sequentially depositing a planarization layer and an interlayer dielectric layer on the semiconductor substrate , producing a first interface (interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) between the planarization layer and the substrate and a second interface (interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) between the planarization layer and the interlayer dielectric layer ; forming a contact hole to expose the junction region and the interface between the junction region and the planarization layer by etching predetermined portions of the interlayer dielectric layer and the planarization layer ; forming a trench in the exposed junction region of the semiconductor substrate ; forming contact spacers at the sidewalls of the contact hole , the contact spacers extending down to fill portions of the bottom of the trench of the exposed junction region ; cleaning the surface of the semiconductor substrate ; and forming a conductive line to contact the exposed junction region , wherein the contact spacers are formed to cover the interface between the planarization layer and the interlayer dielectric layer and the interface between the planarization layer and , the semiconductor substrate . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch (etching rate) stop layer protects removal of a substrate material by an etch process (etching rate) . |
US20030170979A1 CLAIM 7 . The semiconductor device of claim 1 , wherein the interlayer dielectric layer has a slower etching rate (first etch, etch process) than the planarization layer in an etchant used to form the first and second contact hole portions . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (second interface, first interface) layer insulates said contact region (second contact) . |
US20030170979A1 CLAIM 1 . A semiconductor device comprising : a semiconductor substrate having a junction region ; a planarization layer formed on the substrate and having an interface with the substrate and having a first contact hole portion through which the junction region is exposed ; an interlayer dielectric layer formed on the planarization layer and having an interface with the planarization layer , the interlayer dielectric layer having a second contact (contact region) hole portion extended from the first contact hole portion ; and contact spacers formed at sidewalls of the first and second contact hole portions , wherein the contact spacers are formed to cover the interface between the planarization layer and the interlayer dielectric layer and the interface between the planarization layer and the semiconductor substrate . US20030170979A1 CLAIM 18 . A method of manufacturing a semiconductor device comprising : providing a semiconductor substrate having a junction region ; sequentially depositing a planarization layer and an interlayer dielectric layer on the semiconductor substrate , producing a first interface (interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) between the planarization layer and the substrate and a second interface (interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) between the planarization layer and the interlayer dielectric layer ; forming a contact hole to expose the junction region and the interface between the junction region and the planarization layer by etching predetermined portions of the interlayer dielectric layer and the planarization layer ; forming a trench in the exposed junction region of the semiconductor substrate ; forming contact spacers at the sidewalls of the contact hole , the contact spacers extending down to fill portions of the bottom of the trench of the exposed junction region ; cleaning the surface of the semiconductor substrate ; and forming a conductive line to contact the exposed junction region , wherein the contact spacers are formed to cover the interface between the planarization layer and the interlayer dielectric layer and the interface between the planarization layer and , the semiconductor substrate . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch stop layer protects lower layers during an etching process (etching process) . |
US20030170979A1 CLAIM 19 . The method of claim 18 , wherein the interface between the planarization layer and the semiconductor substrate is exposed by excessively performing the etching process (etching process) for forming the contact hole . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (second interface, first interface) layer insulates said contact region (second contact) . |
US20030170979A1 CLAIM 1 . A semiconductor device comprising : a semiconductor substrate having a junction region ; a planarization layer formed on the substrate and having an interface with the substrate and having a first contact hole portion through which the junction region is exposed ; an interlayer dielectric layer formed on the planarization layer and having an interface with the planarization layer , the interlayer dielectric layer having a second contact (contact region) hole portion extended from the first contact hole portion ; and contact spacers formed at sidewalls of the first and second contact hole portions , wherein the contact spacers are formed to cover the interface between the planarization layer and the interlayer dielectric layer and the interface between the planarization layer and the semiconductor substrate . US20030170979A1 CLAIM 18 . A method of manufacturing a semiconductor device comprising : providing a semiconductor substrate having a junction region ; sequentially depositing a planarization layer and an interlayer dielectric layer on the semiconductor substrate , producing a first interface (interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) between the planarization layer and the substrate and a second interface (interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) between the planarization layer and the interlayer dielectric layer ; forming a contact hole to expose the junction region and the interface between the junction region and the planarization layer by etching predetermined portions of the interlayer dielectric layer and the planarization layer ; forming a trench in the exposed junction region of the semiconductor substrate ; forming contact spacers at the sidewalls of the contact hole , the contact spacers extending down to fill portions of the bottom of the trench of the exposed junction region ; cleaning the surface of the semiconductor substrate ; and forming a conductive line to contact the exposed junction region , wherein the contact spacers are formed to cover the interface between the planarization layer and the interlayer dielectric layer and the interface between the planarization layer and , the semiconductor substrate . |
| US7977797B2 CLAIM 6 . An integrated circuit of claim 1 wherein said spacer region insulates said contact region (second contact) . |
US20030170979A1 CLAIM 1 . A semiconductor device comprising : a semiconductor substrate having a junction region ; a planarization layer formed on the substrate and having an interface with the substrate and having a first contact hole portion through which the junction region is exposed ; an interlayer dielectric layer formed on the planarization layer and having an interface with the planarization layer , the interlayer dielectric layer having a second contact (contact region) hole portion extended from the first contact hole portion ; and contact spacers formed at sidewalls of the first and second contact hole portions , wherein the contact spacers are formed to cover the interface between the planarization layer and the interlayer dielectric layer and the interface between the planarization layer and the semiconductor substrate . |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area of said contact region (second contact) permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
US20030170979A1 CLAIM 1 . A semiconductor device comprising : a semiconductor substrate having a junction region ; a planarization layer formed on the substrate and having an interface with the substrate and having a first contact hole portion through which the junction region is exposed ; an interlayer dielectric layer formed on the planarization layer and having an interface with the planarization layer , the interlayer dielectric layer having a second contact (contact region) hole portion extended from the first contact hole portion ; and contact spacers formed at sidewalls of the first and second contact hole portions , wherein the contact spacers are formed to cover the interface between the planarization layer and the interlayer dielectric layer and the interface between the planarization layer and the semiconductor substrate . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch (etching rate) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (second interface, first interface) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US20030170979A1 CLAIM 7 . The semiconductor device of claim 1 , wherein the interlayer dielectric layer has a slower etching rate (first etch, etch process) than the planarization layer in an etchant used to form the first and second contact hole portions . US20030170979A1 CLAIM 18 . A method of manufacturing a semiconductor device comprising : providing a semiconductor substrate having a junction region ; sequentially depositing a planarization layer and an interlayer dielectric layer on the semiconductor substrate , producing a first interface (interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) between the planarization layer and the substrate and a second interface (interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) between the planarization layer and the interlayer dielectric layer ; forming a contact hole to expose the junction region and the interface between the junction region and the planarization layer by etching predetermined portions of the interlayer dielectric layer and the planarization layer ; forming a trench in the exposed junction region of the semiconductor substrate ; forming contact spacers at the sidewalls of the contact hole , the contact spacers extending down to fill portions of the bottom of the trench of the exposed junction region ; cleaning the surface of the semiconductor substrate ; and forming a conductive line to contact the exposed junction region , wherein the contact spacers are formed to cover the interface between the planarization layer and the interlayer dielectric layer and the interface between the planarization layer and , the semiconductor substrate . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric (second interface, first interface) layer for said contact region (second contact) is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US20030170979A1 CLAIM 1 . A semiconductor device comprising : a semiconductor substrate having a junction region ; a planarization layer formed on the substrate and having an interface with the substrate and having a first contact hole portion through which the junction region is exposed ; an interlayer dielectric layer formed on the planarization layer and having an interface with the planarization layer , the interlayer dielectric layer having a second contact (contact region) hole portion extended from the first contact hole portion ; and contact spacers formed at sidewalls of the first and second contact hole portions , wherein the contact spacers are formed to cover the interface between the planarization layer and the interlayer dielectric layer and the interface between the planarization layer and the semiconductor substrate . US20030170979A1 CLAIM 18 . A method of manufacturing a semiconductor device comprising : providing a semiconductor substrate having a junction region ; sequentially depositing a planarization layer and an interlayer dielectric layer on the semiconductor substrate , producing a first interface (interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) between the planarization layer and the substrate and a second interface (interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) between the planarization layer and the interlayer dielectric layer ; forming a contact hole to expose the junction region and the interface between the junction region and the planarization layer by etching predetermined portions of the interlayer dielectric layer and the planarization layer ; forming a trench in the exposed junction region of the semiconductor substrate ; forming contact spacers at the sidewalls of the contact hole , the contact spacers extending down to fill portions of the bottom of the trench of the exposed junction region ; cleaning the surface of the semiconductor substrate ; and forming a conductive line to contact the exposed junction region , wherein the contact spacers are formed to cover the interface between the planarization layer and the interlayer dielectric layer and the interface between the planarization layer and , the semiconductor substrate . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US20030170979A1 CLAIM 18 . A method of manufacturing a semiconductor device comprising : providing a semiconductor substrate having a junction region ; sequentially depositing a planarization layer and an interlayer dielectric layer on the semiconductor substrate , producing a first interface between the planarization layer and the substrate and a second interface between the planarization layer and the interlayer dielectric layer ; forming a contact hole to expose the junction region and the interface between the junction region and the planarization layer by etching predetermined portions of the interlayer dielectric layer and the planarization layer ; forming a trench in the exposed junction region of the semiconductor substrate ; forming contact spacers at the sidewalls of the contact hole , the contact spacers extending down to fill portions of the bottom of the trench of the exposed junction region ; cleaning the surface of the semiconductor substrate ; and forming (anti reflective coating) a conductive line to contact the exposed junction region , wherein the contact spacers are formed to cover the interface between the planarization layer and the interlayer dielectric layer and the interface between the planarization layer and , the semiconductor substrate . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch (etching rate) stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region (second contact) and under a first sub interlevel dielectric (second interface, first interface) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US20030170979A1 CLAIM 1 . A semiconductor device comprising : a semiconductor substrate having a junction region ; a planarization layer formed on the substrate and having an interface with the substrate and having a first contact hole portion through which the junction region is exposed ; an interlayer dielectric layer formed on the planarization layer and having an interface with the planarization layer , the interlayer dielectric layer having a second contact (contact region) hole portion extended from the first contact hole portion ; and contact spacers formed at sidewalls of the first and second contact hole portions , wherein the contact spacers are formed to cover the interface between the planarization layer and the interlayer dielectric layer and the interface between the planarization layer and the semiconductor substrate . US20030170979A1 CLAIM 7 . The semiconductor device of claim 1 , wherein the interlayer dielectric layer has a slower etching rate (first etch, etch process) than the planarization layer in an etchant used to form the first and second contact hole portions . US20030170979A1 CLAIM 18 . A method of manufacturing a semiconductor device comprising : providing a semiconductor substrate having a junction region ; sequentially depositing a planarization layer and an interlayer dielectric layer on the semiconductor substrate , producing a first interface (interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) between the planarization layer and the substrate and a second interface (interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) between the planarization layer and the interlayer dielectric layer ; forming a contact hole to expose the junction region and the interface between the junction region and the planarization layer by etching predetermined portions of the interlayer dielectric layer and the planarization layer ; forming a trench in the exposed junction region of the semiconductor substrate ; forming contact spacers at the sidewalls of the contact hole , the contact spacers extending down to fill portions of the bottom of the trench of the exposed junction region ; cleaning the surface of the semiconductor substrate ; and forming a conductive line to contact the exposed junction region , wherein the contact spacers are formed to cover the interface between the planarization layer and the interlayer dielectric layer and the interface between the planarization layer and , the semiconductor substrate . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch (etching rate) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (second interface, first interface) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US20030170979A1 CLAIM 7 . The semiconductor device of claim 1 , wherein the interlayer dielectric layer has a slower etching rate (first etch, etch process) than the planarization layer in an etchant used to form the first and second contact hole portions . US20030170979A1 CLAIM 18 . A method of manufacturing a semiconductor device comprising : providing a semiconductor substrate having a junction region ; sequentially depositing a planarization layer and an interlayer dielectric layer on the semiconductor substrate , producing a first interface (interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) between the planarization layer and the substrate and a second interface (interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) between the planarization layer and the interlayer dielectric layer ; forming a contact hole to expose the junction region and the interface between the junction region and the planarization layer by etching predetermined portions of the interlayer dielectric layer and the planarization layer ; forming a trench in the exposed junction region of the semiconductor substrate ; forming contact spacers at the sidewalls of the contact hole , the contact spacers extending down to fill portions of the bottom of the trench of the exposed junction region ; cleaning the surface of the semiconductor substrate ; and forming a conductive line to contact the exposed junction region , wherein the contact spacers are formed to cover the interface between the planarization layer and the interlayer dielectric layer and the interface between the planarization layer and , the semiconductor substrate . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US20030170979A1 CLAIM 18 . A method of manufacturing a semiconductor device comprising : providing a semiconductor substrate having a junction region ; sequentially depositing a planarization layer and an interlayer dielectric layer on the semiconductor substrate , producing a first interface between the planarization layer and the substrate and a second interface between the planarization layer and the interlayer dielectric layer ; forming a contact hole to expose the junction region and the interface between the junction region and the planarization layer by etching predetermined portions of the interlayer dielectric layer and the planarization layer ; forming a trench in the exposed junction region of the semiconductor substrate ; forming contact spacers at the sidewalls of the contact hole , the contact spacers extending down to fill portions of the bottom of the trench of the exposed junction region ; cleaning the surface of the semiconductor substrate ; and forming (anti reflective coating) a conductive line to contact the exposed junction region , wherein the contact spacers are formed to cover the interface between the planarization layer and the interlayer dielectric layer and the interface between the planarization layer and , the semiconductor substrate . |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region (second contact) is a first range of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US20030170979A1 CLAIM 1 . A semiconductor device comprising : a semiconductor substrate having a junction region ; a planarization layer formed on the substrate and having an interface with the substrate and having a first contact hole portion through which the junction region is exposed ; an interlayer dielectric layer formed on the planarization layer and having an interface with the planarization layer , the interlayer dielectric layer having a second contact (contact region) hole portion extended from the first contact hole portion ; and contact spacers formed at sidewalls of the first and second contact hole portions , wherein the contact spacers are formed to cover the interface between the planarization layer and the interlayer dielectric layer and the interface between the planarization layer and the semiconductor substrate . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US20020068443A1 Filed: 2002-01-14 Issued: 2002-06-06 Semiconductor device and method of fabricating the same (Original Assignee) Mitsubishi Electric Corp (Current Assignee) Mitsubishi Electric Corp Takahisa Eimori |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch (etching rate, high etching) stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US20020068443A1 CLAIM 1 . A semiconductor device comprising : a semiconductor base layer ; a multilayer interlayer insulating film formed on said semiconductor base layer and consisting of a plurality of layers differing from each other in etching rate (first etch, etch process) ; and at least a contact formed in a hole which is in turn formed in said multilayer interlayer insulating film , the contact being in contact with said semiconductor base layer ; wherein the diameter of said contact is increased in a portion thereof contiguous with said semiconductor base layer . US20020068443A1 CLAIM 7 . The semiconductor device according to claim 1 , wherein a portion of said interlayer insulating film contiguous with said semiconductor base layer is formed to have a high etching (first etch, etch process) rate , as compared with other portions of said interlayer insulating film . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch (etching rate, high etching) stop layer protects removal of a substrate material by an etch process (etching rate, high etching) . |
US20020068443A1 CLAIM 1 . A semiconductor device comprising : a semiconductor base layer ; a multilayer interlayer insulating film formed on said semiconductor base layer and consisting of a plurality of layers differing from each other in etching rate (first etch, etch process) ; and at least a contact formed in a hole which is in turn formed in said multilayer interlayer insulating film , the contact being in contact with said semiconductor base layer ; wherein the diameter of said contact is increased in a portion thereof contiguous with said semiconductor base layer . US20020068443A1 CLAIM 7 . The semiconductor device according to claim 1 , wherein a portion of said interlayer insulating film contiguous with said semiconductor base layer is formed to have a high etching (first etch, etch process) rate , as compared with other portions of said interlayer insulating film . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch (etching rate, high etching) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US20020068443A1 CLAIM 1 . A semiconductor device comprising : a semiconductor base layer ; a multilayer interlayer insulating film formed on said semiconductor base layer and consisting of a plurality of layers differing from each other in etching rate (first etch, etch process) ; and at least a contact formed in a hole which is in turn formed in said multilayer interlayer insulating film , the contact being in contact with said semiconductor base layer ; wherein the diameter of said contact is increased in a portion thereof contiguous with said semiconductor base layer . US20020068443A1 CLAIM 7 . The semiconductor device according to claim 1 , wherein a portion of said interlayer insulating film contiguous with said semiconductor base layer is formed to have a high etching (first etch, etch process) rate , as compared with other portions of said interlayer insulating film . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US20020068443A1 CLAIM 14 . A method of fabricating a semiconductor device comprising the steps of : forming on a semiconductor base layer an interlayer insulating film in which the portion nearer to the semiconductor base layer has relatively higher etching rate and the portion farther from the semiconductor base layer has relatively low etching rates , respectively ; forming at least a hole through the interlayer insulating film so that the diameter of the hole increases toward the semiconductor base layer ; and forming (anti reflective coating) a contact in the hole so as to be connected to the semiconductor base layer . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch (etching rate, high etching) stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers (adjacent pair) have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US20020068443A1 CLAIM 1 . A semiconductor device comprising : a semiconductor base layer ; a multilayer interlayer insulating film formed on said semiconductor base layer and consisting of a plurality of layers differing from each other in etching rate (first etch, etch process) ; and at least a contact formed in a hole which is in turn formed in said multilayer interlayer insulating film , the contact being in contact with said semiconductor base layer ; wherein the diameter of said contact is increased in a portion thereof contiguous with said semiconductor base layer . US20020068443A1 CLAIM 3 . The semiconductor device according to claim 2 , wherein a plurality of said conductive elements are formed , and said contact is positioned between the adjacent pair (second etch stop layers) of said plurality of conductive elements . US20020068443A1 CLAIM 7 . The semiconductor device according to claim 1 , wherein a portion of said interlayer insulating film contiguous with said semiconductor base layer is formed to have a high etching (first etch, etch process) rate , as compared with other portions of said interlayer insulating film . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch (etching rate, high etching) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US20020068443A1 CLAIM 1 . A semiconductor device comprising : a semiconductor base layer ; a multilayer interlayer insulating film formed on said semiconductor base layer and consisting of a plurality of layers differing from each other in etching rate (first etch, etch process) ; and at least a contact formed in a hole which is in turn formed in said multilayer interlayer insulating film , the contact being in contact with said semiconductor base layer ; wherein the diameter of said contact is increased in a portion thereof contiguous with said semiconductor base layer . US20020068443A1 CLAIM 7 . The semiconductor device according to claim 1 , wherein a portion of said interlayer insulating film contiguous with said semiconductor base layer is formed to have a high etching (first etch, etch process) rate , as compared with other portions of said interlayer insulating film . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US20020068443A1 CLAIM 14 . A method of fabricating a semiconductor device comprising the steps of : forming on a semiconductor base layer an interlayer insulating film in which the portion nearer to the semiconductor base layer has relatively higher etching rate and the portion farther from the semiconductor base layer has relatively low etching rates , respectively ; forming at least a hole through the interlayer insulating film so that the diameter of the hole increases toward the semiconductor base layer ; and forming (anti reflective coating) a contact in the hole so as to be connected to the semiconductor base layer . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US20020079581A1 Filed: 2001-11-02 Issued: 2002-06-27 Electrical contact for high dielectric constant capacitors and method for fabricating the same (Original Assignee) Graettinger Thomas M.; Gealy F. Daniel Thomas Graettinger, F. Gealy |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region (interlevel dielectric layer) such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (conductive oxide) of said contact region ; and a multiple etch (tungsten nitride) stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (high dielectric constant, bottom electrode, conductive word) layer over said first etch stop layer ; a second etch stop layer (gate stack) over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US20020079581A1 CLAIM 4 . The contact structure according to claim 1 , wherein said conductive filler comprises a conductive oxide (metal layer coupling area) . US20020079581A1 CLAIM 9 . The contact structure according to claim 7 , wherein said conductive barrier layer comprises tungsten nitride (multiple etch) . US20020079581A1 CLAIM 28 . The integrated circuit of claim 16 , wherein the insulating spacer directly contacts a conductive layer of the transistor gate stack (second etch stop layer, second etch stop layers) . US20020079581A1 CLAIM 36 . The system of claim 29 , wherein the diffusion barrier directly contacts a conductive word (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) or digit line . US20020079581A1 CLAIM 37 . A memory cell in an integrated circuit , comprising : a capacitor having a top electrode , a bottom electrode (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) , and a high dielectric constant (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) dielectric between the top electrode and the bottom electrode ; a semiconductor substrate having an active area ; a contact plug between the bottom electrode and the active area , the contact plug comprising a non-oxidizing conductive material ; an interlevel dielectric layer (spacer region) surrounding the contact plug ; and a non-conductive spacer between the contact plug and the surrounding interlevel dielectric layer . US20020079581A1 CLAIM 45 . The integrated circuit of claim 44 , wherein the contact connects a transistor active area to a memory cell capacitor , the capacitor incorporating a complex oxide material (second sub interlevel dielectric layer) . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (high dielectric constant, bottom electrode, conductive word) layer insulates said contact region . |
US20020079581A1 CLAIM 36 . The system of claim 29 , wherein the diffusion barrier directly contacts a conductive word (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) or digit line . US20020079581A1 CLAIM 37 . A memory cell in an integrated circuit , comprising : a capacitor having a top electrode , a bottom electrode (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) , and a high dielectric constant (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) dielectric between the top electrode and the bottom electrode ; a semiconductor substrate having an active area ; a contact plug between the bottom electrode and the active area , the contact plug comprising a non-oxidizing conductive material ; an interlevel dielectric layer surrounding the contact plug ; and a non-conductive spacer between the contact plug and the surrounding interlevel dielectric layer . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch stop layer (gate stack) protects lower layers during an etching process . |
US20020079581A1 CLAIM 28 . The integrated circuit of claim 16 , wherein the insulating spacer directly contacts a conductive layer of the transistor gate stack (second etch stop layer, second etch stop layers) . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (high dielectric constant, bottom electrode, conductive word) layer insulates said contact region . |
US20020079581A1 CLAIM 36 . The system of claim 29 , wherein the diffusion barrier directly contacts a conductive word (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) or digit line . US20020079581A1 CLAIM 37 . A memory cell in an integrated circuit , comprising : a capacitor having a top electrode , a bottom electrode (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) , and a high dielectric constant (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) dielectric between the top electrode and the bottom electrode ; a semiconductor substrate having an active area ; a contact plug between the bottom electrode and the active area , the contact plug comprising a non-oxidizing conductive material ; an interlevel dielectric layer surrounding the contact plug ; and a non-conductive spacer between the contact plug and the surrounding interlevel dielectric layer . US20020079581A1 CLAIM 45 . The integrated circuit of claim 44 , wherein the contact connects a transistor active area to a memory cell capacitor , the capacitor incorporating a complex oxide material (second sub interlevel dielectric layer) . |
| US7977797B2 CLAIM 6 . An integrated circuit of claim 1 wherein said spacer region (interlevel dielectric layer) insulates said contact region . |
US20020079581A1 CLAIM 37 . A memory cell in an integrated circuit , comprising : a capacitor having a top electrode , a bottom electrode , and a high dielectric constant dielectric between the top electrode and the bottom electrode ; a semiconductor substrate having an active area ; a contact plug between the bottom electrode and the active area , the contact plug comprising a non-oxidizing conductive material ; an interlevel dielectric layer (spacer region) surrounding the contact plug ; and a non-conductive spacer between the contact plug and the surrounding interlevel dielectric layer . |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area of said contact region permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area (conductive oxide) of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
US20020079581A1 CLAIM 4 . The contact structure according to claim 1 , wherein said conductive filler comprises a conductive oxide (metal layer coupling area) . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (high dielectric constant, bottom electrode, conductive word) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer (gate stack) is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US20020079581A1 CLAIM 28 . The integrated circuit of claim 16 , wherein the insulating spacer directly contacts a conductive layer of the transistor gate stack (second etch stop layer, second etch stop layers) . US20020079581A1 CLAIM 36 . The system of claim 29 , wherein the diffusion barrier directly contacts a conductive word (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) or digit line . US20020079581A1 CLAIM 37 . A memory cell in an integrated circuit , comprising : a capacitor having a top electrode , a bottom electrode (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) , and a high dielectric constant (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) dielectric between the top electrode and the bottom electrode ; a semiconductor substrate having an active area ; a contact plug between the bottom electrode and the active area , the contact plug comprising a non-oxidizing conductive material ; an interlevel dielectric layer surrounding the contact plug ; and a non-conductive spacer between the contact plug and the surrounding interlevel dielectric layer . US20020079581A1 CLAIM 45 . The integrated circuit of claim 44 , wherein the contact connects a transistor active area to a memory cell capacitor , the capacitor incorporating a complex oxide material (second sub interlevel dielectric layer) . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space (said sub) in a portion of said first sub interlevel dielectric (high dielectric constant, bottom electrode, conductive word) layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US20020079581A1 CLAIM 36 . The system of claim 29 , wherein the diffusion barrier directly contacts a conductive word (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) or digit line . US20020079581A1 CLAIM 37 . A memory cell in an integrated circuit , comprising : a capacitor having a top electrode , a bottom electrode (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) , and a high dielectric constant (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) dielectric between the top electrode and the bottom electrode ; a semiconductor substrate having an active area ; a contact plug between the bottom electrode and the active area , the contact plug comprising a non-oxidizing conductive material ; an interlevel dielectric layer surrounding the contact plug ; and a non-conductive spacer between the contact plug and the surrounding interlevel dielectric layer . US20020079581A1 CLAIM 45 . The integrated circuit of claim 44 , wherein the contact connects a transistor active area to a memory cell capacitor , the capacitor incorporating a complex oxide material (second sub interlevel dielectric layer) . US20020079581A1 CLAIM 52 . The process of claim 51 , wherein forming said silicide comprises : depositing a titanium layer within said non-conductive liner in said contact hole ; and reacting said titanium layer with said sub (first space) strate . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US20020079581A1 CLAIM 48 . A process for forming an electrical interconnection between a capacitor and an active area in a semiconductor substrate , comprising : providing an interlevel dielectric over said semiconductor substrate ; etching said interlevel dielectric to form a contact hole exposing the active area ; depositing a non-conductive layer into said contact hole ; conducting a spacer etch on said non-conductive layer to define a nonconductive liner and expose said active area in said contact hole ; depositing a conductive material within said non-conductive liner in said contact hole ; and forming (anti reflective coating) a capacitor over said contact plug . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch (tungsten nitride) stop insulation layer comprising a first etch stop layer and a second etch stop layer (gate stack) wherein said first etch stop layer and said second etch stop layers (gate stack) have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (high dielectric constant, bottom electrode, conductive word) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (conductive oxide) of said contact region . |
US20020079581A1 CLAIM 4 . The contact structure according to claim 1 , wherein said conductive filler comprises a conductive oxide (metal layer coupling area) . US20020079581A1 CLAIM 9 . The contact structure according to claim 7 , wherein said conductive barrier layer comprises tungsten nitride (multiple etch) . US20020079581A1 CLAIM 28 . The integrated circuit of claim 16 , wherein the insulating spacer directly contacts a conductive layer of the transistor gate stack (second etch stop layer, second etch stop layers) . US20020079581A1 CLAIM 36 . The system of claim 29 , wherein the diffusion barrier directly contacts a conductive word (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) or digit line . US20020079581A1 CLAIM 37 . A memory cell in an integrated circuit , comprising : a capacitor having a top electrode , a bottom electrode (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) , and a high dielectric constant (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) dielectric between the top electrode and the bottom electrode ; a semiconductor substrate having an active area ; a contact plug between the bottom electrode and the active area , the contact plug comprising a non-oxidizing conductive material ; an interlevel dielectric layer surrounding the contact plug ; and a non-conductive spacer between the contact plug and the surrounding interlevel dielectric layer . US20020079581A1 CLAIM 45 . The integrated circuit of claim 44 , wherein the contact connects a transistor active area to a memory cell capacitor , the capacitor incorporating a complex oxide material (second sub interlevel dielectric layer) . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (high dielectric constant, bottom electrode, conductive word) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer (gate stack) is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US20020079581A1 CLAIM 28 . The integrated circuit of claim 16 , wherein the insulating spacer directly contacts a conductive layer of the transistor gate stack (second etch stop layer, second etch stop layers) . US20020079581A1 CLAIM 36 . The system of claim 29 , wherein the diffusion barrier directly contacts a conductive word (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) or digit line . US20020079581A1 CLAIM 37 . A memory cell in an integrated circuit , comprising : a capacitor having a top electrode , a bottom electrode (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) , and a high dielectric constant (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) dielectric between the top electrode and the bottom electrode ; a semiconductor substrate having an active area ; a contact plug between the bottom electrode and the active area , the contact plug comprising a non-oxidizing conductive material ; an interlevel dielectric layer surrounding the contact plug ; and a non-conductive spacer between the contact plug and the surrounding interlevel dielectric layer . US20020079581A1 CLAIM 45 . The integrated circuit of claim 44 , wherein the contact connects a transistor active area to a memory cell capacitor , the capacitor incorporating a complex oxide material (second sub interlevel dielectric layer) . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US20020079581A1 CLAIM 48 . A process for forming an electrical interconnection between a capacitor and an active area in a semiconductor substrate , comprising : providing an interlevel dielectric over said semiconductor substrate ; etching said interlevel dielectric to form a contact hole exposing the active area ; depositing a non-conductive layer into said contact hole ; conducting a spacer etch on said non-conductive layer to define a nonconductive liner and expose said active area in said contact hole ; depositing a conductive material within said non-conductive liner in said contact hole ; and forming (anti reflective coating) a capacitor over said contact plug . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US20020070401A1 Filed: 2001-10-26 Issued: 2002-06-13 Semiconductor storage device and method of fabricating thereof (Original Assignee) Nippon Steel Corp (Current Assignee) United Microelectronics Corp Hideki Takeuchi, Hirohiko Izumi |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (upper electrodes, like shape) of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US20020070401A1 CLAIM 1 . A semiconductor storage device , comprising : a semiconductor substrate having a device activation region defined by a device isolation structure ; an access transistor formed at said device activation region in said semiconductor substrate , and having a gate electrode and a pair of impurity diffusion layers ; a first insulating film formed over said access transistor , and having a first contact hole for exposing a portion of a surface of one of said pair of impurity diffusion layers ; a protective film formed on said first insulating film , and having a second contact hole formed on said first contact hole ; a second insulating film formed on a side wall face of said first contact hole in said first insulating film and on a side wall face of said second contact hole in said protective film ; and a memory capacitor in which a lower electrode and an upper electrode are opposed to each other and capacitive-coupled through a dielectric film , wherein said lower electrode of said memory capacitor is filled inside said first and second contact holes to be formed in an island-like shape (metal layer coupling area) on said first insulating film through said protective film so as to be electrically connected with the one of said pair of impurity diffusion layers . US20020070401A1 CLAIM 3 . A semiconductor storage device as claimed in claim 1 , wherein each of said lower and upper electrodes (metal layer coupling area) of said memory capacitor is made of a polycrystal silicon film . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch stop layer protects lower layers during an etching process (film thickness, uniform film) . |
US20020070401A1 CLAIM 21 . A method of fabricating a semiconductor storage device , said semiconductor storage device comprising : a semiconductor substrate having a device activation region defined by a device isolation structure ; an access transistor formed at said device activation region in said semiconductor substrate , and having a gate electrode and a pair of impurity diffusion layers ; and a memory capacitor in which a lower electrode and an upper electrode are opposed to each other and capacitive-coupled through a dielectric film , comprising : a first step of forming a first insulating film over said access transistor ; a second step of forming a protective film on said first insulating film ; a third step of patterning said first insulating film and said protective film by means of a photolithography so as to form first and second contact holes for exposing a portion of a surface of one of said pair of impurity diffusion layers in said first insulating film and said protective film , respectively ; a fourth step of forming a second insulating film in a uniform film thickness (etching process) or a homogeneous film thickness on side wall faces of said first and second contact holes and on a surface of said protective film ; a fifth step of etching said second insulating film with said protective film as a stopper so as to leave said second insulating film only on the side wall faces of said first and second contact holes ; a sixth step of forming a conducting film on said protective film so as to fill said first and second contact holes ; and a seventh step of patterning said conducting film so as to form said lower electrode of said memory capacitor in an island-like shape on said protective film . |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area of said contact region permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area (upper electrodes, like shape) of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
US20020070401A1 CLAIM 1 . A semiconductor storage device , comprising : a semiconductor substrate having a device activation region defined by a device isolation structure ; an access transistor formed at said device activation region in said semiconductor substrate , and having a gate electrode and a pair of impurity diffusion layers ; a first insulating film formed over said access transistor , and having a first contact hole for exposing a portion of a surface of one of said pair of impurity diffusion layers ; a protective film formed on said first insulating film , and having a second contact hole formed on said first contact hole ; a second insulating film formed on a side wall face of said first contact hole in said first insulating film and on a side wall face of said second contact hole in said protective film ; and a memory capacitor in which a lower electrode and an upper electrode are opposed to each other and capacitive-coupled through a dielectric film , wherein said lower electrode of said memory capacitor is filled inside said first and second contact holes to be formed in an island-like shape (metal layer coupling area) on said first insulating film through said protective film so as to be electrically connected with the one of said pair of impurity diffusion layers . US20020070401A1 CLAIM 3 . A semiconductor storage device as claimed in claim 1 , wherein each of said lower and upper electrodes (metal layer coupling area) of said memory capacitor is made of a polycrystal silicon film . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (upper electrodes, like shape) of said contact region . |
US20020070401A1 CLAIM 1 . A semiconductor storage device , comprising : a semiconductor substrate having a device activation region defined by a device isolation structure ; an access transistor formed at said device activation region in said semiconductor substrate , and having a gate electrode and a pair of impurity diffusion layers ; a first insulating film formed over said access transistor , and having a first contact hole for exposing a portion of a surface of one of said pair of impurity diffusion layers ; a protective film formed on said first insulating film , and having a second contact hole formed on said first contact hole ; a second insulating film formed on a side wall face of said first contact hole in said first insulating film and on a side wall face of said second contact hole in said protective film ; and a memory capacitor in which a lower electrode and an upper electrode are opposed to each other and capacitive-coupled through a dielectric film , wherein said lower electrode of said memory capacitor is filled inside said first and second contact holes to be formed in an island-like shape (metal layer coupling area) on said first insulating film through said protective film so as to be electrically connected with the one of said pair of impurity diffusion layers . US20020070401A1 CLAIM 3 . A semiconductor storage device as claimed in claim 1 , wherein each of said lower and upper electrodes (metal layer coupling area) of said memory capacitor is made of a polycrystal silicon film . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US20020093105A1 Filed: 2001-09-07 Issued: 2002-07-18 Semiconductor device having a contact window and fabrication method thereof (Original Assignee) Samsung Electronics Co Ltd (Current Assignee) Samsung Electronics Co Ltd Jeong-sic Jeon, Jae-woong Kim |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch (layer dielectric, wet etch, dry etch, low rate) stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch (layer dielectric, wet etch, dry etch, low rate) stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch (layer dielectric, wet etch, dry etch, low rate) stop layer (layer dielectric, wet etch, dry etch, low rate) over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US20020093105A1 CLAIM 2 . The method of claim 1 , wherein the anisotropic etching is performed using a dry etch (multiple etch, etch process, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, second etch stop layers, second etch) ing process and the isotropic etching is performed using a wet etch (multiple etch, etch process, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, second etch stop layers, second etch) ing process . US20020093105A1 CLAIM 8 . The method of claim 7 , wherein the lower dielectric layer is formed by a process in which a flow rate (multiple etch, etch process, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, second etch stop layers, second etch) of O 3 gas decreases and a flow rate of O 2 gas increases . US20020093105A1 CLAIM 30 . A semiconductor device comprising : an interlayer dielectric (multiple etch, etch process, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, second etch stop layers, second etch) layer on a semiconductor substrate , wherein the interlayer dielectric layer comprises a first dielectric layer , a second dielectric layer and a upper dielectric layer ; a contact window passing through the interlayer dielectric layer , wherein a lower region of the contact window has a wider width than that of an upper region of the contact window ; and a plurality of conductive patterns intervening between the second dielectric layer and the upper dielectric layer , wherein the conductive patterns are spaced apart from the contact window . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch (layer dielectric, wet etch, dry etch, low rate) stop layer protects removal of a substrate material by an etch process (layer dielectric, wet etch, dry etch, low rate) . |
US20020093105A1 CLAIM 2 . The method of claim 1 , wherein the anisotropic etching is performed using a dry etch (multiple etch, etch process, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, second etch stop layers, second etch) ing process and the isotropic etching is performed using a wet etch (multiple etch, etch process, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, second etch stop layers, second etch) ing process . US20020093105A1 CLAIM 8 . The method of claim 7 , wherein the lower dielectric layer is formed by a process in which a flow rate (multiple etch, etch process, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, second etch stop layers, second etch) of O 3 gas decreases and a flow rate of O 2 gas increases . US20020093105A1 CLAIM 30 . A semiconductor device comprising : an interlayer dielectric (multiple etch, etch process, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, second etch stop layers, second etch) layer on a semiconductor substrate , wherein the interlayer dielectric layer comprises a first dielectric layer , a second dielectric layer and a upper dielectric layer ; a contact window passing through the interlayer dielectric layer , wherein a lower region of the contact window has a wider width than that of an upper region of the contact window ; and a plurality of conductive patterns intervening between the second dielectric layer and the upper dielectric layer , wherein the conductive patterns are spaced apart from the contact window . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch (layer dielectric, wet etch, dry etch, low rate) stop layer (layer dielectric, wet etch, dry etch, low rate) protects lower layers during an etching process (etching process) . |
US20020093105A1 CLAIM 2 . The method of claim 1 , wherein the anisotropic etching is performed using a dry etching process (etching process) and the isotropic etching is performed using a wet etching process . US20020093105A1 CLAIM 8 . The method of claim 7 , wherein the lower dielectric layer is formed by a process in which a flow rate (multiple etch, etch process, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, second etch stop layers, second etch) of O 3 gas decreases and a flow rate of O 2 gas increases . US20020093105A1 CLAIM 30 . A semiconductor device comprising : an interlayer dielectric (multiple etch, etch process, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, second etch stop layers, second etch) layer on a semiconductor substrate , wherein the interlayer dielectric layer comprises a first dielectric layer , a second dielectric layer and a upper dielectric layer ; a contact window passing through the interlayer dielectric layer , wherein a lower region of the contact window has a wider width than that of an upper region of the contact window ; and a plurality of conductive patterns intervening between the second dielectric layer and the upper dielectric layer , wherein the conductive patterns are spaced apart from the contact window . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch (layer dielectric, wet etch, dry etch, low rate) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (layer dielectric, wet etch, dry etch, low rate) stop layer (layer dielectric, wet etch, dry etch, low rate) is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US20020093105A1 CLAIM 2 . The method of claim 1 , wherein the anisotropic etching is performed using a dry etch (multiple etch, etch process, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, second etch stop layers, second etch) ing process and the isotropic etching is performed using a wet etch (multiple etch, etch process, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, second etch stop layers, second etch) ing process . US20020093105A1 CLAIM 8 . The method of claim 7 , wherein the lower dielectric layer is formed by a process in which a flow rate (multiple etch, etch process, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, second etch stop layers, second etch) of O 3 gas decreases and a flow rate of O 2 gas increases . US20020093105A1 CLAIM 30 . A semiconductor device comprising : an interlayer dielectric (multiple etch, etch process, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, second etch stop layers, second etch) layer on a semiconductor substrate , wherein the interlayer dielectric layer comprises a first dielectric layer , a second dielectric layer and a upper dielectric layer ; a contact window passing through the interlayer dielectric layer , wherein a lower region of the contact window has a wider width than that of an upper region of the contact window ; and a plurality of conductive patterns intervening between the second dielectric layer and the upper dielectric layer , wherein the conductive patterns are spaced apart from the contact window . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US20020093105A1 CLAIM 5 . The method of claim 1 , wherein forming the lower dielectric layer comprises : forming a first dielectric layer on the semiconductor substrate ; and forming (anti reflective coating) a second dielectric layer on the first dielectric layer , wherein the second dielectric layer has a lower etch rate than the first dielectric layer during the isotropic etching . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch (layer dielectric, wet etch, dry etch, low rate) stop insulation layer comprising a first etch (layer dielectric, wet etch, dry etch, low rate) stop layer and a second etch (layer dielectric, wet etch, dry etch, low rate) stop layer (layer dielectric, wet etch, dry etch, low rate) wherein said first etch stop layer and said second etch stop layers (layer dielectric, wet etch, dry etch, low rate) have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US20020093105A1 CLAIM 2 . The method of claim 1 , wherein the anisotropic etching is performed using a dry etch (multiple etch, etch process, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, second etch stop layers, second etch) ing process and the isotropic etching is performed using a wet etch (multiple etch, etch process, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, second etch stop layers, second etch) ing process . US20020093105A1 CLAIM 8 . The method of claim 7 , wherein the lower dielectric layer is formed by a process in which a flow rate (multiple etch, etch process, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, second etch stop layers, second etch) of O 3 gas decreases and a flow rate of O 2 gas increases . US20020093105A1 CLAIM 30 . A semiconductor device comprising : an interlayer dielectric (multiple etch, etch process, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, second etch stop layers, second etch) layer on a semiconductor substrate , wherein the interlayer dielectric layer comprises a first dielectric layer , a second dielectric layer and a upper dielectric layer ; a contact window passing through the interlayer dielectric layer , wherein a lower region of the contact window has a wider width than that of an upper region of the contact window ; and a plurality of conductive patterns intervening between the second dielectric layer and the upper dielectric layer , wherein the conductive patterns are spaced apart from the contact window . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch (layer dielectric, wet etch, dry etch, low rate) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (layer dielectric, wet etch, dry etch, low rate) stop layer (layer dielectric, wet etch, dry etch, low rate) is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US20020093105A1 CLAIM 2 . The method of claim 1 , wherein the anisotropic etching is performed using a dry etch (multiple etch, etch process, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, second etch stop layers, second etch) ing process and the isotropic etching is performed using a wet etch (multiple etch, etch process, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, second etch stop layers, second etch) ing process . US20020093105A1 CLAIM 8 . The method of claim 7 , wherein the lower dielectric layer is formed by a process in which a flow rate (multiple etch, etch process, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, second etch stop layers, second etch) of O 3 gas decreases and a flow rate of O 2 gas increases . US20020093105A1 CLAIM 30 . A semiconductor device comprising : an interlayer dielectric (multiple etch, etch process, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, second etch stop layers, second etch) layer on a semiconductor substrate , wherein the interlayer dielectric layer comprises a first dielectric layer , a second dielectric layer and a upper dielectric layer ; a contact window passing through the interlayer dielectric layer , wherein a lower region of the contact window has a wider width than that of an upper region of the contact window ; and a plurality of conductive patterns intervening between the second dielectric layer and the upper dielectric layer , wherein the conductive patterns are spaced apart from the contact window . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US20020093105A1 CLAIM 5 . The method of claim 1 , wherein forming the lower dielectric layer comprises : forming a first dielectric layer on the semiconductor substrate ; and forming (anti reflective coating) a second dielectric layer on the first dielectric layer , wherein the second dielectric layer has a lower etch rate than the first dielectric layer during the isotropic etching . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US20020048865A1 Filed: 2001-08-31 Issued: 2002-04-25 Method of forming a local interconnect (Original Assignee) Manning H. Montgomery (Current Assignee) Round Rock Research LLC H. Manning |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch (etch stop layer) stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US20020048865A1 CLAIM 39 . A method of fabricating integrated circuitry comprising : forming a gate dielectric layer over a semiconductor substrate ; forming a conductively doped semiconductive layer over the gate dielectric layer ; forming an insulative capping layer over the semiconductive layer ; forming an etch stop layer (second etch) over the insulative capping layer ; patterning and etching the etch stop layer , the capping layer and the semiconductive layer into a plurality of transistor gate lines ; depositing an oxide layer over the substrate and the transistor gate lines to a thickness greater than that of the combined etched etch stop layer , capping layer and semiconductor layer ; chemical mechanical polishing the deposited oxide layer using the etch stop layer as an etch stop ; patterning and etching the polished oxide layer to expose material of the semiconductor substrate in at least two discrete locations proximate different of the plurality of gate lines ; depositing a local interconnect layer into electrical connection with said locations and over said plurality of gate lines ; and etching the local interconnect layer into a local interconnect line overlying at least two of said plurality of gate lines . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer protects removal of a substrate material (substrate material) by an etch process . |
US20020048865A1 CLAIM 23 . A method of forming a local interconnect comprising : forming a pair of transistor gates having respective opposing sidewalls over a semiconductor substrate ; depositing an insulating layer over the substrate and between the pair of transistor gates ; etching a first contact opening into the insulating layer to proximate the substrate between the pair of transistor gates and another contact opening through the insulating layer to proximate the substrate proximate an opposing side of one of the pair of transistor gates ; forming insulating sidewall spacers over the opposing sidewalls of the one transistor gate , the insulating layer being received between at least one of said sidewalls and one of said sidewall spacers ; and forming a local interconnect layer to overlie the one transistor gate and electrically connect with semiconductor substrate material (substrate material) between the pair of transistor gates and semiconductor substrate material proximate the opposing side of the one transistor gate . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch (etch stop layer) stop layer protects lower layers during an etching process . |
US20020048865A1 CLAIM 39 . A method of fabricating integrated circuitry comprising : forming a gate dielectric layer over a semiconductor substrate ; forming a conductively doped semiconductive layer over the gate dielectric layer ; forming an insulative capping layer over the semiconductive layer ; forming an etch stop layer (second etch) over the insulative capping layer ; patterning and etching the etch stop layer , the capping layer and the semiconductive layer into a plurality of transistor gate lines ; depositing an oxide layer over the substrate and the transistor gate lines to a thickness greater than that of the combined etched etch stop layer , capping layer and semiconductor layer ; chemical mechanical polishing the deposited oxide layer using the etch stop layer as an etch stop ; patterning and etching the polished oxide layer to expose material of the semiconductor substrate in at least two discrete locations proximate different of the plurality of gate lines ; depositing a local interconnect layer into electrical connection with said locations and over said plurality of gate lines ; and etching the local interconnect layer into a local interconnect line overlying at least two of said plurality of gate lines . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (etch stop layer) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US20020048865A1 CLAIM 39 . A method of fabricating integrated circuitry comprising : forming a gate dielectric layer over a semiconductor substrate ; forming a conductively doped semiconductive layer over the gate dielectric layer ; forming an insulative capping layer over the semiconductive layer ; forming an etch stop layer (second etch) over the insulative capping layer ; patterning and etching the etch stop layer , the capping layer and the semiconductive layer into a plurality of transistor gate lines ; depositing an oxide layer over the substrate and the transistor gate lines to a thickness greater than that of the combined etched etch stop layer , capping layer and semiconductor layer ; chemical mechanical polishing the deposited oxide layer using the etch stop layer as an etch stop ; patterning and etching the polished oxide layer to expose material of the semiconductor substrate in at least two discrete locations proximate different of the plurality of gate lines ; depositing a local interconnect layer into electrical connection with said locations and over said plurality of gate lines ; and etching the local interconnect layer into a local interconnect line overlying at least two of said plurality of gate lines . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US20020048865A1 CLAIM 9 . The method of claim 1 comprising : forming field isolation material regions and active area regions on the semiconductor substrate before the depositing ; etching a trench into the field isolation material and the insulating layer into a desired local interconnect line configuration ; and forming (anti reflective coating) a local interconnect layer of material over the substrate which at least partially fills the trench and which electrically connects with one of the active area regions . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch (etch stop layer) stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US20020048865A1 CLAIM 39 . A method of fabricating integrated circuitry comprising : forming a gate dielectric layer over a semiconductor substrate ; forming a conductively doped semiconductive layer over the gate dielectric layer ; forming an insulative capping layer over the semiconductive layer ; forming an etch stop layer (second etch) over the insulative capping layer ; patterning and etching the etch stop layer , the capping layer and the semiconductive layer into a plurality of transistor gate lines ; depositing an oxide layer over the substrate and the transistor gate lines to a thickness greater than that of the combined etched etch stop layer , capping layer and semiconductor layer ; chemical mechanical polishing the deposited oxide layer using the etch stop layer as an etch stop ; patterning and etching the polished oxide layer to expose material of the semiconductor substrate in at least two discrete locations proximate different of the plurality of gate lines ; depositing a local interconnect layer into electrical connection with said locations and over said plurality of gate lines ; and etching the local interconnect layer into a local interconnect line overlying at least two of said plurality of gate lines . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (etch stop layer) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US20020048865A1 CLAIM 39 . A method of fabricating integrated circuitry comprising : forming a gate dielectric layer over a semiconductor substrate ; forming a conductively doped semiconductive layer over the gate dielectric layer ; forming an insulative capping layer over the semiconductive layer ; forming an etch stop layer (second etch) over the insulative capping layer ; patterning and etching the etch stop layer , the capping layer and the semiconductive layer into a plurality of transistor gate lines ; depositing an oxide layer over the substrate and the transistor gate lines to a thickness greater than that of the combined etched etch stop layer , capping layer and semiconductor layer ; chemical mechanical polishing the deposited oxide layer using the etch stop layer as an etch stop ; patterning and etching the polished oxide layer to expose material of the semiconductor substrate in at least two discrete locations proximate different of the plurality of gate lines ; depositing a local interconnect layer into electrical connection with said locations and over said plurality of gate lines ; and etching the local interconnect layer into a local interconnect line overlying at least two of said plurality of gate lines . |
| US7977797B2 CLAIM 13 . An integrated circuit of claim 11 further comprising a floating gate (drain region) . |
US20020048865A1 CLAIM 35 . A method of forming a local interconnect comprising : forming at least two transistor gates over a semiconductor substrate ; depositing a local interconnect layer to overlie at least one of the transistor gates and interconnect at least one source/drain region (floating gate) of one of the gates with semiconductor substrate material proximate another of the transistor gates ; implanting conductivity enhancing impurity into the local interconnect layer in at least two implanting steps , one of the two implantings providing a peak implant location which is deeper into the layer than the other ; and diffusing conductivity enhancing impurity from the local interconnect layer into semiconductor substrate material therebeneath . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US20020048865A1 CLAIM 9 . The method of claim 1 comprising : forming field isolation material regions and active area regions on the semiconductor substrate before the depositing ; etching a trench into the field isolation material and the insulating layer into a desired local interconnect line configuration ; and forming (anti reflective coating) a local interconnect layer of material over the substrate which at least partially fills the trench and which electrically connects with one of the active area regions . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US20020030219A1 Filed: 2001-08-28 Issued: 2002-03-14 Side wall contact structure and method of forming the same (Original Assignee) NEC Corp (Current Assignee) Micron Memory Japan Ltd Masateru Ando |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (storage capacitor) layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US20020030219A1 CLAIM 5 . A method of forming a semiconductor device comprising the steps of : forming a side wall contact in a contact hole in an inter-layer insulator structure over a semiconductor substrate in a method as claimed in claim 1 ; forming a storage electrode extending within and over said contact hole ; forming a dielectric film on a surface of said storage electrode ; and forming an opposite electrode on said dielectric film thereby to form a storage capacitor (interlevel dielectric) over said inter-layer insulator structure , wherein said storage capacitor is electrically connected to said semiconductor substrate through said contact hole . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (storage capacitor) layer insulates said contact region . |
US20020030219A1 CLAIM 5 . A method of forming a semiconductor device comprising the steps of : forming a side wall contact in a contact hole in an inter-layer insulator structure over a semiconductor substrate in a method as claimed in claim 1 ; forming a storage electrode extending within and over said contact hole ; forming a dielectric film on a surface of said storage electrode ; and forming an opposite electrode on said dielectric film thereby to form a storage capacitor (interlevel dielectric) over said inter-layer insulator structure , wherein said storage capacitor is electrically connected to said semiconductor substrate through said contact hole . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (storage capacitor) layer insulates said contact region . |
US20020030219A1 CLAIM 5 . A method of forming a semiconductor device comprising the steps of : forming a side wall contact in a contact hole in an inter-layer insulator structure over a semiconductor substrate in a method as claimed in claim 1 ; forming a storage electrode extending within and over said contact hole ; forming a dielectric film on a surface of said storage electrode ; and forming an opposite electrode on said dielectric film thereby to form a storage capacitor (interlevel dielectric) over said inter-layer insulator structure , wherein said storage capacitor is electrically connected to said semiconductor substrate through said contact hole . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (storage capacitor) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US20020030219A1 CLAIM 5 . A method of forming a semiconductor device comprising the steps of : forming a side wall contact in a contact hole in an inter-layer insulator structure over a semiconductor substrate in a method as claimed in claim 1 ; forming a storage electrode extending within and over said contact hole ; forming a dielectric film on a surface of said storage electrode ; and forming an opposite electrode on said dielectric film thereby to form a storage capacitor (interlevel dielectric) over said inter-layer insulator structure , wherein said storage capacitor is electrically connected to said semiconductor substrate through said contact hole . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric (storage capacitor) layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US20020030219A1 CLAIM 5 . A method of forming a semiconductor device comprising the steps of : forming a side wall contact in a contact hole in an inter-layer insulator structure over a semiconductor substrate in a method as claimed in claim 1 ; forming a storage electrode extending within and over said contact hole ; forming a dielectric film on a surface of said storage electrode ; and forming an opposite electrode on said dielectric film thereby to form a storage capacitor (interlevel dielectric) over said inter-layer insulator structure , wherein said storage capacitor is electrically connected to said semiconductor substrate through said contact hole . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US20020030219A1 CLAIM 5 . A method of forming a semiconductor device comprising the steps of : forming a side wall contact in a contact hole in an inter-layer insulator structure over a semiconductor substrate in a method as claimed in claim 1 ; forming a storage electrode extending within and over said contact hole ; forming a dielectric film on a surface of said storage electrode ; and forming (anti reflective coating) an opposite electrode on said dielectric film thereby to form a storage capacitor over said inter-layer insulator structure , wherein said storage capacitor is electrically connected to said semiconductor substrate through said contact hole . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (storage capacitor) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US20020030219A1 CLAIM 5 . A method of forming a semiconductor device comprising the steps of : forming a side wall contact in a contact hole in an inter-layer insulator structure over a semiconductor substrate in a method as claimed in claim 1 ; forming a storage electrode extending within and over said contact hole ; forming a dielectric film on a surface of said storage electrode ; and forming an opposite electrode on said dielectric film thereby to form a storage capacitor (interlevel dielectric) over said inter-layer insulator structure , wherein said storage capacitor is electrically connected to said semiconductor substrate through said contact hole . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (storage capacitor) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US20020030219A1 CLAIM 5 . A method of forming a semiconductor device comprising the steps of : forming a side wall contact in a contact hole in an inter-layer insulator structure over a semiconductor substrate in a method as claimed in claim 1 ; forming a storage electrode extending within and over said contact hole ; forming a dielectric film on a surface of said storage electrode ; and forming an opposite electrode on said dielectric film thereby to form a storage capacitor (interlevel dielectric) over said inter-layer insulator structure , wherein said storage capacitor is electrically connected to said semiconductor substrate through said contact hole . |
| US7977797B2 CLAIM 13 . An integrated circuit of claim 11 further comprising a floating gate (second insulation) . |
US20020030219A1 CLAIM 1 . A method of forming a side wall contact on a side wall of a contact hole in an inter-layer insulator structure by an etch-back process , said method comprising the steps of : forming a first insulation film on a top insulation layer of said inter-layer insulator structure at least before forming a second insulation (floating gate) film , so that said second insulation film extends on said side wall and a bottom of said contact hole as well as on a surface of said first insulation film , wherein said first insulation film is higher in etching selectivity than said top insulation layer of said inter-layer insulator structure as well as said second insulation film is lower in etching selectivity than said top insulation layer of said inter-layer insulator structure , and said second insulation film is lower in etching selectivity than said first insulation film ; and carrying out an etch back process in over-etching to said second insulation film by use of said first insulation film as an etching stopper so as to completely remove a bottom portion of said second insulation film on said bottom of said contact hole , thereby to form a side wall contact on said side wall of said contact hole , so that said side wall contact has a top level which lies between bottom and top levels of said top insulation layer . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US20020030219A1 CLAIM 5 . A method of forming a semiconductor device comprising the steps of : forming a side wall contact in a contact hole in an inter-layer insulator structure over a semiconductor substrate in a method as claimed in claim 1 ; forming a storage electrode extending within and over said contact hole ; forming a dielectric film on a surface of said storage electrode ; and forming (anti reflective coating) an opposite electrode on said dielectric film thereby to form a storage capacitor over said inter-layer insulator structure , wherein said storage capacitor is electrically connected to said semiconductor substrate through said contact hole . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US20020119623A1 Filed: 2001-08-20 Issued: 2002-08-29 Dram device and method of manufacturing the same background of the invention (Original Assignee) Samsung Electronics Co Ltd (Current Assignee) Samsung Electronics Co Ltd Byung-Jun Park, Kyu-Hyun Lee |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (said plate) of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (bit line contacts, contact plug) layer over said first etch stop layer ; a second etch (sacrificial layer, etch stop layer) stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US20020119623A1 CLAIM 1 . A method of manufacturing DRAM device comprising : forming MOS transistors on a substrate ; forming at least bit line contact holes by depositing an interlayer insulating layer on the whole surface of said substrate on which said MOS transistors are formed and patterning the interlayer insulating layer ; forming a conductive layer for forming bit lines , a subsidiary silicon oxide layer , and a subsidiary silicon nitride layer over the whole surface of said substrate on which said bit line contacts (interlevel dielectric) are formed ; forming a bit line pattern including enlarged width portions at a portion of a peripheral/core area by patterning said conductive layer , said subsidiary silicon oxide layer , and said subsidiary silicon nitride layer ; forming a bit line interlayer insulating layer of silicon oxide material (second sub interlevel dielectric layer) over the whole surface of said substrate over which said bit line pattern is formed ; planarizing said bit line interlayer insulating layer to expose the upper surface of said subsidiary silicon nitride layer of said bit line pattern ; forming enlarged grooves exposing portions of said conductive layer of said bit line pattern forming bit lines by wet-etching said subsidiary silicon nitride layer of said bit line pattern to form first grooves and then etching isotropically said subsidiary silicon oxide layer and said bit line interlayer insulating layer around said first grooves ; forming a silicon nitride layer over the whole surface of said substrate over which said enlarged grooves are formed ; forming a silicon nitride pattern by etching anisotropically the whole surface of said silicon nitride layer to expose said bit line interlayer insulating layer , said silicon nitride pattern having silicon nitride spacers formed on side walls of said enlarged grooves positioned on said conductive layer of said bit line pattern forming said bit lines at said enlarged width portions of said bit line pattern ; forming storage node contacts , storage nodes , a dielectric layer , and plate electrodes at a cell area ; forming a wiring interlayer insulating layer on the whole surface of said substrate over which said plate (metal layer coupling area, second interlevel dielectric layer) electrodes are formed ; forming metal contact holes exposing at least said conductive layer of said bit line pattern forming said bit lines at said enlarged width portions of said bit line pattern ; and forming plugs filling said metal contact holes by depositing a conductive layer over the whole surface of said substrate over which said metal contact holes are formed . US20020119623A1 CLAIM 2 . The method of manufacturing DRAM device according to claim 1 , wherein forming storage node contacts , storage nodes , a dielectric layer , and plate electrodes at said cell area comprises : forming storage node contact holes by patterning said bit line interlayer insulating layer at the whole surface of said substrate over which said nitride pattern is formed ; forming storage node contact plug (interlevel dielectric) s by depositing a polysilicon layer over the whole surface of said substrate over which said storage node contact holes are formed ; forming storage node holes exposing said storage node contact plugs by depositing a molding oxide layer and patterning it ; forming conformally a polysilicon layer over the whole surface of said substrate over which said storage node holes are formed ; filling residual spaces of said storage node holes with a sacrificial layer (second etch) ; forming cylinder shaped storage nodes by planarizing the whole surface of said substrate over which said sacrificial layer is formed , to remove a portion of said conformal polysilicon layer formed on the upper surface of said molding layer and to divide said storage node ; removing remnants of said sacrificial layer and said molding layer to leave only said storage nodes ; forming conformally a dielectric layer over the whole surface of said substrate over which said storage nodes are left ; and forming plate electrodes by forming a polysilicon layer on said dielectric layer and patterning the polysilicon layer . US20020119623A1 CLAIM 5 . The method of manufacturing a DRAM device according to claim 1 , wherein forming at least bit line contact holes comprises : forming a first interlayer insulating layer on the whole surface of said substrate on which said MOS transistors are formed , patterning said first interlayer insulating layer to expose a portion of an active region in said cell area , forming a polysilicon layer on the whole surface of said substrate on which said portion of said active region is exposed , forming pads for storage node contacts and bit line contacts in said cell area by planarizing said polysilicon layer and said first interlayer insulating layer up to the upper surface of said transistors to divide said pads , forming bit line contact holes exposing a portion of said pads in said cell area and metal contact pad holes exposing a portion of said substrate in said peripheral/core area by depositing a second interlayer insulating layer and an etch stop layer (second etch) of silicon nitride material over the whole surface of said substrate on which said pads are to be formed and patterning them , forming metal contact pads and bit line contact plugs by filling , respectively , said metal contact pad holes and said bit line contact holes , and patterning said etch stop layer to leave only a portion thereof around said metal contact pad ; and wherein when forming metal contact holes , metal contact holes exposing said metal contact pads are formed . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer protects removal of a substrate material by an etch process (silicon oxide layer) . |
US20020119623A1 CLAIM 1 . A method of manufacturing DRAM device comprising : forming MOS transistors on a substrate ; forming at least bit line contact holes by depositing an interlayer insulating layer on the whole surface of said substrate on which said MOS transistors are formed and patterning the interlayer insulating layer ; forming a conductive layer for forming bit lines , a subsidiary silicon oxide layer (etch process) , and a subsidiary silicon nitride layer over the whole surface of said substrate on which said bit line contacts are formed ; forming a bit line pattern including enlarged width portions at a portion of a peripheral/core area by patterning said conductive layer , said subsidiary silicon oxide layer , and said subsidiary silicon nitride layer ; forming a bit line interlayer insulating layer of silicon oxide material over the whole surface of said substrate over which said bit line pattern is formed ; planarizing said bit line interlayer insulating layer to expose the upper surface of said subsidiary silicon nitride layer of said bit line pattern ; forming enlarged grooves exposing portions of said conductive layer of said bit line pattern forming bit lines by wet-etching said subsidiary silicon nitride layer of said bit line pattern to form first grooves and then etching isotropically said subsidiary silicon oxide layer and said bit line interlayer insulating layer around said first grooves ; forming a silicon nitride layer over the whole surface of said substrate over which said enlarged grooves are formed ; forming a silicon nitride pattern by etching anisotropically the whole surface of said silicon nitride layer to expose said bit line interlayer insulating layer , said silicon nitride pattern having silicon nitride spacers formed on side walls of said enlarged grooves positioned on said conductive layer of said bit line pattern forming said bit lines at said enlarged width portions of said bit line pattern ; forming storage node contacts , storage nodes , a dielectric layer , and plate electrodes at a cell area ; forming a wiring interlayer insulating layer on the whole surface of said substrate over which said plate electrodes are formed ; forming metal contact holes exposing at least said conductive layer of said bit line pattern forming said bit lines at said enlarged width portions of said bit line pattern ; and forming plugs filling said metal contact holes by depositing a conductive layer over the whole surface of said substrate over which said metal contact holes are formed . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (bit line contacts, contact plug) layer insulates said contact region . |
US20020119623A1 CLAIM 1 . A method of manufacturing DRAM device comprising : forming MOS transistors on a substrate ; forming at least bit line contact holes by depositing an interlayer insulating layer on the whole surface of said substrate on which said MOS transistors are formed and patterning the interlayer insulating layer ; forming a conductive layer for forming bit lines , a subsidiary silicon oxide layer , and a subsidiary silicon nitride layer over the whole surface of said substrate on which said bit line contacts (interlevel dielectric) are formed ; forming a bit line pattern including enlarged width portions at a portion of a peripheral/core area by patterning said conductive layer , said subsidiary silicon oxide layer , and said subsidiary silicon nitride layer ; forming a bit line interlayer insulating layer of silicon oxide material over the whole surface of said substrate over which said bit line pattern is formed ; planarizing said bit line interlayer insulating layer to expose the upper surface of said subsidiary silicon nitride layer of said bit line pattern ; forming enlarged grooves exposing portions of said conductive layer of said bit line pattern forming bit lines by wet-etching said subsidiary silicon nitride layer of said bit line pattern to form first grooves and then etching isotropically said subsidiary silicon oxide layer and said bit line interlayer insulating layer around said first grooves ; forming a silicon nitride layer over the whole surface of said substrate over which said enlarged grooves are formed ; forming a silicon nitride pattern by etching anisotropically the whole surface of said silicon nitride layer to expose said bit line interlayer insulating layer , said silicon nitride pattern having silicon nitride spacers formed on side walls of said enlarged grooves positioned on said conductive layer of said bit line pattern forming said bit lines at said enlarged width portions of said bit line pattern ; forming storage node contacts , storage nodes , a dielectric layer , and plate electrodes at a cell area ; forming a wiring interlayer insulating layer on the whole surface of said substrate over which said plate electrodes are formed ; forming metal contact holes exposing at least said conductive layer of said bit line pattern forming said bit lines at said enlarged width portions of said bit line pattern ; and forming plugs filling said metal contact holes by depositing a conductive layer over the whole surface of said substrate over which said metal contact holes are formed . US20020119623A1 CLAIM 2 . The method of manufacturing DRAM device according to claim 1 , wherein forming storage node contacts , storage nodes , a dielectric layer , and plate electrodes at said cell area comprises : forming storage node contact holes by patterning said bit line interlayer insulating layer at the whole surface of said substrate over which said nitride pattern is formed ; forming storage node contact plug (interlevel dielectric) s by depositing a polysilicon layer over the whole surface of said substrate over which said storage node contact holes are formed ; forming storage node holes exposing said storage node contact plugs by depositing a molding oxide layer and patterning it ; forming conformally a polysilicon layer over the whole surface of said substrate over which said storage node holes are formed ; filling residual spaces of said storage node holes with a sacrificial layer ; forming cylinder shaped storage nodes by planarizing the whole surface of said substrate over which said sacrificial layer is formed , to remove a portion of said conformal polysilicon layer formed on the upper surface of said molding layer and to divide said storage node ; removing remnants of said sacrificial layer and said molding layer to leave only said storage nodes ; forming conformally a dielectric layer over the whole surface of said substrate over which said storage nodes are left ; and forming plate electrodes by forming a polysilicon layer on said dielectric layer and patterning the polysilicon layer . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch (sacrificial layer, etch stop layer) stop layer protects lower layers during an etching process . |
US20020119623A1 CLAIM 2 . The method of manufacturing DRAM device according to claim 1 , wherein forming storage node contacts , storage nodes , a dielectric layer , and plate electrodes at said cell area comprises : forming storage node contact holes by patterning said bit line interlayer insulating layer at the whole surface of said substrate over which said nitride pattern is formed ; forming storage node contact plugs by depositing a polysilicon layer over the whole surface of said substrate over which said storage node contact holes are formed ; forming storage node holes exposing said storage node contact plugs by depositing a molding oxide layer and patterning it ; forming conformally a polysilicon layer over the whole surface of said substrate over which said storage node holes are formed ; filling residual spaces of said storage node holes with a sacrificial layer (second etch) ; forming cylinder shaped storage nodes by planarizing the whole surface of said substrate over which said sacrificial layer is formed , to remove a portion of said conformal polysilicon layer formed on the upper surface of said molding layer and to divide said storage node ; removing remnants of said sacrificial layer and said molding layer to leave only said storage nodes ; forming conformally a dielectric layer over the whole surface of said substrate over which said storage nodes are left ; and forming plate electrodes by forming a polysilicon layer on said dielectric layer and patterning the polysilicon layer . US20020119623A1 CLAIM 5 . The method of manufacturing a DRAM device according to claim 1 , wherein forming at least bit line contact holes comprises : forming a first interlayer insulating layer on the whole surface of said substrate on which said MOS transistors are formed , patterning said first interlayer insulating layer to expose a portion of an active region in said cell area , forming a polysilicon layer on the whole surface of said substrate on which said portion of said active region is exposed , forming pads for storage node contacts and bit line contacts in said cell area by planarizing said polysilicon layer and said first interlayer insulating layer up to the upper surface of said transistors to divide said pads , forming bit line contact holes exposing a portion of said pads in said cell area and metal contact pad holes exposing a portion of said substrate in said peripheral/core area by depositing a second interlayer insulating layer and an etch stop layer (second etch) of silicon nitride material over the whole surface of said substrate on which said pads are to be formed and patterning them , forming metal contact pads and bit line contact plugs by filling , respectively , said metal contact pad holes and said bit line contact holes , and patterning said etch stop layer to leave only a portion thereof around said metal contact pad ; and wherein when forming metal contact holes , metal contact holes exposing said metal contact pads are formed . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (bit line contacts, contact plug) layer insulates said contact region . |
US20020119623A1 CLAIM 1 . A method of manufacturing DRAM device comprising : forming MOS transistors on a substrate ; forming at least bit line contact holes by depositing an interlayer insulating layer on the whole surface of said substrate on which said MOS transistors are formed and patterning the interlayer insulating layer ; forming a conductive layer for forming bit lines , a subsidiary silicon oxide layer , and a subsidiary silicon nitride layer over the whole surface of said substrate on which said bit line contacts (interlevel dielectric) are formed ; forming a bit line pattern including enlarged width portions at a portion of a peripheral/core area by patterning said conductive layer , said subsidiary silicon oxide layer , and said subsidiary silicon nitride layer ; forming a bit line interlayer insulating layer of silicon oxide material (second sub interlevel dielectric layer) over the whole surface of said substrate over which said bit line pattern is formed ; planarizing said bit line interlayer insulating layer to expose the upper surface of said subsidiary silicon nitride layer of said bit line pattern ; forming enlarged grooves exposing portions of said conductive layer of said bit line pattern forming bit lines by wet-etching said subsidiary silicon nitride layer of said bit line pattern to form first grooves and then etching isotropically said subsidiary silicon oxide layer and said bit line interlayer insulating layer around said first grooves ; forming a silicon nitride layer over the whole surface of said substrate over which said enlarged grooves are formed ; forming a silicon nitride pattern by etching anisotropically the whole surface of said silicon nitride layer to expose said bit line interlayer insulating layer , said silicon nitride pattern having silicon nitride spacers formed on side walls of said enlarged grooves positioned on said conductive layer of said bit line pattern forming said bit lines at said enlarged width portions of said bit line pattern ; forming storage node contacts , storage nodes , a dielectric layer , and plate electrodes at a cell area ; forming a wiring interlayer insulating layer on the whole surface of said substrate over which said plate electrodes are formed ; forming metal contact holes exposing at least said conductive layer of said bit line pattern forming said bit lines at said enlarged width portions of said bit line pattern ; and forming plugs filling said metal contact holes by depositing a conductive layer over the whole surface of said substrate over which said metal contact holes are formed . US20020119623A1 CLAIM 2 . The method of manufacturing DRAM device according to claim 1 , wherein forming storage node contacts , storage nodes , a dielectric layer , and plate electrodes at said cell area comprises : forming storage node contact holes by patterning said bit line interlayer insulating layer at the whole surface of said substrate over which said nitride pattern is formed ; forming storage node contact plug (interlevel dielectric) s by depositing a polysilicon layer over the whole surface of said substrate over which said storage node contact holes are formed ; forming storage node holes exposing said storage node contact plugs by depositing a molding oxide layer and patterning it ; forming conformally a polysilicon layer over the whole surface of said substrate over which said storage node holes are formed ; filling residual spaces of said storage node holes with a sacrificial layer ; forming cylinder shaped storage nodes by planarizing the whole surface of said substrate over which said sacrificial layer is formed , to remove a portion of said conformal polysilicon layer formed on the upper surface of said molding layer and to divide said storage node ; removing remnants of said sacrificial layer and said molding layer to leave only said storage nodes ; forming conformally a dielectric layer over the whole surface of said substrate over which said storage nodes are left ; and forming plate electrodes by forming a polysilicon layer on said dielectric layer and patterning the polysilicon layer . |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area of said contact region permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area (said plate) of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
US20020119623A1 CLAIM 1 . A method of manufacturing DRAM device comprising : forming MOS transistors on a substrate ; forming at least bit line contact holes by depositing an interlayer insulating layer on the whole surface of said substrate on which said MOS transistors are formed and patterning the interlayer insulating layer ; forming a conductive layer for forming bit lines , a subsidiary silicon oxide layer , and a subsidiary silicon nitride layer over the whole surface of said substrate on which said bit line contacts are formed ; forming a bit line pattern including enlarged width portions at a portion of a peripheral/core area by patterning said conductive layer , said subsidiary silicon oxide layer , and said subsidiary silicon nitride layer ; forming a bit line interlayer insulating layer of silicon oxide material over the whole surface of said substrate over which said bit line pattern is formed ; planarizing said bit line interlayer insulating layer to expose the upper surface of said subsidiary silicon nitride layer of said bit line pattern ; forming enlarged grooves exposing portions of said conductive layer of said bit line pattern forming bit lines by wet-etching said subsidiary silicon nitride layer of said bit line pattern to form first grooves and then etching isotropically said subsidiary silicon oxide layer and said bit line interlayer insulating layer around said first grooves ; forming a silicon nitride layer over the whole surface of said substrate over which said enlarged grooves are formed ; forming a silicon nitride pattern by etching anisotropically the whole surface of said silicon nitride layer to expose said bit line interlayer insulating layer , said silicon nitride pattern having silicon nitride spacers formed on side walls of said enlarged grooves positioned on said conductive layer of said bit line pattern forming said bit lines at said enlarged width portions of said bit line pattern ; forming storage node contacts , storage nodes , a dielectric layer , and plate electrodes at a cell area ; forming a wiring interlayer insulating layer on the whole surface of said substrate over which said plate (metal layer coupling area, second interlevel dielectric layer) electrodes are formed ; forming metal contact holes exposing at least said conductive layer of said bit line pattern forming said bit lines at said enlarged width portions of said bit line pattern ; and forming plugs filling said metal contact holes by depositing a conductive layer over the whole surface of said substrate over which said metal contact holes are formed . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (bit line contacts, contact plug) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (sacrificial layer, etch stop layer) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US20020119623A1 CLAIM 1 . A method of manufacturing DRAM device comprising : forming MOS transistors on a substrate ; forming at least bit line contact holes by depositing an interlayer insulating layer on the whole surface of said substrate on which said MOS transistors are formed and patterning the interlayer insulating layer ; forming a conductive layer for forming bit lines , a subsidiary silicon oxide layer , and a subsidiary silicon nitride layer over the whole surface of said substrate on which said bit line contacts (interlevel dielectric) are formed ; forming a bit line pattern including enlarged width portions at a portion of a peripheral/core area by patterning said conductive layer , said subsidiary silicon oxide layer , and said subsidiary silicon nitride layer ; forming a bit line interlayer insulating layer of silicon oxide material (second sub interlevel dielectric layer) over the whole surface of said substrate over which said bit line pattern is formed ; planarizing said bit line interlayer insulating layer to expose the upper surface of said subsidiary silicon nitride layer of said bit line pattern ; forming enlarged grooves exposing portions of said conductive layer of said bit line pattern forming bit lines by wet-etching said subsidiary silicon nitride layer of said bit line pattern to form first grooves and then etching isotropically said subsidiary silicon oxide layer and said bit line interlayer insulating layer around said first grooves ; forming a silicon nitride layer over the whole surface of said substrate over which said enlarged grooves are formed ; forming a silicon nitride pattern by etching anisotropically the whole surface of said silicon nitride layer to expose said bit line interlayer insulating layer , said silicon nitride pattern having silicon nitride spacers formed on side walls of said enlarged grooves positioned on said conductive layer of said bit line pattern forming said bit lines at said enlarged width portions of said bit line pattern ; forming storage node contacts , storage nodes , a dielectric layer , and plate electrodes at a cell area ; forming a wiring interlayer insulating layer on the whole surface of said substrate over which said plate electrodes are formed ; forming metal contact holes exposing at least said conductive layer of said bit line pattern forming said bit lines at said enlarged width portions of said bit line pattern ; and forming plugs filling said metal contact holes by depositing a conductive layer over the whole surface of said substrate over which said metal contact holes are formed . US20020119623A1 CLAIM 2 . The method of manufacturing DRAM device according to claim 1 , wherein forming storage node contacts , storage nodes , a dielectric layer , and plate electrodes at said cell area comprises : forming storage node contact holes by patterning said bit line interlayer insulating layer at the whole surface of said substrate over which said nitride pattern is formed ; forming storage node contact plug (interlevel dielectric) s by depositing a polysilicon layer over the whole surface of said substrate over which said storage node contact holes are formed ; forming storage node holes exposing said storage node contact plugs by depositing a molding oxide layer and patterning it ; forming conformally a polysilicon layer over the whole surface of said substrate over which said storage node holes are formed ; filling residual spaces of said storage node holes with a sacrificial layer (second etch) ; forming cylinder shaped storage nodes by planarizing the whole surface of said substrate over which said sacrificial layer is formed , to remove a portion of said conformal polysilicon layer formed on the upper surface of said molding layer and to divide said storage node ; removing remnants of said sacrificial layer and said molding layer to leave only said storage nodes ; forming conformally a dielectric layer over the whole surface of said substrate over which said storage nodes are left ; and forming plate electrodes by forming a polysilicon layer on said dielectric layer and patterning the polysilicon layer . US20020119623A1 CLAIM 5 . The method of manufacturing a DRAM device according to claim 1 , wherein forming at least bit line contact holes comprises : forming a first interlayer insulating layer on the whole surface of said substrate on which said MOS transistors are formed , patterning said first interlayer insulating layer to expose a portion of an active region in said cell area , forming a polysilicon layer on the whole surface of said substrate on which said portion of said active region is exposed , forming pads for storage node contacts and bit line contacts in said cell area by planarizing said polysilicon layer and said first interlayer insulating layer up to the upper surface of said transistors to divide said pads , forming bit line contact holes exposing a portion of said pads in said cell area and metal contact pad holes exposing a portion of said substrate in said peripheral/core area by depositing a second interlayer insulating layer and an etch stop layer (second etch) of silicon nitride material over the whole surface of said substrate on which said pads are to be formed and patterning them , forming metal contact pads and bit line contact plugs by filling , respectively , said metal contact pad holes and said bit line contact holes , and patterning said etch stop layer to leave only a portion thereof around said metal contact pad ; and wherein when forming metal contact holes , metal contact holes exposing said metal contact pads are formed . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric (bit line contacts, contact plug) layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US20020119623A1 CLAIM 1 . A method of manufacturing DRAM device comprising : forming MOS transistors on a substrate ; forming at least bit line contact holes by depositing an interlayer insulating layer on the whole surface of said substrate on which said MOS transistors are formed and patterning the interlayer insulating layer ; forming a conductive layer for forming bit lines , a subsidiary silicon oxide layer , and a subsidiary silicon nitride layer over the whole surface of said substrate on which said bit line contacts (interlevel dielectric) are formed ; forming a bit line pattern including enlarged width portions at a portion of a peripheral/core area by patterning said conductive layer , said subsidiary silicon oxide layer , and said subsidiary silicon nitride layer ; forming a bit line interlayer insulating layer of silicon oxide material (second sub interlevel dielectric layer) over the whole surface of said substrate over which said bit line pattern is formed ; planarizing said bit line interlayer insulating layer to expose the upper surface of said subsidiary silicon nitride layer of said bit line pattern ; forming enlarged grooves exposing portions of said conductive layer of said bit line pattern forming bit lines by wet-etching said subsidiary silicon nitride layer of said bit line pattern to form first grooves and then etching isotropically said subsidiary silicon oxide layer and said bit line interlayer insulating layer around said first grooves ; forming a silicon nitride layer over the whole surface of said substrate over which said enlarged grooves are formed ; forming a silicon nitride pattern by etching anisotropically the whole surface of said silicon nitride layer to expose said bit line interlayer insulating layer , said silicon nitride pattern having silicon nitride spacers formed on side walls of said enlarged grooves positioned on said conductive layer of said bit line pattern forming said bit lines at said enlarged width portions of said bit line pattern ; forming storage node contacts , storage nodes , a dielectric layer , and plate electrodes at a cell area ; forming a wiring interlayer insulating layer on the whole surface of said substrate over which said plate electrodes are formed ; forming metal contact holes exposing at least said conductive layer of said bit line pattern forming said bit lines at said enlarged width portions of said bit line pattern ; and forming plugs filling said metal contact holes by depositing a conductive layer over the whole surface of said substrate over which said metal contact holes are formed . US20020119623A1 CLAIM 2 . The method of manufacturing DRAM device according to claim 1 , wherein forming storage node contacts , storage nodes , a dielectric layer , and plate electrodes at said cell area comprises : forming storage node contact holes by patterning said bit line interlayer insulating layer at the whole surface of said substrate over which said nitride pattern is formed ; forming storage node contact plug (interlevel dielectric) s by depositing a polysilicon layer over the whole surface of said substrate over which said storage node contact holes are formed ; forming storage node holes exposing said storage node contact plugs by depositing a molding oxide layer and patterning it ; forming conformally a polysilicon layer over the whole surface of said substrate over which said storage node holes are formed ; filling residual spaces of said storage node holes with a sacrificial layer ; forming cylinder shaped storage nodes by planarizing the whole surface of said substrate over which said sacrificial layer is formed , to remove a portion of said conformal polysilicon layer formed on the upper surface of said molding layer and to divide said storage node ; removing remnants of said sacrificial layer and said molding layer to leave only said storage nodes ; forming conformally a dielectric layer over the whole surface of said substrate over which said storage nodes are left ; and forming plate electrodes by forming a polysilicon layer on said dielectric layer and patterning the polysilicon layer . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US20020119623A1 CLAIM 1 . A method of manufacturing DRAM device comprising : forming MOS transistors on a substrate ; forming at least bit line contact holes by depositing an interlayer insulating layer on the whole surface of said substrate on which said MOS transistors are formed and patterning the interlayer insulating layer ; forming a conductive layer for forming bit lines , a subsidiary silicon oxide layer , and a subsidiary silicon nitride layer over the whole surface of said substrate on which said bit line contacts are formed ; forming a bit line pattern including enlarged width portions at a portion of a peripheral/core area by patterning said conductive layer , said subsidiary silicon oxide layer , and said subsidiary silicon nitride layer ; forming a bit line interlayer insulating layer of silicon oxide material over the whole surface of said substrate over which said bit line pattern is formed ; planarizing said bit line interlayer insulating layer to expose the upper surface of said subsidiary silicon nitride layer of said bit line pattern ; forming enlarged grooves exposing portions of said conductive layer of said bit line pattern forming bit lines by wet-etching said subsidiary silicon nitride layer of said bit line pattern to form first grooves and then etching isotropically said subsidiary silicon oxide layer and said bit line interlayer insulating layer around said first grooves ; forming a silicon nitride layer over the whole surface of said substrate over which said enlarged grooves are formed ; forming a silicon nitride pattern by etching anisotropically the whole surface of said silicon nitride layer to expose said bit line interlayer insulating layer , said silicon nitride pattern having silicon nitride spacers formed on side walls of said enlarged grooves positioned on said conductive layer of said bit line pattern forming said bit lines at said enlarged width portions of said bit line pattern ; forming storage node contacts , storage nodes , a dielectric layer , and plate electrodes at a cell area ; forming a wiring interlayer insulating layer on the whole surface of said substrate over which said plate electrodes are formed ; forming metal contact holes exposing at least said conductive layer of said bit line pattern forming said bit lines at said enlarged width portions of said bit line pattern ; and forming (anti reflective coating) plugs filling said metal contact holes by depositing a conductive layer over the whole surface of said substrate over which said metal contact holes are formed . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch (sacrificial layer, etch stop layer) stop layer wherein said first etch stop layer and said second etch stop layers (silicon nitride layer) have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (bit line contacts, contact plug) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (said plate) of said contact region . |
US20020119623A1 CLAIM 1 . A method of manufacturing DRAM device comprising : forming MOS transistors on a substrate ; forming at least bit line contact holes by depositing an interlayer insulating layer on the whole surface of said substrate on which said MOS transistors are formed and patterning the interlayer insulating layer ; forming a conductive layer for forming bit lines , a subsidiary silicon oxide layer , and a subsidiary silicon nitride layer (second etch stop layers) over the whole surface of said substrate on which said bit line contacts (interlevel dielectric) are formed ; forming a bit line pattern including enlarged width portions at a portion of a peripheral/core area by patterning said conductive layer , said subsidiary silicon oxide layer , and said subsidiary silicon nitride layer ; forming a bit line interlayer insulating layer of silicon oxide material (second sub interlevel dielectric layer) over the whole surface of said substrate over which said bit line pattern is formed ; planarizing said bit line interlayer insulating layer to expose the upper surface of said subsidiary silicon nitride layer of said bit line pattern ; forming enlarged grooves exposing portions of said conductive layer of said bit line pattern forming bit lines by wet-etching said subsidiary silicon nitride layer of said bit line pattern to form first grooves and then etching isotropically said subsidiary silicon oxide layer and said bit line interlayer insulating layer around said first grooves ; forming a silicon nitride layer over the whole surface of said substrate over which said enlarged grooves are formed ; forming a silicon nitride pattern by etching anisotropically the whole surface of said silicon nitride layer to expose said bit line interlayer insulating layer , said silicon nitride pattern having silicon nitride spacers formed on side walls of said enlarged grooves positioned on said conductive layer of said bit line pattern forming said bit lines at said enlarged width portions of said bit line pattern ; forming storage node contacts , storage nodes , a dielectric layer , and plate electrodes at a cell area ; forming a wiring interlayer insulating layer on the whole surface of said substrate over which said plate (metal layer coupling area, second interlevel dielectric layer) electrodes are formed ; forming metal contact holes exposing at least said conductive layer of said bit line pattern forming said bit lines at said enlarged width portions of said bit line pattern ; and forming plugs filling said metal contact holes by depositing a conductive layer over the whole surface of said substrate over which said metal contact holes are formed . US20020119623A1 CLAIM 2 . The method of manufacturing DRAM device according to claim 1 , wherein forming storage node contacts , storage nodes , a dielectric layer , and plate electrodes at said cell area comprises : forming storage node contact holes by patterning said bit line interlayer insulating layer at the whole surface of said substrate over which said nitride pattern is formed ; forming storage node contact plug (interlevel dielectric) s by depositing a polysilicon layer over the whole surface of said substrate over which said storage node contact holes are formed ; forming storage node holes exposing said storage node contact plugs by depositing a molding oxide layer and patterning it ; forming conformally a polysilicon layer over the whole surface of said substrate over which said storage node holes are formed ; filling residual spaces of said storage node holes with a sacrificial layer (second etch) ; forming cylinder shaped storage nodes by planarizing the whole surface of said substrate over which said sacrificial layer is formed , to remove a portion of said conformal polysilicon layer formed on the upper surface of said molding layer and to divide said storage node ; removing remnants of said sacrificial layer and said molding layer to leave only said storage nodes ; forming conformally a dielectric layer over the whole surface of said substrate over which said storage nodes are left ; and forming plate electrodes by forming a polysilicon layer on said dielectric layer and patterning the polysilicon layer . US20020119623A1 CLAIM 5 . The method of manufacturing a DRAM device according to claim 1 , wherein forming at least bit line contact holes comprises : forming a first interlayer insulating layer on the whole surface of said substrate on which said MOS transistors are formed , patterning said first interlayer insulating layer to expose a portion of an active region in said cell area , forming a polysilicon layer on the whole surface of said substrate on which said portion of said active region is exposed , forming pads for storage node contacts and bit line contacts in said cell area by planarizing said polysilicon layer and said first interlayer insulating layer up to the upper surface of said transistors to divide said pads , forming bit line contact holes exposing a portion of said pads in said cell area and metal contact pad holes exposing a portion of said substrate in said peripheral/core area by depositing a second interlayer insulating layer and an etch stop layer (second etch) of silicon nitride material over the whole surface of said substrate on which said pads are to be formed and patterning them , forming metal contact pads and bit line contact plugs by filling , respectively , said metal contact pad holes and said bit line contact holes , and patterning said etch stop layer to leave only a portion thereof around said metal contact pad ; and wherein when forming metal contact holes , metal contact holes exposing said metal contact pads are formed . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (bit line contacts, contact plug) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (sacrificial layer, etch stop layer) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US20020119623A1 CLAIM 1 . A method of manufacturing DRAM device comprising : forming MOS transistors on a substrate ; forming at least bit line contact holes by depositing an interlayer insulating layer on the whole surface of said substrate on which said MOS transistors are formed and patterning the interlayer insulating layer ; forming a conductive layer for forming bit lines , a subsidiary silicon oxide layer , and a subsidiary silicon nitride layer over the whole surface of said substrate on which said bit line contacts (interlevel dielectric) are formed ; forming a bit line pattern including enlarged width portions at a portion of a peripheral/core area by patterning said conductive layer , said subsidiary silicon oxide layer , and said subsidiary silicon nitride layer ; forming a bit line interlayer insulating layer of silicon oxide material (second sub interlevel dielectric layer) over the whole surface of said substrate over which said bit line pattern is formed ; planarizing said bit line interlayer insulating layer to expose the upper surface of said subsidiary silicon nitride layer of said bit line pattern ; forming enlarged grooves exposing portions of said conductive layer of said bit line pattern forming bit lines by wet-etching said subsidiary silicon nitride layer of said bit line pattern to form first grooves and then etching isotropically said subsidiary silicon oxide layer and said bit line interlayer insulating layer around said first grooves ; forming a silicon nitride layer over the whole surface of said substrate over which said enlarged grooves are formed ; forming a silicon nitride pattern by etching anisotropically the whole surface of said silicon nitride layer to expose said bit line interlayer insulating layer , said silicon nitride pattern having silicon nitride spacers formed on side walls of said enlarged grooves positioned on said conductive layer of said bit line pattern forming said bit lines at said enlarged width portions of said bit line pattern ; forming storage node contacts , storage nodes , a dielectric layer , and plate electrodes at a cell area ; forming a wiring interlayer insulating layer on the whole surface of said substrate over which said plate electrodes are formed ; forming metal contact holes exposing at least said conductive layer of said bit line pattern forming said bit lines at said enlarged width portions of said bit line pattern ; and forming plugs filling said metal contact holes by depositing a conductive layer over the whole surface of said substrate over which said metal contact holes are formed . US20020119623A1 CLAIM 2 . The method of manufacturing DRAM device according to claim 1 , wherein forming storage node contacts , storage nodes , a dielectric layer , and plate electrodes at said cell area comprises : forming storage node contact holes by patterning said bit line interlayer insulating layer at the whole surface of said substrate over which said nitride pattern is formed ; forming storage node contact plug (interlevel dielectric) s by depositing a polysilicon layer over the whole surface of said substrate over which said storage node contact holes are formed ; forming storage node holes exposing said storage node contact plugs by depositing a molding oxide layer and patterning it ; forming conformally a polysilicon layer over the whole surface of said substrate over which said storage node holes are formed ; filling residual spaces of said storage node holes with a sacrificial layer (second etch) ; forming cylinder shaped storage nodes by planarizing the whole surface of said substrate over which said sacrificial layer is formed , to remove a portion of said conformal polysilicon layer formed on the upper surface of said molding layer and to divide said storage node ; removing remnants of said sacrificial layer and said molding layer to leave only said storage nodes ; forming conformally a dielectric layer over the whole surface of said substrate over which said storage nodes are left ; and forming plate electrodes by forming a polysilicon layer on said dielectric layer and patterning the polysilicon layer . US20020119623A1 CLAIM 5 . The method of manufacturing a DRAM device according to claim 1 , wherein forming at least bit line contact holes comprises : forming a first interlayer insulating layer on the whole surface of said substrate on which said MOS transistors are formed , patterning said first interlayer insulating layer to expose a portion of an active region in said cell area , forming a polysilicon layer on the whole surface of said substrate on which said portion of said active region is exposed , forming pads for storage node contacts and bit line contacts in said cell area by planarizing said polysilicon layer and said first interlayer insulating layer up to the upper surface of said transistors to divide said pads , forming bit line contact holes exposing a portion of said pads in said cell area and metal contact pad holes exposing a portion of said substrate in said peripheral/core area by depositing a second interlayer insulating layer and an etch stop layer (second etch) of silicon nitride material over the whole surface of said substrate on which said pads are to be formed and patterning them , forming metal contact pads and bit line contact plugs by filling , respectively , said metal contact pad holes and said bit line contact holes , and patterning said etch stop layer to leave only a portion thereof around said metal contact pad ; and wherein when forming metal contact holes , metal contact holes exposing said metal contact pads are formed . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US20020119623A1 CLAIM 1 . A method of manufacturing DRAM device comprising : forming MOS transistors on a substrate ; forming at least bit line contact holes by depositing an interlayer insulating layer on the whole surface of said substrate on which said MOS transistors are formed and patterning the interlayer insulating layer ; forming a conductive layer for forming bit lines , a subsidiary silicon oxide layer , and a subsidiary silicon nitride layer over the whole surface of said substrate on which said bit line contacts are formed ; forming a bit line pattern including enlarged width portions at a portion of a peripheral/core area by patterning said conductive layer , said subsidiary silicon oxide layer , and said subsidiary silicon nitride layer ; forming a bit line interlayer insulating layer of silicon oxide material over the whole surface of said substrate over which said bit line pattern is formed ; planarizing said bit line interlayer insulating layer to expose the upper surface of said subsidiary silicon nitride layer of said bit line pattern ; forming enlarged grooves exposing portions of said conductive layer of said bit line pattern forming bit lines by wet-etching said subsidiary silicon nitride layer of said bit line pattern to form first grooves and then etching isotropically said subsidiary silicon oxide layer and said bit line interlayer insulating layer around said first grooves ; forming a silicon nitride layer over the whole surface of said substrate over which said enlarged grooves are formed ; forming a silicon nitride pattern by etching anisotropically the whole surface of said silicon nitride layer to expose said bit line interlayer insulating layer , said silicon nitride pattern having silicon nitride spacers formed on side walls of said enlarged grooves positioned on said conductive layer of said bit line pattern forming said bit lines at said enlarged width portions of said bit line pattern ; forming storage node contacts , storage nodes , a dielectric layer , and plate electrodes at a cell area ; forming a wiring interlayer insulating layer on the whole surface of said substrate over which said plate electrodes are formed ; forming metal contact holes exposing at least said conductive layer of said bit line pattern forming said bit lines at said enlarged width portions of said bit line pattern ; and forming (anti reflective coating) plugs filling said metal contact holes by depositing a conductive layer over the whole surface of said substrate over which said metal contact holes are formed . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US20020079536A1 Filed: 2001-07-10 Issued: 2002-06-27 Semiconductor device (Original Assignee) Mitsubishi Electric Corp (Current Assignee) Renesas Electronics Corp Takashi Terauchi, Yoshinori Tanaka |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (interlayer insulating film) layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US20020079536A1 CLAIM 1 . A semiconductor device having a contact hole defined between adjacent two wirings by a self-aligning manner , comprising : a contact plug formed in said contact hole ; a substrate layer conductive to the bottom face of said contact plug ; an interlayer oxide film formed on said substrate layer ; a lower insulating film formed of a nitride based insulating film so as to cover the entire surface (first sub interlevel dielectric layer) of said interlayer oxide film except for said contact hole portion ; said two wirings formed on said lower insulating film with said contact hole interposed therebetween ; an upper insulating film formed of a nitride based insulating film with the same width as said each wiring so as to cover the upper surface of said each wiring ; and sidewalls formed of a nitride based insulating film so as to cover the side faces of said each wiring and the side faces of said upper insulating film , wherein said contact hole has an enlarged portion formed in the same layer as said interlayer oxide film , which has a diameter larger than an interval defined between said two wirings . US20020079536A1 CLAIM 13 . The semiconductor device according to claim 1 , wherein said substrate layer includes a gate electrode formed on a semiconductor substrate , an interlayer insulating film (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer) for covering said gate electrode , and a plurality of pad contact plugs which extend through said interlayer insulating film so as to be conductive to a source-drain region of said semiconductor substrate , said each wiring is a bit line formed over said substrate layer ; and said contact plug is a storage node contact plug which passes between said bit lines and is thereby conductive to one of said plurality of pad contact plugs , and said semiconductor device further comprising : a bit line contact plug which extends through said lower insulating film and said interlayer oxide film to thereby bring said bit line and part of said plurality of pad contact plugs to a conducting state , and a capacitor formed on said storage node contact plug . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (interlayer insulating film) layer insulates said contact region . |
US20020079536A1 CLAIM 1 . A semiconductor device having a contact hole defined between adjacent two wirings by a self-aligning manner , comprising : a contact plug formed in said contact hole ; a substrate layer conductive to the bottom face of said contact plug ; an interlayer oxide film formed on said substrate layer ; a lower insulating film formed of a nitride based insulating film so as to cover the entire surface (first sub interlevel dielectric layer) of said interlayer oxide film except for said contact hole portion ; said two wirings formed on said lower insulating film with said contact hole interposed therebetween ; an upper insulating film formed of a nitride based insulating film with the same width as said each wiring so as to cover the upper surface of said each wiring ; and sidewalls formed of a nitride based insulating film so as to cover the side faces of said each wiring and the side faces of said upper insulating film , wherein said contact hole has an enlarged portion formed in the same layer as said interlayer oxide film , which has a diameter larger than an interval defined between said two wirings . US20020079536A1 CLAIM 13 . The semiconductor device according to claim 1 , wherein said substrate layer includes a gate electrode formed on a semiconductor substrate , an interlayer insulating film (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer) for covering said gate electrode , and a plurality of pad contact plugs which extend through said interlayer insulating film so as to be conductive to a source-drain region of said semiconductor substrate , said each wiring is a bit line formed over said substrate layer ; and said contact plug is a storage node contact plug which passes between said bit lines and is thereby conductive to one of said plurality of pad contact plugs , and said semiconductor device further comprising : a bit line contact plug which extends through said lower insulating film and said interlayer oxide film to thereby bring said bit line and part of said plurality of pad contact plugs to a conducting state , and a capacitor formed on said storage node contact plug . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (interlayer insulating film) layer insulates said contact region . |
US20020079536A1 CLAIM 13 . The semiconductor device according to claim 1 , wherein said substrate layer includes a gate electrode formed on a semiconductor substrate , an interlayer insulating film (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer) for covering said gate electrode , and a plurality of pad contact plugs which extend through said interlayer insulating film so as to be conductive to a source-drain region of said semiconductor substrate , said each wiring is a bit line formed over said substrate layer ; and said contact plug is a storage node contact plug which passes between said bit lines and is thereby conductive to one of said plurality of pad contact plugs , and said semiconductor device further comprising : a bit line contact plug which extends through said lower insulating film and said interlayer oxide film to thereby bring said bit line and part of said plurality of pad contact plugs to a conducting state , and a capacitor formed on said storage node contact plug . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (interlayer insulating film) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US20020079536A1 CLAIM 1 . A semiconductor device having a contact hole defined between adjacent two wirings by a self-aligning manner , comprising : a contact plug formed in said contact hole ; a substrate layer conductive to the bottom face of said contact plug ; an interlayer oxide film formed on said substrate layer ; a lower insulating film formed of a nitride based insulating film so as to cover the entire surface (first sub interlevel dielectric layer) of said interlayer oxide film except for said contact hole portion ; said two wirings formed on said lower insulating film with said contact hole interposed therebetween ; an upper insulating film formed of a nitride based insulating film with the same width as said each wiring so as to cover the upper surface of said each wiring ; and sidewalls formed of a nitride based insulating film so as to cover the side faces of said each wiring and the side faces of said upper insulating film , wherein said contact hole has an enlarged portion formed in the same layer as said interlayer oxide film , which has a diameter larger than an interval defined between said two wirings . US20020079536A1 CLAIM 13 . The semiconductor device according to claim 1 , wherein said substrate layer includes a gate electrode formed on a semiconductor substrate , an interlayer insulating film (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer) for covering said gate electrode , and a plurality of pad contact plugs which extend through said interlayer insulating film so as to be conductive to a source-drain region of said semiconductor substrate , said each wiring is a bit line formed over said substrate layer ; and said contact plug is a storage node contact plug which passes between said bit lines and is thereby conductive to one of said plurality of pad contact plugs , and said semiconductor device further comprising : a bit line contact plug which extends through said lower insulating film and said interlayer oxide film to thereby bring said bit line and part of said plurality of pad contact plugs to a conducting state , and a capacitor formed on said storage node contact plug . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space (said sub) in a portion of said first sub interlevel dielectric (interlayer insulating film) layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space (storage node, drain region) in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US20020079536A1 CLAIM 1 . A semiconductor device having a contact hole defined between adjacent two wirings by a self-aligning manner , comprising : a contact plug formed in said contact hole ; a substrate layer conductive to the bottom face of said contact plug ; an interlayer oxide film formed on said sub (first space) strate layer ; a lower insulating film formed of a nitride based insulating film so as to cover the entire surface (first sub interlevel dielectric layer) of said interlayer oxide film except for said contact hole portion ; said two wirings formed on said lower insulating film with said contact hole interposed therebetween ; an upper insulating film formed of a nitride based insulating film with the same width as said each wiring so as to cover the upper surface of said each wiring ; and sidewalls formed of a nitride based insulating film so as to cover the side faces of said each wiring and the side faces of said upper insulating film , wherein said contact hole has an enlarged portion formed in the same layer as said interlayer oxide film , which has a diameter larger than an interval defined between said two wirings . US20020079536A1 CLAIM 13 . The semiconductor device according to claim 1 , wherein said substrate layer includes a gate electrode formed on a semiconductor substrate , an interlayer insulating film (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer) for covering said gate electrode , and a plurality of pad contact plugs which extend through said interlayer insulating film so as to be conductive to a source-drain region (second space, floating gate) of said semiconductor substrate , said each wiring is a bit line formed over said substrate layer ; and said contact plug is a storage node (second space, floating gate) contact plug which passes between said bit lines and is thereby conductive to one of said plurality of pad contact plugs , and said semiconductor device further comprising : a bit line contact plug which extends through said lower insulating film and said interlayer oxide film to thereby bring said bit line and part of said plurality of pad contact plugs to a conducting state , and a capacitor formed on said storage node contact plug . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (interlayer insulating film) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US20020079536A1 CLAIM 1 . A semiconductor device having a contact hole defined between adjacent two wirings by a self-aligning manner , comprising : a contact plug formed in said contact hole ; a substrate layer conductive to the bottom face of said contact plug ; an interlayer oxide film formed on said substrate layer ; a lower insulating film formed of a nitride based insulating film so as to cover the entire surface (first sub interlevel dielectric layer) of said interlayer oxide film except for said contact hole portion ; said two wirings formed on said lower insulating film with said contact hole interposed therebetween ; an upper insulating film formed of a nitride based insulating film with the same width as said each wiring so as to cover the upper surface of said each wiring ; and sidewalls formed of a nitride based insulating film so as to cover the side faces of said each wiring and the side faces of said upper insulating film , wherein said contact hole has an enlarged portion formed in the same layer as said interlayer oxide film , which has a diameter larger than an interval defined between said two wirings . US20020079536A1 CLAIM 13 . The semiconductor device according to claim 1 , wherein said substrate layer includes a gate electrode formed on a semiconductor substrate , an interlayer insulating film (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer) for covering said gate electrode , and a plurality of pad contact plugs which extend through said interlayer insulating film so as to be conductive to a source-drain region of said semiconductor substrate , said each wiring is a bit line formed over said substrate layer ; and said contact plug is a storage node contact plug which passes between said bit lines and is thereby conductive to one of said plurality of pad contact plugs , and said semiconductor device further comprising : a bit line contact plug which extends through said lower insulating film and said interlayer oxide film to thereby bring said bit line and part of said plurality of pad contact plugs to a conducting state , and a capacitor formed on said storage node contact plug . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (interlayer insulating film) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US20020079536A1 CLAIM 1 . A semiconductor device having a contact hole defined between adjacent two wirings by a self-aligning manner , comprising : a contact plug formed in said contact hole ; a substrate layer conductive to the bottom face of said contact plug ; an interlayer oxide film formed on said substrate layer ; a lower insulating film formed of a nitride based insulating film so as to cover the entire surface (first sub interlevel dielectric layer) of said interlayer oxide film except for said contact hole portion ; said two wirings formed on said lower insulating film with said contact hole interposed therebetween ; an upper insulating film formed of a nitride based insulating film with the same width as said each wiring so as to cover the upper surface of said each wiring ; and sidewalls formed of a nitride based insulating film so as to cover the side faces of said each wiring and the side faces of said upper insulating film , wherein said contact hole has an enlarged portion formed in the same layer as said interlayer oxide film , which has a diameter larger than an interval defined between said two wirings . US20020079536A1 CLAIM 13 . The semiconductor device according to claim 1 , wherein said substrate layer includes a gate electrode formed on a semiconductor substrate , an interlayer insulating film (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer) for covering said gate electrode , and a plurality of pad contact plugs which extend through said interlayer insulating film so as to be conductive to a source-drain region of said semiconductor substrate , said each wiring is a bit line formed over said substrate layer ; and said contact plug is a storage node contact plug which passes between said bit lines and is thereby conductive to one of said plurality of pad contact plugs , and said semiconductor device further comprising : a bit line contact plug which extends through said lower insulating film and said interlayer oxide film to thereby bring said bit line and part of said plurality of pad contact plugs to a conducting state , and a capacitor formed on said storage node contact plug . |
| US7977797B2 CLAIM 13 . An integrated circuit of claim 11 further comprising a floating gate (storage node, drain region) . |
US20020079536A1 CLAIM 13 . The semiconductor device according to claim 1 , wherein said substrate layer includes a gate electrode formed on a semiconductor substrate , an interlayer insulating film for covering said gate electrode , and a plurality of pad contact plugs which extend through said interlayer insulating film so as to be conductive to a source-drain region (second space, floating gate) of said semiconductor substrate , said each wiring is a bit line formed over said substrate layer ; and said contact plug is a storage node (second space, floating gate) contact plug which passes between said bit lines and is thereby conductive to one of said plurality of pad contact plugs , and said semiconductor device further comprising : a bit line contact plug which extends through said lower insulating film and said interlayer oxide film to thereby bring said bit line and part of said plurality of pad contact plugs to a conducting state , and a capacitor formed on said storage node contact plug . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US20010024854A1 Filed: 2001-03-27 Issued: 2001-09-27 Semiconductor storage device and method of fabricating thereof (Original Assignee) Hideki Takeuchi; Hirohiko Izumi (Current Assignee) United Microelectronics Corp Hideki Takeuchi, Hirohiko Izumi |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (upper electrodes, like shape) of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US20010024854A1 CLAIM 1 . A semiconductor storage device , comprising : a semiconductor substrate having a device activation region defined by a device isolation structure ; an access transistor formed at said device activation region in said semiconductor substrate , and having a gate electrode and a pair of impurity diffusion layers ; a first insulating film formed over said access transistor , and having a first contact hole for exposing a portion of a surface of one of said pair of impurity diffusion layers ; a protective film formed on said first insulating film , and having a second contact hole formed on said first contact hole ; a second insulating film formed on a side wall face of said first contact hole in said first insulating film and on a side wall face of said second contact hole in said protective film ; and a memory capacitor in which a lower electrode and an upper electrode are opposed to each other and capacitive-coupled through a dielectric film , wherein said lower electrode of said memory capacitor is filled inside said first and second contact holes to be formed in an island-like shape (metal layer coupling area) on said first insulating film through said protective film so as to be electrically connected with the one of said pair of impurity diffusion layers . US20010024854A1 CLAIM 3 . A semiconductor storage device as claimed in claim 1 , wherein each of said lower and upper electrodes (metal layer coupling area) of said memory capacitor is made of a polycrystal silicon film . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch stop layer protects lower layers during an etching process (film thickness, uniform film) . |
US20010024854A1 CLAIM 21 . A method of fabricating a semiconductor storage device , said semiconductor storage device comprising : a semiconductor substrate having a device activation region defined by a device isolation structure ; an access transistor formed at said device activation region in said semiconductor substrate , and having a gate electrode and a pair of impurity diffusion layers ; and a memory capacitor in which a lower electrode and an upper electrode are opposed to each other and capacitive-coupled through a dielectric film , comprising : a first step of forming a first insulating film over said access transistor ; a second step of forming a protective film on said first insulating film ; a third step of patterning said first insulating film and said protective film by means of a photolithography so as to form first and second contact holes for exposing a portion of a surface of one of said pair of impurity diffusion layers in said first insulating film and said protective film , respectively ; a fourth step of forming a second insulating film in a uniform film thickness (etching process) or a homogeneous film thickness on side wall faces of said first and second contact holes and on a surface of said protective film ; a fifth step of etching said second insulating film with said protective film as a stopper so as to leave said second insulating film only on the side wall faces of said first and second contact holes ; a sixth step of forming a conducting film on said protective film so as to fill said first and second contact holes ; and a seventh step of patterning said conducting film so as to form said lower electrode of said memory capacitor in an island-like shape or said protective film . |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area of said contact region permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area (upper electrodes, like shape) of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
US20010024854A1 CLAIM 1 . A semiconductor storage device , comprising : a semiconductor substrate having a device activation region defined by a device isolation structure ; an access transistor formed at said device activation region in said semiconductor substrate , and having a gate electrode and a pair of impurity diffusion layers ; a first insulating film formed over said access transistor , and having a first contact hole for exposing a portion of a surface of one of said pair of impurity diffusion layers ; a protective film formed on said first insulating film , and having a second contact hole formed on said first contact hole ; a second insulating film formed on a side wall face of said first contact hole in said first insulating film and on a side wall face of said second contact hole in said protective film ; and a memory capacitor in which a lower electrode and an upper electrode are opposed to each other and capacitive-coupled through a dielectric film , wherein said lower electrode of said memory capacitor is filled inside said first and second contact holes to be formed in an island-like shape (metal layer coupling area) on said first insulating film through said protective film so as to be electrically connected with the one of said pair of impurity diffusion layers . US20010024854A1 CLAIM 3 . A semiconductor storage device as claimed in claim 1 , wherein each of said lower and upper electrodes (metal layer coupling area) of said memory capacitor is made of a polycrystal silicon film . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (upper electrodes, like shape) of said contact region . |
US20010024854A1 CLAIM 1 . A semiconductor storage device , comprising : a semiconductor substrate having a device activation region defined by a device isolation structure ; an access transistor formed at said device activation region in said semiconductor substrate , and having a gate electrode and a pair of impurity diffusion layers ; a first insulating film formed over said access transistor , and having a first contact hole for exposing a portion of a surface of one of said pair of impurity diffusion layers ; a protective film formed on said first insulating film , and having a second contact hole formed on said first contact hole ; a second insulating film formed on a side wall face of said first contact hole in said first insulating film and on a side wall face of said second contact hole in said protective film ; and a memory capacitor in which a lower electrode and an upper electrode are opposed to each other and capacitive-coupled through a dielectric film , wherein said lower electrode of said memory capacitor is filled inside said first and second contact holes to be formed in an island-like shape (metal layer coupling area) on said first insulating film through said protective film so as to be electrically connected with the one of said pair of impurity diffusion layers . US20010024854A1 CLAIM 3 . A semiconductor storage device as claimed in claim 1 , wherein each of said lower and upper electrodes (metal layer coupling area) of said memory capacitor is made of a polycrystal silicon film . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US20020008323A1 Filed: 2000-12-14 Issued: 2002-01-24 Semiconductor device with dual damascene wiring (Original Assignee) Fujitsu Ltd (Current Assignee) TRINITY SEMICONDUCTOR RESEARCH GK Kenichi Watanabe, Daisuke Komada, Fumihiko Shimpuku |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region (second contact) coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (cross sectional shape) of said contact region ; and a multiple etch (hard mask, etch rates, first etch) stop insulation layer (hard mask, etch rates, first etch) coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch (hard mask, etch rates, first etch) stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch (hard mask, etch rates, first etch) stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US20020008323A1 CLAIM 5 . A semiconductor device according to claim 3 , wherein the second kind of the insulating layer is capable of functioning as an etch stopper while the first kind of the insulating layer is etched , and said contact hole has a substantially same cross sectional shape (metal layer coupling area) from a bottom surface of the second kind of the insulating layer to the surface of the conductive region . US20020008323A1 CLAIM 8 . A method of manufacturing a semiconductor device , comprising the steps of : forming an insulating etch stopper film on an underlie having a conductive region in a surface layer of the underlie ; forming an interlayer insulating film on the insulating etch stopper film , the interlayer insulating film including a first kind of an insulating layer and a second kind of an insulating layer formed under the first kind of the insulating layer , the second kind of the insulating layer having etching characteristics different from the first kind of the insulating layer ; forming a first contact hole extending from a surface of the interlayer insulating film to the insulating etch stopper film through the interlayer insulating film ; embedding an organic protective filler in the contact hole to a height lower than a surface of the second kind of the insulating layer ; forming a wiring trench in the first kind of the insulating layer of the interlayer insulating film , the wiring trench having a first depth from the surface of the interlayer insulating film and overlapping or including the first contact hole as viewed in plan ; removing the protective filler ; removing the insulating etching stopper film exposed in the first contact hole to form a second contact (contact region) hole continuous with the first contact hole and reaching the underlie having the conductive region ; and forming a dual damascene wiring layer embedded in the wiring trench and the first and second contact holes . US20020008323A1 CLAIM 10 . A method of manufacturing a semiconductor device according to claim 9 , wherein the second kind of the insulating layer has an etch rate lower than etch rates (second etch, first etch, multiple etch stop insulation layer, first etch stop layer, etch process, multiple etch, etching process, second etch stop layers) of the first and third kinds of the insulating layers . US20020008323A1 CLAIM 12 . A method of manufacturing a semiconductor device , comprising : a step of forming an insulating etch stopper film on an underlie having a conductive region in a surface layer of the underlie ; a step of forming an interlayer insulating film on the insulating etch stopper film , the interlayer insulating film including a first kind of an insulating layer and a second kind of an insulating layer formed under the first kind of the insulating film , the second kind of the insulating layer having etching characteristics different from the first kind of the insulating layer ; a first etch (second etch, first etch, multiple etch stop insulation layer, first etch stop layer, etch process, multiple etch, etching process, second etch stop layers) ing step of forming a first contact hole extending from a surface of the interlayer insulating film to the second kind of the insulating layer through the first kind of the insulating layer by etching ; a second etching step of forming a wiring trench in the first kind of the insulating layer of the interlayer insulating film and removing a remaining interlayer insulating film under the first contact hole by etching , the wiring trench having a first depth from a surface of the interlayer insulating film and overlapping or including the first contact hole as viewed in plan ; a step of removing the insulating etch stopper film exposed in the first contact hole to form a second contact hole continuous with the first contact hole and reaching the underlie having the conductive region ; and a step of forming a dual damascene wiring layer embedded in the wiring trench and in the first and second contact holes . US20020008323A1 CLAIM 15 . A method of manufacturing a semiconductor device according to claim 12 , further composing the step of forming a hard mask (second etch, first etch, multiple etch stop insulation layer, first etch stop layer, etch process, multiple etch, etching process, second etch stop layers) layer on the interlayer insulating film , wherein said first etching step includes a step of forming a first resist mask on the hard mask layer , and said second etching step includes a step of forming a second resist mask on the hard mask layer and etching the hard mask layer and a step of removing thereafter the second resist mask and etching the interlayer insulating film by using the hard mask layer as an etching mask . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch (hard mask, etch rates, first etch) stop layer protects removal of a substrate material by an etch process (hard mask, etch rates, first etch) . |
US20020008323A1 CLAIM 10 . A method of manufacturing a semiconductor device according to claim 9 , wherein the second kind of the insulating layer has an etch rate lower than etch rates (second etch, first etch, multiple etch stop insulation layer, first etch stop layer, etch process, multiple etch, etching process, second etch stop layers) of the first and third kinds of the insulating layers . US20020008323A1 CLAIM 12 . A method of manufacturing a semiconductor device , comprising : a step of forming an insulating etch stopper film on an underlie having a conductive region in a surface layer of the underlie ; a step of forming an interlayer insulating film on the insulating etch stopper film , the interlayer insulating film including a first kind of an insulating layer and a second kind of an insulating layer formed under the first kind of the insulating film , the second kind of the insulating layer having etching characteristics different from the first kind of the insulating layer ; a first etch (second etch, first etch, multiple etch stop insulation layer, first etch stop layer, etch process, multiple etch, etching process, second etch stop layers) ing step of forming a first contact hole extending from a surface of the interlayer insulating film to the second kind of the insulating layer through the first kind of the insulating layer by etching ; a second etching step of forming a wiring trench in the first kind of the insulating layer of the interlayer insulating film and removing a remaining interlayer insulating film under the first contact hole by etching , the wiring trench having a first depth from a surface of the interlayer insulating film and overlapping or including the first contact hole as viewed in plan ; a step of removing the insulating etch stopper film exposed in the first contact hole to form a second contact hole continuous with the first contact hole and reaching the underlie having the conductive region ; and a step of forming a dual damascene wiring layer embedded in the wiring trench and in the first and second contact holes . US20020008323A1 CLAIM 15 . A method of manufacturing a semiconductor device according to claim 12 , further composing the step of forming a hard mask (second etch, first etch, multiple etch stop insulation layer, first etch stop layer, etch process, multiple etch, etching process, second etch stop layers) layer on the interlayer insulating film , wherein said first etching step includes a step of forming a first resist mask on the hard mask layer , and said second etching step includes a step of forming a second resist mask on the hard mask layer and etching the hard mask layer and a step of removing thereafter the second resist mask and etching the interlayer insulating film by using the hard mask layer as an etching mask . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric layer insulates said contact region (second contact) . |
US20020008323A1 CLAIM 8 . A method of manufacturing a semiconductor device , comprising the steps of : forming an insulating etch stopper film on an underlie having a conductive region in a surface layer of the underlie ; forming an interlayer insulating film on the insulating etch stopper film , the interlayer insulating film including a first kind of an insulating layer and a second kind of an insulating layer formed under the first kind of the insulating layer , the second kind of the insulating layer having etching characteristics different from the first kind of the insulating layer ; forming a first contact hole extending from a surface of the interlayer insulating film to the insulating etch stopper film through the interlayer insulating film ; embedding an organic protective filler in the contact hole to a height lower than a surface of the second kind of the insulating layer ; forming a wiring trench in the first kind of the insulating layer of the interlayer insulating film , the wiring trench having a first depth from the surface of the interlayer insulating film and overlapping or including the first contact hole as viewed in plan ; removing the protective filler ; removing the insulating etching stopper film exposed in the first contact hole to form a second contact (contact region) hole continuous with the first contact hole and reaching the underlie having the conductive region ; and forming a dual damascene wiring layer embedded in the wiring trench and the first and second contact holes . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch (hard mask, etch rates, first etch) stop layer protects lower layers during an etching process (hard mask, etch rates, first etch) . |
US20020008323A1 CLAIM 10 . A method of manufacturing a semiconductor device according to claim 9 , wherein the second kind of the insulating layer has an etch rate lower than etch rates (second etch, first etch, multiple etch stop insulation layer, first etch stop layer, etch process, multiple etch, etching process, second etch stop layers) of the first and third kinds of the insulating layers . US20020008323A1 CLAIM 12 . A method of manufacturing a semiconductor device , comprising : a step of forming an insulating etch stopper film on an underlie having a conductive region in a surface layer of the underlie ; a step of forming an interlayer insulating film on the insulating etch stopper film , the interlayer insulating film including a first kind of an insulating layer and a second kind of an insulating layer formed under the first kind of the insulating film , the second kind of the insulating layer having etching characteristics different from the first kind of the insulating layer ; a first etch (second etch, first etch, multiple etch stop insulation layer, first etch stop layer, etch process, multiple etch, etching process, second etch stop layers) ing step of forming a first contact hole extending from a surface of the interlayer insulating film to the second kind of the insulating layer through the first kind of the insulating layer by etching ; a second etching step of forming a wiring trench in the first kind of the insulating layer of the interlayer insulating film and removing a remaining interlayer insulating film under the first contact hole by etching , the wiring trench having a first depth from a surface of the interlayer insulating film and overlapping or including the first contact hole as viewed in plan ; a step of removing the insulating etch stopper film exposed in the first contact hole to form a second contact hole continuous with the first contact hole and reaching the underlie having the conductive region ; and a step of forming a dual damascene wiring layer embedded in the wiring trench and in the first and second contact holes . US20020008323A1 CLAIM 15 . A method of manufacturing a semiconductor device according to claim 12 , further composing the step of forming a hard mask (second etch, first etch, multiple etch stop insulation layer, first etch stop layer, etch process, multiple etch, etching process, second etch stop layers) layer on the interlayer insulating film , wherein said first etching step includes a step of forming a first resist mask on the hard mask layer , and said second etching step includes a step of forming a second resist mask on the hard mask layer and etching the hard mask layer and a step of removing thereafter the second resist mask and etching the interlayer insulating film by using the hard mask layer as an etching mask . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric layer insulates said contact region (second contact) . |
US20020008323A1 CLAIM 8 . A method of manufacturing a semiconductor device , comprising the steps of : forming an insulating etch stopper film on an underlie having a conductive region in a surface layer of the underlie ; forming an interlayer insulating film on the insulating etch stopper film , the interlayer insulating film including a first kind of an insulating layer and a second kind of an insulating layer formed under the first kind of the insulating layer , the second kind of the insulating layer having etching characteristics different from the first kind of the insulating layer ; forming a first contact hole extending from a surface of the interlayer insulating film to the insulating etch stopper film through the interlayer insulating film ; embedding an organic protective filler in the contact hole to a height lower than a surface of the second kind of the insulating layer ; forming a wiring trench in the first kind of the insulating layer of the interlayer insulating film , the wiring trench having a first depth from the surface of the interlayer insulating film and overlapping or including the first contact hole as viewed in plan ; removing the protective filler ; removing the insulating etching stopper film exposed in the first contact hole to form a second contact (contact region) hole continuous with the first contact hole and reaching the underlie having the conductive region ; and forming a dual damascene wiring layer embedded in the wiring trench and the first and second contact holes . |
| US7977797B2 CLAIM 6 . An integrated circuit of claim 1 wherein said spacer region insulates said contact region (second contact) . |
US20020008323A1 CLAIM 8 . A method of manufacturing a semiconductor device , comprising the steps of : forming an insulating etch stopper film on an underlie having a conductive region in a surface layer of the underlie ; forming an interlayer insulating film on the insulating etch stopper film , the interlayer insulating film including a first kind of an insulating layer and a second kind of an insulating layer formed under the first kind of the insulating layer , the second kind of the insulating layer having etching characteristics different from the first kind of the insulating layer ; forming a first contact hole extending from a surface of the interlayer insulating film to the insulating etch stopper film through the interlayer insulating film ; embedding an organic protective filler in the contact hole to a height lower than a surface of the second kind of the insulating layer ; forming a wiring trench in the first kind of the insulating layer of the interlayer insulating film , the wiring trench having a first depth from the surface of the interlayer insulating film and overlapping or including the first contact hole as viewed in plan ; removing the protective filler ; removing the insulating etching stopper film exposed in the first contact hole to form a second contact (contact region) hole continuous with the first contact hole and reaching the underlie having the conductive region ; and forming a dual damascene wiring layer embedded in the wiring trench and the first and second contact holes . |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area of said contact region (second contact) permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area (cross sectional shape) of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
US20020008323A1 CLAIM 5 . A semiconductor device according to claim 3 , wherein the second kind of the insulating layer is capable of functioning as an etch stopper while the first kind of the insulating layer is etched , and said contact hole has a substantially same cross sectional shape (metal layer coupling area) from a bottom surface of the second kind of the insulating layer to the surface of the conductive region . US20020008323A1 CLAIM 8 . A method of manufacturing a semiconductor device , comprising the steps of : forming an insulating etch stopper film on an underlie having a conductive region in a surface layer of the underlie ; forming an interlayer insulating film on the insulating etch stopper film , the interlayer insulating film including a first kind of an insulating layer and a second kind of an insulating layer formed under the first kind of the insulating layer , the second kind of the insulating layer having etching characteristics different from the first kind of the insulating layer ; forming a first contact hole extending from a surface of the interlayer insulating film to the insulating etch stopper film through the interlayer insulating film ; embedding an organic protective filler in the contact hole to a height lower than a surface of the second kind of the insulating layer ; forming a wiring trench in the first kind of the insulating layer of the interlayer insulating film , the wiring trench having a first depth from the surface of the interlayer insulating film and overlapping or including the first contact hole as viewed in plan ; removing the protective filler ; removing the insulating etching stopper film exposed in the first contact hole to form a second contact (contact region) hole continuous with the first contact hole and reaching the underlie having the conductive region ; and forming a dual damascene wiring layer embedded in the wiring trench and the first and second contact holes . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch (hard mask, etch rates, first etch) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (hard mask, etch rates, first etch) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US20020008323A1 CLAIM 10 . A method of manufacturing a semiconductor device according to claim 9 , wherein the second kind of the insulating layer has an etch rate lower than etch rates (second etch, first etch, multiple etch stop insulation layer, first etch stop layer, etch process, multiple etch, etching process, second etch stop layers) of the first and third kinds of the insulating layers . US20020008323A1 CLAIM 12 . A method of manufacturing a semiconductor device , comprising : a step of forming an insulating etch stopper film on an underlie having a conductive region in a surface layer of the underlie ; a step of forming an interlayer insulating film on the insulating etch stopper film , the interlayer insulating film including a first kind of an insulating layer and a second kind of an insulating layer formed under the first kind of the insulating film , the second kind of the insulating layer having etching characteristics different from the first kind of the insulating layer ; a first etch (second etch, first etch, multiple etch stop insulation layer, first etch stop layer, etch process, multiple etch, etching process, second etch stop layers) ing step of forming a first contact hole extending from a surface of the interlayer insulating film to the second kind of the insulating layer through the first kind of the insulating layer by etching ; a second etching step of forming a wiring trench in the first kind of the insulating layer of the interlayer insulating film and removing a remaining interlayer insulating film under the first contact hole by etching , the wiring trench having a first depth from a surface of the interlayer insulating film and overlapping or including the first contact hole as viewed in plan ; a step of removing the insulating etch stopper film exposed in the first contact hole to form a second contact hole continuous with the first contact hole and reaching the underlie having the conductive region ; and a step of forming a dual damascene wiring layer embedded in the wiring trench and in the first and second contact holes . US20020008323A1 CLAIM 15 . A method of manufacturing a semiconductor device according to claim 12 , further composing the step of forming a hard mask (second etch, first etch, multiple etch stop insulation layer, first etch stop layer, etch process, multiple etch, etching process, second etch stop layers) layer on the interlayer insulating film , wherein said first etching step includes a step of forming a first resist mask on the hard mask layer , and said second etching step includes a step of forming a second resist mask on the hard mask layer and etching the hard mask layer and a step of removing thereafter the second resist mask and etching the interlayer insulating film by using the hard mask layer as an etching mask . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric layer for said contact region (second contact) is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US20020008323A1 CLAIM 8 . A method of manufacturing a semiconductor device , comprising the steps of : forming an insulating etch stopper film on an underlie having a conductive region in a surface layer of the underlie ; forming an interlayer insulating film on the insulating etch stopper film , the interlayer insulating film including a first kind of an insulating layer and a second kind of an insulating layer formed under the first kind of the insulating layer , the second kind of the insulating layer having etching characteristics different from the first kind of the insulating layer ; forming a first contact hole extending from a surface of the interlayer insulating film to the insulating etch stopper film through the interlayer insulating film ; embedding an organic protective filler in the contact hole to a height lower than a surface of the second kind of the insulating layer ; forming a wiring trench in the first kind of the insulating layer of the interlayer insulating film , the wiring trench having a first depth from the surface of the interlayer insulating film and overlapping or including the first contact hole as viewed in plan ; removing the protective filler ; removing the insulating etching stopper film exposed in the first contact hole to form a second contact (contact region) hole continuous with the first contact hole and reaching the underlie having the conductive region ; and forming a dual damascene wiring layer embedded in the wiring trench and the first and second contact holes . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US20020008323A1 CLAIM 8 . A method of manufacturing a semiconductor device , comprising the steps of : forming an insulating etch stopper film on an underlie having a conductive region in a surface layer of the underlie ; forming an interlayer insulating film on the insulating etch stopper film , the interlayer insulating film including a first kind of an insulating layer and a second kind of an insulating layer formed under the first kind of the insulating layer , the second kind of the insulating layer having etching characteristics different from the first kind of the insulating layer ; forming a first contact hole extending from a surface of the interlayer insulating film to the insulating etch stopper film through the interlayer insulating film ; embedding an organic protective filler in the contact hole to a height lower than a surface of the second kind of the insulating layer ; forming a wiring trench in the first kind of the insulating layer of the interlayer insulating film , the wiring trench having a first depth from the surface of the interlayer insulating film and overlapping or including the first contact hole as viewed in plan ; removing the protective filler ; removing the insulating etching stopper film exposed in the first contact hole to form a second contact hole continuous with the first contact hole and reaching the underlie having the conductive region ; and forming (anti reflective coating) a dual damascene wiring layer embedded in the wiring trench and the first and second contact holes . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch (hard mask, etch rates, first etch) stop insulation layer (hard mask, etch rates, first etch) comprising a first etch (hard mask, etch rates, first etch) stop layer and a second etch (hard mask, etch rates, first etch) stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region (second contact) and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (cross sectional shape) of said contact region . |
US20020008323A1 CLAIM 5 . A semiconductor device according to claim 3 , wherein the second kind of the insulating layer is capable of functioning as an etch stopper while the first kind of the insulating layer is etched , and said contact hole has a substantially same cross sectional shape (metal layer coupling area) from a bottom surface of the second kind of the insulating layer to the surface of the conductive region . US20020008323A1 CLAIM 8 . A method of manufacturing a semiconductor device , comprising the steps of : forming an insulating etch stopper film on an underlie having a conductive region in a surface layer of the underlie ; forming an interlayer insulating film on the insulating etch stopper film , the interlayer insulating film including a first kind of an insulating layer and a second kind of an insulating layer formed under the first kind of the insulating layer , the second kind of the insulating layer having etching characteristics different from the first kind of the insulating layer ; forming a first contact hole extending from a surface of the interlayer insulating film to the insulating etch stopper film through the interlayer insulating film ; embedding an organic protective filler in the contact hole to a height lower than a surface of the second kind of the insulating layer ; forming a wiring trench in the first kind of the insulating layer of the interlayer insulating film , the wiring trench having a first depth from the surface of the interlayer insulating film and overlapping or including the first contact hole as viewed in plan ; removing the protective filler ; removing the insulating etching stopper film exposed in the first contact hole to form a second contact (contact region) hole continuous with the first contact hole and reaching the underlie having the conductive region ; and forming a dual damascene wiring layer embedded in the wiring trench and the first and second contact holes . US20020008323A1 CLAIM 10 . A method of manufacturing a semiconductor device according to claim 9 , wherein the second kind of the insulating layer has an etch rate lower than etch rates (second etch, first etch, multiple etch stop insulation layer, first etch stop layer, etch process, multiple etch, etching process, second etch stop layers) of the first and third kinds of the insulating layers . US20020008323A1 CLAIM 12 . A method of manufacturing a semiconductor device , comprising : a step of forming an insulating etch stopper film on an underlie having a conductive region in a surface layer of the underlie ; a step of forming an interlayer insulating film on the insulating etch stopper film , the interlayer insulating film including a first kind of an insulating layer and a second kind of an insulating layer formed under the first kind of the insulating film , the second kind of the insulating layer having etching characteristics different from the first kind of the insulating layer ; a first etch (second etch, first etch, multiple etch stop insulation layer, first etch stop layer, etch process, multiple etch, etching process, second etch stop layers) ing step of forming a first contact hole extending from a surface of the interlayer insulating film to the second kind of the insulating layer through the first kind of the insulating layer by etching ; a second etching step of forming a wiring trench in the first kind of the insulating layer of the interlayer insulating film and removing a remaining interlayer insulating film under the first contact hole by etching , the wiring trench having a first depth from a surface of the interlayer insulating film and overlapping or including the first contact hole as viewed in plan ; a step of removing the insulating etch stopper film exposed in the first contact hole to form a second contact hole continuous with the first contact hole and reaching the underlie having the conductive region ; and a step of forming a dual damascene wiring layer embedded in the wiring trench and in the first and second contact holes . US20020008323A1 CLAIM 15 . A method of manufacturing a semiconductor device according to claim 12 , further composing the step of forming a hard mask (second etch, first etch, multiple etch stop insulation layer, first etch stop layer, etch process, multiple etch, etching process, second etch stop layers) layer on the interlayer insulating film , wherein said first etching step includes a step of forming a first resist mask on the hard mask layer , and said second etching step includes a step of forming a second resist mask on the hard mask layer and etching the hard mask layer and a step of removing thereafter the second resist mask and etching the interlayer insulating film by using the hard mask layer as an etching mask . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch (hard mask, etch rates, first etch) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (hard mask, etch rates, first etch) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US20020008323A1 CLAIM 10 . A method of manufacturing a semiconductor device according to claim 9 , wherein the second kind of the insulating layer has an etch rate lower than etch rates (second etch, first etch, multiple etch stop insulation layer, first etch stop layer, etch process, multiple etch, etching process, second etch stop layers) of the first and third kinds of the insulating layers . US20020008323A1 CLAIM 12 . A method of manufacturing a semiconductor device , comprising : a step of forming an insulating etch stopper film on an underlie having a conductive region in a surface layer of the underlie ; a step of forming an interlayer insulating film on the insulating etch stopper film , the interlayer insulating film including a first kind of an insulating layer and a second kind of an insulating layer formed under the first kind of the insulating film , the second kind of the insulating layer having etching characteristics different from the first kind of the insulating layer ; a first etch (second etch, first etch, multiple etch stop insulation layer, first etch stop layer, etch process, multiple etch, etching process, second etch stop layers) ing step of forming a first contact hole extending from a surface of the interlayer insulating film to the second kind of the insulating layer through the first kind of the insulating layer by etching ; a second etching step of forming a wiring trench in the first kind of the insulating layer of the interlayer insulating film and removing a remaining interlayer insulating film under the first contact hole by etching , the wiring trench having a first depth from a surface of the interlayer insulating film and overlapping or including the first contact hole as viewed in plan ; a step of removing the insulating etch stopper film exposed in the first contact hole to form a second contact hole continuous with the first contact hole and reaching the underlie having the conductive region ; and a step of forming a dual damascene wiring layer embedded in the wiring trench and in the first and second contact holes . US20020008323A1 CLAIM 15 . A method of manufacturing a semiconductor device according to claim 12 , further composing the step of forming a hard mask (second etch, first etch, multiple etch stop insulation layer, first etch stop layer, etch process, multiple etch, etching process, second etch stop layers) layer on the interlayer insulating film , wherein said first etching step includes a step of forming a first resist mask on the hard mask layer , and said second etching step includes a step of forming a second resist mask on the hard mask layer and etching the hard mask layer and a step of removing thereafter the second resist mask and etching the interlayer insulating film by using the hard mask layer as an etching mask . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US20020008323A1 CLAIM 8 . A method of manufacturing a semiconductor device , comprising the steps of : forming an insulating etch stopper film on an underlie having a conductive region in a surface layer of the underlie ; forming an interlayer insulating film on the insulating etch stopper film , the interlayer insulating film including a first kind of an insulating layer and a second kind of an insulating layer formed under the first kind of the insulating layer , the second kind of the insulating layer having etching characteristics different from the first kind of the insulating layer ; forming a first contact hole extending from a surface of the interlayer insulating film to the insulating etch stopper film through the interlayer insulating film ; embedding an organic protective filler in the contact hole to a height lower than a surface of the second kind of the insulating layer ; forming a wiring trench in the first kind of the insulating layer of the interlayer insulating film , the wiring trench having a first depth from the surface of the interlayer insulating film and overlapping or including the first contact hole as viewed in plan ; removing the protective filler ; removing the insulating etching stopper film exposed in the first contact hole to form a second contact hole continuous with the first contact hole and reaching the underlie having the conductive region ; and forming (anti reflective coating) a dual damascene wiring layer embedded in the wiring trench and the first and second contact holes . |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region (second contact) is a first range of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US20020008323A1 CLAIM 8 . A method of manufacturing a semiconductor device , comprising the steps of : forming an insulating etch stopper film on an underlie having a conductive region in a surface layer of the underlie ; forming an interlayer insulating film on the insulating etch stopper film , the interlayer insulating film including a first kind of an insulating layer and a second kind of an insulating layer formed under the first kind of the insulating layer , the second kind of the insulating layer having etching characteristics different from the first kind of the insulating layer ; forming a first contact hole extending from a surface of the interlayer insulating film to the insulating etch stopper film through the interlayer insulating film ; embedding an organic protective filler in the contact hole to a height lower than a surface of the second kind of the insulating layer ; forming a wiring trench in the first kind of the insulating layer of the interlayer insulating film , the wiring trench having a first depth from the surface of the interlayer insulating film and overlapping or including the first contact hole as viewed in plan ; removing the protective filler ; removing the insulating etching stopper film exposed in the first contact hole to form a second contact (contact region) hole continuous with the first contact hole and reaching the underlie having the conductive region ; and forming a dual damascene wiring layer embedded in the wiring trench and the first and second contact holes . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | KR20020033881A Filed: 2000-10-30 Issued: 2002-05-08 접촉창을 갖는 반도체 장치 및 그 제조 방법 (Original Assignee) 윤종용; 삼성전자 주식회사 전정식, 김재웅 |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch (부산물) stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
KR20020033881A CLAIM 9 제 1 항에 있어서 , 상기 이방성 식각 단계는 , 상기 이방성 식각시 발생하는 폴리머 성분의 부산물 (second etch) 은 상기 트렌치의 측벽에 100 내지 500 Å의 두께로 형성되도록 하고 , 상기 폴리머는 상기 등방성 식각에 대한 식각 억제막으로 사용되는 것을 특징으로 하는 반도체 장치의 제조 방법 . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch (부산물) stop layer protects lower layers during an etching process . |
KR20020033881A CLAIM 9 제 1 항에 있어서 , 상기 이방성 식각 단계는 , 상기 이방성 식각시 발생하는 폴리머 성분의 부산물 (second etch) 은 상기 트렌치의 측벽에 100 내지 500 Å의 두께로 형성되도록 하고 , 상기 폴리머는 상기 등방성 식각에 대한 식각 억제막으로 사용되는 것을 특징으로 하는 반도체 장치의 제조 방법 . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Å thick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Å thick , said second etch (부산물) stop layer is in a range of about 300 to 800 Å thick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Å thick . |
KR20020033881A CLAIM 9 제 1 항에 있어서 , 상기 이방성 식각 단계는 , 상기 이방성 식각시 발생하는 폴리머 성분의 부산물 (second etch) 은 상기 트렌치의 측벽에 100 내지 500 Å의 두께로 형성되도록 하고 , 상기 폴리머는 상기 등방성 식각에 대한 식각 억제막으로 사용되는 것을 특징으로 하는 반도체 장치의 제조 방법 . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch (부산물) stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer (연막의) , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
KR20020033881A CLAIM 1 반도체 기판 상에 하부 절연막을 형성하는 단계 ; 상기 하부 절연막 상에 상부 절연막을 형성하는 단계 ; 상기 상부 절연막과 상기 하부 절연막을 이방성 식각하여 , 상기 상부 절연막을 관통하고 상기 하부 절연막의 (second interlevel dielectric layer) 두께와 상기 상부 절연막 두께의 합 보다작은 깊이를 같는 트렌치를 형성하는 단계 및 상기 트렌치에 의해 노출된 하부 절연막을 등방성 식각하여 , 하부의 폭이 상부의 폭 보다 큰 접촉창을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 장치의 제조 방법 . KR20020033881A CLAIM 9 제 1 항에 있어서 , 상기 이방성 식각 단계는 , 상기 이방성 식각시 발생하는 폴리머 성분의 부산물 (second etch) 은 상기 트렌치의 측벽에 100 내지 500 Å의 두께로 형성되도록 하고 , 상기 폴리머는 상기 등방성 식각에 대한 식각 억제막으로 사용되는 것을 특징으로 하는 반도체 장치의 제조 방법 . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Å thick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Å thick , said second etch (부산물) stop layer is in a range of about 300 to 800 Å thick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Å thick . |
KR20020033881A CLAIM 9 제 1 항에 있어서 , 상기 이방성 식각 단계는 , 상기 이방성 식각시 발생하는 폴리머 성분의 부산물 (second etch) 은 상기 트렌치의 측벽에 100 내지 500 Å의 두께로 형성되도록 하고 , 상기 폴리머는 상기 등방성 식각에 대한 식각 억제막으로 사용되는 것을 특징으로 하는 반도체 장치의 제조 방법 . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US6369446B1 Filed: 1999-11-15 Issued: 2002-04-09 Multilayered semiconductor device (Original Assignee) Mitsubishi Electric Corp (Current Assignee) Renesas Electronics Corp Yoshinori Tanaka |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch (said second circuit) stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US6369446B1 CLAIM 1 . A semiconductor device in which first and second circuit elements to be connected to each other are disposed in such a manner as to be spaced from each other with a specific gap kept therebetween in the stacking direction , said semiconductor device comprising : a first interlayer insulating film formed on said first circuit element , and wherein said first circuit element is a source/drain region of a transistor provided on a silicon substrate ; a conductive pad provided in said first interlayer insulating film in such a manner that one end surface thereof is connected to said first circuit element and the other end surface thereof is exposed to the surface of said first interlayer insulating film ; a second interlayer insulating film formed on said first interlayer insulating film and said pad ; and a conductive plug provided in said second interlayer insulating film in such a manner that one end surface thereof is in contact with said pad and the other end surface thereof is connected to said second circuit (second etch, etch process) element , and wherein said second circuit element is a bit line , wherein the surface of said first interlayer insulating film is smoothly continuous to the other end surface of said pad at the same level , said plug is smaller in size than said pad and is in contact with the central portion of said pad , and said bit line is narrower than said conductive plug , and has a uniform width . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer protects removal of a substrate material (stacking direction, silicon oxide) by an etch process (said second circuit) . |
US6369446B1 CLAIM 1 . A semiconductor device in which first and second circuit elements to be connected to each other are disposed in such a manner as to be spaced from each other with a specific gap kept therebetween in the stacking direction (substrate material) , said semiconductor device comprising : a first interlayer insulating film formed on said first circuit element , and wherein said first circuit element is a source/drain region of a transistor provided on a silicon substrate ; a conductive pad provided in said first interlayer insulating film in such a manner that one end surface thereof is connected to said first circuit element and the other end surface thereof is exposed to the surface of said first interlayer insulating film ; a second interlayer insulating film formed on said first interlayer insulating film and said pad ; and a conductive plug provided in said second interlayer insulating film in such a manner that one end surface thereof is in contact with said pad and the other end surface thereof is connected to said second circuit (second etch, etch process) element , and wherein said second circuit element is a bit line , wherein the surface of said first interlayer insulating film is smoothly continuous to the other end surface of said pad at the same level , said plug is smaller in size than said pad and is in contact with the central portion of said pad , and said bit line is narrower than said conductive plug , and has a uniform width . US6369446B1 CLAIM 3 . The semiconductor device according to claim 2 , further comprising : a silicon nitride film formed on said third interlayer insulating film ; and a silicon oxide (substrate material) film formed on said silicon nitride film ; wherein said first electrode is a cylindrical electrode formed in an opening provided in said silicon oxide film and said silicon nitride film ; and each of said first electrode , said capacitor side plug and said capacitor side pad is made from doped silicon which is doped with an impurity at an arbitrary concentration . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch (said second circuit) stop layer protects lower layers during an etching process . |
US6369446B1 CLAIM 1 . A semiconductor device in which first and second circuit elements to be connected to each other are disposed in such a manner as to be spaced from each other with a specific gap kept therebetween in the stacking direction , said semiconductor device comprising : a first interlayer insulating film formed on said first circuit element , and wherein said first circuit element is a source/drain region of a transistor provided on a silicon substrate ; a conductive pad provided in said first interlayer insulating film in such a manner that one end surface thereof is connected to said first circuit element and the other end surface thereof is exposed to the surface of said first interlayer insulating film ; a second interlayer insulating film formed on said first interlayer insulating film and said pad ; and a conductive plug provided in said second interlayer insulating film in such a manner that one end surface thereof is in contact with said pad and the other end surface thereof is connected to said second circuit (second etch, etch process) element , and wherein said second circuit element is a bit line , wherein the surface of said first interlayer insulating film is smoothly continuous to the other end surface of said pad at the same level , said plug is smaller in size than said pad and is in contact with the central portion of said pad , and said bit line is narrower than said conductive plug , and has a uniform width . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (said second circuit) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6369446B1 CLAIM 1 . A semiconductor device in which first and second circuit elements to be connected to each other are disposed in such a manner as to be spaced from each other with a specific gap kept therebetween in the stacking direction , said semiconductor device comprising : a first interlayer insulating film formed on said first circuit element , and wherein said first circuit element is a source/drain region of a transistor provided on a silicon substrate ; a conductive pad provided in said first interlayer insulating film in such a manner that one end surface thereof is connected to said first circuit element and the other end surface thereof is exposed to the surface of said first interlayer insulating film ; a second interlayer insulating film formed on said first interlayer insulating film and said pad ; and a conductive plug provided in said second interlayer insulating film in such a manner that one end surface thereof is in contact with said pad and the other end surface thereof is connected to said second circuit (second etch, etch process) element , and wherein said second circuit element is a bit line , wherein the surface of said first interlayer insulating film is smoothly continuous to the other end surface of said pad at the same level , said plug is smaller in size than said pad and is in contact with the central portion of said pad , and said bit line is narrower than said conductive plug , and has a uniform width . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch (said second circuit) stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US6369446B1 CLAIM 1 . A semiconductor device in which first and second circuit elements to be connected to each other are disposed in such a manner as to be spaced from each other with a specific gap kept therebetween in the stacking direction , said semiconductor device comprising : a first interlayer insulating film formed on said first circuit element , and wherein said first circuit element is a source/drain region of a transistor provided on a silicon substrate ; a conductive pad provided in said first interlayer insulating film in such a manner that one end surface thereof is connected to said first circuit element and the other end surface thereof is exposed to the surface of said first interlayer insulating film ; a second interlayer insulating film formed on said first interlayer insulating film and said pad ; and a conductive plug provided in said second interlayer insulating film in such a manner that one end surface thereof is in contact with said pad and the other end surface thereof is connected to said second circuit (second etch, etch process) element , and wherein said second circuit element is a bit line , wherein the surface of said first interlayer insulating film is smoothly continuous to the other end surface of said pad at the same level , said plug is smaller in size than said pad and is in contact with the central portion of said pad , and said bit line is narrower than said conductive plug , and has a uniform width . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (said second circuit) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6369446B1 CLAIM 1 . A semiconductor device in which first and second circuit elements to be connected to each other are disposed in such a manner as to be spaced from each other with a specific gap kept therebetween in the stacking direction , said semiconductor device comprising : a first interlayer insulating film formed on said first circuit element , and wherein said first circuit element is a source/drain region of a transistor provided on a silicon substrate ; a conductive pad provided in said first interlayer insulating film in such a manner that one end surface thereof is connected to said first circuit element and the other end surface thereof is exposed to the surface of said first interlayer insulating film ; a second interlayer insulating film formed on said first interlayer insulating film and said pad ; and a conductive plug provided in said second interlayer insulating film in such a manner that one end surface thereof is in contact with said pad and the other end surface thereof is connected to said second circuit (second etch, etch process) element , and wherein said second circuit element is a bit line , wherein the surface of said first interlayer insulating film is smoothly continuous to the other end surface of said pad at the same level , said plug is smaller in size than said pad and is in contact with the central portion of said pad , and said bit line is narrower than said conductive plug , and has a uniform width . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US6365504B1 Filed: 1999-10-15 Issued: 2002-04-02 Self aligned dual damascene method (Original Assignee) TSMC Acer Semiconductor Manufacturing Inc (Current Assignee) Taiwan Semiconductor Manufacturing Co TSMC Ltd Wu Kuo Chien, Chen Hsi Chieh, Chen Han Ping |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer (first etch stop layer) directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US6365504B1 CLAIM 9 . A dual damascene method for producing a conductive line and a via plug , comprising the steps of : (a) forming a second conductive line pattern by applying a first photoresist on a structure to be formed the conductive line and the via plug thereon , wherein the structure locates on a first conductive line and a first insulating layer and comprises in a sequence from bottom to top a second insulating layer , a first etch stop layer (first etch stop layer) , a third insulating layer and a second etch stop layer , wherein the first photoresist is formed on the second etch stop layer ; (b) utilizing the first photoresist as an etching mask and etching the second etch stop layer and the third insulating layer , the etching process stopping at the first etch stop layer and a second conductive line opening being formed ; (c) removing the first photoresist ; (d) forming second spacers on the first etch stop layer and the sidewalls of the second conductive line opening ; (e) forming a via pattern on the second etch stop layer by a second photoresist ; (f) utilizing the second photoresist and the second spacers as an etching mask and etching the first etch stop layer and the second insulating layer , the etching process stopping at the first conductive line and a via hole being formed ; (g) removing the second photoresist ; and (h) filling the second conductive line opening and the via hole with a conductive material and forming an interconnection of the second conductive line and the via plug . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer (first etch stop layer) protects removal of a substrate material by an etch process . |
US6365504B1 CLAIM 9 . A dual damascene method for producing a conductive line and a via plug , comprising the steps of : (a) forming a second conductive line pattern by applying a first photoresist on a structure to be formed the conductive line and the via plug thereon , wherein the structure locates on a first conductive line and a first insulating layer and comprises in a sequence from bottom to top a second insulating layer , a first etch stop layer (first etch stop layer) , a third insulating layer and a second etch stop layer , wherein the first photoresist is formed on the second etch stop layer ; (b) utilizing the first photoresist as an etching mask and etching the second etch stop layer and the third insulating layer , the etching process stopping at the first etch stop layer and a second conductive line opening being formed ; (c) removing the first photoresist ; (d) forming second spacers on the first etch stop layer and the sidewalls of the second conductive line opening ; (e) forming a via pattern on the second etch stop layer by a second photoresist ; (f) utilizing the second photoresist and the second spacers as an etching mask and etching the first etch stop layer and the second insulating layer , the etching process stopping at the first conductive line and a via hole being formed ; (g) removing the second photoresist ; and (h) filling the second conductive line opening and the via hole with a conductive material and forming an interconnection of the second conductive line and the via plug . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch stop layer protects lower layers during an etching process (etching process) . |
US6365504B1 CLAIM 9 . A dual damascene method for producing a conductive line and a via plug , comprising the steps of : (a) forming a second conductive line pattern by applying a first photoresist on a structure to be formed the conductive line and the via plug thereon , wherein the structure locates on a first conductive line and a first insulating layer and comprises in a sequence from bottom to top a second insulating layer , a first etch stop layer , a third insulating layer and a second etch stop layer , wherein the first photoresist is formed on the second etch stop layer ; (b) utilizing the first photoresist as an etching mask and etching the second etch stop layer and the third insulating layer , the etching process (etching process) stopping at the first etch stop layer and a second conductive line opening being formed ; (c) removing the first photoresist ; (d) forming second spacers on the first etch stop layer and the sidewalls of the second conductive line opening ; (e) forming a via pattern on the second etch stop layer by a second photoresist ; (f) utilizing the second photoresist and the second spacers as an etching mask and etching the first etch stop layer and the second insulating layer , the etching process stopping at the first conductive line and a via hole being formed ; (g) removing the second photoresist ; and (h) filling the second conductive line opening and the via hole with a conductive material and forming an interconnection of the second conductive line and the via plug . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer (first etch stop layer) is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6365504B1 CLAIM 9 . A dual damascene method for producing a conductive line and a via plug , comprising the steps of : (a) forming a second conductive line pattern by applying a first photoresist on a structure to be formed the conductive line and the via plug thereon , wherein the structure locates on a first conductive line and a first insulating layer and comprises in a sequence from bottom to top a second insulating layer , a first etch stop layer (first etch stop layer) , a third insulating layer and a second etch stop layer , wherein the first photoresist is formed on the second etch stop layer ; (b) utilizing the first photoresist as an etching mask and etching the second etch stop layer and the third insulating layer , the etching process stopping at the first etch stop layer and a second conductive line opening being formed ; (c) removing the first photoresist ; (d) forming second spacers on the first etch stop layer and the sidewalls of the second conductive line opening ; (e) forming a via pattern on the second etch stop layer by a second photoresist ; (f) utilizing the second photoresist and the second spacers as an etching mask and etching the first etch stop layer and the second insulating layer , the etching process stopping at the first conductive line and a via hole being formed ; (g) removing the second photoresist ; and (h) filling the second conductive line opening and the via hole with a conductive material and forming an interconnection of the second conductive line and the via plug . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space (second space) in said second sub interlevel dielectric layer for said contact region is in a second range (upper part) of about 0 . 16 μm to 0 . 18 μm wide . |
US6365504B1 CLAIM 1 . A method for fabricating an interconnection between a conductive line and a via plug on an insulating layer , comprising the steps of : (a) forming a conductive line pattern on a upper part (second range) of the insulating layer ; (b) etching the upper part of the insulating layer and forming a conductive line opening in the upper part of the insulating layer ; (c) depositing spacers on the sidewalls of the conductive line opening ; (d) formiing a via pattern on the upper part of the insulating layer ; the opening of the via pattern being substantially larger than the width of the conductive line opening ; (e) etching a lower part of the insulating layer exposed between the spacers and forming a via hole ; and (f) filling the conductive line opening and the via hole with a conductive material and forming an interconnection of the conductive line and the via plug . US6365504B1 CLAIM 9 . A dual damascene method for producing a conductive line and a via plug , comprising the steps of : (a) forming a second conductive line pattern by applying a first photoresist on a structure to be formed the conductive line and the via plug thereon , wherein the structure locates on a first conductive line and a first insulating layer and comprises in a sequence from bottom to top a second insulating layer , a first etch stop layer , a third insulating layer and a second etch stop layer , wherein the first photoresist is formed on the second etch stop layer ; (b) utilizing the first photoresist as an etching mask and etching the second etch stop layer and the third insulating layer , the etching process stopping at the first etch stop layer and a second conductive line opening being formed ; (c) removing the first photoresist ; (d) forming second space (second space) rs on the first etch stop layer and the sidewalls of the second conductive line opening ; (e) forming a via pattern on the second etch stop layer by a second photoresist ; (f) utilizing the second photoresist and the second spacers as an etching mask and etching the first etch stop layer and the second insulating layer , the etching process stopping at the first conductive line and a via hole being formed ; (g) removing the second photoresist ; and (h) filling the second conductive line opening and the via hole with a conductive material and forming an interconnection of the second conductive line and the via plug . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US6365504B1 CLAIM 1 . A method for fabricating an interconnection between a conductive line and a via plug on an insulating layer , comprising the steps of : (a) forming a conductive line pattern on a upper part of the insulating layer ; (b) etching the upper part of the insulating layer and forming (anti reflective coating) a conductive line opening in the upper part of the insulating layer ; (c) depositing spacers on the sidewalls of the conductive line opening ; (d) formiing a via pattern on the upper part of the insulating layer ; the opening of the via pattern being substantially larger than the width of the conductive line opening ; (e) etching a lower part of the insulating layer exposed between the spacers and forming a via hole ; and (f) filling the conductive line opening and the via hole with a conductive material and forming an interconnection of the conductive line and the via plug . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer (first etch stop layer) and a second etch stop layer wherein said first etch stop layer and said second etch stop layers (second etch stop layers) have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom (lower part) , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US6365504B1 CLAIM 1 . A method for fabricating an interconnection between a conductive line and a via plug on an insulating layer , comprising the steps of : (a) forming a conductive line pattern on a upper part of the insulating layer ; (b) etching the upper part of the insulating layer and forming a conductive line opening in the upper part of the insulating layer ; (c) depositing spacers on the sidewalls of the conductive line opening ; (d) formiing a via pattern on the upper part of the insulating layer ; the opening of the via pattern being substantially larger than the width of the conductive line opening ; (e) etching a lower part (contact bottom) of the insulating layer exposed between the spacers and forming a via hole ; and (f) filling the conductive line opening and the via hole with a conductive material and forming an interconnection of the conductive line and the via plug . US6365504B1 CLAIM 9 . A dual damascene method for producing a conductive line and a via plug , comprising the steps of : (a) forming a second conductive line pattern by applying a first photoresist on a structure to be formed the conductive line and the via plug thereon , wherein the structure locates on a first conductive line and a first insulating layer and comprises in a sequence from bottom to top a second insulating layer , a first etch stop layer (first etch stop layer) , a third insulating layer and a second etch stop layer , wherein the first photoresist is formed on the second etch stop layer ; (b) utilizing the first photoresist as an etching mask and etching the second etch stop layer and the third insulating layer , the etching process stopping at the first etch stop layer and a second conductive line opening being formed ; (c) removing the first photoresist ; (d) forming second spacers on the first etch stop layer and the sidewalls of the second conductive line opening ; (e) forming a via pattern on the second etch stop layer by a second photoresist ; (f) utilizing the second photoresist and the second spacers as an etching mask and etching the first etch stop layer and the second insulating layer , the etching process stopping at the first conductive line and a via hole being formed ; (g) removing the second photoresist ; and (h) filling the second conductive line opening and the via hole with a conductive material and forming an interconnection of the second conductive line and the via plug . US6365504B1 CLAIM 10 . The dual damascene method of claim 9 , wherein the first and the second etch stop layers (second etch stop layers) are composed of silicon nitride . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer (first etch stop layer) is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6365504B1 CLAIM 9 . A dual damascene method for producing a conductive line and a via plug , comprising the steps of : (a) forming a second conductive line pattern by applying a first photoresist on a structure to be formed the conductive line and the via plug thereon , wherein the structure locates on a first conductive line and a first insulating layer and comprises in a sequence from bottom to top a second insulating layer , a first etch stop layer (first etch stop layer) , a third insulating layer and a second etch stop layer , wherein the first photoresist is formed on the second etch stop layer ; (b) utilizing the first photoresist as an etching mask and etching the second etch stop layer and the third insulating layer , the etching process stopping at the first etch stop layer and a second conductive line opening being formed ; (c) removing the first photoresist ; (d) forming second spacers on the first etch stop layer and the sidewalls of the second conductive line opening ; (e) forming a via pattern on the second etch stop layer by a second photoresist ; (f) utilizing the second photoresist and the second spacers as an etching mask and etching the first etch stop layer and the second insulating layer , the etching process stopping at the first conductive line and a via hole being formed ; (g) removing the second photoresist ; and (h) filling the second conductive line opening and the via hole with a conductive material and forming an interconnection of the second conductive line and the via plug . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US6365504B1 CLAIM 1 . A method for fabricating an interconnection between a conductive line and a via plug on an insulating layer , comprising the steps of : (a) forming a conductive line pattern on a upper part of the insulating layer ; (b) etching the upper part of the insulating layer and forming (anti reflective coating) a conductive line opening in the upper part of the insulating layer ; (c) depositing spacers on the sidewalls of the conductive line opening ; (d) formiing a via pattern on the upper part of the insulating layer ; the opening of the via pattern being substantially larger than the width of the conductive line opening ; (e) etching a lower part of the insulating layer exposed between the spacers and forming a via hole ; and (f) filling the conductive line opening and the via hole with a conductive material and forming an interconnection of the conductive line and the via plug . |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region is a first range of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range (upper part) of about 0 . 16 μm to 0 . 18 μm wide . |
US6365504B1 CLAIM 1 . A method for fabricating an interconnection between a conductive line and a via plug on an insulating layer , comprising the steps of : (a) forming a conductive line pattern on a upper part (second range) of the insulating layer ; (b) etching the upper part of the insulating layer and forming a conductive line opening in the upper part of the insulating layer ; (c) depositing spacers on the sidewalls of the conductive line opening ; (d) formiing a via pattern on the upper part of the insulating layer ; the opening of the via pattern being substantially larger than the width of the conductive line opening ; (e) etching a lower part of the insulating layer exposed between the spacers and forming a via hole ; and (f) filling the conductive line opening and the via hole with a conductive material and forming an interconnection of the conductive line and the via plug . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US6083822A Filed: 1999-08-12 Issued: 2000-07-04 Fabrication process for copper structures (Original Assignee) Industrial Technology Research Institute ITRI (Current Assignee) Transpacific IP Ltd Tze-Liang Lee |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch (etch stop layer) stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US6083822A CLAIM 14 . A method of forming a dual damascene copper structure , in a dual damascene opening , created in a composite insulator layer , wherein said composite insulator layer is comprised of silicon oxide layers , and multiple silicon nitride , etch stop layer (second etch) s , comprising the steps of : forming an underlying , metal interconnect structure ; depositing a first silicon nitride layer , overlying said underlying , metal interconnect structure ; depositing a first silicon oxide layer , on said first silicon nitride layer ; depositing a second silicon nitride layer , on said first silicon oxide layer ; depositing a second silicon oxide layer , on said second silicon nitride layer ; depositing a third silicon nitride layer , on said second silicon oxide layer ; depositing a third silicon oxide layer , on said third silicon nitride layer ; using a first photoresist shape as a mask , to anisotropically create a first , initial diameter opening , in said third silicon oxide layer , in said third silicon nitride layer , in said second silicon oxide layer , and in said second silicon nitride layer ; using a second photoresist shape as a mask , to anisotropically create a final diameter opening , in said third silicon oxide layer , wherein said final diameter is wider than said first , initial diameter , while using said first , initial diameter opening , in said third silicon nitride layer , as a mask , to create a second , initial diameter opening , in said third silicon nitride layer , in said second silicon oxide layer , in said second silicon nitride layer , and in said first silicon oxide layer , wherein diameter of said first , initial diameter opening is equal to diameter of said second , initial diameter opening , resulting in said dual damascene opening ; anisotropically removing the portion of said first silicon nitride layer , exposed at the bottom of said second , initial diameter opening , while anisotropically removing the regions of said third silicon nitride layer , exposed in said final diameter opening ; depositing a copper layer ; and removing portions of copper layer from the top surface of said third silicon oxide layer , forming said dual damascene copper structure , in said dual damascene opening , in said composite insulator layer , with said dual damascene copper structure comprised of a copper interconnect structure , located in said wide diameter opening , and comprised of a copper via structure , located in said second , initial diameter opening . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer protects removal of a substrate material (active ion) by an etch process . |
US6083822A CLAIM 8 . The method of claim 1 , wherein said first , initial diameter opening , is formed via an anisotropic reactive ion (substrate material) etching , (RIE) , procedure , using CHF 3 as an etchant for said third insulator layer , and for said second insulator layer , with an etch rate selectivity of said third insulator layer , and of said second insulator layer , to said second silicon nitride layer , and to said first silicon nitride layer , of about 2 to 1 , while a fluorine based chemistry , chosen from a group that contains CF 4 , CH 2 F 2 , or CH 3 F , is used as an etchant for said second silicon nitride layer , and for said first silicon nitride layer , with an etch rate selectivity of said second silicon nitride layer , and of said first silicon nitride layer , to said third insulator layer , and to said second insulator layer , of about 8 to 1 . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch (etch stop layer) stop layer protects lower layers during an etching process . |
US6083822A CLAIM 14 . A method of forming a dual damascene copper structure , in a dual damascene opening , created in a composite insulator layer , wherein said composite insulator layer is comprised of silicon oxide layers , and multiple silicon nitride , etch stop layer (second etch) s , comprising the steps of : forming an underlying , metal interconnect structure ; depositing a first silicon nitride layer , overlying said underlying , metal interconnect structure ; depositing a first silicon oxide layer , on said first silicon nitride layer ; depositing a second silicon nitride layer , on said first silicon oxide layer ; depositing a second silicon oxide layer , on said second silicon nitride layer ; depositing a third silicon nitride layer , on said second silicon oxide layer ; depositing a third silicon oxide layer , on said third silicon nitride layer ; using a first photoresist shape as a mask , to anisotropically create a first , initial diameter opening , in said third silicon oxide layer , in said third silicon nitride layer , in said second silicon oxide layer , and in said second silicon nitride layer ; using a second photoresist shape as a mask , to anisotropically create a final diameter opening , in said third silicon oxide layer , wherein said final diameter is wider than said first , initial diameter , while using said first , initial diameter opening , in said third silicon nitride layer , as a mask , to create a second , initial diameter opening , in said third silicon nitride layer , in said second silicon oxide layer , in said second silicon nitride layer , and in said first silicon oxide layer , wherein diameter of said first , initial diameter opening is equal to diameter of said second , initial diameter opening , resulting in said dual damascene opening ; anisotropically removing the portion of said first silicon nitride layer , exposed at the bottom of said second , initial diameter opening , while anisotropically removing the regions of said third silicon nitride layer , exposed in said final diameter opening ; depositing a copper layer ; and removing portions of copper layer from the top surface of said third silicon oxide layer , forming said dual damascene copper structure , in said dual damascene opening , in said composite insulator layer , with said dual damascene copper structure comprised of a copper interconnect structure , located in said wide diameter opening , and comprised of a copper via structure , located in said second , initial diameter opening . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (etch stop layer) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6083822A CLAIM 14 . A method of forming a dual damascene copper structure , in a dual damascene opening , created in a composite insulator layer , wherein said composite insulator layer is comprised of silicon oxide layers , and multiple silicon nitride , etch stop layer (second etch) s , comprising the steps of : forming an underlying , metal interconnect structure ; depositing a first silicon nitride layer , overlying said underlying , metal interconnect structure ; depositing a first silicon oxide layer , on said first silicon nitride layer ; depositing a second silicon nitride layer , on said first silicon oxide layer ; depositing a second silicon oxide layer , on said second silicon nitride layer ; depositing a third silicon nitride layer , on said second silicon oxide layer ; depositing a third silicon oxide layer , on said third silicon nitride layer ; using a first photoresist shape as a mask , to anisotropically create a first , initial diameter opening , in said third silicon oxide layer , in said third silicon nitride layer , in said second silicon oxide layer , and in said second silicon nitride layer ; using a second photoresist shape as a mask , to anisotropically create a final diameter opening , in said third silicon oxide layer , wherein said final diameter is wider than said first , initial diameter , while using said first , initial diameter opening , in said third silicon nitride layer , as a mask , to create a second , initial diameter opening , in said third silicon nitride layer , in said second silicon oxide layer , in said second silicon nitride layer , and in said first silicon oxide layer , wherein diameter of said first , initial diameter opening is equal to diameter of said second , initial diameter opening , resulting in said dual damascene opening ; anisotropically removing the portion of said first silicon nitride layer , exposed at the bottom of said second , initial diameter opening , while anisotropically removing the regions of said third silicon nitride layer , exposed in said final diameter opening ; depositing a copper layer ; and removing portions of copper layer from the top surface of said third silicon oxide layer , forming said dual damascene copper structure , in said dual damascene opening , in said composite insulator layer , with said dual damascene copper structure comprised of a copper interconnect structure , located in said wide diameter opening , and comprised of a copper via structure , located in said second , initial diameter opening . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US6083822A CLAIM 1 . A method of fabricating a dual damascene metal structure , in a dual damascene opening , on a semiconductor substrate , wherein the dual damascene opening is formed in a composite insulator layer , comprising the steps of : providing an underlying metal interconnect structure ; depositing a barrier layer ; depositing said composite insulator layer , on said barrier layer , with said composite insulator layer comprised of : an underlying , first insulator layer ; a first silicon nitride layer ; a second insulator layer ; a second silicon nitride layer ; and a third insulator layer ; using a first photoresist shape as a mask to form a first , initial diameter opening , in said third insulator layer , in said second silicon nitride layer , in said second insulator layer , and in said first silicon nitride layer ; using a second photoresist shape as a mask to form a final diameter opening in said third insulator layer , wherein said final diameter is wider than said first , initial diameter , while using said first , initial diameter opening , in said second silicon nitride layer , as a mask for removal of said first insulator layer , creating a second , initial diameter opening , of said dual damascene opening , comprised in said second silicon nitride layer , in said second insulator layer , in said first silicon nitride layer , in said first insulator layer , wherein diameter of said first , initial diameter opening , is equal to diameter of said second , initial diameter opening ; removing a region of said barrier layer , exposed at the bottom of said second , initial diameter opening , exposing a portion of the top surface of said underlying , metal interconnect structure , while also removing regions of said second silicon nitride layer , exposed in said final diameter opening ; and forming (anti reflective coating) said dual damascene metal structure , in said dual damascene opening , in said composite insulator layer , with said dual damascene metal structure , contacting the top surface of said underlying metal structure , located at the bottom of said dual damascene opening . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US6083822A CLAIM 1 . A method of fabricating a dual damascene metal structure , in a dual damascene opening , on a semiconductor substrate , wherein the dual damascene opening is formed in a composite insulator layer , comprising the steps of : providing an underlying metal interconnect structure ; depositing a barrier layer ; depositing said composite insulator layer , on said barrier layer , with said composite insulator layer comprised of : an underlying , first insulator layer ; a first silicon nitride layer ; a second insulator layer ; a second silicon nitride layer ; and a third insulator layer ; using a first photoresist shape as a mask to form a first , initial diameter opening , in said third insulator layer , in said second silicon nitride layer , in said second insulator layer , and in said first silicon nitride layer ; using a second photoresist shape as a mask to form a final diameter opening in said third insulator layer , wherein said final diameter is wider than said first , initial diameter , while using said first , initial diameter opening , in said second silicon nitride layer , as a mask for removal of said first insulator layer , creating a second , initial diameter opening , of said dual damascene opening , comprised in said second silicon nitride layer , in said second insulator layer , in said first silicon nitride layer , in said first insulator layer , wherein diameter of said first , initial diameter opening , is equal to diameter of said second , initial diameter opening ; removing a region of said barrier layer , exposed at the bottom of said second , initial diameter opening , exposing a portion of the top surface of said underlying , metal interconnect structure , while also removing regions of said second silicon nitride layer , exposed in said final diameter opening ; and forming (anti reflective coating) said dual damascene metal structure , in said dual damascene opening , in said composite insulator layer , with said dual damascene metal structure , contacting the top surface of said underlying metal structure , located at the bottom of said dual damascene opening . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US6194301B1 Filed: 1999-07-12 Issued: 2001-02-27 Method of fabricating an integrated circuit of logic and memory using damascene gate structure (Original Assignee) International Business Machines Corp (Current Assignee) International Business Machines Corp Carl Radens, Mary E. Weybright, Gary Bronner |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (second interlevel dielectric layer, first interlevel, upper surfaces) layer over said first etch stop layer ; a second etch (second thickness) stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US6194301B1 CLAIM 1 . A process for fabricating an integrated circuit device having a first transistor and a second transistor , comprising : providing a semiconductor substrate ; forming a well within the semiconductor substrate ; forming a first gate oxide layer on the semiconductor substrate ; depositing a first gate conductor layer on the first gate oxide layer ; depositing a gate cap dielectric layer on the first gate conductor layer ; patterning the first gate oxide layer , first gate conductor layer , and gate cap dielectric layer to form first gate electrodes ; forming source/drain areas adjacent to and self-aligned with the first gate electrodes ; depositing a first spacer material over the first gate electrodes and elsewhere on the semiconductor substrate ; etching back the first spacer material thereby forming first sidewall spacers on the first gate electrodes ; depositing a first interlevel (second interlevel dielectric layer, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, first sub) dielectric layer over the first gate electrodes and elsewhere on the semiconductor substrate ; chemical/mechanically polishing the first interlevel dielectric layer to the gate cap dielectric layer of first gate electrodes ; stripping one of the first gate electrodes to the semiconductor substrate at a selected region of the semiconductor substrate ; forming a second gate oxide at the selected region of the semiconductor substrate ; depositing a second gate conductor on the second gate oxide ; forming a salicide at an upper portion of the second gate conductor , whereby a second gate electrode is formed ; depositing a second interlevel dielectric layer (second interlevel dielectric layer, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, first sub) over the first and second gate electrodes and first level dielectric layer ; and forming a plurality of contacts to form electrical interconnections over the shallow trench isolation regions including the source/drain regions . US6194301B1 CLAIM 5 . The process as in claim 1 , wherein the first gate oxide layer has a first thickness and the second gate oxide layer has a second thickness (second etch, second sub, second etch stop layer) , the first thickness being different from the second thicknesses . US6194301B1 CLAIM 14 . The process as in claim 12 , further comprising : depositing a first spacer material over the first gate electrodes and elsewhere on the semiconductor substrate ; etching back the first spacer material thereby forming first sidewall spacers on the first gate electrodes ; and depositing a first interlevel dielectric layer over the first gate electrodes and elsewhere on the semiconductor substrate , the first interlevel dielectric layer being planarized to upper surfaces (second interlevel dielectric layer, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, first sub) of the first gate electrodes prior to selectively removing the at least one of the first gate electrodes . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer protects removal of a substrate material by an etch process (ion implantation) . |
US6194301B1 CLAIM 6 . The process as in claim 1 , wherein a self-aligned channel region is formed generally below the second gate electrode by ion implantation (etch process) . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (second interlevel dielectric layer, first interlevel, upper surfaces) layer insulates said contact region . |
US6194301B1 CLAIM 1 . A process for fabricating an integrated circuit device having a first transistor and a second transistor , comprising : providing a semiconductor substrate ; forming a well within the semiconductor substrate ; forming a first gate oxide layer on the semiconductor substrate ; depositing a first gate conductor layer on the first gate oxide layer ; depositing a gate cap dielectric layer on the first gate conductor layer ; patterning the first gate oxide layer , first gate conductor layer , and gate cap dielectric layer to form first gate electrodes ; forming source/drain areas adjacent to and self-aligned with the first gate electrodes ; depositing a first spacer material over the first gate electrodes and elsewhere on the semiconductor substrate ; etching back the first spacer material thereby forming first sidewall spacers on the first gate electrodes ; depositing a first interlevel (second interlevel dielectric layer, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, first sub) dielectric layer over the first gate electrodes and elsewhere on the semiconductor substrate ; chemical/mechanically polishing the first interlevel dielectric layer to the gate cap dielectric layer of first gate electrodes ; stripping one of the first gate electrodes to the semiconductor substrate at a selected region of the semiconductor substrate ; forming a second gate oxide at the selected region of the semiconductor substrate ; depositing a second gate conductor on the second gate oxide ; forming a salicide at an upper portion of the second gate conductor , whereby a second gate electrode is formed ; depositing a second interlevel dielectric layer (second interlevel dielectric layer, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, first sub) over the first and second gate electrodes and first level dielectric layer ; and forming a plurality of contacts to form electrical interconnections over the shallow trench isolation regions including the source/drain regions . US6194301B1 CLAIM 14 . The process as in claim 12 , further comprising : depositing a first spacer material over the first gate electrodes and elsewhere on the semiconductor substrate ; etching back the first spacer material thereby forming first sidewall spacers on the first gate electrodes ; and depositing a first interlevel dielectric layer over the first gate electrodes and elsewhere on the semiconductor substrate , the first interlevel dielectric layer being planarized to upper surfaces (second interlevel dielectric layer, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, first sub) of the first gate electrodes prior to selectively removing the at least one of the first gate electrodes . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch (second thickness) stop layer protects lower layers during an etching process . |
US6194301B1 CLAIM 5 . The process as in claim 1 , wherein the first gate oxide layer has a first thickness and the second gate oxide layer has a second thickness (second etch, second sub, second etch stop layer) , the first thickness being different from the second thicknesses . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (second interlevel dielectric layer, first interlevel, upper surfaces) layer insulates said contact region . |
US6194301B1 CLAIM 1 . A process for fabricating an integrated circuit device having a first transistor and a second transistor , comprising : providing a semiconductor substrate ; forming a well within the semiconductor substrate ; forming a first gate oxide layer on the semiconductor substrate ; depositing a first gate conductor layer on the first gate oxide layer ; depositing a gate cap dielectric layer on the first gate conductor layer ; patterning the first gate oxide layer , first gate conductor layer , and gate cap dielectric layer to form first gate electrodes ; forming source/drain areas adjacent to and self-aligned with the first gate electrodes ; depositing a first spacer material over the first gate electrodes and elsewhere on the semiconductor substrate ; etching back the first spacer material thereby forming first sidewall spacers on the first gate electrodes ; depositing a first interlevel (second interlevel dielectric layer, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, first sub) dielectric layer over the first gate electrodes and elsewhere on the semiconductor substrate ; chemical/mechanically polishing the first interlevel dielectric layer to the gate cap dielectric layer of first gate electrodes ; stripping one of the first gate electrodes to the semiconductor substrate at a selected region of the semiconductor substrate ; forming a second gate oxide at the selected region of the semiconductor substrate ; depositing a second gate conductor on the second gate oxide ; forming a salicide at an upper portion of the second gate conductor , whereby a second gate electrode is formed ; depositing a second interlevel dielectric layer (second interlevel dielectric layer, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, first sub) over the first and second gate electrodes and first level dielectric layer ; and forming a plurality of contacts to form electrical interconnections over the shallow trench isolation regions including the source/drain regions . US6194301B1 CLAIM 5 . The process as in claim 1 , wherein the first gate oxide layer has a first thickness and the second gate oxide layer has a second thickness (second etch, second sub, second etch stop layer) , the first thickness being different from the second thicknesses . US6194301B1 CLAIM 14 . The process as in claim 12 , further comprising : depositing a first spacer material over the first gate electrodes and elsewhere on the semiconductor substrate ; etching back the first spacer material thereby forming first sidewall spacers on the first gate electrodes ; and depositing a first interlevel dielectric layer over the first gate electrodes and elsewhere on the semiconductor substrate , the first interlevel dielectric layer being planarized to upper surfaces (second interlevel dielectric layer, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, first sub) of the first gate electrodes prior to selectively removing the at least one of the first gate electrodes . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (second interlevel dielectric layer, first interlevel, upper surfaces) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (second thickness) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6194301B1 CLAIM 1 . A process for fabricating an integrated circuit device having a first transistor and a second transistor , comprising : providing a semiconductor substrate ; forming a well within the semiconductor substrate ; forming a first gate oxide layer on the semiconductor substrate ; depositing a first gate conductor layer on the first gate oxide layer ; depositing a gate cap dielectric layer on the first gate conductor layer ; patterning the first gate oxide layer , first gate conductor layer , and gate cap dielectric layer to form first gate electrodes ; forming source/drain areas adjacent to and self-aligned with the first gate electrodes ; depositing a first spacer material over the first gate electrodes and elsewhere on the semiconductor substrate ; etching back the first spacer material thereby forming first sidewall spacers on the first gate electrodes ; depositing a first interlevel (second interlevel dielectric layer, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, first sub) dielectric layer over the first gate electrodes and elsewhere on the semiconductor substrate ; chemical/mechanically polishing the first interlevel dielectric layer to the gate cap dielectric layer of first gate electrodes ; stripping one of the first gate electrodes to the semiconductor substrate at a selected region of the semiconductor substrate ; forming a second gate oxide at the selected region of the semiconductor substrate ; depositing a second gate conductor on the second gate oxide ; forming a salicide at an upper portion of the second gate conductor , whereby a second gate electrode is formed ; depositing a second interlevel dielectric layer (second interlevel dielectric layer, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, first sub) over the first and second gate electrodes and first level dielectric layer ; and forming a plurality of contacts to form electrical interconnections over the shallow trench isolation regions including the source/drain regions . US6194301B1 CLAIM 5 . The process as in claim 1 , wherein the first gate oxide layer has a first thickness and the second gate oxide layer has a second thickness (second etch, second sub, second etch stop layer) , the first thickness being different from the second thicknesses . US6194301B1 CLAIM 14 . The process as in claim 12 , further comprising : depositing a first spacer material over the first gate electrodes and elsewhere on the semiconductor substrate ; etching back the first spacer material thereby forming first sidewall spacers on the first gate electrodes ; and depositing a first interlevel dielectric layer over the first gate electrodes and elsewhere on the semiconductor substrate , the first interlevel dielectric layer being planarized to upper surfaces (second interlevel dielectric layer, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, first sub) of the first gate electrodes prior to selectively removing the at least one of the first gate electrodes . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space (trench isolation regions, first space) in a portion of said first sub interlevel dielectric (second interlevel dielectric layer, first interlevel, upper surfaces) layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space (second space) in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US6194301B1 CLAIM 1 . A process for fabricating an integrated circuit device having a first transistor and a second transistor , comprising : providing a semiconductor substrate ; forming a well within the semiconductor substrate ; forming a first gate oxide layer on the semiconductor substrate ; depositing a first gate conductor layer on the first gate oxide layer ; depositing a gate cap dielectric layer on the first gate conductor layer ; patterning the first gate oxide layer , first gate conductor layer , and gate cap dielectric layer to form first gate electrodes ; forming source/drain areas adjacent to and self-aligned with the first gate electrodes ; depositing a first space (first space) r material over the first gate electrodes and elsewhere on the semiconductor substrate ; etching back the first spacer material thereby forming first sidewall spacers on the first gate electrodes ; depositing a first interlevel (second interlevel dielectric layer, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, first sub) dielectric layer over the first gate electrodes and elsewhere on the semiconductor substrate ; chemical/mechanically polishing the first interlevel dielectric layer to the gate cap dielectric layer of first gate electrodes ; stripping one of the first gate electrodes to the semiconductor substrate at a selected region of the semiconductor substrate ; forming a second gate oxide at the selected region of the semiconductor substrate ; depositing a second gate conductor on the second gate oxide ; forming a salicide at an upper portion of the second gate conductor , whereby a second gate electrode is formed ; depositing a second interlevel dielectric layer (second interlevel dielectric layer, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, first sub) over the first and second gate electrodes and first level dielectric layer ; and forming a plurality of contacts to form electrical interconnections over the shallow trench isolation regions (first space) including the source/drain regions . US6194301B1 CLAIM 5 . The process as in claim 1 , wherein the first gate oxide layer has a first thickness and the second gate oxide layer has a second thickness (second etch, second sub, second etch stop layer) , the first thickness being different from the second thicknesses . US6194301B1 CLAIM 8 . The process as in claim 1 , further comprising : removing the first sidewall spacers formed adjacent to the removed first gate electrode prior to forming the second gate oxide layer ; and depositing a second space (second space) r material over the first gate electrode and elsewhere on the semiconductor substrate ; etching back the second spacer material thereby forming second sidewall spacers in the selected region where the first gate electrode was removed . US6194301B1 CLAIM 14 . The process as in claim 12 , further comprising : depositing a first spacer material over the first gate electrodes and elsewhere on the semiconductor substrate ; etching back the first spacer material thereby forming first sidewall spacers on the first gate electrodes ; and depositing a first interlevel dielectric layer over the first gate electrodes and elsewhere on the semiconductor substrate , the first interlevel dielectric layer being planarized to upper surfaces (second interlevel dielectric layer, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, first sub) of the first gate electrodes prior to selectively removing the at least one of the first gate electrodes . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US6194301B1 CLAIM 1 . A process for fabricating an integrated circuit device having a first transistor and a second transistor , comprising : providing a semiconductor substrate ; forming a well within the semiconductor substrate ; forming a first gate oxide layer on the semiconductor substrate ; depositing a first gate conductor layer on the first gate oxide layer ; depositing a gate cap dielectric layer on the first gate conductor layer ; patterning the first gate oxide layer , first gate conductor layer , and gate cap dielectric layer to form first gate electrodes ; forming source/drain areas adjacent to and self-aligned with the first gate electrodes ; depositing a first spacer material over the first gate electrodes and elsewhere on the semiconductor substrate ; etching back the first spacer material thereby forming first sidewall spacers on the first gate electrodes ; depositing a first interlevel dielectric layer over the first gate electrodes and elsewhere on the semiconductor substrate ; chemical/mechanically polishing the first interlevel dielectric layer to the gate cap dielectric layer of first gate electrodes ; stripping one of the first gate electrodes to the semiconductor substrate at a selected region of the semiconductor substrate ; forming a second gate oxide at the selected region of the semiconductor substrate ; depositing a second gate conductor on the second gate oxide ; forming a salicide at an upper portion of the second gate conductor , whereby a second gate electrode is formed ; depositing a second interlevel dielectric layer over the first and second gate electrodes and first level dielectric layer ; and forming (anti reflective coating) a plurality of contacts to form electrical interconnections over the shallow trench isolation regions including the source/drain regions . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch (second thickness) stop layer wherein said first etch stop layer and said second etch stop layers (second sidewall spacer, first sidewall spacer, drain regions) have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (second interlevel dielectric layer, first interlevel, upper surfaces) layer and said second etch stop layer formed under a second interlevel dielectric layer (second interlevel dielectric layer, first interlevel, upper surfaces) , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US6194301B1 CLAIM 1 . A process for fabricating an integrated circuit device having a first transistor and a second transistor , comprising : providing a semiconductor substrate ; forming a well within the semiconductor substrate ; forming a first gate oxide layer on the semiconductor substrate ; depositing a first gate conductor layer on the first gate oxide layer ; depositing a gate cap dielectric layer on the first gate conductor layer ; patterning the first gate oxide layer , first gate conductor layer , and gate cap dielectric layer to form first gate electrodes ; forming source/drain areas adjacent to and self-aligned with the first gate electrodes ; depositing a first spacer material over the first gate electrodes and elsewhere on the semiconductor substrate ; etching back the first spacer material thereby forming first sidewall spacer (second etch stop layers, floating gate) s on the first gate electrodes ; depositing a first interlevel (second interlevel dielectric layer, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, first sub) dielectric layer over the first gate electrodes and elsewhere on the semiconductor substrate ; chemical/mechanically polishing the first interlevel dielectric layer to the gate cap dielectric layer of first gate electrodes ; stripping one of the first gate electrodes to the semiconductor substrate at a selected region of the semiconductor substrate ; forming a second gate oxide at the selected region of the semiconductor substrate ; depositing a second gate conductor on the second gate oxide ; forming a salicide at an upper portion of the second gate conductor , whereby a second gate electrode is formed ; depositing a second interlevel dielectric layer (second interlevel dielectric layer, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, first sub) over the first and second gate electrodes and first level dielectric layer ; and forming a plurality of contacts to form electrical interconnections over the shallow trench isolation regions including the source/drain regions (second etch stop layers, floating gate) . US6194301B1 CLAIM 5 . The process as in claim 1 , wherein the first gate oxide layer has a first thickness and the second gate oxide layer has a second thickness (second etch, second sub, second etch stop layer) , the first thickness being different from the second thicknesses . US6194301B1 CLAIM 8 . The process as in claim 1 , further comprising : removing the first sidewall spacers formed adjacent to the removed first gate electrode prior to forming the second gate oxide layer ; and depositing a second spacer material over the first gate electrode and elsewhere on the semiconductor substrate ; etching back the second spacer material thereby forming second sidewall spacer (second etch stop layers, floating gate) s in the selected region where the first gate electrode was removed . US6194301B1 CLAIM 14 . The process as in claim 12 , further comprising : depositing a first spacer material over the first gate electrodes and elsewhere on the semiconductor substrate ; etching back the first spacer material thereby forming first sidewall spacers on the first gate electrodes ; and depositing a first interlevel dielectric layer over the first gate electrodes and elsewhere on the semiconductor substrate , the first interlevel dielectric layer being planarized to upper surfaces (second interlevel dielectric layer, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, first sub) of the first gate electrodes prior to selectively removing the at least one of the first gate electrodes . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (second interlevel dielectric layer, first interlevel, upper surfaces) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (second thickness) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6194301B1 CLAIM 1 . A process for fabricating an integrated circuit device having a first transistor and a second transistor , comprising : providing a semiconductor substrate ; forming a well within the semiconductor substrate ; forming a first gate oxide layer on the semiconductor substrate ; depositing a first gate conductor layer on the first gate oxide layer ; depositing a gate cap dielectric layer on the first gate conductor layer ; patterning the first gate oxide layer , first gate conductor layer , and gate cap dielectric layer to form first gate electrodes ; forming source/drain areas adjacent to and self-aligned with the first gate electrodes ; depositing a first spacer material over the first gate electrodes and elsewhere on the semiconductor substrate ; etching back the first spacer material thereby forming first sidewall spacers on the first gate electrodes ; depositing a first interlevel (second interlevel dielectric layer, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, first sub) dielectric layer over the first gate electrodes and elsewhere on the semiconductor substrate ; chemical/mechanically polishing the first interlevel dielectric layer to the gate cap dielectric layer of first gate electrodes ; stripping one of the first gate electrodes to the semiconductor substrate at a selected region of the semiconductor substrate ; forming a second gate oxide at the selected region of the semiconductor substrate ; depositing a second gate conductor on the second gate oxide ; forming a salicide at an upper portion of the second gate conductor , whereby a second gate electrode is formed ; depositing a second interlevel dielectric layer (second interlevel dielectric layer, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, first sub) over the first and second gate electrodes and first level dielectric layer ; and forming a plurality of contacts to form electrical interconnections over the shallow trench isolation regions including the source/drain regions . US6194301B1 CLAIM 5 . The process as in claim 1 , wherein the first gate oxide layer has a first thickness and the second gate oxide layer has a second thickness (second etch, second sub, second etch stop layer) , the first thickness being different from the second thicknesses . US6194301B1 CLAIM 14 . The process as in claim 12 , further comprising : depositing a first spacer material over the first gate electrodes and elsewhere on the semiconductor substrate ; etching back the first spacer material thereby forming first sidewall spacers on the first gate electrodes ; and depositing a first interlevel dielectric layer over the first gate electrodes and elsewhere on the semiconductor substrate , the first interlevel dielectric layer being planarized to upper surfaces (second interlevel dielectric layer, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, first sub) of the first gate electrodes prior to selectively removing the at least one of the first gate electrodes . |
| US7977797B2 CLAIM 13 . An integrated circuit of claim 11 further comprising a floating gate (second sidewall spacer, first sidewall spacer, drain regions) . |
US6194301B1 CLAIM 1 . A process for fabricating an integrated circuit device having a first transistor and a second transistor , comprising : providing a semiconductor substrate ; forming a well within the semiconductor substrate ; forming a first gate oxide layer on the semiconductor substrate ; depositing a first gate conductor layer on the first gate oxide layer ; depositing a gate cap dielectric layer on the first gate conductor layer ; patterning the first gate oxide layer , first gate conductor layer , and gate cap dielectric layer to form first gate electrodes ; forming source/drain areas adjacent to and self-aligned with the first gate electrodes ; depositing a first spacer material over the first gate electrodes and elsewhere on the semiconductor substrate ; etching back the first spacer material thereby forming first sidewall spacer (second etch stop layers, floating gate) s on the first gate electrodes ; depositing a first interlevel dielectric layer over the first gate electrodes and elsewhere on the semiconductor substrate ; chemical/mechanically polishing the first interlevel dielectric layer to the gate cap dielectric layer of first gate electrodes ; stripping one of the first gate electrodes to the semiconductor substrate at a selected region of the semiconductor substrate ; forming a second gate oxide at the selected region of the semiconductor substrate ; depositing a second gate conductor on the second gate oxide ; forming a salicide at an upper portion of the second gate conductor , whereby a second gate electrode is formed ; depositing a second interlevel dielectric layer over the first and second gate electrodes and first level dielectric layer ; and forming a plurality of contacts to form electrical interconnections over the shallow trench isolation regions including the source/drain regions (second etch stop layers, floating gate) . US6194301B1 CLAIM 8 . The process as in claim 1 , further comprising : removing the first sidewall spacers formed adjacent to the removed first gate electrode prior to forming the second gate oxide layer ; and depositing a second spacer material over the first gate electrode and elsewhere on the semiconductor substrate ; etching back the second spacer material thereby forming second sidewall spacer (second etch stop layers, floating gate) s in the selected region where the first gate electrode was removed . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US6194301B1 CLAIM 1 . A process for fabricating an integrated circuit device having a first transistor and a second transistor , comprising : providing a semiconductor substrate ; forming a well within the semiconductor substrate ; forming a first gate oxide layer on the semiconductor substrate ; depositing a first gate conductor layer on the first gate oxide layer ; depositing a gate cap dielectric layer on the first gate conductor layer ; patterning the first gate oxide layer , first gate conductor layer , and gate cap dielectric layer to form first gate electrodes ; forming source/drain areas adjacent to and self-aligned with the first gate electrodes ; depositing a first spacer material over the first gate electrodes and elsewhere on the semiconductor substrate ; etching back the first spacer material thereby forming first sidewall spacers on the first gate electrodes ; depositing a first interlevel dielectric layer over the first gate electrodes and elsewhere on the semiconductor substrate ; chemical/mechanically polishing the first interlevel dielectric layer to the gate cap dielectric layer of first gate electrodes ; stripping one of the first gate electrodes to the semiconductor substrate at a selected region of the semiconductor substrate ; forming a second gate oxide at the selected region of the semiconductor substrate ; depositing a second gate conductor on the second gate oxide ; forming a salicide at an upper portion of the second gate conductor , whereby a second gate electrode is formed ; depositing a second interlevel dielectric layer over the first and second gate electrodes and first level dielectric layer ; and forming (anti reflective coating) a plurality of contacts to form electrical interconnections over the shallow trench isolation regions including the source/drain regions . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | JP2000340743A Filed: 1999-05-31 Issued: 2000-12-08 半導体装置およびその製造方法 (Original Assignee) Mitsubishi Electric Corp; 三菱電機株式会社 Yoshinori Tanaka, 義典 田中 |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (製造方法) of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation (の絶縁) between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (誘電体膜) layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
JP2000340743A CLAIM 2 【請求項２】 互いに導通すべき第１および第２の回路 要素が積層方向に所定間隔を空けて配置される半導体装 置の製造方法 (metal layer coupling area) であって、 前記第１の回路要素の上層に第１層間膜を形成するステ ップと、 一端面が前記第１の回路要素に導通する導電性のパッド を前記第１層間膜の内部に設けるステップと、 前記第１層間膜および前記パッドの上層に第２層間膜を 形成するステップと、 一端面が前記パッドに接触し、かつ、他端面が前記第２ の回路要素と導通する導電性のプラグを前記第２層間膜 の内部に設けるステップと、を備え、 前記パッドを設けるステップは、前記パッドの他端面 が、前記第１層間膜の表面と同一平面を成す状態を形成 するステップを含み、 前記プラグは、前記パッドに比して小さく、前記パッド の中央部近傍に接触するように形成されることを特徴と する半導体装置の製造方法。 JP2000340743A CLAIM 11 【請求項１１】 前記パッドは不純物を含有するドープ トシリコンを含み、 前記第１電極は、前記パッドと接触する高融点金属膜 と、前記高融点金属膜に比して抵抗の低い金属膜とが積 層された導電膜を含み、 前記パッドと前記第１電極との境界近傍にシリサイド膜 を備え、 前記シリサイド膜は、ドープトシリコンからの不純物の 吸い上げ防止に適した第１の高融点金属膜と前記パッド との反応物であり、 前記第１電極に含まれる前記高融点金属膜は、ドープト シリコンと、前記金属膜との反応防止に適した第２の高 融点金属膜であり、更に、 前記第１電極の上層に形成され、キャパシタの絶縁 (electrical insulation) 膜と して機能する高誘電体膜 (interlevel dielectric, second interlevel dielectric layer) と、 前記高誘電体膜の上層に形成されるキャパシタの第２電 極と、 を備えることを特徴とする請求項６記載の半導体装置。 |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (誘電体膜) layer insulates said contact region . |
JP2000340743A CLAIM 11 【請求項１１】 前記パッドは不純物を含有するドープ トシリコンを含み、 前記第１電極は、前記パッドと接触する高融点金属膜 と、前記高融点金属膜に比して抵抗の低い金属膜とが積 層された導電膜を含み、 前記パッドと前記第１電極との境界近傍にシリサイド膜 を備え、 前記シリサイド膜は、ドープトシリコンからの不純物の 吸い上げ防止に適した第１の高融点金属膜と前記パッド との反応物であり、 前記第１電極に含まれる前記高融点金属膜は、ドープト シリコンと、前記金属膜との反応防止に適した第２の高 融点金属膜であり、更に、 前記第１電極の上層に形成され、キャパシタの絶縁膜と して機能する高誘電体膜 (interlevel dielectric, second interlevel dielectric layer) と、 前記高誘電体膜の上層に形成されるキャパシタの第２電 極と、 を備えることを特徴とする請求項６記載の半導体装置。 |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (誘電体膜) layer insulates said contact region . |
JP2000340743A CLAIM 11 【請求項１１】 前記パッドは不純物を含有するドープ トシリコンを含み、 前記第１電極は、前記パッドと接触する高融点金属膜 と、前記高融点金属膜に比して抵抗の低い金属膜とが積 層された導電膜を含み、 前記パッドと前記第１電極との境界近傍にシリサイド膜 を備え、 前記シリサイド膜は、ドープトシリコンからの不純物の 吸い上げ防止に適した第１の高融点金属膜と前記パッド との反応物であり、 前記第１電極に含まれる前記高融点金属膜は、ドープト シリコンと、前記金属膜との反応防止に適した第２の高 融点金属膜であり、更に、 前記第１電極の上層に形成され、キャパシタの絶縁膜と して機能する高誘電体膜 (interlevel dielectric, second interlevel dielectric layer) と、 前記高誘電体膜の上層に形成されるキャパシタの第２電 極と、 を備えることを特徴とする請求項６記載の半導体装置。 |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area of said contact region permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area (製造方法) of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
JP2000340743A CLAIM 2 【請求項２】 互いに導通すべき第１および第２の回路 要素が積層方向に所定間隔を空けて配置される半導体装 置の製造方法 (metal layer coupling area) であって、 前記第１の回路要素の上層に第１層間膜を形成するステ ップと、 一端面が前記第１の回路要素に導通する導電性のパッド を前記第１層間膜の内部に設けるステップと、 前記第１層間膜および前記パッドの上層に第２層間膜を 形成するステップと、 一端面が前記パッドに接触し、かつ、他端面が前記第２ の回路要素と導通する導電性のプラグを前記第２層間膜 の内部に設けるステップと、を備え、 前記パッドを設けるステップは、前記パッドの他端面 が、前記第１層間膜の表面と同一平面を成す状態を形成 するステップを含み、 前記プラグは、前記パッドに比して小さく、前記パッド の中央部近傍に接触するように形成されることを特徴と する半導体装置の製造方法。 |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Å thick , said first sub interlevel dielectric (誘電体膜) layer is in a range of about 1 , 000 to 2 , 000 Å thick , said second etch stop layer is in a range of about 300 to 800 Å thick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Å thick . |
JP2000340743A CLAIM 11 【請求項１１】 前記パッドは不純物を含有するドープ トシリコンを含み、 前記第１電極は、前記パッドと接触する高融点金属膜 と、前記高融点金属膜に比して抵抗の低い金属膜とが積 層された導電膜を含み、 前記パッドと前記第１電極との境界近傍にシリサイド膜 を備え、 前記シリサイド膜は、ドープトシリコンからの不純物の 吸い上げ防止に適した第１の高融点金属膜と前記パッド との反応物であり、 前記第１電極に含まれる前記高融点金属膜は、ドープト シリコンと、前記金属膜との反応防止に適した第２の高 融点金属膜であり、更に、 前記第１電極の上層に形成され、キャパシタの絶縁膜と して機能する高誘電体膜 (interlevel dielectric, second interlevel dielectric layer) と、 前記高誘電体膜の上層に形成されるキャパシタの第２電 極と、 を備えることを特徴とする請求項６記載の半導体装置。 |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric (誘電体膜) layer for said contact region is in a first range (部近傍) of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range (あること, 境界近傍) of about 0 . 16 μm to 0 . 18 μm wide . |
JP2000340743A CLAIM 1 【請求項１】 互いに導通すべき第１および第２の回路 要素が積層方向に所定間隔を空けて配置される半導体装 置であって、 前記第１の回路要素の上層に形成される第１層間膜と、 一端面が前記第１の回路要素に導通し、かつ、他端面が 前記第１層間膜の表面に露出するように、前記第１層間 膜の内部に設けられる導電性のパッドと、 前記第１層間膜および前記パッドの上層に形成される第 ２層間膜と、 一端面が前記パッドに接触し、かつ、他端面が前記第２ の回路要素と導通するように、前記第２層間膜の内部に 設けられる導電性のプラグと、を備え、 前記第１層間膜の表面と、前記パッドの他端面は平滑な 同一平面を形成し、 前記プラグは、前記パッドに比して小さく、前記パッド の中央部近傍 (first range) に接触していることを特徴とする半導体装 置。 JP2000340743A CLAIM 4 【請求項４】 前記パッドと前記プラグとの境界近傍 (second range) に シリサイド膜を備えると共に、 前記シリサイド膜は、ドープトシリコンからの不純物の 吸い上げ防止に適した第１の高融点金属膜と前記パッド との反応物であり、 前記プラグが備える高融点金属膜は、ドープトシリコン と、前記低抵抗金属膜との反応防止に適した第２の高融 点金属膜であること (second range) を特徴とする請求項３記載の半導体 装置。 JP2000340743A CLAIM 11 【請求項１１】 前記パッドは不純物を含有するドープ トシリコンを含み、 前記第１電極は、前記パッドと接触する高融点金属膜 と、前記高融点金属膜に比して抵抗の低い金属膜とが積 層された導電膜を含み、 前記パッドと前記第１電極との境界近傍にシリサイド膜 を備え、 前記シリサイド膜は、ドープトシリコンからの不純物の 吸い上げ防止に適した第１の高融点金属膜と前記パッド との反応物であり、 前記第１電極に含まれる前記高融点金属膜は、ドープト シリコンと、前記金属膜との反応防止に適した第２の高 融点金属膜であり、更に、 前記第１電極の上層に形成され、キャパシタの絶縁膜と して機能する高誘電体膜 (interlevel dielectric, second interlevel dielectric layer) と、 前記高誘電体膜の上層に形成されるキャパシタの第２電 極と、 を備えることを特徴とする請求項６記載の半導体装置。 |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (誘電体膜) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (製造方法) of said contact region . |
JP2000340743A CLAIM 2 【請求項２】 互いに導通すべき第１および第２の回路 要素が積層方向に所定間隔を空けて配置される半導体装 置の製造方法 (metal layer coupling area) であって、 前記第１の回路要素の上層に第１層間膜を形成するステ ップと、 一端面が前記第１の回路要素に導通する導電性のパッド を前記第１層間膜の内部に設けるステップと、 前記第１層間膜および前記パッドの上層に第２層間膜を 形成するステップと、 一端面が前記パッドに接触し、かつ、他端面が前記第２ の回路要素と導通する導電性のプラグを前記第２層間膜 の内部に設けるステップと、を備え、 前記パッドを設けるステップは、前記パッドの他端面 が、前記第１層間膜の表面と同一平面を成す状態を形成 するステップを含み、 前記プラグは、前記パッドに比して小さく、前記パッド の中央部近傍に接触するように形成されることを特徴と する半導体装置の製造方法。 JP2000340743A CLAIM 11 【請求項１１】 前記パッドは不純物を含有するドープ トシリコンを含み、 前記第１電極は、前記パッドと接触する高融点金属膜 と、前記高融点金属膜に比して抵抗の低い金属膜とが積 層された導電膜を含み、 前記パッドと前記第１電極との境界近傍にシリサイド膜 を備え、 前記シリサイド膜は、ドープトシリコンからの不純物の 吸い上げ防止に適した第１の高融点金属膜と前記パッド との反応物であり、 前記第１電極に含まれる前記高融点金属膜は、ドープト シリコンと、前記金属膜との反応防止に適した第２の高 融点金属膜であり、更に、 前記第１電極の上層に形成され、キャパシタの絶縁膜と して機能する高誘電体膜 (interlevel dielectric, second interlevel dielectric layer) と、 前記高誘電体膜の上層に形成されるキャパシタの第２電 極と、 を備えることを特徴とする請求項６記載の半導体装置。 |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Å thick , said first sub interlevel dielectric (誘電体膜) layer is in a range of about 1 , 000 to 2 , 000 Å thick , said second etch stop layer is in a range of about 300 to 800 Å thick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Å thick . |
JP2000340743A CLAIM 11 【請求項１１】 前記パッドは不純物を含有するドープ トシリコンを含み、 前記第１電極は、前記パッドと接触する高融点金属膜 と、前記高融点金属膜に比して抵抗の低い金属膜とが積 層された導電膜を含み、 前記パッドと前記第１電極との境界近傍にシリサイド膜 を備え、 前記シリサイド膜は、ドープトシリコンからの不純物の 吸い上げ防止に適した第１の高融点金属膜と前記パッド との反応物であり、 前記第１電極に含まれる前記高融点金属膜は、ドープト シリコンと、前記金属膜との反応防止に適した第２の高 融点金属膜であり、更に、 前記第１電極の上層に形成され、キャパシタの絶縁膜と して機能する高誘電体膜 (interlevel dielectric, second interlevel dielectric layer) と、 前記高誘電体膜の上層に形成されるキャパシタの第２電 極と、 を備えることを特徴とする請求項６記載の半導体装置。 |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region is a first range (部近傍) of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range (あること, 境界近傍) of about 0 . 16 μm to 0 . 18 μm wide . |
JP2000340743A CLAIM 1 【請求項１】 互いに導通すべき第１および第２の回路 要素が積層方向に所定間隔を空けて配置される半導体装 置であって、 前記第１の回路要素の上層に形成される第１層間膜と、 一端面が前記第１の回路要素に導通し、かつ、他端面が 前記第１層間膜の表面に露出するように、前記第１層間 膜の内部に設けられる導電性のパッドと、 前記第１層間膜および前記パッドの上層に形成される第 ２層間膜と、 一端面が前記パッドに接触し、かつ、他端面が前記第２ の回路要素と導通するように、前記第２層間膜の内部に 設けられる導電性のプラグと、を備え、 前記第１層間膜の表面と、前記パッドの他端面は平滑な 同一平面を形成し、 前記プラグは、前記パッドに比して小さく、前記パッド の中央部近傍 (first range) に接触していることを特徴とする半導体装 置。 JP2000340743A CLAIM 4 【請求項４】 前記パッドと前記プラグとの境界近傍 (second range) に シリサイド膜を備えると共に、 前記シリサイド膜は、ドープトシリコンからの不純物の 吸い上げ防止に適した第１の高融点金属膜と前記パッド との反応物であり、 前記プラグが備える高融点金属膜は、ドープトシリコン と、前記低抵抗金属膜との反応防止に適した第２の高融 点金属膜であること (second range) を特徴とする請求項３記載の半導体 装置。 |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US6194304B1 Filed: 1999-04-27 Issued: 2001-02-27 Semiconductor device and method of fabricating the same (Original Assignee) Seiko Epson Corp (Current Assignee) Seiko Epson Corp Yukio Morozumi, Michio Asahina, Naohiro Moriya, Kazuki Matsumoto, Eiji Suzuki |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area (silane compound) of said contact region is smaller than a metal layer coupling area (silane compound) of said contact region ; and a multiple etch (silicon oxide layer, layer dielectric) stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US6194304B1 CLAIM 1 . A method of fabricating a semiconductor device , comprising the steps of : forming an interlayer dielectric (etch process, multiple etch) on a semiconductor substrate including an electronic element ; forming a through-hole in said interlayer dielectric ; forming a barrier layer on surfaces of said interlayer dielectric and said through-hole ; and forming a conductive layer on a surface of said barrier layer , and wherein said step of forming an interlayer dielectric comprises at least the following steps (a) to (c) : (a) forming a first silicon oxide layer (etch process, multiple etch) by reacting a silicon compound with hydrogen peroxide using a chemical vapor deposition method ; (b) forming a porous second silicon oxide layer by reacting a compound including an impurity , a silicon compound , and at least one substance selected from oxygen and compounds including oxygen using a chemical vapor deposition method to permit gaseous by-products to escape therefrom ; and (c) annealing at a temperature of 300° C . to 850° C . US6194304B1 CLAIM 2 . The method of fabricating a semiconductor device as defined in claim 1 , wherein : said silicon compound used in said step (a) is at least one substance selected from inorganic silane compound (substrate coupling area, metal layer coupling area) s such as monosilane , disilane , SiH 2 Cl 2 , and SiF 4 ; and organic silane compounds such as CH 3 SiH 3 , tripropylsilane , and tetraethoxysilane . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer protects removal of a substrate material by an etch process (silicon oxide layer, layer dielectric) . |
US6194304B1 CLAIM 1 . A method of fabricating a semiconductor device , comprising the steps of : forming an interlayer dielectric (etch process, multiple etch) on a semiconductor substrate including an electronic element ; forming a through-hole in said interlayer dielectric ; forming a barrier layer on surfaces of said interlayer dielectric and said through-hole ; and forming a conductive layer on a surface of said barrier layer , and wherein said step of forming an interlayer dielectric comprises at least the following steps (a) to (c) : (a) forming a first silicon oxide layer (etch process, multiple etch) by reacting a silicon compound with hydrogen peroxide using a chemical vapor deposition method ; (b) forming a porous second silicon oxide layer by reacting a compound including an impurity , a silicon compound , and at least one substance selected from oxygen and compounds including oxygen using a chemical vapor deposition method to permit gaseous by-products to escape therefrom ; and (c) annealing at a temperature of 300° C . to 850° C . |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area (silane compound) of said contact region permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area (silane compound) of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
US6194304B1 CLAIM 2 . The method of fabricating a semiconductor device as defined in claim 1 , wherein : said silicon compound used in said step (a) is at least one substance selected from inorganic silane compound (substrate coupling area, metal layer coupling area) s such as monosilane , disilane , SiH 2 Cl 2 , and SiF 4 ; and organic silane compounds such as CH 3 SiH 3 , tripropylsilane , and tetraethoxysilane . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US6194304B1 CLAIM 1 . A method of fabricating a semiconductor device , comprising the steps of : forming an interlayer dielectric on a semiconductor substrate including an electronic element ; forming a through-hole in said interlayer dielectric ; forming a barrier layer on surfaces of said interlayer dielectric and said through-hole ; and forming (anti reflective coating) a conductive layer on a surface of said barrier layer , and wherein said step of forming an interlayer dielectric comprises at least the following steps (a) to (c) : (a) forming a first silicon oxide layer by reacting a silicon compound with hydrogen peroxide using a chemical vapor deposition method ; (b) forming a porous second silicon oxide layer by reacting a compound including an impurity , a silicon compound , and at least one substance selected from oxygen and compounds including oxygen using a chemical vapor deposition method to permit gaseous by-products to escape therefrom ; and (c) annealing at a temperature of 300° C . to 850° C . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch (silicon oxide layer, layer dielectric) stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area (silane compound) of said contact region is smaller than a metal layer coupling area (silane compound) of said contact region . |
US6194304B1 CLAIM 1 . A method of fabricating a semiconductor device , comprising the steps of : forming an interlayer dielectric (etch process, multiple etch) on a semiconductor substrate including an electronic element ; forming a through-hole in said interlayer dielectric ; forming a barrier layer on surfaces of said interlayer dielectric and said through-hole ; and forming a conductive layer on a surface of said barrier layer , and wherein said step of forming an interlayer dielectric comprises at least the following steps (a) to (c) : (a) forming a first silicon oxide layer (etch process, multiple etch) by reacting a silicon compound with hydrogen peroxide using a chemical vapor deposition method ; (b) forming a porous second silicon oxide layer by reacting a compound including an impurity , a silicon compound , and at least one substance selected from oxygen and compounds including oxygen using a chemical vapor deposition method to permit gaseous by-products to escape therefrom ; and (c) annealing at a temperature of 300° C . to 850° C . US6194304B1 CLAIM 2 . The method of fabricating a semiconductor device as defined in claim 1 , wherein : said silicon compound used in said step (a) is at least one substance selected from inorganic silane compound (substrate coupling area, metal layer coupling area) s such as monosilane , disilane , SiH 2 Cl 2 , and SiF 4 ; and organic silane compounds such as CH 3 SiH 3 , tripropylsilane , and tetraethoxysilane . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US6194304B1 CLAIM 1 . A method of fabricating a semiconductor device , comprising the steps of : forming an interlayer dielectric on a semiconductor substrate including an electronic element ; forming a through-hole in said interlayer dielectric ; forming a barrier layer on surfaces of said interlayer dielectric and said through-hole ; and forming (anti reflective coating) a conductive layer on a surface of said barrier layer , and wherein said step of forming an interlayer dielectric comprises at least the following steps (a) to (c) : (a) forming a first silicon oxide layer by reacting a silicon compound with hydrogen peroxide using a chemical vapor deposition method ; (b) forming a porous second silicon oxide layer by reacting a compound including an impurity , a silicon compound , and at least one substance selected from oxygen and compounds including oxygen using a chemical vapor deposition method to permit gaseous by-products to escape therefrom ; and (c) annealing at a temperature of 300° C . to 850° C . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US6348709B1 Filed: 1999-03-15 Issued: 2002-02-19 Electrical contact for high dielectric constant capacitors and method for fabricating the same (Original Assignee) Micron Technology Inc (Current Assignee) Micron Technology Inc Thomas M. Graettinger, F. Daniel Gealy |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region (interlevel dielectric layer) such that a substrate coupling area (conductive bar) of said contact region is smaller than a metal layer coupling area (conductive oxide) of said contact region ; and a multiple etch (tungsten nitride) stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (high dielectric constant, bottom electrode) layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US6348709B1 CLAIM 4 . The contact structure of claim 1 , wherein said conductive filler comprises a conductive oxide (metal layer coupling area) . US6348709B1 CLAIM 7 . The contact structure of claim 1 wherein said conductive diffusion barrier liner comprises tungsten nitride (multiple etch) . US6348709B1 CLAIM 33 . The system of claim 32 , wherein the lower surface of the contact plug further comprises an active area cladding interposed between the second conductive bar (substrate coupling area) rier and an active area of the lower circuit element . US6348709B1 CLAIM 37 . A memory cell in an integrated circuit , comprising : a capacitor having a top electrode , a bottom electrode (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) , and a high dielectric constant (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) dielectric between the top electrode and the bottom electrode ; a semiconductor substrate having an active area ; a contact plug between the bottom electrode and the active area , the contact plug comprising a oxidation-resistant conductive material ; an interlevel dielectric layer (spacer region) surrounding the contact plug ; a non-conductive spacer between the contact plug and the surrounding interlevel dielectric layer , wherein the non-conductive spacer comprises silicon nitride ; and a conductive diffusion barrier comprising a first conductive diffusion barrier layer interposed between the non-conductive spacer and the contact plug , a second conductive diffusion barrier layer interposed between the contact plug and the active area , and a third conductive diffusion barrier layer interposed between the contact plug and the bottom electrode , wherein the memory cell further comprises one of a bit line and a word line having a conductive portion directly contacting the non-conductive spacer . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (high dielectric constant, bottom electrode) layer insulates said contact region . |
US6348709B1 CLAIM 37 . A memory cell in an integrated circuit , comprising : a capacitor having a top electrode , a bottom electrode (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) , and a high dielectric constant (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) dielectric between the top electrode and the bottom electrode ; a semiconductor substrate having an active area ; a contact plug between the bottom electrode and the active area , the contact plug comprising a oxidation-resistant conductive material ; an interlevel dielectric layer surrounding the contact plug ; a non-conductive spacer between the contact plug and the surrounding interlevel dielectric layer , wherein the non-conductive spacer comprises silicon nitride ; and a conductive diffusion barrier comprising a first conductive diffusion barrier layer interposed between the non-conductive spacer and the contact plug , a second conductive diffusion barrier layer interposed between the contact plug and the active area , and a third conductive diffusion barrier layer interposed between the contact plug and the bottom electrode , wherein the memory cell further comprises one of a bit line and a word line having a conductive portion directly contacting the non-conductive spacer . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (high dielectric constant, bottom electrode) layer insulates said contact region . |
US6348709B1 CLAIM 37 . A memory cell in an integrated circuit , comprising : a capacitor having a top electrode , a bottom electrode (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) , and a high dielectric constant (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) dielectric between the top electrode and the bottom electrode ; a semiconductor substrate having an active area ; a contact plug between the bottom electrode and the active area , the contact plug comprising a oxidation-resistant conductive material ; an interlevel dielectric layer surrounding the contact plug ; a non-conductive spacer between the contact plug and the surrounding interlevel dielectric layer , wherein the non-conductive spacer comprises silicon nitride ; and a conductive diffusion barrier comprising a first conductive diffusion barrier layer interposed between the non-conductive spacer and the contact plug , a second conductive diffusion barrier layer interposed between the contact plug and the active area , and a third conductive diffusion barrier layer interposed between the contact plug and the bottom electrode , wherein the memory cell further comprises one of a bit line and a word line having a conductive portion directly contacting the non-conductive spacer . |
| US7977797B2 CLAIM 6 . An integrated circuit of claim 1 wherein said spacer region (interlevel dielectric layer) insulates said contact region . |
US6348709B1 CLAIM 37 . A memory cell in an integrated circuit , comprising : a capacitor having a top electrode , a bottom electrode , and a high dielectric constant dielectric between the top electrode and the bottom electrode ; a semiconductor substrate having an active area ; a contact plug between the bottom electrode and the active area , the contact plug comprising a oxidation-resistant conductive material ; an interlevel dielectric layer (spacer region) surrounding the contact plug ; a non-conductive spacer between the contact plug and the surrounding interlevel dielectric layer , wherein the non-conductive spacer comprises silicon nitride ; and a conductive diffusion barrier comprising a first conductive diffusion barrier layer interposed between the non-conductive spacer and the contact plug , a second conductive diffusion barrier layer interposed between the contact plug and the active area , and a third conductive diffusion barrier layer interposed between the contact plug and the bottom electrode , wherein the memory cell further comprises one of a bit line and a word line having a conductive portion directly contacting the non-conductive spacer . |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area (conductive bar) of said contact region permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area (conductive oxide) of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
US6348709B1 CLAIM 4 . The contact structure of claim 1 , wherein said conductive filler comprises a conductive oxide (metal layer coupling area) . US6348709B1 CLAIM 33 . The system of claim 32 , wherein the lower surface of the contact plug further comprises an active area cladding interposed between the second conductive bar (substrate coupling area) rier and an active area of the lower circuit element . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (high dielectric constant, bottom electrode) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6348709B1 CLAIM 37 . A memory cell in an integrated circuit , comprising : a capacitor having a top electrode , a bottom electrode (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) , and a high dielectric constant (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) dielectric between the top electrode and the bottom electrode ; a semiconductor substrate having an active area ; a contact plug between the bottom electrode and the active area , the contact plug comprising a oxidation-resistant conductive material ; an interlevel dielectric layer surrounding the contact plug ; a non-conductive spacer between the contact plug and the surrounding interlevel dielectric layer , wherein the non-conductive spacer comprises silicon nitride ; and a conductive diffusion barrier comprising a first conductive diffusion barrier layer interposed between the non-conductive spacer and the contact plug , a second conductive diffusion barrier layer interposed between the contact plug and the active area , and a third conductive diffusion barrier layer interposed between the contact plug and the bottom electrode , wherein the memory cell further comprises one of a bit line and a word line having a conductive portion directly contacting the non-conductive spacer . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric (high dielectric constant, bottom electrode) layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US6348709B1 CLAIM 37 . A memory cell in an integrated circuit , comprising : a capacitor having a top electrode , a bottom electrode (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) , and a high dielectric constant (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) dielectric between the top electrode and the bottom electrode ; a semiconductor substrate having an active area ; a contact plug between the bottom electrode and the active area , the contact plug comprising a oxidation-resistant conductive material ; an interlevel dielectric layer surrounding the contact plug ; a non-conductive spacer between the contact plug and the surrounding interlevel dielectric layer , wherein the non-conductive spacer comprises silicon nitride ; and a conductive diffusion barrier comprising a first conductive diffusion barrier layer interposed between the non-conductive spacer and the contact plug , a second conductive diffusion barrier layer interposed between the contact plug and the active area , and a third conductive diffusion barrier layer interposed between the contact plug and the bottom electrode , wherein the memory cell further comprises one of a bit line and a word line having a conductive portion directly contacting the non-conductive spacer . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch (tungsten nitride) stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (high dielectric constant, bottom electrode) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area (conductive bar) of said contact region is smaller than a metal layer coupling area (conductive oxide) of said contact region . |
US6348709B1 CLAIM 4 . The contact structure of claim 1 , wherein said conductive filler comprises a conductive oxide (metal layer coupling area) . US6348709B1 CLAIM 7 . The contact structure of claim 1 wherein said conductive diffusion barrier liner comprises tungsten nitride (multiple etch) . US6348709B1 CLAIM 33 . The system of claim 32 , wherein the lower surface of the contact plug further comprises an active area cladding interposed between the second conductive bar (substrate coupling area) rier and an active area of the lower circuit element . US6348709B1 CLAIM 37 . A memory cell in an integrated circuit , comprising : a capacitor having a top electrode , a bottom electrode (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) , and a high dielectric constant (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) dielectric between the top electrode and the bottom electrode ; a semiconductor substrate having an active area ; a contact plug between the bottom electrode and the active area , the contact plug comprising a oxidation-resistant conductive material ; an interlevel dielectric layer surrounding the contact plug ; a non-conductive spacer between the contact plug and the surrounding interlevel dielectric layer , wherein the non-conductive spacer comprises silicon nitride ; and a conductive diffusion barrier comprising a first conductive diffusion barrier layer interposed between the non-conductive spacer and the contact plug , a second conductive diffusion barrier layer interposed between the contact plug and the active area , and a third conductive diffusion barrier layer interposed between the contact plug and the bottom electrode , wherein the memory cell further comprises one of a bit line and a word line having a conductive portion directly contacting the non-conductive spacer . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (high dielectric constant, bottom electrode) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6348709B1 CLAIM 37 . A memory cell in an integrated circuit , comprising : a capacitor having a top electrode , a bottom electrode (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) , and a high dielectric constant (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) dielectric between the top electrode and the bottom electrode ; a semiconductor substrate having an active area ; a contact plug between the bottom electrode and the active area , the contact plug comprising a oxidation-resistant conductive material ; an interlevel dielectric layer surrounding the contact plug ; a non-conductive spacer between the contact plug and the surrounding interlevel dielectric layer , wherein the non-conductive spacer comprises silicon nitride ; and a conductive diffusion barrier comprising a first conductive diffusion barrier layer interposed between the non-conductive spacer and the contact plug , a second conductive diffusion barrier layer interposed between the contact plug and the active area , and a third conductive diffusion barrier layer interposed between the contact plug and the bottom electrode , wherein the memory cell further comprises one of a bit line and a word line having a conductive portion directly contacting the non-conductive spacer . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US6180494B1 Filed: 1999-03-11 Issued: 2001-01-30 Integrated circuitry, methods of fabricating integrated circuitry, methods of forming local interconnects, and methods of forming conductive lines (Original Assignee) Micron Technology Inc (Current Assignee) Round Rock Research LLC H. Montgomery Manning |
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| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer protects removal of a substrate material (substrate material) by an etch process . |
US6180494B1 CLAIM 22 . A method of forming a local interconnect comprising : forming a pair of transistor gates having respective opposing sidewalls over a semiconductor substrate ; depositing an insulating layer over the substrate and between the pair of transistor gates ; etching a first contact opening into the insulating layer to proximate the substrate between the pair of transistor gates and another contact opening through the insulating layer to proximate the substrate proximate an opposing side of one of the pair of transistor gates ; forming insulating sidewall spacers over the opposing sidewalls of the one transistor gate , the insulating layer being received between at least one of said sidewalls and one of said sidewall spacers ; forming a local interconnect layer to overlie the one transistor gate and electrically connect with semiconductor substrate material (substrate material) between the pair of transistor gates and semiconductor substrate material proximate the opposing side of the one transistor gate ; forming field isolation material regions and active area regions on the semiconductor substrate before the depositing ; etching a trench into the field isolation material and the insulating layer into a desired local interconnect line configuration ; and forming the local interconnect layer to at least partially fill the trench and which electrically connects with one of the active area regions . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US6180494B1 CLAIM 1 . A method of fabricating integrated circuitry comprising : forming a conductive line having opposing sidewalls over a semiconductor substrate ; depositing an insulating layer over the substrate and the line ; etching the insulating layer proximate the line along at least a portion of at least one sidewall of the line ; after the etching , depositing an insulating spacer forming layer over the substrate and the line , and anisotropically etching it to form an insulating sidewall spacer along said portion of the at least one sidewall ; forming field isolation material regions and active area regions on the semiconductor substrate before the depositing ; etching a trench into the field isolation material and the insulating layer into a desired local interconnect line configuration ; and forming (anti reflective coating) a local interconnect layer of material over the substrate which at least partially fills the trench and which electrically connects with one of the active area regions . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US6180494B1 CLAIM 1 . A method of fabricating integrated circuitry comprising : forming a conductive line having opposing sidewalls over a semiconductor substrate ; depositing an insulating layer over the substrate and the line ; etching the insulating layer proximate the line along at least a portion of at least one sidewall of the line ; after the etching , depositing an insulating spacer forming layer over the substrate and the line , and anisotropically etching it to form an insulating sidewall spacer along said portion of the at least one sidewall ; forming field isolation material regions and active area regions on the semiconductor substrate before the depositing ; etching a trench into the field isolation material and the insulating layer into a desired local interconnect line configuration ; and forming (anti reflective coating) a local interconnect layer of material over the substrate which at least partially fills the trench and which electrically connects with one of the active area regions . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US6323557B1 Filed: 1999-02-23 Issued: 2001-11-27 Method and structure for improved alignment tolerance in multiple, singulated plugs (Original Assignee) Micron Technology Inc (Current Assignee) Micron Technology Inc Thomas A. Figura |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region (contact region, inner plug) coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US6323557B1 CLAIM 1 . An integrated circuit device on a substrate , comprising : a number of semiconductor surface structures spaced apart along the substrate ; a number of plugs contacting the substrate between the number of surface structures , wherein the number of plugs includes an inner plug (contact region) and a pair of outer plugs , each one of the outer pair being formed adjacent to and on opposing sides of the inner plug , each one of the outer pair having upper portions , wherein the upper portions cover top surfaces of the surface structures , wherein the inner plug is beneath the top surfaces of the surface structures ; an inner electrical contact coupling to the inner plug and separated from the upper portions of the outer plugs by a pair of opposing spacers ; and a pair of outer contact region (contact region) s , wherein each of the outer contact regions couples to one of the outer plugs . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric layer insulates said contact region (contact region, inner plug) . |
US6323557B1 CLAIM 1 . An integrated circuit device on a substrate , comprising : a number of semiconductor surface structures spaced apart along the substrate ; a number of plugs contacting the substrate between the number of surface structures , wherein the number of plugs includes an inner plug (contact region) and a pair of outer plugs , each one of the outer pair being formed adjacent to and on opposing sides of the inner plug , each one of the outer pair having upper portions , wherein the upper portions cover top surfaces of the surface structures , wherein the inner plug is beneath the top surfaces of the surface structures ; an inner electrical contact coupling to the inner plug and separated from the upper portions of the outer plugs by a pair of opposing spacers ; and a pair of outer contact region (contact region) s , wherein each of the outer contact regions couples to one of the outer plugs . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric layer insulates said contact region (contact region, inner plug) . |
US6323557B1 CLAIM 1 . An integrated circuit device on a substrate , comprising : a number of semiconductor surface structures spaced apart along the substrate ; a number of plugs contacting the substrate between the number of surface structures , wherein the number of plugs includes an inner plug (contact region) and a pair of outer plugs , each one of the outer pair being formed adjacent to and on opposing sides of the inner plug , each one of the outer pair having upper portions , wherein the upper portions cover top surfaces of the surface structures , wherein the inner plug is beneath the top surfaces of the surface structures ; an inner electrical contact coupling to the inner plug and separated from the upper portions of the outer plugs by a pair of opposing spacers ; and a pair of outer contact region (contact region) s , wherein each of the outer contact regions couples to one of the outer plugs . |
| US7977797B2 CLAIM 6 . An integrated circuit of claim 1 wherein said spacer region insulates said contact region (contact region, inner plug) . |
US6323557B1 CLAIM 1 . An integrated circuit device on a substrate , comprising : a number of semiconductor surface structures spaced apart along the substrate ; a number of plugs contacting the substrate between the number of surface structures , wherein the number of plugs includes an inner plug (contact region) and a pair of outer plugs , each one of the outer pair being formed adjacent to and on opposing sides of the inner plug , each one of the outer pair having upper portions , wherein the upper portions cover top surfaces of the surface structures , wherein the inner plug is beneath the top surfaces of the surface structures ; an inner electrical contact coupling to the inner plug and separated from the upper portions of the outer plugs by a pair of opposing spacers ; and a pair of outer contact region (contact region) s , wherein each of the outer contact regions couples to one of the outer plugs . |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area of said contact region (contact region, inner plug) permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
US6323557B1 CLAIM 1 . An integrated circuit device on a substrate , comprising : a number of semiconductor surface structures spaced apart along the substrate ; a number of plugs contacting the substrate between the number of surface structures , wherein the number of plugs includes an inner plug (contact region) and a pair of outer plugs , each one of the outer pair being formed adjacent to and on opposing sides of the inner plug , each one of the outer pair having upper portions , wherein the upper portions cover top surfaces of the surface structures , wherein the inner plug is beneath the top surfaces of the surface structures ; an inner electrical contact coupling to the inner plug and separated from the upper portions of the outer plugs by a pair of opposing spacers ; and a pair of outer contact region (contact region) s , wherein each of the outer contact regions couples to one of the outer plugs . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric layer for said contact region (contact region, inner plug) is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US6323557B1 CLAIM 1 . An integrated circuit device on a substrate , comprising : a number of semiconductor surface structures spaced apart along the substrate ; a number of plugs contacting the substrate between the number of surface structures , wherein the number of plugs includes an inner plug (contact region) and a pair of outer plugs , each one of the outer pair being formed adjacent to and on opposing sides of the inner plug , each one of the outer pair having upper portions , wherein the upper portions cover top surfaces of the surface structures , wherein the inner plug is beneath the top surfaces of the surface structures ; an inner electrical contact coupling to the inner plug and separated from the upper portions of the outer plugs by a pair of opposing spacers ; and a pair of outer contact region (contact region) s , wherein each of the outer contact regions couples to one of the outer plugs . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers (adjacent pair) have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region (contact region, inner plug) and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US6323557B1 CLAIM 1 . An integrated circuit device on a substrate , comprising : a number of semiconductor surface structures spaced apart along the substrate ; a number of plugs contacting the substrate between the number of surface structures , wherein the number of plugs includes an inner plug (contact region) and a pair of outer plugs , each one of the outer pair being formed adjacent to and on opposing sides of the inner plug , each one of the outer pair having upper portions , wherein the upper portions cover top surfaces of the surface structures , wherein the inner plug is beneath the top surfaces of the surface structures ; an inner electrical contact coupling to the inner plug and separated from the upper portions of the outer plugs by a pair of opposing spacers ; and a pair of outer contact region (contact region) s , wherein each of the outer contact regions couples to one of the outer plugs . US6323557B1 CLAIM 10 . A memory device , comprising : multiple insulated wordlines having top surfaces , wherein the insulated wordlines are spaced apart from one another and formed on a substrate ; a bitline plug located between an adjacent pair (second etch stop layers) of the insulated wordlines , the bitline plug having a top surface beneath the top surfaces of the insulated wordlines ; a pair of storage node plugs located on the opposite side of the adjacent pair of insulated wordlines from the bitline plug , wherein the pair of storage node plugs each have a top surface above the top surfaces of the insulated wordlines and are formed over portions of the adjacent wordlines ; a buried bitline coupled to the bitline plug ; a pair of opposing spacers located above the adjacent pair of insulated wordlines , wherein the spacers isolate the buried bitline from the pair of storage node plugs ; and a pair of storage node contacts , wherein each of the storage node contacts couples to one of the storage node plugs . |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region (contact region, inner plug) is a first range of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US6323557B1 CLAIM 1 . An integrated circuit device on a substrate , comprising : a number of semiconductor surface structures spaced apart along the substrate ; a number of plugs contacting the substrate between the number of surface structures , wherein the number of plugs includes an inner plug (contact region) and a pair of outer plugs , each one of the outer pair being formed adjacent to and on opposing sides of the inner plug , each one of the outer pair having upper portions , wherein the upper portions cover top surfaces of the surface structures , wherein the inner plug is beneath the top surfaces of the surface structures ; an inner electrical contact coupling to the inner plug and separated from the upper portions of the outer plugs by a pair of opposing spacers ; and a pair of outer contact region (contact region) s , wherein each of the outer contact regions couples to one of the outer plugs . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US20010012688A1 Filed: 1998-09-25 Issued: 2001-08-09 Process for forming miniature contact holes in semiconductor device without short-circuit (Original Assignee) NEC Corp (Current Assignee) NEC Corp Masaki Kawaguchi, Takeo Fujii |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (contact hole) layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US20010012688A1 CLAIM 7 . The process as set forth in claim 1 , in which said target hole serves as a node contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) for a storage node electrode of a dynamic random access memory cell . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (contact hole) layer insulates said contact region . |
US20010012688A1 CLAIM 7 . The process as set forth in claim 1 , in which said target hole serves as a node contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) for a storage node electrode of a dynamic random access memory cell . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (contact hole) layer insulates said contact region . |
US20010012688A1 CLAIM 7 . The process as set forth in claim 1 , in which said target hole serves as a node contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) for a storage node electrode of a dynamic random access memory cell . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (contact hole) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US20010012688A1 CLAIM 7 . The process as set forth in claim 1 , in which said target hole serves as a node contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) for a storage node electrode of a dynamic random access memory cell . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric (contact hole) layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space (storage node) in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US20010012688A1 CLAIM 7 . The process as set forth in claim 1 , in which said target hole serves as a node contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) for a storage node (second space, floating gate) electrode of a dynamic random access memory cell . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (contact hole) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US20010012688A1 CLAIM 7 . The process as set forth in claim 1 , in which said target hole serves as a node contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) for a storage node electrode of a dynamic random access memory cell . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (contact hole) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US20010012688A1 CLAIM 7 . The process as set forth in claim 1 , in which said target hole serves as a node contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) for a storage node electrode of a dynamic random access memory cell . |
| US7977797B2 CLAIM 13 . An integrated circuit of claim 11 further comprising a floating gate (storage node) . |
US20010012688A1 CLAIM 7 . The process as set forth in claim 1 , in which said target hole serves as a node contact hole for a storage node (second space, floating gate) electrode of a dynamic random access memory cell . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US6693335B2 Filed: 1998-09-01 Issued: 2004-02-17 Semiconductor raised source-drain structure (Original Assignee) Micron Technology Inc (Current Assignee) Micron Technology Inc Fernando Gonzalez, Chandra Mouli |
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| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer protects removal of a substrate material by an etch process (dielectric material) . |
US6693335B2 CLAIM 1 . A semiconductor structure , comprising : a raised source ; a raised drain ; a gate located between said source and said drain ; a first capping layer in communication with at least a portion of said gate and said source ; a first portion of a gate oxide region in communication with at least a portion of said gate and said source ; said source ; said gate , said first capping layer , and said first portion of said gate oxide region defining a first gap therein , said first gap having one of a gas and a vacuum therein , wherein no dielectric material (etch process) is positioned between said first gap and any one of said gate , said source , said first capping layer , and said first portion of said gate oxide region ; a second capping layer in communication with at least a portion of said gate and said drain ; a second portion of said gate oxide region in communication with at least a portion of said gate and said drain ; and said drain , said gate , said second capping layer , and said second portion of said gate oxide region defining a second gap therein , said second gap having one of a gas and a vacuum therein , wherein no dielectric material is positioned between said second gap and any one of said gate , said drain , said second capping layer , and said second portion of said gate oxide region . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch stop layer protects lower layers during an etching process (doped polysilicon) . |
US6693335B2 CLAIM 2 . The structure of claim 1 wherein said raised source includes doped polysilicon (etching process) . |
| US7977797B2 CLAIM 13 . An integrated circuit of claim 11 further comprising a floating gate (semiconductor structure) . |
US6693335B2 CLAIM 1 . A semiconductor structure (floating gate) , comprising : a raised source ; a raised drain ; a gate located between said source and said drain ; a first capping layer in communication with at least a portion of said gate and said source ; a first portion of a gate oxide region in communication with at least a portion of said gate and said source ; said source ; said gate , said first capping layer , and said first portion of said gate oxide region defining a first gap therein , said first gap having one of a gas and a vacuum therein , wherein no dielectric material is positioned between said first gap and any one of said gate , said source , said first capping layer , and said first portion of said gate oxide region ; a second capping layer in communication with at least a portion of said gate and said drain ; a second portion of said gate oxide region in communication with at least a portion of said gate and said drain ; and said drain , said gate , said second capping layer , and said second portion of said gate oxide region defining a second gap therein , said second gap having one of a gas and a vacuum therein , wherein no dielectric material is positioned between said second gap and any one of said gate , said drain , said second capping layer , and said second portion of said gate oxide region . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US6162676A Filed: 1998-08-31 Issued: 2000-12-19 Method of making a semiconductor device with an etching stopper (Original Assignee) NEC Corp (Current Assignee) NEC Electronics Corp Hidemitsu Mori |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region (second contact) coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region (inner surfaces) such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer (entire surface) over said first etch stop layer ; a second etch (second etch) stop layer (insulating film) over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US6162676A CLAIM 1 . A method of manufacturing a semiconductor device , comprising the steps of : (a) sequentially forming an etching stopper insulating film (second etch (second etch) stop layer, second interlevel dielectric layer) and a first insulating interlayer on a semiconductor substrate having a semiconductor element formed thereon ; (b) forming at least a pair of first upper contact holes in said first insulating interlayer ; (c) forming first side wall conductive layers on inner surfaces (spacer region) of the respective upper contact holes ; (d) forming lower contact holes in said etching stopper insulating film in the pair of first upper contact holes by using said first side wall conductive layers as a mask so as to reach said semiconductor element ; (e) forming first buried conductive layers by burying conductive layers in the pair of contact holes each constituted by the upper and lower contact holes ; (f) forming a first interconnection above one of said pair of buried conductive layers ; (g) sequentially forming a second etching stopper insulating film and a second insulating interlayer on an entire surface (first sub interlevel dielectric layer) ; (h) forming a second upper contact hole in said second insulating interlayer corresponding to a portion above the other one of said first buried conductive layers ; (i) forming a second side wall conductive layer on an inner surface of the second upper contact hole ; (j) forming a second lower contact hole in said second etching stopper insulating film in the second upper contact hole by using said second side wall conductive layer as a mask so as to reach said first buried conductive layer , the second lower contact hole and the second upper contact hole forming a second contact (contact region) hole ; and (k) forming a second buried conductive layer in the second contact hole and a second interconnection integrally connected to said second buried conductive layer . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric layer (entire surface) insulates said contact region (second contact) . |
US6162676A CLAIM 1 . A method of manufacturing a semiconductor device , comprising the steps of : (a) sequentially forming an etching stopper insulating film and a first insulating interlayer on a semiconductor substrate having a semiconductor element formed thereon ; (b) forming at least a pair of first upper contact holes in said first insulating interlayer ; (c) forming first side wall conductive layers on inner surfaces of the respective upper contact holes ; (d) forming lower contact holes in said etching stopper insulating film in the pair of first upper contact holes by using said first side wall conductive layers as a mask so as to reach said semiconductor element ; (e) forming first buried conductive layers by burying conductive layers in the pair of contact holes each constituted by the upper and lower contact holes ; (f) forming a first interconnection above one of said pair of buried conductive layers ; (g) sequentially forming a second etching stopper insulating film and a second insulating interlayer on an entire surface (first sub interlevel dielectric layer) ; (h) forming a second upper contact hole in said second insulating interlayer corresponding to a portion above the other one of said first buried conductive layers ; (i) forming a second side wall conductive layer on an inner surface of the second upper contact hole ; (j) forming a second lower contact hole in said second etching stopper insulating film in the second upper contact hole by using said second side wall conductive layer as a mask so as to reach said first buried conductive layer , the second lower contact hole and the second upper contact hole forming a second contact (contact region) hole ; and (k) forming a second buried conductive layer in the second contact hole and a second interconnection integrally connected to said second buried conductive layer . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch (second etch) stop layer (insulating film) protects lower layers during an etching process . |
US6162676A CLAIM 1 . A method of manufacturing a semiconductor device , comprising the steps of : (a) sequentially forming an etching stopper insulating film (second etch (second etch) stop layer, second interlevel dielectric layer) and a first insulating interlayer on a semiconductor substrate having a semiconductor element formed thereon ; (b) forming at least a pair of first upper contact holes in said first insulating interlayer ; (c) forming first side wall conductive layers on inner surfaces of the respective upper contact holes ; (d) forming lower contact holes in said etching stopper insulating film in the pair of first upper contact holes by using said first side wall conductive layers as a mask so as to reach said semiconductor element ; (e) forming first buried conductive layers by burying conductive layers in the pair of contact holes each constituted by the upper and lower contact holes ; (f) forming a first interconnection above one of said pair of buried conductive layers ; (g) sequentially forming a second etching stopper insulating film and a second insulating interlayer on an entire surface ; (h) forming a second upper contact hole in said second insulating interlayer corresponding to a portion above the other one of said first buried conductive layers ; (i) forming a second side wall conductive layer on an inner surface of the second upper contact hole ; (j) forming a second lower contact hole in said second etching stopper insulating film in the second upper contact hole by using said second side wall conductive layer as a mask so as to reach said first buried conductive layer , the second lower contact hole and the second upper contact hole forming a second contact hole ; and (k) forming a second buried conductive layer in the second contact hole and a second interconnection integrally connected to said second buried conductive layer . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric layer insulates said contact region (second contact) . |
US6162676A CLAIM 1 . A method of manufacturing a semiconductor device , comprising the steps of : (a) sequentially forming an etching stopper insulating film and a first insulating interlayer on a semiconductor substrate having a semiconductor element formed thereon ; (b) forming at least a pair of first upper contact holes in said first insulating interlayer ; (c) forming first side wall conductive layers on inner surfaces of the respective upper contact holes ; (d) forming lower contact holes in said etching stopper insulating film in the pair of first upper contact holes by using said first side wall conductive layers as a mask so as to reach said semiconductor element ; (e) forming first buried conductive layers by burying conductive layers in the pair of contact holes each constituted by the upper and lower contact holes ; (f) forming a first interconnection above one of said pair of buried conductive layers ; (g) sequentially forming a second etching stopper insulating film and a second insulating interlayer on an entire surface ; (h) forming a second upper contact hole in said second insulating interlayer corresponding to a portion above the other one of said first buried conductive layers ; (i) forming a second side wall conductive layer on an inner surface of the second upper contact hole ; (j) forming a second lower contact hole in said second etching stopper insulating film in the second upper contact hole by using said second side wall conductive layer as a mask so as to reach said first buried conductive layer , the second lower contact hole and the second upper contact hole forming a second contact (contact region) hole ; and (k) forming a second buried conductive layer in the second contact hole and a second interconnection integrally connected to said second buried conductive layer . |
| US7977797B2 CLAIM 6 . An integrated circuit of claim 1 wherein said spacer region (inner surfaces) insulates said contact region (second contact) . |
US6162676A CLAIM 1 . A method of manufacturing a semiconductor device , comprising the steps of : (a) sequentially forming an etching stopper insulating film and a first insulating interlayer on a semiconductor substrate having a semiconductor element formed thereon ; (b) forming at least a pair of first upper contact holes in said first insulating interlayer ; (c) forming first side wall conductive layers on inner surfaces (spacer region) of the respective upper contact holes ; (d) forming lower contact holes in said etching stopper insulating film in the pair of first upper contact holes by using said first side wall conductive layers as a mask so as to reach said semiconductor element ; (e) forming first buried conductive layers by burying conductive layers in the pair of contact holes each constituted by the upper and lower contact holes ; (f) forming a first interconnection above one of said pair of buried conductive layers ; (g) sequentially forming a second etching stopper insulating film and a second insulating interlayer on an entire surface ; (h) forming a second upper contact hole in said second insulating interlayer corresponding to a portion above the other one of said first buried conductive layers ; (i) forming a second side wall conductive layer on an inner surface of the second upper contact hole ; (j) forming a second lower contact hole in said second etching stopper insulating film in the second upper contact hole by using said second side wall conductive layer as a mask so as to reach said first buried conductive layer , the second lower contact hole and the second upper contact hole forming a second contact (contact region) hole ; and (k) forming a second buried conductive layer in the second contact hole and a second interconnection integrally connected to said second buried conductive layer . |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area of said contact region (second contact) permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
US6162676A CLAIM 1 . A method of manufacturing a semiconductor device , comprising the steps of : (a) sequentially forming an etching stopper insulating film and a first insulating interlayer on a semiconductor substrate having a semiconductor element formed thereon ; (b) forming at least a pair of first upper contact holes in said first insulating interlayer ; (c) forming first side wall conductive layers on inner surfaces of the respective upper contact holes ; (d) forming lower contact holes in said etching stopper insulating film in the pair of first upper contact holes by using said first side wall conductive layers as a mask so as to reach said semiconductor element ; (e) forming first buried conductive layers by burying conductive layers in the pair of contact holes each constituted by the upper and lower contact holes ; (f) forming a first interconnection above one of said pair of buried conductive layers ; (g) sequentially forming a second etching stopper insulating film and a second insulating interlayer on an entire surface ; (h) forming a second upper contact hole in said second insulating interlayer corresponding to a portion above the other one of said first buried conductive layers ; (i) forming a second side wall conductive layer on an inner surface of the second upper contact hole ; (j) forming a second lower contact hole in said second etching stopper insulating film in the second upper contact hole by using said second side wall conductive layer as a mask so as to reach said first buried conductive layer , the second lower contact hole and the second upper contact hole forming a second contact (contact region) hole ; and (k) forming a second buried conductive layer in the second contact hole and a second interconnection integrally connected to said second buried conductive layer . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer (entire surface) is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (second etch) stop layer (insulating film) is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6162676A CLAIM 1 . A method of manufacturing a semiconductor device , comprising the steps of : (a) sequentially forming an etching stopper insulating film (second etch (second etch) stop layer, second interlevel dielectric layer) and a first insulating interlayer on a semiconductor substrate having a semiconductor element formed thereon ; (b) forming at least a pair of first upper contact holes in said first insulating interlayer ; (c) forming first side wall conductive layers on inner surfaces of the respective upper contact holes ; (d) forming lower contact holes in said etching stopper insulating film in the pair of first upper contact holes by using said first side wall conductive layers as a mask so as to reach said semiconductor element ; (e) forming first buried conductive layers by burying conductive layers in the pair of contact holes each constituted by the upper and lower contact holes ; (f) forming a first interconnection above one of said pair of buried conductive layers ; (g) sequentially forming a second etching stopper insulating film and a second insulating interlayer on an entire surface (first sub interlevel dielectric layer) ; (h) forming a second upper contact hole in said second insulating interlayer corresponding to a portion above the other one of said first buried conductive layers ; (i) forming a second side wall conductive layer on an inner surface of the second upper contact hole ; (j) forming a second lower contact hole in said second etching stopper insulating film in the second upper contact hole by using said second side wall conductive layer as a mask so as to reach said first buried conductive layer , the second lower contact hole and the second upper contact hole forming a second contact hole ; and (k) forming a second buried conductive layer in the second contact hole and a second interconnection integrally connected to said second buried conductive layer . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric layer (entire surface) for said contact region (second contact) is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US6162676A CLAIM 1 . A method of manufacturing a semiconductor device , comprising the steps of : (a) sequentially forming an etching stopper insulating film and a first insulating interlayer on a semiconductor substrate having a semiconductor element formed thereon ; (b) forming at least a pair of first upper contact holes in said first insulating interlayer ; (c) forming first side wall conductive layers on inner surfaces of the respective upper contact holes ; (d) forming lower contact holes in said etching stopper insulating film in the pair of first upper contact holes by using said first side wall conductive layers as a mask so as to reach said semiconductor element ; (e) forming first buried conductive layers by burying conductive layers in the pair of contact holes each constituted by the upper and lower contact holes ; (f) forming a first interconnection above one of said pair of buried conductive layers ; (g) sequentially forming a second etching stopper insulating film and a second insulating interlayer on an entire surface (first sub interlevel dielectric layer) ; (h) forming a second upper contact hole in said second insulating interlayer corresponding to a portion above the other one of said first buried conductive layers ; (i) forming a second side wall conductive layer on an inner surface of the second upper contact hole ; (j) forming a second lower contact hole in said second etching stopper insulating film in the second upper contact hole by using said second side wall conductive layer as a mask so as to reach said first buried conductive layer , the second lower contact hole and the second upper contact hole forming a second contact (contact region) hole ; and (k) forming a second buried conductive layer in the second contact hole and a second interconnection integrally connected to said second buried conductive layer . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch (second etch) stop layer (insulating film) wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region (second contact) and under a first sub interlevel dielectric layer (entire surface) and said second etch stop layer formed under a second interlevel dielectric layer (insulating film) , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US6162676A CLAIM 1 . A method of manufacturing a semiconductor device , comprising the steps of : (a) sequentially forming an etching stopper insulating film (second etch (second etch) stop layer, second interlevel dielectric layer) and a first insulating interlayer on a semiconductor substrate having a semiconductor element formed thereon ; (b) forming at least a pair of first upper contact holes in said first insulating interlayer ; (c) forming first side wall conductive layers on inner surfaces of the respective upper contact holes ; (d) forming lower contact holes in said etching stopper insulating film in the pair of first upper contact holes by using said first side wall conductive layers as a mask so as to reach said semiconductor element ; (e) forming first buried conductive layers by burying conductive layers in the pair of contact holes each constituted by the upper and lower contact holes ; (f) forming a first interconnection above one of said pair of buried conductive layers ; (g) sequentially forming a second etching stopper insulating film and a second insulating interlayer on an entire surface (first sub interlevel dielectric layer) ; (h) forming a second upper contact hole in said second insulating interlayer corresponding to a portion above the other one of said first buried conductive layers ; (i) forming a second side wall conductive layer on an inner surface of the second upper contact hole ; (j) forming a second lower contact hole in said second etching stopper insulating film in the second upper contact hole by using said second side wall conductive layer as a mask so as to reach said first buried conductive layer , the second lower contact hole and the second upper contact hole forming a second contact (contact region) hole ; and (k) forming a second buried conductive layer in the second contact hole and a second interconnection integrally connected to said second buried conductive layer . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer (entire surface) is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (second etch) stop layer (insulating film) is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6162676A CLAIM 1 . A method of manufacturing a semiconductor device , comprising the steps of : (a) sequentially forming an etching stopper insulating film (second etch (second etch) stop layer, second interlevel dielectric layer) and a first insulating interlayer on a semiconductor substrate having a semiconductor element formed thereon ; (b) forming at least a pair of first upper contact holes in said first insulating interlayer ; (c) forming first side wall conductive layers on inner surfaces of the respective upper contact holes ; (d) forming lower contact holes in said etching stopper insulating film in the pair of first upper contact holes by using said first side wall conductive layers as a mask so as to reach said semiconductor element ; (e) forming first buried conductive layers by burying conductive layers in the pair of contact holes each constituted by the upper and lower contact holes ; (f) forming a first interconnection above one of said pair of buried conductive layers ; (g) sequentially forming a second etching stopper insulating film and a second insulating interlayer on an entire surface (first sub interlevel dielectric layer) ; (h) forming a second upper contact hole in said second insulating interlayer corresponding to a portion above the other one of said first buried conductive layers ; (i) forming a second side wall conductive layer on an inner surface of the second upper contact hole ; (j) forming a second lower contact hole in said second etching stopper insulating film in the second upper contact hole by using said second side wall conductive layer as a mask so as to reach said first buried conductive layer , the second lower contact hole and the second upper contact hole forming a second contact hole ; and (k) forming a second buried conductive layer in the second contact hole and a second interconnection integrally connected to said second buried conductive layer . |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region (second contact) is a first range of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US6162676A CLAIM 1 . A method of manufacturing a semiconductor device , comprising the steps of : (a) sequentially forming an etching stopper insulating film and a first insulating interlayer on a semiconductor substrate having a semiconductor element formed thereon ; (b) forming at least a pair of first upper contact holes in said first insulating interlayer ; (c) forming first side wall conductive layers on inner surfaces of the respective upper contact holes ; (d) forming lower contact holes in said etching stopper insulating film in the pair of first upper contact holes by using said first side wall conductive layers as a mask so as to reach said semiconductor element ; (e) forming first buried conductive layers by burying conductive layers in the pair of contact holes each constituted by the upper and lower contact holes ; (f) forming a first interconnection above one of said pair of buried conductive layers ; (g) sequentially forming a second etching stopper insulating film and a second insulating interlayer on an entire surface ; (h) forming a second upper contact hole in said second insulating interlayer corresponding to a portion above the other one of said first buried conductive layers ; (i) forming a second side wall conductive layer on an inner surface of the second upper contact hole ; (j) forming a second lower contact hole in said second etching stopper insulating film in the second upper contact hole by using said second side wall conductive layer as a mask so as to reach said first buried conductive layer , the second lower contact hole and the second upper contact hole forming a second contact (contact region) hole ; and (k) forming a second buried conductive layer in the second contact hole and a second interconnection integrally connected to said second buried conductive layer . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US6255686B1 Filed: 1998-07-30 Issued: 2001-07-03 Semiconductor storage device including short circuit avoiding structure and method of fabricating thereof (Original Assignee) Nippon Steel Corp (Current Assignee) United Microelectronics Corp Hideki Takeuchi, Hirohiko Izumi |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region (second contact) coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (upper electrodes, like shape) of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch (isolation structure) stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US6255686B1 CLAIM 1 . A semiconductor storage device , comprising : a semiconductor substrate having a device activation region defined by a device isolation structure (first etch, first etch stop layer) ; an access transistor formed at said device activation region in said semiconductor substrate , and having a gate electrode and a pair of impurity diffusion layers ; a first insulating film formed over said access transistor , and having a first contact hole for exposing a portion of a surface of one of said pair of impurity diffusion layers ; a protective film formed on said first insulating film , and having a second contact (contact region) hole formed on said first contact hole ; a second insulating film formed on a side wall face of said first contact hole in said first insulating film and on a side wall face of said second contact hole in said protective film ; and a memory capacitor in which a lower electrode and an upper electrode are opposed to each other and capacitive-coupled through a dielectric film , wherein said lower electrode of said memory capacitor is filled inside said first and second contact holes to be formed in an mushroom-shaped shape on said first insulating film through said protective film so as to be electrically connected with the one of said pair of impurity diffusion layers . US6255686B1 CLAIM 3 . A semiconductor storage device as claimed in claim 1 , wherein each of said lower and upper electrodes (metal layer coupling area) of said memory capacitor is made of a polycrystal silicon film . US6255686B1 CLAIM 5 . A semiconductor storage device as claimed in claim 1 , wherein said protective film is a polycrystal silicon film , and is formed only between said island-like shape (metal layer coupling area) d lower electrode and said first insulating film . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch (isolation structure) stop layer protects removal of a substrate material by an etch process . |
US6255686B1 CLAIM 1 . A semiconductor storage device , comprising : a semiconductor substrate having a device activation region defined by a device isolation structure (first etch, first etch stop layer) ; an access transistor formed at said device activation region in said semiconductor substrate , and having a gate electrode and a pair of impurity diffusion layers ; a first insulating film formed over said access transistor , and having a first contact hole for exposing a portion of a surface of one of said pair of impurity diffusion layers ; a protective film formed on said first insulating film , and having a second contact hole formed on said first contact hole ; a second insulating film formed on a side wall face of said first contact hole in said first insulating film and on a side wall face of said second contact hole in said protective film ; and a memory capacitor in which a lower electrode and an upper electrode are opposed to each other and capacitive-coupled through a dielectric film , wherein said lower electrode of said memory capacitor is filled inside said first and second contact holes to be formed in an mushroom-shaped shape on said first insulating film through said protective film so as to be electrically connected with the one of said pair of impurity diffusion layers . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric layer insulates said contact region (second contact) . |
US6255686B1 CLAIM 1 . A semiconductor storage device , comprising : a semiconductor substrate having a device activation region defined by a device isolation structure ; an access transistor formed at said device activation region in said semiconductor substrate , and having a gate electrode and a pair of impurity diffusion layers ; a first insulating film formed over said access transistor , and having a first contact hole for exposing a portion of a surface of one of said pair of impurity diffusion layers ; a protective film formed on said first insulating film , and having a second contact (contact region) hole formed on said first contact hole ; a second insulating film formed on a side wall face of said first contact hole in said first insulating film and on a side wall face of said second contact hole in said protective film ; and a memory capacitor in which a lower electrode and an upper electrode are opposed to each other and capacitive-coupled through a dielectric film , wherein said lower electrode of said memory capacitor is filled inside said first and second contact holes to be formed in an mushroom-shaped shape on said first insulating film through said protective film so as to be electrically connected with the one of said pair of impurity diffusion layers . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric layer insulates said contact region (second contact) . |
US6255686B1 CLAIM 1 . A semiconductor storage device , comprising : a semiconductor substrate having a device activation region defined by a device isolation structure ; an access transistor formed at said device activation region in said semiconductor substrate , and having a gate electrode and a pair of impurity diffusion layers ; a first insulating film formed over said access transistor , and having a first contact hole for exposing a portion of a surface of one of said pair of impurity diffusion layers ; a protective film formed on said first insulating film , and having a second contact (contact region) hole formed on said first contact hole ; a second insulating film formed on a side wall face of said first contact hole in said first insulating film and on a side wall face of said second contact hole in said protective film ; and a memory capacitor in which a lower electrode and an upper electrode are opposed to each other and capacitive-coupled through a dielectric film , wherein said lower electrode of said memory capacitor is filled inside said first and second contact holes to be formed in an mushroom-shaped shape on said first insulating film through said protective film so as to be electrically connected with the one of said pair of impurity diffusion layers . |
| US7977797B2 CLAIM 6 . An integrated circuit of claim 1 wherein said spacer region insulates said contact region (second contact) . |
US6255686B1 CLAIM 1 . A semiconductor storage device , comprising : a semiconductor substrate having a device activation region defined by a device isolation structure ; an access transistor formed at said device activation region in said semiconductor substrate , and having a gate electrode and a pair of impurity diffusion layers ; a first insulating film formed over said access transistor , and having a first contact hole for exposing a portion of a surface of one of said pair of impurity diffusion layers ; a protective film formed on said first insulating film , and having a second contact (contact region) hole formed on said first contact hole ; a second insulating film formed on a side wall face of said first contact hole in said first insulating film and on a side wall face of said second contact hole in said protective film ; and a memory capacitor in which a lower electrode and an upper electrode are opposed to each other and capacitive-coupled through a dielectric film , wherein said lower electrode of said memory capacitor is filled inside said first and second contact holes to be formed in an mushroom-shaped shape on said first insulating film through said protective film so as to be electrically connected with the one of said pair of impurity diffusion layers . |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area of said contact region (second contact) permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area (upper electrodes, like shape) of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
US6255686B1 CLAIM 1 . A semiconductor storage device , comprising : a semiconductor substrate having a device activation region defined by a device isolation structure ; an access transistor formed at said device activation region in said semiconductor substrate , and having a gate electrode and a pair of impurity diffusion layers ; a first insulating film formed over said access transistor , and having a first contact hole for exposing a portion of a surface of one of said pair of impurity diffusion layers ; a protective film formed on said first insulating film , and having a second contact (contact region) hole formed on said first contact hole ; a second insulating film formed on a side wall face of said first contact hole in said first insulating film and on a side wall face of said second contact hole in said protective film ; and a memory capacitor in which a lower electrode and an upper electrode are opposed to each other and capacitive-coupled through a dielectric film , wherein said lower electrode of said memory capacitor is filled inside said first and second contact holes to be formed in an mushroom-shaped shape on said first insulating film through said protective film so as to be electrically connected with the one of said pair of impurity diffusion layers . US6255686B1 CLAIM 3 . A semiconductor storage device as claimed in claim 1 , wherein each of said lower and upper electrodes (metal layer coupling area) of said memory capacitor is made of a polycrystal silicon film . US6255686B1 CLAIM 5 . A semiconductor storage device as claimed in claim 1 , wherein said protective film is a polycrystal silicon film , and is formed only between said island-like shape (metal layer coupling area) d lower electrode and said first insulating film . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch (isolation structure) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6255686B1 CLAIM 1 . A semiconductor storage device , comprising : a semiconductor substrate having a device activation region defined by a device isolation structure (first etch, first etch stop layer) ; an access transistor formed at said device activation region in said semiconductor substrate , and having a gate electrode and a pair of impurity diffusion layers ; a first insulating film formed over said access transistor , and having a first contact hole for exposing a portion of a surface of one of said pair of impurity diffusion layers ; a protective film formed on said first insulating film , and having a second contact hole formed on said first contact hole ; a second insulating film formed on a side wall face of said first contact hole in said first insulating film and on a side wall face of said second contact hole in said protective film ; and a memory capacitor in which a lower electrode and an upper electrode are opposed to each other and capacitive-coupled through a dielectric film , wherein said lower electrode of said memory capacitor is filled inside said first and second contact holes to be formed in an mushroom-shaped shape on said first insulating film through said protective film so as to be electrically connected with the one of said pair of impurity diffusion layers . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric layer for said contact region (second contact) is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US6255686B1 CLAIM 1 . A semiconductor storage device , comprising : a semiconductor substrate having a device activation region defined by a device isolation structure ; an access transistor formed at said device activation region in said semiconductor substrate , and having a gate electrode and a pair of impurity diffusion layers ; a first insulating film formed over said access transistor , and having a first contact hole for exposing a portion of a surface of one of said pair of impurity diffusion layers ; a protective film formed on said first insulating film , and having a second contact (contact region) hole formed on said first contact hole ; a second insulating film formed on a side wall face of said first contact hole in said first insulating film and on a side wall face of said second contact hole in said protective film ; and a memory capacitor in which a lower electrode and an upper electrode are opposed to each other and capacitive-coupled through a dielectric film , wherein said lower electrode of said memory capacitor is filled inside said first and second contact holes to be formed in an mushroom-shaped shape on said first insulating film through said protective film so as to be electrically connected with the one of said pair of impurity diffusion layers . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch (isolation structure) stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region (second contact) and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom (lower electrode) , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (upper electrodes, like shape) of said contact region . |
US6255686B1 CLAIM 1 . A semiconductor storage device , comprising : a semiconductor substrate having a device activation region defined by a device isolation structure (first etch, first etch stop layer) ; an access transistor formed at said device activation region in said semiconductor substrate , and having a gate electrode and a pair of impurity diffusion layers ; a first insulating film formed over said access transistor , and having a first contact hole for exposing a portion of a surface of one of said pair of impurity diffusion layers ; a protective film formed on said first insulating film , and having a second contact (contact region) hole formed on said first contact hole ; a second insulating film formed on a side wall face of said first contact hole in said first insulating film and on a side wall face of said second contact hole in said protective film ; and a memory capacitor in which a lower electrode (contact bottom) and an upper electrode are opposed to each other and capacitive-coupled through a dielectric film , wherein said lower electrode of said memory capacitor is filled inside said first and second contact holes to be formed in an mushroom-shaped shape on said first insulating film through said protective film so as to be electrically connected with the one of said pair of impurity diffusion layers . US6255686B1 CLAIM 3 . A semiconductor storage device as claimed in claim 1 , wherein each of said lower and upper electrodes (metal layer coupling area) of said memory capacitor is made of a polycrystal silicon film . US6255686B1 CLAIM 5 . A semiconductor storage device as claimed in claim 1 , wherein said protective film is a polycrystal silicon film , and is formed only between said island-like shape (metal layer coupling area) d lower electrode and said first insulating film . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch (isolation structure) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6255686B1 CLAIM 1 . A semiconductor storage device , comprising : a semiconductor substrate having a device activation region defined by a device isolation structure (first etch, first etch stop layer) ; an access transistor formed at said device activation region in said semiconductor substrate , and having a gate electrode and a pair of impurity diffusion layers ; a first insulating film formed over said access transistor , and having a first contact hole for exposing a portion of a surface of one of said pair of impurity diffusion layers ; a protective film formed on said first insulating film , and having a second contact hole formed on said first contact hole ; a second insulating film formed on a side wall face of said first contact hole in said first insulating film and on a side wall face of said second contact hole in said protective film ; and a memory capacitor in which a lower electrode and an upper electrode are opposed to each other and capacitive-coupled through a dielectric film , wherein said lower electrode of said memory capacitor is filled inside said first and second contact holes to be formed in an mushroom-shaped shape on said first insulating film through said protective film so as to be electrically connected with the one of said pair of impurity diffusion layers . |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region (second contact) is a first range of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US6255686B1 CLAIM 1 . A semiconductor storage device , comprising : a semiconductor substrate having a device activation region defined by a device isolation structure ; an access transistor formed at said device activation region in said semiconductor substrate , and having a gate electrode and a pair of impurity diffusion layers ; a first insulating film formed over said access transistor , and having a first contact hole for exposing a portion of a surface of one of said pair of impurity diffusion layers ; a protective film formed on said first insulating film , and having a second contact (contact region) hole formed on said first contact hole ; a second insulating film formed on a side wall face of said first contact hole in said first insulating film and on a side wall face of said second contact hole in said protective film ; and a memory capacitor in which a lower electrode and an upper electrode are opposed to each other and capacitive-coupled through a dielectric film , wherein said lower electrode of said memory capacitor is filled inside said first and second contact holes to be formed in an mushroom-shaped shape on said first insulating film through said protective film so as to be electrically connected with the one of said pair of impurity diffusion layers . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | JPH11168199A Filed: 1997-12-02 Issued: 1999-06-22 半導体記憶装置及びその製造方法 (Original Assignee) Nippon Steel Corp; 新日本製鐵株式会社 Hideki Takeuchi, 英樹 武内 |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (製造方法) of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (キャパシタ, 誘電体膜) layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
JPH11168199A CLAIM 1 【請求項１】 半導体基板上で素子分離構造により画定 された素子活性領域に、ゲート及び一対の不純物拡散層 を有するアクセストランジスタと、下部電極と上部電極 とが誘電体膜 (interlevel dielectric, second interlevel dielectric layer) を介して対向して容量結合するメモリキャ パシタとを備えた半導体記憶装置において、 前記アクセストランジスタを覆う第１の絶縁膜及び前記 第１の絶縁膜上に形成された保護膜を穿って一方の前記 不純物拡散層の表面の一部を露出させる開孔が形成され ているとともに、前記開孔の側壁面を覆う第２の絶縁膜 が形成されており、 前記メモリキャパシタ (interlevel dielectric, second interlevel dielectric layer) の前記下部電極は、前記開孔を前 記第２の絶縁膜を介して充填して前記一方の前記不純物 拡散層と接続されるとともに、前記保護膜を介して前記 第１の絶縁膜上に島状に立設されていることを特徴とす る半導体記憶装置。 JPH11168199A CLAIM 6 【請求項６】 前記下部電極の下部にビット線が形成さ れており、前記開孔の前記側壁面の少なくとも (second sub interlevel dielectric layer) 近傍に前 記ビット線が位置し、前記第２の絶縁膜により前記下部 電極と前記ビット線とが絶縁されていることを特徴とす る請求項１〜５のいずれか１項に記載の半導体記憶装 置。 JPH11168199A CLAIM 10 【請求項１０】 半導体基板上で素子分離構造により画 定された素子活性領域に、ゲート及び一対の不純物拡散 層を有するアクセストランジスタと、下部電極と上部電 極とが誘電体膜を介して対向して容量結合するメモリキ ャパシタとを備えた半導体記憶装置の製造方法 (metal layer coupling area) におい て、 前記アクセストランジスタを覆う第１の絶縁膜を形成す る第１の工程と、 前記第１の絶縁膜上に保護膜を形成する第２の工程と、 前記第１の絶縁膜及び前記保護膜をパターニングし、一 方の前記不純物拡散層の表面の一部を露出させる開孔を 形成する第３の工程と、 前記開孔内を含む前記保護膜の全面に第２の絶縁膜を堆 積する第４の工程と、 前記保護膜をストッパーとして前記第２の絶縁膜の全面 をエッチングし、前記開孔内の側壁面のみに前記第２の 絶縁膜を残す第５の工程と、 前記開孔内を前記第２の絶縁膜を介して充填するととも に前記保護膜上を覆うように導電膜を形成する第６の工 程と、 前記導電膜をパターニングし、前記開孔を通じて前記一 方の前記不純物拡散層と接続されるとともに前記保護膜 上に立設されるように島状の前記下部電極を形成する第 ７の工程とを有することを特徴とする半導体記憶装置の 製造方法。 |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (キャパシタ, 誘電体膜) layer insulates said contact region . |
JPH11168199A CLAIM 1 【請求項１】 半導体基板上で素子分離構造により画定 された素子活性領域に、ゲート及び一対の不純物拡散層 を有するアクセストランジスタと、下部電極と上部電極 とが誘電体膜 (interlevel dielectric, second interlevel dielectric layer) を介して対向して容量結合するメモリキャ パシタとを備えた半導体記憶装置において、 前記アクセストランジスタを覆う第１の絶縁膜及び前記 第１の絶縁膜上に形成された保護膜を穿って一方の前記 不純物拡散層の表面の一部を露出させる開孔が形成され ているとともに、前記開孔の側壁面を覆う第２の絶縁膜 が形成されており、 前記メモリキャパシタ (interlevel dielectric, second interlevel dielectric layer) の前記下部電極は、前記開孔を前 記第２の絶縁膜を介して充填して前記一方の前記不純物 拡散層と接続されるとともに、前記保護膜を介して前記 第１の絶縁膜上に島状に立設されていることを特徴とす る半導体記憶装置。 |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (キャパシタ, 誘電体膜) layer insulates said contact region . |
JPH11168199A CLAIM 1 【請求項１】 半導体基板上で素子分離構造により画定 された素子活性領域に、ゲート及び一対の不純物拡散層 を有するアクセストランジスタと、下部電極と上部電極 とが誘電体膜 (interlevel dielectric, second interlevel dielectric layer) を介して対向して容量結合するメモリキャ パシタとを備えた半導体記憶装置において、 前記アクセストランジスタを覆う第１の絶縁膜及び前記 第１の絶縁膜上に形成された保護膜を穿って一方の前記 不純物拡散層の表面の一部を露出させる開孔が形成され ているとともに、前記開孔の側壁面を覆う第２の絶縁膜 が形成されており、 前記メモリキャパシタ (interlevel dielectric, second interlevel dielectric layer) の前記下部電極は、前記開孔を前 記第２の絶縁膜を介して充填して前記一方の前記不純物 拡散層と接続されるとともに、前記保護膜を介して前記 第１の絶縁膜上に島状に立設されていることを特徴とす る半導体記憶装置。 JPH11168199A CLAIM 6 【請求項６】 前記下部電極の下部にビット線が形成さ れており、前記開孔の前記側壁面の少なくとも (second sub interlevel dielectric layer) 近傍に前 記ビット線が位置し、前記第２の絶縁膜により前記下部 電極と前記ビット線とが絶縁されていることを特徴とす る請求項１〜５のいずれか１項に記載の半導体記憶装 置。 |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area of said contact region permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area (製造方法) of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
JPH11168199A CLAIM 10 【請求項１０】 半導体基板上で素子分離構造により画 定された素子活性領域に、ゲート及び一対の不純物拡散 層を有するアクセストランジスタと、下部電極と上部電 極とが誘電体膜を介して対向して容量結合するメモリキ ャパシタとを備えた半導体記憶装置の製造方法 (metal layer coupling area) におい て、 前記アクセストランジスタを覆う第１の絶縁膜を形成す る第１の工程と、 前記第１の絶縁膜上に保護膜を形成する第２の工程と、 前記第１の絶縁膜及び前記保護膜をパターニングし、一 方の前記不純物拡散層の表面の一部を露出させる開孔を 形成する第３の工程と、 前記開孔内を含む前記保護膜の全面に第２の絶縁膜を堆 積する第４の工程と、 前記保護膜をストッパーとして前記第２の絶縁膜の全面 をエッチングし、前記開孔内の側壁面のみに前記第２の 絶縁膜を残す第５の工程と、 前記開孔内を前記第２の絶縁膜を介して充填するととも に前記保護膜上を覆うように導電膜を形成する第６の工 程と、 前記導電膜をパターニングし、前記開孔を通じて前記一 方の前記不純物拡散層と接続されるとともに前記保護膜 上に立設されるように島状の前記下部電極を形成する第 ７の工程とを有することを特徴とする半導体記憶装置の 製造方法。 |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Å thick , said first sub interlevel dielectric (キャパシタ, 誘電体膜) layer is in a range of about 1 , 000 to 2 , 000 Å thick , said second etch stop layer is in a range of about 300 to 800 Å thick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Å thick . |
JPH11168199A CLAIM 1 【請求項１】 半導体基板上で素子分離構造により画定 された素子活性領域に、ゲート及び一対の不純物拡散層 を有するアクセストランジスタと、下部電極と上部電極 とが誘電体膜 (interlevel dielectric, second interlevel dielectric layer) を介して対向して容量結合するメモリキャ パシタとを備えた半導体記憶装置において、 前記アクセストランジスタを覆う第１の絶縁膜及び前記 第１の絶縁膜上に形成された保護膜を穿って一方の前記 不純物拡散層の表面の一部を露出させる開孔が形成され ているとともに、前記開孔の側壁面を覆う第２の絶縁膜 が形成されており、 前記メモリキャパシタ (interlevel dielectric, second interlevel dielectric layer) の前記下部電極は、前記開孔を前 記第２の絶縁膜を介して充填して前記一方の前記不純物 拡散層と接続されるとともに、前記保護膜を介して前記 第１の絶縁膜上に島状に立設されていることを特徴とす る半導体記憶装置。 JPH11168199A CLAIM 6 【請求項６】 前記下部電極の下部にビット線が形成さ れており、前記開孔の前記側壁面の少なくとも (second sub interlevel dielectric layer) 近傍に前 記ビット線が位置し、前記第２の絶縁膜により前記下部 電極と前記ビット線とが絶縁されていることを特徴とす る請求項１〜５のいずれか１項に記載の半導体記憶装 置。 |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space (前記保) in a portion of said first sub interlevel dielectric (キャパシタ, 誘電体膜) layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range (あること) of about 0 . 16 μm to 0 . 18 μm wide . |
JPH11168199A CLAIM 1 【請求項１】 半導体基板上で素子分離構造により画定 された素子活性領域に、ゲート及び一対の不純物拡散層 を有するアクセストランジスタと、下部電極と上部電極 とが誘電体膜 (interlevel dielectric, second interlevel dielectric layer) を介して対向して容量結合するメモリキャ パシタとを備えた半導体記憶装置において、 前記アクセストランジスタを覆う第１の絶縁膜及び前記 第１の絶縁膜上に形成された保護膜を穿って一方の前記 不純物拡散層の表面の一部を露出させる開孔が形成され ているとともに、前記開孔の側壁面を覆う第２の絶縁膜 が形成されており、 前記メモリキャパシタ (interlevel dielectric, second interlevel dielectric layer) の前記下部電極は、前記開孔を前 記第２の絶縁膜を介して充填して前記一方の前記不純物 拡散層と接続されるとともに、前記保 (first space) 護膜を介して前記 第１の絶縁膜上に島状に立設されていることを特徴とす る半導体記憶装置。 JPH11168199A CLAIM 4 【請求項４】 前記保護膜がシリコン窒化膜であること (second range) を特徴とする請求項１〜３のいずれか１項に記載の半導 体記憶装置。 JPH11168199A CLAIM 6 【請求項６】 前記下部電極の下部にビット線が形成さ れており、前記開孔の前記側壁面の少なくとも (second sub interlevel dielectric layer) 近傍に前 記ビット線が位置し、前記第２の絶縁膜により前記下部 電極と前記ビット線とが絶縁されていることを特徴とす る請求項１〜５のいずれか１項に記載の半導体記憶装 置。 |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (キャパシタ, 誘電体膜) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (製造方法) of said contact region . |
JPH11168199A CLAIM 1 【請求項１】 半導体基板上で素子分離構造により画定 された素子活性領域に、ゲート及び一対の不純物拡散層 を有するアクセストランジスタと、下部電極と上部電極 とが誘電体膜 (interlevel dielectric, second interlevel dielectric layer) を介して対向して容量結合するメモリキャ パシタとを備えた半導体記憶装置において、 前記アクセストランジスタを覆う第１の絶縁膜及び前記 第１の絶縁膜上に形成された保護膜を穿って一方の前記 不純物拡散層の表面の一部を露出させる開孔が形成され ているとともに、前記開孔の側壁面を覆う第２の絶縁膜 が形成されており、 前記メモリキャパシタ (interlevel dielectric, second interlevel dielectric layer) の前記下部電極は、前記開孔を前 記第２の絶縁膜を介して充填して前記一方の前記不純物 拡散層と接続されるとともに、前記保護膜を介して前記 第１の絶縁膜上に島状に立設されていることを特徴とす る半導体記憶装置。 JPH11168199A CLAIM 6 【請求項６】 前記下部電極の下部にビット線が形成さ れており、前記開孔の前記側壁面の少なくとも (second sub interlevel dielectric layer) 近傍に前 記ビット線が位置し、前記第２の絶縁膜により前記下部 電極と前記ビット線とが絶縁されていることを特徴とす る請求項１〜５のいずれか１項に記載の半導体記憶装 置。 JPH11168199A CLAIM 10 【請求項１０】 半導体基板上で素子分離構造により画 定された素子活性領域に、ゲート及び一対の不純物拡散 層を有するアクセストランジスタと、下部電極と上部電 極とが誘電体膜を介して対向して容量結合するメモリキ ャパシタとを備えた半導体記憶装置の製造方法 (metal layer coupling area) におい て、 前記アクセストランジスタを覆う第１の絶縁膜を形成す る第１の工程と、 前記第１の絶縁膜上に保護膜を形成する第２の工程と、 前記第１の絶縁膜及び前記保護膜をパターニングし、一 方の前記不純物拡散層の表面の一部を露出させる開孔を 形成する第３の工程と、 前記開孔内を含む前記保護膜の全面に第２の絶縁膜を堆 積する第４の工程と、 前記保護膜をストッパーとして前記第２の絶縁膜の全面 をエッチングし、前記開孔内の側壁面のみに前記第２の 絶縁膜を残す第５の工程と、 前記開孔内を前記第２の絶縁膜を介して充填するととも に前記保護膜上を覆うように導電膜を形成する第６の工 程と、 前記導電膜をパターニングし、前記開孔を通じて前記一 方の前記不純物拡散層と接続されるとともに前記保護膜 上に立設されるように島状の前記下部電極を形成する第 ７の工程とを有することを特徴とする半導体記憶装置の 製造方法。 |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Å thick , said first sub interlevel dielectric (キャパシタ, 誘電体膜) layer is in a range of about 1 , 000 to 2 , 000 Å thick , said second etch stop layer is in a range of about 300 to 800 Å thick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Å thick . |
JPH11168199A CLAIM 1 【請求項１】 半導体基板上で素子分離構造により画定 された素子活性領域に、ゲート及び一対の不純物拡散層 を有するアクセストランジスタと、下部電極と上部電極 とが誘電体膜 (interlevel dielectric, second interlevel dielectric layer) を介して対向して容量結合するメモリキャ パシタとを備えた半導体記憶装置において、 前記アクセストランジスタを覆う第１の絶縁膜及び前記 第１の絶縁膜上に形成された保護膜を穿って一方の前記 不純物拡散層の表面の一部を露出させる開孔が形成され ているとともに、前記開孔の側壁面を覆う第２の絶縁膜 が形成されており、 前記メモリキャパシタ (interlevel dielectric, second interlevel dielectric layer) の前記下部電極は、前記開孔を前 記第２の絶縁膜を介して充填して前記一方の前記不純物 拡散層と接続されるとともに、前記保護膜を介して前記 第１の絶縁膜上に島状に立設されていることを特徴とす る半導体記憶装置。 JPH11168199A CLAIM 6 【請求項６】 前記下部電極の下部にビット線が形成さ れており、前記開孔の前記側壁面の少なくとも (second sub interlevel dielectric layer) 近傍に前 記ビット線が位置し、前記第２の絶縁膜により前記下部 電極と前記ビット線とが絶縁されていることを特徴とす る請求項１〜５のいずれか１項に記載の半導体記憶装 置。 |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region is a first range of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range (あること) of about 0 . 16 μm to 0 . 18 μm wide . |
JPH11168199A CLAIM 4 【請求項４】 前記保護膜がシリコン窒化膜であること (second range) を特徴とする請求項１〜３のいずれか１項に記載の半導 体記憶装置。 |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | JPH1174352A Filed: 1997-11-25 Issued: 1999-03-16 半導体装置およびその製造方法 (Original Assignee) Seiko Epson Corp; セイコーエプソン株式会社 Michio Asahina, Kazumi Matsumoto, Naohiro Moriya, Yukio Morozumi, Eiji Suzuki, 幸男 両角, 直弘 守屋, 通雄 朝比奈, 和己 松本, 英司 鈴木 |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area (前記層) of said contact region is smaller than a metal layer coupling area (製造方法) of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation (なる第２) between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer (少なくとも) over said second etch stop layer . |
JPH1174352A CLAIM 1 【請求項１】 素子を含む半導体基板、前記半導体基板 の上に形成された層間絶縁膜、前記層 (substrate coupling area) 間絶縁膜に形成さ れたスルーホール、前記層間絶縁膜および前記スルーホ ールの表面に形成されたバリア層、および前記バリア層 の上に形成された導電膜を含み、 前記層間絶縁膜は、 シリコン化合物と過酸化水素との重縮合反応によって形 成された第１のシリコン酸化膜、および前記第１のシリ コン酸化膜の上に形成され、不純物を含有する第２のシ リコン酸化膜、 を含む半導体装置。 JPH1174352A CLAIM 5 【請求項５】 素子を含む半導体基板の上に層間絶縁膜 を形成する工程、前記層間絶縁膜にスルーホールを形成 する工程、前記層間絶縁膜および前記スルーホールの表 面にバリア層を形成する工程、および前記バリア層の表 面に導電膜を形成する工程を含み、前記層間絶縁膜を形 成する工程は、少なくとも (second sub interlevel dielectric layer) 以下の工程（ａ）〜（ｃ）を 含む半導体装置の製造方法 (metal layer coupling area) 。 （ａ）シリコン化合物と過酸化水素とを化学気相成長法 によって反応させて第１のシリコン酸化膜を形成する工 程、 （ｂ）シリコン化合物、酸素および酸素を含む化合物の 少なくとも１種、および不純物を含む化合物を化学気相 成長法によって反応させて多孔性の第２のシリコン酸化 膜を形成する工程、および （ｃ）６００〜８５０℃の温度でアニール処理を行う工 程。 JPH1174352A CLAIM 17 【請求項１７】 請求項５ないし請求項１６のいずれか において、 前記導電膜は、２００℃以下の温度で、アルミニウムあ るいはアルミニウムを主成分とする合金からなる第１の アルミニウム膜を形成し、その後、３００℃以上の温度 で、アルミニウムあるいはアルミニウムを主成分とする 合金からなる第２ (electrical insulation) のアルミニウム膜を形成する半導体装 置の製造方法。 |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch stop layer protects lower layers during an etching process (１００) . |
JPH1174352A CLAIM 8 【請求項８】 請求項５または請求項６において、 前記工程（ａ）は、前記シリコン化合物が有機シラン化 合物であって、１００ (etching process) 〜１５０℃の温度条件下で減圧化 学気相成長法によって行われる半導体装置の製造方法。 |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric layer (少なくとも) insulates said contact region . |
JPH1174352A CLAIM 5 【請求項５】 素子を含む半導体基板の上に層間絶縁膜 を形成する工程、前記層間絶縁膜にスルーホールを形成 する工程、前記層間絶縁膜および前記スルーホールの表 面にバリア層を形成する工程、および前記バリア層の表 面に導電膜を形成する工程を含み、前記層間絶縁膜を形 成する工程は、少なくとも (second sub interlevel dielectric layer) 以下の工程（ａ）〜（ｃ）を 含む半導体装置の製造方法。 （ａ）シリコン化合物と過酸化水素とを化学気相成長法 によって反応させて第１のシリコン酸化膜を形成する工 程、 （ｂ）シリコン化合物、酸素および酸素を含む化合物の 少なくとも１種、および不純物を含む化合物を化学気相 成長法によって反応させて多孔性の第２のシリコン酸化 膜を形成する工程、および （ｃ）６００〜８５０℃の温度でアニール処理を行う工 程。 |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area (前記層) of said contact region permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area (製造方法) of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
JPH1174352A CLAIM 1 【請求項１】 素子を含む半導体基板、前記半導体基板 の上に形成された層間絶縁膜、前記層 (substrate coupling area) 間絶縁膜に形成さ れたスルーホール、前記層間絶縁膜および前記スルーホ ールの表面に形成されたバリア層、および前記バリア層 の上に形成された導電膜を含み、 前記層間絶縁膜は、 シリコン化合物と過酸化水素との重縮合反応によって形 成された第１のシリコン酸化膜、および前記第１のシリ コン酸化膜の上に形成され、不純物を含有する第２のシ リコン酸化膜、 を含む半導体装置。 JPH1174352A CLAIM 5 【請求項５】 素子を含む半導体基板の上に層間絶縁膜 を形成する工程、前記層間絶縁膜にスルーホールを形成 する工程、前記層間絶縁膜および前記スルーホールの表 面にバリア層を形成する工程、および前記バリア層の表 面に導電膜を形成する工程を含み、前記層間絶縁膜を形 成する工程は、少なくとも以下の工程（ａ）〜（ｃ）を 含む半導体装置の製造方法 (metal layer coupling area) 。 （ａ）シリコン化合物と過酸化水素とを化学気相成長法 によって反応させて第１のシリコン酸化膜を形成する工 程、 （ｂ）シリコン化合物、酸素および酸素を含む化合物の 少なくとも１種、および不純物を含む化合物を化学気相 成長法によって反応させて多孔性の第２のシリコン酸化 膜を形成する工程、および （ｃ）６００〜８５０℃の温度でアニール処理を行う工 程。 |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Å thick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Å thick , said second etch stop layer is in a range of about 300 to 800 Å thick and said second sub interlevel dielectric layer (少なくとも) is in a range of about 10K ű1K Å thick . |
JPH1174352A CLAIM 5 【請求項５】 素子を含む半導体基板の上に層間絶縁膜 を形成する工程、前記層間絶縁膜にスルーホールを形成 する工程、前記層間絶縁膜および前記スルーホールの表 面にバリア層を形成する工程、および前記バリア層の表 面に導電膜を形成する工程を含み、前記層間絶縁膜を形 成する工程は、少なくとも (second sub interlevel dielectric layer) 以下の工程（ａ）〜（ｃ）を 含む半導体装置の製造方法。 （ａ）シリコン化合物と過酸化水素とを化学気相成長法 によって反応させて第１のシリコン酸化膜を形成する工 程、 （ｂ）シリコン化合物、酸素および酸素を含む化合物の 少なくとも１種、および不純物を含む化合物を化学気相 成長法によって反応させて多孔性の第２のシリコン酸化 膜を形成する工程、および （ｃ）６００〜８５０℃の温度でアニール処理を行う工 程。 |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer (少なくとも) for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
JPH1174352A CLAIM 5 【請求項５】 素子を含む半導体基板の上に層間絶縁膜 を形成する工程、前記層間絶縁膜にスルーホールを形成 する工程、前記層間絶縁膜および前記スルーホールの表 面にバリア層を形成する工程、および前記バリア層の表 面に導電膜を形成する工程を含み、前記層間絶縁膜を形 成する工程は、少なくとも (second sub interlevel dielectric layer) 以下の工程（ａ）〜（ｃ）を 含む半導体装置の製造方法。 （ａ）シリコン化合物と過酸化水素とを化学気相成長法 によって反応させて第１のシリコン酸化膜を形成する工 程、 （ｂ）シリコン化合物、酸素および酸素を含む化合物の 少なくとも１種、および不純物を含む化合物を化学気相 成長法によって反応させて多孔性の第２のシリコン酸化 膜を形成する工程、および （ｃ）６００〜８５０℃の温度でアニール処理を行う工 程。 |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer (少なくとも) and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area (前記層) of said contact region is smaller than a metal layer coupling area (製造方法) of said contact region . |
JPH1174352A CLAIM 1 【請求項１】 素子を含む半導体基板、前記半導体基板 の上に形成された層間絶縁膜、前記層 (substrate coupling area) 間絶縁膜に形成さ れたスルーホール、前記層間絶縁膜および前記スルーホ ールの表面に形成されたバリア層、および前記バリア層 の上に形成された導電膜を含み、 前記層間絶縁膜は、 シリコン化合物と過酸化水素との重縮合反応によって形 成された第１のシリコン酸化膜、および前記第１のシリ コン酸化膜の上に形成され、不純物を含有する第２のシ リコン酸化膜、 を含む半導体装置。 JPH1174352A CLAIM 5 【請求項５】 素子を含む半導体基板の上に層間絶縁膜 を形成する工程、前記層間絶縁膜にスルーホールを形成 する工程、前記層間絶縁膜および前記スルーホールの表 面にバリア層を形成する工程、および前記バリア層の表 面に導電膜を形成する工程を含み、前記層間絶縁膜を形 成する工程は、少なくとも (second sub interlevel dielectric layer) 以下の工程（ａ）〜（ｃ）を 含む半導体装置の製造方法 (metal layer coupling area) 。 （ａ）シリコン化合物と過酸化水素とを化学気相成長法 によって反応させて第１のシリコン酸化膜を形成する工 程、 （ｂ）シリコン化合物、酸素および酸素を含む化合物の 少なくとも１種、および不純物を含む化合物を化学気相 成長法によって反応させて多孔性の第２のシリコン酸化 膜を形成する工程、および （ｃ）６００〜８５０℃の温度でアニール処理を行う工 程。 |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Å thick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Å thick , said second etch stop layer is in a range of about 300 to 800 Å thick and said second sub interlevel dielectric layer (少なくとも) is in a range of about 10K ű1K Å thick . |
JPH1174352A CLAIM 5 【請求項５】 素子を含む半導体基板の上に層間絶縁膜 を形成する工程、前記層間絶縁膜にスルーホールを形成 する工程、前記層間絶縁膜および前記スルーホールの表 面にバリア層を形成する工程、および前記バリア層の表 面に導電膜を形成する工程を含み、前記層間絶縁膜を形 成する工程は、少なくとも (second sub interlevel dielectric layer) 以下の工程（ａ）〜（ｃ）を 含む半導体装置の製造方法。 （ａ）シリコン化合物と過酸化水素とを化学気相成長法 によって反応させて第１のシリコン酸化膜を形成する工 程、 （ｂ）シリコン化合物、酸素および酸素を含む化合物の 少なくとも１種、および不純物を含む化合物を化学気相 成長法によって反応させて多孔性の第２のシリコン酸化 膜を形成する工程、および （ｃ）６００〜８５０℃の温度でアニール処理を行う工 程。 |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | CN1195192A Filed: 1997-11-24 Issued: 1998-10-07 半导体器件及其制造方法 (Original Assignee) 三菱电机株式会社 荣森贵尚 |
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| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer protects removal of a substrate material (层形成) by an etch process (的工艺) . |
CN1195192A CLAIM 8 . 一种半导体器件，其特征在于，包括：半导体衬底层；下部导电部分，邻接该半导体衬底层形成 (substrate material) 该部分；层间绝缘膜，以覆盖所述下部导电部分的形式形成在所述半导体衬底层上；上部导电部分，在所述层间绝缘膜中距所述半导体衬底层预定距离处形成该部分；和在接近所述上部导电部分和下部导电部分的所述层间绝缘膜的开孔中形成的至所述半导体衬底层的接触；所述接触在包括所述层间绝缘膜内的所述上部导电部分或下部导电部分的各自部分之间径向方向地扩大。 CN1195192A CLAIM 14 . 一种半导体器件的制造方法，其特征在于，包括：在半导体衬底层上与所述半导体衬底层邻接的部分，在离开腐蚀率相对高的所述半导体衬底层部分，形成腐蚀率相对低的层间绝缘膜的工艺 (etch process, lithography process) ；形成贯通所述层间绝缘膜并在与所述层间绝缘膜的与所述半导体衬底层邻接部分形成内径相对扩大的开孔的工艺；在所述开孔中形成与所述半导体衬底层的接触的工艺。 |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process (的工艺) ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom (的接触) , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
CN1195192A CLAIM 1 . 一种半导体器件，其特征在于，包括：半导体衬底层；层间绝缘膜，它由在该半导体衬底层上形成的多个腐蚀率不同的层构成；和在设置在该层间绝缘膜上的开孔中形成的与所述半导体衬底层的接触 (contact bottom) ，所述接触在所述层间绝缘膜内与所述半导体衬底层的邻接部分被径向方向地扩大。 CN1195192A CLAIM 14 . 一种半导体器件的制造方法，其特征在于，包括：在半导体衬底层上与所述半导体衬底层邻接的部分，在离开腐蚀率相对高的所述半导体衬底层部分，形成腐蚀率相对低的层间绝缘膜的工艺 (etch process, lithography process) ；形成贯通所述层间绝缘膜并在与所述层间绝缘膜的与所述半导体衬底层邻接部分形成内径相对扩大的开孔的工艺；在所述开孔中形成与所述半导体衬底层的接触的工艺。 |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US6187671B1 Filed: 1997-11-13 Issued: 2001-02-13 Method of forming semiconductor device having minute contact hole (Original Assignee) Ricoh Co Ltd (Current Assignee) Ricoh Co Ltd Mitsugu Irinoda |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch (etching rate) stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (contact hole) layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US6187671B1 CLAIM 1 . A method for fabricating a semiconductor device , comprising the steps of : forming a second layer of an insulating material on a conductive first layer ; forming a third layer on said second layer by depositing an inorganic material that shows a selectivity to a dry etching process with respect to said material forming said second layer ; forming a depression in said second and third layers by a dry etching process while using a resist mask provided on said third layer , such that said depression extends from a top surface of said third layer toward a bottom surface of said second layer , said dry etching process being conducted by setting a condition such that a dry etching occurs with substantially the same etching rate (first etch, etch process) in said second and third layers , said depression being thereby formed so as to have a bottom surface below a bottom surface of said third layer and above said bottom surface of said second layer and a first inner peripheral wall having a first inner diameter , wherein a depth of said depression is less than or equal to 50% of a total thickness of said second and third layers ; depositing a fourth layer of an undoped polysilicon material that shows a selectivity to a dry etching process with respect to said material forming said second layer , on said third layer with a uniform thickness and in conformity with a shape of said depression ; removing said fourth layer from said top surface of said third layer by applying a dry etching process such that said dry etching process acts substantially vertically to said fourth layer , the dry etching conditions being set such that the fourth layer is etched with an etching rate much larger than the etching rate of the third layer , said step of removing said fourth layer being conducted such that a part of said fourth layer remains in the form of a ring-shaped member fitted in said depression with an intimate contact with said first inner peripheral wall of said depression , said ring-shaped member having a second inner peripheral wall of a second , smaller inner diameter and exposing said second layer at a bottom part thereof ; and applying a dry etching process to said second layer exposed at the bottom part of said ring-shaped member , while using said ring-shaped member and said third layer as a mask , such that a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) having an inner diameter substantially identical to said second inner diameter of said ring-shaped member is formed in said second layer , such that said contact hole reaches said bottom surface of said second layer and such that said contact hole has a third inner peripheral wall substantially in alignment to said second inner peripheral wall of said ring-shaped member . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch (etching rate) stop layer protects removal of a substrate material by an etch process (etching rate) . |
US6187671B1 CLAIM 1 . A method for fabricating a semiconductor device , comprising the steps of : forming a second layer of an insulating material on a conductive first layer ; forming a third layer on said second layer by depositing an inorganic material that shows a selectivity to a dry etching process with respect to said material forming said second layer ; forming a depression in said second and third layers by a dry etching process while using a resist mask provided on said third layer , such that said depression extends from a top surface of said third layer toward a bottom surface of said second layer , said dry etching process being conducted by setting a condition such that a dry etching occurs with substantially the same etching rate (first etch, etch process) in said second and third layers , said depression being thereby formed so as to have a bottom surface below a bottom surface of said third layer and above said bottom surface of said second layer and a first inner peripheral wall having a first inner diameter , wherein a depth of said depression is less than or equal to 50% of a total thickness of said second and third layers ; depositing a fourth layer of an undoped polysilicon material that shows a selectivity to a dry etching process with respect to said material forming said second layer , on said third layer with a uniform thickness and in conformity with a shape of said depression ; removing said fourth layer from said top surface of said third layer by applying a dry etching process such that said dry etching process acts substantially vertically to said fourth layer , the dry etching conditions being set such that the fourth layer is etched with an etching rate much larger than the etching rate of the third layer , said step of removing said fourth layer being conducted such that a part of said fourth layer remains in the form of a ring-shaped member fitted in said depression with an intimate contact with said first inner peripheral wall of said depression , said ring-shaped member having a second inner peripheral wall of a second , smaller inner diameter and exposing said second layer at a bottom part thereof ; and applying a dry etching process to said second layer exposed at the bottom part of said ring-shaped member , while using said ring-shaped member and said third layer as a mask , such that a contact hole having an inner diameter substantially identical to said second inner diameter of said ring-shaped member is formed in said second layer , such that said contact hole reaches said bottom surface of said second layer and such that said contact hole has a third inner peripheral wall substantially in alignment to said second inner peripheral wall of said ring-shaped member . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (contact hole) layer insulates said contact region . |
US6187671B1 CLAIM 1 . A method for fabricating a semiconductor device , comprising the steps of : forming a second layer of an insulating material on a conductive first layer ; forming a third layer on said second layer by depositing an inorganic material that shows a selectivity to a dry etching process with respect to said material forming said second layer ; forming a depression in said second and third layers by a dry etching process while using a resist mask provided on said third layer , such that said depression extends from a top surface of said third layer toward a bottom surface of said second layer , said dry etching process being conducted by setting a condition such that a dry etching occurs with substantially the same etching rate in said second and third layers , said depression being thereby formed so as to have a bottom surface below a bottom surface of said third layer and above said bottom surface of said second layer and a first inner peripheral wall having a first inner diameter , wherein a depth of said depression is less than or equal to 50% of a total thickness of said second and third layers ; depositing a fourth layer of an undoped polysilicon material that shows a selectivity to a dry etching process with respect to said material forming said second layer , on said third layer with a uniform thickness and in conformity with a shape of said depression ; removing said fourth layer from said top surface of said third layer by applying a dry etching process such that said dry etching process acts substantially vertically to said fourth layer , the dry etching conditions being set such that the fourth layer is etched with an etching rate much larger than the etching rate of the third layer , said step of removing said fourth layer being conducted such that a part of said fourth layer remains in the form of a ring-shaped member fitted in said depression with an intimate contact with said first inner peripheral wall of said depression , said ring-shaped member having a second inner peripheral wall of a second , smaller inner diameter and exposing said second layer at a bottom part thereof ; and applying a dry etching process to said second layer exposed at the bottom part of said ring-shaped member , while using said ring-shaped member and said third layer as a mask , such that a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) having an inner diameter substantially identical to said second inner diameter of said ring-shaped member is formed in said second layer , such that said contact hole reaches said bottom surface of said second layer and such that said contact hole has a third inner peripheral wall substantially in alignment to said second inner peripheral wall of said ring-shaped member . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch stop layer protects lower layers during an etching process (doped polysilicon, uniform thickness) . |
US6187671B1 CLAIM 1 . A method for fabricating a semiconductor device , comprising the steps of : forming a second layer of an insulating material on a conductive first layer ; forming a third layer on said second layer by depositing an inorganic material that shows a selectivity to a dry etching process with respect to said material forming said second layer ; forming a depression in said second and third layers by a dry etching process while using a resist mask provided on said third layer , such that said depression extends from a top surface of said third layer toward a bottom surface of said second layer , said dry etching process being conducted by setting a condition such that a dry etching occurs with substantially the same etching rate in said second and third layers , said depression being thereby formed so as to have a bottom surface below a bottom surface of said third layer and above said bottom surface of said second layer and a first inner peripheral wall having a first inner diameter , wherein a depth of said depression is less than or equal to 50% of a total thickness of said second and third layers ; depositing a fourth layer of an undoped polysilicon (etching process) material that shows a selectivity to a dry etching process with respect to said material forming said second layer , on said third layer with a uniform thickness (etching process) and in conformity with a shape of said depression ; removing said fourth layer from said top surface of said third layer by applying a dry etching process such that said dry etching process acts substantially vertically to said fourth layer , the dry etching conditions being set such that the fourth layer is etched with an etching rate much larger than the etching rate of the third layer , said step of removing said fourth layer being conducted such that a part of said fourth layer remains in the form of a ring-shaped member fitted in said depression with an intimate contact with said first inner peripheral wall of said depression , said ring-shaped member having a second inner peripheral wall of a second , smaller inner diameter and exposing said second layer at a bottom part thereof ; and applying a dry etching process to said second layer exposed at the bottom part of said ring-shaped member , while using said ring-shaped member and said third layer as a mask , such that a contact hole having an inner diameter substantially identical to said second inner diameter of said ring-shaped member is formed in said second layer , such that said contact hole reaches said bottom surface of said second layer and such that said contact hole has a third inner peripheral wall substantially in alignment to said second inner peripheral wall of said ring-shaped member . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (contact hole) layer insulates said contact region . |
US6187671B1 CLAIM 1 . A method for fabricating a semiconductor device , comprising the steps of : forming a second layer of an insulating material on a conductive first layer ; forming a third layer on said second layer by depositing an inorganic material that shows a selectivity to a dry etching process with respect to said material forming said second layer ; forming a depression in said second and third layers by a dry etching process while using a resist mask provided on said third layer , such that said depression extends from a top surface of said third layer toward a bottom surface of said second layer , said dry etching process being conducted by setting a condition such that a dry etching occurs with substantially the same etching rate in said second and third layers , said depression being thereby formed so as to have a bottom surface below a bottom surface of said third layer and above said bottom surface of said second layer and a first inner peripheral wall having a first inner diameter , wherein a depth of said depression is less than or equal to 50% of a total thickness of said second and third layers ; depositing a fourth layer of an undoped polysilicon material that shows a selectivity to a dry etching process with respect to said material forming said second layer , on said third layer with a uniform thickness and in conformity with a shape of said depression ; removing said fourth layer from said top surface of said third layer by applying a dry etching process such that said dry etching process acts substantially vertically to said fourth layer , the dry etching conditions being set such that the fourth layer is etched with an etching rate much larger than the etching rate of the third layer , said step of removing said fourth layer being conducted such that a part of said fourth layer remains in the form of a ring-shaped member fitted in said depression with an intimate contact with said first inner peripheral wall of said depression , said ring-shaped member having a second inner peripheral wall of a second , smaller inner diameter and exposing said second layer at a bottom part thereof ; and applying a dry etching process to said second layer exposed at the bottom part of said ring-shaped member , while using said ring-shaped member and said third layer as a mask , such that a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) having an inner diameter substantially identical to said second inner diameter of said ring-shaped member is formed in said second layer , such that said contact hole reaches said bottom surface of said second layer and such that said contact hole has a third inner peripheral wall substantially in alignment to said second inner peripheral wall of said ring-shaped member . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch (etching rate) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (contact hole) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6187671B1 CLAIM 1 . A method for fabricating a semiconductor device , comprising the steps of : forming a second layer of an insulating material on a conductive first layer ; forming a third layer on said second layer by depositing an inorganic material that shows a selectivity to a dry etching process with respect to said material forming said second layer ; forming a depression in said second and third layers by a dry etching process while using a resist mask provided on said third layer , such that said depression extends from a top surface of said third layer toward a bottom surface of said second layer , said dry etching process being conducted by setting a condition such that a dry etching occurs with substantially the same etching rate (first etch, etch process) in said second and third layers , said depression being thereby formed so as to have a bottom surface below a bottom surface of said third layer and above said bottom surface of said second layer and a first inner peripheral wall having a first inner diameter , wherein a depth of said depression is less than or equal to 50% of a total thickness of said second and third layers ; depositing a fourth layer of an undoped polysilicon material that shows a selectivity to a dry etching process with respect to said material forming said second layer , on said third layer with a uniform thickness and in conformity with a shape of said depression ; removing said fourth layer from said top surface of said third layer by applying a dry etching process such that said dry etching process acts substantially vertically to said fourth layer , the dry etching conditions being set such that the fourth layer is etched with an etching rate much larger than the etching rate of the third layer , said step of removing said fourth layer being conducted such that a part of said fourth layer remains in the form of a ring-shaped member fitted in said depression with an intimate contact with said first inner peripheral wall of said depression , said ring-shaped member having a second inner peripheral wall of a second , smaller inner diameter and exposing said second layer at a bottom part thereof ; and applying a dry etching process to said second layer exposed at the bottom part of said ring-shaped member , while using said ring-shaped member and said third layer as a mask , such that a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) having an inner diameter substantially identical to said second inner diameter of said ring-shaped member is formed in said second layer , such that said contact hole reaches said bottom surface of said second layer and such that said contact hole has a third inner peripheral wall substantially in alignment to said second inner peripheral wall of said ring-shaped member . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric (contact hole) layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US6187671B1 CLAIM 1 . A method for fabricating a semiconductor device , comprising the steps of : forming a second layer of an insulating material on a conductive first layer ; forming a third layer on said second layer by depositing an inorganic material that shows a selectivity to a dry etching process with respect to said material forming said second layer ; forming a depression in said second and third layers by a dry etching process while using a resist mask provided on said third layer , such that said depression extends from a top surface of said third layer toward a bottom surface of said second layer , said dry etching process being conducted by setting a condition such that a dry etching occurs with substantially the same etching rate in said second and third layers , said depression being thereby formed so as to have a bottom surface below a bottom surface of said third layer and above said bottom surface of said second layer and a first inner peripheral wall having a first inner diameter , wherein a depth of said depression is less than or equal to 50% of a total thickness of said second and third layers ; depositing a fourth layer of an undoped polysilicon material that shows a selectivity to a dry etching process with respect to said material forming said second layer , on said third layer with a uniform thickness and in conformity with a shape of said depression ; removing said fourth layer from said top surface of said third layer by applying a dry etching process such that said dry etching process acts substantially vertically to said fourth layer , the dry etching conditions being set such that the fourth layer is etched with an etching rate much larger than the etching rate of the third layer , said step of removing said fourth layer being conducted such that a part of said fourth layer remains in the form of a ring-shaped member fitted in said depression with an intimate contact with said first inner peripheral wall of said depression , said ring-shaped member having a second inner peripheral wall of a second , smaller inner diameter and exposing said second layer at a bottom part thereof ; and applying a dry etching process to said second layer exposed at the bottom part of said ring-shaped member , while using said ring-shaped member and said third layer as a mask , such that a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) having an inner diameter substantially identical to said second inner diameter of said ring-shaped member is formed in said second layer , such that said contact hole reaches said bottom surface of said second layer and such that said contact hole has a third inner peripheral wall substantially in alignment to said second inner peripheral wall of said ring-shaped member . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch (etching rate) stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (contact hole) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US6187671B1 CLAIM 1 . A method for fabricating a semiconductor device , comprising the steps of : forming a second layer of an insulating material on a conductive first layer ; forming a third layer on said second layer by depositing an inorganic material that shows a selectivity to a dry etching process with respect to said material forming said second layer ; forming a depression in said second and third layers by a dry etching process while using a resist mask provided on said third layer , such that said depression extends from a top surface of said third layer toward a bottom surface of said second layer , said dry etching process being conducted by setting a condition such that a dry etching occurs with substantially the same etching rate (first etch, etch process) in said second and third layers , said depression being thereby formed so as to have a bottom surface below a bottom surface of said third layer and above said bottom surface of said second layer and a first inner peripheral wall having a first inner diameter , wherein a depth of said depression is less than or equal to 50% of a total thickness of said second and third layers ; depositing a fourth layer of an undoped polysilicon material that shows a selectivity to a dry etching process with respect to said material forming said second layer , on said third layer with a uniform thickness and in conformity with a shape of said depression ; removing said fourth layer from said top surface of said third layer by applying a dry etching process such that said dry etching process acts substantially vertically to said fourth layer , the dry etching conditions being set such that the fourth layer is etched with an etching rate much larger than the etching rate of the third layer , said step of removing said fourth layer being conducted such that a part of said fourth layer remains in the form of a ring-shaped member fitted in said depression with an intimate contact with said first inner peripheral wall of said depression , said ring-shaped member having a second inner peripheral wall of a second , smaller inner diameter and exposing said second layer at a bottom part thereof ; and applying a dry etching process to said second layer exposed at the bottom part of said ring-shaped member , while using said ring-shaped member and said third layer as a mask , such that a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) having an inner diameter substantially identical to said second inner diameter of said ring-shaped member is formed in said second layer , such that said contact hole reaches said bottom surface of said second layer and such that said contact hole has a third inner peripheral wall substantially in alignment to said second inner peripheral wall of said ring-shaped member . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch (etching rate) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (contact hole) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6187671B1 CLAIM 1 . A method for fabricating a semiconductor device , comprising the steps of : forming a second layer of an insulating material on a conductive first layer ; forming a third layer on said second layer by depositing an inorganic material that shows a selectivity to a dry etching process with respect to said material forming said second layer ; forming a depression in said second and third layers by a dry etching process while using a resist mask provided on said third layer , such that said depression extends from a top surface of said third layer toward a bottom surface of said second layer , said dry etching process being conducted by setting a condition such that a dry etching occurs with substantially the same etching rate (first etch, etch process) in said second and third layers , said depression being thereby formed so as to have a bottom surface below a bottom surface of said third layer and above said bottom surface of said second layer and a first inner peripheral wall having a first inner diameter , wherein a depth of said depression is less than or equal to 50% of a total thickness of said second and third layers ; depositing a fourth layer of an undoped polysilicon material that shows a selectivity to a dry etching process with respect to said material forming said second layer , on said third layer with a uniform thickness and in conformity with a shape of said depression ; removing said fourth layer from said top surface of said third layer by applying a dry etching process such that said dry etching process acts substantially vertically to said fourth layer , the dry etching conditions being set such that the fourth layer is etched with an etching rate much larger than the etching rate of the third layer , said step of removing said fourth layer being conducted such that a part of said fourth layer remains in the form of a ring-shaped member fitted in said depression with an intimate contact with said first inner peripheral wall of said depression , said ring-shaped member having a second inner peripheral wall of a second , smaller inner diameter and exposing said second layer at a bottom part thereof ; and applying a dry etching process to said second layer exposed at the bottom part of said ring-shaped member , while using said ring-shaped member and said third layer as a mask , such that a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) having an inner diameter substantially identical to said second inner diameter of said ring-shaped member is formed in said second layer , such that said contact hole reaches said bottom surface of said second layer and such that said contact hole has a third inner peripheral wall substantially in alignment to said second inner peripheral wall of said ring-shaped member . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US20020056913A1 Filed: 1997-09-23 Issued: 2002-05-16 Semiconductor device and method of fabricating the same (Original Assignee) Mitsubishi Electric Corp (Current Assignee) Renesas Electronics Corp Takahisa Eimori |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch (etching rate, high etching) stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US20020056913A1 CLAIM 1 . A semiconductor device comprising : a semiconductor base layer ; a multilayer interlayer insulating film formed on said semiconductor base layer and consisting of a plurality of layers differing from each other in etching rate (first etch, etch process) ; and at least a contact formed in a hole which is in turn formed in said multilayer interlayer insulating film , the contact being in contact with said semiconductor base layer ; wherein the diameter of said contact is increased in a portion thereof contiguous with said semiconductor base layer . US20020056913A1 CLAIM 7 . The semiconductor device according to claim 1 , wherein a portion of said interlayer insulating film contiguous with said semiconductor base layer is formed to have a high etching (first etch, etch process) rate , as compared with other portions of said interlayer insulating film . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch (etching rate, high etching) stop layer protects removal of a substrate material by an etch process (etching rate, high etching) . |
US20020056913A1 CLAIM 1 . A semiconductor device comprising : a semiconductor base layer ; a multilayer interlayer insulating film formed on said semiconductor base layer and consisting of a plurality of layers differing from each other in etching rate (first etch, etch process) ; and at least a contact formed in a hole which is in turn formed in said multilayer interlayer insulating film , the contact being in contact with said semiconductor base layer ; wherein the diameter of said contact is increased in a portion thereof contiguous with said semiconductor base layer . US20020056913A1 CLAIM 7 . The semiconductor device according to claim 1 , wherein a portion of said interlayer insulating film contiguous with said semiconductor base layer is formed to have a high etching (first etch, etch process) rate , as compared with other portions of said interlayer insulating film . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch (etching rate, high etching) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US20020056913A1 CLAIM 1 . A semiconductor device comprising : a semiconductor base layer ; a multilayer interlayer insulating film formed on said semiconductor base layer and consisting of a plurality of layers differing from each other in etching rate (first etch, etch process) ; and at least a contact formed in a hole which is in turn formed in said multilayer interlayer insulating film , the contact being in contact with said semiconductor base layer ; wherein the diameter of said contact is increased in a portion thereof contiguous with said semiconductor base layer . US20020056913A1 CLAIM 7 . The semiconductor device according to claim 1 , wherein a portion of said interlayer insulating film contiguous with said semiconductor base layer is formed to have a high etching (first etch, etch process) rate , as compared with other portions of said interlayer insulating film . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US20020056913A1 CLAIM 14 . A method of fabricating a semiconductor device comprising the steps of : forming on a semiconductor base layer an interlayer insulating film in which the portion nearer to the semiconductor base layer has relatively higher etching rate and the portion farther from the semiconductor base layer has relatively low etching rates , respectively ; forming at least a hole through the interlayer insulating film so that the diameter of the hole increases toward the semiconductor base layer ; and forming (anti reflective coating) a contact in the hole so as to be connected to the semiconductor base layer . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch (etching rate, high etching) stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers (adjacent pair) have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US20020056913A1 CLAIM 1 . A semiconductor device comprising : a semiconductor base layer ; a multilayer interlayer insulating film formed on said semiconductor base layer and consisting of a plurality of layers differing from each other in etching rate (first etch, etch process) ; and at least a contact formed in a hole which is in turn formed in said multilayer interlayer insulating film , the contact being in contact with said semiconductor base layer ; wherein the diameter of said contact is increased in a portion thereof contiguous with said semiconductor base layer . US20020056913A1 CLAIM 3 . The semiconductor device according to claim 2 , wherein a plurality of said conductive elements are formed , and said contact is positioned between the adjacent pair (second etch stop layers) of said plurality of conductive elements . US20020056913A1 CLAIM 7 . The semiconductor device according to claim 1 , wherein a portion of said interlayer insulating film contiguous with said semiconductor base layer is formed to have a high etching (first etch, etch process) rate , as compared with other portions of said interlayer insulating film . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch (etching rate, high etching) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US20020056913A1 CLAIM 1 . A semiconductor device comprising : a semiconductor base layer ; a multilayer interlayer insulating film formed on said semiconductor base layer and consisting of a plurality of layers differing from each other in etching rate (first etch, etch process) ; and at least a contact formed in a hole which is in turn formed in said multilayer interlayer insulating film , the contact being in contact with said semiconductor base layer ; wherein the diameter of said contact is increased in a portion thereof contiguous with said semiconductor base layer . US20020056913A1 CLAIM 7 . The semiconductor device according to claim 1 , wherein a portion of said interlayer insulating film contiguous with said semiconductor base layer is formed to have a high etching (first etch, etch process) rate , as compared with other portions of said interlayer insulating film . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US20020056913A1 CLAIM 14 . A method of fabricating a semiconductor device comprising the steps of : forming on a semiconductor base layer an interlayer insulating film in which the portion nearer to the semiconductor base layer has relatively higher etching rate and the portion farther from the semiconductor base layer has relatively low etching rates , respectively ; forming at least a hole through the interlayer insulating film so that the diameter of the hole increases toward the semiconductor base layer ; and forming (anti reflective coating) a contact in the hole so as to be connected to the semiconductor base layer . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5912188A Filed: 1997-08-04 Issued: 1999-06-15 Method of forming a contact hole in an interlevel dielectric layer using dual etch stops (Original Assignee) Advanced Micro Devices Inc (Current Assignee) Lone Star Silicon Innovations LLC Mark I. Gardner, Daniel Kadosh, Frederick N. Hause |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch (local interconnect, first etch, contact hole) stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (local interconnect, first etch, contact hole) layer over said first etch stop layer ; a second etch (second etch, gate oxide) stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5912188A CLAIM 1 . A method of forming a contact hole (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) in an interlevel dielectric layer using dual etch stops , comprising : providing a semiconductor substrate ; forming a gate over the substrate , forming a source/drain region in the substrate ; providing a source/drain contact electrically coupled to the source/drain region ; forming an interlevel dielectric layer that includes first , second and third dielectric layers over the source/drain contact ; forming an etch mask over the interlevel dielectric layer ; applying a first etch (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) which is highly selective of the first dielectric layer with respect to the second dielectric layer through an opening in the etch mask using the second dielectric layer as an etch stop , thereby forming a first hole in the first dielectric layer that extends to the second dielectric layer without extending to the third dielectric layer ; applying a second etch (second etch) which is highly selective of the second dielectric layer with respect to the third dielectric layer through the opening in the etch mask using the third dielectric layer as an etch stop , thereby forming a second hole in the second dielectric layer that extends to the third dielectric layer without extending to the source/drain contact ; and applying a third etch which is highly selective of the third dielectric layer with respect to the source/drain contact through the opening in the etch mask , thereby forming a third hole in the third dielectric layer that extends to the source/drain contact , wherein the first , second and third holes in combination provide a contact hole in the interlevel dielectric layer . US5912188A CLAIM 21 . A method of forming a contact hole in an interlevel dielectric layer using dual etch stops , comprising the sequence set forth : providing a semiconductor substrate ; forming a gate oxide (second etch) over the substrate ; forming a polysilicon gate on the gate oxide ; forming a source/drain region in the substrate and providing a source/drain contact electrically coupled to the source/drain region , wherein a distance between a top surface of the polysilicon gate and the substrate is greater than a distance between a top surface of the source/drain contact and the substrate ; forming an interlevel dielectric layer that consists of first , second and third dielectric layers over the source/drain contact , including forming the first dielectric layer on the second dielectric layer , forming the second dielectric layer on the third dielectric layer , and forming the third dielectric layer on the source/drain contact , wherein the first and third dielectric layers are the same material , the polysilicon gate has a greater thickness than a combined thickness of the second and third dielectric layers , and the first dielectric layer has a greater thickness than the polysilicon gate ; forming a photoresist layer on the interlevel dielectric layer ; applying a first anisotropic etch which is highly selective of the first dielectric layer with respect to the second dielectric layer through an opening in the photoresist layer using the photoresist layer as an etch mask and the second dielectric layer as an etch stop , thereby forming a first hole in the first dielectric layer that extends to the second dielectric layer without extending to the third dielectric layer ; applying a second anisotropic etch which is highly selective of the second dielectric layer with respect to the third dielectric layer through the opening in the photoresist layer using the photoresist layer as an etch mask and the third dielectric layer as an etch stop , thereby forming a second hole in the second dielectric layer that extends to the third dielectric layer without extending to the source/drain contact ; and applying a third anisotropic etch which is highly selective of the third dielectric layer with respect to the source/drain contact through the opening in the photoresist layer using the photoresist layer as an etch mask , thereby forming a third hole through the third dielectric layer that extends to the source/drain contact , wherein the first , second and third holes in combination provide a contact hole with straight sidewalls in the interlevel dielectric layer . US5912188A CLAIM 30 . The method of claim 29 , wherein : the contact hole exposes the source/drain contact , a dielectric isolation region in the substrate , and a second source/drain contact electrically coupled to a second source/drain region in the substrate ; and the conductive plug provides a local interconnect (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) between the source/drain contact and the second source/drain contact . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch (local interconnect, first etch, contact hole) stop layer protects removal of a substrate material by an etch process . |
US5912188A CLAIM 1 . A method of forming a contact hole (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) in an interlevel dielectric layer using dual etch stops , comprising : providing a semiconductor substrate ; forming a gate over the substrate , forming a source/drain region in the substrate ; providing a source/drain contact electrically coupled to the source/drain region ; forming an interlevel dielectric layer that includes first , second and third dielectric layers over the source/drain contact ; forming an etch mask over the interlevel dielectric layer ; applying a first etch (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) which is highly selective of the first dielectric layer with respect to the second dielectric layer through an opening in the etch mask using the second dielectric layer as an etch stop , thereby forming a first hole in the first dielectric layer that extends to the second dielectric layer without extending to the third dielectric layer ; applying a second etch which is highly selective of the second dielectric layer with respect to the third dielectric layer through the opening in the etch mask using the third dielectric layer as an etch stop , thereby forming a second hole in the second dielectric layer that extends to the third dielectric layer without extending to the source/drain contact ; and applying a third etch which is highly selective of the third dielectric layer with respect to the source/drain contact through the opening in the etch mask , thereby forming a third hole in the third dielectric layer that extends to the source/drain contact , wherein the first , second and third holes in combination provide a contact hole in the interlevel dielectric layer . US5912188A CLAIM 30 . The method of claim 29 , wherein : the contact hole exposes the source/drain contact , a dielectric isolation region in the substrate , and a second source/drain contact electrically coupled to a second source/drain region in the substrate ; and the conductive plug provides a local interconnect (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) between the source/drain contact and the second source/drain contact . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (local interconnect, first etch, contact hole) layer insulates said contact region . |
US5912188A CLAIM 1 . A method of forming a contact hole (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) in an interlevel dielectric layer using dual etch stops , comprising : providing a semiconductor substrate ; forming a gate over the substrate , forming a source/drain region in the substrate ; providing a source/drain contact electrically coupled to the source/drain region ; forming an interlevel dielectric layer that includes first , second and third dielectric layers over the source/drain contact ; forming an etch mask over the interlevel dielectric layer ; applying a first etch (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) which is highly selective of the first dielectric layer with respect to the second dielectric layer through an opening in the etch mask using the second dielectric layer as an etch stop , thereby forming a first hole in the first dielectric layer that extends to the second dielectric layer without extending to the third dielectric layer ; applying a second etch which is highly selective of the second dielectric layer with respect to the third dielectric layer through the opening in the etch mask using the third dielectric layer as an etch stop , thereby forming a second hole in the second dielectric layer that extends to the third dielectric layer without extending to the source/drain contact ; and applying a third etch which is highly selective of the third dielectric layer with respect to the source/drain contact through the opening in the etch mask , thereby forming a third hole in the third dielectric layer that extends to the source/drain contact , wherein the first , second and third holes in combination provide a contact hole in the interlevel dielectric layer . US5912188A CLAIM 30 . The method of claim 29 , wherein : the contact hole exposes the source/drain contact , a dielectric isolation region in the substrate , and a second source/drain contact electrically coupled to a second source/drain region in the substrate ; and the conductive plug provides a local interconnect (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) between the source/drain contact and the second source/drain contact . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch (second etch, gate oxide) stop layer protects lower layers during an etching process . |
US5912188A CLAIM 1 . A method of forming a contact hole in an interlevel dielectric layer using dual etch stops , comprising : providing a semiconductor substrate ; forming a gate over the substrate , forming a source/drain region in the substrate ; providing a source/drain contact electrically coupled to the source/drain region ; forming an interlevel dielectric layer that includes first , second and third dielectric layers over the source/drain contact ; forming an etch mask over the interlevel dielectric layer ; applying a first etch which is highly selective of the first dielectric layer with respect to the second dielectric layer through an opening in the etch mask using the second dielectric layer as an etch stop , thereby forming a first hole in the first dielectric layer that extends to the second dielectric layer without extending to the third dielectric layer ; applying a second etch (second etch) which is highly selective of the second dielectric layer with respect to the third dielectric layer through the opening in the etch mask using the third dielectric layer as an etch stop , thereby forming a second hole in the second dielectric layer that extends to the third dielectric layer without extending to the source/drain contact ; and applying a third etch which is highly selective of the third dielectric layer with respect to the source/drain contact through the opening in the etch mask , thereby forming a third hole in the third dielectric layer that extends to the source/drain contact , wherein the first , second and third holes in combination provide a contact hole in the interlevel dielectric layer . US5912188A CLAIM 21 . A method of forming a contact hole in an interlevel dielectric layer using dual etch stops , comprising the sequence set forth : providing a semiconductor substrate ; forming a gate oxide (second etch) over the substrate ; forming a polysilicon gate on the gate oxide ; forming a source/drain region in the substrate and providing a source/drain contact electrically coupled to the source/drain region , wherein a distance between a top surface of the polysilicon gate and the substrate is greater than a distance between a top surface of the source/drain contact and the substrate ; forming an interlevel dielectric layer that consists of first , second and third dielectric layers over the source/drain contact , including forming the first dielectric layer on the second dielectric layer , forming the second dielectric layer on the third dielectric layer , and forming the third dielectric layer on the source/drain contact , wherein the first and third dielectric layers are the same material , the polysilicon gate has a greater thickness than a combined thickness of the second and third dielectric layers , and the first dielectric layer has a greater thickness than the polysilicon gate ; forming a photoresist layer on the interlevel dielectric layer ; applying a first anisotropic etch which is highly selective of the first dielectric layer with respect to the second dielectric layer through an opening in the photoresist layer using the photoresist layer as an etch mask and the second dielectric layer as an etch stop , thereby forming a first hole in the first dielectric layer that extends to the second dielectric layer without extending to the third dielectric layer ; applying a second anisotropic etch which is highly selective of the second dielectric layer with respect to the third dielectric layer through the opening in the photoresist layer using the photoresist layer as an etch mask and the third dielectric layer as an etch stop , thereby forming a second hole in the second dielectric layer that extends to the third dielectric layer without extending to the source/drain contact ; and applying a third anisotropic etch which is highly selective of the third dielectric layer with respect to the source/drain contact through the opening in the photoresist layer using the photoresist layer as an etch mask , thereby forming a third hole through the third dielectric layer that extends to the source/drain contact , wherein the first , second and third holes in combination provide a contact hole with straight sidewalls in the interlevel dielectric layer . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (local interconnect, first etch, contact hole) layer insulates said contact region . |
US5912188A CLAIM 1 . A method of forming a contact hole (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) in an interlevel dielectric layer using dual etch stops , comprising : providing a semiconductor substrate ; forming a gate over the substrate , forming a source/drain region in the substrate ; providing a source/drain contact electrically coupled to the source/drain region ; forming an interlevel dielectric layer that includes first , second and third dielectric layers over the source/drain contact ; forming an etch mask over the interlevel dielectric layer ; applying a first etch (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) which is highly selective of the first dielectric layer with respect to the second dielectric layer through an opening in the etch mask using the second dielectric layer as an etch stop , thereby forming a first hole in the first dielectric layer that extends to the second dielectric layer without extending to the third dielectric layer ; applying a second etch which is highly selective of the second dielectric layer with respect to the third dielectric layer through the opening in the etch mask using the third dielectric layer as an etch stop , thereby forming a second hole in the second dielectric layer that extends to the third dielectric layer without extending to the source/drain contact ; and applying a third etch which is highly selective of the third dielectric layer with respect to the source/drain contact through the opening in the etch mask , thereby forming a third hole in the third dielectric layer that extends to the source/drain contact , wherein the first , second and third holes in combination provide a contact hole in the interlevel dielectric layer . US5912188A CLAIM 30 . The method of claim 29 , wherein : the contact hole exposes the source/drain contact , a dielectric isolation region in the substrate , and a second source/drain contact electrically coupled to a second source/drain region in the substrate ; and the conductive plug provides a local interconnect (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) between the source/drain contact and the second source/drain contact . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch (local interconnect, first etch, contact hole) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (local interconnect, first etch, contact hole) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (second etch, gate oxide) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5912188A CLAIM 1 . A method of forming a contact hole (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) in an interlevel dielectric layer using dual etch stops , comprising : providing a semiconductor substrate ; forming a gate over the substrate , forming a source/drain region in the substrate ; providing a source/drain contact electrically coupled to the source/drain region ; forming an interlevel dielectric layer that includes first , second and third dielectric layers over the source/drain contact ; forming an etch mask over the interlevel dielectric layer ; applying a first etch (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) which is highly selective of the first dielectric layer with respect to the second dielectric layer through an opening in the etch mask using the second dielectric layer as an etch stop , thereby forming a first hole in the first dielectric layer that extends to the second dielectric layer without extending to the third dielectric layer ; applying a second etch (second etch) which is highly selective of the second dielectric layer with respect to the third dielectric layer through the opening in the etch mask using the third dielectric layer as an etch stop , thereby forming a second hole in the second dielectric layer that extends to the third dielectric layer without extending to the source/drain contact ; and applying a third etch which is highly selective of the third dielectric layer with respect to the source/drain contact through the opening in the etch mask , thereby forming a third hole in the third dielectric layer that extends to the source/drain contact , wherein the first , second and third holes in combination provide a contact hole in the interlevel dielectric layer . US5912188A CLAIM 21 . A method of forming a contact hole in an interlevel dielectric layer using dual etch stops , comprising the sequence set forth : providing a semiconductor substrate ; forming a gate oxide (second etch) over the substrate ; forming a polysilicon gate on the gate oxide ; forming a source/drain region in the substrate and providing a source/drain contact electrically coupled to the source/drain region , wherein a distance between a top surface of the polysilicon gate and the substrate is greater than a distance between a top surface of the source/drain contact and the substrate ; forming an interlevel dielectric layer that consists of first , second and third dielectric layers over the source/drain contact , including forming the first dielectric layer on the second dielectric layer , forming the second dielectric layer on the third dielectric layer , and forming the third dielectric layer on the source/drain contact , wherein the first and third dielectric layers are the same material , the polysilicon gate has a greater thickness than a combined thickness of the second and third dielectric layers , and the first dielectric layer has a greater thickness than the polysilicon gate ; forming a photoresist layer on the interlevel dielectric layer ; applying a first anisotropic etch which is highly selective of the first dielectric layer with respect to the second dielectric layer through an opening in the photoresist layer using the photoresist layer as an etch mask and the second dielectric layer as an etch stop , thereby forming a first hole in the first dielectric layer that extends to the second dielectric layer without extending to the third dielectric layer ; applying a second anisotropic etch which is highly selective of the second dielectric layer with respect to the third dielectric layer through the opening in the photoresist layer using the photoresist layer as an etch mask and the third dielectric layer as an etch stop , thereby forming a second hole in the second dielectric layer that extends to the third dielectric layer without extending to the source/drain contact ; and applying a third anisotropic etch which is highly selective of the third dielectric layer with respect to the source/drain contact through the opening in the photoresist layer using the photoresist layer as an etch mask , thereby forming a third hole through the third dielectric layer that extends to the source/drain contact , wherein the first , second and third holes in combination provide a contact hole with straight sidewalls in the interlevel dielectric layer . US5912188A CLAIM 30 . The method of claim 29 , wherein : the contact hole exposes the source/drain contact , a dielectric isolation region in the substrate , and a second source/drain contact electrically coupled to a second source/drain region in the substrate ; and the conductive plug provides a local interconnect (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) between the source/drain contact and the second source/drain contact . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric (local interconnect, first etch, contact hole) layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5912188A CLAIM 1 . A method of forming a contact hole (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) in an interlevel dielectric layer using dual etch stops , comprising : providing a semiconductor substrate ; forming a gate over the substrate , forming a source/drain region in the substrate ; providing a source/drain contact electrically coupled to the source/drain region ; forming an interlevel dielectric layer that includes first , second and third dielectric layers over the source/drain contact ; forming an etch mask over the interlevel dielectric layer ; applying a first etch (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) which is highly selective of the first dielectric layer with respect to the second dielectric layer through an opening in the etch mask using the second dielectric layer as an etch stop , thereby forming a first hole in the first dielectric layer that extends to the second dielectric layer without extending to the third dielectric layer ; applying a second etch which is highly selective of the second dielectric layer with respect to the third dielectric layer through the opening in the etch mask using the third dielectric layer as an etch stop , thereby forming a second hole in the second dielectric layer that extends to the third dielectric layer without extending to the source/drain contact ; and applying a third etch which is highly selective of the third dielectric layer with respect to the source/drain contact through the opening in the etch mask , thereby forming a third hole in the third dielectric layer that extends to the source/drain contact , wherein the first , second and third holes in combination provide a contact hole in the interlevel dielectric layer . US5912188A CLAIM 30 . The method of claim 29 , wherein : the contact hole exposes the source/drain contact , a dielectric isolation region in the substrate , and a second source/drain contact electrically coupled to a second source/drain region in the substrate ; and the conductive plug provides a local interconnect (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) between the source/drain contact and the second source/drain contact . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US5912188A CLAIM 11 . A method of forming a contact hole in an interlevel dielectric layer using dual etch stops , comprising : providing a semiconductor substrate ; forming a gate insulator over the substrate ; forming a gate on the gate insulator ; forming a source/drain region in the substrate ; providing a source/drain contact electrically coupled to the source/drain region ; forming an interlevel dielectric layer that includes first , second and third dielectric layers over the source/drain contact , including forming the first dielectric layer on the second dielectric layer and forming (anti reflective coating) the second dielectric layer on the third dielectric layer , wherein the gate has a greater thickness than a combined thickness of the second and third dielectric layers ; forming an etch mask over the interlevel dielectric layer ; applying a first anisotropic etch which is highly selective of the first dielectric layer with respect to the second dielectric layer through an opening in the etch mask using the second dielectric layer as an etch stop , thereby forming a first hole in the first dielectric layer that extends to the second dielectric layer without extending to the third dielectric layer ; applying a second anisotropic etch which is highly selective of the second dielectric layer with respect to the third dielectric layer through the opening in the etch mask using the third dielectric layer as an etch stop , thereby forming a second hole in the second dielectric layer that extends to the third dielectric layer without extending to the source/drain contact ; and applying a third anisotropic etch which is highly selective of the third dielectric layer with respect to the source/drain contact through the opening in the etch mask , thereby forming a third hole in the third dielectric layer that extends to the source/drain contact , wherein the first , second and third holes in combination provide a contact hole in the interlevel dielectric layer . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch (local interconnect, first etch, contact hole) stop layer and a second etch (second etch, gate oxide) stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (local interconnect, first etch, contact hole) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US5912188A CLAIM 1 . A method of forming a contact hole (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) in an interlevel dielectric layer using dual etch stops , comprising : providing a semiconductor substrate ; forming a gate over the substrate , forming a source/drain region in the substrate ; providing a source/drain contact electrically coupled to the source/drain region ; forming an interlevel dielectric layer that includes first , second and third dielectric layers over the source/drain contact ; forming an etch mask over the interlevel dielectric layer ; applying a first etch (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) which is highly selective of the first dielectric layer with respect to the second dielectric layer through an opening in the etch mask using the second dielectric layer as an etch stop , thereby forming a first hole in the first dielectric layer that extends to the second dielectric layer without extending to the third dielectric layer ; applying a second etch (second etch) which is highly selective of the second dielectric layer with respect to the third dielectric layer through the opening in the etch mask using the third dielectric layer as an etch stop , thereby forming a second hole in the second dielectric layer that extends to the third dielectric layer without extending to the source/drain contact ; and applying a third etch which is highly selective of the third dielectric layer with respect to the source/drain contact through the opening in the etch mask , thereby forming a third hole in the third dielectric layer that extends to the source/drain contact , wherein the first , second and third holes in combination provide a contact hole in the interlevel dielectric layer . US5912188A CLAIM 21 . A method of forming a contact hole in an interlevel dielectric layer using dual etch stops , comprising the sequence set forth : providing a semiconductor substrate ; forming a gate oxide (second etch) over the substrate ; forming a polysilicon gate on the gate oxide ; forming a source/drain region in the substrate and providing a source/drain contact electrically coupled to the source/drain region , wherein a distance between a top surface of the polysilicon gate and the substrate is greater than a distance between a top surface of the source/drain contact and the substrate ; forming an interlevel dielectric layer that consists of first , second and third dielectric layers over the source/drain contact , including forming the first dielectric layer on the second dielectric layer , forming the second dielectric layer on the third dielectric layer , and forming the third dielectric layer on the source/drain contact , wherein the first and third dielectric layers are the same material , the polysilicon gate has a greater thickness than a combined thickness of the second and third dielectric layers , and the first dielectric layer has a greater thickness than the polysilicon gate ; forming a photoresist layer on the interlevel dielectric layer ; applying a first anisotropic etch which is highly selective of the first dielectric layer with respect to the second dielectric layer through an opening in the photoresist layer using the photoresist layer as an etch mask and the second dielectric layer as an etch stop , thereby forming a first hole in the first dielectric layer that extends to the second dielectric layer without extending to the third dielectric layer ; applying a second anisotropic etch which is highly selective of the second dielectric layer with respect to the third dielectric layer through the opening in the photoresist layer using the photoresist layer as an etch mask and the third dielectric layer as an etch stop , thereby forming a second hole in the second dielectric layer that extends to the third dielectric layer without extending to the source/drain contact ; and applying a third anisotropic etch which is highly selective of the third dielectric layer with respect to the source/drain contact through the opening in the photoresist layer using the photoresist layer as an etch mask , thereby forming a third hole through the third dielectric layer that extends to the source/drain contact , wherein the first , second and third holes in combination provide a contact hole with straight sidewalls in the interlevel dielectric layer . US5912188A CLAIM 30 . The method of claim 29 , wherein : the contact hole exposes the source/drain contact , a dielectric isolation region in the substrate , and a second source/drain contact electrically coupled to a second source/drain region in the substrate ; and the conductive plug provides a local interconnect (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) between the source/drain contact and the second source/drain contact . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch (local interconnect, first etch, contact hole) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (local interconnect, first etch, contact hole) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (second etch, gate oxide) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5912188A CLAIM 1 . A method of forming a contact hole (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) in an interlevel dielectric layer using dual etch stops , comprising : providing a semiconductor substrate ; forming a gate over the substrate , forming a source/drain region in the substrate ; providing a source/drain contact electrically coupled to the source/drain region ; forming an interlevel dielectric layer that includes first , second and third dielectric layers over the source/drain contact ; forming an etch mask over the interlevel dielectric layer ; applying a first etch (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) which is highly selective of the first dielectric layer with respect to the second dielectric layer through an opening in the etch mask using the second dielectric layer as an etch stop , thereby forming a first hole in the first dielectric layer that extends to the second dielectric layer without extending to the third dielectric layer ; applying a second etch (second etch) which is highly selective of the second dielectric layer with respect to the third dielectric layer through the opening in the etch mask using the third dielectric layer as an etch stop , thereby forming a second hole in the second dielectric layer that extends to the third dielectric layer without extending to the source/drain contact ; and applying a third etch which is highly selective of the third dielectric layer with respect to the source/drain contact through the opening in the etch mask , thereby forming a third hole in the third dielectric layer that extends to the source/drain contact , wherein the first , second and third holes in combination provide a contact hole in the interlevel dielectric layer . US5912188A CLAIM 21 . A method of forming a contact hole in an interlevel dielectric layer using dual etch stops , comprising the sequence set forth : providing a semiconductor substrate ; forming a gate oxide (second etch) over the substrate ; forming a polysilicon gate on the gate oxide ; forming a source/drain region in the substrate and providing a source/drain contact electrically coupled to the source/drain region , wherein a distance between a top surface of the polysilicon gate and the substrate is greater than a distance between a top surface of the source/drain contact and the substrate ; forming an interlevel dielectric layer that consists of first , second and third dielectric layers over the source/drain contact , including forming the first dielectric layer on the second dielectric layer , forming the second dielectric layer on the third dielectric layer , and forming the third dielectric layer on the source/drain contact , wherein the first and third dielectric layers are the same material , the polysilicon gate has a greater thickness than a combined thickness of the second and third dielectric layers , and the first dielectric layer has a greater thickness than the polysilicon gate ; forming a photoresist layer on the interlevel dielectric layer ; applying a first anisotropic etch which is highly selective of the first dielectric layer with respect to the second dielectric layer through an opening in the photoresist layer using the photoresist layer as an etch mask and the second dielectric layer as an etch stop , thereby forming a first hole in the first dielectric layer that extends to the second dielectric layer without extending to the third dielectric layer ; applying a second anisotropic etch which is highly selective of the second dielectric layer with respect to the third dielectric layer through the opening in the photoresist layer using the photoresist layer as an etch mask and the third dielectric layer as an etch stop , thereby forming a second hole in the second dielectric layer that extends to the third dielectric layer without extending to the source/drain contact ; and applying a third anisotropic etch which is highly selective of the third dielectric layer with respect to the source/drain contact through the opening in the photoresist layer using the photoresist layer as an etch mask , thereby forming a third hole through the third dielectric layer that extends to the source/drain contact , wherein the first , second and third holes in combination provide a contact hole with straight sidewalls in the interlevel dielectric layer . US5912188A CLAIM 30 . The method of claim 29 , wherein : the contact hole exposes the source/drain contact , a dielectric isolation region in the substrate , and a second source/drain contact electrically coupled to a second source/drain region in the substrate ; and the conductive plug provides a local interconnect (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) between the source/drain contact and the second source/drain contact . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US5912188A CLAIM 11 . A method of forming a contact hole in an interlevel dielectric layer using dual etch stops , comprising : providing a semiconductor substrate ; forming a gate insulator over the substrate ; forming a gate on the gate insulator ; forming a source/drain region in the substrate ; providing a source/drain contact electrically coupled to the source/drain region ; forming an interlevel dielectric layer that includes first , second and third dielectric layers over the source/drain contact , including forming the first dielectric layer on the second dielectric layer and forming (anti reflective coating) the second dielectric layer on the third dielectric layer , wherein the gate has a greater thickness than a combined thickness of the second and third dielectric layers ; forming an etch mask over the interlevel dielectric layer ; applying a first anisotropic etch which is highly selective of the first dielectric layer with respect to the second dielectric layer through an opening in the etch mask using the second dielectric layer as an etch stop , thereby forming a first hole in the first dielectric layer that extends to the second dielectric layer without extending to the third dielectric layer ; applying a second anisotropic etch which is highly selective of the second dielectric layer with respect to the third dielectric layer through the opening in the etch mask using the third dielectric layer as an etch stop , thereby forming a second hole in the second dielectric layer that extends to the third dielectric layer without extending to the source/drain contact ; and applying a third anisotropic etch which is highly selective of the third dielectric layer with respect to the source/drain contact through the opening in the etch mask , thereby forming a third hole in the third dielectric layer that extends to the source/drain contact , wherein the first , second and third holes in combination provide a contact hole in the interlevel dielectric layer . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US6078073A Filed: 1997-06-18 Issued: 2000-06-20 Semiconductor apparatus formed by SAC (self-aligned contact) method and manufacturing method therefor (Original Assignee) Toshiba Corp (Current Assignee) Toshiba Corp Mariko Habu, Kazumasa Sunouchi, Masami Aoki, Tohru Ozaki |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region (gate electrodes) such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch (etching rate) stop layer (fourth insulating) directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer (second film) over said second etch stop layer . |
US6078073A CLAIM 1 . A semiconductor apparatus comprising : a semiconductor substrate ; a gate insulating film formed on said semiconductor substrate ; first and second gate electrodes (spacer region) formed on said gate insulating film and respectively having first and second insulating films laminated thereon ; side insulating films formed on the side walls of said first and second gate electrodes ; a wiring layer formed between said first and second gate electrodes ; a third insulating film for covering a predetermined portion on said first insulating film and said side insulating film opposite to the side wall of said first gate electrode adjacent to said wiring layer ; a fourth insulating (first etch stop layer) film for covering a predetermined portion on said second insulating film and said side insulating film opposite to the side wall of said second gate electrode adjacent to said wiring layer ; respective interlayer dielectric films covering the third insulating film and the fourth insulating film ; a first diffusion layer formed on the two sides of a region which is formed below said first and second gate electrodes and in which a channel will be formed , said first diffusion layer being formed on the surface of said semiconductor substrate ; and a second diffusion layer having an end adjacent to said region in which said channel will be formed and located more apart from said region in which said channel will be formed than the end of said first diffusion layer adjacent to said region in which said channel will be formed , said second diffusion layer having a bottom portion which is deeper than the bottom portion of said first diffusion layer , wherein etching rate (first etch, etch process) s of said third insulating film , said fourth insulating film , and said respective interlayer dielectric films are about the same and higher than etching rates of said first and second insulating films and said side insulating films . US6078073A CLAIM 7 . A semiconductor apparatus comprising : a semiconductor substrate ; a gate insulating film formed on said semiconductor substrate ; first and second gate electrodes formed on said gate insulating film and respectively having first and second insulating films laminated thereon ; side insulating films formed on the side walls of said first and second gate electrodes ; a wiring layer formed between said first and second gate electrodes ; a first BPSG film covering a predetermined portion on said first insulating film and said side insulating film opposite to the side wall of said first gate electrode adjacent to said wiring layer ; a second BSPG film covering a predetermined portion on said second insulating film and said side insulating film opposite to the side wall of said second gate electrode adjacent to said wiring layer ; respective interlayer BSG films covering the first BPSG film and the second BPSG film ; a first diffusion layer formed on the two sides of a region which is formed below said first and second gate electrodes and in which a channel will be formed , said first diffusion layer being formed on the surface of said semiconductor substrate ; and a second diffusion layer having an end adjacent to said region in which said channel will be formed and located more apart from said region in which said channel will be formed than the end of said first diffusion layer adjacent to said region in which said channel will be formed , said second diffusion layer having a bottom portion which is deeper than the bottom portion of said first diffusion layer , wherein etching rates of the first BPSG film , the second BPSG film and the respective interlayer BSG films are higher than etching rates of the first and second film (second sub interlevel dielectric layer) s and the side insulating films . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch (etching rate) stop layer (fourth insulating) protects removal of a substrate material by an etch process (etching rate) . |
US6078073A CLAIM 1 . A semiconductor apparatus comprising : a semiconductor substrate ; a gate insulating film formed on said semiconductor substrate ; first and second gate electrodes formed on said gate insulating film and respectively having first and second insulating films laminated thereon ; side insulating films formed on the side walls of said first and second gate electrodes ; a wiring layer formed between said first and second gate electrodes ; a third insulating film for covering a predetermined portion on said first insulating film and said side insulating film opposite to the side wall of said first gate electrode adjacent to said wiring layer ; a fourth insulating (first etch stop layer) film for covering a predetermined portion on said second insulating film and said side insulating film opposite to the side wall of said second gate electrode adjacent to said wiring layer ; respective interlayer dielectric films covering the third insulating film and the fourth insulating film ; a first diffusion layer formed on the two sides of a region which is formed below said first and second gate electrodes and in which a channel will be formed , said first diffusion layer being formed on the surface of said semiconductor substrate ; and a second diffusion layer having an end adjacent to said region in which said channel will be formed and located more apart from said region in which said channel will be formed than the end of said first diffusion layer adjacent to said region in which said channel will be formed , said second diffusion layer having a bottom portion which is deeper than the bottom portion of said first diffusion layer , wherein etching rate (first etch, etch process) s of said third insulating film , said fourth insulating film , and said respective interlayer dielectric films are about the same and higher than etching rates of said first and second insulating films and said side insulating films . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric layer (second film) insulates said contact region . |
US6078073A CLAIM 7 . A semiconductor apparatus comprising : a semiconductor substrate ; a gate insulating film formed on said semiconductor substrate ; first and second gate electrodes formed on said gate insulating film and respectively having first and second insulating films laminated thereon ; side insulating films formed on the side walls of said first and second gate electrodes ; a wiring layer formed between said first and second gate electrodes ; a first BPSG film covering a predetermined portion on said first insulating film and said side insulating film opposite to the side wall of said first gate electrode adjacent to said wiring layer ; a second BSPG film covering a predetermined portion on said second insulating film and said side insulating film opposite to the side wall of said second gate electrode adjacent to said wiring layer ; respective interlayer BSG films covering the first BPSG film and the second BPSG film ; a first diffusion layer formed on the two sides of a region which is formed below said first and second gate electrodes and in which a channel will be formed , said first diffusion layer being formed on the surface of said semiconductor substrate ; and a second diffusion layer having an end adjacent to said region in which said channel will be formed and located more apart from said region in which said channel will be formed than the end of said first diffusion layer adjacent to said region in which said channel will be formed , said second diffusion layer having a bottom portion which is deeper than the bottom portion of said first diffusion layer , wherein etching rates of the first BPSG film , the second BPSG film and the respective interlayer BSG films are higher than etching rates of the first and second film (second sub interlevel dielectric layer) s and the side insulating films . |
| US7977797B2 CLAIM 6 . An integrated circuit of claim 1 wherein said spacer region (gate electrodes) insulates said contact region . |
US6078073A CLAIM 1 . A semiconductor apparatus comprising : a semiconductor substrate ; a gate insulating film formed on said semiconductor substrate ; first and second gate electrodes (spacer region) formed on said gate insulating film and respectively having first and second insulating films laminated thereon ; side insulating films formed on the side walls of said first and second gate electrodes ; a wiring layer formed between said first and second gate electrodes ; a third insulating film for covering a predetermined portion on said first insulating film and said side insulating film opposite to the side wall of said first gate electrode adjacent to said wiring layer ; a fourth insulating film for covering a predetermined portion on said second insulating film and said side insulating film opposite to the side wall of said second gate electrode adjacent to said wiring layer ; respective interlayer dielectric films covering the third insulating film and the fourth insulating film ; a first diffusion layer formed on the two sides of a region which is formed below said first and second gate electrodes and in which a channel will be formed , said first diffusion layer being formed on the surface of said semiconductor substrate ; and a second diffusion layer having an end adjacent to said region in which said channel will be formed and located more apart from said region in which said channel will be formed than the end of said first diffusion layer adjacent to said region in which said channel will be formed , said second diffusion layer having a bottom portion which is deeper than the bottom portion of said first diffusion layer , wherein etching rates of said third insulating film , said fourth insulating film , and said respective interlayer dielectric films are about the same and higher than etching rates of said first and second insulating films and said side insulating films . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch (etching rate) stop layer (fourth insulating) is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer (second film) is in a range of about 10K ű1K Šthick . |
US6078073A CLAIM 1 . A semiconductor apparatus comprising : a semiconductor substrate ; a gate insulating film formed on said semiconductor substrate ; first and second gate electrodes formed on said gate insulating film and respectively having first and second insulating films laminated thereon ; side insulating films formed on the side walls of said first and second gate electrodes ; a wiring layer formed between said first and second gate electrodes ; a third insulating film for covering a predetermined portion on said first insulating film and said side insulating film opposite to the side wall of said first gate electrode adjacent to said wiring layer ; a fourth insulating (first etch stop layer) film for covering a predetermined portion on said second insulating film and said side insulating film opposite to the side wall of said second gate electrode adjacent to said wiring layer ; respective interlayer dielectric films covering the third insulating film and the fourth insulating film ; a first diffusion layer formed on the two sides of a region which is formed below said first and second gate electrodes and in which a channel will be formed , said first diffusion layer being formed on the surface of said semiconductor substrate ; and a second diffusion layer having an end adjacent to said region in which said channel will be formed and located more apart from said region in which said channel will be formed than the end of said first diffusion layer adjacent to said region in which said channel will be formed , said second diffusion layer having a bottom portion which is deeper than the bottom portion of said first diffusion layer , wherein etching rate (first etch, etch process) s of said third insulating film , said fourth insulating film , and said respective interlayer dielectric films are about the same and higher than etching rates of said first and second insulating films and said side insulating films . US6078073A CLAIM 7 . A semiconductor apparatus comprising : a semiconductor substrate ; a gate insulating film formed on said semiconductor substrate ; first and second gate electrodes formed on said gate insulating film and respectively having first and second insulating films laminated thereon ; side insulating films formed on the side walls of said first and second gate electrodes ; a wiring layer formed between said first and second gate electrodes ; a first BPSG film covering a predetermined portion on said first insulating film and said side insulating film opposite to the side wall of said first gate electrode adjacent to said wiring layer ; a second BSPG film covering a predetermined portion on said second insulating film and said side insulating film opposite to the side wall of said second gate electrode adjacent to said wiring layer ; respective interlayer BSG films covering the first BPSG film and the second BPSG film ; a first diffusion layer formed on the two sides of a region which is formed below said first and second gate electrodes and in which a channel will be formed , said first diffusion layer being formed on the surface of said semiconductor substrate ; and a second diffusion layer having an end adjacent to said region in which said channel will be formed and located more apart from said region in which said channel will be formed than the end of said first diffusion layer adjacent to said region in which said channel will be formed , said second diffusion layer having a bottom portion which is deeper than the bottom portion of said first diffusion layer , wherein etching rates of the first BPSG film , the second BPSG film and the respective interlayer BSG films are higher than etching rates of the first and second film (second sub interlevel dielectric layer) s and the side insulating films . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer (second film) for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US6078073A CLAIM 7 . A semiconductor apparatus comprising : a semiconductor substrate ; a gate insulating film formed on said semiconductor substrate ; first and second gate electrodes formed on said gate insulating film and respectively having first and second insulating films laminated thereon ; side insulating films formed on the side walls of said first and second gate electrodes ; a wiring layer formed between said first and second gate electrodes ; a first BPSG film covering a predetermined portion on said first insulating film and said side insulating film opposite to the side wall of said first gate electrode adjacent to said wiring layer ; a second BSPG film covering a predetermined portion on said second insulating film and said side insulating film opposite to the side wall of said second gate electrode adjacent to said wiring layer ; respective interlayer BSG films covering the first BPSG film and the second BPSG film ; a first diffusion layer formed on the two sides of a region which is formed below said first and second gate electrodes and in which a channel will be formed , said first diffusion layer being formed on the surface of said semiconductor substrate ; and a second diffusion layer having an end adjacent to said region in which said channel will be formed and located more apart from said region in which said channel will be formed than the end of said first diffusion layer adjacent to said region in which said channel will be formed , said second diffusion layer having a bottom portion which is deeper than the bottom portion of said first diffusion layer , wherein etching rates of the first BPSG film , the second BPSG film and the respective interlayer BSG films are higher than etching rates of the first and second film (second sub interlevel dielectric layer) s and the side insulating films . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch (etching rate) stop layer (fourth insulating) and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer (second film) and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US6078073A CLAIM 1 . A semiconductor apparatus comprising : a semiconductor substrate ; a gate insulating film formed on said semiconductor substrate ; first and second gate electrodes formed on said gate insulating film and respectively having first and second insulating films laminated thereon ; side insulating films formed on the side walls of said first and second gate electrodes ; a wiring layer formed between said first and second gate electrodes ; a third insulating film for covering a predetermined portion on said first insulating film and said side insulating film opposite to the side wall of said first gate electrode adjacent to said wiring layer ; a fourth insulating (first etch stop layer) film for covering a predetermined portion on said second insulating film and said side insulating film opposite to the side wall of said second gate electrode adjacent to said wiring layer ; respective interlayer dielectric films covering the third insulating film and the fourth insulating film ; a first diffusion layer formed on the two sides of a region which is formed below said first and second gate electrodes and in which a channel will be formed , said first diffusion layer being formed on the surface of said semiconductor substrate ; and a second diffusion layer having an end adjacent to said region in which said channel will be formed and located more apart from said region in which said channel will be formed than the end of said first diffusion layer adjacent to said region in which said channel will be formed , said second diffusion layer having a bottom portion which is deeper than the bottom portion of said first diffusion layer , wherein etching rate (first etch, etch process) s of said third insulating film , said fourth insulating film , and said respective interlayer dielectric films are about the same and higher than etching rates of said first and second insulating films and said side insulating films . US6078073A CLAIM 7 . A semiconductor apparatus comprising : a semiconductor substrate ; a gate insulating film formed on said semiconductor substrate ; first and second gate electrodes formed on said gate insulating film and respectively having first and second insulating films laminated thereon ; side insulating films formed on the side walls of said first and second gate electrodes ; a wiring layer formed between said first and second gate electrodes ; a first BPSG film covering a predetermined portion on said first insulating film and said side insulating film opposite to the side wall of said first gate electrode adjacent to said wiring layer ; a second BSPG film covering a predetermined portion on said second insulating film and said side insulating film opposite to the side wall of said second gate electrode adjacent to said wiring layer ; respective interlayer BSG films covering the first BPSG film and the second BPSG film ; a first diffusion layer formed on the two sides of a region which is formed below said first and second gate electrodes and in which a channel will be formed , said first diffusion layer being formed on the surface of said semiconductor substrate ; and a second diffusion layer having an end adjacent to said region in which said channel will be formed and located more apart from said region in which said channel will be formed than the end of said first diffusion layer adjacent to said region in which said channel will be formed , said second diffusion layer having a bottom portion which is deeper than the bottom portion of said first diffusion layer , wherein etching rates of the first BPSG film , the second BPSG film and the respective interlayer BSG films are higher than etching rates of the first and second film (second sub interlevel dielectric layer) s and the side insulating films . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch (etching rate) stop layer (fourth insulating) is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer (second film) is in a range of about 10K ű1K Šthick . |
US6078073A CLAIM 1 . A semiconductor apparatus comprising : a semiconductor substrate ; a gate insulating film formed on said semiconductor substrate ; first and second gate electrodes formed on said gate insulating film and respectively having first and second insulating films laminated thereon ; side insulating films formed on the side walls of said first and second gate electrodes ; a wiring layer formed between said first and second gate electrodes ; a third insulating film for covering a predetermined portion on said first insulating film and said side insulating film opposite to the side wall of said first gate electrode adjacent to said wiring layer ; a fourth insulating (first etch stop layer) film for covering a predetermined portion on said second insulating film and said side insulating film opposite to the side wall of said second gate electrode adjacent to said wiring layer ; respective interlayer dielectric films covering the third insulating film and the fourth insulating film ; a first diffusion layer formed on the two sides of a region which is formed below said first and second gate electrodes and in which a channel will be formed , said first diffusion layer being formed on the surface of said semiconductor substrate ; and a second diffusion layer having an end adjacent to said region in which said channel will be formed and located more apart from said region in which said channel will be formed than the end of said first diffusion layer adjacent to said region in which said channel will be formed , said second diffusion layer having a bottom portion which is deeper than the bottom portion of said first diffusion layer , wherein etching rate (first etch, etch process) s of said third insulating film , said fourth insulating film , and said respective interlayer dielectric films are about the same and higher than etching rates of said first and second insulating films and said side insulating films . US6078073A CLAIM 7 . A semiconductor apparatus comprising : a semiconductor substrate ; a gate insulating film formed on said semiconductor substrate ; first and second gate electrodes formed on said gate insulating film and respectively having first and second insulating films laminated thereon ; side insulating films formed on the side walls of said first and second gate electrodes ; a wiring layer formed between said first and second gate electrodes ; a first BPSG film covering a predetermined portion on said first insulating film and said side insulating film opposite to the side wall of said first gate electrode adjacent to said wiring layer ; a second BSPG film covering a predetermined portion on said second insulating film and said side insulating film opposite to the side wall of said second gate electrode adjacent to said wiring layer ; respective interlayer BSG films covering the first BPSG film and the second BPSG film ; a first diffusion layer formed on the two sides of a region which is formed below said first and second gate electrodes and in which a channel will be formed , said first diffusion layer being formed on the surface of said semiconductor substrate ; and a second diffusion layer having an end adjacent to said region in which said channel will be formed and located more apart from said region in which said channel will be formed than the end of said first diffusion layer adjacent to said region in which said channel will be formed , said second diffusion layer having a bottom portion which is deeper than the bottom portion of said first diffusion layer , wherein etching rates of the first BPSG film , the second BPSG film and the respective interlayer BSG films are higher than etching rates of the first and second film (second sub interlevel dielectric layer) s and the side insulating films . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | JPH10270555A Filed: 1997-03-27 Issued: 1998-10-09 半導体装置及びその製造方法 (Original Assignee) Mitsubishi Electric Corp; 三菱電機株式会社 Takahisa Sakaemori, 貴尚 栄森 |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (製造方法) of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer (少なくとも) over said second etch stop layer . |
JPH10270555A CLAIM 9 【請求項９】 半導体下地層と、この半導体下地層の上 に少なくとも (second sub interlevel dielectric layer) 側面がエッチング停止膜で覆われて上記半 導体下地層に接して形成された複数の導電部と、上記複 数の導電部の上記エッチング停止膜を覆うように上記半 導体下地層の上に形成されエッチングレートの異なる複 数の層から構成された層間絶縁膜と、上記複数の導電部 の相隣るエッチング停止膜の間隙において上記層間絶縁 膜に設けられた開孔に形成され相隣るエッチング停止膜 の間隙を通って上記半導体下地層に至るコンタクトとを 備え、上記層間絶縁膜のうち上記半導体下地層及び上記 エッチング停止膜に隣接した部分が他の部分よりも相対 的にエッチングレートが高く形成されていることを特徴 とする半導体装置。 JPH10270555A CLAIM 16 【請求項１６】 上記導電部を複数形成し、相隣る上記 導電部の間に上記開孔を形成することを特徴とする請求 項１５に記載の半導体装置の製造方法 (metal layer coupling area) 。 |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric layer (少なくとも) insulates said contact region . |
JPH10270555A CLAIM 9 【請求項９】 半導体下地層と、この半導体下地層の上 に少なくとも (second sub interlevel dielectric layer) 側面がエッチング停止膜で覆われて上記半 導体下地層に接して形成された複数の導電部と、上記複 数の導電部の上記エッチング停止膜を覆うように上記半 導体下地層の上に形成されエッチングレートの異なる複 数の層から構成された層間絶縁膜と、上記複数の導電部 の相隣るエッチング停止膜の間隙において上記層間絶縁 膜に設けられた開孔に形成され相隣るエッチング停止膜 の間隙を通って上記半導体下地層に至るコンタクトとを 備え、上記層間絶縁膜のうち上記半導体下地層及び上記 エッチング停止膜に隣接した部分が他の部分よりも相対 的にエッチングレートが高く形成されていることを特徴 とする半導体装置。 |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area of said contact region permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area (製造方法) of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
JPH10270555A CLAIM 16 【請求項１６】 上記導電部を複数形成し、相隣る上記 導電部の間に上記開孔を形成することを特徴とする請求 項１５に記載の半導体装置の製造方法 (metal layer coupling area) 。 |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Å thick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Å thick , said second etch stop layer is in a range of about 300 to 800 Å thick and said second sub interlevel dielectric layer (少なくとも) is in a range of about 10K ű1K Å thick . |
JPH10270555A CLAIM 9 【請求項９】 半導体下地層と、この半導体下地層の上 に少なくとも (second sub interlevel dielectric layer) 側面がエッチング停止膜で覆われて上記半 導体下地層に接して形成された複数の導電部と、上記複 数の導電部の上記エッチング停止膜を覆うように上記半 導体下地層の上に形成されエッチングレートの異なる複 数の層から構成された層間絶縁膜と、上記複数の導電部 の相隣るエッチング停止膜の間隙において上記層間絶縁 膜に設けられた開孔に形成され相隣るエッチング停止膜 の間隙を通って上記半導体下地層に至るコンタクトとを 備え、上記層間絶縁膜のうち上記半導体下地層及び上記 エッチング停止膜に隣接した部分が他の部分よりも相対 的にエッチングレートが高く形成されていることを特徴 とする半導体装置。 |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer (少なくとも) for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
JPH10270555A CLAIM 9 【請求項９】 半導体下地層と、この半導体下地層の上 に少なくとも (second sub interlevel dielectric layer) 側面がエッチング停止膜で覆われて上記半 導体下地層に接して形成された複数の導電部と、上記複 数の導電部の上記エッチング停止膜を覆うように上記半 導体下地層の上に形成されエッチングレートの異なる複 数の層から構成された層間絶縁膜と、上記複数の導電部 の相隣るエッチング停止膜の間隙において上記層間絶縁 膜に設けられた開孔に形成され相隣るエッチング停止膜 の間隙を通って上記半導体下地層に至るコンタクトとを 備え、上記層間絶縁膜のうち上記半導体下地層及び上記 エッチング停止膜に隣接した部分が他の部分よりも相対 的にエッチングレートが高く形成されていることを特徴 とする半導体装置。 |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer (少なくとも) and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (製造方法) of said contact region . |
JPH10270555A CLAIM 9 【請求項９】 半導体下地層と、この半導体下地層の上 に少なくとも (second sub interlevel dielectric layer) 側面がエッチング停止膜で覆われて上記半 導体下地層に接して形成された複数の導電部と、上記複 数の導電部の上記エッチング停止膜を覆うように上記半 導体下地層の上に形成されエッチングレートの異なる複 数の層から構成された層間絶縁膜と、上記複数の導電部 の相隣るエッチング停止膜の間隙において上記層間絶縁 膜に設けられた開孔に形成され相隣るエッチング停止膜 の間隙を通って上記半導体下地層に至るコンタクトとを 備え、上記層間絶縁膜のうち上記半導体下地層及び上記 エッチング停止膜に隣接した部分が他の部分よりも相対 的にエッチングレートが高く形成されていることを特徴 とする半導体装置。 JPH10270555A CLAIM 16 【請求項１６】 上記導電部を複数形成し、相隣る上記 導電部の間に上記開孔を形成することを特徴とする請求 項１５に記載の半導体装置の製造方法 (metal layer coupling area) 。 |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Å thick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Å thick , said second etch stop layer is in a range of about 300 to 800 Å thick and said second sub interlevel dielectric layer (少なくとも) is in a range of about 10K ű1K Å thick . |
JPH10270555A CLAIM 9 【請求項９】 半導体下地層と、この半導体下地層の上 に少なくとも (second sub interlevel dielectric layer) 側面がエッチング停止膜で覆われて上記半 導体下地層に接して形成された複数の導電部と、上記複 数の導電部の上記エッチング停止膜を覆うように上記半 導体下地層の上に形成されエッチングレートの異なる複 数の層から構成された層間絶縁膜と、上記複数の導電部 の相隣るエッチング停止膜の間隙において上記層間絶縁 膜に設けられた開孔に形成され相隣るエッチング停止膜 の間隙を通って上記半導体下地層に至るコンタクトとを 備え、上記層間絶縁膜のうち上記半導体下地層及び上記 エッチング停止膜に隣接した部分が他の部分よりも相対 的にエッチングレートが高く形成されていることを特徴 とする半導体装置。 |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5808365A Filed: 1997-01-09 Issued: 1998-09-15 Semiconductor device and method of manufacturing the same (Original Assignee) NEC Corp (Current Assignee) NEC Electronics Corp Hidemitsu Mori |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region (second contact) coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub (upper surfaces) interlevel dielectric layer over said first etch stop layer ; a second etch (second etch) stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5808365A CLAIM 1 . A semiconductor device comprising : (a) a semiconductor substrate having a semiconductor element formed thereon ; (b) a first etching stopper insulating film formed on said semiconductor substrate ; (c) a first insulating interlayer formed on said first etching stopper insulating film and having etching selectivity with respect to said first etching stopper insulating film ; (d) at least a pair of first contact holes formed at a predetermined interval in a direction parallel to a surface of said semiconductor substrate so as to reach said semiconductor element through said first insulating interlayer and said first etching stopper insulating film ; (e) first buried conductive layers formed in the first contact holes , respectively ; (f) a first interconnection connected to one of said first buried conductive layers ; (g) a second insulating interlayer formed on said first interconnection and said first insulating interlayer ; (h) a second contact (contact region) hole formed to reach the other one of said first buried conductive layers through said second insulating interlayer ; (i) a second buried conductive layer formed in the second contact hole ; and (j) a second interconnection connected to said second buried conductive layer , wherein each of the first contact holes includes upper and lower cylindrical portions , the upper cylindrical portion having a larger diameter than the lower cylindrical portion . US5808365A CLAIM 2 . A device according to claim 1 , further comprising a second etch (second etch) ing stopper insulating film formed between said first insulating interlayer and said second insulating interlayer , wherein the second contact hole is constituted by a large-diameter upper contact hole formed in said second insulating interlayer and a small-diameter lower contact hole formed in said second etching stopper insulating film . US5808365A CLAIM 12 . A device according to claim 11 , wherein an upper surface of the first insulating interlayer is positioned above upper surfaces (first sub, first sub interlevel dielectric layer) of the first buried contacts . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub (upper surfaces) interlevel dielectric layer insulates said contact region (second contact) . |
US5808365A CLAIM 1 . A semiconductor device comprising : (a) a semiconductor substrate having a semiconductor element formed thereon ; (b) a first etching stopper insulating film formed on said semiconductor substrate ; (c) a first insulating interlayer formed on said first etching stopper insulating film and having etching selectivity with respect to said first etching stopper insulating film ; (d) at least a pair of first contact holes formed at a predetermined interval in a direction parallel to a surface of said semiconductor substrate so as to reach said semiconductor element through said first insulating interlayer and said first etching stopper insulating film ; (e) first buried conductive layers formed in the first contact holes , respectively ; (f) a first interconnection connected to one of said first buried conductive layers ; (g) a second insulating interlayer formed on said first interconnection and said first insulating interlayer ; (h) a second contact (contact region) hole formed to reach the other one of said first buried conductive layers through said second insulating interlayer ; (i) a second buried conductive layer formed in the second contact hole ; and (j) a second interconnection connected to said second buried conductive layer , wherein each of the first contact holes includes upper and lower cylindrical portions , the upper cylindrical portion having a larger diameter than the lower cylindrical portion . US5808365A CLAIM 12 . A device according to claim 11 , wherein an upper surface of the first insulating interlayer is positioned above upper surfaces (first sub, first sub interlevel dielectric layer) of the first buried contacts . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch (second etch) stop layer protects lower layers during an etching process . |
US5808365A CLAIM 2 . A device according to claim 1 , further comprising a second etch (second etch) ing stopper insulating film formed between said first insulating interlayer and said second insulating interlayer , wherein the second contact hole is constituted by a large-diameter upper contact hole formed in said second insulating interlayer and a small-diameter lower contact hole formed in said second etching stopper insulating film . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric layer insulates said contact region (second contact) . |
US5808365A CLAIM 1 . A semiconductor device comprising : (a) a semiconductor substrate having a semiconductor element formed thereon ; (b) a first etching stopper insulating film formed on said semiconductor substrate ; (c) a first insulating interlayer formed on said first etching stopper insulating film and having etching selectivity with respect to said first etching stopper insulating film ; (d) at least a pair of first contact holes formed at a predetermined interval in a direction parallel to a surface of said semiconductor substrate so as to reach said semiconductor element through said first insulating interlayer and said first etching stopper insulating film ; (e) first buried conductive layers formed in the first contact holes , respectively ; (f) a first interconnection connected to one of said first buried conductive layers ; (g) a second insulating interlayer formed on said first interconnection and said first insulating interlayer ; (h) a second contact (contact region) hole formed to reach the other one of said first buried conductive layers through said second insulating interlayer ; (i) a second buried conductive layer formed in the second contact hole ; and (j) a second interconnection connected to said second buried conductive layer , wherein each of the first contact holes includes upper and lower cylindrical portions , the upper cylindrical portion having a larger diameter than the lower cylindrical portion . |
| US7977797B2 CLAIM 6 . An integrated circuit of claim 1 wherein said spacer region insulates said contact region (second contact) . |
US5808365A CLAIM 1 . A semiconductor device comprising : (a) a semiconductor substrate having a semiconductor element formed thereon ; (b) a first etching stopper insulating film formed on said semiconductor substrate ; (c) a first insulating interlayer formed on said first etching stopper insulating film and having etching selectivity with respect to said first etching stopper insulating film ; (d) at least a pair of first contact holes formed at a predetermined interval in a direction parallel to a surface of said semiconductor substrate so as to reach said semiconductor element through said first insulating interlayer and said first etching stopper insulating film ; (e) first buried conductive layers formed in the first contact holes , respectively ; (f) a first interconnection connected to one of said first buried conductive layers ; (g) a second insulating interlayer formed on said first interconnection and said first insulating interlayer ; (h) a second contact (contact region) hole formed to reach the other one of said first buried conductive layers through said second insulating interlayer ; (i) a second buried conductive layer formed in the second contact hole ; and (j) a second interconnection connected to said second buried conductive layer , wherein each of the first contact holes includes upper and lower cylindrical portions , the upper cylindrical portion having a larger diameter than the lower cylindrical portion . |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area of said contact region (second contact) permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
US5808365A CLAIM 1 . A semiconductor device comprising : (a) a semiconductor substrate having a semiconductor element formed thereon ; (b) a first etching stopper insulating film formed on said semiconductor substrate ; (c) a first insulating interlayer formed on said first etching stopper insulating film and having etching selectivity with respect to said first etching stopper insulating film ; (d) at least a pair of first contact holes formed at a predetermined interval in a direction parallel to a surface of said semiconductor substrate so as to reach said semiconductor element through said first insulating interlayer and said first etching stopper insulating film ; (e) first buried conductive layers formed in the first contact holes , respectively ; (f) a first interconnection connected to one of said first buried conductive layers ; (g) a second insulating interlayer formed on said first interconnection and said first insulating interlayer ; (h) a second contact (contact region) hole formed to reach the other one of said first buried conductive layers through said second insulating interlayer ; (i) a second buried conductive layer formed in the second contact hole ; and (j) a second interconnection connected to said second buried conductive layer , wherein each of the first contact holes includes upper and lower cylindrical portions , the upper cylindrical portion having a larger diameter than the lower cylindrical portion . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub (upper surfaces) interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (second etch) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5808365A CLAIM 2 . A device according to claim 1 , further comprising a second etch (second etch) ing stopper insulating film formed between said first insulating interlayer and said second insulating interlayer , wherein the second contact hole is constituted by a large-diameter upper contact hole formed in said second insulating interlayer and a small-diameter lower contact hole formed in said second etching stopper insulating film . US5808365A CLAIM 12 . A device according to claim 11 , wherein an upper surface of the first insulating interlayer is positioned above upper surfaces (first sub, first sub interlevel dielectric layer) of the first buried contacts . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub (upper surfaces) interlevel dielectric layer for said contact region (second contact) is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space (storage node) in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5808365A CLAIM 1 . A semiconductor device comprising : (a) a semiconductor substrate having a semiconductor element formed thereon ; (b) a first etching stopper insulating film formed on said semiconductor substrate ; (c) a first insulating interlayer formed on said first etching stopper insulating film and having etching selectivity with respect to said first etching stopper insulating film ; (d) at least a pair of first contact holes formed at a predetermined interval in a direction parallel to a surface of said semiconductor substrate so as to reach said semiconductor element through said first insulating interlayer and said first etching stopper insulating film ; (e) first buried conductive layers formed in the first contact holes , respectively ; (f) a first interconnection connected to one of said first buried conductive layers ; (g) a second insulating interlayer formed on said first interconnection and said first insulating interlayer ; (h) a second contact (contact region) hole formed to reach the other one of said first buried conductive layers through said second insulating interlayer ; (i) a second buried conductive layer formed in the second contact hole ; and (j) a second interconnection connected to said second buried conductive layer , wherein each of the first contact holes includes upper and lower cylindrical portions , the upper cylindrical portion having a larger diameter than the lower cylindrical portion . US5808365A CLAIM 5 . A device according to claim 1 , wherein said semiconductor element is a DRAM memory cell , said first interconnection is a bit line , and said second interconnection is a storage node (second space, floating gate) electrode . US5808365A CLAIM 12 . A device according to claim 11 , wherein an upper surface of the first insulating interlayer is positioned above upper surfaces (first sub, first sub interlevel dielectric layer) of the first buried contacts . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch (second etch) stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region (second contact) and under a first sub (upper surfaces) interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US5808365A CLAIM 1 . A semiconductor device comprising : (a) a semiconductor substrate having a semiconductor element formed thereon ; (b) a first etching stopper insulating film formed on said semiconductor substrate ; (c) a first insulating interlayer formed on said first etching stopper insulating film and having etching selectivity with respect to said first etching stopper insulating film ; (d) at least a pair of first contact holes formed at a predetermined interval in a direction parallel to a surface of said semiconductor substrate so as to reach said semiconductor element through said first insulating interlayer and said first etching stopper insulating film ; (e) first buried conductive layers formed in the first contact holes , respectively ; (f) a first interconnection connected to one of said first buried conductive layers ; (g) a second insulating interlayer formed on said first interconnection and said first insulating interlayer ; (h) a second contact (contact region) hole formed to reach the other one of said first buried conductive layers through said second insulating interlayer ; (i) a second buried conductive layer formed in the second contact hole ; and (j) a second interconnection connected to said second buried conductive layer , wherein each of the first contact holes includes upper and lower cylindrical portions , the upper cylindrical portion having a larger diameter than the lower cylindrical portion . US5808365A CLAIM 2 . A device according to claim 1 , further comprising a second etch (second etch) ing stopper insulating film formed between said first insulating interlayer and said second insulating interlayer , wherein the second contact hole is constituted by a large-diameter upper contact hole formed in said second insulating interlayer and a small-diameter lower contact hole formed in said second etching stopper insulating film . US5808365A CLAIM 12 . A device according to claim 11 , wherein an upper surface of the first insulating interlayer is positioned above upper surfaces (first sub, first sub interlevel dielectric layer) of the first buried contacts . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub (upper surfaces) interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (second etch) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5808365A CLAIM 2 . A device according to claim 1 , further comprising a second etch (second etch) ing stopper insulating film formed between said first insulating interlayer and said second insulating interlayer , wherein the second contact hole is constituted by a large-diameter upper contact hole formed in said second insulating interlayer and a small-diameter lower contact hole formed in said second etching stopper insulating film . US5808365A CLAIM 12 . A device according to claim 11 , wherein an upper surface of the first insulating interlayer is positioned above upper surfaces (first sub, first sub interlevel dielectric layer) of the first buried contacts . |
| US7977797B2 CLAIM 13 . An integrated circuit of claim 11 further comprising a floating gate (storage node) . |
US5808365A CLAIM 5 . A device according to claim 1 , wherein said semiconductor element is a DRAM memory cell , said first interconnection is a bit line , and said second interconnection is a storage node (second space, floating gate) electrode . |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region (second contact) is a first range of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5808365A CLAIM 1 . A semiconductor device comprising : (a) a semiconductor substrate having a semiconductor element formed thereon ; (b) a first etching stopper insulating film formed on said semiconductor substrate ; (c) a first insulating interlayer formed on said first etching stopper insulating film and having etching selectivity with respect to said first etching stopper insulating film ; (d) at least a pair of first contact holes formed at a predetermined interval in a direction parallel to a surface of said semiconductor substrate so as to reach said semiconductor element through said first insulating interlayer and said first etching stopper insulating film ; (e) first buried conductive layers formed in the first contact holes , respectively ; (f) a first interconnection connected to one of said first buried conductive layers ; (g) a second insulating interlayer formed on said first interconnection and said first insulating interlayer ; (h) a second contact (contact region) hole formed to reach the other one of said first buried conductive layers through said second insulating interlayer ; (i) a second buried conductive layer formed in the second contact hole ; and (j) a second interconnection connected to said second buried conductive layer , wherein each of the first contact holes includes upper and lower cylindrical portions , the upper cylindrical portion having a larger diameter than the lower cylindrical portion . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5726499A Filed: 1996-07-22 Issued: 1998-03-10 Semiconductor device having a minute contact hole (Original Assignee) Ricoh Co Ltd (Current Assignee) Ricoh Co Ltd Mitsugu Irinoda |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region (second regions) coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region (second regions) such that a substrate coupling area (second conductive layer) of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch (second insulating layers, dry etch) stop insulation layer (second insulating layers, dry etch) coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (upper electrode) layer over said first etch stop layer ; a second etch (second insulating layers, dry etch) stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5726499A CLAIM 1 . A contact structure , comprising : a conductive first layer ; a second layer of an insulating material provided on said first layer ; a third layer provided on said second layer ; a depression provided on said second and third layers so as to extend from a top surface of said third layer toward a bottom surface of said second layer , said depression having a bottom surface above said bottom surface of said second layer and below a bottom surface of said third layer , said depression being defined by a first inner peripheral wall having a first inner diameter and extending from said top surface of said third layer to said bottom surface of said depression , said first inner peripheral wall surrounding said depression continuously ; a through hole provided on said bottom surface of said depression generally at a center thereof , such that said through hole extends from said bottom surface of said depression to said bottom surface of said second layer , said through hole thereby exposing a top surface of said first layer and being defined by a second inner periphery having a second inner diameter substantially smaller than said first inner diameter ; a ring-shaped wall member fitted in said depression so as to form an intimate contact with said first inner peripheral wall of said depression , said ring-shaped wall member being thereby defined by a third inner peripheral wall having a third inner diameter substantially identical to said second inner diameter of said through hole , said third layer being formed of an inorganic insulating material that shows a resistance to a dry etch (multiple etch stop insulation layer, multiple etch, second etch, second etch stop layer, second etch stop layers) ing process with respect to said material forming said second layer , said ring-shaped wall member being formed of an inorganic material that shows a selectivity to a dry etching process with respect to said material forming said second layer . US5726499A CLAIM 15 . A semiconductor device as claimed in claim 14 , wherein said first conductive layer includes a diffusion region formed in said semiconductor substrate , and said second conductive layer (substrate coupling area) includes a conductor pattern provided on a field oxide film provided on said semiconductor substrate . US5726499A CLAIM 17 . A semiconductor integrated circuit as claimed in claim 16 , wherein said semiconductor integrated circuit further comprises an multilayer interconnection structure , said multilayer interconnection structure comprising , in each of said semiconductor devices : an interconnection pattern provided on said third layer in electric connection with said electrode ; a fourth layer of an insulating material provided on said third layer so as to bury said interconnection pattern underneath ; a fifth layer provided on said second layer ; a second depression provided on said fourth and fifth layers so as to extend from a top surface of said fifth layer toward a bottom surface of said fourth layer , said second depression having a bottom surface above said bottom surface of said fourth layer and below a bottom surface of said fifth layer , said second depression being defined by a first inner peripheral wall having a first inner diameter and extending from said top surface of said fifth layer to said bottom surface of said second depression ; a second through hole provided on said bottom surface of said second depression generally at a center thereof , such that said second through hole extends from said bottom surface of said second depression to said bottom surface of said fourth layer , said through hole thereby exposing a top surface of said interconnection pattern and being defined by a second inner periphery having a second inner diameter substantially smaller than said first inner diameter of said second depression ; a second ring-shaped wall member fitted in said second depression so as to form an intimate contact with said first inner peripheral wall of said second depression , said second ring-shaped wall member being thereby defined by a third inner peripheral wall having a third inner diameter substantially identical to said second inner diameter of said second through hole ; and an upper electrode (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) filling said second ring-shaped wall member and said second through hole in an intimate contact with said interconnection pattern ; said fifth layer being formed of an inorganic insulating material that shows a selectivity to a dry etching process with respect to said material forming said fourth layer , said second ring-shaped wall member being formed of an inorganic material that shows a selectivity to a dry etching process with respect to said material forming said second layer . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (upper electrode) layer insulates said contact region (second regions) . |
US5726499A CLAIM 17 . A semiconductor integrated circuit as claimed in claim 16 , wherein said semiconductor integrated circuit further comprises an multilayer interconnection structure , said multilayer interconnection structure comprising , in each of said semiconductor devices : an interconnection pattern provided on said third layer in electric connection with said electrode ; a fourth layer of an insulating material provided on said third layer so as to bury said interconnection pattern underneath ; a fifth layer provided on said second layer ; a second depression provided on said fourth and fifth layers so as to extend from a top surface of said fifth layer toward a bottom surface of said fourth layer , said second depression having a bottom surface above said bottom surface of said fourth layer and below a bottom surface of said fifth layer , said second depression being defined by a first inner peripheral wall having a first inner diameter and extending from said top surface of said fifth layer to said bottom surface of said second depression ; a second through hole provided on said bottom surface of said second depression generally at a center thereof , such that said second through hole extends from said bottom surface of said second depression to said bottom surface of said fourth layer , said through hole thereby exposing a top surface of said interconnection pattern and being defined by a second inner periphery having a second inner diameter substantially smaller than said first inner diameter of said second depression ; a second ring-shaped wall member fitted in said second depression so as to form an intimate contact with said first inner peripheral wall of said second depression , said second ring-shaped wall member being thereby defined by a third inner peripheral wall having a third inner diameter substantially identical to said second inner diameter of said second through hole ; and an upper electrode (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) filling said second ring-shaped wall member and said second through hole in an intimate contact with said interconnection pattern ; said fifth layer being formed of an inorganic insulating material that shows a selectivity to a dry etching process with respect to said material forming said fourth layer , said second ring-shaped wall member being formed of an inorganic material that shows a selectivity to a dry etching process with respect to said material forming said second layer . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch (second insulating layers, dry etch) stop layer protects lower layers during an etching process (doped polysilicon, etching process) . |
US5726499A CLAIM 1 . A contact structure , comprising : a conductive first layer ; a second layer of an insulating material provided on said first layer ; a third layer provided on said second layer ; a depression provided on said second and third layers so as to extend from a top surface of said third layer toward a bottom surface of said second layer , said depression having a bottom surface above said bottom surface of said second layer and below a bottom surface of said third layer , said depression being defined by a first inner peripheral wall having a first inner diameter and extending from said top surface of said third layer to said bottom surface of said depression , said first inner peripheral wall surrounding said depression continuously ; a through hole provided on said bottom surface of said depression generally at a center thereof , such that said through hole extends from said bottom surface of said depression to said bottom surface of said second layer , said through hole thereby exposing a top surface of said first layer and being defined by a second inner periphery having a second inner diameter substantially smaller than said first inner diameter ; a ring-shaped wall member fitted in said depression so as to form an intimate contact with said first inner peripheral wall of said depression , said ring-shaped wall member being thereby defined by a third inner peripheral wall having a third inner diameter substantially identical to said second inner diameter of said through hole , said third layer being formed of an inorganic insulating material that shows a resistance to a dry etching process (etching process) with respect to said material forming said second layer , said ring-shaped wall member being formed of an inorganic material that shows a selectivity to a dry etching process with respect to said material forming said second layer . US5726499A CLAIM 3 . A contact structure as claimed in claim 1 wherein said ring-shaped wall member comprises an undoped polysilicon (etching process) . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (upper electrode) layer insulates said contact region (second regions) . |
US5726499A CLAIM 17 . A semiconductor integrated circuit as claimed in claim 16 , wherein said semiconductor integrated circuit further comprises an multilayer interconnection structure , said multilayer interconnection structure comprising , in each of said semiconductor devices : an interconnection pattern provided on said third layer in electric connection with said electrode ; a fourth layer of an insulating material provided on said third layer so as to bury said interconnection pattern underneath ; a fifth layer provided on said second layer ; a second depression provided on said fourth and fifth layers so as to extend from a top surface of said fifth layer toward a bottom surface of said fourth layer , said second depression having a bottom surface above said bottom surface of said fourth layer and below a bottom surface of said fifth layer , said second depression being defined by a first inner peripheral wall having a first inner diameter and extending from said top surface of said fifth layer to said bottom surface of said second depression ; a second through hole provided on said bottom surface of said second depression generally at a center thereof , such that said second through hole extends from said bottom surface of said second depression to said bottom surface of said fourth layer , said through hole thereby exposing a top surface of said interconnection pattern and being defined by a second inner periphery having a second inner diameter substantially smaller than said first inner diameter of said second depression ; a second ring-shaped wall member fitted in said second depression so as to form an intimate contact with said first inner peripheral wall of said second depression , said second ring-shaped wall member being thereby defined by a third inner peripheral wall having a third inner diameter substantially identical to said second inner diameter of said second through hole ; and an upper electrode (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) filling said second ring-shaped wall member and said second through hole in an intimate contact with said interconnection pattern ; said fifth layer being formed of an inorganic insulating material that shows a selectivity to a dry etching process with respect to said material forming said fourth layer , said second ring-shaped wall member being formed of an inorganic material that shows a selectivity to a dry etching process with respect to said material forming said second layer . |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area (second conductive layer) of said contact region (second regions) permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
US5726499A CLAIM 15 . A semiconductor device as claimed in claim 14 , wherein said first conductive layer includes a diffusion region formed in said semiconductor substrate , and said second conductive layer (substrate coupling area) includes a conductor pattern provided on a field oxide film provided on said semiconductor substrate . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (upper electrode) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (second insulating layers, dry etch) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5726499A CLAIM 1 . A contact structure , comprising : a conductive first layer ; a second layer of an insulating material provided on said first layer ; a third layer provided on said second layer ; a depression provided on said second and third layers so as to extend from a top surface of said third layer toward a bottom surface of said second layer , said depression having a bottom surface above said bottom surface of said second layer and below a bottom surface of said third layer , said depression being defined by a first inner peripheral wall having a first inner diameter and extending from said top surface of said third layer to said bottom surface of said depression , said first inner peripheral wall surrounding said depression continuously ; a through hole provided on said bottom surface of said depression generally at a center thereof , such that said through hole extends from said bottom surface of said depression to said bottom surface of said second layer , said through hole thereby exposing a top surface of said first layer and being defined by a second inner periphery having a second inner diameter substantially smaller than said first inner diameter ; a ring-shaped wall member fitted in said depression so as to form an intimate contact with said first inner peripheral wall of said depression , said ring-shaped wall member being thereby defined by a third inner peripheral wall having a third inner diameter substantially identical to said second inner diameter of said through hole , said third layer being formed of an inorganic insulating material that shows a resistance to a dry etch (multiple etch stop insulation layer, multiple etch, second etch, second etch stop layer, second etch stop layers) ing process with respect to said material forming said second layer , said ring-shaped wall member being formed of an inorganic material that shows a selectivity to a dry etching process with respect to said material forming said second layer . US5726499A CLAIM 17 . A semiconductor integrated circuit as claimed in claim 16 , wherein said semiconductor integrated circuit further comprises an multilayer interconnection structure , said multilayer interconnection structure comprising , in each of said semiconductor devices : an interconnection pattern provided on said third layer in electric connection with said electrode ; a fourth layer of an insulating material provided on said third layer so as to bury said interconnection pattern underneath ; a fifth layer provided on said second layer ; a second depression provided on said fourth and fifth layers so as to extend from a top surface of said fifth layer toward a bottom surface of said fourth layer , said second depression having a bottom surface above said bottom surface of said fourth layer and below a bottom surface of said fifth layer , said second depression being defined by a first inner peripheral wall having a first inner diameter and extending from said top surface of said fifth layer to said bottom surface of said second depression ; a second through hole provided on said bottom surface of said second depression generally at a center thereof , such that said second through hole extends from said bottom surface of said second depression to said bottom surface of said fourth layer , said through hole thereby exposing a top surface of said interconnection pattern and being defined by a second inner periphery having a second inner diameter substantially smaller than said first inner diameter of said second depression ; a second ring-shaped wall member fitted in said second depression so as to form an intimate contact with said first inner peripheral wall of said second depression , said second ring-shaped wall member being thereby defined by a third inner peripheral wall having a third inner diameter substantially identical to said second inner diameter of said second through hole ; and an upper electrode (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) filling said second ring-shaped wall member and said second through hole in an intimate contact with said interconnection pattern ; said fifth layer being formed of an inorganic insulating material that shows a selectivity to a dry etching process with respect to said material forming said fourth layer , said second ring-shaped wall member being formed of an inorganic material that shows a selectivity to a dry etching process with respect to said material forming said second layer . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric (upper electrode) layer for said contact region (second regions) is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5726499A CLAIM 17 . A semiconductor integrated circuit as claimed in claim 16 , wherein said semiconductor integrated circuit further comprises an multilayer interconnection structure , said multilayer interconnection structure comprising , in each of said semiconductor devices : an interconnection pattern provided on said third layer in electric connection with said electrode ; a fourth layer of an insulating material provided on said third layer so as to bury said interconnection pattern underneath ; a fifth layer provided on said second layer ; a second depression provided on said fourth and fifth layers so as to extend from a top surface of said fifth layer toward a bottom surface of said fourth layer , said second depression having a bottom surface above said bottom surface of said fourth layer and below a bottom surface of said fifth layer , said second depression being defined by a first inner peripheral wall having a first inner diameter and extending from said top surface of said fifth layer to said bottom surface of said second depression ; a second through hole provided on said bottom surface of said second depression generally at a center thereof , such that said second through hole extends from said bottom surface of said second depression to said bottom surface of said fourth layer , said through hole thereby exposing a top surface of said interconnection pattern and being defined by a second inner periphery having a second inner diameter substantially smaller than said first inner diameter of said second depression ; a second ring-shaped wall member fitted in said second depression so as to form an intimate contact with said first inner peripheral wall of said second depression , said second ring-shaped wall member being thereby defined by a third inner peripheral wall having a third inner diameter substantially identical to said second inner diameter of said second through hole ; and an upper electrode (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) filling said second ring-shaped wall member and said second through hole in an intimate contact with said interconnection pattern ; said fifth layer being formed of an inorganic insulating material that shows a selectivity to a dry etching process with respect to said material forming said fourth layer , said second ring-shaped wall member being formed of an inorganic material that shows a selectivity to a dry etching process with respect to said material forming said second layer . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch (second insulating layers, dry etch) stop insulation layer (second insulating layers, dry etch) comprising a first etch stop layer and a second etch (second insulating layers, dry etch) stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region (second regions) and under a first sub interlevel dielectric (upper electrode) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area (second conductive layer) of said contact region is smaller than a metal layer coupling area of said contact region . |
US5726499A CLAIM 1 . A contact structure , comprising : a conductive first layer ; a second layer of an insulating material provided on said first layer ; a third layer provided on said second layer ; a depression provided on said second and third layers so as to extend from a top surface of said third layer toward a bottom surface of said second layer , said depression having a bottom surface above said bottom surface of said second layer and below a bottom surface of said third layer , said depression being defined by a first inner peripheral wall having a first inner diameter and extending from said top surface of said third layer to said bottom surface of said depression , said first inner peripheral wall surrounding said depression continuously ; a through hole provided on said bottom surface of said depression generally at a center thereof , such that said through hole extends from said bottom surface of said depression to said bottom surface of said second layer , said through hole thereby exposing a top surface of said first layer and being defined by a second inner periphery having a second inner diameter substantially smaller than said first inner diameter ; a ring-shaped wall member fitted in said depression so as to form an intimate contact with said first inner peripheral wall of said depression , said ring-shaped wall member being thereby defined by a third inner peripheral wall having a third inner diameter substantially identical to said second inner diameter of said through hole , said third layer being formed of an inorganic insulating material that shows a resistance to a dry etch (multiple etch stop insulation layer, multiple etch, second etch, second etch stop layer, second etch stop layers) ing process with respect to said material forming said second layer , said ring-shaped wall member being formed of an inorganic material that shows a selectivity to a dry etching process with respect to said material forming said second layer . US5726499A CLAIM 15 . A semiconductor device as claimed in claim 14 , wherein said first conductive layer includes a diffusion region formed in said semiconductor substrate , and said second conductive layer (substrate coupling area) includes a conductor pattern provided on a field oxide film provided on said semiconductor substrate . US5726499A CLAIM 17 . A semiconductor integrated circuit as claimed in claim 16 , wherein said semiconductor integrated circuit further comprises an multilayer interconnection structure , said multilayer interconnection structure comprising , in each of said semiconductor devices : an interconnection pattern provided on said third layer in electric connection with said electrode ; a fourth layer of an insulating material provided on said third layer so as to bury said interconnection pattern underneath ; a fifth layer provided on said second layer ; a second depression provided on said fourth and fifth layers so as to extend from a top surface of said fifth layer toward a bottom surface of said fourth layer , said second depression having a bottom surface above said bottom surface of said fourth layer and below a bottom surface of said fifth layer , said second depression being defined by a first inner peripheral wall having a first inner diameter and extending from said top surface of said fifth layer to said bottom surface of said second depression ; a second through hole provided on said bottom surface of said second depression generally at a center thereof , such that said second through hole extends from said bottom surface of said second depression to said bottom surface of said fourth layer , said through hole thereby exposing a top surface of said interconnection pattern and being defined by a second inner periphery having a second inner diameter substantially smaller than said first inner diameter of said second depression ; a second ring-shaped wall member fitted in said second depression so as to form an intimate contact with said first inner peripheral wall of said second depression , said second ring-shaped wall member being thereby defined by a third inner peripheral wall having a third inner diameter substantially identical to said second inner diameter of said second through hole ; and an upper electrode (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) filling said second ring-shaped wall member and said second through hole in an intimate contact with said interconnection pattern ; said fifth layer being formed of an inorganic insulating material that shows a selectivity to a dry etching process with respect to said material forming said fourth layer , said second ring-shaped wall member being formed of an inorganic material that shows a selectivity to a dry etching process with respect to said material forming said second layer . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (upper electrode) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (second insulating layers, dry etch) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5726499A CLAIM 1 . A contact structure , comprising : a conductive first layer ; a second layer of an insulating material provided on said first layer ; a third layer provided on said second layer ; a depression provided on said second and third layers so as to extend from a top surface of said third layer toward a bottom surface of said second layer , said depression having a bottom surface above said bottom surface of said second layer and below a bottom surface of said third layer , said depression being defined by a first inner peripheral wall having a first inner diameter and extending from said top surface of said third layer to said bottom surface of said depression , said first inner peripheral wall surrounding said depression continuously ; a through hole provided on said bottom surface of said depression generally at a center thereof , such that said through hole extends from said bottom surface of said depression to said bottom surface of said second layer , said through hole thereby exposing a top surface of said first layer and being defined by a second inner periphery having a second inner diameter substantially smaller than said first inner diameter ; a ring-shaped wall member fitted in said depression so as to form an intimate contact with said first inner peripheral wall of said depression , said ring-shaped wall member being thereby defined by a third inner peripheral wall having a third inner diameter substantially identical to said second inner diameter of said through hole , said third layer being formed of an inorganic insulating material that shows a resistance to a dry etch (multiple etch stop insulation layer, multiple etch, second etch, second etch stop layer, second etch stop layers) ing process with respect to said material forming said second layer , said ring-shaped wall member being formed of an inorganic material that shows a selectivity to a dry etching process with respect to said material forming said second layer . US5726499A CLAIM 17 . A semiconductor integrated circuit as claimed in claim 16 , wherein said semiconductor integrated circuit further comprises an multilayer interconnection structure , said multilayer interconnection structure comprising , in each of said semiconductor devices : an interconnection pattern provided on said third layer in electric connection with said electrode ; a fourth layer of an insulating material provided on said third layer so as to bury said interconnection pattern underneath ; a fifth layer provided on said second layer ; a second depression provided on said fourth and fifth layers so as to extend from a top surface of said fifth layer toward a bottom surface of said fourth layer , said second depression having a bottom surface above said bottom surface of said fourth layer and below a bottom surface of said fifth layer , said second depression being defined by a first inner peripheral wall having a first inner diameter and extending from said top surface of said fifth layer to said bottom surface of said second depression ; a second through hole provided on said bottom surface of said second depression generally at a center thereof , such that said second through hole extends from said bottom surface of said second depression to said bottom surface of said fourth layer , said through hole thereby exposing a top surface of said interconnection pattern and being defined by a second inner periphery having a second inner diameter substantially smaller than said first inner diameter of said second depression ; a second ring-shaped wall member fitted in said second depression so as to form an intimate contact with said first inner peripheral wall of said second depression , said second ring-shaped wall member being thereby defined by a third inner peripheral wall having a third inner diameter substantially identical to said second inner diameter of said second through hole ; and an upper electrode (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) filling said second ring-shaped wall member and said second through hole in an intimate contact with said interconnection pattern ; said fifth layer being formed of an inorganic insulating material that shows a selectivity to a dry etching process with respect to said material forming said fourth layer , said second ring-shaped wall member being formed of an inorganic material that shows a selectivity to a dry etching process with respect to said material forming said second layer . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | JPH09191084A Filed: 1996-01-10 Issued: 1997-07-22 半導体装置及びその製造方法 (Original Assignee) Nec Corp; 日本電気株式会社 Hidemitsu Mori, 秀光 森 |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (製造方法) of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation (の絶縁) between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
JPH09191084A CLAIM 1 【請求項１】 素子が形成された半導体基板と、この半 導体基板上に形成された絶縁膜と、この絶縁 (electrical insulation) 膜上に形成 されてこの絶縁膜とエッチング選択性のある第１の層間 絶縁膜と、前記絶縁膜および第１の層間絶縁膜に開設さ れて前記素子に電気接続される第１の開孔部と、この第 １の開孔部内に形成される第１の埋め込み導電層と、前 記第１の埋め込み導電層の一部の上に形成される第１の 配線と、前記第１の配線及び第１の層間絶縁膜上に形成 される第２の層間絶縁膜と、前記第１の埋め込み導電層 の他の一部上の前記第２の層間絶縁膜に形成される第２ の開孔部と、この第２の開孔部内に形成される第２の配 線またはこれに接続される第２の埋め込み導電層とを備 え、前記第１の開孔部は、前記絶縁膜に開設された小径 の下部開孔部と前記第１の層間絶縁膜に開設された大径 の上部開孔部とで構成され、かつ第１の埋め込み導電層 は第１の層間絶縁膜の表面上には突出されていないこと を特徴とする半導体装置。 JPH09191084A CLAIM 5 【請求項５】 素子が形成された半導体基板にエッチン グストッパ絶縁膜と第１の層間絶縁膜を形成する工程 と、前記第１の層間絶縁膜に上部開孔部を開設する工程 と、前記上部開孔部の内面に第１のサイドウォール導電 層を形成する工程と、前記第１のサイドウォール導電層 をマスクとして前記エッチングストッパ絶縁膜に前記素 子に達するまでの下部開孔部を開設する工程と、前記上 部および下部の各開孔部で構成される第１の開孔部内に 導電材を埋め込んで第１の埋め込み導電層を形成する工 程と、前記第１の埋め込み導電層の一部の上側に第１の 配線を形成する工程と、全面に第２の層間絶縁膜を形成 する工程と、前記第１の埋め込み導電層の他の一部上の 前記第２の層間絶縁膜に開孔部を開設する工程と、この 第２の開孔部に第２の配線またはこれに接続される第２ の埋め込み導電層を形成する工程を含むことを特徴とす る半導体装置の製造方法 (metal layer coupling area) 。 |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer protects removal of a substrate material (ウォール) by an etch process . |
JPH09191084A CLAIM 3 【請求項３】 上部開孔部の内面には、その内径が下部 開孔部の内径に等しいサイドウォール (substrate material) 導電層が形成され てなる請求項１または２の半導体装置。 |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area of said contact region permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area (製造方法) of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
JPH09191084A CLAIM 5 【請求項５】 素子が形成された半導体基板にエッチン グストッパ絶縁膜と第１の層間絶縁膜を形成する工程 と、前記第１の層間絶縁膜に上部開孔部を開設する工程 と、前記上部開孔部の内面に第１のサイドウォール導電 層を形成する工程と、前記第１のサイドウォール導電層 をマスクとして前記エッチングストッパ絶縁膜に前記素 子に達するまでの下部開孔部を開設する工程と、前記上 部および下部の各開孔部で構成される第１の開孔部内に 導電材を埋め込んで第１の埋め込み導電層を形成する工 程と、前記第１の埋め込み導電層の一部の上側に第１の 配線を形成する工程と、全面に第２の層間絶縁膜を形成 する工程と、前記第１の埋め込み導電層の他の一部上の 前記第２の層間絶縁膜に開孔部を開設する工程と、この 第２の開孔部に第２の配線またはこれに接続される第２ の埋め込み導電層を形成する工程を含むことを特徴とす る半導体装置の製造方法 (metal layer coupling area) 。 |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (製造方法) of said contact region . |
JPH09191084A CLAIM 5 【請求項５】 素子が形成された半導体基板にエッチン グストッパ絶縁膜と第１の層間絶縁膜を形成する工程 と、前記第１の層間絶縁膜に上部開孔部を開設する工程 と、前記上部開孔部の内面に第１のサイドウォール導電 層を形成する工程と、前記第１のサイドウォール導電層 をマスクとして前記エッチングストッパ絶縁膜に前記素 子に達するまでの下部開孔部を開設する工程と、前記上 部および下部の各開孔部で構成される第１の開孔部内に 導電材を埋め込んで第１の埋め込み導電層を形成する工 程と、前記第１の埋め込み導電層の一部の上側に第１の 配線を形成する工程と、全面に第２の層間絶縁膜を形成 する工程と、前記第１の埋め込み導電層の他の一部上の 前記第２の層間絶縁膜に開孔部を開設する工程と、この 第２の開孔部に第２の配線またはこれに接続される第２ の埋め込み導電層を形成する工程を含むことを特徴とす る半導体装置の製造方法 (metal layer coupling area) 。 |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5663097A Filed: 1994-09-28 Issued: 1997-09-02 Method of fabricating a semiconductor device having an insulating side wall (Original Assignee) Canon Inc (Current Assignee) Canon Inc Masaru Sakamoto, Kei Fujita |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer (bottom wall) over said first etch stop layer ; a second etch stop layer (insulating film) over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5663097A CLAIM 1 . A method of producing a semiconductor device including a bipolar transistor , comprising the steps of : (a) forming a semiconductor layer of a first conductivity type for formulation into a base region on a substrate ; (b) providing an insulating film (second etch stop layer, second interlevel dielectric layer) of a width W1 on the semiconductor layer ; (c) providing a conductive layer , for formulating into a base electrode , so that the conductive layer covers the insulating film on the semiconductor layer and contacts the semiconductor layer ; (d) providing a nitride layer on the conductive layer ; (e) removing partially the conductive layer and the nitride layer , for forming an opening having a width W2 , which is smaller than the width W1 of the insulating film ; (f) introducing a dopant into the opening for forming a semiconductor layer of a second conductivity type , for formulation into a emitter , within the semiconductor layer ; (g) after said step (f) , performing an oxidization for forming an oxide at a side wall and at a bottom wall (first sub interlevel dielectric layer) of the opening ; (h) etching for removing the oxide and the insulating film at the bottom of the opening , with the oxide remaining at the side wall ; and (i) burying a conductor within the opening for forming an emitter electrode for contact to the semiconductor layer . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric layer (bottom wall) insulates said contact region . |
US5663097A CLAIM 1 . A method of producing a semiconductor device including a bipolar transistor , comprising the steps of : (a) forming a semiconductor layer of a first conductivity type for formulation into a base region on a substrate ; (b) providing an insulating film of a width W1 on the semiconductor layer ; (c) providing a conductive layer , for formulating into a base electrode , so that the conductive layer covers the insulating film on the semiconductor layer and contacts the semiconductor layer ; (d) providing a nitride layer on the conductive layer ; (e) removing partially the conductive layer and the nitride layer , for forming an opening having a width W2 , which is smaller than the width W1 of the insulating film ; (f) introducing a dopant into the opening for forming a semiconductor layer of a second conductivity type , for formulation into a emitter , within the semiconductor layer ; (g) after said step (f) , performing an oxidization for forming an oxide at a side wall and at a bottom wall (first sub interlevel dielectric layer) of the opening ; (h) etching for removing the oxide and the insulating film at the bottom of the opening , with the oxide remaining at the side wall ; and (i) burying a conductor within the opening for forming an emitter electrode for contact to the semiconductor layer . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch stop layer (insulating film) protects lower layers during an etching process . |
US5663097A CLAIM 1 . A method of producing a semiconductor device including a bipolar transistor , comprising the steps of : (a) forming a semiconductor layer of a first conductivity type for formulation into a base region on a substrate ; (b) providing an insulating film (second etch stop layer, second interlevel dielectric layer) of a width W1 on the semiconductor layer ; (c) providing a conductive layer , for formulating into a base electrode , so that the conductive layer covers the insulating film on the semiconductor layer and contacts the semiconductor layer ; (d) providing a nitride layer on the conductive layer ; (e) removing partially the conductive layer and the nitride layer , for forming an opening having a width W2 , which is smaller than the width W1 of the insulating film ; (f) introducing a dopant into the opening for forming a semiconductor layer of a second conductivity type , for formulation into a emitter , within the semiconductor layer ; (g) after said step (f) , performing an oxidization for forming an oxide at a side wall and at a bottom wall of the opening ; (h) etching for removing the oxide and the insulating film at the bottom of the opening , with the oxide remaining at the side wall ; and (i) burying a conductor within the opening for forming an emitter electrode for contact to the semiconductor layer . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer (bottom wall) is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer (insulating film) is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5663097A CLAIM 1 . A method of producing a semiconductor device including a bipolar transistor , comprising the steps of : (a) forming a semiconductor layer of a first conductivity type for formulation into a base region on a substrate ; (b) providing an insulating film (second etch stop layer, second interlevel dielectric layer) of a width W1 on the semiconductor layer ; (c) providing a conductive layer , for formulating into a base electrode , so that the conductive layer covers the insulating film on the semiconductor layer and contacts the semiconductor layer ; (d) providing a nitride layer on the conductive layer ; (e) removing partially the conductive layer and the nitride layer , for forming an opening having a width W2 , which is smaller than the width W1 of the insulating film ; (f) introducing a dopant into the opening for forming a semiconductor layer of a second conductivity type , for formulation into a emitter , within the semiconductor layer ; (g) after said step (f) , performing an oxidization for forming an oxide at a side wall and at a bottom wall (first sub interlevel dielectric layer) of the opening ; (h) etching for removing the oxide and the insulating film at the bottom of the opening , with the oxide remaining at the side wall ; and (i) burying a conductor within the opening for forming an emitter electrode for contact to the semiconductor layer . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric layer (bottom wall) for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5663097A CLAIM 1 . A method of producing a semiconductor device including a bipolar transistor , comprising the steps of : (a) forming a semiconductor layer of a first conductivity type for formulation into a base region on a substrate ; (b) providing an insulating film of a width W1 on the semiconductor layer ; (c) providing a conductive layer , for formulating into a base electrode , so that the conductive layer covers the insulating film on the semiconductor layer and contacts the semiconductor layer ; (d) providing a nitride layer on the conductive layer ; (e) removing partially the conductive layer and the nitride layer , for forming an opening having a width W2 , which is smaller than the width W1 of the insulating film ; (f) introducing a dopant into the opening for forming a semiconductor layer of a second conductivity type , for formulation into a emitter , within the semiconductor layer ; (g) after said step (f) , performing an oxidization for forming an oxide at a side wall and at a bottom wall (first sub interlevel dielectric layer) of the opening ; (h) etching for removing the oxide and the insulating film at the bottom of the opening , with the oxide remaining at the side wall ; and (i) burying a conductor within the opening for forming an emitter electrode for contact to the semiconductor layer . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer (insulating film) wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer (bottom wall) and said second etch stop layer formed under a second interlevel dielectric layer (insulating film) , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US5663097A CLAIM 1 . A method of producing a semiconductor device including a bipolar transistor , comprising the steps of : (a) forming a semiconductor layer of a first conductivity type for formulation into a base region on a substrate ; (b) providing an insulating film (second etch stop layer, second interlevel dielectric layer) of a width W1 on the semiconductor layer ; (c) providing a conductive layer , for formulating into a base electrode , so that the conductive layer covers the insulating film on the semiconductor layer and contacts the semiconductor layer ; (d) providing a nitride layer on the conductive layer ; (e) removing partially the conductive layer and the nitride layer , for forming an opening having a width W2 , which is smaller than the width W1 of the insulating film ; (f) introducing a dopant into the opening for forming a semiconductor layer of a second conductivity type , for formulation into a emitter , within the semiconductor layer ; (g) after said step (f) , performing an oxidization for forming an oxide at a side wall and at a bottom wall (first sub interlevel dielectric layer) of the opening ; (h) etching for removing the oxide and the insulating film at the bottom of the opening , with the oxide remaining at the side wall ; and (i) burying a conductor within the opening for forming an emitter electrode for contact to the semiconductor layer . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer (bottom wall) is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer (insulating film) is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5663097A CLAIM 1 . A method of producing a semiconductor device including a bipolar transistor , comprising the steps of : (a) forming a semiconductor layer of a first conductivity type for formulation into a base region on a substrate ; (b) providing an insulating film (second etch stop layer, second interlevel dielectric layer) of a width W1 on the semiconductor layer ; (c) providing a conductive layer , for formulating into a base electrode , so that the conductive layer covers the insulating film on the semiconductor layer and contacts the semiconductor layer ; (d) providing a nitride layer on the conductive layer ; (e) removing partially the conductive layer and the nitride layer , for forming an opening having a width W2 , which is smaller than the width W1 of the insulating film ; (f) introducing a dopant into the opening for forming a semiconductor layer of a second conductivity type , for formulation into a emitter , within the semiconductor layer ; (g) after said step (f) , performing an oxidization for forming an oxide at a side wall and at a bottom wall (first sub interlevel dielectric layer) of the opening ; (h) etching for removing the oxide and the insulating film at the bottom of the opening , with the oxide remaining at the side wall ; and (i) burying a conductor within the opening for forming an emitter electrode for contact to the semiconductor layer . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5317193A Filed: 1993-03-11 Issued: 1994-05-31 Contact via for semiconductor device (Original Assignee) Mitsubishi Electric Corp (Current Assignee) Mitsubishi Electric Corp Shinya Watanabe |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region (second contact) coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (upper electrode) layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5317193A CLAIM 1 . A semiconductor device comprising : an interlayer insulating film formed between conductive layers , a first contact hole formed penetrating said interlayer insulating film for electrically connecting the conductive layers , and a second contact (contact region) hole of a depth greater than that of said first contact hole , formed penetrating said interlayer insulating film for electrically connecting the conductive layers , wherein said second contact hole is formed to have a diameter smaller than that of said first contact hole and an inclining angle of an inner circumferential wall of said first contact hole is greater than that of said second contact hole . US5317193A CLAIM 5 . A semiconductor device comprising : a first interlayer insulating film formed expanding over a first region on a semiconductor substrate and on a second region higher than the first region from the surface of said semiconductor substrate and having a first dent of a predetermined diameter and depth formed in said second region , a conductive interconnection layer formed on said first interlayer insulating film including an entire surface (first sub interlevel dielectric layer) of said first dent and having a second dent formed in an area of said conductive interconnection layer covering said first dent , and a second interlayer insulating film formed on said conductive interconnection layer , wherein a contact hole having a diameter smaller than that of said second dent is formed in a portion of said second interlayer insulating film covering the bottom of said second dent . US5317193A CLAIM 7 . The semiconductor device according to claim 6 , wherein said conductive interconnection layer forms an upper electrode (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) of a capacitor of a memory cell of a DRAM . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (upper electrode) layer insulates said contact region (second contact) . |
US5317193A CLAIM 1 . A semiconductor device comprising : an interlayer insulating film formed between conductive layers , a first contact hole formed penetrating said interlayer insulating film for electrically connecting the conductive layers , and a second contact (contact region) hole of a depth greater than that of said first contact hole , formed penetrating said interlayer insulating film for electrically connecting the conductive layers , wherein said second contact hole is formed to have a diameter smaller than that of said first contact hole and an inclining angle of an inner circumferential wall of said first contact hole is greater than that of said second contact hole . US5317193A CLAIM 5 . A semiconductor device comprising : a first interlayer insulating film formed expanding over a first region on a semiconductor substrate and on a second region higher than the first region from the surface of said semiconductor substrate and having a first dent of a predetermined diameter and depth formed in said second region , a conductive interconnection layer formed on said first interlayer insulating film including an entire surface (first sub interlevel dielectric layer) of said first dent and having a second dent formed in an area of said conductive interconnection layer covering said first dent , and a second interlayer insulating film formed on said conductive interconnection layer , wherein a contact hole having a diameter smaller than that of said second dent is formed in a portion of said second interlayer insulating film covering the bottom of said second dent . US5317193A CLAIM 7 . The semiconductor device according to claim 6 , wherein said conductive interconnection layer forms an upper electrode (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) of a capacitor of a memory cell of a DRAM . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch stop layer protects lower layers during an etching process (alloy layer) . |
US5317193A CLAIM 2 . The semiconductor device according to claim 1 , wherein a conductive interconnection layered of a barrier metal layer and an aluminum alloy layer (etching process) is buried in said first contact hole and in said second contact hole . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (upper electrode) layer insulates said contact region (second contact) . |
US5317193A CLAIM 1 . A semiconductor device comprising : an interlayer insulating film formed between conductive layers , a first contact hole formed penetrating said interlayer insulating film for electrically connecting the conductive layers , and a second contact (contact region) hole of a depth greater than that of said first contact hole , formed penetrating said interlayer insulating film for electrically connecting the conductive layers , wherein said second contact hole is formed to have a diameter smaller than that of said first contact hole and an inclining angle of an inner circumferential wall of said first contact hole is greater than that of said second contact hole . US5317193A CLAIM 7 . The semiconductor device according to claim 6 , wherein said conductive interconnection layer forms an upper electrode (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) of a capacitor of a memory cell of a DRAM . |
| US7977797B2 CLAIM 6 . An integrated circuit of claim 1 wherein said spacer region insulates said contact region (second contact) . |
US5317193A CLAIM 1 . A semiconductor device comprising : an interlayer insulating film formed between conductive layers , a first contact hole formed penetrating said interlayer insulating film for electrically connecting the conductive layers , and a second contact (contact region) hole of a depth greater than that of said first contact hole , formed penetrating said interlayer insulating film for electrically connecting the conductive layers , wherein said second contact hole is formed to have a diameter smaller than that of said first contact hole and an inclining angle of an inner circumferential wall of said first contact hole is greater than that of said second contact hole . |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area of said contact region (second contact) permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
US5317193A CLAIM 1 . A semiconductor device comprising : an interlayer insulating film formed between conductive layers , a first contact hole formed penetrating said interlayer insulating film for electrically connecting the conductive layers , and a second contact (contact region) hole of a depth greater than that of said first contact hole , formed penetrating said interlayer insulating film for electrically connecting the conductive layers , wherein said second contact hole is formed to have a diameter smaller than that of said first contact hole and an inclining angle of an inner circumferential wall of said first contact hole is greater than that of said second contact hole . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (upper electrode) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5317193A CLAIM 5 . A semiconductor device comprising : a first interlayer insulating film formed expanding over a first region on a semiconductor substrate and on a second region higher than the first region from the surface of said semiconductor substrate and having a first dent of a predetermined diameter and depth formed in said second region , a conductive interconnection layer formed on said first interlayer insulating film including an entire surface (first sub interlevel dielectric layer) of said first dent and having a second dent formed in an area of said conductive interconnection layer covering said first dent , and a second interlayer insulating film formed on said conductive interconnection layer , wherein a contact hole having a diameter smaller than that of said second dent is formed in a portion of said second interlayer insulating film covering the bottom of said second dent . US5317193A CLAIM 7 . The semiconductor device according to claim 6 , wherein said conductive interconnection layer forms an upper electrode (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) of a capacitor of a memory cell of a DRAM . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric (upper electrode) layer for said contact region (second contact) is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5317193A CLAIM 1 . A semiconductor device comprising : an interlayer insulating film formed between conductive layers , a first contact hole formed penetrating said interlayer insulating film for electrically connecting the conductive layers , and a second contact (contact region) hole of a depth greater than that of said first contact hole , formed penetrating said interlayer insulating film for electrically connecting the conductive layers , wherein said second contact hole is formed to have a diameter smaller than that of said first contact hole and an inclining angle of an inner circumferential wall of said first contact hole is greater than that of said second contact hole . US5317193A CLAIM 5 . A semiconductor device comprising : a first interlayer insulating film formed expanding over a first region on a semiconductor substrate and on a second region higher than the first region from the surface of said semiconductor substrate and having a first dent of a predetermined diameter and depth formed in said second region , a conductive interconnection layer formed on said first interlayer insulating film including an entire surface (first sub interlevel dielectric layer) of said first dent and having a second dent formed in an area of said conductive interconnection layer covering said first dent , and a second interlayer insulating film formed on said conductive interconnection layer , wherein a contact hole having a diameter smaller than that of said second dent is formed in a portion of said second interlayer insulating film covering the bottom of said second dent . US5317193A CLAIM 7 . The semiconductor device according to claim 6 , wherein said conductive interconnection layer forms an upper electrode (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) of a capacitor of a memory cell of a DRAM . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region (second contact) and under a first sub interlevel dielectric (upper electrode) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US5317193A CLAIM 1 . A semiconductor device comprising : an interlayer insulating film formed between conductive layers , a first contact hole formed penetrating said interlayer insulating film for electrically connecting the conductive layers , and a second contact (contact region) hole of a depth greater than that of said first contact hole , formed penetrating said interlayer insulating film for electrically connecting the conductive layers , wherein said second contact hole is formed to have a diameter smaller than that of said first contact hole and an inclining angle of an inner circumferential wall of said first contact hole is greater than that of said second contact hole . US5317193A CLAIM 5 . A semiconductor device comprising : a first interlayer insulating film formed expanding over a first region on a semiconductor substrate and on a second region higher than the first region from the surface of said semiconductor substrate and having a first dent of a predetermined diameter and depth formed in said second region , a conductive interconnection layer formed on said first interlayer insulating film including an entire surface (first sub interlevel dielectric layer) of said first dent and having a second dent formed in an area of said conductive interconnection layer covering said first dent , and a second interlayer insulating film formed on said conductive interconnection layer , wherein a contact hole having a diameter smaller than that of said second dent is formed in a portion of said second interlayer insulating film covering the bottom of said second dent . US5317193A CLAIM 7 . The semiconductor device according to claim 6 , wherein said conductive interconnection layer forms an upper electrode (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) of a capacitor of a memory cell of a DRAM . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (upper electrode) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5317193A CLAIM 5 . A semiconductor device comprising : a first interlayer insulating film formed expanding over a first region on a semiconductor substrate and on a second region higher than the first region from the surface of said semiconductor substrate and having a first dent of a predetermined diameter and depth formed in said second region , a conductive interconnection layer formed on said first interlayer insulating film including an entire surface (first sub interlevel dielectric layer) of said first dent and having a second dent formed in an area of said conductive interconnection layer covering said first dent , and a second interlayer insulating film formed on said conductive interconnection layer , wherein a contact hole having a diameter smaller than that of said second dent is formed in a portion of said second interlayer insulating film covering the bottom of said second dent . US5317193A CLAIM 7 . The semiconductor device according to claim 6 , wherein said conductive interconnection layer forms an upper electrode (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) of a capacitor of a memory cell of a DRAM . |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region (second contact) is a first range of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5317193A CLAIM 1 . A semiconductor device comprising : an interlayer insulating film formed between conductive layers , a first contact hole formed penetrating said interlayer insulating film for electrically connecting the conductive layers , and a second contact (contact region) hole of a depth greater than that of said first contact hole , formed penetrating said interlayer insulating film for electrically connecting the conductive layers , wherein said second contact hole is formed to have a diameter smaller than that of said first contact hole and an inclining angle of an inner circumferential wall of said first contact hole is greater than that of said second contact hole . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | JPH05315457A Filed: 1992-05-07 Issued: 1993-11-26 半導体装置およびその製造方法 (Original Assignee) Mitsubishi Electric Corp; 三菱電機株式会社 Shinya Watabe, 真也 渡部 |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area (前記層) of said contact region is smaller than a metal layer coupling area (製造方法) of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer (ドライエッチング速度) over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
JPH05315457A CLAIM 1 【請求項１】 導電層間に形成された層間絶縁膜と、 この層間絶縁膜を貫通して形成され、導電層間を電気的 に接続するための、第１のコンタクトホールと、 前記層 (substrate coupling area) 間絶縁膜を貫通して形成され、導電層間を電気的 に接続するための、前記第１のコンタクトホールよりも 深さの深い第２のコンタクトホールとを備え、 前記第２のコンタクトホールは、前記第１のコンタクト ホールよりも径が小さくなるように形成された半導体装 置。 JPH05315457A CLAIM 3 【請求項３】 層間絶縁膜に、互いに開口深さの異なる 複数のコンタクトホールをドライエッチングによって形 成する工程において、 予め求めたコンタクトホール径とドライエッチング速度 (first sub interlevel dielectric layer) 比との相関関係に基づいて、前記複数のコンタクトホー ルの開口径を、各々の前記コンタクトホールの開口深さ に応じて決定することにより、前記コンタクトホールの ドライエッチング速度を制御する半導体装置の製造方 法。 JPH05315457A CLAIM 4 【請求項４】 半導体基板上に第１の層間絶縁膜を形成 する工程と、 前記第１の層間絶縁膜の表面の所定位置に、所定の径と 深さを有する窪みを形成する工程と、 前記第１の層間絶縁膜の表面および前記窪みの内表面に 沿って、第１の導電配線層を形成する工程と、 前記第１の導電配線層上に第２の層間絶縁膜を形成する 工程と、 前記第２の層間絶縁膜に、前記窪み上の領域において、 前記第１の導電配線層の表面に至るコンタクトホールを 形成する工程と、 前記第２の層間絶縁膜の表面および前記コンタクトホー ル内に、第２の導電配線層を形成する工程とを備えた半 導体装置の製造方法 (metal layer coupling area) 。 |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric layer (ドライエッチング速度) insulates said contact region . |
JPH05315457A CLAIM 3 【請求項３】 層間絶縁膜に、互いに開口深さの異なる 複数のコンタクトホールをドライエッチングによって形 成する工程において、 予め求めたコンタクトホール径とドライエッチング速度 (first sub interlevel dielectric layer) 比との相関関係に基づいて、前記複数のコンタクトホー ルの開口径を、各々の前記コンタクトホールの開口深さ に応じて決定することにより、前記コンタクトホールの ドライエッチング速度を制御する半導体装置の製造方 法。 |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area (前記層) of said contact region permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area (製造方法) of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
JPH05315457A CLAIM 1 【請求項１】 導電層間に形成された層間絶縁膜と、 この層間絶縁膜を貫通して形成され、導電層間を電気的 に接続するための、第１のコンタクトホールと、 前記層 (substrate coupling area) 間絶縁膜を貫通して形成され、導電層間を電気的 に接続するための、前記第１のコンタクトホールよりも 深さの深い第２のコンタクトホールとを備え、 前記第２のコンタクトホールは、前記第１のコンタクト ホールよりも径が小さくなるように形成された半導体装 置。 JPH05315457A CLAIM 4 【請求項４】 半導体基板上に第１の層間絶縁膜を形成 する工程と、 前記第１の層間絶縁膜の表面の所定位置に、所定の径と 深さを有する窪みを形成する工程と、 前記第１の層間絶縁膜の表面および前記窪みの内表面に 沿って、第１の導電配線層を形成する工程と、 前記第１の導電配線層上に第２の層間絶縁膜を形成する 工程と、 前記第２の層間絶縁膜に、前記窪み上の領域において、 前記第１の導電配線層の表面に至るコンタクトホールを 形成する工程と、 前記第２の層間絶縁膜の表面および前記コンタクトホー ル内に、第２の導電配線層を形成する工程とを備えた半 導体装置の製造方法 (metal layer coupling area) 。 |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Å thick , said first sub interlevel dielectric layer (ドライエッチング速度) is in a range of about 1 , 000 to 2 , 000 Å thick , said second etch stop layer is in a range of about 300 to 800 Å thick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Å thick . |
JPH05315457A CLAIM 3 【請求項３】 層間絶縁膜に、互いに開口深さの異なる 複数のコンタクトホールをドライエッチングによって形 成する工程において、 予め求めたコンタクトホール径とドライエッチング速度 (first sub interlevel dielectric layer) 比との相関関係に基づいて、前記複数のコンタクトホー ルの開口径を、各々の前記コンタクトホールの開口深さ に応じて決定することにより、前記コンタクトホールの ドライエッチング速度を制御する半導体装置の製造方 法。 |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric layer (ドライエッチング速度) for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
JPH05315457A CLAIM 3 【請求項３】 層間絶縁膜に、互いに開口深さの異なる 複数のコンタクトホールをドライエッチングによって形 成する工程において、 予め求めたコンタクトホール径とドライエッチング速度 (first sub interlevel dielectric layer) 比との相関関係に基づいて、前記複数のコンタクトホー ルの開口径を、各々の前記コンタクトホールの開口深さ に応じて決定することにより、前記コンタクトホールの ドライエッチング速度を制御する半導体装置の製造方 法。 |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer (ドライエッチング速度) and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area (前記層) of said contact region is smaller than a metal layer coupling area (製造方法) of said contact region . |
JPH05315457A CLAIM 1 【請求項１】 導電層間に形成された層間絶縁膜と、 この層間絶縁膜を貫通して形成され、導電層間を電気的 に接続するための、第１のコンタクトホールと、 前記層 (substrate coupling area) 間絶縁膜を貫通して形成され、導電層間を電気的 に接続するための、前記第１のコンタクトホールよりも 深さの深い第２のコンタクトホールとを備え、 前記第２のコンタクトホールは、前記第１のコンタクト ホールよりも径が小さくなるように形成された半導体装 置。 JPH05315457A CLAIM 3 【請求項３】 層間絶縁膜に、互いに開口深さの異なる 複数のコンタクトホールをドライエッチングによって形 成する工程において、 予め求めたコンタクトホール径とドライエッチング速度 (first sub interlevel dielectric layer) 比との相関関係に基づいて、前記複数のコンタクトホー ルの開口径を、各々の前記コンタクトホールの開口深さ に応じて決定することにより、前記コンタクトホールの ドライエッチング速度を制御する半導体装置の製造方 法。 JPH05315457A CLAIM 4 【請求項４】 半導体基板上に第１の層間絶縁膜を形成 する工程と、 前記第１の層間絶縁膜の表面の所定位置に、所定の径と 深さを有する窪みを形成する工程と、 前記第１の層間絶縁膜の表面および前記窪みの内表面に 沿って、第１の導電配線層を形成する工程と、 前記第１の導電配線層上に第２の層間絶縁膜を形成する 工程と、 前記第２の層間絶縁膜に、前記窪み上の領域において、 前記第１の導電配線層の表面に至るコンタクトホールを 形成する工程と、 前記第２の層間絶縁膜の表面および前記コンタクトホー ル内に、第２の導電配線層を形成する工程とを備えた半 導体装置の製造方法 (metal layer coupling area) 。 |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Å thick , said first sub interlevel dielectric layer (ドライエッチング速度) is in a range of about 1 , 000 to 2 , 000 Å thick , said second etch stop layer is in a range of about 300 to 800 Å thick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Å thick . |
JPH05315457A CLAIM 3 【請求項３】 層間絶縁膜に、互いに開口深さの異なる 複数のコンタクトホールをドライエッチングによって形 成する工程において、 予め求めたコンタクトホール径とドライエッチング速度 (first sub interlevel dielectric layer) 比との相関関係に基づいて、前記複数のコンタクトホー ルの開口径を、各々の前記コンタクトホールの開口深さ に応じて決定することにより、前記コンタクトホールの ドライエッチング速度を制御する半導体装置の製造方 法。 |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5116779A Filed: 1991-02-20 Issued: 1992-05-26 Process for forming semiconductor device isolation regions (Original Assignee) Sharp Corp (Current Assignee) Sharp Corp Katsuji Iguchi |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer (bottom wall) over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5116779A CLAIM 1 . A process for simultaneously forming semiconductor device isolation regions having various widths which comprises : a) forming on a silicon substrate at least a first thin silicon oxide film and a first silicon nitride film thereon , b) etching the substrate to form a trench for providing a narrow isolation region , forming a second silicon oxide film and a second silicon nitride film on the side walls and bottom wall (first sub interlevel dielectric layer) of the trench , subsequently forming a first polycrystalline silicon film on the substrate including the trench , leaving the first polycrystalline siliconfilm only on the side walls of the trench by anisotropic etching , and thereafter oxidizing the remaining first polycrystalline silicon film to form an oxide film on the side walls of the trench , further forming a second polycrystalline silicon film over the semiconductor substrate including the trench , leaving the second polycrystalline silicon film only between the oxide film portions on the side walls of the trench by anisotropic etching , c) etching the part of said first silicon nitride film which will form a wide isolation region , and d) thereafter simultaneously oxidizing both the remaining second polycrystalline silicon film and said etched part of the siliconnitride film to thereby form oxide films . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer protects removal of a substrate material (silicon oxide) by an etch process . |
US5116779A CLAIM 1 . A process for simultaneously forming semiconductor device isolation regions having various widths which comprises : a) forming on a silicon substrate at least a first thin silicon oxide (substrate material) film and a first silicon nitride film thereon , b) etching the substrate to form a trench for providing a narrow isolation region , forming a second silicon oxide film and a second silicon nitride film on the side walls and bottom wall of the trench , subsequently forming a first polycrystalline silicon film on the substrate including the trench , leaving the first polycrystalline siliconfilm only on the side walls of the trench by anisotropic etching , and thereafter oxidizing the remaining first polycrystalline silicon film to form an oxide film on the side walls of the trench , further forming a second polycrystalline silicon film over the semiconductor substrate including the trench , leaving the second polycrystalline silicon film only between the oxide film portions on the side walls of the trench by anisotropic etching , c) etching the part of said first silicon nitride film which will form a wide isolation region , and d) thereafter simultaneously oxidizing both the remaining second polycrystalline silicon film and said etched part of the siliconnitride film to thereby form oxide films . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric layer (bottom wall) insulates said contact region . |
US5116779A CLAIM 1 . A process for simultaneously forming semiconductor device isolation regions having various widths which comprises : a) forming on a silicon substrate at least a first thin silicon oxide film and a first silicon nitride film thereon , b) etching the substrate to form a trench for providing a narrow isolation region , forming a second silicon oxide film and a second silicon nitride film on the side walls and bottom wall (first sub interlevel dielectric layer) of the trench , subsequently forming a first polycrystalline silicon film on the substrate including the trench , leaving the first polycrystalline siliconfilm only on the side walls of the trench by anisotropic etching , and thereafter oxidizing the remaining first polycrystalline silicon film to form an oxide film on the side walls of the trench , further forming a second polycrystalline silicon film over the semiconductor substrate including the trench , leaving the second polycrystalline silicon film only between the oxide film portions on the side walls of the trench by anisotropic etching , c) etching the part of said first silicon nitride film which will form a wide isolation region , and d) thereafter simultaneously oxidizing both the remaining second polycrystalline silicon film and said etched part of the siliconnitride film to thereby form oxide films . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer (bottom wall) is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5116779A CLAIM 1 . A process for simultaneously forming semiconductor device isolation regions having various widths which comprises : a) forming on a silicon substrate at least a first thin silicon oxide film and a first silicon nitride film thereon , b) etching the substrate to form a trench for providing a narrow isolation region , forming a second silicon oxide film and a second silicon nitride film on the side walls and bottom wall (first sub interlevel dielectric layer) of the trench , subsequently forming a first polycrystalline silicon film on the substrate including the trench , leaving the first polycrystalline siliconfilm only on the side walls of the trench by anisotropic etching , and thereafter oxidizing the remaining first polycrystalline silicon film to form an oxide film on the side walls of the trench , further forming a second polycrystalline silicon film over the semiconductor substrate including the trench , leaving the second polycrystalline silicon film only between the oxide film portions on the side walls of the trench by anisotropic etching , c) etching the part of said first silicon nitride film which will form a wide isolation region , and d) thereafter simultaneously oxidizing both the remaining second polycrystalline silicon film and said etched part of the siliconnitride film to thereby form oxide films . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric layer (bottom wall) for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5116779A CLAIM 1 . A process for simultaneously forming semiconductor device isolation regions having various widths which comprises : a) forming on a silicon substrate at least a first thin silicon oxide film and a first silicon nitride film thereon , b) etching the substrate to form a trench for providing a narrow isolation region , forming a second silicon oxide film and a second silicon nitride film on the side walls and bottom wall (first sub interlevel dielectric layer) of the trench , subsequently forming a first polycrystalline silicon film on the substrate including the trench , leaving the first polycrystalline siliconfilm only on the side walls of the trench by anisotropic etching , and thereafter oxidizing the remaining first polycrystalline silicon film to form an oxide film on the side walls of the trench , further forming a second polycrystalline silicon film over the semiconductor substrate including the trench , leaving the second polycrystalline silicon film only between the oxide film portions on the side walls of the trench by anisotropic etching , c) etching the part of said first silicon nitride film which will form a wide isolation region , and d) thereafter simultaneously oxidizing both the remaining second polycrystalline silicon film and said etched part of the siliconnitride film to thereby form oxide films . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer (bottom wall) and said second etch stop layer formed under a second interlevel dielectric layer (minimum width) , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US5116779A CLAIM 1 . A process for simultaneously forming semiconductor device isolation regions having various widths which comprises : a) forming on a silicon substrate at least a first thin silicon oxide film and a first silicon nitride film thereon , b) etching the substrate to form a trench for providing a narrow isolation region , forming a second silicon oxide film and a second silicon nitride film on the side walls and bottom wall (first sub interlevel dielectric layer) of the trench , subsequently forming a first polycrystalline silicon film on the substrate including the trench , leaving the first polycrystalline siliconfilm only on the side walls of the trench by anisotropic etching , and thereafter oxidizing the remaining first polycrystalline silicon film to form an oxide film on the side walls of the trench , further forming a second polycrystalline silicon film over the semiconductor substrate including the trench , leaving the second polycrystalline silicon film only between the oxide film portions on the side walls of the trench by anisotropic etching , c) etching the part of said first silicon nitride film which will form a wide isolation region , and d) thereafter simultaneously oxidizing both the remaining second polycrystalline silicon film and said etched part of the siliconnitride film to thereby form oxide films . US5116779A CLAIM 5 . A process of claim 1 in which the thickness of the first polycrystalline silicon film is about one-fourth of a minimum width (second interlevel dielectric layer) of the trench . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer (bottom wall) is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5116779A CLAIM 1 . A process for simultaneously forming semiconductor device isolation regions having various widths which comprises : a) forming on a silicon substrate at least a first thin silicon oxide film and a first silicon nitride film thereon , b) etching the substrate to form a trench for providing a narrow isolation region , forming a second silicon oxide film and a second silicon nitride film on the side walls and bottom wall (first sub interlevel dielectric layer) of the trench , subsequently forming a first polycrystalline silicon film on the substrate including the trench , leaving the first polycrystalline siliconfilm only on the side walls of the trench by anisotropic etching , and thereafter oxidizing the remaining first polycrystalline silicon film to form an oxide film on the side walls of the trench , further forming a second polycrystalline silicon film over the semiconductor substrate including the trench , leaving the second polycrystalline silicon film only between the oxide film portions on the side walls of the trench by anisotropic etching , c) etching the part of said first silicon nitride film which will form a wide isolation region , and d) thereafter simultaneously oxidizing both the remaining second polycrystalline silicon film and said etched part of the siliconnitride film to thereby form oxide films . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US20040161923A1 Filed: 2004-02-13 Issued: 2004-08-19 Method for forming wire line by damascene process using hard mask formed from contacts (Original Assignee) Samsung Electronics Co Ltd (Current Assignee) Samsung Electronics Co Ltd In-deog Bae, Chang-Iln Kong, Jeong-sic Jeon, Kyeong-koo Chi |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region (conducting layer) such that a substrate coupling area (second conductive layer) of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US20040161923A1 CLAIM 10 . The method of claim 1 , wherein the step of forming a bit line comprises : forming a second conductive layer (substrate coupling area) of a material different from that of the first conductive layer over the trench ; and etching the second conductive layer selectively so that a surface of the second conductive layer is lower than an entrance of the trench . US20040161923A1 CLAIM 24 . The method of claim 23 , wherein the step of forming a bit line comprises : forming a second conductive layer of a material different from that of the first conducting layer (spacer region) over the trench ; and etching the second conductive layer selectively so that a surface of the second conductive layer is lower than an entrance of the trench |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer protects removal of a substrate material (silicon oxide) by an etch process (etch process) . |
US20040161923A1 CLAIM 4 . The method of claim 3 , wherein in order to obtain the etch selectivity , the first conductive layer is formed of polysilicon , and the first insulating layer is formed of silicon oxide (substrate material) . US20040161923A1 CLAIM 13 . The method of claim 11 , wherein the contact hole is formed by a taper etch process (etch process) so as to extend a width of the barrier wall . |
| US7977797B2 CLAIM 6 . An integrated circuit of claim 1 wherein said spacer region (conducting layer) insulates said contact region . |
US20040161923A1 CLAIM 24 . The method of claim 23 , wherein the step of forming a bit line comprises : forming a second conductive layer of a material different from that of the first conducting layer (spacer region) over the trench ; and etching the second conductive layer selectively so that a surface of the second conductive layer is lower than an entrance of the trench |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area (second conductive layer) of said contact region permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
US20040161923A1 CLAIM 10 . The method of claim 1 , wherein the step of forming a bit line comprises : forming a second conductive layer (substrate coupling area) of a material different from that of the first conductive layer over the trench ; and etching the second conductive layer selectively so that a surface of the second conductive layer is lower than an entrance of the trench . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US20040161923A1 CLAIM 1 . A method for forming a wire line by a damascene process , the method comprising : forming a first insulating layer on a semiconductor substrate ; etching the first insulating layer to form a contact hole ; forming a first conductive layer over the first insulating layer that fills the contact hole ; patterning the first conductive layer ; forming a storage node contact that fills the contact hole and is electrically connected to the semiconductor substrate ; forming a hard mask over the storage node contact ; etching the first insulating layer using the hard mask as an etch mask to form a trench in the first insulating layer ; forming a bit line that is electrically connected to the semiconductor substrate in the trench ; forming a second insulating layer that covers the bit line ; planarizing the second insulating layer and the hard mask ; and forming (anti reflective coating) a storage node on the storage node contact . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area (second conductive layer) of said contact region is smaller than a metal layer coupling area of said contact region . |
US20040161923A1 CLAIM 10 . The method of claim 1 , wherein the step of forming a bit line comprises : forming a second conductive layer (substrate coupling area) of a material different from that of the first conductive layer over the trench ; and etching the second conductive layer selectively so that a surface of the second conductive layer is lower than an entrance of the trench . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US20040161923A1 CLAIM 1 . A method for forming a wire line by a damascene process , the method comprising : forming a first insulating layer on a semiconductor substrate ; etching the first insulating layer to form a contact hole ; forming a first conductive layer over the first insulating layer that fills the contact hole ; patterning the first conductive layer ; forming a storage node contact that fills the contact hole and is electrically connected to the semiconductor substrate ; forming a hard mask over the storage node contact ; etching the first insulating layer using the hard mask as an etch mask to form a trench in the first insulating layer ; forming a bit line that is electrically connected to the semiconductor substrate in the trench ; forming a second insulating layer that covers the bit line ; planarizing the second insulating layer and the hard mask ; and forming (anti reflective coating) a storage node on the storage node contact . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US20040152256A1 Filed: 2003-12-31 Issued: 2004-08-05 Semiconductor device manufacturing method (Original Assignee) Renesas Technology Corp (Current Assignee) Renesas Electronics Corp Junji Noguchi, Toshinori Imai, Tsuyoshi Fujiwara |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer (bottom electrode) over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US20040152256A1 CLAIM 1 . A semiconductor device manufacturing method comprising the steps of : (a) preparing a semiconductor substrate ; (b) forming , on said semiconductor substrate , a first insulation film where a first interconnect with a copper-based first conductor film and a capacitor bottom electrode (second interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) are buried ; (c) forming a second insulation film on said first insulation film where said first interconnect and said bottom electrode are buried ; (d) forming a third insulation film on said second insulation film ; (e) forming a first hole by removing a selected area of said third insulation film ; (f) forming a capacitor top electrode with a second conductor film in said first hole ; (g) forming a fourth insulation film on said third insulation film where said top electrode is buried ; (h) forming a second hole and a third hole to expose said top electrode by removing a selected area of said fourth insulation film , and forming a fourth hole to expose said first interconnect by removing selected areas of said third insulation film and said second insulation film at the bottom of said second hole ; and (i) filling a copper-based third conductor film into said second hole , said third hole , and said fourth hole . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric layer (bottom electrode) insulates said contact region . |
US20040152256A1 CLAIM 1 . A semiconductor device manufacturing method comprising the steps of : (a) preparing a semiconductor substrate ; (b) forming , on said semiconductor substrate , a first insulation film where a first interconnect with a copper-based first conductor film and a capacitor bottom electrode (second interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) are buried ; (c) forming a second insulation film on said first insulation film where said first interconnect and said bottom electrode are buried ; (d) forming a third insulation film on said second insulation film ; (e) forming a first hole by removing a selected area of said third insulation film ; (f) forming a capacitor top electrode with a second conductor film in said first hole ; (g) forming a fourth insulation film on said third insulation film where said top electrode is buried ; (h) forming a second hole and a third hole to expose said top electrode by removing a selected area of said fourth insulation film , and forming a fourth hole to expose said first interconnect by removing selected areas of said third insulation film and said second insulation film at the bottom of said second hole ; and (i) filling a copper-based third conductor film into said second hole , said third hole , and said fourth hole . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer (bottom electrode) is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US20040152256A1 CLAIM 1 . A semiconductor device manufacturing method comprising the steps of : (a) preparing a semiconductor substrate ; (b) forming , on said semiconductor substrate , a first insulation film where a first interconnect with a copper-based first conductor film and a capacitor bottom electrode (second interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) are buried ; (c) forming a second insulation film on said first insulation film where said first interconnect and said bottom electrode are buried ; (d) forming a third insulation film on said second insulation film ; (e) forming a first hole by removing a selected area of said third insulation film ; (f) forming a capacitor top electrode with a second conductor film in said first hole ; (g) forming a fourth insulation film on said third insulation film where said top electrode is buried ; (h) forming a second hole and a third hole to expose said top electrode by removing a selected area of said fourth insulation film , and forming a fourth hole to expose said first interconnect by removing selected areas of said third insulation film and said second insulation film at the bottom of said second hole ; and (i) filling a copper-based third conductor film into said second hole , said third hole , and said fourth hole . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric layer (bottom electrode) for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US20040152256A1 CLAIM 1 . A semiconductor device manufacturing method comprising the steps of : (a) preparing a semiconductor substrate ; (b) forming , on said semiconductor substrate , a first insulation film where a first interconnect with a copper-based first conductor film and a capacitor bottom electrode (second interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) are buried ; (c) forming a second insulation film on said first insulation film where said first interconnect and said bottom electrode are buried ; (d) forming a third insulation film on said second insulation film ; (e) forming a first hole by removing a selected area of said third insulation film ; (f) forming a capacitor top electrode with a second conductor film in said first hole ; (g) forming a fourth insulation film on said third insulation film where said top electrode is buried ; (h) forming a second hole and a third hole to expose said top electrode by removing a selected area of said fourth insulation film , and forming a fourth hole to expose said first interconnect by removing selected areas of said third insulation film and said second insulation film at the bottom of said second hole ; and (i) filling a copper-based third conductor film into said second hole , said third hole , and said fourth hole . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US20040152256A1 CLAIM 1 . A semiconductor device manufacturing method comprising the steps of : (a) preparing a semiconductor substrate ; (b) forming , on said semiconductor substrate , a first insulation film where a first interconnect with a copper-based first conductor film and a capacitor bottom electrode are buried ; (c) forming a second insulation film on said first insulation film where said first interconnect and said bottom electrode are buried ; (d) forming a third insulation film on said second insulation film ; (e) forming a first hole by removing a selected area of said third insulation film ; (f) forming a capacitor top electrode with a second conductor film in said first hole ; (g) forming a fourth insulation film on said third insulation film where said top electrode is buried ; (h) forming a second hole and a third hole to expose said top electrode by removing a selected area of said fourth insulation film , and forming (anti reflective coating) a fourth hole to expose said first interconnect by removing selected areas of said third insulation film and said second insulation film at the bottom of said second hole ; and (i) filling a copper-based third conductor film into said second hole , said third hole , and said fourth hole . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer (bottom electrode) and said second etch stop layer formed under a second interlevel dielectric (bottom electrode) layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US20040152256A1 CLAIM 1 . A semiconductor device manufacturing method comprising the steps of : (a) preparing a semiconductor substrate ; (b) forming , on said semiconductor substrate , a first insulation film where a first interconnect with a copper-based first conductor film and a capacitor bottom electrode (second interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) are buried ; (c) forming a second insulation film on said first insulation film where said first interconnect and said bottom electrode are buried ; (d) forming a third insulation film on said second insulation film ; (e) forming a first hole by removing a selected area of said third insulation film ; (f) forming a capacitor top electrode with a second conductor film in said first hole ; (g) forming a fourth insulation film on said third insulation film where said top electrode is buried ; (h) forming a second hole and a third hole to expose said top electrode by removing a selected area of said fourth insulation film , and forming a fourth hole to expose said first interconnect by removing selected areas of said third insulation film and said second insulation film at the bottom of said second hole ; and (i) filling a copper-based third conductor film into said second hole , said third hole , and said fourth hole . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer (bottom electrode) is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US20040152256A1 CLAIM 1 . A semiconductor device manufacturing method comprising the steps of : (a) preparing a semiconductor substrate ; (b) forming , on said semiconductor substrate , a first insulation film where a first interconnect with a copper-based first conductor film and a capacitor bottom electrode (second interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) are buried ; (c) forming a second insulation film on said first insulation film where said first interconnect and said bottom electrode are buried ; (d) forming a third insulation film on said second insulation film ; (e) forming a first hole by removing a selected area of said third insulation film ; (f) forming a capacitor top electrode with a second conductor film in said first hole ; (g) forming a fourth insulation film on said third insulation film where said top electrode is buried ; (h) forming a second hole and a third hole to expose said top electrode by removing a selected area of said fourth insulation film , and forming a fourth hole to expose said first interconnect by removing selected areas of said third insulation film and said second insulation film at the bottom of said second hole ; and (i) filling a copper-based third conductor film into said second hole , said third hole , and said fourth hole . |
| US7977797B2 CLAIM 13 . An integrated circuit of claim 11 further comprising a floating gate (second insulation) . |
US20040152256A1 CLAIM 1 . A semiconductor device manufacturing method comprising the steps of : (a) preparing a semiconductor substrate ; (b) forming , on said semiconductor substrate , a first insulation film where a first interconnect with a copper-based first conductor film and a capacitor bottom electrode are buried ; (c) forming a second insulation (floating gate) film on said first insulation film where said first interconnect and said bottom electrode are buried ; (d) forming a third insulation film on said second insulation film ; (e) forming a first hole by removing a selected area of said third insulation film ; (f) forming a capacitor top electrode with a second conductor film in said first hole ; (g) forming a fourth insulation film on said third insulation film where said top electrode is buried ; (h) forming a second hole and a third hole to expose said top electrode by removing a selected area of said fourth insulation film , and forming a fourth hole to expose said first interconnect by removing selected areas of said third insulation film and said second insulation film at the bottom of said second hole ; and (i) filling a copper-based third conductor film into said second hole , said third hole , and said fourth hole . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US20040152256A1 CLAIM 1 . A semiconductor device manufacturing method comprising the steps of : (a) preparing a semiconductor substrate ; (b) forming , on said semiconductor substrate , a first insulation film where a first interconnect with a copper-based first conductor film and a capacitor bottom electrode are buried ; (c) forming a second insulation film on said first insulation film where said first interconnect and said bottom electrode are buried ; (d) forming a third insulation film on said second insulation film ; (e) forming a first hole by removing a selected area of said third insulation film ; (f) forming a capacitor top electrode with a second conductor film in said first hole ; (g) forming a fourth insulation film on said third insulation film where said top electrode is buried ; (h) forming a second hole and a third hole to expose said top electrode by removing a selected area of said fourth insulation film , and forming (anti reflective coating) a fourth hole to expose said first interconnect by removing selected areas of said third insulation film and said second insulation film at the bottom of said second hole ; and (i) filling a copper-based third conductor film into said second hole , said third hole , and said fourth hole . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | CN1519914A Filed: 2003-12-30 Issued: 2004-08-11 电容器及其制备方法 (Original Assignee) 海力士半导体有限公司 崔亨福 |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer (绝缘层上) coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer (在第一) directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer (在第一) over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
CN1519914A CLAIM 1 . 一种用于制备半导体装置的电容器的方法，包含下列步骤：在基板上形成一层间绝缘层；形成局部地露出部分基板的一储存节点接触孔，它是通过蚀刻层间绝缘层而形成；形成一储存节点接触点，使其埋入于接触孔内，而具有与该层间绝缘层表面相同的平面位准；在层间绝缘层上 (multiple etch stop insulation layer) 形成一储存节点氧化物层；形成一露出储存节点接触点的储存节点孔，它是通过蚀刻该储存节点氧化物层而形成；形成一沿着向下方向呈中空形式的支撑孔，它是通过下凹，或通过局部移除因储存节点孔露出的储存节点接触点的上部部分；以及形成一具有圆柱体结构且与该储存节点接点形成电连接的储存节点，其中将该储存节点的底部部分配置在支撑孔内，以使由此受到该支撑孔及层间绝缘层的支撑。 CN1519914A CLAIM 22 . 如权利要求21的方法，其中，用以形成多层绝缘支撑元件的步骤还包括下列步骤：形成一第一蚀刻阻挡层在该层间绝缘层上；形成一绝缘层在该第一蚀刻阻挡层上；形成一第二蚀刻阻挡层于该绝缘层上；以及形成一下切区域，它是通过选择性移除绝缘层而处在第一 (first etch stop layer, second etch stop layer) 蚀刻阻挡层与第二蚀刻阻挡层之间。 |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer (在第一) protects removal of a substrate material (层形成) by an etch process . |
CN1519914A CLAIM 8 . 一种半导体装置用电容器的制造方法，包含下列步骤：于基板上形成一层间绝缘层；形成一个局部露出部分基板的储存节点接触孔，它通过蚀刻层间绝缘层而形成；形成一储存节点接点，使其埋藏于接触孔内，并具有与层内绝缘层表面相同的平面位准；形成一具有上层和下层构的双层结构的储存节点氧化物层，其中形成层间绝缘层上的上层的蚀刻选择比高于下层的蚀刻选择比；形成一个露出储存节点接点的储存节点孔，其通过蚀刻储存节点氧化物层形成 (substrate material) ；展宽储存节点孔的宽度，且同时在该储存节点氧化物层的下层上形成一下切区域；形成一沿着向下方向呈中空的支撑孔，其是通过下凹或通过局部移除因展宽其宽度的储存节点孔而露出的储存节点接点的上部的局部部分；以及形成一具有圆柱体结构，且与该储存节点接点形成电连接的储存节点，使储存节点孔内的储存节点底部区域是受到该支撑孔及下切区域支撑。 CN1519914A CLAIM 22 . 如权利要求21的方法，其中，用以形成多层绝缘支撑元件的步骤还包括下列步骤：形成一第一蚀刻阻挡层在该层间绝缘层上；形成一绝缘层在该第一蚀刻阻挡层上；形成一第二蚀刻阻挡层于该绝缘层上；以及形成一下切区域，它是通过选择性移除绝缘层而处在第一 (first etch stop layer, second etch stop layer) 蚀刻阻挡层与第二蚀刻阻挡层之间。 |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch stop layer (在第一) protects lower layers during an etching process . |
CN1519914A CLAIM 22 . 如权利要求21的方法，其中，用以形成多层绝缘支撑元件的步骤还包括下列步骤：形成一第一蚀刻阻挡层在该层间绝缘层上；形成一绝缘层在该第一蚀刻阻挡层上；形成一第二蚀刻阻挡层于该绝缘层上；以及形成一下切区域，它是通过选择性移除绝缘层而处在第一 (first etch stop layer, second etch stop layer) 蚀刻阻挡层与第二蚀刻阻挡层之间。 |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer (在第一) is in a range of about 300 to 800 Å thick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Å thick , said second etch stop layer (在第一) is in a range of about 300 to 800 Å thick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Å thick . |
CN1519914A CLAIM 22 . 如权利要求21的方法，其中，用以形成多层绝缘支撑元件的步骤还包括下列步骤：形成一第一蚀刻阻挡层在该层间绝缘层上；形成一绝缘层在该第一蚀刻阻挡层上；形成一第二蚀刻阻挡层于该绝缘层上；以及形成一下切区域，它是通过选择性移除绝缘层而处在第一 (first etch stop layer, second etch stop layer) 蚀刻阻挡层与第二蚀刻阻挡层之间。 |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer (绝缘层上) comprising a first etch stop layer (在第一) and a second etch stop layer (在第一) wherein said first etch stop layer and said second etch stop layers (形成一绝缘层) have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom (底部区域, 的接触) , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
CN1519914A CLAIM 1 . 一种用于制备半导体装置的电容器的方法，包含下列步骤：在基板上形成一层间绝缘层；形成局部地露出部分基板的一储存节点接触孔，它是通过蚀刻层间绝缘层而形成；形成一储存节点接触点，使其埋入于接触孔内，而具有与该层间绝缘层表面相同的平面位准；在层间绝缘层上 (multiple etch stop insulation layer) 形成一储存节点氧化物层；形成一露出储存节点接触点的储存节点孔，它是通过蚀刻该储存节点氧化物层而形成；形成一沿着向下方向呈中空形式的支撑孔，它是通过下凹，或通过局部移除因储存节点孔露出的储存节点接触点的上部部分；以及形成一具有圆柱体结构且与该储存节点接点形成电连接的储存节点，其中将该储存节点的底部部分配置在支撑孔内，以使由此受到该支撑孔及层间绝缘层的支撑。 CN1519914A CLAIM 8 . 一种半导体装置用电容器的制造方法，包含下列步骤：于基板上形成一层间绝缘层；形成一个局部露出部分基板的储存节点接触孔，它通过蚀刻层间绝缘层而形成；形成一储存节点接点，使其埋藏于接触孔内，并具有与层内绝缘层表面相同的平面位准；形成一具有上层和下层构的双层结构的储存节点氧化物层，其中形成层间绝缘层上的上层的蚀刻选择比高于下层的蚀刻选择比；形成一个露出储存节点接点的储存节点孔，其通过蚀刻储存节点氧化物层形成；展宽储存节点孔的宽度，且同时在该储存节点氧化物层的下层上形成一下切区域；形成一沿着向下方向呈中空的支撑孔，其是通过下凹或通过局部移除因展宽其宽度的储存节点孔而露出的储存节点接点的上部的局部部分；以及形成一具有圆柱体结构，且与该储存节点接点形成电连接的储存节点，使储存节点孔内的储存节点底部区域 (contact bottom) 是受到该支撑孔及下切区域支撑。 CN1519914A CLAIM 16 . 一种半导体装置用电容器，是包含：一基板；一层间绝缘层，它具有一局部地露出部分基板的接触 (contact bottom) 孔并形成在该基板上；一储存节点接触点，它在接触孔的上部区域上配有支撑孔并用以局部填充部分接触孔；以及一储存节点，它连接到储存节点接点上，其中，将该储存节点的底部部分插入并固定在支撑孔中。 CN1519914A CLAIM 22 . 如权利要求21的方法，其中，用以形成多层绝缘支撑元件的步骤还包括下列步骤：形成一第一蚀刻阻挡层在该层间绝缘层上；形成一绝缘层 (second etch stop layers) 在该第一蚀刻阻挡层上；形成一第二蚀刻阻挡层于该绝缘层上；以及形成一下切区域，它是通过选择性移除绝缘层而处在第一 (first etch stop layer, second etch stop layer) 蚀刻阻挡层与第二蚀刻阻挡层之间。 |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer (在第一) is in a range of about 300 to 800 Å thick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Å thick , said second etch stop layer (在第一) is in a range of about 300 to 800 Å thick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Å thick . |
CN1519914A CLAIM 22 . 如权利要求21的方法，其中，用以形成多层绝缘支撑元件的步骤还包括下列步骤：形成一第一蚀刻阻挡层在该层间绝缘层上；形成一绝缘层在该第一蚀刻阻挡层上；形成一第二蚀刻阻挡层于该绝缘层上；以及形成一下切区域，它是通过选择性移除绝缘层而处在第一 (first etch stop layer, second etch stop layer) 蚀刻阻挡层与第二蚀刻阻挡层之间。 |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US20040155340A1 Filed: 2003-10-29 Issued: 2004-08-12 Silicon oxycarbide, growth method of silicon oxycarbide layer, semiconductor device and manufacture method for semiconductor device (Original Assignee) Fujitsu Ltd Tamotsu Owada, Shun-ichi Fukuyama, Hirofumi Watatani, Kengo Inoue, Atsuo Shimizu |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch (low rate) stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US20040155340A1 CLAIM 6 . A method of growing a silicon oxycarbide layer comprising the steps of : preparing an underlying layer ; and growing a silicon oxycarbide layer on said underlying layer by vapor deposition using , as source gas , tetramethylcyclotetrasiloxane , carbon dioxide gas and oxygen gas , a flow rate (multiple etch, etch process) of said oxygen gas being at most 3% of a flow rate of said carbon dioxide gas . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer protects removal of a substrate material (silicon oxide) by an etch process (low rate) . |
US20040155340A1 CLAIM 6 . A method of growing a silicon oxycarbide layer comprising the steps of : preparing an underlying layer ; and growing a silicon oxycarbide layer on said underlying layer by vapor deposition using , as source gas , tetramethylcyclotetrasiloxane , carbon dioxide gas and oxygen gas , a flow rate (multiple etch, etch process) of said oxygen gas being at most 3% of a flow rate of said carbon dioxide gas . US20040155340A1 CLAIM 15 . The semiconductor device according to claim 12 , further comprising a low dielectric constant insulating layer formed on said first silicon oxycarbide layer , said low dielectric constant insulating layer having a specific dielectric constant lower than a specific dielectric constant of silicon oxide (substrate material) . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch stop layer protects lower layers during an etching process (copper wiring) . |
US20040155340A1 CLAIM 12 . A semiconductor device comprising : a semiconductor substrate ; a copper wiring (etching process) formed above said semiconductor substrate ; a silicon carbide layer covering said copper wiring ; and a first silicon oxycarbide layer covering said silicon carbide layer , said first silicon oxycarbide layer containing hydrogen and having a carbon content of at least about 18 at % and a specific dielectric constant of at most about 3 . 1 . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US20040155340A1 CLAIM 27 . A method of manufacturing a semiconductor device comprising the steps of : preparing an underlying structure having a semiconductor substrate , a copper wiring formed above said semiconductor substrate and a silicon carbide layer covering said copper wiring ; making hydrophilic a surface of the silicon carbide layer of said underlying structure by using plasma of oxidizing gas which contains oxygen and has a molecular weight larger than a molecular wright of O 2 ; and forming (anti reflective coating) a low dielectric constant insulating layer on the surface of said hydrophilic silicon carbide layer , said low dielectric constant insulating layer having a specific dielectric constant lower than a specific dielectric constant of silicon oxide . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch (low rate) stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom (silicon carbide) , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US20040155340A1 CLAIM 6 . A method of growing a silicon oxycarbide layer comprising the steps of : preparing an underlying layer ; and growing a silicon oxycarbide layer on said underlying layer by vapor deposition using , as source gas , tetramethylcyclotetrasiloxane , carbon dioxide gas and oxygen gas , a flow rate (multiple etch, etch process) of said oxygen gas being at most 3% of a flow rate of said carbon dioxide gas . US20040155340A1 CLAIM 12 . A semiconductor device comprising : a semiconductor substrate ; a copper wiring formed above said semiconductor substrate ; a silicon carbide (contact bottom) layer covering said copper wiring ; and a first silicon oxycarbide layer covering said silicon carbide layer , said first silicon oxycarbide layer containing hydrogen and having a carbon content of at least about 18 at % and a specific dielectric constant of at most about 3 . 1 . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US20040155340A1 CLAIM 27 . A method of manufacturing a semiconductor device comprising the steps of : preparing an underlying structure having a semiconductor substrate , a copper wiring formed above said semiconductor substrate and a silicon carbide layer covering said copper wiring ; making hydrophilic a surface of the silicon carbide layer of said underlying structure by using plasma of oxidizing gas which contains oxygen and has a molecular weight larger than a molecular wright of O 2 ; and forming (anti reflective coating) a low dielectric constant insulating layer on the surface of said hydrophilic silicon carbide layer , said low dielectric constant insulating layer having a specific dielectric constant lower than a specific dielectric constant of silicon oxide . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US20040119164A1 Filed: 2003-08-14 Issued: 2004-06-24 Semiconductor device and its manufacturing method (Original Assignee) Toshiba Corp (Current Assignee) Toshiba Corp Nobuyuki Kurashima, Gaku Minamihaba, Dai Fukushima, Yoshikuni Tateyama, Hiroyuki Yano |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region (predetermined value, two layers) coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area (adjacent layers) of said contact region is smaller than a metal layer coupling area (adjacent layers) of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US20040119164A1 CLAIM 1 . A semiconductor device comprising : a substrate ; a first insulating film which is provided above the substrate and has a relative dielectric constant which is at most a predetermined value (contact region, contact bottom) ; a second insulating film which is provided on a surface of the first insulating film and has a relative dielectric constant greater than the predetermined value ; a wire which is provided in a recess for the wire , which is formed passing through the second insulating film and extending into the first insulating film ; and a dummy wire provided in a recess for the dummy wire , which is formed passing through the second insulating film and extending into the first insulating film , and is located in a predetermined area spaced from an area where the wire is provided . US20040119164A1 CLAIM 2 . The device according to claim 1 , wherein : at least two layers (contact region, contact bottom) of interlayer insulating films comprising the first and second insulating films are provided above the substrate ; and the dummy wires are provided in the interlayer insulating films of each layer of the second and subsequent layers , passing through the interlayer insulating films of the each layer and are continued the dummy wire provided in the next lower interlayer insulating film . US20040119164A1 CLAIM 3 . The device according to claim 1 , wherein : at least three layers of interlayer insulating films comprising the first and second insulating films are provided above the substrate ; the dummy wire is provided in the interlayer insulating film of an n-th layer (n is 1 or a greater integer) , passing through the second insulating film and extending into the first insulating film ; the dummy wire is provided in the interlayer insulating film of a predetermined layer in an (n+2) th and subsequent layers , passing through the second and first insulating films , and that part of the dummy wire which lies at the second insulating film extends along a surface of the interlayer insulating film of the predetermined layer and over the dummy wire provided in the interlayer insulating film of the n-th layer , for a longer distance than that part which lies at the first insulating film ; and at least the one dummy wire is provided in at least one interlayer insulating film which lies between the n-th layer and the predetermined layer in the (n+2) th and subsequent layers , passing through the second and first insulating films and continued the dummy wires provided in interlayer insulating films of adjacent layers (substrate coupling area, metal layer coupling area) . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer protects removal of a substrate material (plane view) by an etch process . |
US20040119164A1 CLAIM 5 . The device according to claim 1 , wherein : a pattern shape in a plane view (substrate material) of a single unit of the dummy wire is a nonlinear shape . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric layer insulates said contact region (predetermined value, two layers) . |
US20040119164A1 CLAIM 1 . A semiconductor device comprising : a substrate ; a first insulating film which is provided above the substrate and has a relative dielectric constant which is at most a predetermined value (contact region, contact bottom) ; a second insulating film which is provided on a surface of the first insulating film and has a relative dielectric constant greater than the predetermined value ; a wire which is provided in a recess for the wire , which is formed passing through the second insulating film and extending into the first insulating film ; and a dummy wire provided in a recess for the dummy wire , which is formed passing through the second insulating film and extending into the first insulating film , and is located in a predetermined area spaced from an area where the wire is provided . US20040119164A1 CLAIM 2 . The device according to claim 1 , wherein : at least two layers (contact region, contact bottom) of interlayer insulating films comprising the first and second insulating films are provided above the substrate ; and the dummy wires are provided in the interlayer insulating films of each layer of the second and subsequent layers , passing through the interlayer insulating films of the each layer and are continued the dummy wire provided in the next lower interlayer insulating film . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric layer insulates said contact region (predetermined value, two layers) . |
US20040119164A1 CLAIM 1 . A semiconductor device comprising : a substrate ; a first insulating film which is provided above the substrate and has a relative dielectric constant which is at most a predetermined value (contact region, contact bottom) ; a second insulating film which is provided on a surface of the first insulating film and has a relative dielectric constant greater than the predetermined value ; a wire which is provided in a recess for the wire , which is formed passing through the second insulating film and extending into the first insulating film ; and a dummy wire provided in a recess for the dummy wire , which is formed passing through the second insulating film and extending into the first insulating film , and is located in a predetermined area spaced from an area where the wire is provided . US20040119164A1 CLAIM 2 . The device according to claim 1 , wherein : at least two layers (contact region, contact bottom) of interlayer insulating films comprising the first and second insulating films are provided above the substrate ; and the dummy wires are provided in the interlayer insulating films of each layer of the second and subsequent layers , passing through the interlayer insulating films of the each layer and are continued the dummy wire provided in the next lower interlayer insulating film . |
| US7977797B2 CLAIM 6 . An integrated circuit of claim 1 wherein said spacer region insulates said contact region (predetermined value, two layers) . |
US20040119164A1 CLAIM 1 . A semiconductor device comprising : a substrate ; a first insulating film which is provided above the substrate and has a relative dielectric constant which is at most a predetermined value (contact region, contact bottom) ; a second insulating film which is provided on a surface of the first insulating film and has a relative dielectric constant greater than the predetermined value ; a wire which is provided in a recess for the wire , which is formed passing through the second insulating film and extending into the first insulating film ; and a dummy wire provided in a recess for the dummy wire , which is formed passing through the second insulating film and extending into the first insulating film , and is located in a predetermined area spaced from an area where the wire is provided . US20040119164A1 CLAIM 2 . The device according to claim 1 , wherein : at least two layers (contact region, contact bottom) of interlayer insulating films comprising the first and second insulating films are provided above the substrate ; and the dummy wires are provided in the interlayer insulating films of each layer of the second and subsequent layers , passing through the interlayer insulating films of the each layer and are continued the dummy wire provided in the next lower interlayer insulating film . |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area (adjacent layers) of said contact region (predetermined value, two layers) permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area (adjacent layers) of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
US20040119164A1 CLAIM 1 . A semiconductor device comprising : a substrate ; a first insulating film which is provided above the substrate and has a relative dielectric constant which is at most a predetermined value (contact region, contact bottom) ; a second insulating film which is provided on a surface of the first insulating film and has a relative dielectric constant greater than the predetermined value ; a wire which is provided in a recess for the wire , which is formed passing through the second insulating film and extending into the first insulating film ; and a dummy wire provided in a recess for the dummy wire , which is formed passing through the second insulating film and extending into the first insulating film , and is located in a predetermined area spaced from an area where the wire is provided . US20040119164A1 CLAIM 2 . The device according to claim 1 , wherein : at least two layers (contact region, contact bottom) of interlayer insulating films comprising the first and second insulating films are provided above the substrate ; and the dummy wires are provided in the interlayer insulating films of each layer of the second and subsequent layers , passing through the interlayer insulating films of the each layer and are continued the dummy wire provided in the next lower interlayer insulating film . US20040119164A1 CLAIM 3 . The device according to claim 1 , wherein : at least three layers of interlayer insulating films comprising the first and second insulating films are provided above the substrate ; the dummy wire is provided in the interlayer insulating film of an n-th layer (n is 1 or a greater integer) , passing through the second insulating film and extending into the first insulating film ; the dummy wire is provided in the interlayer insulating film of a predetermined layer in an (n+2) th and subsequent layers , passing through the second and first insulating films , and that part of the dummy wire which lies at the second insulating film extends along a surface of the interlayer insulating film of the predetermined layer and over the dummy wire provided in the interlayer insulating film of the n-th layer , for a longer distance than that part which lies at the first insulating film ; and at least the one dummy wire is provided in at least one interlayer insulating film which lies between the n-th layer and the predetermined layer in the (n+2) th and subsequent layers , passing through the second and first insulating films and continued the dummy wires provided in interlayer insulating films of adjacent layers (substrate coupling area, metal layer coupling area) . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric layer for said contact region (predetermined value, two layers) is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US20040119164A1 CLAIM 1 . A semiconductor device comprising : a substrate ; a first insulating film which is provided above the substrate and has a relative dielectric constant which is at most a predetermined value (contact region, contact bottom) ; a second insulating film which is provided on a surface of the first insulating film and has a relative dielectric constant greater than the predetermined value ; a wire which is provided in a recess for the wire , which is formed passing through the second insulating film and extending into the first insulating film ; and a dummy wire provided in a recess for the dummy wire , which is formed passing through the second insulating film and extending into the first insulating film , and is located in a predetermined area spaced from an area where the wire is provided . US20040119164A1 CLAIM 2 . The device according to claim 1 , wherein : at least two layers (contact region, contact bottom) of interlayer insulating films comprising the first and second insulating films are provided above the substrate ; and the dummy wires are provided in the interlayer insulating films of each layer of the second and subsequent layers , passing through the interlayer insulating films of the each layer and are continued the dummy wire provided in the next lower interlayer insulating film . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region (predetermined value, two layers) and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom (predetermined value, two layers) , such that a substrate coupling area (adjacent layers) of said contact region is smaller than a metal layer coupling area (adjacent layers) of said contact region . |
US20040119164A1 CLAIM 1 . A semiconductor device comprising : a substrate ; a first insulating film which is provided above the substrate and has a relative dielectric constant which is at most a predetermined value (contact region, contact bottom) ; a second insulating film which is provided on a surface of the first insulating film and has a relative dielectric constant greater than the predetermined value ; a wire which is provided in a recess for the wire , which is formed passing through the second insulating film and extending into the first insulating film ; and a dummy wire provided in a recess for the dummy wire , which is formed passing through the second insulating film and extending into the first insulating film , and is located in a predetermined area spaced from an area where the wire is provided . US20040119164A1 CLAIM 2 . The device according to claim 1 , wherein : at least two layers (contact region, contact bottom) of interlayer insulating films comprising the first and second insulating films are provided above the substrate ; and the dummy wires are provided in the interlayer insulating films of each layer of the second and subsequent layers , passing through the interlayer insulating films of the each layer and are continued the dummy wire provided in the next lower interlayer insulating film . US20040119164A1 CLAIM 3 . The device according to claim 1 , wherein : at least three layers of interlayer insulating films comprising the first and second insulating films are provided above the substrate ; the dummy wire is provided in the interlayer insulating film of an n-th layer (n is 1 or a greater integer) , passing through the second insulating film and extending into the first insulating film ; the dummy wire is provided in the interlayer insulating film of a predetermined layer in an (n+2) th and subsequent layers , passing through the second and first insulating films , and that part of the dummy wire which lies at the second insulating film extends along a surface of the interlayer insulating film of the predetermined layer and over the dummy wire provided in the interlayer insulating film of the n-th layer , for a longer distance than that part which lies at the first insulating film ; and at least the one dummy wire is provided in at least one interlayer insulating film which lies between the n-th layer and the predetermined layer in the (n+2) th and subsequent layers , passing through the second and first insulating films and continued the dummy wires provided in interlayer insulating films of adjacent layers (substrate coupling area, metal layer coupling area) . |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region (predetermined value, two layers) is a first range of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US20040119164A1 CLAIM 1 . A semiconductor device comprising : a substrate ; a first insulating film which is provided above the substrate and has a relative dielectric constant which is at most a predetermined value (contact region, contact bottom) ; a second insulating film which is provided on a surface of the first insulating film and has a relative dielectric constant greater than the predetermined value ; a wire which is provided in a recess for the wire , which is formed passing through the second insulating film and extending into the first insulating film ; and a dummy wire provided in a recess for the dummy wire , which is formed passing through the second insulating film and extending into the first insulating film , and is located in a predetermined area spaced from an area where the wire is provided . US20040119164A1 CLAIM 2 . The device according to claim 1 , wherein : at least two layers (contact region, contact bottom) of interlayer insulating films comprising the first and second insulating films are provided above the substrate ; and the dummy wires are provided in the interlayer insulating films of each layer of the second and subsequent layers , passing through the interlayer insulating films of the each layer and are continued the dummy wire provided in the next lower interlayer insulating film . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | JP2004096080A Filed: 2003-06-04 Issued: 2004-03-25 金属間絶縁膜のパターン形成方法 (Original Assignee) Samsung Electronics Co Ltd; 三星電子株式会社 Hyun Dam Jeong, Kwang Hee Lee, Kyoung-Woo Lee, Soo-Geun Lee, 李 光 煕, 李 守 根, 李 敬 雨, 鄭 鉉 潭 |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area (前記層) of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch (エッチング後) stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
JP2004096080A CLAIM 1 ａ）下部配線が形成された半導体基板上に下部エッチング阻止膜、下部絶縁膜、上部エッチング阻止膜及び上部絶縁膜を順次形成する段階と、 ｂ）前記上部絶縁膜、上部エッチング阻止膜及び下部絶縁膜をパターニングして、前記下部配線上の下部エッチング阻止膜を露出させるビアホールを形成する段階と、 ｃ）エッチング後 (first etch) にビアホールをＵＶ光で照射する段階と、 ｄ）前記ビアホールが形成された半導体基板の全面にフォトレジスト膜を形成し、パターニングする段階と、 ｅ）前記フォトレジストパターンをエッチングマスクとして上部絶縁膜をパターニングすることにより、ビアホールを通る配線溝を上部絶縁膜に形成する段階と、 ｆ）下部配線の上部を露出させる段階とを含む金属間絶縁膜のパターン形成方法。 JP2004096080A CLAIM 2 前記層 (substrate coupling area) 間絶縁膜がＳｉＯ ２ 膜、ＳｉＯＦ膜、ＳｉＯＣ膜又は多孔性絶縁膜であることを特徴とする請求項１に記載の金属間絶縁膜のパターン形成方法。 |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch (エッチング後) stop layer protects removal of a substrate material by an etch process . |
JP2004096080A CLAIM 1 ａ）下部配線が形成された半導体基板上に下部エッチング阻止膜、下部絶縁膜、上部エッチング阻止膜及び上部絶縁膜を順次形成する段階と、 ｂ）前記上部絶縁膜、上部エッチング阻止膜及び下部絶縁膜をパターニングして、前記下部配線上の下部エッチング阻止膜を露出させるビアホールを形成する段階と、 ｃ）エッチング後 (first etch) にビアホールをＵＶ光で照射する段階と、 ｄ）前記ビアホールが形成された半導体基板の全面にフォトレジスト膜を形成し、パターニングする段階と、 ｅ）前記フォトレジストパターンをエッチングマスクとして上部絶縁膜をパターニングすることにより、ビアホールを通る配線溝を上部絶縁膜に形成する段階と、 ｆ）下部配線の上部を露出させる段階とを含む金属間絶縁膜のパターン形成方法。 |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch stop layer protects lower layers during an etching process (１００) . |
JP2004096080A CLAIM 10 前記ＵＶ光の照射時に１００ (etching process) 〜３００℃の熱を共に加えることを特徴とする請求項１に記載の金属間絶縁膜のパターン形成方法。 |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area (前記層) of said contact region permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
JP2004096080A CLAIM 2 前記層 (substrate coupling area) 間絶縁膜がＳｉＯ ２ 膜、ＳｉＯＦ膜、ＳｉＯＣ膜又は多孔性絶縁膜であることを特徴とする請求項１に記載の金属間絶縁膜のパターン形成方法。 |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch (エッチング後) stop layer is in a range of about 300 to 800 Å thick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Å thick , said second etch stop layer is in a range of about 300 to 800 Å thick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Å thick . |
JP2004096080A CLAIM 1 ａ）下部配線が形成された半導体基板上に下部エッチング阻止膜、下部絶縁膜、上部エッチング阻止膜及び上部絶縁膜を順次形成する段階と、 ｂ）前記上部絶縁膜、上部エッチング阻止膜及び下部絶縁膜をパターニングして、前記下部配線上の下部エッチング阻止膜を露出させるビアホールを形成する段階と、 ｃ）エッチング後 (first etch) にビアホールをＵＶ光で照射する段階と、 ｄ）前記ビアホールが形成された半導体基板の全面にフォトレジスト膜を形成し、パターニングする段階と、 ｅ）前記フォトレジストパターンをエッチングマスクとして上部絶縁膜をパターニングすることにより、ビアホールを通る配線溝を上部絶縁膜に形成する段階と、 ｆ）下部配線の上部を露出させる段階とを含む金属間絶縁膜のパターン形成方法。 |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range (あること) of about 0 . 16 μm to 0 . 18 μm wide . |
JP2004096080A CLAIM 2 前記層間絶縁膜がＳｉＯ ２ 膜、ＳｉＯＦ膜、ＳｉＯＣ膜又は多孔性絶縁膜であること (second range) を特徴とする請求項１に記載の金属間絶縁膜のパターン形成方法。 |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch (エッチング後) stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area (前記層) of said contact region is smaller than a metal layer coupling area of said contact region . |
JP2004096080A CLAIM 1 ａ）下部配線が形成された半導体基板上に下部エッチング阻止膜、下部絶縁膜、上部エッチング阻止膜及び上部絶縁膜を順次形成する段階と、 ｂ）前記上部絶縁膜、上部エッチング阻止膜及び下部絶縁膜をパターニングして、前記下部配線上の下部エッチング阻止膜を露出させるビアホールを形成する段階と、 ｃ）エッチング後 (first etch) にビアホールをＵＶ光で照射する段階と、 ｄ）前記ビアホールが形成された半導体基板の全面にフォトレジスト膜を形成し、パターニングする段階と、 ｅ）前記フォトレジストパターンをエッチングマスクとして上部絶縁膜をパターニングすることにより、ビアホールを通る配線溝を上部絶縁膜に形成する段階と、 ｆ）下部配線の上部を露出させる段階とを含む金属間絶縁膜のパターン形成方法。 JP2004096080A CLAIM 2 前記層 (substrate coupling area) 間絶縁膜がＳｉＯ ２ 膜、ＳｉＯＦ膜、ＳｉＯＣ膜又は多孔性絶縁膜であることを特徴とする請求項１に記載の金属間絶縁膜のパターン形成方法。 |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch (エッチング後) stop layer is in a range of about 300 to 800 Å thick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Å thick , said second etch stop layer is in a range of about 300 to 800 Å thick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Å thick . |
JP2004096080A CLAIM 1 ａ）下部配線が形成された半導体基板上に下部エッチング阻止膜、下部絶縁膜、上部エッチング阻止膜及び上部絶縁膜を順次形成する段階と、 ｂ）前記上部絶縁膜、上部エッチング阻止膜及び下部絶縁膜をパターニングして、前記下部配線上の下部エッチング阻止膜を露出させるビアホールを形成する段階と、 ｃ）エッチング後 (first etch) にビアホールをＵＶ光で照射する段階と、 ｄ）前記ビアホールが形成された半導体基板の全面にフォトレジスト膜を形成し、パターニングする段階と、 ｅ）前記フォトレジストパターンをエッチングマスクとして上部絶縁膜をパターニングすることにより、ビアホールを通る配線溝を上部絶縁膜に形成する段階と、 ｆ）下部配線の上部を露出させる段階とを含む金属間絶縁膜のパターン形成方法。 |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region is a first range of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range (あること) of about 0 . 16 μm to 0 . 18 μm wide . |
JP2004096080A CLAIM 2 前記層間絶縁膜がＳｉＯ ２ 膜、ＳｉＯＦ膜、ＳｉＯＣ膜又は多孔性絶縁膜であること (second range) を特徴とする請求項１に記載の金属間絶縁膜のパターン形成方法。 |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US6777291B2 Filed: 2003-04-30 Issued: 2004-08-17 Methods of forming programmable memory devices comprising tungsten (Original Assignee) Micron Technology Inc (Current Assignee) Micron Technology Inc Paul J. Rudeck, Graham Wolstenholme, Robert Carr |
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| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US6777291B2 CLAIM 5 . The method of claim 1 further comprising , prior to forming the first layer : forming a layer consisting essentially of silicon nitride over the mass ; forming a layer comprising non-oxidized silicon over the layer consisting essentially of silicon nitride ; and forming (anti reflective coating) a layer comprising silicon oxynitride over the layer comprising non-oxidized silicon . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom (two layers) , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US6777291B2 CLAIM 3 . The method of claim 1 wherein the dielectric material comprises a layer consisting essentially of silicon nitride between two layers (contact bottom) consisting essentially of silicon dioxide . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US6777291B2 CLAIM 5 . The method of claim 1 further comprising , prior to forming the first layer : forming a layer consisting essentially of silicon nitride over the mass ; forming a layer comprising non-oxidized silicon over the layer consisting essentially of silicon nitride ; and forming (anti reflective coating) a layer comprising silicon oxynitride over the layer comprising non-oxidized silicon . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US20040046251A1 Filed: 2003-04-22 Issued: 2004-03-11 Semiconductor contact structure and method of forming the same (Original Assignee) Samsung Electronics Co Ltd (Current Assignee) Samsung Electronics Co Ltd Seung-Whan Lee |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (contact plug) layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US20040046251A1 CLAIM 1 . A semiconductor contact structure comprising : a semiconductor substrate ; an interlayer dielectric disposed on said semiconductor substrate , said interlayer dielectric having a contact hole extending therethrough and exposing a predetermined region of conductive material on the semiconductor substrate , and said conductive material having a recess in the upper surface thereof at the region exposed by the contact hole , said recess being wider than the contact hole as taken laterally in a direction extending along the upper surface of said substrate such that said recess undercuts sidewalls that define said contact hole ; and a contact plug (interlevel dielectric) having a lower portion that rests directly on said conductive material and fills said recess and an upper portion that fills said contact hole , whereby the lower portion of the contact plug is wider than the upper portion thereof so that the contact plug is stably supported atop said conductive material . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (contact plug) layer insulates said contact region . |
US20040046251A1 CLAIM 1 . A semiconductor contact structure comprising : a semiconductor substrate ; an interlayer dielectric disposed on said semiconductor substrate , said interlayer dielectric having a contact hole extending therethrough and exposing a predetermined region of conductive material on the semiconductor substrate , and said conductive material having a recess in the upper surface thereof at the region exposed by the contact hole , said recess being wider than the contact hole as taken laterally in a direction extending along the upper surface of said substrate such that said recess undercuts sidewalls that define said contact hole ; and a contact plug (interlevel dielectric) having a lower portion that rests directly on said conductive material and fills said recess and an upper portion that fills said contact hole , whereby the lower portion of the contact plug is wider than the upper portion thereof so that the contact plug is stably supported atop said conductive material . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch stop layer protects lower layers during an etching process (undercut region) . |
US20040046251A1 CLAIM 8 . The semiconductor contact structure as claimed in claim 1 , wherein said recess is located entirely below the upper surface of said semiconductor substrate undercut region (etching process) is lower than the surface of the semiconductor substrate such that said recess undercuts the sidewalls that define said contact hole at locations beneath the upper surface of said semiconductor substrate . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (contact plug) layer insulates said contact region . |
US20040046251A1 CLAIM 1 . A semiconductor contact structure comprising : a semiconductor substrate ; an interlayer dielectric disposed on said semiconductor substrate , said interlayer dielectric having a contact hole extending therethrough and exposing a predetermined region of conductive material on the semiconductor substrate , and said conductive material having a recess in the upper surface thereof at the region exposed by the contact hole , said recess being wider than the contact hole as taken laterally in a direction extending along the upper surface of said substrate such that said recess undercuts sidewalls that define said contact hole ; and a contact plug (interlevel dielectric) having a lower portion that rests directly on said conductive material and fills said recess and an upper portion that fills said contact hole , whereby the lower portion of the contact plug is wider than the upper portion thereof so that the contact plug is stably supported atop said conductive material . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (contact plug) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US20040046251A1 CLAIM 1 . A semiconductor contact structure comprising : a semiconductor substrate ; an interlayer dielectric disposed on said semiconductor substrate , said interlayer dielectric having a contact hole extending therethrough and exposing a predetermined region of conductive material on the semiconductor substrate , and said conductive material having a recess in the upper surface thereof at the region exposed by the contact hole , said recess being wider than the contact hole as taken laterally in a direction extending along the upper surface of said substrate such that said recess undercuts sidewalls that define said contact hole ; and a contact plug (interlevel dielectric) having a lower portion that rests directly on said conductive material and fills said recess and an upper portion that fills said contact hole , whereby the lower portion of the contact plug is wider than the upper portion thereof so that the contact plug is stably supported atop said conductive material . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space (said sub) in a portion of said first sub interlevel dielectric (contact plug) layer for said contact region is in a first range (predetermined region) of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US20040046251A1 CLAIM 1 . A semiconductor contact structure comprising : a semiconductor substrate ; an interlayer dielectric disposed on said semiconductor substrate , said interlayer dielectric having a contact hole extending therethrough and exposing a predetermined region (first range) of conductive material on the semiconductor substrate , and said conductive material having a recess in the upper surface thereof at the region exposed by the contact hole , said recess being wider than the contact hole as taken laterally in a direction extending along the upper surface of said sub (first space) strate such that said recess undercuts sidewalls that define said contact hole ; and a contact plug (interlevel dielectric) having a lower portion that rests directly on said conductive material and fills said recess and an upper portion that fills said contact hole , whereby the lower portion of the contact plug is wider than the upper portion thereof so that the contact plug is stably supported atop said conductive material . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US20040046251A1 CLAIM 13 . The method as claimed in claim 12 , wherein said forming (anti reflective coating) a conductive pad comprises forming the conductive pad of polysilicon . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (contact plug) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US20040046251A1 CLAIM 1 . A semiconductor contact structure comprising : a semiconductor substrate ; an interlayer dielectric disposed on said semiconductor substrate , said interlayer dielectric having a contact hole extending therethrough and exposing a predetermined region of conductive material on the semiconductor substrate , and said conductive material having a recess in the upper surface thereof at the region exposed by the contact hole , said recess being wider than the contact hole as taken laterally in a direction extending along the upper surface of said substrate such that said recess undercuts sidewalls that define said contact hole ; and a contact plug (interlevel dielectric) having a lower portion that rests directly on said conductive material and fills said recess and an upper portion that fills said contact hole , whereby the lower portion of the contact plug is wider than the upper portion thereof so that the contact plug is stably supported atop said conductive material . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (contact plug) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US20040046251A1 CLAIM 1 . A semiconductor contact structure comprising : a semiconductor substrate ; an interlayer dielectric disposed on said semiconductor substrate , said interlayer dielectric having a contact hole extending therethrough and exposing a predetermined region of conductive material on the semiconductor substrate , and said conductive material having a recess in the upper surface thereof at the region exposed by the contact hole , said recess being wider than the contact hole as taken laterally in a direction extending along the upper surface of said substrate such that said recess undercuts sidewalls that define said contact hole ; and a contact plug (interlevel dielectric) having a lower portion that rests directly on said conductive material and fills said recess and an upper portion that fills said contact hole , whereby the lower portion of the contact plug is wider than the upper portion thereof so that the contact plug is stably supported atop said conductive material . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US20040046251A1 CLAIM 13 . The method as claimed in claim 12 , wherein said forming (anti reflective coating) a conductive pad comprises forming the conductive pad of polysilicon . |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region is a first range (predetermined region) of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US20040046251A1 CLAIM 1 . A semiconductor contact structure comprising : a semiconductor substrate ; an interlayer dielectric disposed on said semiconductor substrate , said interlayer dielectric having a contact hole extending therethrough and exposing a predetermined region (first range) of conductive material on the semiconductor substrate , and said conductive material having a recess in the upper surface thereof at the region exposed by the contact hole , said recess being wider than the contact hole as taken laterally in a direction extending along the upper surface of said substrate such that said recess undercuts sidewalls that define said contact hole ; and a contact plug having a lower portion that rests directly on said conductive material and fills said recess and an upper portion that fills said contact hole , whereby the lower portion of the contact plug is wider than the upper portion thereof so that the contact plug is stably supported atop said conductive material . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | CN1445838A Filed: 2003-03-13 Issued: 2003-10-01 半导体器件及其制造方法 (Original Assignee) 株式会社日立制作所; 日立超大规模集成电路系统株式会社 钵嶺清太, 清水昭博, 大木長斗司, 酒井哲, 山本直樹 |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer (形成第一) directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
CN1445838A CLAIM 1 . 一种制造具有分别形成在半导体基片上的n沟道导电型场效应晶体管和p沟道导电型场效应晶体管的半导体器件的方法，其中包括：(a)在所述n沟道导电型场效应晶体管和p沟道导电型场效应晶体管上形成第一 (first etch stop layer) 绝缘膜，用于在沟道形成区中产生伸张应力，以覆盖所述晶体管的栅极，并且用一个绝缘膜覆盖所述p沟道导电型场效应晶体管的栅极和所述半导体基片的元件隔离区之间的半导体区域；(b)通过蚀刻有选择地从所述p沟道导电型场效应晶体管的上表面除去所述第一绝缘膜；(c)在所述n沟道导电型场效应晶体管和所述p沟道导电型场效应晶体管上形成第二绝缘膜，用于在所述p沟道导电型场效应晶体管的沟道形成区中产生压缩应力，以覆盖所述晶体管的栅极；以及(d)有选择地除去在n沟道导电型场效应晶体管上的第二绝缘膜。 |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer (形成第一) protects removal of a substrate material (氮化硅膜) by an etch process . |
CN1445838A CLAIM 1 . 一种制造具有分别形成在半导体基片上的n沟道导电型场效应晶体管和p沟道导电型场效应晶体管的半导体器件的方法，其中包括：(a)在所述n沟道导电型场效应晶体管和p沟道导电型场效应晶体管上形成第一 (first etch stop layer) 绝缘膜，用于在沟道形成区中产生伸张应力，以覆盖所述晶体管的栅极，并且用一个绝缘膜覆盖所述p沟道导电型场效应晶体管的栅极和所述半导体基片的元件隔离区之间的半导体区域；(b)通过蚀刻有选择地从所述p沟道导电型场效应晶体管的上表面除去所述第一绝缘膜；(c)在所述n沟道导电型场效应晶体管和所述p沟道导电型场效应晶体管上形成第二绝缘膜，用于在所述p沟道导电型场效应晶体管的沟道形成区中产生压缩应力，以覆盖所述晶体管的栅极；以及(d)有选择地除去在n沟道导电型场效应晶体管上的第二绝缘膜。 CN1445838A CLAIM 9 . 根据权利要求1所述的方法，其中：其中所述第一和第二绝缘膜分别为由氮化硅膜 (substrate material) 所制成的用于自对准的绝缘膜。 |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer (形成第一) is in a range of about 300 to 800 Å thick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Å thick , said second etch stop layer is in a range of about 300 to 800 Å thick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Å thick . |
CN1445838A CLAIM 1 . 一种制造具有分别形成在半导体基片上的n沟道导电型场效应晶体管和p沟道导电型场效应晶体管的半导体器件的方法，其中包括：(a)在所述n沟道导电型场效应晶体管和p沟道导电型场效应晶体管上形成第一 (first etch stop layer) 绝缘膜，用于在沟道形成区中产生伸张应力，以覆盖所述晶体管的栅极，并且用一个绝缘膜覆盖所述p沟道导电型场效应晶体管的栅极和所述半导体基片的元件隔离区之间的半导体区域；(b)通过蚀刻有选择地从所述p沟道导电型场效应晶体管的上表面除去所述第一绝缘膜；(c)在所述n沟道导电型场效应晶体管和所述p沟道导电型场效应晶体管上形成第二绝缘膜，用于在所述p沟道导电型场效应晶体管的沟道形成区中产生压缩应力，以覆盖所述晶体管的栅极；以及(d)有选择地除去在n沟道导电型场效应晶体管上的第二绝缘膜。 |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer (形成第一) and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
CN1445838A CLAIM 1 . 一种制造具有分别形成在半导体基片上的n沟道导电型场效应晶体管和p沟道导电型场效应晶体管的半导体器件的方法，其中包括：(a)在所述n沟道导电型场效应晶体管和p沟道导电型场效应晶体管上形成第一 (first etch stop layer) 绝缘膜，用于在沟道形成区中产生伸张应力，以覆盖所述晶体管的栅极，并且用一个绝缘膜覆盖所述p沟道导电型场效应晶体管的栅极和所述半导体基片的元件隔离区之间的半导体区域；(b)通过蚀刻有选择地从所述p沟道导电型场效应晶体管的上表面除去所述第一绝缘膜；(c)在所述n沟道导电型场效应晶体管和所述p沟道导电型场效应晶体管上形成第二绝缘膜，用于在所述p沟道导电型场效应晶体管的沟道形成区中产生压缩应力，以覆盖所述晶体管的栅极；以及(d)有选择地除去在n沟道导电型场效应晶体管上的第二绝缘膜。 |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer (形成第一) is in a range of about 300 to 800 Å thick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Å thick , said second etch stop layer is in a range of about 300 to 800 Å thick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Å thick . |
CN1445838A CLAIM 1 . 一种制造具有分别形成在半导体基片上的n沟道导电型场效应晶体管和p沟道导电型场效应晶体管的半导体器件的方法，其中包括：(a)在所述n沟道导电型场效应晶体管和p沟道导电型场效应晶体管上形成第一 (first etch stop layer) 绝缘膜，用于在沟道形成区中产生伸张应力，以覆盖所述晶体管的栅极，并且用一个绝缘膜覆盖所述p沟道导电型场效应晶体管的栅极和所述半导体基片的元件隔离区之间的半导体区域；(b)通过蚀刻有选择地从所述p沟道导电型场效应晶体管的上表面除去所述第一绝缘膜；(c)在所述n沟道导电型场效应晶体管和所述p沟道导电型场效应晶体管上形成第二绝缘膜，用于在所述p沟道导电型场效应晶体管的沟道形成区中产生压缩应力，以覆盖所述晶体管的栅极；以及(d)有选择地除去在n沟道导电型场效应晶体管上的第二绝缘膜。 |
| US7977797B2 CLAIM 13 . An integrated circuit of claim 11 further comprising a floating gate (栅极侧壁) . |
CN1445838A CLAIM 41 . 一种半导体器件，其中包括：第一场效应晶体管，其形成在所述半导体基片上，并且在置于所述第一晶体管的栅极侧壁 (floating gate) 上的侧壁衬垫与所述半导体基片的元件隔离区之间的半导体区域上具有一个硅化物层；第二场效应晶体管，其形成在所述半导体基片上，并且在置于所述第一晶体管的栅极侧壁上的侧壁衬垫与所述半导体基片的元件隔离区之间的半导体区域上没有硅化物层；第一绝缘膜，用于在所述第一场效应晶体管的沟道形成区中产生应力，并且形成在所述第一场效应晶体管上，以覆盖其栅极；以及第二绝缘膜，用于在所述第二场效应晶体管的沟道形成区中产生应力，并且形成在所述第二场效应晶体管上，以覆盖其栅极；其中在所述第二场效应晶体管的半导体区域和所述第二绝缘膜之间设置一个第三绝缘膜；以及在所述第一场效应晶体管的硅化物层和所述第一绝缘膜之间不设置所述第三绝缘膜。 |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US20040157392A1 Filed: 2003-02-24 Issued: 2004-08-12 Capacitor in an interconnect system and method of manufacturing thereof (Original Assignee) United Microelectronics Corp (Current Assignee) United Microelectronics Corp Ming-Yin Hao, Tri-Rung Yew, Coming Chen, Tsong-Minn Hsieh, Nai-Chen Peng, Jih-Cheng Yeh |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area (second conductive layer) of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer (first etch stop layer) directly on said substrate in said contact region ; a first sub interlevel dielectric (capacitor structure, oxide material) layer over said first etch stop layer ; a second etch stop layer (second etch stop layer) over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US20040157392A1 CLAIM 1 . A method for fabricating a capacitor in a dual damascene interconnect system , comprising : providing a semiconductor wafer layer having at least a metal line ; forming a stack layer over the metal line ; patterning the stack layer to form a capacitor structure (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second etch stop layers, second interlevel dielectric layer) over and in contact with the metal line ; forming an inter-metal dielectric layer over the capacitor structure and the metal line ; and forming simultaneously a first dual damascene interconnect over and in contact with the capacitor structure and a second dual damascene interconnect in the inter-metal dielectric layer . US20040157392A1 CLAIM 5 . The method of claim 1 , wherein the inter-metal dielectric layer is formed with an oxide material (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second etch stop layers, second interlevel dielectric layer) , a silicate glass material , a tetraethylorthosilane material or a low k-dielectric material . US20040157392A1 CLAIM 10 . The method of claim 1 , wherein forming the inter-metal dielectric layer comprises forming sequentially a first etch stop layer (first etch stop layer) , a first insulating layer , a second etch stop layer (second etch stop layer) and a second insulating layer . US20040157392A1 CLAIM 12 . A method for integrating a fabrication of capacitor into a dual damascene process , comprising : providing a semiconductor wafer layer having at least a metal line ; forming a stack layer of a first conductive layer , an amorphous silicon layer and a second conductive layer (substrate coupling area) over the metal line as a capacitor element ; forming a conformal first etch stop layer over the capacitor element and the metal line ; forming a first insulating layer over the first etch stop layer ; planarizing the first insulating layer ; forming a second etch stop layer over the planarized first insulating layer ; forming a second insulating layer over the second etch stop layer ; performing a via first dual damascene profile etch or a trench first dual damascene profile etch to form simultaneously a first dual damascene opening substantially over the capacitor element and a second dual damascene opening in the first etch stop layer , the first insulating layer , the second etch stop layer and the second insulating layer ; forming a conformal barrier layer over the first dual damascene opening , the second dual damascene opening and the second insulating layer ; forming a metal layer over the barrier layer and the second insulating layer and filling the first dual damascene opening and the second dual damascene opening ; and removing the metal layer and the barrier layer outside the first dual damascene opening and the second dual damascene opening . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer (first etch stop layer) protects removal of a substrate material by an etch process (dielectric material) . |
US20040157392A1 CLAIM 5 . The method of claim 1 , wherein the inter-metal dielectric layer is formed with an oxide material , a silicate glass material , a tetraethylorthosilane material or a low k-dielectric material (etch process) . US20040157392A1 CLAIM 10 . The method of claim 1 , wherein forming the inter-metal dielectric layer comprises forming sequentially a first etch stop layer (first etch stop layer) , a first insulating layer , a second etch stop layer and a second insulating layer . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (capacitor structure, oxide material) layer insulates said contact region . |
US20040157392A1 CLAIM 1 . A method for fabricating a capacitor in a dual damascene interconnect system , comprising : providing a semiconductor wafer layer having at least a metal line ; forming a stack layer over the metal line ; patterning the stack layer to form a capacitor structure (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second etch stop layers, second interlevel dielectric layer) over and in contact with the metal line ; forming an inter-metal dielectric layer over the capacitor structure and the metal line ; and forming simultaneously a first dual damascene interconnect over and in contact with the capacitor structure and a second dual damascene interconnect in the inter-metal dielectric layer . US20040157392A1 CLAIM 5 . The method of claim 1 , wherein the inter-metal dielectric layer is formed with an oxide material (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second etch stop layers, second interlevel dielectric layer) , a silicate glass material , a tetraethylorthosilane material or a low k-dielectric material . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch stop layer (second etch stop layer) protects lower layers during an etching process . |
US20040157392A1 CLAIM 10 . The method of claim 1 , wherein forming the inter-metal dielectric layer comprises forming sequentially a first etch stop layer , a first insulating layer , a second etch stop layer (second etch stop layer) and a second insulating layer . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (capacitor structure, oxide material) layer insulates said contact region . |
US20040157392A1 CLAIM 1 . A method for fabricating a capacitor in a dual damascene interconnect system , comprising : providing a semiconductor wafer layer having at least a metal line ; forming a stack layer over the metal line ; patterning the stack layer to form a capacitor structure (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second etch stop layers, second interlevel dielectric layer) over and in contact with the metal line ; forming an inter-metal dielectric layer over the capacitor structure and the metal line ; and forming simultaneously a first dual damascene interconnect over and in contact with the capacitor structure and a second dual damascene interconnect in the inter-metal dielectric layer . US20040157392A1 CLAIM 5 . The method of claim 1 , wherein the inter-metal dielectric layer is formed with an oxide material (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second etch stop layers, second interlevel dielectric layer) , a silicate glass material , a tetraethylorthosilane material or a low k-dielectric material . |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area (second conductive layer) of said contact region permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
US20040157392A1 CLAIM 12 . A method for integrating a fabrication of capacitor into a dual damascene process , comprising : providing a semiconductor wafer layer having at least a metal line ; forming a stack layer of a first conductive layer , an amorphous silicon layer and a second conductive layer (substrate coupling area) over the metal line as a capacitor element ; forming a conformal first etch stop layer over the capacitor element and the metal line ; forming a first insulating layer over the first etch stop layer ; planarizing the first insulating layer ; forming a second etch stop layer over the planarized first insulating layer ; forming a second insulating layer over the second etch stop layer ; performing a via first dual damascene profile etch or a trench first dual damascene profile etch to form simultaneously a first dual damascene opening substantially over the capacitor element and a second dual damascene opening in the first etch stop layer , the first insulating layer , the second etch stop layer and the second insulating layer ; forming a conformal barrier layer over the first dual damascene opening , the second dual damascene opening and the second insulating layer ; forming a metal layer over the barrier layer and the second insulating layer and filling the first dual damascene opening and the second dual damascene opening ; and removing the metal layer and the barrier layer outside the first dual damascene opening and the second dual damascene opening . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer (first etch stop layer) is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (capacitor structure, oxide material) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer (second etch stop layer) is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US20040157392A1 CLAIM 1 . A method for fabricating a capacitor in a dual damascene interconnect system , comprising : providing a semiconductor wafer layer having at least a metal line ; forming a stack layer over the metal line ; patterning the stack layer to form a capacitor structure (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second etch stop layers, second interlevel dielectric layer) over and in contact with the metal line ; forming an inter-metal dielectric layer over the capacitor structure and the metal line ; and forming simultaneously a first dual damascene interconnect over and in contact with the capacitor structure and a second dual damascene interconnect in the inter-metal dielectric layer . US20040157392A1 CLAIM 5 . The method of claim 1 , wherein the inter-metal dielectric layer is formed with an oxide material (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second etch stop layers, second interlevel dielectric layer) , a silicate glass material , a tetraethylorthosilane material or a low k-dielectric material . US20040157392A1 CLAIM 10 . The method of claim 1 , wherein forming the inter-metal dielectric layer comprises forming sequentially a first etch stop layer (first etch stop layer) , a first insulating layer , a second etch stop layer (second etch stop layer) and a second insulating layer . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric (capacitor structure, oxide material) layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US20040157392A1 CLAIM 1 . A method for fabricating a capacitor in a dual damascene interconnect system , comprising : providing a semiconductor wafer layer having at least a metal line ; forming a stack layer over the metal line ; patterning the stack layer to form a capacitor structure (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second etch stop layers, second interlevel dielectric layer) over and in contact with the metal line ; forming an inter-metal dielectric layer over the capacitor structure and the metal line ; and forming simultaneously a first dual damascene interconnect over and in contact with the capacitor structure and a second dual damascene interconnect in the inter-metal dielectric layer . US20040157392A1 CLAIM 5 . The method of claim 1 , wherein the inter-metal dielectric layer is formed with an oxide material (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second etch stop layers, second interlevel dielectric layer) , a silicate glass material , a tetraethylorthosilane material or a low k-dielectric material . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US20040157392A1 CLAIM 1 . A method for fabricating a capacitor in a dual damascene interconnect system , comprising : providing a semiconductor wafer layer having at least a metal line ; forming a stack layer over the metal line ; patterning the stack layer to form a capacitor structure over and in contact with the metal line ; forming an inter-metal dielectric layer over the capacitor structure and the metal line ; and forming (anti reflective coating) simultaneously a first dual damascene interconnect over and in contact with the capacitor structure and a second dual damascene interconnect in the inter-metal dielectric layer . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer (first etch stop layer) and a second etch stop layer (second etch stop layer) wherein said first etch stop layer and said second etch stop layers (capacitor structure, oxide material) have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (capacitor structure, oxide material) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom (silicon carbide) , such that a substrate coupling area (second conductive layer) of said contact region is smaller than a metal layer coupling area of said contact region . |
US20040157392A1 CLAIM 1 . A method for fabricating a capacitor in a dual damascene interconnect system , comprising : providing a semiconductor wafer layer having at least a metal line ; forming a stack layer over the metal line ; patterning the stack layer to form a capacitor structure (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second etch stop layers, second interlevel dielectric layer) over and in contact with the metal line ; forming an inter-metal dielectric layer over the capacitor structure and the metal line ; and forming simultaneously a first dual damascene interconnect over and in contact with the capacitor structure and a second dual damascene interconnect in the inter-metal dielectric layer . US20040157392A1 CLAIM 4 . The method of claim 1 , wherein the stack layer is formed with the group consisting of a tantalum nitride/amorphous carbide/tantalum nitride layer , a tantalum nitride/silicon carbide (contact bottom) /tantalum nitride layer , a titanium nitride/amorphous silicon/titanium nitride layer , a titanium nitride/amorphous carbide/titanium nitride layer and a titanium nitride/silicon carbide/titanium nitride layer . US20040157392A1 CLAIM 5 . The method of claim 1 , wherein the inter-metal dielectric layer is formed with an oxide material (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second etch stop layers, second interlevel dielectric layer) , a silicate glass material , a tetraethylorthosilane material or a low k-dielectric material . US20040157392A1 CLAIM 10 . The method of claim 1 , wherein forming the inter-metal dielectric layer comprises forming sequentially a first etch stop layer (first etch stop layer) , a first insulating layer , a second etch stop layer (second etch stop layer) and a second insulating layer . US20040157392A1 CLAIM 12 . A method for integrating a fabrication of capacitor into a dual damascene process , comprising : providing a semiconductor wafer layer having at least a metal line ; forming a stack layer of a first conductive layer , an amorphous silicon layer and a second conductive layer (substrate coupling area) over the metal line as a capacitor element ; forming a conformal first etch stop layer over the capacitor element and the metal line ; forming a first insulating layer over the first etch stop layer ; planarizing the first insulating layer ; forming a second etch stop layer over the planarized first insulating layer ; forming a second insulating layer over the second etch stop layer ; performing a via first dual damascene profile etch or a trench first dual damascene profile etch to form simultaneously a first dual damascene opening substantially over the capacitor element and a second dual damascene opening in the first etch stop layer , the first insulating layer , the second etch stop layer and the second insulating layer ; forming a conformal barrier layer over the first dual damascene opening , the second dual damascene opening and the second insulating layer ; forming a metal layer over the barrier layer and the second insulating layer and filling the first dual damascene opening and the second dual damascene opening ; and removing the metal layer and the barrier layer outside the first dual damascene opening and the second dual damascene opening . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer (first etch stop layer) is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (capacitor structure, oxide material) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer (second etch stop layer) is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US20040157392A1 CLAIM 1 . A method for fabricating a capacitor in a dual damascene interconnect system , comprising : providing a semiconductor wafer layer having at least a metal line ; forming a stack layer over the metal line ; patterning the stack layer to form a capacitor structure (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second etch stop layers, second interlevel dielectric layer) over and in contact with the metal line ; forming an inter-metal dielectric layer over the capacitor structure and the metal line ; and forming simultaneously a first dual damascene interconnect over and in contact with the capacitor structure and a second dual damascene interconnect in the inter-metal dielectric layer . US20040157392A1 CLAIM 5 . The method of claim 1 , wherein the inter-metal dielectric layer is formed with an oxide material (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second etch stop layers, second interlevel dielectric layer) , a silicate glass material , a tetraethylorthosilane material or a low k-dielectric material . US20040157392A1 CLAIM 10 . The method of claim 1 , wherein forming the inter-metal dielectric layer comprises forming sequentially a first etch stop layer (first etch stop layer) , a first insulating layer , a second etch stop layer (second etch stop layer) and a second insulating layer . |
| US7977797B2 CLAIM 13 . An integrated circuit of claim 11 further comprising a floating gate (amorphous silicon layer) . |
US20040157392A1 CLAIM 2 . The method of claim 1 , wherein forming the stack layer comprises forming sequentially a tantalum nitride layer , an amorphous silicon layer (floating gate) and a tantalum nitride layer . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US20040157392A1 CLAIM 1 . A method for fabricating a capacitor in a dual damascene interconnect system , comprising : providing a semiconductor wafer layer having at least a metal line ; forming a stack layer over the metal line ; patterning the stack layer to form a capacitor structure over and in contact with the metal line ; forming an inter-metal dielectric layer over the capacitor structure and the metal line ; and forming (anti reflective coating) simultaneously a first dual damascene interconnect over and in contact with the capacitor structure and a second dual damascene interconnect in the inter-metal dielectric layer . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US20040152268A1 Filed: 2003-02-05 Issued: 2004-08-05 Novel method of fabricating split gate flash memory cell without select gate-to-drain bridging (Original Assignee) Taiwan Semiconductor Manufacturing Co TSMC Ltd (Current Assignee) Taiwan Semiconductor Manufacturing Co TSMC Ltd Kwo Chu, Chih Chen |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region (contact region) coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (said stack) of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance (forming two) of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer (oxide insulating layer, gate stack) over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US20040152268A1 CLAIM 1 . A method of forming select gate for a split gate flash memory cell comprising : forming a poly silicon select gate stack (second etch stop layer, second etch stop layers) on a silicon substrate , said stack (metal layer coupling area) including select gate oxide , select gate poly silicon layer , and high temperature oxide (HTO) film ; forming select gate mask on said select gate stack ; and selective etching of said select gate stack to stop on said substrate . US20040152268A1 CLAIM 4 . A method of forming a split gate flash memory cell without bridging between select gate and drain , comprising : forming a poly silicon-1 select gate stack on a silicon substrate , said stack including gate oxide , a gate poly silicon-1 layer , and first high temperature oxide (HTO) film ; etching said select gate stack ; forming sidewall silicon oxide spacers around said poly silicon-1 etched structure , depositing floating gate oxide , floating gate poly silicon-2 , and oxide/nitride/oxide (ONO) films over said select gate poly silicon-1 etched structure ; depositing control gate poly silicon-3 and silicon-oxy-nitride (SiON) films over said poly-silicon-1/poly-silicon-2 composite structure ; selective anisotropic etching of said SiON and poly-silicon-3 films to stop on said ONO film ; forming two (isolates guidance) mirror image gate structures by two-step etching of said ONO and poly silicon-2 films to stop on said HTO film and then etching of said HTO and poly silicon-1 films to stop on said select gate oxide ; forming source and drain regions ; forming dielectric spacers in the drain contact region (contact region) ; and forming electrical contacts on said silicon surfaces . US20040152268A1 CLAIM 28 . A triple-poly split gate flash memory cell comprising : select gate oxide over silicon substrate ; select gate poly silicon-1 layer over said gate oxide ; first high temperature oxide insulating layer (second etch stop layer, second etch stop layers) and spacers around said select gate ; floating gate oxide over said silicon substrate and surrounding said select gate ; floating gate poly silicon-2 over said select gate ; oxide-nitride-oxide (ONO) layer over said floating gate ; control gate poly silicon-3 over said ONO layer ; source and drain regions over said substrate and adjacent to said split gates ; second high temperature dielectric spacer around split gate structures ; and electrical contacts over source and drain regions . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer protects removal of a substrate material (silicon oxide) by an etch process (ion implantation) . |
US20040152268A1 CLAIM 4 . A method of forming a split gate flash memory cell without bridging between select gate and drain , comprising : forming a poly silicon-1 select gate stack on a silicon substrate , said stack including gate oxide , a gate poly silicon-1 layer , and first high temperature oxide (HTO) film ; etching said select gate stack ; forming sidewall silicon oxide (substrate material) spacers around said poly silicon-1 etched structure , depositing floating gate oxide , floating gate poly silicon-2 , and oxide/nitride/oxide (ONO) films over said select gate poly silicon-1 etched structure ; depositing control gate poly silicon-3 and silicon-oxy-nitride (SiON) films over said poly-silicon-1/poly-silicon-2 composite structure ; selective anisotropic etching of said SiON and poly-silicon-3 films to stop on said ONO film ; forming two mirror image gate structures by two-step etching of said ONO and poly silicon-2 films to stop on said HTO film and then etching of said HTO and poly silicon-1 films to stop on said select gate oxide ; forming source and drain regions ; forming dielectric spacers in the drain contact region ; and forming electrical contacts on said silicon surfaces . US20040152268A1 CLAIM 17 . A method of forming split gate flash memory cell according to claim 4 , wherein said source and drain regions are formed preferably by ion implantation (etch process) doping . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric layer insulates said contact region (contact region) . |
US20040152268A1 CLAIM 4 . A method of forming a split gate flash memory cell without bridging between select gate and drain , comprising : forming a poly silicon-1 select gate stack on a silicon substrate , said stack including gate oxide , a gate poly silicon-1 layer , and first high temperature oxide (HTO) film ; etching said select gate stack ; forming sidewall silicon oxide spacers around said poly silicon-1 etched structure , depositing floating gate oxide , floating gate poly silicon-2 , and oxide/nitride/oxide (ONO) films over said select gate poly silicon-1 etched structure ; depositing control gate poly silicon-3 and silicon-oxy-nitride (SiON) films over said poly-silicon-1/poly-silicon-2 composite structure ; selective anisotropic etching of said SiON and poly-silicon-3 films to stop on said ONO film ; forming two mirror image gate structures by two-step etching of said ONO and poly silicon-2 films to stop on said HTO film and then etching of said HTO and poly silicon-1 films to stop on said select gate oxide ; forming source and drain regions ; forming dielectric spacers in the drain contact region (contact region) ; and forming electrical contacts on said silicon surfaces . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch stop layer (oxide insulating layer, gate stack) protects lower layers during an etching process (film thickness) . |
US20040152268A1 CLAIM 1 . A method of forming select gate for a split gate flash memory cell comprising : forming a poly silicon select gate stack (second etch stop layer, second etch stop layers) on a silicon substrate , said stack including select gate oxide , select gate poly silicon layer , and high temperature oxide (HTO) film ; forming select gate mask on said select gate stack ; and selective etching of said select gate stack to stop on said substrate . US20040152268A1 CLAIM 11 . A method of forming split gate flash memory cell according to claim 4 , wherein said ONO film thickness (etching process) is between about 40-80° A for bottom silicon oxide , about 60-100° A for silicon nitride , and about 40-80° A for top silicon oxide . US20040152268A1 CLAIM 28 . A triple-poly split gate flash memory cell comprising : select gate oxide over silicon substrate ; select gate poly silicon-1 layer over said gate oxide ; first high temperature oxide insulating layer (second etch stop layer, second etch stop layers) and spacers around said select gate ; floating gate oxide over said silicon substrate and surrounding said select gate ; floating gate poly silicon-2 over said select gate ; oxide-nitride-oxide (ONO) layer over said floating gate ; control gate poly silicon-3 over said ONO layer ; source and drain regions over said substrate and adjacent to said split gates ; second high temperature dielectric spacer around split gate structures ; and electrical contacts over source and drain regions . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric layer insulates said contact region (contact region) . |
US20040152268A1 CLAIM 4 . A method of forming a split gate flash memory cell without bridging between select gate and drain , comprising : forming a poly silicon-1 select gate stack on a silicon substrate , said stack including gate oxide , a gate poly silicon-1 layer , and first high temperature oxide (HTO) film ; etching said select gate stack ; forming sidewall silicon oxide spacers around said poly silicon-1 etched structure , depositing floating gate oxide , floating gate poly silicon-2 , and oxide/nitride/oxide (ONO) films over said select gate poly silicon-1 etched structure ; depositing control gate poly silicon-3 and silicon-oxy-nitride (SiON) films over said poly-silicon-1/poly-silicon-2 composite structure ; selective anisotropic etching of said SiON and poly-silicon-3 films to stop on said ONO film ; forming two mirror image gate structures by two-step etching of said ONO and poly silicon-2 films to stop on said HTO film and then etching of said HTO and poly silicon-1 films to stop on said select gate oxide ; forming source and drain regions ; forming dielectric spacers in the drain contact region (contact region) ; and forming electrical contacts on said silicon surfaces . |
| US7977797B2 CLAIM 6 . An integrated circuit of claim 1 wherein said spacer region insulates said contact region (contact region) . |
US20040152268A1 CLAIM 4 . A method of forming a split gate flash memory cell without bridging between select gate and drain , comprising : forming a poly silicon-1 select gate stack on a silicon substrate , said stack including gate oxide , a gate poly silicon-1 layer , and first high temperature oxide (HTO) film ; etching said select gate stack ; forming sidewall silicon oxide spacers around said poly silicon-1 etched structure , depositing floating gate oxide , floating gate poly silicon-2 , and oxide/nitride/oxide (ONO) films over said select gate poly silicon-1 etched structure ; depositing control gate poly silicon-3 and silicon-oxy-nitride (SiON) films over said poly-silicon-1/poly-silicon-2 composite structure ; selective anisotropic etching of said SiON and poly-silicon-3 films to stop on said ONO film ; forming two mirror image gate structures by two-step etching of said ONO and poly silicon-2 films to stop on said HTO film and then etching of said HTO and poly silicon-1 films to stop on said select gate oxide ; forming source and drain regions ; forming dielectric spacers in the drain contact region (contact region) ; and forming electrical contacts on said silicon surfaces . |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area of said contact region (contact region) permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area (said stack) of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
US20040152268A1 CLAIM 1 . A method of forming select gate for a split gate flash memory cell comprising : forming a poly silicon select gate stack on a silicon substrate , said stack (metal layer coupling area) including select gate oxide , select gate poly silicon layer , and high temperature oxide (HTO) film ; forming select gate mask on said select gate stack ; and selective etching of said select gate stack to stop on said substrate . US20040152268A1 CLAIM 4 . A method of forming a split gate flash memory cell without bridging between select gate and drain , comprising : forming a poly silicon-1 select gate stack on a silicon substrate , said stack including gate oxide , a gate poly silicon-1 layer , and first high temperature oxide (HTO) film ; etching said select gate stack ; forming sidewall silicon oxide spacers around said poly silicon-1 etched structure , depositing floating gate oxide , floating gate poly silicon-2 , and oxide/nitride/oxide (ONO) films over said select gate poly silicon-1 etched structure ; depositing control gate poly silicon-3 and silicon-oxy-nitride (SiON) films over said poly-silicon-1/poly-silicon-2 composite structure ; selective anisotropic etching of said SiON and poly-silicon-3 films to stop on said ONO film ; forming two mirror image gate structures by two-step etching of said ONO and poly silicon-2 films to stop on said HTO film and then etching of said HTO and poly silicon-1 films to stop on said select gate oxide ; forming source and drain regions ; forming dielectric spacers in the drain contact region (contact region) ; and forming electrical contacts on said silicon surfaces . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer (oxide insulating layer, gate stack) is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US20040152268A1 CLAIM 1 . A method of forming select gate for a split gate flash memory cell comprising : forming a poly silicon select gate stack (second etch stop layer, second etch stop layers) on a silicon substrate , said stack including select gate oxide , select gate poly silicon layer , and high temperature oxide (HTO) film ; forming select gate mask on said select gate stack ; and selective etching of said select gate stack to stop on said substrate . US20040152268A1 CLAIM 28 . A triple-poly split gate flash memory cell comprising : select gate oxide over silicon substrate ; select gate poly silicon-1 layer over said gate oxide ; first high temperature oxide insulating layer (second etch stop layer, second etch stop layers) and spacers around said select gate ; floating gate oxide over said silicon substrate and surrounding said select gate ; floating gate poly silicon-2 over said select gate ; oxide-nitride-oxide (ONO) layer over said floating gate ; control gate poly silicon-3 over said ONO layer ; source and drain regions over said substrate and adjacent to said split gates ; second high temperature dielectric spacer around split gate structures ; and electrical contacts over source and drain regions . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space (said sub) in a portion of said first sub interlevel dielectric layer for said contact region (contact region) is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US20040152268A1 CLAIM 1 . A method of forming select gate for a split gate flash memory cell comprising : forming a poly silicon select gate stack on a silicon substrate , said stack including select gate oxide , select gate poly silicon layer , and high temperature oxide (HTO) film ; forming select gate mask on said select gate stack ; and selective etching of said select gate stack to stop on said sub (first space) strate . US20040152268A1 CLAIM 4 . A method of forming a split gate flash memory cell without bridging between select gate and drain , comprising : forming a poly silicon-1 select gate stack on a silicon substrate , said stack including gate oxide , a gate poly silicon-1 layer , and first high temperature oxide (HTO) film ; etching said select gate stack ; forming sidewall silicon oxide spacers around said poly silicon-1 etched structure , depositing floating gate oxide , floating gate poly silicon-2 , and oxide/nitride/oxide (ONO) films over said select gate poly silicon-1 etched structure ; depositing control gate poly silicon-3 and silicon-oxy-nitride (SiON) films over said poly-silicon-1/poly-silicon-2 composite structure ; selective anisotropic etching of said SiON and poly-silicon-3 films to stop on said ONO film ; forming two mirror image gate structures by two-step etching of said ONO and poly silicon-2 films to stop on said HTO film and then etching of said HTO and poly silicon-1 films to stop on said select gate oxide ; forming source and drain regions ; forming dielectric spacers in the drain contact region (contact region) ; and forming electrical contacts on said silicon surfaces . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US20040152268A1 CLAIM 4 . A method of forming a split gate flash memory cell without bridging between select gate and drain , comprising : forming a poly silicon-1 select gate stack on a silicon substrate , said stack including gate oxide , a gate poly silicon-1 layer , and first high temperature oxide (HTO) film ; etching said select gate stack ; forming sidewall silicon oxide spacers around said poly silicon-1 etched structure , depositing floating gate oxide , floating gate poly silicon-2 , and oxide/nitride/oxide (ONO) films over said select gate poly silicon-1 etched structure ; depositing control gate poly silicon-3 and silicon-oxy-nitride (SiON) films over said poly-silicon-1/poly-silicon-2 composite structure ; selective anisotropic etching of said SiON and poly-silicon-3 films to stop on said ONO film ; forming two mirror image gate structures by two-step etching of said ONO and poly silicon-2 films to stop on said HTO film and then etching of said HTO and poly silicon-1 films to stop on said select gate oxide ; forming source and drain regions ; forming dielectric spacers in the drain contact region ; and forming (anti reflective coating) electrical contacts on said silicon surfaces . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer (oxide insulating layer, gate stack) wherein said first etch stop layer and said second etch stop layers (oxide insulating layer, gate stack) have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region (contact region) and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (said stack) of said contact region . |
US20040152268A1 CLAIM 1 . A method of forming select gate for a split gate flash memory cell comprising : forming a poly silicon select gate stack (second etch stop layer, second etch stop layers) on a silicon substrate , said stack (metal layer coupling area) including select gate oxide , select gate poly silicon layer , and high temperature oxide (HTO) film ; forming select gate mask on said select gate stack ; and selective etching of said select gate stack to stop on said substrate . US20040152268A1 CLAIM 4 . A method of forming a split gate flash memory cell without bridging between select gate and drain , comprising : forming a poly silicon-1 select gate stack on a silicon substrate , said stack including gate oxide , a gate poly silicon-1 layer , and first high temperature oxide (HTO) film ; etching said select gate stack ; forming sidewall silicon oxide spacers around said poly silicon-1 etched structure , depositing floating gate oxide , floating gate poly silicon-2 , and oxide/nitride/oxide (ONO) films over said select gate poly silicon-1 etched structure ; depositing control gate poly silicon-3 and silicon-oxy-nitride (SiON) films over said poly-silicon-1/poly-silicon-2 composite structure ; selective anisotropic etching of said SiON and poly-silicon-3 films to stop on said ONO film ; forming two mirror image gate structures by two-step etching of said ONO and poly silicon-2 films to stop on said HTO film and then etching of said HTO and poly silicon-1 films to stop on said select gate oxide ; forming source and drain regions ; forming dielectric spacers in the drain contact region (contact region) ; and forming electrical contacts on said silicon surfaces . US20040152268A1 CLAIM 28 . A triple-poly split gate flash memory cell comprising : select gate oxide over silicon substrate ; select gate poly silicon-1 layer over said gate oxide ; first high temperature oxide insulating layer (second etch stop layer, second etch stop layers) and spacers around said select gate ; floating gate oxide over said silicon substrate and surrounding said select gate ; floating gate poly silicon-2 over said select gate ; oxide-nitride-oxide (ONO) layer over said floating gate ; control gate poly silicon-3 over said ONO layer ; source and drain regions over said substrate and adjacent to said split gates ; second high temperature dielectric spacer around split gate structures ; and electrical contacts over source and drain regions . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer (oxide insulating layer, gate stack) is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US20040152268A1 CLAIM 1 . A method of forming select gate for a split gate flash memory cell comprising : forming a poly silicon select gate stack (second etch stop layer, second etch stop layers) on a silicon substrate , said stack including select gate oxide , select gate poly silicon layer , and high temperature oxide (HTO) film ; forming select gate mask on said select gate stack ; and selective etching of said select gate stack to stop on said substrate . US20040152268A1 CLAIM 28 . A triple-poly split gate flash memory cell comprising : select gate oxide over silicon substrate ; select gate poly silicon-1 layer over said gate oxide ; first high temperature oxide insulating layer (second etch stop layer, second etch stop layers) and spacers around said select gate ; floating gate oxide over said silicon substrate and surrounding said select gate ; floating gate poly silicon-2 over said select gate ; oxide-nitride-oxide (ONO) layer over said floating gate ; control gate poly silicon-3 over said ONO layer ; source and drain regions over said substrate and adjacent to said split gates ; second high temperature dielectric spacer around split gate structures ; and electrical contacts over source and drain regions . |
| US7977797B2 CLAIM 13 . An integrated circuit of claim 11 further comprising a floating gate (floating gate, drain regions) . |
US20040152268A1 CLAIM 4 . A method of forming a split gate flash memory cell without bridging between select gate and drain , comprising : forming a poly silicon-1 select gate stack on a silicon substrate , said stack including gate oxide , a gate poly silicon-1 layer , and first high temperature oxide (HTO) film ; etching said select gate stack ; forming sidewall silicon oxide spacers around said poly silicon-1 etched structure , depositing floating gate (floating gate) oxide , floating gate poly silicon-2 , and oxide/nitride/oxide (ONO) films over said select gate poly silicon-1 etched structure ; depositing control gate poly silicon-3 and silicon-oxy-nitride (SiON) films over said poly-silicon-1/poly-silicon-2 composite structure ; selective anisotropic etching of said SiON and poly-silicon-3 films to stop on said ONO film ; forming two mirror image gate structures by two-step etching of said ONO and poly silicon-2 films to stop on said HTO film and then etching of said HTO and poly silicon-1 films to stop on said select gate oxide ; forming source and drain regions (floating gate) ; forming dielectric spacers in the drain contact region ; and forming electrical contacts on said silicon surfaces . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US20040152268A1 CLAIM 4 . A method of forming a split gate flash memory cell without bridging between select gate and drain , comprising : forming a poly silicon-1 select gate stack on a silicon substrate , said stack including gate oxide , a gate poly silicon-1 layer , and first high temperature oxide (HTO) film ; etching said select gate stack ; forming sidewall silicon oxide spacers around said poly silicon-1 etched structure , depositing floating gate oxide , floating gate poly silicon-2 , and oxide/nitride/oxide (ONO) films over said select gate poly silicon-1 etched structure ; depositing control gate poly silicon-3 and silicon-oxy-nitride (SiON) films over said poly-silicon-1/poly-silicon-2 composite structure ; selective anisotropic etching of said SiON and poly-silicon-3 films to stop on said ONO film ; forming two mirror image gate structures by two-step etching of said ONO and poly silicon-2 films to stop on said HTO film and then etching of said HTO and poly silicon-1 films to stop on said select gate oxide ; forming source and drain regions ; forming dielectric spacers in the drain contact region ; and forming (anti reflective coating) electrical contacts on said silicon surfaces . |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region (contact region) is a first range of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US20040152268A1 CLAIM 4 . A method of forming a split gate flash memory cell without bridging between select gate and drain , comprising : forming a poly silicon-1 select gate stack on a silicon substrate , said stack including gate oxide , a gate poly silicon-1 layer , and first high temperature oxide (HTO) film ; etching said select gate stack ; forming sidewall silicon oxide spacers around said poly silicon-1 etched structure , depositing floating gate oxide , floating gate poly silicon-2 , and oxide/nitride/oxide (ONO) films over said select gate poly silicon-1 etched structure ; depositing control gate poly silicon-3 and silicon-oxy-nitride (SiON) films over said poly-silicon-1/poly-silicon-2 composite structure ; selective anisotropic etching of said SiON and poly-silicon-3 films to stop on said ONO film ; forming two mirror image gate structures by two-step etching of said ONO and poly silicon-2 films to stop on said HTO film and then etching of said HTO and poly silicon-1 films to stop on said select gate oxide ; forming source and drain regions ; forming dielectric spacers in the drain contact region (contact region) ; and forming electrical contacts on said silicon surfaces . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | JP2004221104A Filed: 2003-01-09 Issued: 2004-08-05 半導体装置とその製造方法 (Original Assignee) Matsushita Electric Ind Co Ltd; 松下電器産業株式会社 Mitsuru Sekiguchi, 満 関口 |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (製造方法) of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (膜密度) layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer (少なくとも) over said second etch stop layer . |
JP2004221104A CLAIM 1 半導体基板上に形成された低誘電率膜上に接続孔を形成する工程（ａ）と、 前記低誘電率膜の表面と前記接続孔内に露出した前記低誘電率膜の表面の膜密度 (interlevel dielectric) を上げる工程（ｂ）と、 前記工程（ｂ）の後に少なくとも (second sub interlevel dielectric layer) 前記接続孔を含む領域に開口部を有するレジストパターンを形成する工程（ｃ）とを有する半導体装置の製造方法 (metal layer coupling area) 。 |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (膜密度) layer insulates said contact region . |
JP2004221104A CLAIM 1 半導体基板上に形成された低誘電率膜上に接続孔を形成する工程（ａ）と、 前記低誘電率膜の表面と前記接続孔内に露出した前記低誘電率膜の表面の膜密度 (interlevel dielectric) を上げる工程（ｂ）と、 前記工程（ｂ）の後に少なくとも前記接続孔を含む領域に開口部を有するレジストパターンを形成する工程（ｃ）とを有する半導体装置の製造方法。 |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (膜密度) layer (少なくとも) insulates said contact region . |
JP2004221104A CLAIM 1 半導体基板上に形成された低誘電率膜上に接続孔を形成する工程（ａ）と、 前記低誘電率膜の表面と前記接続孔内に露出した前記低誘電率膜の表面の膜密度 (interlevel dielectric) を上げる工程（ｂ）と、 前記工程（ｂ）の後に少なくとも (second sub interlevel dielectric layer) 前記接続孔を含む領域に開口部を有するレジストパターンを形成する工程（ｃ）とを有する半導体装置の製造方法。 |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area of said contact region permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area (製造方法) of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
JP2004221104A CLAIM 1 半導体基板上に形成された低誘電率膜上に接続孔を形成する工程（ａ）と、 前記低誘電率膜の表面と前記接続孔内に露出した前記低誘電率膜の表面の膜密度を上げる工程（ｂ）と、 前記工程（ｂ）の後に少なくとも前記接続孔を含む領域に開口部を有するレジストパターンを形成する工程（ｃ）とを有する半導体装置の製造方法 (metal layer coupling area) 。 |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Å thick , said first sub interlevel dielectric (膜密度) layer is in a range of about 1 , 000 to 2 , 000 Å thick , said second etch stop layer is in a range of about 300 to 800 Å thick and said second sub interlevel dielectric layer (少なくとも) is in a range of about 10K ű1K Å thick . |
JP2004221104A CLAIM 1 半導体基板上に形成された低誘電率膜上に接続孔を形成する工程（ａ）と、 前記低誘電率膜の表面と前記接続孔内に露出した前記低誘電率膜の表面の膜密度 (interlevel dielectric) を上げる工程（ｂ）と、 前記工程（ｂ）の後に少なくとも (second sub interlevel dielectric layer) 前記接続孔を含む領域に開口部を有するレジストパターンを形成する工程（ｃ）とを有する半導体装置の製造方法。 |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric (膜密度) layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer (少なくとも) for said contact region is in a second range (あること) of about 0 . 16 μm to 0 . 18 μm wide . |
JP2004221104A CLAIM 1 半導体基板上に形成された低誘電率膜上に接続孔を形成する工程（ａ）と、 前記低誘電率膜の表面と前記接続孔内に露出した前記低誘電率膜の表面の膜密度 (interlevel dielectric) を上げる工程（ｂ）と、 前記工程（ｂ）の後に少なくとも (second sub interlevel dielectric layer) 前記接続孔を含む領域に開口部を有するレジストパターンを形成する工程（ｃ）とを有する半導体装置の製造方法。 JP2004221104A CLAIM 10 前記低誘電率膜が、Ｃを含むシリコン酸化膜であること (second range) を特徴とする、請求項９に記載の半導体装置。 |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (膜密度) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer (少なくとも) and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (製造方法) of said contact region . |
JP2004221104A CLAIM 1 半導体基板上に形成された低誘電率膜上に接続孔を形成する工程（ａ）と、 前記低誘電率膜の表面と前記接続孔内に露出した前記低誘電率膜の表面の膜密度 (interlevel dielectric) を上げる工程（ｂ）と、 前記工程（ｂ）の後に少なくとも (second sub interlevel dielectric layer) 前記接続孔を含む領域に開口部を有するレジストパターンを形成する工程（ｃ）とを有する半導体装置の製造方法 (metal layer coupling area) 。 |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Å thick , said first sub interlevel dielectric (膜密度) layer is in a range of about 1 , 000 to 2 , 000 Å thick , said second etch stop layer is in a range of about 300 to 800 Å thick and said second sub interlevel dielectric layer (少なくとも) is in a range of about 10K ű1K Å thick . |
JP2004221104A CLAIM 1 半導体基板上に形成された低誘電率膜上に接続孔を形成する工程（ａ）と、 前記低誘電率膜の表面と前記接続孔内に露出した前記低誘電率膜の表面の膜密度 (interlevel dielectric) を上げる工程（ｂ）と、 前記工程（ｂ）の後に少なくとも (second sub interlevel dielectric layer) 前記接続孔を含む領域に開口部を有するレジストパターンを形成する工程（ｃ）とを有する半導体装置の製造方法。 |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region is a first range of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range (あること) of about 0 . 16 μm to 0 . 18 μm wide . |
JP2004221104A CLAIM 10 前記低誘電率膜が、Ｃを含むシリコン酸化膜であること (second range) を特徴とする、請求項９に記載の半導体装置。 |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US20040014278A1 Filed: 2002-12-09 Issued: 2004-01-22 Method for fabricating semiconductor device (Original Assignee) SK Hynix Inc (Current Assignee) SK Hynix Inc Sung-Kwon Lee, Dong-Sauk Kim |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area (second conductive layer) of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch (tungsten nitride) stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (contact hole, mixed gas) layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US20040014278A1 CLAIM 1 . A method for fabricating a semiconductor device , comprising the steps of : forming a plurality of patterns on a substrate , wherein the patterns are formed by stacking and patterning a first conductive layer , a silicon nitride mask layer and a metal mask layer on the substrate ; depositing a first silicon oxide layer along the profile containing the patterns ; etching the first silicon oxide layer for forming a silicon oxide spacer with a height lower than a top part of the silicon nitride mask layer so as to partially expose a top part of lateral sides of patterns and simultaneously etching the metal mask layer to expose the silicon nitride mask layer , wherein the metal mask layer prevents losses of the silicon nitride mask layer ; forming a silicon nitride spacer on a surface of the silicon oxide spacer and the lateral sides of the patterns ; forming a second silicon oxide layer on an entire structure in which the silicon nitride spacer is formed ; etching selectively the second silicon oxide layer to expose silicon nitride layer spacer and forming a self-align contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) that is partially expanded to the top portion of the patterns ; and forming a self-align contact structure by filling the self-align contact hole with a second conductive layer (substrate coupling area) . US20040014278A1 CLAIM 3 . The method as recited in claim 2 , wherein the metal mask layer includes any one material selected from a group consisting of tungsten , tungsten silicide and tungsten nitride (multiple etch) . US20040014278A1 CLAIM 8 . The method as recited in claim 6 , wherein the mixed gas (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) is any one selected from a group consisting of C 4 F 8 , C 5 F 8 and C 4 F 6 . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (contact hole, mixed gas) layer insulates said contact region . |
US20040014278A1 CLAIM 1 . A method for fabricating a semiconductor device , comprising the steps of : forming a plurality of patterns on a substrate , wherein the patterns are formed by stacking and patterning a first conductive layer , a silicon nitride mask layer and a metal mask layer on the substrate ; depositing a first silicon oxide layer along the profile containing the patterns ; etching the first silicon oxide layer for forming a silicon oxide spacer with a height lower than a top part of the silicon nitride mask layer so as to partially expose a top part of lateral sides of patterns and simultaneously etching the metal mask layer to expose the silicon nitride mask layer , wherein the metal mask layer prevents losses of the silicon nitride mask layer ; forming a silicon nitride spacer on a surface of the silicon oxide spacer and the lateral sides of the patterns ; forming a second silicon oxide layer on an entire structure in which the silicon nitride spacer is formed ; etching selectively the second silicon oxide layer to expose silicon nitride layer spacer and forming a self-align contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) that is partially expanded to the top portion of the patterns ; and forming a self-align contact structure by filling the self-align contact hole with a second conductive layer . US20040014278A1 CLAIM 8 . The method as recited in claim 6 , wherein the mixed gas (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) is any one selected from a group consisting of C 4 F 8 , C 5 F 8 and C 4 F 6 . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (contact hole, mixed gas) layer insulates said contact region . |
US20040014278A1 CLAIM 1 . A method for fabricating a semiconductor device , comprising the steps of : forming a plurality of patterns on a substrate , wherein the patterns are formed by stacking and patterning a first conductive layer , a silicon nitride mask layer and a metal mask layer on the substrate ; depositing a first silicon oxide layer along the profile containing the patterns ; etching the first silicon oxide layer for forming a silicon oxide spacer with a height lower than a top part of the silicon nitride mask layer so as to partially expose a top part of lateral sides of patterns and simultaneously etching the metal mask layer to expose the silicon nitride mask layer , wherein the metal mask layer prevents losses of the silicon nitride mask layer ; forming a silicon nitride spacer on a surface of the silicon oxide spacer and the lateral sides of the patterns ; forming a second silicon oxide layer on an entire structure in which the silicon nitride spacer is formed ; etching selectively the second silicon oxide layer to expose silicon nitride layer spacer and forming a self-align contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) that is partially expanded to the top portion of the patterns ; and forming a self-align contact structure by filling the self-align contact hole with a second conductive layer . US20040014278A1 CLAIM 8 . The method as recited in claim 6 , wherein the mixed gas (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) is any one selected from a group consisting of C 4 F 8 , C 5 F 8 and C 4 F 6 . |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area (second conductive layer) of said contact region permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
US20040014278A1 CLAIM 1 . A method for fabricating a semiconductor device , comprising the steps of : forming a plurality of patterns on a substrate , wherein the patterns are formed by stacking and patterning a first conductive layer , a silicon nitride mask layer and a metal mask layer on the substrate ; depositing a first silicon oxide layer along the profile containing the patterns ; etching the first silicon oxide layer for forming a silicon oxide spacer with a height lower than a top part of the silicon nitride mask layer so as to partially expose a top part of lateral sides of patterns and simultaneously etching the metal mask layer to expose the silicon nitride mask layer , wherein the metal mask layer prevents losses of the silicon nitride mask layer ; forming a silicon nitride spacer on a surface of the silicon oxide spacer and the lateral sides of the patterns ; forming a second silicon oxide layer on an entire structure in which the silicon nitride spacer is formed ; etching selectively the second silicon oxide layer to expose silicon nitride layer spacer and forming a self-align contact hole that is partially expanded to the top portion of the patterns ; and forming a self-align contact structure by filling the self-align contact hole with a second conductive layer (substrate coupling area) . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (contact hole, mixed gas) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US20040014278A1 CLAIM 1 . A method for fabricating a semiconductor device , comprising the steps of : forming a plurality of patterns on a substrate , wherein the patterns are formed by stacking and patterning a first conductive layer , a silicon nitride mask layer and a metal mask layer on the substrate ; depositing a first silicon oxide layer along the profile containing the patterns ; etching the first silicon oxide layer for forming a silicon oxide spacer with a height lower than a top part of the silicon nitride mask layer so as to partially expose a top part of lateral sides of patterns and simultaneously etching the metal mask layer to expose the silicon nitride mask layer , wherein the metal mask layer prevents losses of the silicon nitride mask layer ; forming a silicon nitride spacer on a surface of the silicon oxide spacer and the lateral sides of the patterns ; forming a second silicon oxide layer on an entire structure in which the silicon nitride spacer is formed ; etching selectively the second silicon oxide layer to expose silicon nitride layer spacer and forming a self-align contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) that is partially expanded to the top portion of the patterns ; and forming a self-align contact structure by filling the self-align contact hole with a second conductive layer . US20040014278A1 CLAIM 8 . The method as recited in claim 6 , wherein the mixed gas (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) is any one selected from a group consisting of C 4 F 8 , C 5 F 8 and C 4 F 6 . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric (contact hole, mixed gas) layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US20040014278A1 CLAIM 1 . A method for fabricating a semiconductor device , comprising the steps of : forming a plurality of patterns on a substrate , wherein the patterns are formed by stacking and patterning a first conductive layer , a silicon nitride mask layer and a metal mask layer on the substrate ; depositing a first silicon oxide layer along the profile containing the patterns ; etching the first silicon oxide layer for forming a silicon oxide spacer with a height lower than a top part of the silicon nitride mask layer so as to partially expose a top part of lateral sides of patterns and simultaneously etching the metal mask layer to expose the silicon nitride mask layer , wherein the metal mask layer prevents losses of the silicon nitride mask layer ; forming a silicon nitride spacer on a surface of the silicon oxide spacer and the lateral sides of the patterns ; forming a second silicon oxide layer on an entire structure in which the silicon nitride spacer is formed ; etching selectively the second silicon oxide layer to expose silicon nitride layer spacer and forming a self-align contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) that is partially expanded to the top portion of the patterns ; and forming a self-align contact structure by filling the self-align contact hole with a second conductive layer . US20040014278A1 CLAIM 8 . The method as recited in claim 6 , wherein the mixed gas (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) is any one selected from a group consisting of C 4 F 8 , C 5 F 8 and C 4 F 6 . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US20040014278A1 CLAIM 1 . A method for fabricating a semiconductor device , comprising the steps of : forming a plurality of patterns on a substrate , wherein the patterns are formed by stacking and patterning a first conductive layer , a silicon nitride mask layer and a metal mask layer on the substrate ; depositing a first silicon oxide layer along the profile containing the patterns ; etching the first silicon oxide layer for forming a silicon oxide spacer with a height lower than a top part of the silicon nitride mask layer so as to partially expose a top part of lateral sides of patterns and simultaneously etching the metal mask layer to expose the silicon nitride mask layer , wherein the metal mask layer prevents losses of the silicon nitride mask layer ; forming a silicon nitride spacer on a surface of the silicon oxide spacer and the lateral sides of the patterns ; forming a second silicon oxide layer on an entire structure in which the silicon nitride spacer is formed ; etching selectively the second silicon oxide layer to expose silicon nitride layer spacer and forming (anti reflective coating) a self-align contact hole that is partially expanded to the top portion of the patterns ; and forming a self-align contact structure by filling the self-align contact hole with a second conductive layer . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch (tungsten nitride) stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers (silicon nitride layer) have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (contact hole, mixed gas) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom (top portion) , such that a substrate coupling area (second conductive layer) of said contact region is smaller than a metal layer coupling area of said contact region . |
US20040014278A1 CLAIM 1 . A method for fabricating a semiconductor device , comprising the steps of : forming a plurality of patterns on a substrate , wherein the patterns are formed by stacking and patterning a first conductive layer , a silicon nitride mask layer and a metal mask layer on the substrate ; depositing a first silicon oxide layer along the profile containing the patterns ; etching the first silicon oxide layer for forming a silicon oxide spacer with a height lower than a top part of the silicon nitride mask layer so as to partially expose a top part of lateral sides of patterns and simultaneously etching the metal mask layer to expose the silicon nitride mask layer , wherein the metal mask layer prevents losses of the silicon nitride mask layer ; forming a silicon nitride spacer on a surface of the silicon oxide spacer and the lateral sides of the patterns ; forming a second silicon oxide layer on an entire structure in which the silicon nitride spacer is formed ; etching selectively the second silicon oxide layer to expose silicon nitride layer (second etch stop layers) spacer and forming a self-align contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) that is partially expanded to the top portion (contact bottom) of the patterns ; and forming a self-align contact structure by filling the self-align contact hole with a second conductive layer (substrate coupling area) . US20040014278A1 CLAIM 3 . The method as recited in claim 2 , wherein the metal mask layer includes any one material selected from a group consisting of tungsten , tungsten silicide and tungsten nitride (multiple etch) . US20040014278A1 CLAIM 8 . The method as recited in claim 6 , wherein the mixed gas (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) is any one selected from a group consisting of C 4 F 8 , C 5 F 8 and C 4 F 6 . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (contact hole, mixed gas) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US20040014278A1 CLAIM 1 . A method for fabricating a semiconductor device , comprising the steps of : forming a plurality of patterns on a substrate , wherein the patterns are formed by stacking and patterning a first conductive layer , a silicon nitride mask layer and a metal mask layer on the substrate ; depositing a first silicon oxide layer along the profile containing the patterns ; etching the first silicon oxide layer for forming a silicon oxide spacer with a height lower than a top part of the silicon nitride mask layer so as to partially expose a top part of lateral sides of patterns and simultaneously etching the metal mask layer to expose the silicon nitride mask layer , wherein the metal mask layer prevents losses of the silicon nitride mask layer ; forming a silicon nitride spacer on a surface of the silicon oxide spacer and the lateral sides of the patterns ; forming a second silicon oxide layer on an entire structure in which the silicon nitride spacer is formed ; etching selectively the second silicon oxide layer to expose silicon nitride layer spacer and forming a self-align contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) that is partially expanded to the top portion of the patterns ; and forming a self-align contact structure by filling the self-align contact hole with a second conductive layer . US20040014278A1 CLAIM 8 . The method as recited in claim 6 , wherein the mixed gas (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) is any one selected from a group consisting of C 4 F 8 , C 5 F 8 and C 4 F 6 . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US20040014278A1 CLAIM 1 . A method for fabricating a semiconductor device , comprising the steps of : forming a plurality of patterns on a substrate , wherein the patterns are formed by stacking and patterning a first conductive layer , a silicon nitride mask layer and a metal mask layer on the substrate ; depositing a first silicon oxide layer along the profile containing the patterns ; etching the first silicon oxide layer for forming a silicon oxide spacer with a height lower than a top part of the silicon nitride mask layer so as to partially expose a top part of lateral sides of patterns and simultaneously etching the metal mask layer to expose the silicon nitride mask layer , wherein the metal mask layer prevents losses of the silicon nitride mask layer ; forming a silicon nitride spacer on a surface of the silicon oxide spacer and the lateral sides of the patterns ; forming a second silicon oxide layer on an entire structure in which the silicon nitride spacer is formed ; etching selectively the second silicon oxide layer to expose silicon nitride layer spacer and forming (anti reflective coating) a self-align contact hole that is partially expanded to the top portion of the patterns ; and forming a self-align contact structure by filling the self-align contact hole with a second conductive layer . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | JP2003174144A Filed: 2002-12-05 Issued: 2003-06-20 半導体装置における微小コンタクト領域、高性能相変化メモリセル及びその製造方法 (Original Assignee) Ovonyx Inc; Stmicroelectronics Srl; エスティーマイクロエレクトロニクス エス．アール．エル; オヴォニクス インコーポレイテッド Roberto Bez, Fabio Pellizzer, Caterina Riva, Romina Zonca, カテリーナ・リーヴァ, ファビオ・ペリゼール, ロベルト・ベズ, ロミーナ・ゾンカ |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region (前記第１方向, 接触面) coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer (コレクタ) coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation (の絶縁) between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer (少なくとも) over said second etch stop layer . |
JP2003174144A CLAIM 1 【請求項１】 第１方向に第１サブリソグラフィック 寸法を有する第１の薄膜部分を含む第１伝導性領域と、 前記第１方向 (contact region) を横断する第２方向に第２サブリソグラフ ィック寸法を有する第２の薄膜部分を含む第２伝導性領 域とを備え、 前記第１及び第２の伝導性領域が、前記第１及び第２の 薄膜部分と直接電気的に接触し、サブリソグラフィック 伸張部を有する接触面 (contact region) を構成することを特徴とする電子 半導体装置におけるコンタクト構造。 JP2003174144A CLAIM 5 【請求項５】 前記第２方向が、少なくとも (second sub interlevel dielectric layer) 前記接触 面の近隣で前記第１方向に垂直となることを特徴とする 請求項１記載のコンタクト構造。 JP2003174144A CLAIM 14 【請求項１４】 前記第１及び第２の絶縁 (electrical insulation) 層が低−Ｋ 材料であることを特徴とする請求項１１記載の相変化メ モリセル。 JP2003174144A CLAIM 17 【請求項１７】 前記半導体本体が基板及びエピタキ シャル層を含み、前記エピタキシャル層が、前記陰極領 域と前記基板の間に広がるコレクタ (multiple etch stop insulation layer) 領域を収容し、前記 陽極領域と前記陰極領域とともにバイポーラトランジス タを形成することを特徴とする請求項１６記載の相変化 メモリセル。 |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric layer insulates said contact region (前記第１方向, 接触面) . |
JP2003174144A CLAIM 1 【請求項１】 第１方向に第１サブリソグラフィック 寸法を有する第１の薄膜部分を含む第１伝導性領域と、 前記第１方向 (contact region) を横断する第２方向に第２サブリソグラフ ィック寸法を有する第２の薄膜部分を含む第２伝導性領 域とを備え、 前記第１及び第２の伝導性領域が、前記第１及び第２の 薄膜部分と直接電気的に接触し、サブリソグラフィック 伸張部を有する接触面 (contact region) を構成することを特徴とする電子 半導体装置におけるコンタクト構造。 |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch stop layer protects lower layers during an etching process (１００) . |
JP2003174144A CLAIM 2 【請求項２】 前記第１及び第２のサブリソグラフィ ック寸法が１００ (etching process) ｎｍより小さいことを特徴とする請求 項１記載のコンタクト構造。 |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric layer (少なくとも) insulates said contact region (前記第１方向, 接触面) . |
JP2003174144A CLAIM 1 【請求項１】 第１方向に第１サブリソグラフィック 寸法を有する第１の薄膜部分を含む第１伝導性領域と、 前記第１方向 (contact region) を横断する第２方向に第２サブリソグラフ ィック寸法を有する第２の薄膜部分を含む第２伝導性領 域とを備え、 前記第１及び第２の伝導性領域が、前記第１及び第２の 薄膜部分と直接電気的に接触し、サブリソグラフィック 伸張部を有する接触面 (contact region) を構成することを特徴とする電子 半導体装置におけるコンタクト構造。 JP2003174144A CLAIM 5 【請求項５】 前記第２方向が、少なくとも (second sub interlevel dielectric layer) 前記接触 面の近隣で前記第１方向に垂直となることを特徴とする 請求項１記載のコンタクト構造。 |
| US7977797B2 CLAIM 6 . An integrated circuit of claim 1 wherein said spacer region insulates said contact region (前記第１方向, 接触面) . |
JP2003174144A CLAIM 1 【請求項１】 第１方向に第１サブリソグラフィック 寸法を有する第１の薄膜部分を含む第１伝導性領域と、 前記第１方向 (contact region) を横断する第２方向に第２サブリソグラフ ィック寸法を有する第２の薄膜部分を含む第２伝導性領 域とを備え、 前記第１及び第２の伝導性領域が、前記第１及び第２の 薄膜部分と直接電気的に接触し、サブリソグラフィック 伸張部を有する接触面 (contact region) を構成することを特徴とする電子 半導体装置におけるコンタクト構造。 |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area of said contact region (前記第１方向, 接触面) permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
JP2003174144A CLAIM 1 【請求項１】 第１方向に第１サブリソグラフィック 寸法を有する第１の薄膜部分を含む第１伝導性領域と、 前記第１方向 (contact region) を横断する第２方向に第２サブリソグラフ ィック寸法を有する第２の薄膜部分を含む第２伝導性領 域とを備え、 前記第１及び第２の伝導性領域が、前記第１及び第２の 薄膜部分と直接電気的に接触し、サブリソグラフィック 伸張部を有する接触面 (contact region) を構成することを特徴とする電子 半導体装置におけるコンタクト構造。 |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Å thick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Å thick , said second etch stop layer is in a range of about 300 to 800 Å thick and said second sub interlevel dielectric layer (少なくとも) is in a range of about 10K ű1K Å thick . |
JP2003174144A CLAIM 5 【請求項５】 前記第２方向が、少なくとも (second sub interlevel dielectric layer) 前記接触 面の近隣で前記第１方向に垂直となることを特徴とする 請求項１記載のコンタクト構造。 |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space (モールド) in a portion of said first sub interlevel dielectric layer for said contact region (前記第１方向, 接触面) is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer (少なくとも) for said contact region is in a second range (あること) of about 0 . 16 μm to 0 . 18 μm wide . |
JP2003174144A CLAIM 1 【請求項１】 第１方向に第１サブリソグラフィック 寸法を有する第１の薄膜部分を含む第１伝導性領域と、 前記第１方向 (contact region) を横断する第２方向に第２サブリソグラフ ィック寸法を有する第２の薄膜部分を含む第２伝導性領 域とを備え、 前記第１及び第２の伝導性領域が、前記第１及び第２の 薄膜部分と直接電気的に接触し、サブリソグラフィック 伸張部を有する接触面 (contact region) を構成することを特徴とする電子 半導体装置におけるコンタクト構造。 JP2003174144A CLAIM 4 【請求項４】 前記第１及び第２のサブリソグラフィ ック寸法が約２０ｎｍであること (second range) を特徴とする請求項１ 記載のコンタクト構造。 JP2003174144A CLAIM 5 【請求項５】 前記第２方向が、少なくとも (second sub interlevel dielectric layer) 前記接触 面の近隣で前記第１方向に垂直となることを特徴とする 請求項１記載のコンタクト構造。 JP2003174144A CLAIM 24 【請求項２４】 第１限界層を形成する前に、前記第１ 絶縁層の上部にモールド (first space) 層を形成するステップを有し、 前記第２開口部を用いる前記ステップが前記第２開口部 の下の前記モールド層内に第３開口部を形成するステッ プと、前記第１及び第２の限界層を取り除くステップ と、前記第３開口部を第２導体材料で充填するステップ とを有することを特徴とする請求項２２記載の製造方 法。 |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer (コレクタ) comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region (前記第１方向, 接触面) and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer (少なくとも) and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
JP2003174144A CLAIM 1 【請求項１】 第１方向に第１サブリソグラフィック 寸法を有する第１の薄膜部分を含む第１伝導性領域と、 前記第１方向 (contact region) を横断する第２方向に第２サブリソグラフ ィック寸法を有する第２の薄膜部分を含む第２伝導性領 域とを備え、 前記第１及び第２の伝導性領域が、前記第１及び第２の 薄膜部分と直接電気的に接触し、サブリソグラフィック 伸張部を有する接触面 (contact region) を構成することを特徴とする電子 半導体装置におけるコンタクト構造。 JP2003174144A CLAIM 5 【請求項５】 前記第２方向が、少なくとも (second sub interlevel dielectric layer) 前記接触 面の近隣で前記第１方向に垂直となることを特徴とする 請求項１記載のコンタクト構造。 JP2003174144A CLAIM 17 【請求項１７】 前記半導体本体が基板及びエピタキ シャル層を含み、前記エピタキシャル層が、前記陰極領 域と前記基板の間に広がるコレクタ (multiple etch stop insulation layer) 領域を収容し、前記 陽極領域と前記陰極領域とともにバイポーラトランジス タを形成することを特徴とする請求項１６記載の相変化 メモリセル。 |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Å thick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Å thick , said second etch stop layer is in a range of about 300 to 800 Å thick and said second sub interlevel dielectric layer (少なくとも) is in a range of about 10K ű1K Å thick . |
JP2003174144A CLAIM 5 【請求項５】 前記第２方向が、少なくとも (second sub interlevel dielectric layer) 前記接触 面の近隣で前記第１方向に垂直となることを特徴とする 請求項１記載のコンタクト構造。 |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region (前記第１方向, 接触面) is a first range of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range (あること) of about 0 . 16 μm to 0 . 18 μm wide . |
JP2003174144A CLAIM 1 【請求項１】 第１方向に第１サブリソグラフィック 寸法を有する第１の薄膜部分を含む第１伝導性領域と、 前記第１方向 (contact region) を横断する第２方向に第２サブリソグラフ ィック寸法を有する第２の薄膜部分を含む第２伝導性領 域とを備え、 前記第１及び第２の伝導性領域が、前記第１及び第２の 薄膜部分と直接電気的に接触し、サブリソグラフィック 伸張部を有する接触面 (contact region) を構成することを特徴とする電子 半導体装置におけるコンタクト構造。 JP2003174144A CLAIM 4 【請求項４】 前記第１及び第２のサブリソグラフィ ック寸法が約２０ｎｍであること (second range) を特徴とする請求項１ 記載のコンタクト構造。 |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | JP2003229482A Filed: 2002-12-05 Issued: 2003-08-15 半導体素子の銅配線形成方法 (Original Assignee) Hynix Semiconductor Inc; 株式会社ハイニックスセミコンダクター Choon Kun Ryu, 春 根 柳 |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions (さまた) of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (ハードマスク) layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
JP2003229482A CLAIM 1 【請求項１】 下部金属配線が形成された半導体基板を 提供する段階と、 前記下部金属配線を含んだ全体構造上に低誘電膜を形成 する段階と、 前記低誘電膜上にハードマスク (interlevel dielectric) 層を形成する段階と、 前記ハードマスク層上にフォトレジストパターンを形成 した後、前記フォトレジストパターンを用いたエッチン グ工程で前記低誘電膜の一部分をエッチングしてダマシ ンパターンを形成し、前記ダマシンパターン形成のため のエッチング工程中に発生するポリマーが前記ダマシン パターンの側面に付着してポリマー層を形成する段階 と、 ＳｉＨ ４ プラズマを用いて前記ポリマー層をＳｉＣＨ膜 に変化させた後、前記フォトレジストパターンを除去す る段階と、 前記ハードマスク層と前記ＳｉＣＨ膜によって取り囲ま れている前記低誘電膜を含んだ全体構造上に銅層を形成 した後、化学機械研磨工程で前記銅層を研磨して銅配線 を形成する段階とを含んでなることを特徴とする半導体 素子の銅配線形成方法。 JP2003229482A CLAIM 5 【請求項５】 前記ポリマー層はエッチングガスを変化 させて厚さまた (other regions) は成分を調節することを特徴とする請求 項１記載の半導体素子の銅配線形成方法。 |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (ハードマスク) layer insulates said contact region . |
JP2003229482A CLAIM 1 【請求項１】 下部金属配線が形成された半導体基板を 提供する段階と、 前記下部金属配線を含んだ全体構造上に低誘電膜を形成 する段階と、 前記低誘電膜上にハードマスク (interlevel dielectric) 層を形成する段階と、 前記ハードマスク層上にフォトレジストパターンを形成 した後、前記フォトレジストパターンを用いたエッチン グ工程で前記低誘電膜の一部分をエッチングしてダマシ ンパターンを形成し、前記ダマシンパターン形成のため のエッチング工程中に発生するポリマーが前記ダマシン パターンの側面に付着してポリマー層を形成する段階 と、 ＳｉＨ ４ プラズマを用いて前記ポリマー層をＳｉＣＨ膜 に変化させた後、前記フォトレジストパターンを除去す る段階と、 前記ハードマスク層と前記ＳｉＣＨ膜によって取り囲ま れている前記低誘電膜を含んだ全体構造上に銅層を形成 した後、化学機械研磨工程で前記銅層を研磨して銅配線 を形成する段階とを含んでなることを特徴とする半導体 素子の銅配線形成方法。 |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (ハードマスク) layer insulates said contact region . |
JP2003229482A CLAIM 1 【請求項１】 下部金属配線が形成された半導体基板を 提供する段階と、 前記下部金属配線を含んだ全体構造上に低誘電膜を形成 する段階と、 前記低誘電膜上にハードマスク (interlevel dielectric) 層を形成する段階と、 前記ハードマスク層上にフォトレジストパターンを形成 した後、前記フォトレジストパターンを用いたエッチン グ工程で前記低誘電膜の一部分をエッチングしてダマシ ンパターンを形成し、前記ダマシンパターン形成のため のエッチング工程中に発生するポリマーが前記ダマシン パターンの側面に付着してポリマー層を形成する段階 と、 ＳｉＨ ４ プラズマを用いて前記ポリマー層をＳｉＣＨ膜 に変化させた後、前記フォトレジストパターンを除去す る段階と、 前記ハードマスク層と前記ＳｉＣＨ膜によって取り囲ま れている前記低誘電膜を含んだ全体構造上に銅層を形成 した後、化学機械研磨工程で前記銅層を研磨して銅配線 を形成する段階とを含んでなることを特徴とする半導体 素子の銅配線形成方法。 |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Å thick , said first sub interlevel dielectric (ハードマスク) layer is in a range of about 1 , 000 to 2 , 000 Å thick , said second etch stop layer is in a range of about 300 to 800 Å thick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Å thick . |
JP2003229482A CLAIM 1 【請求項１】 下部金属配線が形成された半導体基板を 提供する段階と、 前記下部金属配線を含んだ全体構造上に低誘電膜を形成 する段階と、 前記低誘電膜上にハードマスク (interlevel dielectric) 層を形成する段階と、 前記ハードマスク層上にフォトレジストパターンを形成 した後、前記フォトレジストパターンを用いたエッチン グ工程で前記低誘電膜の一部分をエッチングしてダマシ ンパターンを形成し、前記ダマシンパターン形成のため のエッチング工程中に発生するポリマーが前記ダマシン パターンの側面に付着してポリマー層を形成する段階 と、 ＳｉＨ ４ プラズマを用いて前記ポリマー層をＳｉＣＨ膜 に変化させた後、前記フォトレジストパターンを除去す る段階と、 前記ハードマスク層と前記ＳｉＣＨ膜によって取り囲ま れている前記低誘電膜を含んだ全体構造上に銅層を形成 した後、化学機械研磨工程で前記銅層を研磨して銅配線 を形成する段階とを含んでなることを特徴とする半導体 素子の銅配線形成方法。 |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric (ハードマスク) layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
JP2003229482A CLAIM 1 【請求項１】 下部金属配線が形成された半導体基板を 提供する段階と、 前記下部金属配線を含んだ全体構造上に低誘電膜を形成 する段階と、 前記低誘電膜上にハードマスク (interlevel dielectric) 層を形成する段階と、 前記ハードマスク層上にフォトレジストパターンを形成 した後、前記フォトレジストパターンを用いたエッチン グ工程で前記低誘電膜の一部分をエッチングしてダマシ ンパターンを形成し、前記ダマシンパターン形成のため のエッチング工程中に発生するポリマーが前記ダマシン パターンの側面に付着してポリマー層を形成する段階 と、 ＳｉＨ ４ プラズマを用いて前記ポリマー層をＳｉＣＨ膜 に変化させた後、前記フォトレジストパターンを除去す る段階と、 前記ハードマスク層と前記ＳｉＣＨ膜によって取り囲ま れている前記低誘電膜を含んだ全体構造上に銅層を形成 した後、化学機械研磨工程で前記銅層を研磨して銅配線 を形成する段階とを含んでなることを特徴とする半導体 素子の銅配線形成方法。 |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (ハードマスク) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
JP2003229482A CLAIM 1 【請求項１】 下部金属配線が形成された半導体基板を 提供する段階と、 前記下部金属配線を含んだ全体構造上に低誘電膜を形成 する段階と、 前記低誘電膜上にハードマスク (interlevel dielectric) 層を形成する段階と、 前記ハードマスク層上にフォトレジストパターンを形成 した後、前記フォトレジストパターンを用いたエッチン グ工程で前記低誘電膜の一部分をエッチングしてダマシ ンパターンを形成し、前記ダマシンパターン形成のため のエッチング工程中に発生するポリマーが前記ダマシン パターンの側面に付着してポリマー層を形成する段階 と、 ＳｉＨ ４ プラズマを用いて前記ポリマー層をＳｉＣＨ膜 に変化させた後、前記フォトレジストパターンを除去す る段階と、 前記ハードマスク層と前記ＳｉＣＨ膜によって取り囲ま れている前記低誘電膜を含んだ全体構造上に銅層を形成 した後、化学機械研磨工程で前記銅層を研磨して銅配線 を形成する段階とを含んでなることを特徴とする半導体 素子の銅配線形成方法。 |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Å thick , said first sub interlevel dielectric (ハードマスク) layer is in a range of about 1 , 000 to 2 , 000 Å thick , said second etch stop layer is in a range of about 300 to 800 Å thick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Å thick . |
JP2003229482A CLAIM 1 【請求項１】 下部金属配線が形成された半導体基板を 提供する段階と、 前記下部金属配線を含んだ全体構造上に低誘電膜を形成 する段階と、 前記低誘電膜上にハードマスク (interlevel dielectric) 層を形成する段階と、 前記ハードマスク層上にフォトレジストパターンを形成 した後、前記フォトレジストパターンを用いたエッチン グ工程で前記低誘電膜の一部分をエッチングしてダマシ ンパターンを形成し、前記ダマシンパターン形成のため のエッチング工程中に発生するポリマーが前記ダマシン パターンの側面に付着してポリマー層を形成する段階 と、 ＳｉＨ ４ プラズマを用いて前記ポリマー層をＳｉＣＨ膜 に変化させた後、前記フォトレジストパターンを除去す る段階と、 前記ハードマスク層と前記ＳｉＣＨ膜によって取り囲ま れている前記低誘電膜を含んだ全体構造上に銅層を形成 した後、化学機械研磨工程で前記銅層を研磨して銅配線 を形成する段階とを含んでなることを特徴とする半導体 素子の銅配線形成方法。 |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | JP2004186452A Filed: 2002-12-04 Issued: 2004-07-02 不揮発性半導体記憶装置およびその製造方法 (Original Assignee) Renesas Technology Corp; 株式会社ルネサステクノロジ Masaru Hisamoto, Shinichiro Kimura, Nozomi Matsuzaki, Kan Yasui, 大 久本, 感 安井, 紳一郎 木村, 望 松崎 |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer (前記電圧) coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
JP2004186452A CLAIM 18 請求項１７記載の不揮発性半導体記憶装置において、 前記電圧 (multiple etch stop insulation layer) パルスは、前記第２ゲートに負電位を与え、前記第２半導体領域に正電位を与える電圧パルスであることを特徴とする不揮発性半導体記憶装置。 |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric layer for said contact region is in a first range (範囲内) of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range (あること) of about 0 . 16 μm to 0 . 18 μm wide . |
JP2004186452A CLAIM 4 請求項１記載の不揮発性半導体記憶装置において、 前記第２絶縁膜は、酸化シリコン膜、窒化シリコン膜および酸化シリコン膜の積層膜であること (second range) を特徴とする不揮発性半導体記憶装置。 JP2004186452A CLAIM 6 請求項１記載の不揮発性半導体記憶装置において、 前記第２チャネル領域の不純物の電荷密度は１０ １７ ／ｃｍ ３ 〜１０ １８ ／ｃｍ ３ の範囲内 (first range) であることを特徴とする不揮発性半導体記憶装置。 |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer (前記電圧) comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
JP2004186452A CLAIM 18 請求項１７記載の不揮発性半導体記憶装置において、 前記電圧 (multiple etch stop insulation layer) パルスは、前記第２ゲートに負電位を与え、前記第２半導体領域に正電位を与える電圧パルスであることを特徴とする不揮発性半導体記憶装置。 |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region is a first range (範囲内) of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range (あること) of about 0 . 16 μm to 0 . 18 μm wide . |
JP2004186452A CLAIM 4 請求項１記載の不揮発性半導体記憶装置において、 前記第２絶縁膜は、酸化シリコン膜、窒化シリコン膜および酸化シリコン膜の積層膜であること (second range) を特徴とする不揮発性半導体記憶装置。 JP2004186452A CLAIM 6 請求項１記載の不揮発性半導体記憶装置において、 前記第２チャネル領域の不純物の電荷密度は１０ １７ ／ｃｍ ３ 〜１０ １８ ／ｃｍ ３ の範囲内 (first range) であることを特徴とする不揮発性半導体記憶装置。 |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | KR20040038422A Filed: 2002-11-01 Issued: 2004-05-08 상변환 기억소자 및 그 제조방법 (Original Assignee) 삼성전자주식회사 이세호, 황영남 |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region (콘택홀이) such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
KR20040038422A CLAIM 2 제1 항에 있어서 , 상기 하부전극을 갖는 반도체 기판에 덮여지고 , 상기 하부전극 상에 콘택홀이 (spacer region) 형성된 층간절연막을 더 포함하되 , 상기 상변환 패턴은 상기 콘택홀 내에 형성되고 상기 하부전극 방향으로 덴트를 갖는 것을 특징으로 하는 상변환 기억소자 . |
| US7977797B2 CLAIM 6 . An integrated circuit of claim 1 wherein said spacer region (콘택홀이) insulates said contact region . |
KR20040038422A CLAIM 2 제1 항에 있어서 , 상기 하부전극을 갖는 반도체 기판에 덮여지고 , 상기 하부전극 상에 콘택홀이 (spacer region) 형성된 층간절연막을 더 포함하되 , 상기 상변환 패턴은 상기 콘택홀 내에 형성되고 상기 하부전극 방향으로 덴트를 갖는 것을 특징으로 하는 상변환 기억소자 . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers (low region) have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer (연막의) , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
KR20040038422A CLAIM 3 반도체 기판에 형성된 하부전극 ; 상기 하부전극을 갖는 반도체 기판 상에 형성되고 , 상기 하부전극 상에 콘택홀의 내벽을 형성하는 층간절연막 ; 상기 콘택홀의 내벽에 형성되어 상기 하부전극 상에 할로영역(hollow region (second etch stop layers) )을 갖는 스페이서 패턴 ; 상기 할로영역을 채우고 , 상기 층간절연막 상에 측벽을 갖는 상변환 패턴 ; 상기 상변환 패턴 상에 형성된 상부전극을 포함하되 , 상기 상부전극은 상기 하부전극 상부에 상기 하부전극을 향하는 팁(tip)을 갖는 것을 특징으로 하는 상변환 기억소자 . KR20040038422A CLAIM 20 제17 항에 있어서 , 상기 상변환 패턴을 형성하는 단계는 , 상기 할로영역을 갖는 반도체 기판 상에 상기 하부전극 상부에 덴트를 갖는 상변환막을 형성하되 , 상기 덴트의 최심부는 상기 층간절연막의 (second interlevel dielectric layer) 상부면보다 낮은 레벨에 위치하도록 형성하는 단계 ; 화학적기계적 연마공정을 사용하여 상기 상변환막을 연마하여 상기 층간절연막을 노출시키고 , 상기 할로영역 내에 상변환 패턴을 형성하는 단계를 포함하는 것을 특징으로 하는 상변환 기억소자의 제조방법 . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | JP2004146442A Filed: 2002-10-22 Issued: 2004-05-20 薄膜トランジスタ及び薄膜トランジスタの製造方法 (Original Assignee) Toshiba Corp; 株式会社東芝 Takashi Fujimura, Yuki Matsuura, 松 浦 由 紀, 藤 村 尚 |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area (前記層) of said contact region is smaller than a metal layer coupling area (製造方法) of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer (少なくとも) over said second etch stop layer . |
JP2004146442A CLAIM 2 前記層 (substrate coupling area) 間絶縁膜及び前記ゲート絶縁膜に形成されたコンタクトホール内に埋め込み形成された前記ソース・ドレイン領域に接続する信号線電極を備えることを特徴とする請求項１に記載の薄膜トランジスタ。 JP2004146442A CLAIM 4 薄膜トランジスタにおけるシリコン酸化膜によるゲート絶縁膜と、前記ゲート絶縁膜上に形成されたシリコン窒化膜による第１層間絶縁膜部と、前記第１層間絶縁膜部上に形成された有機絶縁膜による第２層間絶縁膜部とをエッチングし、ソース・ドレイン領域に通じるコンタクトホールを形成する工程を有する薄膜トランジスタの製造方法 (metal layer coupling area) において、 前記第２層間絶縁膜部及び前記第１層間絶縁膜部に第１のホールを形成する第１のエッチング工程と、 前記ゲート絶縁膜に、前記第１のホールに連通し、この第１のホールとでコンタクトホールをなす、第２のホールを形成する第２のエッチング工程とを備え、 前記第１のエッチング工程では、炭素、フッ素、窒素ガスを少なくとも (second sub interlevel dielectric layer) 含んだ混合ガスでエッチングをし、前記第２のエッチング工程では、炭素、フッ素、水素ガスを少なくとも含んだ混合ガスでエッチングをする、 ことを特徴とする薄膜トランジスタの製造方法。 |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric layer (少なくとも) insulates said contact region . |
JP2004146442A CLAIM 4 薄膜トランジスタにおけるシリコン酸化膜によるゲート絶縁膜と、前記ゲート絶縁膜上に形成されたシリコン窒化膜による第１層間絶縁膜部と、前記第１層間絶縁膜部上に形成された有機絶縁膜による第２層間絶縁膜部とをエッチングし、ソース・ドレイン領域に通じるコンタクトホールを形成する工程を有する薄膜トランジスタの製造方法において、 前記第２層間絶縁膜部及び前記第１層間絶縁膜部に第１のホールを形成する第１のエッチング工程と、 前記ゲート絶縁膜に、前記第１のホールに連通し、この第１のホールとでコンタクトホールをなす、第２のホールを形成する第２のエッチング工程とを備え、 前記第１のエッチング工程では、炭素、フッ素、窒素ガスを少なくとも (second sub interlevel dielectric layer) 含んだ混合ガスでエッチングをし、前記第２のエッチング工程では、炭素、フッ素、水素ガスを少なくとも含んだ混合ガスでエッチングをする、 ことを特徴とする薄膜トランジスタの製造方法。 |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area (前記層) of said contact region permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area (製造方法) of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
JP2004146442A CLAIM 2 前記層 (substrate coupling area) 間絶縁膜及び前記ゲート絶縁膜に形成されたコンタクトホール内に埋め込み形成された前記ソース・ドレイン領域に接続する信号線電極を備えることを特徴とする請求項１に記載の薄膜トランジスタ。 JP2004146442A CLAIM 4 薄膜トランジスタにおけるシリコン酸化膜によるゲート絶縁膜と、前記ゲート絶縁膜上に形成されたシリコン窒化膜による第１層間絶縁膜部と、前記第１層間絶縁膜部上に形成された有機絶縁膜による第２層間絶縁膜部とをエッチングし、ソース・ドレイン領域に通じるコンタクトホールを形成する工程を有する薄膜トランジスタの製造方法 (metal layer coupling area) において、 前記第２層間絶縁膜部及び前記第１層間絶縁膜部に第１のホールを形成する第１のエッチング工程と、 前記ゲート絶縁膜に、前記第１のホールに連通し、この第１のホールとでコンタクトホールをなす、第２のホールを形成する第２のエッチング工程とを備え、 前記第１のエッチング工程では、炭素、フッ素、窒素ガスを少なくとも含んだ混合ガスでエッチングをし、前記第２のエッチング工程では、炭素、フッ素、水素ガスを少なくとも含んだ混合ガスでエッチングをする、 ことを特徴とする薄膜トランジスタの製造方法。 |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Å thick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Å thick , said second etch stop layer is in a range of about 300 to 800 Å thick and said second sub interlevel dielectric layer (少なくとも) is in a range of about 10K ű1K Å thick . |
JP2004146442A CLAIM 4 薄膜トランジスタにおけるシリコン酸化膜によるゲート絶縁膜と、前記ゲート絶縁膜上に形成されたシリコン窒化膜による第１層間絶縁膜部と、前記第１層間絶縁膜部上に形成された有機絶縁膜による第２層間絶縁膜部とをエッチングし、ソース・ドレイン領域に通じるコンタクトホールを形成する工程を有する薄膜トランジスタの製造方法において、 前記第２層間絶縁膜部及び前記第１層間絶縁膜部に第１のホールを形成する第１のエッチング工程と、 前記ゲート絶縁膜に、前記第１のホールに連通し、この第１のホールとでコンタクトホールをなす、第２のホールを形成する第２のエッチング工程とを備え、 前記第１のエッチング工程では、炭素、フッ素、窒素ガスを少なくとも (second sub interlevel dielectric layer) 含んだ混合ガスでエッチングをし、前記第２のエッチング工程では、炭素、フッ素、水素ガスを少なくとも含んだ混合ガスでエッチングをする、 ことを特徴とする薄膜トランジスタの製造方法。 |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer (少なくとも) for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
JP2004146442A CLAIM 4 薄膜トランジスタにおけるシリコン酸化膜によるゲート絶縁膜と、前記ゲート絶縁膜上に形成されたシリコン窒化膜による第１層間絶縁膜部と、前記第１層間絶縁膜部上に形成された有機絶縁膜による第２層間絶縁膜部とをエッチングし、ソース・ドレイン領域に通じるコンタクトホールを形成する工程を有する薄膜トランジスタの製造方法において、 前記第２層間絶縁膜部及び前記第１層間絶縁膜部に第１のホールを形成する第１のエッチング工程と、 前記ゲート絶縁膜に、前記第１のホールに連通し、この第１のホールとでコンタクトホールをなす、第２のホールを形成する第２のエッチング工程とを備え、 前記第１のエッチング工程では、炭素、フッ素、窒素ガスを少なくとも (second sub interlevel dielectric layer) 含んだ混合ガスでエッチングをし、前記第２のエッチング工程では、炭素、フッ素、水素ガスを少なくとも含んだ混合ガスでエッチングをする、 ことを特徴とする薄膜トランジスタの製造方法。 |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer (少なくとも) and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area (前記層) of said contact region is smaller than a metal layer coupling area (製造方法) of said contact region . |
JP2004146442A CLAIM 2 前記層 (substrate coupling area) 間絶縁膜及び前記ゲート絶縁膜に形成されたコンタクトホール内に埋め込み形成された前記ソース・ドレイン領域に接続する信号線電極を備えることを特徴とする請求項１に記載の薄膜トランジスタ。 JP2004146442A CLAIM 4 薄膜トランジスタにおけるシリコン酸化膜によるゲート絶縁膜と、前記ゲート絶縁膜上に形成されたシリコン窒化膜による第１層間絶縁膜部と、前記第１層間絶縁膜部上に形成された有機絶縁膜による第２層間絶縁膜部とをエッチングし、ソース・ドレイン領域に通じるコンタクトホールを形成する工程を有する薄膜トランジスタの製造方法 (metal layer coupling area) において、 前記第２層間絶縁膜部及び前記第１層間絶縁膜部に第１のホールを形成する第１のエッチング工程と、 前記ゲート絶縁膜に、前記第１のホールに連通し、この第１のホールとでコンタクトホールをなす、第２のホールを形成する第２のエッチング工程とを備え、 前記第１のエッチング工程では、炭素、フッ素、窒素ガスを少なくとも (second sub interlevel dielectric layer) 含んだ混合ガスでエッチングをし、前記第２のエッチング工程では、炭素、フッ素、水素ガスを少なくとも含んだ混合ガスでエッチングをする、 ことを特徴とする薄膜トランジスタの製造方法。 |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Å thick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Å thick , said second etch stop layer is in a range of about 300 to 800 Å thick and said second sub interlevel dielectric layer (少なくとも) is in a range of about 10K ű1K Å thick . |
JP2004146442A CLAIM 4 薄膜トランジスタにおけるシリコン酸化膜によるゲート絶縁膜と、前記ゲート絶縁膜上に形成されたシリコン窒化膜による第１層間絶縁膜部と、前記第１層間絶縁膜部上に形成された有機絶縁膜による第２層間絶縁膜部とをエッチングし、ソース・ドレイン領域に通じるコンタクトホールを形成する工程を有する薄膜トランジスタの製造方法において、 前記第２層間絶縁膜部及び前記第１層間絶縁膜部に第１のホールを形成する第１のエッチング工程と、 前記ゲート絶縁膜に、前記第１のホールに連通し、この第１のホールとでコンタクトホールをなす、第２のホールを形成する第２のエッチング工程とを備え、 前記第１のエッチング工程では、炭素、フッ素、窒素ガスを少なくとも (second sub interlevel dielectric layer) 含んだ混合ガスでエッチングをし、前記第２のエッチング工程では、炭素、フッ素、水素ガスを少なくとも含んだ混合ガスでエッチングをする、 ことを特徴とする薄膜トランジスタの製造方法。 |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US6777305B2 Filed: 2002-09-11 Issued: 2004-08-17 Method for fabricating semiconductor device (Original Assignee) SK Hynix Inc (Current Assignee) SK Hynix Inc Kee-jeung Lee, Byung-Seop Hong |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (RF power) of said contact region ; and a multiple etch (doped polysilicon, hard mask, low rate) stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (contact hole, opening part, contact plug) layer (entire surface) over said first etch stop layer ; a second etch (doped polysilicon, hard mask, low rate) stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US6777305B2 CLAIM 1 . A method for fabricating a capacitor , comprising : forming a first insulating film on a semiconductor substrate ; forming a contact plug (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) through the first insulating film ; sequentially forming an etch barrier film and a second insulating film upon the first insulating film ; sequentially etching the second insulating film and the etch barrier film to form an opening part (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) so as to expose the contact plug ; forming a conductive film on the second insulating film and on the opening part ; selectively etching the conductive film , wherein the conductive film is over-etched relative to the second insulating film , so as to form a storage node within the opening part ; forming prominences on a surface of the storage node ; and sequentially forming a dielectric film and a plate node upon the storage node and the second insulating film . US6777305B2 CLAIM 3 . The method as claimed in claim 1 , wherein forming the opening part comprises : forming a hard mask (etching process, multiple etch, second etch, etch process, second etch stop layers) on the second insulating film ; forming a second mask on the hard mask ; etching the hard mask and the second insulating film by using the second mask as an etch mask so as to make the etching stop at the etch barrier film ; removing the second mask ; etching the etch barrier film by using the hard mask as an etch mask ; and carrying out a plasma treatment on a top of the contact plug , the top of the contact plug having been exposed upon etching the etch barrier film . US6777305B2 CLAIM 4 . The method as claimed in claim 3 , wherein the hard mask is formed to a thickness ranging from 500 Å to 2000 Å by using doped or undoped polysilicon (etching process, multiple etch, second etch, etch process, second etch stop layers) . US6777305B2 CLAIM 7 . The method as claimed in claim 5 , wherein during doping the phosphorus , a thermal doping is performed under a 1% to 5% PH 3 /N 2 or PH 3 /He gas atmosphere having a flow rate (etching process, multiple etch, second etch, etch process, second etch stop layers) ranging from 50 sccm to 2000 sccm . US6777305B2 CLAIM 10 . The method as claimed in claim 5 , wherein at the step of doping the phosphorus , a plasma glow discharge is performed for 30 to 120 seconds with an RF power (metal layer coupling area) ranging from 100 W to 500 W under a PH 3 atmosphere within a chamber . US6777305B2 CLAIM 15 . A method for fabricating a semiconductor device , comprising : forming a first insulating film on a semiconductor substrate ; forming a plurality of bit lines on the first insulating film ; forming a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) through the first insulating film between the bit lines reaching the semiconductor substrate ; forming a spacer on a sidewall of the contact hole ; forming a first contact plug , the first contact plug being buried into the contact hole reaching the semiconductor substrate ; sequentially forming an etch barrier film and a second insulating film on the first insulating film and on the first contact plug ; sequentially etching the second insulating film and the etch barrier film to form an opening part so as to expose the first contact plug ; forming a first conductive film on an entire surface (first sub interlevel dielectric layer) including the opening part ; selectively etching the first conductive film , with the first conductive film being over-etched relative to the second insulating film , so as to form a storage node within the opening part ; and sequentially forming a dielectric film and a plate node upon the storage node . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer protects removal of a substrate material by an etch process (doped polysilicon, hard mask, low rate) . |
US6777305B2 CLAIM 3 . The method as claimed in claim 1 , wherein forming the opening part comprises : forming a hard mask (etching process, multiple etch, second etch, etch process, second etch stop layers) on the second insulating film ; forming a second mask on the hard mask ; etching the hard mask and the second insulating film by using the second mask as an etch mask so as to make the etching stop at the etch barrier film ; removing the second mask ; etching the etch barrier film by using the hard mask as an etch mask ; and carrying out a plasma treatment on a top of the contact plug , the top of the contact plug having been exposed upon etching the etch barrier film . US6777305B2 CLAIM 4 . The method as claimed in claim 3 , wherein the hard mask is formed to a thickness ranging from 500 Å to 2000 Å by using doped or undoped polysilicon (etching process, multiple etch, second etch, etch process, second etch stop layers) . US6777305B2 CLAIM 7 . The method as claimed in claim 5 , wherein during doping the phosphorus , a thermal doping is performed under a 1% to 5% PH 3 /N 2 or PH 3 /He gas atmosphere having a flow rate (etching process, multiple etch, second etch, etch process, second etch stop layers) ranging from 50 sccm to 2000 sccm . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (contact hole, opening part, contact plug) layer (entire surface) insulates said contact region . |
US6777305B2 CLAIM 1 . A method for fabricating a capacitor , comprising : forming a first insulating film on a semiconductor substrate ; forming a contact plug (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) through the first insulating film ; sequentially forming an etch barrier film and a second insulating film upon the first insulating film ; sequentially etching the second insulating film and the etch barrier film to form an opening part (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) so as to expose the contact plug ; forming a conductive film on the second insulating film and on the opening part ; selectively etching the conductive film , wherein the conductive film is over-etched relative to the second insulating film , so as to form a storage node within the opening part ; forming prominences on a surface of the storage node ; and sequentially forming a dielectric film and a plate node upon the storage node and the second insulating film . US6777305B2 CLAIM 15 . A method for fabricating a semiconductor device , comprising : forming a first insulating film on a semiconductor substrate ; forming a plurality of bit lines on the first insulating film ; forming a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) through the first insulating film between the bit lines reaching the semiconductor substrate ; forming a spacer on a sidewall of the contact hole ; forming a first contact plug , the first contact plug being buried into the contact hole reaching the semiconductor substrate ; sequentially forming an etch barrier film and a second insulating film on the first insulating film and on the first contact plug ; sequentially etching the second insulating film and the etch barrier film to form an opening part so as to expose the first contact plug ; forming a first conductive film on an entire surface (first sub interlevel dielectric layer) including the opening part ; selectively etching the first conductive film , with the first conductive film being over-etched relative to the second insulating film , so as to form a storage node within the opening part ; and sequentially forming a dielectric film and a plate node upon the storage node . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch (doped polysilicon, hard mask, low rate) stop layer protects lower layers during an etching process (doped polysilicon, hard mask, low rate) . |
US6777305B2 CLAIM 3 . The method as claimed in claim 1 , wherein forming the opening part comprises : forming a hard mask (etching process, multiple etch, second etch, etch process, second etch stop layers) on the second insulating film ; forming a second mask on the hard mask ; etching the hard mask and the second insulating film by using the second mask as an etch mask so as to make the etching stop at the etch barrier film ; removing the second mask ; etching the etch barrier film by using the hard mask as an etch mask ; and carrying out a plasma treatment on a top of the contact plug , the top of the contact plug having been exposed upon etching the etch barrier film . US6777305B2 CLAIM 4 . The method as claimed in claim 3 , wherein the hard mask is formed to a thickness ranging from 500 Å to 2000 Å by using doped or undoped polysilicon (etching process, multiple etch, second etch, etch process, second etch stop layers) . US6777305B2 CLAIM 7 . The method as claimed in claim 5 , wherein during doping the phosphorus , a thermal doping is performed under a 1% to 5% PH 3 /N 2 or PH 3 /He gas atmosphere having a flow rate (etching process, multiple etch, second etch, etch process, second etch stop layers) ranging from 50 sccm to 2000 sccm . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (contact hole, opening part, contact plug) layer insulates said contact region . |
US6777305B2 CLAIM 1 . A method for fabricating a capacitor , comprising : forming a first insulating film on a semiconductor substrate ; forming a contact plug (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) through the first insulating film ; sequentially forming an etch barrier film and a second insulating film upon the first insulating film ; sequentially etching the second insulating film and the etch barrier film to form an opening part (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) so as to expose the contact plug ; forming a conductive film on the second insulating film and on the opening part ; selectively etching the conductive film , wherein the conductive film is over-etched relative to the second insulating film , so as to form a storage node within the opening part ; forming prominences on a surface of the storage node ; and sequentially forming a dielectric film and a plate node upon the storage node and the second insulating film . US6777305B2 CLAIM 15 . A method for fabricating a semiconductor device , comprising : forming a first insulating film on a semiconductor substrate ; forming a plurality of bit lines on the first insulating film ; forming a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) through the first insulating film between the bit lines reaching the semiconductor substrate ; forming a spacer on a sidewall of the contact hole ; forming a first contact plug , the first contact plug being buried into the contact hole reaching the semiconductor substrate ; sequentially forming an etch barrier film and a second insulating film on the first insulating film and on the first contact plug ; sequentially etching the second insulating film and the etch barrier film to form an opening part so as to expose the first contact plug ; forming a first conductive film on an entire surface including the opening part ; selectively etching the first conductive film , with the first conductive film being over-etched relative to the second insulating film , so as to form a storage node within the opening part ; and sequentially forming a dielectric film and a plate node upon the storage node . |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area of said contact region permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area (RF power) of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
US6777305B2 CLAIM 10 . The method as claimed in claim 5 , wherein at the step of doping the phosphorus , a plasma glow discharge is performed for 30 to 120 seconds with an RF power (metal layer coupling area) ranging from 100 W to 500 W under a PH 3 atmosphere within a chamber . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (contact hole, opening part, contact plug) layer (entire surface) is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (doped polysilicon, hard mask, low rate) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6777305B2 CLAIM 1 . A method for fabricating a capacitor , comprising : forming a first insulating film on a semiconductor substrate ; forming a contact plug (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) through the first insulating film ; sequentially forming an etch barrier film and a second insulating film upon the first insulating film ; sequentially etching the second insulating film and the etch barrier film to form an opening part (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) so as to expose the contact plug ; forming a conductive film on the second insulating film and on the opening part ; selectively etching the conductive film , wherein the conductive film is over-etched relative to the second insulating film , so as to form a storage node within the opening part ; forming prominences on a surface of the storage node ; and sequentially forming a dielectric film and a plate node upon the storage node and the second insulating film . US6777305B2 CLAIM 3 . The method as claimed in claim 1 , wherein forming the opening part comprises : forming a hard mask (etching process, multiple etch, second etch, etch process, second etch stop layers) on the second insulating film ; forming a second mask on the hard mask ; etching the hard mask and the second insulating film by using the second mask as an etch mask so as to make the etching stop at the etch barrier film ; removing the second mask ; etching the etch barrier film by using the hard mask as an etch mask ; and carrying out a plasma treatment on a top of the contact plug , the top of the contact plug having been exposed upon etching the etch barrier film . US6777305B2 CLAIM 4 . The method as claimed in claim 3 , wherein the hard mask is formed to a thickness ranging from 500 Å to 2000 Å by using doped or undoped polysilicon (etching process, multiple etch, second etch, etch process, second etch stop layers) . US6777305B2 CLAIM 7 . The method as claimed in claim 5 , wherein during doping the phosphorus , a thermal doping is performed under a 1% to 5% PH 3 /N 2 or PH 3 /He gas atmosphere having a flow rate (etching process, multiple etch, second etch, etch process, second etch stop layers) ranging from 50 sccm to 2000 sccm . US6777305B2 CLAIM 15 . A method for fabricating a semiconductor device , comprising : forming a first insulating film on a semiconductor substrate ; forming a plurality of bit lines on the first insulating film ; forming a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) through the first insulating film between the bit lines reaching the semiconductor substrate ; forming a spacer on a sidewall of the contact hole ; forming a first contact plug , the first contact plug being buried into the contact hole reaching the semiconductor substrate ; sequentially forming an etch barrier film and a second insulating film on the first insulating film and on the first contact plug ; sequentially etching the second insulating film and the etch barrier film to form an opening part so as to expose the first contact plug ; forming a first conductive film on an entire surface (first sub interlevel dielectric layer) including the opening part ; selectively etching the first conductive film , with the first conductive film being over-etched relative to the second insulating film , so as to form a storage node within the opening part ; and sequentially forming a dielectric film and a plate node upon the storage node . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric (contact hole, opening part, contact plug) layer (entire surface) for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US6777305B2 CLAIM 1 . A method for fabricating a capacitor , comprising : forming a first insulating film on a semiconductor substrate ; forming a contact plug (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) through the first insulating film ; sequentially forming an etch barrier film and a second insulating film upon the first insulating film ; sequentially etching the second insulating film and the etch barrier film to form an opening part (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) so as to expose the contact plug ; forming a conductive film on the second insulating film and on the opening part ; selectively etching the conductive film , wherein the conductive film is over-etched relative to the second insulating film , so as to form a storage node within the opening part ; forming prominences on a surface of the storage node ; and sequentially forming a dielectric film and a plate node upon the storage node and the second insulating film . US6777305B2 CLAIM 15 . A method for fabricating a semiconductor device , comprising : forming a first insulating film on a semiconductor substrate ; forming a plurality of bit lines on the first insulating film ; forming a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) through the first insulating film between the bit lines reaching the semiconductor substrate ; forming a spacer on a sidewall of the contact hole ; forming a first contact plug , the first contact plug being buried into the contact hole reaching the semiconductor substrate ; sequentially forming an etch barrier film and a second insulating film on the first insulating film and on the first contact plug ; sequentially etching the second insulating film and the etch barrier film to form an opening part so as to expose the first contact plug ; forming a first conductive film on an entire surface (first sub interlevel dielectric layer) including the opening part ; selectively etching the first conductive film , with the first conductive film being over-etched relative to the second insulating film , so as to form a storage node within the opening part ; and sequentially forming a dielectric film and a plate node upon the storage node . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch (doped polysilicon, hard mask, low rate) stop insulation layer comprising a first etch stop layer and a second etch (doped polysilicon, hard mask, low rate) stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (contact hole, opening part, contact plug) layer (entire surface) and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (RF power) of said contact region . |
US6777305B2 CLAIM 1 . A method for fabricating a capacitor , comprising : forming a first insulating film on a semiconductor substrate ; forming a contact plug (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) through the first insulating film ; sequentially forming an etch barrier film and a second insulating film upon the first insulating film ; sequentially etching the second insulating film and the etch barrier film to form an opening part (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) so as to expose the contact plug ; forming a conductive film on the second insulating film and on the opening part ; selectively etching the conductive film , wherein the conductive film is over-etched relative to the second insulating film , so as to form a storage node within the opening part ; forming prominences on a surface of the storage node ; and sequentially forming a dielectric film and a plate node upon the storage node and the second insulating film . US6777305B2 CLAIM 3 . The method as claimed in claim 1 , wherein forming the opening part comprises : forming a hard mask (etching process, multiple etch, second etch, etch process, second etch stop layers) on the second insulating film ; forming a second mask on the hard mask ; etching the hard mask and the second insulating film by using the second mask as an etch mask so as to make the etching stop at the etch barrier film ; removing the second mask ; etching the etch barrier film by using the hard mask as an etch mask ; and carrying out a plasma treatment on a top of the contact plug , the top of the contact plug having been exposed upon etching the etch barrier film . US6777305B2 CLAIM 4 . The method as claimed in claim 3 , wherein the hard mask is formed to a thickness ranging from 500 Å to 2000 Å by using doped or undoped polysilicon (etching process, multiple etch, second etch, etch process, second etch stop layers) . US6777305B2 CLAIM 7 . The method as claimed in claim 5 , wherein during doping the phosphorus , a thermal doping is performed under a 1% to 5% PH 3 /N 2 or PH 3 /He gas atmosphere having a flow rate (etching process, multiple etch, second etch, etch process, second etch stop layers) ranging from 50 sccm to 2000 sccm . US6777305B2 CLAIM 10 . The method as claimed in claim 5 , wherein at the step of doping the phosphorus , a plasma glow discharge is performed for 30 to 120 seconds with an RF power (metal layer coupling area) ranging from 100 W to 500 W under a PH 3 atmosphere within a chamber . US6777305B2 CLAIM 15 . A method for fabricating a semiconductor device , comprising : forming a first insulating film on a semiconductor substrate ; forming a plurality of bit lines on the first insulating film ; forming a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) through the first insulating film between the bit lines reaching the semiconductor substrate ; forming a spacer on a sidewall of the contact hole ; forming a first contact plug , the first contact plug being buried into the contact hole reaching the semiconductor substrate ; sequentially forming an etch barrier film and a second insulating film on the first insulating film and on the first contact plug ; sequentially etching the second insulating film and the etch barrier film to form an opening part so as to expose the first contact plug ; forming a first conductive film on an entire surface (first sub interlevel dielectric layer) including the opening part ; selectively etching the first conductive film , with the first conductive film being over-etched relative to the second insulating film , so as to form a storage node within the opening part ; and sequentially forming a dielectric film and a plate node upon the storage node . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (contact hole, opening part, contact plug) layer (entire surface) is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (doped polysilicon, hard mask, low rate) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6777305B2 CLAIM 1 . A method for fabricating a capacitor , comprising : forming a first insulating film on a semiconductor substrate ; forming a contact plug (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) through the first insulating film ; sequentially forming an etch barrier film and a second insulating film upon the first insulating film ; sequentially etching the second insulating film and the etch barrier film to form an opening part (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) so as to expose the contact plug ; forming a conductive film on the second insulating film and on the opening part ; selectively etching the conductive film , wherein the conductive film is over-etched relative to the second insulating film , so as to form a storage node within the opening part ; forming prominences on a surface of the storage node ; and sequentially forming a dielectric film and a plate node upon the storage node and the second insulating film . US6777305B2 CLAIM 3 . The method as claimed in claim 1 , wherein forming the opening part comprises : forming a hard mask (etching process, multiple etch, second etch, etch process, second etch stop layers) on the second insulating film ; forming a second mask on the hard mask ; etching the hard mask and the second insulating film by using the second mask as an etch mask so as to make the etching stop at the etch barrier film ; removing the second mask ; etching the etch barrier film by using the hard mask as an etch mask ; and carrying out a plasma treatment on a top of the contact plug , the top of the contact plug having been exposed upon etching the etch barrier film . US6777305B2 CLAIM 4 . The method as claimed in claim 3 , wherein the hard mask is formed to a thickness ranging from 500 Å to 2000 Å by using doped or undoped polysilicon (etching process, multiple etch, second etch, etch process, second etch stop layers) . US6777305B2 CLAIM 7 . The method as claimed in claim 5 , wherein during doping the phosphorus , a thermal doping is performed under a 1% to 5% PH 3 /N 2 or PH 3 /He gas atmosphere having a flow rate (etching process, multiple etch, second etch, etch process, second etch stop layers) ranging from 50 sccm to 2000 sccm . US6777305B2 CLAIM 15 . A method for fabricating a semiconductor device , comprising : forming a first insulating film on a semiconductor substrate ; forming a plurality of bit lines on the first insulating film ; forming a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) through the first insulating film between the bit lines reaching the semiconductor substrate ; forming a spacer on a sidewall of the contact hole ; forming a first contact plug , the first contact plug being buried into the contact hole reaching the semiconductor substrate ; sequentially forming an etch barrier film and a second insulating film on the first insulating film and on the first contact plug ; sequentially etching the second insulating film and the etch barrier film to form an opening part so as to expose the first contact plug ; forming a first conductive film on an entire surface (first sub interlevel dielectric layer) including the opening part ; selectively etching the first conductive film , with the first conductive film being over-etched relative to the second insulating film , so as to form a storage node within the opening part ; and sequentially forming a dielectric film and a plate node upon the storage node . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US6737310B2 Filed: 2002-09-06 Issued: 2004-05-18 Self-aligned process for a stacked gate RF MOSFET device (Original Assignee) Taiwan Semiconductor Manufacturing Co TSMC Ltd (Current Assignee) Taiwan Semiconductor Manufacturing Co TSMC Ltd Chaochieh Tsai, Chung-Long Chang, Jui-Yu Chang, Shyh-Chyi Wong |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region (interlevel dielectric, first interlevel, contact hole) such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (interlevel dielectric, first interlevel, contact hole) layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US6737310B2 CLAIM 1 . A method of forming a metal oxide semiconductor field effect transistor (MOSFET) , device , on a semiconductor substrate , comprising the steps of : forming a gate structure on an underlying gate insulator layer , on a portion of said semiconductor substrate used as an active device region of said semiconductor substrate , comprised with insulator spacers on the sides of said gate structure , comprised with a source/drain region in an area of said active device region of said semiconductor substrate not covered by said gate structure , and comprised with metal silicide formed on the top surface of said gate structure , and on the top surface of said source/drain region ; depositing a first interlevel dielectric (interlevel dielectric, spacer region, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) (ILD) layer ; depositing a silicon nitride layer ; forming an opening in said silicon nitride layer , with said opening exposing a portion of said first ILD layer in a region in which said first ILD layer overlays the top surface of said gate structure , in a region in which said gate structure overlays a portion of said active device region of said semiconductor substrate ; depositing a second ILD layer ; forming contact hole (interlevel dielectric, spacer region, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) openings in said second ILD layer , in said silicon nitride layer , and in said first ILD layer , to expose portions of said source/drain region ; forming a dual damascene type opening in said second ILD , and in a top portion of said first ILD layer , exposing a portion of the top surface of said gate structure , in a region in which said gate structure is located overlying said active device region of said semiconductor substrate , with said dual damascene opening comprised with a wide opening in said second ILD layer , and comprised with a narrow opening in said first ILD layer , formed using said opening in said silicon nitride layer as a mask ; forming metal contact structures in said contact hole openings , and forming a metal gate contact structure in said dual damascene opening ; and forming lower level metal interconnect structures , with a first lower level metal interconnect structure overlying and contacting said metal gate contact structure , and with a second lower level metal interconnect structures , overlying and contacting a metal contact structure . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer protects removal of a substrate material by an etch process (silicon oxide layer) . |
US6737310B2 CLAIM 7 . The method of claim 1 , wherein said first ILD layer , is a silicon oxide layer (etch process) , obtained via LPCVD or PECVD procedures , at a thickness between about 2500 to 3500 Angstroms . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (interlevel dielectric, first interlevel, contact hole) layer insulates said contact region . |
US6737310B2 CLAIM 1 . A method of forming a metal oxide semiconductor field effect transistor (MOSFET) , device , on a semiconductor substrate , comprising the steps of : forming a gate structure on an underlying gate insulator layer , on a portion of said semiconductor substrate used as an active device region of said semiconductor substrate , comprised with insulator spacers on the sides of said gate structure , comprised with a source/drain region in an area of said active device region of said semiconductor substrate not covered by said gate structure , and comprised with metal silicide formed on the top surface of said gate structure , and on the top surface of said source/drain region ; depositing a first interlevel dielectric (interlevel dielectric, spacer region, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) (ILD) layer ; depositing a silicon nitride layer ; forming an opening in said silicon nitride layer , with said opening exposing a portion of said first ILD layer in a region in which said first ILD layer overlays the top surface of said gate structure , in a region in which said gate structure overlays a portion of said active device region of said semiconductor substrate ; depositing a second ILD layer ; forming contact hole (interlevel dielectric, spacer region, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) openings in said second ILD layer , in said silicon nitride layer , and in said first ILD layer , to expose portions of said source/drain region ; forming a dual damascene type opening in said second ILD , and in a top portion of said first ILD layer , exposing a portion of the top surface of said gate structure , in a region in which said gate structure is located overlying said active device region of said semiconductor substrate , with said dual damascene opening comprised with a wide opening in said second ILD layer , and comprised with a narrow opening in said first ILD layer , formed using said opening in said silicon nitride layer as a mask ; forming metal contact structures in said contact hole openings , and forming a metal gate contact structure in said dual damascene opening ; and forming lower level metal interconnect structures , with a first lower level metal interconnect structure overlying and contacting said metal gate contact structure , and with a second lower level metal interconnect structures , overlying and contacting a metal contact structure . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (interlevel dielectric, first interlevel, contact hole) layer insulates said contact region . |
US6737310B2 CLAIM 1 . A method of forming a metal oxide semiconductor field effect transistor (MOSFET) , device , on a semiconductor substrate , comprising the steps of : forming a gate structure on an underlying gate insulator layer , on a portion of said semiconductor substrate used as an active device region of said semiconductor substrate , comprised with insulator spacers on the sides of said gate structure , comprised with a source/drain region in an area of said active device region of said semiconductor substrate not covered by said gate structure , and comprised with metal silicide formed on the top surface of said gate structure , and on the top surface of said source/drain region ; depositing a first interlevel dielectric (interlevel dielectric, spacer region, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) (ILD) layer ; depositing a silicon nitride layer ; forming an opening in said silicon nitride layer , with said opening exposing a portion of said first ILD layer in a region in which said first ILD layer overlays the top surface of said gate structure , in a region in which said gate structure overlays a portion of said active device region of said semiconductor substrate ; depositing a second ILD layer ; forming contact hole (interlevel dielectric, spacer region, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) openings in said second ILD layer , in said silicon nitride layer , and in said first ILD layer , to expose portions of said source/drain region ; forming a dual damascene type opening in said second ILD , and in a top portion of said first ILD layer , exposing a portion of the top surface of said gate structure , in a region in which said gate structure is located overlying said active device region of said semiconductor substrate , with said dual damascene opening comprised with a wide opening in said second ILD layer , and comprised with a narrow opening in said first ILD layer , formed using said opening in said silicon nitride layer as a mask ; forming metal contact structures in said contact hole openings , and forming a metal gate contact structure in said dual damascene opening ; and forming lower level metal interconnect structures , with a first lower level metal interconnect structure overlying and contacting said metal gate contact structure , and with a second lower level metal interconnect structures , overlying and contacting a metal contact structure . |
| US7977797B2 CLAIM 6 . An integrated circuit of claim 1 wherein said spacer region (interlevel dielectric, first interlevel, contact hole) insulates said contact region . |
US6737310B2 CLAIM 1 . A method of forming a metal oxide semiconductor field effect transistor (MOSFET) , device , on a semiconductor substrate , comprising the steps of : forming a gate structure on an underlying gate insulator layer , on a portion of said semiconductor substrate used as an active device region of said semiconductor substrate , comprised with insulator spacers on the sides of said gate structure , comprised with a source/drain region in an area of said active device region of said semiconductor substrate not covered by said gate structure , and comprised with metal silicide formed on the top surface of said gate structure , and on the top surface of said source/drain region ; depositing a first interlevel dielectric (interlevel dielectric, spacer region, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) (ILD) layer ; depositing a silicon nitride layer ; forming an opening in said silicon nitride layer , with said opening exposing a portion of said first ILD layer in a region in which said first ILD layer overlays the top surface of said gate structure , in a region in which said gate structure overlays a portion of said active device region of said semiconductor substrate ; depositing a second ILD layer ; forming contact hole (interlevel dielectric, spacer region, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) openings in said second ILD layer , in said silicon nitride layer , and in said first ILD layer , to expose portions of said source/drain region ; forming a dual damascene type opening in said second ILD , and in a top portion of said first ILD layer , exposing a portion of the top surface of said gate structure , in a region in which said gate structure is located overlying said active device region of said semiconductor substrate , with said dual damascene opening comprised with a wide opening in said second ILD layer , and comprised with a narrow opening in said first ILD layer , formed using said opening in said silicon nitride layer as a mask ; forming metal contact structures in said contact hole openings , and forming a metal gate contact structure in said dual damascene opening ; and forming lower level metal interconnect structures , with a first lower level metal interconnect structure overlying and contacting said metal gate contact structure , and with a second lower level metal interconnect structures , overlying and contacting a metal contact structure . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (interlevel dielectric, first interlevel, contact hole) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6737310B2 CLAIM 1 . A method of forming a metal oxide semiconductor field effect transistor (MOSFET) , device , on a semiconductor substrate , comprising the steps of : forming a gate structure on an underlying gate insulator layer , on a portion of said semiconductor substrate used as an active device region of said semiconductor substrate , comprised with insulator spacers on the sides of said gate structure , comprised with a source/drain region in an area of said active device region of said semiconductor substrate not covered by said gate structure , and comprised with metal silicide formed on the top surface of said gate structure , and on the top surface of said source/drain region ; depositing a first interlevel dielectric (interlevel dielectric, spacer region, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) (ILD) layer ; depositing a silicon nitride layer ; forming an opening in said silicon nitride layer , with said opening exposing a portion of said first ILD layer in a region in which said first ILD layer overlays the top surface of said gate structure , in a region in which said gate structure overlays a portion of said active device region of said semiconductor substrate ; depositing a second ILD layer ; forming contact hole (interlevel dielectric, spacer region, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) openings in said second ILD layer , in said silicon nitride layer , and in said first ILD layer , to expose portions of said source/drain region ; forming a dual damascene type opening in said second ILD , and in a top portion of said first ILD layer , exposing a portion of the top surface of said gate structure , in a region in which said gate structure is located overlying said active device region of said semiconductor substrate , with said dual damascene opening comprised with a wide opening in said second ILD layer , and comprised with a narrow opening in said first ILD layer , formed using said opening in said silicon nitride layer as a mask ; forming metal contact structures in said contact hole openings , and forming a metal gate contact structure in said dual damascene opening ; and forming lower level metal interconnect structures , with a first lower level metal interconnect structure overlying and contacting said metal gate contact structure , and with a second lower level metal interconnect structures , overlying and contacting a metal contact structure . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric (interlevel dielectric, first interlevel, contact hole) layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US6737310B2 CLAIM 1 . A method of forming a metal oxide semiconductor field effect transistor (MOSFET) , device , on a semiconductor substrate , comprising the steps of : forming a gate structure on an underlying gate insulator layer , on a portion of said semiconductor substrate used as an active device region of said semiconductor substrate , comprised with insulator spacers on the sides of said gate structure , comprised with a source/drain region in an area of said active device region of said semiconductor substrate not covered by said gate structure , and comprised with metal silicide formed on the top surface of said gate structure , and on the top surface of said source/drain region ; depositing a first interlevel dielectric (interlevel dielectric, spacer region, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) (ILD) layer ; depositing a silicon nitride layer ; forming an opening in said silicon nitride layer , with said opening exposing a portion of said first ILD layer in a region in which said first ILD layer overlays the top surface of said gate structure , in a region in which said gate structure overlays a portion of said active device region of said semiconductor substrate ; depositing a second ILD layer ; forming contact hole (interlevel dielectric, spacer region, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) openings in said second ILD layer , in said silicon nitride layer , and in said first ILD layer , to expose portions of said source/drain region ; forming a dual damascene type opening in said second ILD , and in a top portion of said first ILD layer , exposing a portion of the top surface of said gate structure , in a region in which said gate structure is located overlying said active device region of said semiconductor substrate , with said dual damascene opening comprised with a wide opening in said second ILD layer , and comprised with a narrow opening in said first ILD layer , formed using said opening in said silicon nitride layer as a mask ; forming metal contact structures in said contact hole openings , and forming a metal gate contact structure in said dual damascene opening ; and forming lower level metal interconnect structures , with a first lower level metal interconnect structure overlying and contacting said metal gate contact structure , and with a second lower level metal interconnect structures , overlying and contacting a metal contact structure . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US6737310B2 CLAIM 1 . A method of forming a metal oxide semiconductor field effect transistor (MOSFET) , device , on a semiconductor substrate , comprising the steps of : forming a gate structure on an underlying gate insulator layer , on a portion of said semiconductor substrate used as an active device region of said semiconductor substrate , comprised with insulator spacers on the sides of said gate structure , comprised with a source/drain region in an area of said active device region of said semiconductor substrate not covered by said gate structure , and comprised with metal silicide formed on the top surface of said gate structure , and on the top surface of said source/drain region ; depositing a first interlevel dielectric (ILD) layer ; depositing a silicon nitride layer ; forming an opening in said silicon nitride layer , with said opening exposing a portion of said first ILD layer in a region in which said first ILD layer overlays the top surface of said gate structure , in a region in which said gate structure overlays a portion of said active device region of said semiconductor substrate ; depositing a second ILD layer ; forming contact hole openings in said second ILD layer , in said silicon nitride layer , and in said first ILD layer , to expose portions of said source/drain region ; forming a dual damascene type opening in said second ILD , and in a top portion of said first ILD layer , exposing a portion of the top surface of said gate structure , in a region in which said gate structure is located overlying said active device region of said semiconductor substrate , with said dual damascene opening comprised with a wide opening in said second ILD layer , and comprised with a narrow opening in said first ILD layer , formed using said opening in said silicon nitride layer as a mask ; forming metal contact structures in said contact hole openings , and forming (anti reflective coating) a metal gate contact structure in said dual damascene opening ; and forming lower level metal interconnect structures , with a first lower level metal interconnect structure overlying and contacting said metal gate contact structure , and with a second lower level metal interconnect structures , overlying and contacting a metal contact structure . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers (silicon nitride layer) have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (interlevel dielectric, first interlevel, contact hole) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom (top portion) , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US6737310B2 CLAIM 1 . A method of forming a metal oxide semiconductor field effect transistor (MOSFET) , device , on a semiconductor substrate , comprising the steps of : forming a gate structure on an underlying gate insulator layer , on a portion of said semiconductor substrate used as an active device region of said semiconductor substrate , comprised with insulator spacers on the sides of said gate structure , comprised with a source/drain region in an area of said active device region of said semiconductor substrate not covered by said gate structure , and comprised with metal silicide formed on the top surface of said gate structure , and on the top surface of said source/drain region ; depositing a first interlevel dielectric (interlevel dielectric, spacer region, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) (ILD) layer ; depositing a silicon nitride layer (second etch stop layers) ; forming an opening in said silicon nitride layer , with said opening exposing a portion of said first ILD layer in a region in which said first ILD layer overlays the top surface of said gate structure , in a region in which said gate structure overlays a portion of said active device region of said semiconductor substrate ; depositing a second ILD layer ; forming contact hole (interlevel dielectric, spacer region, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) openings in said second ILD layer , in said silicon nitride layer , and in said first ILD layer , to expose portions of said source/drain region ; forming a dual damascene type opening in said second ILD , and in a top portion (contact bottom) of said first ILD layer , exposing a portion of the top surface of said gate structure , in a region in which said gate structure is located overlying said active device region of said semiconductor substrate , with said dual damascene opening comprised with a wide opening in said second ILD layer , and comprised with a narrow opening in said first ILD layer , formed using said opening in said silicon nitride layer as a mask ; forming metal contact structures in said contact hole openings , and forming a metal gate contact structure in said dual damascene opening ; and forming lower level metal interconnect structures , with a first lower level metal interconnect structure overlying and contacting said metal gate contact structure , and with a second lower level metal interconnect structures , overlying and contacting a metal contact structure . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (interlevel dielectric, first interlevel, contact hole) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6737310B2 CLAIM 1 . A method of forming a metal oxide semiconductor field effect transistor (MOSFET) , device , on a semiconductor substrate , comprising the steps of : forming a gate structure on an underlying gate insulator layer , on a portion of said semiconductor substrate used as an active device region of said semiconductor substrate , comprised with insulator spacers on the sides of said gate structure , comprised with a source/drain region in an area of said active device region of said semiconductor substrate not covered by said gate structure , and comprised with metal silicide formed on the top surface of said gate structure , and on the top surface of said source/drain region ; depositing a first interlevel dielectric (interlevel dielectric, spacer region, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) (ILD) layer ; depositing a silicon nitride layer ; forming an opening in said silicon nitride layer , with said opening exposing a portion of said first ILD layer in a region in which said first ILD layer overlays the top surface of said gate structure , in a region in which said gate structure overlays a portion of said active device region of said semiconductor substrate ; depositing a second ILD layer ; forming contact hole (interlevel dielectric, spacer region, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) openings in said second ILD layer , in said silicon nitride layer , and in said first ILD layer , to expose portions of said source/drain region ; forming a dual damascene type opening in said second ILD , and in a top portion of said first ILD layer , exposing a portion of the top surface of said gate structure , in a region in which said gate structure is located overlying said active device region of said semiconductor substrate , with said dual damascene opening comprised with a wide opening in said second ILD layer , and comprised with a narrow opening in said first ILD layer , formed using said opening in said silicon nitride layer as a mask ; forming metal contact structures in said contact hole openings , and forming a metal gate contact structure in said dual damascene opening ; and forming lower level metal interconnect structures , with a first lower level metal interconnect structure overlying and contacting said metal gate contact structure , and with a second lower level metal interconnect structures , overlying and contacting a metal contact structure . |
| US7977797B2 CLAIM 13 . An integrated circuit of claim 11 further comprising a floating gate (drain region) . |
US6737310B2 CLAIM 1 . A method of forming a metal oxide semiconductor field effect transistor (MOSFET) , device , on a semiconductor substrate , comprising the steps of : forming a gate structure on an underlying gate insulator layer , on a portion of said semiconductor substrate used as an active device region of said semiconductor substrate , comprised with insulator spacers on the sides of said gate structure , comprised with a source/drain region (floating gate) in an area of said active device region of said semiconductor substrate not covered by said gate structure , and comprised with metal silicide formed on the top surface of said gate structure , and on the top surface of said source/drain region ; depositing a first interlevel dielectric (ILD) layer ; depositing a silicon nitride layer ; forming an opening in said silicon nitride layer , with said opening exposing a portion of said first ILD layer in a region in which said first ILD layer overlays the top surface of said gate structure , in a region in which said gate structure overlays a portion of said active device region of said semiconductor substrate ; depositing a second ILD layer ; forming contact hole openings in said second ILD layer , in said silicon nitride layer , and in said first ILD layer , to expose portions of said source/drain region ; forming a dual damascene type opening in said second ILD , and in a top portion of said first ILD layer , exposing a portion of the top surface of said gate structure , in a region in which said gate structure is located overlying said active device region of said semiconductor substrate , with said dual damascene opening comprised with a wide opening in said second ILD layer , and comprised with a narrow opening in said first ILD layer , formed using said opening in said silicon nitride layer as a mask ; forming metal contact structures in said contact hole openings , and forming a metal gate contact structure in said dual damascene opening ; and forming lower level metal interconnect structures , with a first lower level metal interconnect structure overlying and contacting said metal gate contact structure , and with a second lower level metal interconnect structures , overlying and contacting a metal contact structure . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US6737310B2 CLAIM 1 . A method of forming a metal oxide semiconductor field effect transistor (MOSFET) , device , on a semiconductor substrate , comprising the steps of : forming a gate structure on an underlying gate insulator layer , on a portion of said semiconductor substrate used as an active device region of said semiconductor substrate , comprised with insulator spacers on the sides of said gate structure , comprised with a source/drain region in an area of said active device region of said semiconductor substrate not covered by said gate structure , and comprised with metal silicide formed on the top surface of said gate structure , and on the top surface of said source/drain region ; depositing a first interlevel dielectric (ILD) layer ; depositing a silicon nitride layer ; forming an opening in said silicon nitride layer , with said opening exposing a portion of said first ILD layer in a region in which said first ILD layer overlays the top surface of said gate structure , in a region in which said gate structure overlays a portion of said active device region of said semiconductor substrate ; depositing a second ILD layer ; forming contact hole openings in said second ILD layer , in said silicon nitride layer , and in said first ILD layer , to expose portions of said source/drain region ; forming a dual damascene type opening in said second ILD , and in a top portion of said first ILD layer , exposing a portion of the top surface of said gate structure , in a region in which said gate structure is located overlying said active device region of said semiconductor substrate , with said dual damascene opening comprised with a wide opening in said second ILD layer , and comprised with a narrow opening in said first ILD layer , formed using said opening in said silicon nitride layer as a mask ; forming metal contact structures in said contact hole openings , and forming (anti reflective coating) a metal gate contact structure in said dual damascene opening ; and forming lower level metal interconnect structures , with a first lower level metal interconnect structure overlying and contacting said metal gate contact structure , and with a second lower level metal interconnect structures , overlying and contacting a metal contact structure . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | JP2004047873A Filed: 2002-07-15 Issued: 2004-02-12 有機シロキサン共重合体膜、その製造方法、成長装置、ならびに該共重合体膜を用いた半導体装置 (Original Assignee) Nec Corp; 日本電気株式会社 Yoshihiro Hayashi, 林 喜宏 |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer (少なくとも) over said second etch stop layer . |
JP2004047873A CLAIM 1 複数種の有機シロキサンを構成ユニットとする有機シロキサン共重合体膜であって、 前記複数種の有機シロキサン由来の構成ユニットとして、 少なくとも (second sub interlevel dielectric layer) 、環状シロキサンを骨格とする第１の有機シロキサンと、直鎖状シロキサンを骨格とする第２の有機シロキサンとを含んでなり、 前記第１の有機シロキサンに対して、前記第２の有機シロキサンが複数個結合して、架橋構造を形成していることを特徴とする有機シロキサン共重合体膜。 |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer protects removal of a substrate material by an etch process (付ける工程と) . |
JP2004047873A CLAIM 5 基板上において、複数種の有機シロキサンを構成ユニットとする有機シロキサン共重合体膜を成長する方法であって、 前記有機シロキサン共重合体膜は、前記複数種の有機シロキサン由来の構成ユニットとして、 少なくとも、環状シロキサンを骨格とする第１の有機シロキサンと、直鎖状シロキサンを骨格とする第２の有機シロキサンとを含んでなり、 前記第１の有機シロキサンに対して、前記第２の有機シロキサンが複数個結合して、架橋構造を形成している共重合体膜であり、 少なくとも、 前記環状シロキサンを骨格とする第１の有機シロキサンモノマーを気化する工程と、 前記直鎖状シロキサンを骨格とする第２の有機シロキサンモノマーを気化する工程と、 気化された前記第１の有機シロキサンモノマーガスを所定の供給速度で供給する工程と、 気化された前記第２の有機シロキサンモノマーガスを所定の供給速度で供給する工程と、 供給される前記第１の有機シロキサンモノマーガスと前記第２の有機シロキサンモノマーガスとを混合して、混合ガスを構成する工程と、 前記混合ガスを減圧下の反応室に導入する工程と、 導入される前記混合ガスを、該反応室内に形成されたプラズマ雰囲気中を通過させた後、加熱される基板上に吹き付ける工程と (etch process) を有し、 基板上において、吹き付けられた前記混合ガス中に含まれる、前記第１の有機シロキサンモノマーと第２の有機シロキサンモノマーを反応させて、前記第１の有機シロキサンに対して、前記第２の有機シロキサンが複数個結合して、架橋構造を形成している共重合体膜の成長を行うことを特徴とする有機シロキサン共重合体膜の気相成長方法。 |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric layer (少なくとも) insulates said contact region . |
JP2004047873A CLAIM 1 複数種の有機シロキサンを構成ユニットとする有機シロキサン共重合体膜であって、 前記複数種の有機シロキサン由来の構成ユニットとして、 少なくとも (second sub interlevel dielectric layer) 、環状シロキサンを骨格とする第１の有機シロキサンと、直鎖状シロキサンを骨格とする第２の有機シロキサンとを含んでなり、 前記第１の有機シロキサンに対して、前記第２の有機シロキサンが複数個結合して、架橋構造を形成していることを特徴とする有機シロキサン共重合体膜。 |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Å thick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Å thick , said second etch stop layer is in a range of about 300 to 800 Å thick and said second sub interlevel dielectric layer (少なくとも) is in a range of about 10K ű1K Å thick . |
JP2004047873A CLAIM 1 複数種の有機シロキサンを構成ユニットとする有機シロキサン共重合体膜であって、 前記複数種の有機シロキサン由来の構成ユニットとして、 少なくとも (second sub interlevel dielectric layer) 、環状シロキサンを骨格とする第１の有機シロキサンと、直鎖状シロキサンを骨格とする第２の有機シロキサンとを含んでなり、 前記第１の有機シロキサンに対して、前記第２の有機シロキサンが複数個結合して、架橋構造を形成していることを特徴とする有機シロキサン共重合体膜。 |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer (少なくとも) for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
JP2004047873A CLAIM 1 複数種の有機シロキサンを構成ユニットとする有機シロキサン共重合体膜であって、 前記複数種の有機シロキサン由来の構成ユニットとして、 少なくとも (second sub interlevel dielectric layer) 、環状シロキサンを骨格とする第１の有機シロキサンと、直鎖状シロキサンを骨格とする第２の有機シロキサンとを含んでなり、 前記第１の有機シロキサンに対して、前記第２の有機シロキサンが複数個結合して、架橋構造を形成していることを特徴とする有機シロキサン共重合体膜。 |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer (少なくとも) and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
JP2004047873A CLAIM 1 複数種の有機シロキサンを構成ユニットとする有機シロキサン共重合体膜であって、 前記複数種の有機シロキサン由来の構成ユニットとして、 少なくとも (second sub interlevel dielectric layer) 、環状シロキサンを骨格とする第１の有機シロキサンと、直鎖状シロキサンを骨格とする第２の有機シロキサンとを含んでなり、 前記第１の有機シロキサンに対して、前記第２の有機シロキサンが複数個結合して、架橋構造を形成していることを特徴とする有機シロキサン共重合体膜。 |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Å thick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Å thick , said second etch stop layer is in a range of about 300 to 800 Å thick and said second sub interlevel dielectric layer (少なくとも) is in a range of about 10K ű1K Å thick . |
JP2004047873A CLAIM 1 複数種の有機シロキサンを構成ユニットとする有機シロキサン共重合体膜であって、 前記複数種の有機シロキサン由来の構成ユニットとして、 少なくとも (second sub interlevel dielectric layer) 、環状シロキサンを骨格とする第１の有機シロキサンと、直鎖状シロキサンを骨格とする第２の有機シロキサンとを含んでなり、 前記第１の有機シロキサンに対して、前記第２の有機シロキサンが複数個結合して、架橋構造を形成していることを特徴とする有機シロキサン共重合体膜。 |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | KR20040003948A Filed: 2002-07-05 Issued: 2004-01-13 반도체소자의 ｍｏｓ 트랜지스터 제조방법 (Original Assignee) 주식회사 하이닉스반도체 서문식 |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region (반도체소자의) coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region (산화막을) such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
KR20040003948A CLAIM 1 필드산화막이 형성된 실리콘기판 상에 랜딩플러그 영역이 형성되도록 절연막 패턴을 형성한 후 , 이를 마스크로 소오스/드레인 이온주입 공정을 진행하여 소오스/드레인 영역을 형성하는 단계와 ; 상기 랜딩플러그 영역에 국부적으로 산화막을 (spacer region) 형성하고 결과물 전체에 폴리를 증착한 후 , 산화막 상부에 제1스페이서를 형성하는 단계와 ; 상기 제1스페이서를 마스크로 과도식각하여 콘택홀을 형성하는 단계와 ; 상기 결과물 상에 도핑된 폴리실리콘을 증착하고 에치백 공정을 진행하여 제1 랜딩플러그폴리를 형성하는 단계와 ; 상기 결과물 상에 선택적으로 게이트산화막을 형성하고 , 게이트전극과 절연막이 순차적으로 적층된 게이트 패턴을 형성하는 단계와 ; 상기 게이트 패턴 측벽에 게이트 스페이서를 형성하고 감광막 패턴을 형성한 후 , 감광막 패턴과 게이트 스페이서를 마스크로 노출된 게이트산화막을 제거하는 단계와 ; 상기 결과물 상에 도핑된 폴리실리콘을 증착하여 제 2랜딩플러그폴리를 형성하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체소자의 (contact region) MOS 트랜지스터 제조방법 . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric layer insulates said contact region (반도체소자의) . |
KR20040003948A CLAIM 1 필드산화막이 형성된 실리콘기판 상에 랜딩플러그 영역이 형성되도록 절연막 패턴을 형성한 후 , 이를 마스크로 소오스/드레인 이온주입 공정을 진행하여 소오스/드레인 영역을 형성하는 단계와 ; 상기 랜딩플러그 영역에 국부적으로 산화막을 형성하고 결과물 전체에 폴리를 증착한 후 , 산화막 상부에 제1스페이서를 형성하는 단계와 ; 상기 제1스페이서를 마스크로 과도식각하여 콘택홀을 형성하는 단계와 ; 상기 결과물 상에 도핑된 폴리실리콘을 증착하고 에치백 공정을 진행하여 제1 랜딩플러그폴리를 형성하는 단계와 ; 상기 결과물 상에 선택적으로 게이트산화막을 형성하고 , 게이트전극과 절연막이 순차적으로 적층된 게이트 패턴을 형성하는 단계와 ; 상기 게이트 패턴 측벽에 게이트 스페이서를 형성하고 감광막 패턴을 형성한 후 , 감광막 패턴과 게이트 스페이서를 마스크로 노출된 게이트산화막을 제거하는 단계와 ; 상기 결과물 상에 도핑된 폴리실리콘을 증착하여 제 2랜딩플러그폴리를 형성하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체소자의 (contact region) MOS 트랜지스터 제조방법 . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric layer insulates said contact region (반도체소자의) . |
KR20040003948A CLAIM 1 필드산화막이 형성된 실리콘기판 상에 랜딩플러그 영역이 형성되도록 절연막 패턴을 형성한 후 , 이를 마스크로 소오스/드레인 이온주입 공정을 진행하여 소오스/드레인 영역을 형성하는 단계와 ; 상기 랜딩플러그 영역에 국부적으로 산화막을 형성하고 결과물 전체에 폴리를 증착한 후 , 산화막 상부에 제1스페이서를 형성하는 단계와 ; 상기 제1스페이서를 마스크로 과도식각하여 콘택홀을 형성하는 단계와 ; 상기 결과물 상에 도핑된 폴리실리콘을 증착하고 에치백 공정을 진행하여 제1 랜딩플러그폴리를 형성하는 단계와 ; 상기 결과물 상에 선택적으로 게이트산화막을 형성하고 , 게이트전극과 절연막이 순차적으로 적층된 게이트 패턴을 형성하는 단계와 ; 상기 게이트 패턴 측벽에 게이트 스페이서를 형성하고 감광막 패턴을 형성한 후 , 감광막 패턴과 게이트 스페이서를 마스크로 노출된 게이트산화막을 제거하는 단계와 ; 상기 결과물 상에 도핑된 폴리실리콘을 증착하여 제 2랜딩플러그폴리를 형성하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체소자의 (contact region) MOS 트랜지스터 제조방법 . |
| US7977797B2 CLAIM 6 . An integrated circuit of claim 1 wherein said spacer region (산화막을) insulates said contact region (반도체소자의) . |
KR20040003948A CLAIM 1 필드산화막이 형성된 실리콘기판 상에 랜딩플러그 영역이 형성되도록 절연막 패턴을 형성한 후 , 이를 마스크로 소오스/드레인 이온주입 공정을 진행하여 소오스/드레인 영역을 형성하는 단계와 ; 상기 랜딩플러그 영역에 국부적으로 산화막을 (spacer region) 형성하고 결과물 전체에 폴리를 증착한 후 , 산화막 상부에 제1스페이서를 형성하는 단계와 ; 상기 제1스페이서를 마스크로 과도식각하여 콘택홀을 형성하는 단계와 ; 상기 결과물 상에 도핑된 폴리실리콘을 증착하고 에치백 공정을 진행하여 제1 랜딩플러그폴리를 형성하는 단계와 ; 상기 결과물 상에 선택적으로 게이트산화막을 형성하고 , 게이트전극과 절연막이 순차적으로 적층된 게이트 패턴을 형성하는 단계와 ; 상기 게이트 패턴 측벽에 게이트 스페이서를 형성하고 감광막 패턴을 형성한 후 , 감광막 패턴과 게이트 스페이서를 마스크로 노출된 게이트산화막을 제거하는 단계와 ; 상기 결과물 상에 도핑된 폴리실리콘을 증착하여 제 2랜딩플러그폴리를 형성하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체소자의 (contact region) MOS 트랜지스터 제조방법 . |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area of said contact region (반도체소자의) permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (페이스는) (CD) . |
KR20040003948A CLAIM 1 필드산화막이 형성된 실리콘기판 상에 랜딩플러그 영역이 형성되도록 절연막 패턴을 형성한 후 , 이를 마스크로 소오스/드레인 이온주입 공정을 진행하여 소오스/드레인 영역을 형성하는 단계와 ; 상기 랜딩플러그 영역에 국부적으로 산화막을 형성하고 결과물 전체에 폴리를 증착한 후 , 산화막 상부에 제1스페이서를 형성하는 단계와 ; 상기 제1스페이서를 마스크로 과도식각하여 콘택홀을 형성하는 단계와 ; 상기 결과물 상에 도핑된 폴리실리콘을 증착하고 에치백 공정을 진행하여 제1 랜딩플러그폴리를 형성하는 단계와 ; 상기 결과물 상에 선택적으로 게이트산화막을 형성하고 , 게이트전극과 절연막이 순차적으로 적층된 게이트 패턴을 형성하는 단계와 ; 상기 게이트 패턴 측벽에 게이트 스페이서를 형성하고 감광막 패턴을 형성한 후 , 감광막 패턴과 게이트 스페이서를 마스크로 노출된 게이트산화막을 제거하는 단계와 ; 상기 결과물 상에 도핑된 폴리실리콘을 증착하여 제 2랜딩플러그폴리를 형성하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체소자의 (contact region) MOS 트랜지스터 제조방법 . KR20040003948A CLAIM 2 제 1항에 있어서 , 상기 제 1스페이스는 (critical dimension) 도핑된 폴리실리콘을 증착한 후 , 건식식각하여 형성하는 것을 특징으로 하는 반도체소자의 MOS 트랜지스터 제조방법 . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric layer for said contact region (반도체소자의) is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
KR20040003948A CLAIM 1 필드산화막이 형성된 실리콘기판 상에 랜딩플러그 영역이 형성되도록 절연막 패턴을 형성한 후 , 이를 마스크로 소오스/드레인 이온주입 공정을 진행하여 소오스/드레인 영역을 형성하는 단계와 ; 상기 랜딩플러그 영역에 국부적으로 산화막을 형성하고 결과물 전체에 폴리를 증착한 후 , 산화막 상부에 제1스페이서를 형성하는 단계와 ; 상기 제1스페이서를 마스크로 과도식각하여 콘택홀을 형성하는 단계와 ; 상기 결과물 상에 도핑된 폴리실리콘을 증착하고 에치백 공정을 진행하여 제1 랜딩플러그폴리를 형성하는 단계와 ; 상기 결과물 상에 선택적으로 게이트산화막을 형성하고 , 게이트전극과 절연막이 순차적으로 적층된 게이트 패턴을 형성하는 단계와 ; 상기 게이트 패턴 측벽에 게이트 스페이서를 형성하고 감광막 패턴을 형성한 후 , 감광막 패턴과 게이트 스페이서를 마스크로 노출된 게이트산화막을 제거하는 단계와 ; 상기 결과물 상에 도핑된 폴리실리콘을 증착하여 제 2랜딩플러그폴리를 형성하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체소자의 (contact region) MOS 트랜지스터 제조방법 . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region (반도체소자의) and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
KR20040003948A CLAIM 1 필드산화막이 형성된 실리콘기판 상에 랜딩플러그 영역이 형성되도록 절연막 패턴을 형성한 후 , 이를 마스크로 소오스/드레인 이온주입 공정을 진행하여 소오스/드레인 영역을 형성하는 단계와 ; 상기 랜딩플러그 영역에 국부적으로 산화막을 형성하고 결과물 전체에 폴리를 증착한 후 , 산화막 상부에 제1스페이서를 형성하는 단계와 ; 상기 제1스페이서를 마스크로 과도식각하여 콘택홀을 형성하는 단계와 ; 상기 결과물 상에 도핑된 폴리실리콘을 증착하고 에치백 공정을 진행하여 제1 랜딩플러그폴리를 형성하는 단계와 ; 상기 결과물 상에 선택적으로 게이트산화막을 형성하고 , 게이트전극과 절연막이 순차적으로 적층된 게이트 패턴을 형성하는 단계와 ; 상기 게이트 패턴 측벽에 게이트 스페이서를 형성하고 감광막 패턴을 형성한 후 , 감광막 패턴과 게이트 스페이서를 마스크로 노출된 게이트산화막을 제거하는 단계와 ; 상기 결과물 상에 도핑된 폴리실리콘을 증착하여 제 2랜딩플러그폴리를 형성하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체소자의 (contact region) MOS 트랜지스터 제조방법 . |
| US7977797B2 CLAIM 13 . An integrated circuit of claim 11 further comprising a floating gate (절연막) . |
KR20040003948A CLAIM 1 필드산화막이 형성된 실리콘기판 상에 랜딩플러그 영역이 형성되도록 절연막 (floating gate) 패턴을 형성한 후 , 이를 마스크로 소오스/드레인 이온주입 공정을 진행하여 소오스/드레인 영역을 형성하는 단계와 ; 상기 랜딩플러그 영역에 국부적으로 산화막을 형성하고 결과물 전체에 폴리를 증착한 후 , 산화막 상부에 제1스페이서를 형성하는 단계와 ; 상기 제1스페이서를 마스크로 과도식각하여 콘택홀을 형성하는 단계와 ; 상기 결과물 상에 도핑된 폴리실리콘을 증착하고 에치백 공정을 진행하여 제1 랜딩플러그폴리를 형성하는 단계와 ; 상기 결과물 상에 선택적으로 게이트산화막을 형성하고 , 게이트전극과 절연막이 순차적으로 적층된 게이트 패턴을 형성하는 단계와 ; 상기 게이트 패턴 측벽에 게이트 스페이서를 형성하고 감광막 패턴을 형성한 후 , 감광막 패턴과 게이트 스페이서를 마스크로 노출된 게이트산화막을 제거하는 단계와 ; 상기 결과물 상에 도핑된 폴리실리콘을 증착하여 제 2랜딩플러그폴리를 형성하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체소자의 MOS 트랜지스터 제조방법 . |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region (반도체소자의) is a first range of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
KR20040003948A CLAIM 1 필드산화막이 형성된 실리콘기판 상에 랜딩플러그 영역이 형성되도록 절연막 패턴을 형성한 후 , 이를 마스크로 소오스/드레인 이온주입 공정을 진행하여 소오스/드레인 영역을 형성하는 단계와 ; 상기 랜딩플러그 영역에 국부적으로 산화막을 형성하고 결과물 전체에 폴리를 증착한 후 , 산화막 상부에 제1스페이서를 형성하는 단계와 ; 상기 제1스페이서를 마스크로 과도식각하여 콘택홀을 형성하는 단계와 ; 상기 결과물 상에 도핑된 폴리실리콘을 증착하고 에치백 공정을 진행하여 제1 랜딩플러그폴리를 형성하는 단계와 ; 상기 결과물 상에 선택적으로 게이트산화막을 형성하고 , 게이트전극과 절연막이 순차적으로 적층된 게이트 패턴을 형성하는 단계와 ; 상기 게이트 패턴 측벽에 게이트 스페이서를 형성하고 감광막 패턴을 형성한 후 , 감광막 패턴과 게이트 스페이서를 마스크로 노출된 게이트산화막을 제거하는 단계와 ; 상기 결과물 상에 도핑된 폴리실리콘을 증착하여 제 2랜딩플러그폴리를 형성하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체소자의 (contact region) MOS 트랜지스터 제조방법 . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US20020195686A1 Filed: 2002-03-29 Issued: 2002-12-26 Semiconductor device having shared contact and fabrication method thereof (Original Assignee) Samsung Electronics Co Ltd (Current Assignee) Samsung Electronics Co Ltd Do-hyung Kim, Jung-In Hong |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region (contact region) coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (contact hole) layer (entire surface) over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US20020195686A1 CLAIM 3 . The semiconductor device of claim 1 , at the shared contact region (contact region) , further comprising : a spacer having etch selectivity with the interlayer insulation layer at the side of the gate electrode ; and a high-concentration ion-implantation region spaced from the edge of the spacer at the LDD-type source/drain region . US20020195686A1 CLAIM 7 . A method of forming a semiconductor device , comprising : forming at least one gate pattern on a substrate ; forming a low-concentration source/drain region at a substrate located at both sides of the gate pattern through ion-implantation ; forming a spacer having an etch selectivity with respect to the gate pattern at a side of the gate pattern ; performing ion-implantation by using the gate pattern and the spacer as ion-implantation masks to form a high-concentration impurity ion-implantation region ; forming an interlayer insulation layer over the gate pattern at whose sidewall the spacer is formed ; and forming a shared contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) exposing parts of the top surface of the gate pattern and the LDD-type source/drain regions of the substrate adjacent to the gate pattern , and simultaneously etching and removing a certain width of the spacer together with the interlayer insulation layer at the shared contact region . US20020195686A1 CLAIM 11 . The method of claim 7 , wherein an etch-stopping layer formed using a material having a difference in etch selectivity with respect to the interlayer insulation layer at the entire surface (first sub interlevel dielectric layer) of the substrate , is formed before forming the interlayer insulation layer . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer protects removal of a substrate material (silicon oxide) by an etch process . |
US20020195686A1 CLAIM 9 . The method of claim 8 , wherein the interlayer insulation layer and the outer spacer layer are formed of silicon oxide (substrate material) and the inner spacer layer is formed of silicon nitride . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (contact hole) layer (entire surface) insulates said contact region (contact region) . |
US20020195686A1 CLAIM 3 . The semiconductor device of claim 1 , at the shared contact region (contact region) , further comprising : a spacer having etch selectivity with the interlayer insulation layer at the side of the gate electrode ; and a high-concentration ion-implantation region spaced from the edge of the spacer at the LDD-type source/drain region . US20020195686A1 CLAIM 7 . A method of forming a semiconductor device , comprising : forming at least one gate pattern on a substrate ; forming a low-concentration source/drain region at a substrate located at both sides of the gate pattern through ion-implantation ; forming a spacer having an etch selectivity with respect to the gate pattern at a side of the gate pattern ; performing ion-implantation by using the gate pattern and the spacer as ion-implantation masks to form a high-concentration impurity ion-implantation region ; forming an interlayer insulation layer over the gate pattern at whose sidewall the spacer is formed ; and forming a shared contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) exposing parts of the top surface of the gate pattern and the LDD-type source/drain regions of the substrate adjacent to the gate pattern , and simultaneously etching and removing a certain width of the spacer together with the interlayer insulation layer at the shared contact region . US20020195686A1 CLAIM 11 . The method of claim 7 , wherein an etch-stopping layer formed using a material having a difference in etch selectivity with respect to the interlayer insulation layer at the entire surface (first sub interlevel dielectric layer) of the substrate , is formed before forming the interlayer insulation layer . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch stop layer protects lower layers during an etching process (etching process) . |
US20020195686A1 CLAIM 10 . The method of claim 7 , wherein before forming the spacer , the method further comprises forming a non-conductive etch-stopping layer having a difference in etch selectivity with respect to the interlayer insulation layer over the gate pattern , and the forming of the shared contact hole further comprises removing the etch-stopping layer through an etching process (etching process) at the shared contact region . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (contact hole) layer insulates said contact region (contact region) . |
US20020195686A1 CLAIM 3 . The semiconductor device of claim 1 , at the shared contact region (contact region) , further comprising : a spacer having etch selectivity with the interlayer insulation layer at the side of the gate electrode ; and a high-concentration ion-implantation region spaced from the edge of the spacer at the LDD-type source/drain region . US20020195686A1 CLAIM 7 . A method of forming a semiconductor device , comprising : forming at least one gate pattern on a substrate ; forming a low-concentration source/drain region at a substrate located at both sides of the gate pattern through ion-implantation ; forming a spacer having an etch selectivity with respect to the gate pattern at a side of the gate pattern ; performing ion-implantation by using the gate pattern and the spacer as ion-implantation masks to form a high-concentration impurity ion-implantation region ; forming an interlayer insulation layer over the gate pattern at whose sidewall the spacer is formed ; and forming a shared contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) exposing parts of the top surface of the gate pattern and the LDD-type source/drain regions of the substrate adjacent to the gate pattern , and simultaneously etching and removing a certain width of the spacer together with the interlayer insulation layer at the shared contact region . |
| US7977797B2 CLAIM 6 . An integrated circuit of claim 1 wherein said spacer region insulates said contact region (contact region) . |
US20020195686A1 CLAIM 3 . The semiconductor device of claim 1 , at the shared contact region (contact region) , further comprising : a spacer having etch selectivity with the interlayer insulation layer at the side of the gate electrode ; and a high-concentration ion-implantation region spaced from the edge of the spacer at the LDD-type source/drain region . |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area of said contact region (contact region) permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
US20020195686A1 CLAIM 3 . The semiconductor device of claim 1 , at the shared contact region (contact region) , further comprising : a spacer having etch selectivity with the interlayer insulation layer at the side of the gate electrode ; and a high-concentration ion-implantation region spaced from the edge of the spacer at the LDD-type source/drain region . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (contact hole) layer (entire surface) is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US20020195686A1 CLAIM 7 . A method of forming a semiconductor device , comprising : forming at least one gate pattern on a substrate ; forming a low-concentration source/drain region at a substrate located at both sides of the gate pattern through ion-implantation ; forming a spacer having an etch selectivity with respect to the gate pattern at a side of the gate pattern ; performing ion-implantation by using the gate pattern and the spacer as ion-implantation masks to form a high-concentration impurity ion-implantation region ; forming an interlayer insulation layer over the gate pattern at whose sidewall the spacer is formed ; and forming a shared contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) exposing parts of the top surface of the gate pattern and the LDD-type source/drain regions of the substrate adjacent to the gate pattern , and simultaneously etching and removing a certain width of the spacer together with the interlayer insulation layer at the shared contact region . US20020195686A1 CLAIM 11 . The method of claim 7 , wherein an etch-stopping layer formed using a material having a difference in etch selectivity with respect to the interlayer insulation layer at the entire surface (first sub interlevel dielectric layer) of the substrate , is formed before forming the interlayer insulation layer . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric (contact hole) layer (entire surface) for said contact region (contact region) is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US20020195686A1 CLAIM 3 . The semiconductor device of claim 1 , at the shared contact region (contact region) , further comprising : a spacer having etch selectivity with the interlayer insulation layer at the side of the gate electrode ; and a high-concentration ion-implantation region spaced from the edge of the spacer at the LDD-type source/drain region . US20020195686A1 CLAIM 7 . A method of forming a semiconductor device , comprising : forming at least one gate pattern on a substrate ; forming a low-concentration source/drain region at a substrate located at both sides of the gate pattern through ion-implantation ; forming a spacer having an etch selectivity with respect to the gate pattern at a side of the gate pattern ; performing ion-implantation by using the gate pattern and the spacer as ion-implantation masks to form a high-concentration impurity ion-implantation region ; forming an interlayer insulation layer over the gate pattern at whose sidewall the spacer is formed ; and forming a shared contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) exposing parts of the top surface of the gate pattern and the LDD-type source/drain regions of the substrate adjacent to the gate pattern , and simultaneously etching and removing a certain width of the spacer together with the interlayer insulation layer at the shared contact region . US20020195686A1 CLAIM 11 . The method of claim 7 , wherein an etch-stopping layer formed using a material having a difference in etch selectivity with respect to the interlayer insulation layer at the entire surface (first sub interlevel dielectric layer) of the substrate , is formed before forming the interlayer insulation layer . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US20020195686A1 CLAIM 7 . A method of forming a semiconductor device , comprising : forming at least one gate pattern on a substrate ; forming a low-concentration source/drain region at a substrate located at both sides of the gate pattern through ion-implantation ; forming a spacer having an etch selectivity with respect to the gate pattern at a side of the gate pattern ; performing ion-implantation by using the gate pattern and the spacer as ion-implantation masks to form a high-concentration impurity ion-implantation region ; forming an interlayer insulation layer over the gate pattern at whose sidewall the spacer is formed ; and forming (anti reflective coating) a shared contact hole exposing parts of the top surface of the gate pattern and the LDD-type source/drain regions of the substrate adjacent to the gate pattern , and simultaneously etching and removing a certain width of the spacer together with the interlayer insulation layer at the shared contact region . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region (contact region) and under a first sub interlevel dielectric (contact hole) layer (entire surface) and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US20020195686A1 CLAIM 3 . The semiconductor device of claim 1 , at the shared contact region (contact region) , further comprising : a spacer having etch selectivity with the interlayer insulation layer at the side of the gate electrode ; and a high-concentration ion-implantation region spaced from the edge of the spacer at the LDD-type source/drain region . US20020195686A1 CLAIM 7 . A method of forming a semiconductor device , comprising : forming at least one gate pattern on a substrate ; forming a low-concentration source/drain region at a substrate located at both sides of the gate pattern through ion-implantation ; forming a spacer having an etch selectivity with respect to the gate pattern at a side of the gate pattern ; performing ion-implantation by using the gate pattern and the spacer as ion-implantation masks to form a high-concentration impurity ion-implantation region ; forming an interlayer insulation layer over the gate pattern at whose sidewall the spacer is formed ; and forming a shared contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) exposing parts of the top surface of the gate pattern and the LDD-type source/drain regions of the substrate adjacent to the gate pattern , and simultaneously etching and removing a certain width of the spacer together with the interlayer insulation layer at the shared contact region . US20020195686A1 CLAIM 11 . The method of claim 7 , wherein an etch-stopping layer formed using a material having a difference in etch selectivity with respect to the interlayer insulation layer at the entire surface (first sub interlevel dielectric layer) of the substrate , is formed before forming the interlayer insulation layer . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (contact hole) layer (entire surface) is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US20020195686A1 CLAIM 7 . A method of forming a semiconductor device , comprising : forming at least one gate pattern on a substrate ; forming a low-concentration source/drain region at a substrate located at both sides of the gate pattern through ion-implantation ; forming a spacer having an etch selectivity with respect to the gate pattern at a side of the gate pattern ; performing ion-implantation by using the gate pattern and the spacer as ion-implantation masks to form a high-concentration impurity ion-implantation region ; forming an interlayer insulation layer over the gate pattern at whose sidewall the spacer is formed ; and forming a shared contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) exposing parts of the top surface of the gate pattern and the LDD-type source/drain regions of the substrate adjacent to the gate pattern , and simultaneously etching and removing a certain width of the spacer together with the interlayer insulation layer at the shared contact region . US20020195686A1 CLAIM 11 . The method of claim 7 , wherein an etch-stopping layer formed using a material having a difference in etch selectivity with respect to the interlayer insulation layer at the entire surface (first sub interlevel dielectric layer) of the substrate , is formed before forming the interlayer insulation layer . |
| US7977797B2 CLAIM 13 . An integrated circuit of claim 11 further comprising a floating gate (drain regions) . |
US20020195686A1 CLAIM 1 . A semiconductor device comprising : a semiconductor substrate ; a gate electrode insulated from the semiconductor substrate by a gate insulation layer ; LDD-type source/drain regions (floating gate) formed at both sides of the gate electrode ; an interlayer insulation layer formed over the gate electrode and the substrate ; and a shared contact piercing the interlayer insulation layer and contacting the gate electrode and one of the LDD-type source/drain regions including at least a portion of a lightly doped drain region . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US20020195686A1 CLAIM 7 . A method of forming a semiconductor device , comprising : forming at least one gate pattern on a substrate ; forming a low-concentration source/drain region at a substrate located at both sides of the gate pattern through ion-implantation ; forming a spacer having an etch selectivity with respect to the gate pattern at a side of the gate pattern ; performing ion-implantation by using the gate pattern and the spacer as ion-implantation masks to form a high-concentration impurity ion-implantation region ; forming an interlayer insulation layer over the gate pattern at whose sidewall the spacer is formed ; and forming (anti reflective coating) a shared contact hole exposing parts of the top surface of the gate pattern and the LDD-type source/drain regions of the substrate adjacent to the gate pattern , and simultaneously etching and removing a certain width of the spacer together with the interlayer insulation layer at the shared contact region . |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region (contact region) is a first range of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US20020195686A1 CLAIM 3 . The semiconductor device of claim 1 , at the shared contact region (contact region) , further comprising : a spacer having etch selectivity with the interlayer insulation layer at the side of the gate electrode ; and a high-concentration ion-implantation region spaced from the edge of the spacer at the LDD-type source/drain region . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | KR20020067664A Filed: 2002-02-15 Issued: 2002-08-23 반도체 장치 및 그 제조 방법 (Original Assignee) 산요 덴키 가부시키가이샤 히노요시노리, 다께이시나오에이, 다니구찌도시미쯔 |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region (산화막을) such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
KR20020067664A CLAIM 10 일도전형의 반도체 내에 형성되는 저농도의 역도전형 소스 ·드레인층과 , 상기 저농도의 역도전형 소스 ·드레인층 내에 형성되는 고농도의 역도전형소스 ·드레인층과 , 상기 반도체 상에 게이트 산화막을 (spacer region) 사이에 두고서 형성되는 게이트 전극과 , 상기 게이트 전극 하방에 형성되고 , 상기 소스 ·드레인층간에 위치하는 채널을 형성하는 일도전형 반도체층과 , 상기 소스 ·드레인층에 콘택트하는 복수 배열된 콘택트부와 , 상기 콘택트부를 사이에 두고서 상기 소스 ·드레인층에 콘택트 접속하는 소스 ·드레인 전극을 구비한 것을 특징으로 하는 반도체 장치 . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer protects removal of a substrate material by an etch process (이외의) . |
KR20020067664A CLAIM 19 하층 배선을 피복하는 층간 절연막에 형성되는 비아홀을 사이에 두고서 상층 배선이 콘택트 접속되어 이루어지는 반도체 장치에 있어서 , 상기 비아홀이 , 패드부에 구성되는 범프 전극 아래 이외의 (etch process) 영역에 형성되어 있는 것을 특징으로 하는 반도체 장치 . |
| US7977797B2 CLAIM 6 . An integrated circuit of claim 1 wherein said spacer region (산화막을) insulates said contact region . |
KR20020067664A CLAIM 10 일도전형의 반도체 내에 형성되는 저농도의 역도전형 소스 ·드레인층과 , 상기 저농도의 역도전형 소스 ·드레인층 내에 형성되는 고농도의 역도전형소스 ·드레인층과 , 상기 반도체 상에 게이트 산화막을 (spacer region) 사이에 두고서 형성되는 게이트 전극과 , 상기 게이트 전극 하방에 형성되고 , 상기 소스 ·드레인층간에 위치하는 채널을 형성하는 일도전형 반도체층과 , 상기 소스 ·드레인층에 콘택트하는 복수 배열된 콘택트부와 , 상기 콘택트부를 사이에 두고서 상기 소스 ·드레인층에 콘택트 접속하는 소스 ·드레인 전극을 구비한 것을 특징으로 하는 반도체 장치 . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer (연막의) , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
KR20020067664A CLAIM 25 하층 배선을 피복하는 층간 절연막에 형성되는 비아홀을 사이에 두고서 상층배선이 콘택트 접속되어 이루어지는 반도체 장치의 제조 방법에 있어서 , 상기 하층 배선을 피복하도록 층간 절연막을 형성하는 공정과 , 상기 층간 절연막의 (second interlevel dielectric layer) 패드 형성부 이외의 영역에 비아홀을 형성한 후에 상기 비아홀을 사이에 두고서 상기 하층 배선에 콘택트하도록 상기 상층 배선을 형성하는 공정과 , 패드부에 범프 전극을 형성하는 공정을 구비한 것을 특징으로 하는 반도체 장치의 제조 방법 . |
| US7977797B2 CLAIM 13 . An integrated circuit of claim 11 further comprising a floating gate (절연막) . |
KR20020067664A CLAIM 16 일도전형의 반도체 장치 상에 게이트 산화막을 사이에 두고서 게이트 전극이 형성되어 이루어지는 반도체 장치의 제조 방법에 있어서 , 상기 반도체 내에 역도전형 불순물을 이온 주입하여 저농도의 역도전형 소스 ·드레인층을 형성하는 공정과 , 역도전형 불순물을 이온 주입하여 상기 저농도의 역도전형 소스 ·드레인층에 연결되는 역도전형층을 형성하는 공정과 , 역도전형 불순물을 이온 주입하여 상기 저농도의 역도전형 소스 ·드레인층 내에 고농도의 역도전형 소스 ·드레인층을 형성하는 공정과 , 일도전형 불순물을 이온 주입하여 상기 게이트 전극 하방에 상기 역도전형층을 분단하는 일도전형 바디층을 형성하는 공정과 , 상기 게이트 전극을 피복하는 층간 절연막 (floating gate) 을 사이에 두고서 상기 소스 ·드레인층에 콘택트 접속하기 위한 콘택트부를 복수열 형성하는 공정을 구비한 것을 특징으로 하는 반도체 장치의 제조 방법 . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | JP2003188386A Filed: 2001-12-20 Issued: 2003-07-04 半導体装置およびその製造方法 (Original Assignee) Sony Corp; ソニー株式会社 Kazuhide Koyama, 一英 小山 |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area (前記層) of said contact region is smaller than a metal layer coupling area (製造方法) of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch (オーバーエッチング) stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
JP2003188386A CLAIM 1 【請求項１】 Ｓｉ基板上に埋め込み酸化膜を介してＳ ＯＩ層が形成されたＳＯＩ基板を用い、そのＳＯＩ層に 複数個の素子分離領域を形成し、それら各素子分離領域 間のＳｉ活性層領域のボディ部，ソース・ドレイン部に 各々の不純物を注入してＭＯＳＦＥＴを構成した半導体 装置において、 前記Ｓｉ活性層領域上に対しゲート絶縁膜を介して形成 されたゲート電極と、 前記ゲート電極およびゲート絶縁膜の側壁側に形成され たゲートサイドウォールと、 前記Ｓｉ活性層領域におけるソース・ドレイン部に形成 されたシリサイド膜と、 前記の素子分離領域，ソース・ドレイン部，ゲート電 極，サイドウォールを覆うように形成された層間絶縁膜 と、 前記層 (substrate coupling area) 間絶縁膜に開孔されシリサイド膜を介してソース ・ドレイン部と電気的に接続するためのコンタクト孔 と、を備え、 前記コンタクト孔は、そのコンタクト孔底部がソース・ ドレイン部と素子分離領域との境界線上に位置するよう に開孔され、かつ前記コンタクト孔における素子分離領 域側の底部が、埋め込み酸化膜中に位置することを特徴 とする半導体装置。 JP2003188386A CLAIM 6 【請求項６】 Ｓｉ基板上に埋め込み酸化膜を介してＳ ＯＩ層が形成されたＳＯＩ基板を用い、そのＳＯＩ層に 複数個の素子分離領域を形成し、それら各素子分離領域 間のＳｉ活性層領域のボディ部，ソース・ドレイン部に 各々の不純物を注入してＭＯＳＦＥＴを構成した半導体 装置の製造方法 (metal layer coupling area) において、 前記Ｓｉ活性層領域のボディ部上にゲート絶縁膜を介し てゲート電極を形成する工程と、 前記Ｓｉ活性層領域のソース・ドレイン部にエクステン ション不純物を注入してエクステンション層を形成する 工程と、 前記ゲート電極およびゲート絶縁膜の側壁側にサイドウ ォールを形成してから、前記ソース・ドレイン部にシリ サイド膜を形成する工程と、 前記の素子分離領域，ソース・ドレイン部，ゲート電 極，サイドウォールを覆うように層間絶縁膜を形成し、 その層間絶縁膜に対してコンタクト孔を開孔する工程 と、を有し、 前記コンタクト孔において、そのコンタクト孔底部がソ ース・ドレイン部と素子分離領域との境界線上に位置す るように、かつ前記コンタクト孔における素子分離領域 側の底部が埋め込み酸化膜中に位置するように開孔した ことを特徴とする半導体装置の製造方法。 JP2003188386A CLAIM 11 【請求項１１】 前記の素子分離領域，Ｓｉ活性層領 域，ゲート電極，サイドウォールをストッパー膜で被覆 してから前記層間絶縁膜を形成した後、 前記層間絶縁膜をオーバーエッチング (first etch) して第１孔を形成 してから、その第１孔と異なるエッチング条件により残 存したストッパー膜をエッチングして第２孔を形成する ことにより、前記コンタクト孔を開孔したことを特徴と する請求項６記載の半導体装置の製造方法。 |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch (オーバーエッチング) stop layer protects removal of a substrate material (ウォール) by an etch process . |
JP2003188386A CLAIM 1 【請求項１】 Ｓｉ基板上に埋め込み酸化膜を介してＳ ＯＩ層が形成されたＳＯＩ基板を用い、そのＳＯＩ層に 複数個の素子分離領域を形成し、それら各素子分離領域 間のＳｉ活性層領域のボディ部，ソース・ドレイン部に 各々の不純物を注入してＭＯＳＦＥＴを構成した半導体 装置において、 前記Ｓｉ活性層領域上に対しゲート絶縁膜を介して形成 されたゲート電極と、 前記ゲート電極およびゲート絶縁膜の側壁側に形成され たゲートサイドウォール (substrate material) と、 前記Ｓｉ活性層領域におけるソース・ドレイン部に形成 されたシリサイド膜と、 前記の素子分離領域，ソース・ドレイン部，ゲート電 極，サイドウォールを覆うように形成された層間絶縁膜 と、 前記層間絶縁膜に開孔されシリサイド膜を介してソース ・ドレイン部と電気的に接続するためのコンタクト孔 と、を備え、 前記コンタクト孔は、そのコンタクト孔底部がソース・ ドレイン部と素子分離領域との境界線上に位置するよう に開孔され、かつ前記コンタクト孔における素子分離領 域側の底部が、埋め込み酸化膜中に位置することを特徴 とする半導体装置。 JP2003188386A CLAIM 11 【請求項１１】 前記の素子分離領域，Ｓｉ活性層領 域，ゲート電極，サイドウォールをストッパー膜で被覆 してから前記層間絶縁膜を形成した後、 前記層間絶縁膜をオーバーエッチング (first etch) して第１孔を形成 してから、その第１孔と異なるエッチング条件により残 存したストッパー膜をエッチングして第２孔を形成する ことにより、前記コンタクト孔を開孔したことを特徴と する請求項６記載の半導体装置の製造方法。 |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area (前記層) of said contact region permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area (製造方法) of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
JP2003188386A CLAIM 1 【請求項１】 Ｓｉ基板上に埋め込み酸化膜を介してＳ ＯＩ層が形成されたＳＯＩ基板を用い、そのＳＯＩ層に 複数個の素子分離領域を形成し、それら各素子分離領域 間のＳｉ活性層領域のボディ部，ソース・ドレイン部に 各々の不純物を注入してＭＯＳＦＥＴを構成した半導体 装置において、 前記Ｓｉ活性層領域上に対しゲート絶縁膜を介して形成 されたゲート電極と、 前記ゲート電極およびゲート絶縁膜の側壁側に形成され たゲートサイドウォールと、 前記Ｓｉ活性層領域におけるソース・ドレイン部に形成 されたシリサイド膜と、 前記の素子分離領域，ソース・ドレイン部，ゲート電 極，サイドウォールを覆うように形成された層間絶縁膜 と、 前記層 (substrate coupling area) 間絶縁膜に開孔されシリサイド膜を介してソース ・ドレイン部と電気的に接続するためのコンタクト孔 と、を備え、 前記コンタクト孔は、そのコンタクト孔底部がソース・ ドレイン部と素子分離領域との境界線上に位置するよう に開孔され、かつ前記コンタクト孔における素子分離領 域側の底部が、埋め込み酸化膜中に位置することを特徴 とする半導体装置。 JP2003188386A CLAIM 6 【請求項６】 Ｓｉ基板上に埋め込み酸化膜を介してＳ ＯＩ層が形成されたＳＯＩ基板を用い、そのＳＯＩ層に 複数個の素子分離領域を形成し、それら各素子分離領域 間のＳｉ活性層領域のボディ部，ソース・ドレイン部に 各々の不純物を注入してＭＯＳＦＥＴを構成した半導体 装置の製造方法 (metal layer coupling area) において、 前記Ｓｉ活性層領域のボディ部上にゲート絶縁膜を介し てゲート電極を形成する工程と、 前記Ｓｉ活性層領域のソース・ドレイン部にエクステン ション不純物を注入してエクステンション層を形成する 工程と、 前記ゲート電極およびゲート絶縁膜の側壁側にサイドウ ォールを形成してから、前記ソース・ドレイン部にシリ サイド膜を形成する工程と、 前記の素子分離領域，ソース・ドレイン部，ゲート電 極，サイドウォールを覆うように層間絶縁膜を形成し、 その層間絶縁膜に対してコンタクト孔を開孔する工程 と、を有し、 前記コンタクト孔において、そのコンタクト孔底部がソ ース・ドレイン部と素子分離領域との境界線上に位置す るように、かつ前記コンタクト孔における素子分離領域 側の底部が埋め込み酸化膜中に位置するように開孔した ことを特徴とする半導体装置の製造方法。 |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch (オーバーエッチング) stop layer is in a range of about 300 to 800 Å thick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Å thick , said second etch stop layer is in a range of about 300 to 800 Å thick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Å thick . |
JP2003188386A CLAIM 11 【請求項１１】 前記の素子分離領域，Ｓｉ活性層領 域，ゲート電極，サイドウォールをストッパー膜で被覆 してから前記層間絶縁膜を形成した後、 前記層間絶縁膜をオーバーエッチング (first etch) して第１孔を形成 してから、その第１孔と異なるエッチング条件により残 存したストッパー膜をエッチングして第２孔を形成する ことにより、前記コンタクト孔を開孔したことを特徴と する請求項６記載の半導体装置の製造方法。 |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range (あること) of about 0 . 16 μm to 0 . 18 μm wide . |
JP2003188386A CLAIM 5 【請求項５】 前記ソース・ドレイン部におけるシリサ イド膜の側壁側と前記サイドウォール直下に位置するＳ ｉ活性層領域との間において、そのコンタクト抵抗が１ ０Ω・μｍ 2 以下であること (second range) を特徴とする請求項１記載 の半導体装置。 |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch (オーバーエッチング) stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area (前記層) of said contact region is smaller than a metal layer coupling area (製造方法) of said contact region . |
JP2003188386A CLAIM 1 【請求項１】 Ｓｉ基板上に埋め込み酸化膜を介してＳ ＯＩ層が形成されたＳＯＩ基板を用い、そのＳＯＩ層に 複数個の素子分離領域を形成し、それら各素子分離領域 間のＳｉ活性層領域のボディ部，ソース・ドレイン部に 各々の不純物を注入してＭＯＳＦＥＴを構成した半導体 装置において、 前記Ｓｉ活性層領域上に対しゲート絶縁膜を介して形成 されたゲート電極と、 前記ゲート電極およびゲート絶縁膜の側壁側に形成され たゲートサイドウォールと、 前記Ｓｉ活性層領域におけるソース・ドレイン部に形成 されたシリサイド膜と、 前記の素子分離領域，ソース・ドレイン部，ゲート電 極，サイドウォールを覆うように形成された層間絶縁膜 と、 前記層 (substrate coupling area) 間絶縁膜に開孔されシリサイド膜を介してソース ・ドレイン部と電気的に接続するためのコンタクト孔 と、を備え、 前記コンタクト孔は、そのコンタクト孔底部がソース・ ドレイン部と素子分離領域との境界線上に位置するよう に開孔され、かつ前記コンタクト孔における素子分離領 域側の底部が、埋め込み酸化膜中に位置することを特徴 とする半導体装置。 JP2003188386A CLAIM 6 【請求項６】 Ｓｉ基板上に埋め込み酸化膜を介してＳ ＯＩ層が形成されたＳＯＩ基板を用い、そのＳＯＩ層に 複数個の素子分離領域を形成し、それら各素子分離領域 間のＳｉ活性層領域のボディ部，ソース・ドレイン部に 各々の不純物を注入してＭＯＳＦＥＴを構成した半導体 装置の製造方法 (metal layer coupling area) において、 前記Ｓｉ活性層領域のボディ部上にゲート絶縁膜を介し てゲート電極を形成する工程と、 前記Ｓｉ活性層領域のソース・ドレイン部にエクステン ション不純物を注入してエクステンション層を形成する 工程と、 前記ゲート電極およびゲート絶縁膜の側壁側にサイドウ ォールを形成してから、前記ソース・ドレイン部にシリ サイド膜を形成する工程と、 前記の素子分離領域，ソース・ドレイン部，ゲート電 極，サイドウォールを覆うように層間絶縁膜を形成し、 その層間絶縁膜に対してコンタクト孔を開孔する工程 と、を有し、 前記コンタクト孔において、そのコンタクト孔底部がソ ース・ドレイン部と素子分離領域との境界線上に位置す るように、かつ前記コンタクト孔における素子分離領域 側の底部が埋め込み酸化膜中に位置するように開孔した ことを特徴とする半導体装置の製造方法。 JP2003188386A CLAIM 11 【請求項１１】 前記の素子分離領域，Ｓｉ活性層領 域，ゲート電極，サイドウォールをストッパー膜で被覆 してから前記層間絶縁膜を形成した後、 前記層間絶縁膜をオーバーエッチング (first etch) して第１孔を形成 してから、その第１孔と異なるエッチング条件により残 存したストッパー膜をエッチングして第２孔を形成する ことにより、前記コンタクト孔を開孔したことを特徴と する請求項６記載の半導体装置の製造方法。 |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch (オーバーエッチング) stop layer is in a range of about 300 to 800 Å thick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Å thick , said second etch stop layer is in a range of about 300 to 800 Å thick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Å thick . |
JP2003188386A CLAIM 11 【請求項１１】 前記の素子分離領域，Ｓｉ活性層領 域，ゲート電極，サイドウォールをストッパー膜で被覆 してから前記層間絶縁膜を形成した後、 前記層間絶縁膜をオーバーエッチング (first etch) して第１孔を形成 してから、その第１孔と異なるエッチング条件により残 存したストッパー膜をエッチングして第２孔を形成する ことにより、前記コンタクト孔を開孔したことを特徴と する請求項６記載の半導体装置の製造方法。 |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region is a first range of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range (あること) of about 0 . 16 μm to 0 . 18 μm wide . |
JP2003188386A CLAIM 5 【請求項５】 前記ソース・ドレイン部におけるシリサ イド膜の側壁側と前記サイドウォール直下に位置するＳ ｉ活性層領域との間において、そのコンタクト抵抗が１ ０Ω・μｍ 2 以下であること (second range) を特徴とする請求項１記載 の半導体装置。 |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | JP2002141412A Filed: 2001-08-27 Issued: 2002-05-17 導電性結線の製造法 (Original Assignee) Infineon Technologies Ag; インフィネオン テクノロジース アクチエンゲゼルシャフト Barbara Hasler, Guenther Dr Schindler, Rainer Florian Schnabel, Volker Weinrich, シンドラー ギュンター, ハスラー バーバラ, ヴァインリヒ フォルカー, フローリアン シュナーベル ライナ− |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation (絶縁層, の絶縁) between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch (１．５〜４) stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer (少なくとも) over said second etch stop layer . |
JP2002141412A CLAIM 1 【請求項１】 次の工程： ａ）少なくとも (second sub interlevel dielectric layer) １つの絶縁層 (electrical insulation) を有する半導体基板を準備 し； ｂ）マスクを絶縁層の上面上に施こし； ｃ）主に等方性エッチング工程を実施し； ｄ）主に異方的なエッチング工程を、絶縁層の下面が達 成されかつコンタクトホールが製造されるまで実施し； ｅ）マスクを取り除き； ｆ）コンタクトホールを第１の導電性材料で充填し； ｇ）第１の導電性材料を所定の深さになるまで裏面エッ チングし、 ｈ）コンタクトホールの自由領域を少なくとも１つの第 ２の導電性材料で充填することにより、殊に拡散領域と 電極との間に導電性結線を製造するために１つ以上の絶 縁層によって導電性結線を製造する方法。 JP2002141412A CLAIM 2 【請求項２】 等方性エッチングされた領域内のコンタ クトホール面と異方性エッチングされた領域内のコンタ クトホール面との比が１．５〜４ (second etch) 、有利に２〜３であ る、請求項１記載の方法。 |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch (１．５〜４) stop layer protects lower layers during an etching process . |
JP2002141412A CLAIM 2 【請求項２】 等方性エッチングされた領域内のコンタ クトホール面と異方性エッチングされた領域内のコンタ クトホール面との比が１．５〜４ (second etch) 、有利に２〜３であ る、請求項１記載の方法。 |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric layer (少なくとも) insulates said contact region . |
JP2002141412A CLAIM 1 【請求項１】 次の工程： ａ）少なくとも (second sub interlevel dielectric layer) １つの絶縁層を有する半導体基板を準備 し； ｂ）マスクを絶縁層の上面上に施こし； ｃ）主に等方性エッチング工程を実施し； ｄ）主に異方的なエッチング工程を、絶縁層の下面が達 成されかつコンタクトホールが製造されるまで実施し； ｅ）マスクを取り除き； ｆ）コンタクトホールを第１の導電性材料で充填し； ｇ）第１の導電性材料を所定の深さになるまで裏面エッ チングし、 ｈ）コンタクトホールの自由領域を少なくとも１つの第 ２の導電性材料で充填することにより、殊に拡散領域と 電極との間に導電性結線を製造するために１つ以上の絶 縁層によって導電性結線を製造する方法。 |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Å thick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Å thick , said second etch (１．５〜４) stop layer is in a range of about 300 to 800 Å thick and said second sub interlevel dielectric layer (少なくとも) is in a range of about 10K ű1K Å thick . |
JP2002141412A CLAIM 1 【請求項１】 次の工程： ａ）少なくとも (second sub interlevel dielectric layer) １つの絶縁層を有する半導体基板を準備 し； ｂ）マスクを絶縁層の上面上に施こし； ｃ）主に等方性エッチング工程を実施し； ｄ）主に異方的なエッチング工程を、絶縁層の下面が達 成されかつコンタクトホールが製造されるまで実施し； ｅ）マスクを取り除き； ｆ）コンタクトホールを第１の導電性材料で充填し； ｇ）第１の導電性材料を所定の深さになるまで裏面エッ チングし、 ｈ）コンタクトホールの自由領域を少なくとも１つの第 ２の導電性材料で充填することにより、殊に拡散領域と 電極との間に導電性結線を製造するために１つ以上の絶 縁層によって導電性結線を製造する方法。 JP2002141412A CLAIM 2 【請求項２】 等方性エッチングされた領域内のコンタ クトホール面と異方性エッチングされた領域内のコンタ クトホール面との比が１．５〜４ (second etch) 、有利に２〜３であ る、請求項１記載の方法。 |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer (少なくとも) for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
JP2002141412A CLAIM 1 【請求項１】 次の工程： ａ）少なくとも (second sub interlevel dielectric layer) １つの絶縁層を有する半導体基板を準備 し； ｂ）マスクを絶縁層の上面上に施こし； ｃ）主に等方性エッチング工程を実施し； ｄ）主に異方的なエッチング工程を、絶縁層の下面が達 成されかつコンタクトホールが製造されるまで実施し； ｅ）マスクを取り除き； ｆ）コンタクトホールを第１の導電性材料で充填し； ｇ）第１の導電性材料を所定の深さになるまで裏面エッ チングし、 ｈ）コンタクトホールの自由領域を少なくとも１つの第 ２の導電性材料で充填することにより、殊に拡散領域と 電極との間に導電性結線を製造するために１つ以上の絶 縁層によって導電性結線を製造する方法。 |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch (１．５〜４) stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer (少なくとも) and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
JP2002141412A CLAIM 1 【請求項１】 次の工程： ａ）少なくとも (second sub interlevel dielectric layer) １つの絶縁層を有する半導体基板を準備 し； ｂ）マスクを絶縁層の上面上に施こし； ｃ）主に等方性エッチング工程を実施し； ｄ）主に異方的なエッチング工程を、絶縁層の下面が達 成されかつコンタクトホールが製造されるまで実施し； ｅ）マスクを取り除き； ｆ）コンタクトホールを第１の導電性材料で充填し； ｇ）第１の導電性材料を所定の深さになるまで裏面エッ チングし、 ｈ）コンタクトホールの自由領域を少なくとも１つの第 ２の導電性材料で充填することにより、殊に拡散領域と 電極との間に導電性結線を製造するために１つ以上の絶 縁層によって導電性結線を製造する方法。 JP2002141412A CLAIM 2 【請求項２】 等方性エッチングされた領域内のコンタ クトホール面と異方性エッチングされた領域内のコンタ クトホール面との比が１．５〜４ (second etch) 、有利に２〜３であ る、請求項１記載の方法。 |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Å thick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Å thick , said second etch (１．５〜４) stop layer is in a range of about 300 to 800 Å thick and said second sub interlevel dielectric layer (少なくとも) is in a range of about 10K ű1K Å thick . |
JP2002141412A CLAIM 1 【請求項１】 次の工程： ａ）少なくとも (second sub interlevel dielectric layer) １つの絶縁層を有する半導体基板を準備 し； ｂ）マスクを絶縁層の上面上に施こし； ｃ）主に等方性エッチング工程を実施し； ｄ）主に異方的なエッチング工程を、絶縁層の下面が達 成されかつコンタクトホールが製造されるまで実施し； ｅ）マスクを取り除き； ｆ）コンタクトホールを第１の導電性材料で充填し； ｇ）第１の導電性材料を所定の深さになるまで裏面エッ チングし、 ｈ）コンタクトホールの自由領域を少なくとも１つの第 ２の導電性材料で充填することにより、殊に拡散領域と 電極との間に導電性結線を製造するために１つ以上の絶 縁層によって導電性結線を製造する方法。 JP2002141412A CLAIM 2 【請求項２】 等方性エッチングされた領域内のコンタ クトホール面と異方性エッチングされた領域内のコンタ クトホール面との比が１．５〜４ (second etch) 、有利に２〜３であ る、請求項１記載の方法。 |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | CN1333568A Filed: 2001-07-11 Issued: 2002-01-30 半导体器件及其制造方法 (Original Assignee) 株式会社东芝 八木下淳史, 松尾浩司 |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer (形成第一) directly on said substrate in said contact region ; a first sub interlevel dielectric layer (的界面) over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
CN1333568A CLAIM 1 . 一种半导体器件，包括：硅衬底；在该硅衬底上形成的栅绝缘膜；在该栅绝缘膜上形成的栅电极；以及夹着该栅电极在上述硅衬底上形成的、与该硅衬底的界面 (first sub interlevel dielectric layer) 肖特基结合的由硅化物形成的源和漏；其特征在于：满足上述栅绝缘膜的材料是高介电膜和上述栅电极的材料是金属这两个条件中的至少一个。 CN1333568A CLAIM 12 . 一种半导体器件的制造方法，包括下列步骤：在硅衬底上形成层间绝缘膜；选择性地除去PMISFET和NMISFET的源和漏的预定形成区之间的上述层间绝缘膜，形成栅沟；在上述栅沟的侧壁上形成侧壁绝缘膜；在上述栅沟的底面上露出上述硅衬底，在露出的硅衬底的表面上形成栅绝缘膜；在上述栅沟内埋置形成栅电极；选择性地蚀刻上述PMISFET和NMISFET的源和漏的预定形成区的上述层间绝缘膜，形成在底部露出上述硅衬底的表面的PMIS侧源/漏沟；在上述PMIS侧源/漏沟内埋置形成第一 (first etch stop layer) 金属膜，形成PMISFET的源极和漏极；使上述硅衬底和上述PMISFET的源极和漏极反应，形成与该硅衬底肖特基结合的硅化物膜，形成PMISFET的源和漏；选择性地蚀刻上述NMISFET的源和漏的预定形成区的上述层间绝缘膜，形成在底部露出上述硅衬底的表面的NMIS侧源/漏沟；在上述NMIS侧源/漏沟内埋置形成由与第一金属膜不同的材料构成的第二金属膜，形成NMISFET的源极和漏极；使上述硅衬底和上述NMISFET的源极和漏极反应，形成与该硅衬底肖特基结合的硅化物膜，形成NMISFET的源和漏。 |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer (形成第一) protects removal of a substrate material by an etch process . |
CN1333568A CLAIM 12 . 一种半导体器件的制造方法，包括下列步骤：在硅衬底上形成层间绝缘膜；选择性地除去PMISFET和NMISFET的源和漏的预定形成区之间的上述层间绝缘膜，形成栅沟；在上述栅沟的侧壁上形成侧壁绝缘膜；在上述栅沟的底面上露出上述硅衬底，在露出的硅衬底的表面上形成栅绝缘膜；在上述栅沟内埋置形成栅电极；选择性地蚀刻上述PMISFET和NMISFET的源和漏的预定形成区的上述层间绝缘膜，形成在底部露出上述硅衬底的表面的PMIS侧源/漏沟；在上述PMIS侧源/漏沟内埋置形成第一 (first etch stop layer) 金属膜，形成PMISFET的源极和漏极；使上述硅衬底和上述PMISFET的源极和漏极反应，形成与该硅衬底肖特基结合的硅化物膜，形成PMISFET的源和漏；选择性地蚀刻上述NMISFET的源和漏的预定形成区的上述层间绝缘膜，形成在底部露出上述硅衬底的表面的NMIS侧源/漏沟；在上述NMIS侧源/漏沟内埋置形成由与第一金属膜不同的材料构成的第二金属膜，形成NMISFET的源极和漏极；使上述硅衬底和上述NMISFET的源极和漏极反应，形成与该硅衬底肖特基结合的硅化物膜，形成NMISFET的源和漏。 |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric layer (的界面) insulates said contact region . |
CN1333568A CLAIM 1 . 一种半导体器件，包括：硅衬底；在该硅衬底上形成的栅绝缘膜；在该栅绝缘膜上形成的栅电极；以及夹着该栅电极在上述硅衬底上形成的、与该硅衬底的界面 (first sub interlevel dielectric layer) 肖特基结合的由硅化物形成的源和漏；其特征在于：满足上述栅绝缘膜的材料是高介电膜和上述栅电极的材料是金属这两个条件中的至少一个。 |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch stop layer protects lower layers during an etching process (的半导体衬底) . |
CN1333568A CLAIM 3 . 如权利要求1所述的半导体器件，其特征在于：在上述栅电极下的沟道区和上述源与漏之间的半导体衬底 (etching process) 上，形成有与上述沟道区导电型相反的延伸区。 |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area of said contact region permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (肖特基结) (CD) . |
CN1333568A CLAIM 1 . 一种半导体器件，包括：硅衬底；在该硅衬底上形成的栅绝缘膜；在该栅绝缘膜上形成的栅电极；以及夹着该栅电极在上述硅衬底上形成的、与该硅衬底的界面肖特基结 (critical dimension) 合的由硅化物形成的源和漏；其特征在于：满足上述栅绝缘膜的材料是高介电膜和上述栅电极的材料是金属这两个条件中的至少一个。 |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer (形成第一) is in a range of about 300 to 800 Å thick , said first sub interlevel dielectric layer (的界面) is in a range of about 1 , 000 to 2 , 000 Å thick , said second etch stop layer is in a range of about 300 to 800 Å thick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Å thick . |
CN1333568A CLAIM 1 . 一种半导体器件，包括：硅衬底；在该硅衬底上形成的栅绝缘膜；在该栅绝缘膜上形成的栅电极；以及夹着该栅电极在上述硅衬底上形成的、与该硅衬底的界面 (first sub interlevel dielectric layer) 肖特基结合的由硅化物形成的源和漏；其特征在于：满足上述栅绝缘膜的材料是高介电膜和上述栅电极的材料是金属这两个条件中的至少一个。 CN1333568A CLAIM 12 . 一种半导体器件的制造方法，包括下列步骤：在硅衬底上形成层间绝缘膜；选择性地除去PMISFET和NMISFET的源和漏的预定形成区之间的上述层间绝缘膜，形成栅沟；在上述栅沟的侧壁上形成侧壁绝缘膜；在上述栅沟的底面上露出上述硅衬底，在露出的硅衬底的表面上形成栅绝缘膜；在上述栅沟内埋置形成栅电极；选择性地蚀刻上述PMISFET和NMISFET的源和漏的预定形成区的上述层间绝缘膜，形成在底部露出上述硅衬底的表面的PMIS侧源/漏沟；在上述PMIS侧源/漏沟内埋置形成第一 (first etch stop layer) 金属膜，形成PMISFET的源极和漏极；使上述硅衬底和上述PMISFET的源极和漏极反应，形成与该硅衬底肖特基结合的硅化物膜，形成PMISFET的源和漏；选择性地蚀刻上述NMISFET的源和漏的预定形成区的上述层间绝缘膜，形成在底部露出上述硅衬底的表面的NMIS侧源/漏沟；在上述NMIS侧源/漏沟内埋置形成由与第一金属膜不同的材料构成的第二金属膜，形成NMISFET的源极和漏极；使上述硅衬底和上述NMISFET的源极和漏极反应，形成与该硅衬底肖特基结合的硅化物膜，形成NMISFET的源和漏。 |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric layer (的界面) for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
CN1333568A CLAIM 1 . 一种半导体器件，包括：硅衬底；在该硅衬底上形成的栅绝缘膜；在该栅绝缘膜上形成的栅电极；以及夹着该栅电极在上述硅衬底上形成的、与该硅衬底的界面 (first sub interlevel dielectric layer) 肖特基结合的由硅化物形成的源和漏；其特征在于：满足上述栅绝缘膜的材料是高介电膜和上述栅电极的材料是金属这两个条件中的至少一个。 |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer (形成第一) and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer (的界面) and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
CN1333568A CLAIM 1 . 一种半导体器件，包括：硅衬底；在该硅衬底上形成的栅绝缘膜；在该栅绝缘膜上形成的栅电极；以及夹着该栅电极在上述硅衬底上形成的、与该硅衬底的界面 (first sub interlevel dielectric layer) 肖特基结合的由硅化物形成的源和漏；其特征在于：满足上述栅绝缘膜的材料是高介电膜和上述栅电极的材料是金属这两个条件中的至少一个。 CN1333568A CLAIM 12 . 一种半导体器件的制造方法，包括下列步骤：在硅衬底上形成层间绝缘膜；选择性地除去PMISFET和NMISFET的源和漏的预定形成区之间的上述层间绝缘膜，形成栅沟；在上述栅沟的侧壁上形成侧壁绝缘膜；在上述栅沟的底面上露出上述硅衬底，在露出的硅衬底的表面上形成栅绝缘膜；在上述栅沟内埋置形成栅电极；选择性地蚀刻上述PMISFET和NMISFET的源和漏的预定形成区的上述层间绝缘膜，形成在底部露出上述硅衬底的表面的PMIS侧源/漏沟；在上述PMIS侧源/漏沟内埋置形成第一 (first etch stop layer) 金属膜，形成PMISFET的源极和漏极；使上述硅衬底和上述PMISFET的源极和漏极反应，形成与该硅衬底肖特基结合的硅化物膜，形成PMISFET的源和漏；选择性地蚀刻上述NMISFET的源和漏的预定形成区的上述层间绝缘膜，形成在底部露出上述硅衬底的表面的NMIS侧源/漏沟；在上述NMIS侧源/漏沟内埋置形成由与第一金属膜不同的材料构成的第二金属膜，形成NMISFET的源极和漏极；使上述硅衬底和上述NMISFET的源极和漏极反应，形成与该硅衬底肖特基结合的硅化物膜，形成NMISFET的源和漏。 |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer (形成第一) is in a range of about 300 to 800 Å thick , said first sub interlevel dielectric layer (的界面) is in a range of about 1 , 000 to 2 , 000 Å thick , said second etch stop layer is in a range of about 300 to 800 Å thick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Å thick . |
CN1333568A CLAIM 1 . 一种半导体器件，包括：硅衬底；在该硅衬底上形成的栅绝缘膜；在该栅绝缘膜上形成的栅电极；以及夹着该栅电极在上述硅衬底上形成的、与该硅衬底的界面 (first sub interlevel dielectric layer) 肖特基结合的由硅化物形成的源和漏；其特征在于：满足上述栅绝缘膜的材料是高介电膜和上述栅电极的材料是金属这两个条件中的至少一个。 CN1333568A CLAIM 12 . 一种半导体器件的制造方法，包括下列步骤：在硅衬底上形成层间绝缘膜；选择性地除去PMISFET和NMISFET的源和漏的预定形成区之间的上述层间绝缘膜，形成栅沟；在上述栅沟的侧壁上形成侧壁绝缘膜；在上述栅沟的底面上露出上述硅衬底，在露出的硅衬底的表面上形成栅绝缘膜；在上述栅沟内埋置形成栅电极；选择性地蚀刻上述PMISFET和NMISFET的源和漏的预定形成区的上述层间绝缘膜，形成在底部露出上述硅衬底的表面的PMIS侧源/漏沟；在上述PMIS侧源/漏沟内埋置形成第一 (first etch stop layer) 金属膜，形成PMISFET的源极和漏极；使上述硅衬底和上述PMISFET的源极和漏极反应，形成与该硅衬底肖特基结合的硅化物膜，形成PMISFET的源和漏；选择性地蚀刻上述NMISFET的源和漏的预定形成区的上述层间绝缘膜，形成在底部露出上述硅衬底的表面的NMIS侧源/漏沟；在上述NMIS侧源/漏沟内埋置形成由与第一金属膜不同的材料构成的第二金属膜，形成NMISFET的源极和漏极；使上述硅衬底和上述NMISFET的源极和漏极反应，形成与该硅衬底肖特基结合的硅化物膜，形成NMISFET的源和漏。 |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US6653739B2 Filed: 2001-07-10 Issued: 2003-11-25 Semiconductor device (Original Assignee) Mitsubishi Electric Corp (Current Assignee) Renesas Electronics Corp Takashi Terauchi, Yoshinori Tanaka |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (interlayer insulating film) layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US6653739B2 CLAIM 1 . A semiconductor device having a contact hole defined between adjacent two wirings by a self-aligning manner , comprising : a contact plug formed in said contact hole ; a substrate layer conductive to the bottom face of said contact plug ; an interlayer oxide film formed on said substrate layer ; a lower insulating film formed of a nitride based insulating film so as to cover the entire surface (first sub interlevel dielectric layer) of said interlayer oxide film except for said contact hole portion ; said two wirings formed on said lower insulating film with said contact hole interposed therebetween ; an upper insulating film formed of a nitride based insulating film with the same width as said each wiring so as to cover the upper surface of said each wiring ; and sidewalls formed of a nitride based insulating film so as to cover the side faces of said each wiring and the side faces of said upper insulating film , wherein said contact hole has an enlarged portion formed in the same layer as said interlayer oxide film , which has a diameter larger than an interval defined between said two wirings . US6653739B2 CLAIM 13 . The semiconductor device according to claim 1 , wherein said substrate layer includes a gate electrode formed on a semiconductor substrate , an interlayer insulating film (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer) for covering said gate electrode , and a plurality of pad contact plugs which extend through said interlayer insulating film so as to be conductive to a source-drain region of said semiconductor substrate , said each wiring is a bit line formed over said substrate layer ; and said contact plug is a storage node contact plug which passes between said bit lines and is thereby conductive to one of said plurality of pad contact plugs , and said semiconductor device further comprising : a bit line contact plug which extends through said lower insulating film and said interlayer oxide film to thereby bring said bit line and part of said plurality of pad contact plugs to a conducting state , and a capacitor formed on said storage node contact plug . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (interlayer insulating film) layer insulates said contact region . |
US6653739B2 CLAIM 1 . A semiconductor device having a contact hole defined between adjacent two wirings by a self-aligning manner , comprising : a contact plug formed in said contact hole ; a substrate layer conductive to the bottom face of said contact plug ; an interlayer oxide film formed on said substrate layer ; a lower insulating film formed of a nitride based insulating film so as to cover the entire surface (first sub interlevel dielectric layer) of said interlayer oxide film except for said contact hole portion ; said two wirings formed on said lower insulating film with said contact hole interposed therebetween ; an upper insulating film formed of a nitride based insulating film with the same width as said each wiring so as to cover the upper surface of said each wiring ; and sidewalls formed of a nitride based insulating film so as to cover the side faces of said each wiring and the side faces of said upper insulating film , wherein said contact hole has an enlarged portion formed in the same layer as said interlayer oxide film , which has a diameter larger than an interval defined between said two wirings . US6653739B2 CLAIM 13 . The semiconductor device according to claim 1 , wherein said substrate layer includes a gate electrode formed on a semiconductor substrate , an interlayer insulating film (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer) for covering said gate electrode , and a plurality of pad contact plugs which extend through said interlayer insulating film so as to be conductive to a source-drain region of said semiconductor substrate , said each wiring is a bit line formed over said substrate layer ; and said contact plug is a storage node contact plug which passes between said bit lines and is thereby conductive to one of said plurality of pad contact plugs , and said semiconductor device further comprising : a bit line contact plug which extends through said lower insulating film and said interlayer oxide film to thereby bring said bit line and part of said plurality of pad contact plugs to a conducting state , and a capacitor formed on said storage node contact plug . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (interlayer insulating film) layer insulates said contact region . |
US6653739B2 CLAIM 13 . The semiconductor device according to claim 1 , wherein said substrate layer includes a gate electrode formed on a semiconductor substrate , an interlayer insulating film (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer) for covering said gate electrode , and a plurality of pad contact plugs which extend through said interlayer insulating film so as to be conductive to a source-drain region of said semiconductor substrate , said each wiring is a bit line formed over said substrate layer ; and said contact plug is a storage node contact plug which passes between said bit lines and is thereby conductive to one of said plurality of pad contact plugs , and said semiconductor device further comprising : a bit line contact plug which extends through said lower insulating film and said interlayer oxide film to thereby bring said bit line and part of said plurality of pad contact plugs to a conducting state , and a capacitor formed on said storage node contact plug . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (interlayer insulating film) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6653739B2 CLAIM 1 . A semiconductor device having a contact hole defined between adjacent two wirings by a self-aligning manner , comprising : a contact plug formed in said contact hole ; a substrate layer conductive to the bottom face of said contact plug ; an interlayer oxide film formed on said substrate layer ; a lower insulating film formed of a nitride based insulating film so as to cover the entire surface (first sub interlevel dielectric layer) of said interlayer oxide film except for said contact hole portion ; said two wirings formed on said lower insulating film with said contact hole interposed therebetween ; an upper insulating film formed of a nitride based insulating film with the same width as said each wiring so as to cover the upper surface of said each wiring ; and sidewalls formed of a nitride based insulating film so as to cover the side faces of said each wiring and the side faces of said upper insulating film , wherein said contact hole has an enlarged portion formed in the same layer as said interlayer oxide film , which has a diameter larger than an interval defined between said two wirings . US6653739B2 CLAIM 13 . The semiconductor device according to claim 1 , wherein said substrate layer includes a gate electrode formed on a semiconductor substrate , an interlayer insulating film (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer) for covering said gate electrode , and a plurality of pad contact plugs which extend through said interlayer insulating film so as to be conductive to a source-drain region of said semiconductor substrate , said each wiring is a bit line formed over said substrate layer ; and said contact plug is a storage node contact plug which passes between said bit lines and is thereby conductive to one of said plurality of pad contact plugs , and said semiconductor device further comprising : a bit line contact plug which extends through said lower insulating film and said interlayer oxide film to thereby bring said bit line and part of said plurality of pad contact plugs to a conducting state , and a capacitor formed on said storage node contact plug . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space (said sub) in a portion of said first sub interlevel dielectric (interlayer insulating film) layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space (storage node, drain region) in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US6653739B2 CLAIM 1 . A semiconductor device having a contact hole defined between adjacent two wirings by a self-aligning manner , comprising : a contact plug formed in said contact hole ; a substrate layer conductive to the bottom face of said contact plug ; an interlayer oxide film formed on said sub (first space) strate layer ; a lower insulating film formed of a nitride based insulating film so as to cover the entire surface (first sub interlevel dielectric layer) of said interlayer oxide film except for said contact hole portion ; said two wirings formed on said lower insulating film with said contact hole interposed therebetween ; an upper insulating film formed of a nitride based insulating film with the same width as said each wiring so as to cover the upper surface of said each wiring ; and sidewalls formed of a nitride based insulating film so as to cover the side faces of said each wiring and the side faces of said upper insulating film , wherein said contact hole has an enlarged portion formed in the same layer as said interlayer oxide film , which has a diameter larger than an interval defined between said two wirings . US6653739B2 CLAIM 13 . The semiconductor device according to claim 1 , wherein said substrate layer includes a gate electrode formed on a semiconductor substrate , an interlayer insulating film (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer) for covering said gate electrode , and a plurality of pad contact plugs which extend through said interlayer insulating film so as to be conductive to a source-drain region (second space, floating gate) of said semiconductor substrate , said each wiring is a bit line formed over said substrate layer ; and said contact plug is a storage node (second space, floating gate) contact plug which passes between said bit lines and is thereby conductive to one of said plurality of pad contact plugs , and said semiconductor device further comprising : a bit line contact plug which extends through said lower insulating film and said interlayer oxide film to thereby bring said bit line and part of said plurality of pad contact plugs to a conducting state , and a capacitor formed on said storage node contact plug . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (interlayer insulating film) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US6653739B2 CLAIM 1 . A semiconductor device having a contact hole defined between adjacent two wirings by a self-aligning manner , comprising : a contact plug formed in said contact hole ; a substrate layer conductive to the bottom face of said contact plug ; an interlayer oxide film formed on said substrate layer ; a lower insulating film formed of a nitride based insulating film so as to cover the entire surface (first sub interlevel dielectric layer) of said interlayer oxide film except for said contact hole portion ; said two wirings formed on said lower insulating film with said contact hole interposed therebetween ; an upper insulating film formed of a nitride based insulating film with the same width as said each wiring so as to cover the upper surface of said each wiring ; and sidewalls formed of a nitride based insulating film so as to cover the side faces of said each wiring and the side faces of said upper insulating film , wherein said contact hole has an enlarged portion formed in the same layer as said interlayer oxide film , which has a diameter larger than an interval defined between said two wirings . US6653739B2 CLAIM 13 . The semiconductor device according to claim 1 , wherein said substrate layer includes a gate electrode formed on a semiconductor substrate , an interlayer insulating film (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer) for covering said gate electrode , and a plurality of pad contact plugs which extend through said interlayer insulating film so as to be conductive to a source-drain region of said semiconductor substrate , said each wiring is a bit line formed over said substrate layer ; and said contact plug is a storage node contact plug which passes between said bit lines and is thereby conductive to one of said plurality of pad contact plugs , and said semiconductor device further comprising : a bit line contact plug which extends through said lower insulating film and said interlayer oxide film to thereby bring said bit line and part of said plurality of pad contact plugs to a conducting state , and a capacitor formed on said storage node contact plug . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (interlayer insulating film) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6653739B2 CLAIM 1 . A semiconductor device having a contact hole defined between adjacent two wirings by a self-aligning manner , comprising : a contact plug formed in said contact hole ; a substrate layer conductive to the bottom face of said contact plug ; an interlayer oxide film formed on said substrate layer ; a lower insulating film formed of a nitride based insulating film so as to cover the entire surface (first sub interlevel dielectric layer) of said interlayer oxide film except for said contact hole portion ; said two wirings formed on said lower insulating film with said contact hole interposed therebetween ; an upper insulating film formed of a nitride based insulating film with the same width as said each wiring so as to cover the upper surface of said each wiring ; and sidewalls formed of a nitride based insulating film so as to cover the side faces of said each wiring and the side faces of said upper insulating film , wherein said contact hole has an enlarged portion formed in the same layer as said interlayer oxide film , which has a diameter larger than an interval defined between said two wirings . US6653739B2 CLAIM 13 . The semiconductor device according to claim 1 , wherein said substrate layer includes a gate electrode formed on a semiconductor substrate , an interlayer insulating film (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer) for covering said gate electrode , and a plurality of pad contact plugs which extend through said interlayer insulating film so as to be conductive to a source-drain region of said semiconductor substrate , said each wiring is a bit line formed over said substrate layer ; and said contact plug is a storage node contact plug which passes between said bit lines and is thereby conductive to one of said plurality of pad contact plugs , and said semiconductor device further comprising : a bit line contact plug which extends through said lower insulating film and said interlayer oxide film to thereby bring said bit line and part of said plurality of pad contact plugs to a conducting state , and a capacitor formed on said storage node contact plug . |
| US7977797B2 CLAIM 13 . An integrated circuit of claim 11 further comprising a floating gate (storage node, drain region) . |
US6653739B2 CLAIM 13 . The semiconductor device according to claim 1 , wherein said substrate layer includes a gate electrode formed on a semiconductor substrate , an interlayer insulating film for covering said gate electrode , and a plurality of pad contact plugs which extend through said interlayer insulating film so as to be conductive to a source-drain region (second space, floating gate) of said semiconductor substrate , said each wiring is a bit line formed over said substrate layer ; and said contact plug is a storage node (second space, floating gate) contact plug which passes between said bit lines and is thereby conductive to one of said plurality of pad contact plugs , and said semiconductor device further comprising : a bit line contact plug which extends through said lower insulating film and said interlayer oxide film to thereby bring said bit line and part of said plurality of pad contact plugs to a conducting state , and a capacitor formed on said storage node contact plug . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | JP2003017664A Filed: 2001-07-04 Issued: 2003-01-17 半導体装置の製造方法 (Original Assignee) Matsushita Electric Ind Co Ltd; 松下電器産業株式会社 Eiji Fujii, Junji Noma, 英治 藤井, 淳史 野間 |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (製造方法, ７００) of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (ペロブスカイト構造, 容量絶縁膜, 少なくとも) layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
JP2003017664A CLAIM 1 【請求項１】 半導体基板上に、上部電極、結晶化して いる絶縁性金属酸化物よりなる容量絶縁膜 (second interlevel dielectric, interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) 及び下部電極 から構成される容量素子を形成する工程と、 熱処理によって除去可能な不純物を含有するアルミニウ ム酸化物層を少なくとも (second interlevel dielectric, interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) 前記容量素子を覆うように堆積 する工程と、 酸化性ガス雰囲気中において熱処理を行なうことによ り、前記アルミニウム酸化物層を堆積する際に前記絶縁 性金属酸化物が受けたダメージを回復すると共に前記ア ルミニウム酸化物層に含まれる前記不純物を除去する工 程と、 水素雰囲気中において熱処理を行なう工程とを備えてい ることを特徴とする半導体装置の製造方法 (metal layer coupling area) 。 JP2003017664A CLAIM 5 【請求項５】 前記アルミニウム酸化物層を堆積する際 の温度は４００℃以下であり、 前記酸化性ガス雰囲気中の熱処理の温度は７００ (metal layer coupling area) ℃以上 であることを特徴とする請求項１又は２に記載の半導体 装置の製造方法。 JP2003017664A CLAIM 6 【請求項６】 前記絶縁性金属酸化物は、ビスマス層状 ペロブスカイト構造 (second interlevel dielectric, interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) を有する強誘電体、チタン酸ジルコ ン酸鉛、チタン酸バリウムストロンチウム又は酸化タン タルであることを特徴とする請求項１又は２に記載の半 導体装置の製造方法。 |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (ペロブスカイト構造, 容量絶縁膜, 少なくとも) layer insulates said contact region . |
JP2003017664A CLAIM 1 【請求項１】 半導体基板上に、上部電極、結晶化して いる絶縁性金属酸化物よりなる容量絶縁膜 (second interlevel dielectric, interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) 及び下部電極 から構成される容量素子を形成する工程と、 熱処理によって除去可能な不純物を含有するアルミニウ ム酸化物層を少なくとも (second interlevel dielectric, interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) 前記容量素子を覆うように堆積 する工程と、 酸化性ガス雰囲気中において熱処理を行なうことによ り、前記アルミニウム酸化物層を堆積する際に前記絶縁 性金属酸化物が受けたダメージを回復すると共に前記ア ルミニウム酸化物層に含まれる前記不純物を除去する工 程と、 水素雰囲気中において熱処理を行なう工程とを備えてい ることを特徴とする半導体装置の製造方法。 JP2003017664A CLAIM 6 【請求項６】 前記絶縁性金属酸化物は、ビスマス層状 ペロブスカイト構造 (second interlevel dielectric, interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) を有する強誘電体、チタン酸ジルコ ン酸鉛、チタン酸バリウムストロンチウム又は酸化タン タルであることを特徴とする請求項１又は２に記載の半 導体装置の製造方法。 |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch stop layer protects lower layers during an etching process (酸化物層) . |
JP2003017664A CLAIM 1 【請求項１】 半導体基板上に、上部電極、結晶化して いる絶縁性金属酸化物よりなる容量絶縁膜及び下部電極 から構成される容量素子を形成する工程と、 熱処理によって除去可能な不純物を含有するアルミニウ ム酸化物層 (etching process) を少なくとも前記容量素子を覆うように堆積 する工程と、 酸化性ガス雰囲気中において熱処理を行なうことによ り、前記アルミニウム酸化物層を堆積する際に前記絶縁 性金属酸化物が受けたダメージを回復すると共に前記ア ルミニウム酸化物層に含まれる前記不純物を除去する工 程と、 水素雰囲気中において熱処理を行なう工程とを備えてい ることを特徴とする半導体装置の製造方法。 |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (ペロブスカイト構造, 容量絶縁膜, 少なくとも) layer insulates said contact region . |
JP2003017664A CLAIM 1 【請求項１】 半導体基板上に、上部電極、結晶化して いる絶縁性金属酸化物よりなる容量絶縁膜 (second interlevel dielectric, interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) 及び下部電極 から構成される容量素子を形成する工程と、 熱処理によって除去可能な不純物を含有するアルミニウ ム酸化物層を少なくとも (second interlevel dielectric, interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) 前記容量素子を覆うように堆積 する工程と、 酸化性ガス雰囲気中において熱処理を行なうことによ り、前記アルミニウム酸化物層を堆積する際に前記絶縁 性金属酸化物が受けたダメージを回復すると共に前記ア ルミニウム酸化物層に含まれる前記不純物を除去する工 程と、 水素雰囲気中において熱処理を行なう工程とを備えてい ることを特徴とする半導体装置の製造方法。 JP2003017664A CLAIM 6 【請求項６】 前記絶縁性金属酸化物は、ビスマス層状 ペロブスカイト構造 (second interlevel dielectric, interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) を有する強誘電体、チタン酸ジルコ ン酸鉛、チタン酸バリウムストロンチウム又は酸化タン タルであることを特徴とする請求項１又は２に記載の半 導体装置の製造方法。 |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area of said contact region permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area (製造方法, ７００) of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
JP2003017664A CLAIM 1 【請求項１】 半導体基板上に、上部電極、結晶化して いる絶縁性金属酸化物よりなる容量絶縁膜及び下部電極 から構成される容量素子を形成する工程と、 熱処理によって除去可能な不純物を含有するアルミニウ ム酸化物層を少なくとも前記容量素子を覆うように堆積 する工程と、 酸化性ガス雰囲気中において熱処理を行なうことによ り、前記アルミニウム酸化物層を堆積する際に前記絶縁 性金属酸化物が受けたダメージを回復すると共に前記ア ルミニウム酸化物層に含まれる前記不純物を除去する工 程と、 水素雰囲気中において熱処理を行なう工程とを備えてい ることを特徴とする半導体装置の製造方法 (metal layer coupling area) 。 JP2003017664A CLAIM 5 【請求項５】 前記アルミニウム酸化物層を堆積する際 の温度は４００℃以下であり、 前記酸化性ガス雰囲気中の熱処理の温度は７００ (metal layer coupling area) ℃以上 であることを特徴とする請求項１又は２に記載の半導体 装置の製造方法。 |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Å thick , said first sub interlevel dielectric (ペロブスカイト構造, 容量絶縁膜, 少なくとも) layer is in a range of about 1 , 000 to 2 , 000 Å thick , said second etch stop layer is in a range of about 300 to 800 Å thick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Å thick . |
JP2003017664A CLAIM 1 【請求項１】 半導体基板上に、上部電極、結晶化して いる絶縁性金属酸化物よりなる容量絶縁膜 (second interlevel dielectric, interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) 及び下部電極 から構成される容量素子を形成する工程と、 熱処理によって除去可能な不純物を含有するアルミニウ ム酸化物層を少なくとも (second interlevel dielectric, interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) 前記容量素子を覆うように堆積 する工程と、 酸化性ガス雰囲気中において熱処理を行なうことによ り、前記アルミニウム酸化物層を堆積する際に前記絶縁 性金属酸化物が受けたダメージを回復すると共に前記ア ルミニウム酸化物層に含まれる前記不純物を除去する工 程と、 水素雰囲気中において熱処理を行なう工程とを備えてい ることを特徴とする半導体装置の製造方法。 JP2003017664A CLAIM 6 【請求項６】 前記絶縁性金属酸化物は、ビスマス層状 ペロブスカイト構造 (second interlevel dielectric, interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) を有する強誘電体、チタン酸ジルコ ン酸鉛、チタン酸バリウムストロンチウム又は酸化タン タルであることを特徴とする請求項１又は２に記載の半 導体装置の製造方法。 |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric (ペロブスカイト構造, 容量絶縁膜, 少なくとも) layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range (あること) of about 0 . 16 μm to 0 . 18 μm wide . |
JP2003017664A CLAIM 1 【請求項１】 半導体基板上に、上部電極、結晶化して いる絶縁性金属酸化物よりなる容量絶縁膜 (second interlevel dielectric, interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) 及び下部電極 から構成される容量素子を形成する工程と、 熱処理によって除去可能な不純物を含有するアルミニウ ム酸化物層を少なくとも (second interlevel dielectric, interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) 前記容量素子を覆うように堆積 する工程と、 酸化性ガス雰囲気中において熱処理を行なうことによ り、前記アルミニウム酸化物層を堆積する際に前記絶縁 性金属酸化物が受けたダメージを回復すると共に前記ア ルミニウム酸化物層に含まれる前記不純物を除去する工 程と、 水素雰囲気中において熱処理を行なう工程とを備えてい ることを特徴とする半導体装置の製造方法。 JP2003017664A CLAIM 3 【請求項３】 前記酸化性ガス雰囲気は酸素ガスを含む 雰囲気であること (second range) を特徴とする請求項１又は２に記載の 半導体装置の製造方法。 JP2003017664A CLAIM 6 【請求項６】 前記絶縁性金属酸化物は、ビスマス層状 ペロブスカイト構造 (second interlevel dielectric, interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) を有する強誘電体、チタン酸ジルコ ン酸鉛、チタン酸バリウムストロンチウム又は酸化タン タルであることを特徴とする請求項１又は２に記載の半 導体装置の製造方法。 |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (ペロブスカイト構造, 容量絶縁膜, 少なくとも) layer and said second etch stop layer formed under a second interlevel dielectric (ペロブスカイト構造, 容量絶縁膜, 少なくとも) layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (製造方法, ７００) of said contact region . |
JP2003017664A CLAIM 1 【請求項１】 半導体基板上に、上部電極、結晶化して いる絶縁性金属酸化物よりなる容量絶縁膜 (second interlevel dielectric, interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) 及び下部電極 から構成される容量素子を形成する工程と、 熱処理によって除去可能な不純物を含有するアルミニウ ム酸化物層を少なくとも (second interlevel dielectric, interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) 前記容量素子を覆うように堆積 する工程と、 酸化性ガス雰囲気中において熱処理を行なうことによ り、前記アルミニウム酸化物層を堆積する際に前記絶縁 性金属酸化物が受けたダメージを回復すると共に前記ア ルミニウム酸化物層に含まれる前記不純物を除去する工 程と、 水素雰囲気中において熱処理を行なう工程とを備えてい ることを特徴とする半導体装置の製造方法 (metal layer coupling area) 。 JP2003017664A CLAIM 5 【請求項５】 前記アルミニウム酸化物層を堆積する際 の温度は４００℃以下であり、 前記酸化性ガス雰囲気中の熱処理の温度は７００ (metal layer coupling area) ℃以上 であることを特徴とする請求項１又は２に記載の半導体 装置の製造方法。 JP2003017664A CLAIM 6 【請求項６】 前記絶縁性金属酸化物は、ビスマス層状 ペロブスカイト構造 (second interlevel dielectric, interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) を有する強誘電体、チタン酸ジルコ ン酸鉛、チタン酸バリウムストロンチウム又は酸化タン タルであることを特徴とする請求項１又は２に記載の半 導体装置の製造方法。 |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Å thick , said first sub interlevel dielectric (ペロブスカイト構造, 容量絶縁膜, 少なくとも) layer is in a range of about 1 , 000 to 2 , 000 Å thick , said second etch stop layer is in a range of about 300 to 800 Å thick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Å thick . |
JP2003017664A CLAIM 1 【請求項１】 半導体基板上に、上部電極、結晶化して いる絶縁性金属酸化物よりなる容量絶縁膜 (second interlevel dielectric, interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) 及び下部電極 から構成される容量素子を形成する工程と、 熱処理によって除去可能な不純物を含有するアルミニウ ム酸化物層を少なくとも (second interlevel dielectric, interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) 前記容量素子を覆うように堆積 する工程と、 酸化性ガス雰囲気中において熱処理を行なうことによ り、前記アルミニウム酸化物層を堆積する際に前記絶縁 性金属酸化物が受けたダメージを回復すると共に前記ア ルミニウム酸化物層に含まれる前記不純物を除去する工 程と、 水素雰囲気中において熱処理を行なう工程とを備えてい ることを特徴とする半導体装置の製造方法。 JP2003017664A CLAIM 6 【請求項６】 前記絶縁性金属酸化物は、ビスマス層状 ペロブスカイト構造 (second interlevel dielectric, interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) を有する強誘電体、チタン酸ジルコ ン酸鉛、チタン酸バリウムストロンチウム又は酸化タン タルであることを特徴とする請求項１又は２に記載の半 導体装置の製造方法。 |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region is a first range of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range (あること) of about 0 . 16 μm to 0 . 18 μm wide . |
JP2003017664A CLAIM 3 【請求項３】 前記酸化性ガス雰囲気は酸素ガスを含む 雰囲気であること (second range) を特徴とする請求項１又は２に記載の 半導体装置の製造方法。 |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US6514805B2 Filed: 2001-06-30 Issued: 2003-02-04 Trench sidewall profile for device isolation (Original Assignee) Intel Corp (Current Assignee) Micron Technology Inc Daniel Xu, Erman Bengu, Ming Jin |
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| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer protects removal of a substrate material by an etch process (dielectric material) . |
US6514805B2 CLAIM 4 . The method of claim 1 , further comprising forming a dielectric material (etch process) in the first trench and the second trench . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US6514805B2 CLAIM 1 . A method comprising : forming a first trench in a substrate ; and forming (anti reflective coating) a second trench in the substrate by etching the substrate with an isotropic etch chemistry , the second trench intersecting the first trench and having a retrograde sidewall profile relative to a direction from a top of the trench to a bottom of the trench . |
| US7977797B2 CLAIM 13 . An integrated circuit of claim 11 further comprising a floating gate (first trenches) . |
US6514805B2 CLAIM 7 . A method comprising : defining a matrix of cells in a substrate by forming a plurality of first trenches (floating gate) and a plurality of second trenches , wherein forming the plurality of second trenches comprises etching the substrate with an isotropic etch chemistry , the plurality of second trenches intersecting the plurality of first trenches and having a retrograde sidewall profile relative to a direction from a top to a bottom of the respective trench ; and electrically isolating respective ones of the matrix of cells . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US6514805B2 CLAIM 1 . A method comprising : forming a first trench in a substrate ; and forming (anti reflective coating) a second trench in the substrate by etching the substrate with an isotropic etch chemistry , the second trench intersecting the first trench and having a retrograde sidewall profile relative to a direction from a top of the trench to a bottom of the trench . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | JP2003017467A Filed: 2001-06-28 Issued: 2003-01-17 半導体集積回路装置の製造方法および半導体集積回路装置 (Original Assignee) Thin Film Research Center, Hitachi''s Central Research Laboratory, Hitachi, Ibaraki, Japan; 株式会社日立製作所 Hiroyuki Enomoto, Masaru Nagasawa, Shoichi Uno, 正一 宇野, 裕之 榎本, 大 長澤 |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (製造方法) of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer (０．５) directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
JP2003017467A CLAIM 2 【請求項２】 （ａ）半導体基板上に下層から酸化シリ コンを主成分とする第１絶縁膜、炭化シリコンを主成分 とする第２絶縁膜および酸化シリコンを主成分とする第 ３絶縁膜を積層する工程、（ｂ）前記第３絶縁膜上に感 光性のマスキング層を形成する工程、（ｃ）前記マスキ ング層をマスクとし、フロロカーボン系ガス、酸素系ガ スおよび不活性ガスを含む第１エッチングガスを用いて 前記第３絶縁膜をエッチングする工程、（ｄ）前記マス キング層をマスクとし、フロロカーボン系ガス、酸素系 ガスおよび不活性ガスを含む第２エッチングガスを用い て前記第２絶縁膜をエッチングする工程、（ｅ）前記マ スキング層をマスクとし、フロロカーボン系ガス、酸素 系ガスおよび不活性ガスを含む第１エッチングガスを用 いて前記第１絶縁膜をエッチングする工程、を含み、前 記第１エッチングガスにおいて前記酸素系ガスの流量は 前記フロロカーボン系ガスの流量の１．５倍以下とし、 前記第２エッチングガスにおいて前記酸素系ガスの流量 は前記フロロカーボン系ガスの流量の０．５ (first range, first etch stop layer) 倍以上とす ることを特徴とする半導体集積回路装置の製造方法 (metal layer coupling area) 。 |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer (０．５) protects removal of a substrate material by an etch process . |
JP2003017467A CLAIM 2 【請求項２】 （ａ）半導体基板上に下層から酸化シリ コンを主成分とする第１絶縁膜、炭化シリコンを主成分 とする第２絶縁膜および酸化シリコンを主成分とする第 ３絶縁膜を積層する工程、（ｂ）前記第３絶縁膜上に感 光性のマスキング層を形成する工程、（ｃ）前記マスキ ング層をマスクとし、フロロカーボン系ガス、酸素系ガ スおよび不活性ガスを含む第１エッチングガスを用いて 前記第３絶縁膜をエッチングする工程、（ｄ）前記マス キング層をマスクとし、フロロカーボン系ガス、酸素系 ガスおよび不活性ガスを含む第２エッチングガスを用い て前記第２絶縁膜をエッチングする工程、（ｅ）前記マ スキング層をマスクとし、フロロカーボン系ガス、酸素 系ガスおよび不活性ガスを含む第１エッチングガスを用 いて前記第１絶縁膜をエッチングする工程、を含み、前 記第１エッチングガスにおいて前記酸素系ガスの流量は 前記フロロカーボン系ガスの流量の１．５倍以下とし、 前記第２エッチングガスにおいて前記酸素系ガスの流量 は前記フロロカーボン系ガスの流量の０．５ (first range, first etch stop layer) 倍以上とす ることを特徴とする半導体集積回路装置の製造方法。 |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area of said contact region permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area (製造方法) of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
JP2003017467A CLAIM 2 【請求項２】 （ａ）半導体基板上に下層から酸化シリ コンを主成分とする第１絶縁膜、炭化シリコンを主成分 とする第２絶縁膜および酸化シリコンを主成分とする第 ３絶縁膜を積層する工程、（ｂ）前記第３絶縁膜上に感 光性のマスキング層を形成する工程、（ｃ）前記マスキ ング層をマスクとし、フロロカーボン系ガス、酸素系ガ スおよび不活性ガスを含む第１エッチングガスを用いて 前記第３絶縁膜をエッチングする工程、（ｄ）前記マス キング層をマスクとし、フロロカーボン系ガス、酸素系 ガスおよび不活性ガスを含む第２エッチングガスを用い て前記第２絶縁膜をエッチングする工程、（ｅ）前記マ スキング層をマスクとし、フロロカーボン系ガス、酸素 系ガスおよび不活性ガスを含む第１エッチングガスを用 いて前記第１絶縁膜をエッチングする工程、を含み、前 記第１エッチングガスにおいて前記酸素系ガスの流量は 前記フロロカーボン系ガスの流量の１．５倍以下とし、 前記第２エッチングガスにおいて前記酸素系ガスの流量 は前記フロロカーボン系ガスの流量の０．５倍以上とす ることを特徴とする半導体集積回路装置の製造方法 (metal layer coupling area) 。 |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer (０．５) is in a range of about 300 to 800 Å thick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Å thick , said second etch stop layer is in a range of about 300 to 800 Å thick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Å thick . |
JP2003017467A CLAIM 2 【請求項２】 （ａ）半導体基板上に下層から酸化シリ コンを主成分とする第１絶縁膜、炭化シリコンを主成分 とする第２絶縁膜および酸化シリコンを主成分とする第 ３絶縁膜を積層する工程、（ｂ）前記第３絶縁膜上に感 光性のマスキング層を形成する工程、（ｃ）前記マスキ ング層をマスクとし、フロロカーボン系ガス、酸素系ガ スおよび不活性ガスを含む第１エッチングガスを用いて 前記第３絶縁膜をエッチングする工程、（ｄ）前記マス キング層をマスクとし、フロロカーボン系ガス、酸素系 ガスおよび不活性ガスを含む第２エッチングガスを用い て前記第２絶縁膜をエッチングする工程、（ｅ）前記マ スキング層をマスクとし、フロロカーボン系ガス、酸素 系ガスおよび不活性ガスを含む第１エッチングガスを用 いて前記第１絶縁膜をエッチングする工程、を含み、前 記第１エッチングガスにおいて前記酸素系ガスの流量は 前記フロロカーボン系ガスの流量の１．５倍以下とし、 前記第２エッチングガスにおいて前記酸素系ガスの流量 は前記フロロカーボン系ガスの流量の０．５ (first range, first etch stop layer) 倍以上とす ることを特徴とする半導体集積回路装置の製造方法。 |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric layer for said contact region is in a first range (０．５) of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
JP2003017467A CLAIM 2 【請求項２】 （ａ）半導体基板上に下層から酸化シリ コンを主成分とする第１絶縁膜、炭化シリコンを主成分 とする第２絶縁膜および酸化シリコンを主成分とする第 ３絶縁膜を積層する工程、（ｂ）前記第３絶縁膜上に感 光性のマスキング層を形成する工程、（ｃ）前記マスキ ング層をマスクとし、フロロカーボン系ガス、酸素系ガ スおよび不活性ガスを含む第１エッチングガスを用いて 前記第３絶縁膜をエッチングする工程、（ｄ）前記マス キング層をマスクとし、フロロカーボン系ガス、酸素系 ガスおよび不活性ガスを含む第２エッチングガスを用い て前記第２絶縁膜をエッチングする工程、（ｅ）前記マ スキング層をマスクとし、フロロカーボン系ガス、酸素 系ガスおよび不活性ガスを含む第１エッチングガスを用 いて前記第１絶縁膜をエッチングする工程、を含み、前 記第１エッチングガスにおいて前記酸素系ガスの流量は 前記フロロカーボン系ガスの流量の１．５倍以下とし、 前記第２エッチングガスにおいて前記酸素系ガスの流量 は前記フロロカーボン系ガスの流量の０．５ (first range, first etch stop layer) 倍以上とす ることを特徴とする半導体集積回路装置の製造方法。 |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer (０．５) and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (製造方法) of said contact region . |
JP2003017467A CLAIM 2 【請求項２】 （ａ）半導体基板上に下層から酸化シリ コンを主成分とする第１絶縁膜、炭化シリコンを主成分 とする第２絶縁膜および酸化シリコンを主成分とする第 ３絶縁膜を積層する工程、（ｂ）前記第３絶縁膜上に感 光性のマスキング層を形成する工程、（ｃ）前記マスキ ング層をマスクとし、フロロカーボン系ガス、酸素系ガ スおよび不活性ガスを含む第１エッチングガスを用いて 前記第３絶縁膜をエッチングする工程、（ｄ）前記マス キング層をマスクとし、フロロカーボン系ガス、酸素系 ガスおよび不活性ガスを含む第２エッチングガスを用い て前記第２絶縁膜をエッチングする工程、（ｅ）前記マ スキング層をマスクとし、フロロカーボン系ガス、酸素 系ガスおよび不活性ガスを含む第１エッチングガスを用 いて前記第１絶縁膜をエッチングする工程、を含み、前 記第１エッチングガスにおいて前記酸素系ガスの流量は 前記フロロカーボン系ガスの流量の１．５倍以下とし、 前記第２エッチングガスにおいて前記酸素系ガスの流量 は前記フロロカーボン系ガスの流量の０．５ (first range, first etch stop layer) 倍以上とす ることを特徴とする半導体集積回路装置の製造方法 (metal layer coupling area) 。 |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer (０．５) is in a range of about 300 to 800 Å thick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Å thick , said second etch stop layer is in a range of about 300 to 800 Å thick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Å thick . |
JP2003017467A CLAIM 2 【請求項２】 （ａ）半導体基板上に下層から酸化シリ コンを主成分とする第１絶縁膜、炭化シリコンを主成分 とする第２絶縁膜および酸化シリコンを主成分とする第 ３絶縁膜を積層する工程、（ｂ）前記第３絶縁膜上に感 光性のマスキング層を形成する工程、（ｃ）前記マスキ ング層をマスクとし、フロロカーボン系ガス、酸素系ガ スおよび不活性ガスを含む第１エッチングガスを用いて 前記第３絶縁膜をエッチングする工程、（ｄ）前記マス キング層をマスクとし、フロロカーボン系ガス、酸素系 ガスおよび不活性ガスを含む第２エッチングガスを用い て前記第２絶縁膜をエッチングする工程、（ｅ）前記マ スキング層をマスクとし、フロロカーボン系ガス、酸素 系ガスおよび不活性ガスを含む第１エッチングガスを用 いて前記第１絶縁膜をエッチングする工程、を含み、前 記第１エッチングガスにおいて前記酸素系ガスの流量は 前記フロロカーボン系ガスの流量の１．５倍以下とし、 前記第２エッチングガスにおいて前記酸素系ガスの流量 は前記フロロカーボン系ガスの流量の０．５ (first range, first etch stop layer) 倍以上とす ることを特徴とする半導体集積回路装置の製造方法。 |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region is a first range (０．５) of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
JP2003017467A CLAIM 2 【請求項２】 （ａ）半導体基板上に下層から酸化シリ コンを主成分とする第１絶縁膜、炭化シリコンを主成分 とする第２絶縁膜および酸化シリコンを主成分とする第 ３絶縁膜を積層する工程、（ｂ）前記第３絶縁膜上に感 光性のマスキング層を形成する工程、（ｃ）前記マスキ ング層をマスクとし、フロロカーボン系ガス、酸素系ガ スおよび不活性ガスを含む第１エッチングガスを用いて 前記第３絶縁膜をエッチングする工程、（ｄ）前記マス キング層をマスクとし、フロロカーボン系ガス、酸素系 ガスおよび不活性ガスを含む第２エッチングガスを用い て前記第２絶縁膜をエッチングする工程、（ｅ）前記マ スキング層をマスクとし、フロロカーボン系ガス、酸素 系ガスおよび不活性ガスを含む第１エッチングガスを用 いて前記第１絶縁膜をエッチングする工程、を含み、前 記第１エッチングガスにおいて前記酸素系ガスの流量は 前記フロロカーボン系ガスの流量の１．５倍以下とし、 前記第２エッチングガスにおいて前記酸素系ガスの流量 は前記フロロカーボン系ガスの流量の０．５ (first range, first etch stop layer) 倍以上とす ることを特徴とする半導体集積回路装置の製造方法。 |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | JP2002289810A Filed: 2001-03-28 Issued: 2002-10-04 半導体装置およびその製造方法 (Original Assignee) Toshiba Corp; 株式会社東芝 Osamu Arisumi, Keitarou Imai, Katsuaki Natori, Koji Yamakawa, 馨太郎 今井, 克晃 名取, 晃司 山川, 修 有隅 |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (製造方法) of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation (前記誘) between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (キャパシタ, 誘電体膜) layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
JP2002289810A CLAIM 2 【請求項２】半導体基板上に形成された導電性のプラグ と、 前記プラグの上面を覆う炭化珪素膜と、 前記炭化珪素膜を介して前記プラグと電気的に接続する 電極と、 前記電極上に形成され、強誘電体材料または高誘電体材 料を主成分とする誘電体膜 (interlevel dielectric, second interlevel dielectric layer) とを具備してなることを特徴 とする半導体装置。 JP2002289810A CLAIM 4 【請求項４】前記電極および前記誘 (electrical insulation) 電体膜はキャパシタ (interlevel dielectric, second interlevel dielectric layer) を構成するものであり、かつ前記電極は前記誘電体膜の 下に形成されたものであることを特徴とする請求項３に 記載の半導体装置。 JP2002289810A CLAIM 8 【請求項８】半導体基板上に導電性のプラグを形成する 工程と、 前記プラグの上面を覆う炭化珪素膜を形成する工程と、 前記炭化珪素膜上に前記プラグと電気的に接続する電極 を形成する工程と、 前記電極上に強誘電体または高誘電体を主成分とする誘 電体膜を形成する工程と、 酸化性雰囲気中で前記誘電体膜を熱処理する工程とを有 することを特徴とする半導体装置の製造方法 (metal layer coupling area) 。 |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (キャパシタ, 誘電体膜) layer insulates said contact region . |
JP2002289810A CLAIM 2 【請求項２】半導体基板上に形成された導電性のプラグ と、 前記プラグの上面を覆う炭化珪素膜と、 前記炭化珪素膜を介して前記プラグと電気的に接続する 電極と、 前記電極上に形成され、強誘電体材料または高誘電体材 料を主成分とする誘電体膜 (interlevel dielectric, second interlevel dielectric layer) とを具備してなることを特徴 とする半導体装置。 JP2002289810A CLAIM 4 【請求項４】前記電極および前記誘電体膜はキャパシタ (interlevel dielectric, second interlevel dielectric layer) を構成するものであり、かつ前記電極は前記誘電体膜の 下に形成されたものであることを特徴とする請求項３に 記載の半導体装置。 |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch stop layer protects lower layers during an etching process (１００) . |
JP2002289810A CLAIM 7 【請求項７】前記炭化珪素膜の膜厚は、１００ (etching process) ｎｍ以下 であることを特徴とする請求項１ないし６のいずれか１ 項に記載の半導体装置。 |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (キャパシタ, 誘電体膜) layer insulates said contact region . |
JP2002289810A CLAIM 2 【請求項２】半導体基板上に形成された導電性のプラグ と、 前記プラグの上面を覆う炭化珪素膜と、 前記炭化珪素膜を介して前記プラグと電気的に接続する 電極と、 前記電極上に形成され、強誘電体材料または高誘電体材 料を主成分とする誘電体膜 (interlevel dielectric, second interlevel dielectric layer) とを具備してなることを特徴 とする半導体装置。 JP2002289810A CLAIM 4 【請求項４】前記電極および前記誘電体膜はキャパシタ (interlevel dielectric, second interlevel dielectric layer) を構成するものであり、かつ前記電極は前記誘電体膜の 下に形成されたものであることを特徴とする請求項３に 記載の半導体装置。 |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area of said contact region permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area (製造方法) of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
JP2002289810A CLAIM 8 【請求項８】半導体基板上に導電性のプラグを形成する 工程と、 前記プラグの上面を覆う炭化珪素膜を形成する工程と、 前記炭化珪素膜上に前記プラグと電気的に接続する電極 を形成する工程と、 前記電極上に強誘電体または高誘電体を主成分とする誘 電体膜を形成する工程と、 酸化性雰囲気中で前記誘電体膜を熱処理する工程とを有 することを特徴とする半導体装置の製造方法 (metal layer coupling area) 。 |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Å thick , said first sub interlevel dielectric (キャパシタ, 誘電体膜) layer is in a range of about 1 , 000 to 2 , 000 Å thick , said second etch stop layer is in a range of about 300 to 800 Å thick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Å thick . |
JP2002289810A CLAIM 2 【請求項２】半導体基板上に形成された導電性のプラグ と、 前記プラグの上面を覆う炭化珪素膜と、 前記炭化珪素膜を介して前記プラグと電気的に接続する 電極と、 前記電極上に形成され、強誘電体材料または高誘電体材 料を主成分とする誘電体膜 (interlevel dielectric, second interlevel dielectric layer) とを具備してなることを特徴 とする半導体装置。 JP2002289810A CLAIM 4 【請求項４】前記電極および前記誘電体膜はキャパシタ (interlevel dielectric, second interlevel dielectric layer) を構成するものであり、かつ前記電極は前記誘電体膜の 下に形成されたものであることを特徴とする請求項３に 記載の半導体装置。 |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric (キャパシタ, 誘電体膜) layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range (あること) of about 0 . 16 μm to 0 . 18 μm wide . |
JP2002289810A CLAIM 2 【請求項２】半導体基板上に形成された導電性のプラグ と、 前記プラグの上面を覆う炭化珪素膜と、 前記炭化珪素膜を介して前記プラグと電気的に接続する 電極と、 前記電極上に形成され、強誘電体材料または高誘電体材 料を主成分とする誘電体膜 (interlevel dielectric, second interlevel dielectric layer) とを具備してなることを特徴 とする半導体装置。 JP2002289810A CLAIM 3 【請求項３】前記プラグは、前記半導体基板の表面に形 成されたトランジスタの活性領域に電気的に接続したも のであること (second range) を特徴とする請求項１または２に記載の半 導体装置。 JP2002289810A CLAIM 4 【請求項４】前記電極および前記誘電体膜はキャパシタ (interlevel dielectric, second interlevel dielectric layer) を構成するものであり、かつ前記電極は前記誘電体膜の 下に形成されたものであることを特徴とする請求項３に 記載の半導体装置。 |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (キャパシタ, 誘電体膜) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (製造方法) of said contact region . |
JP2002289810A CLAIM 2 【請求項２】半導体基板上に形成された導電性のプラグ と、 前記プラグの上面を覆う炭化珪素膜と、 前記炭化珪素膜を介して前記プラグと電気的に接続する 電極と、 前記電極上に形成され、強誘電体材料または高誘電体材 料を主成分とする誘電体膜 (interlevel dielectric, second interlevel dielectric layer) とを具備してなることを特徴 とする半導体装置。 JP2002289810A CLAIM 4 【請求項４】前記電極および前記誘電体膜はキャパシタ (interlevel dielectric, second interlevel dielectric layer) を構成するものであり、かつ前記電極は前記誘電体膜の 下に形成されたものであることを特徴とする請求項３に 記載の半導体装置。 JP2002289810A CLAIM 8 【請求項８】半導体基板上に導電性のプラグを形成する 工程と、 前記プラグの上面を覆う炭化珪素膜を形成する工程と、 前記炭化珪素膜上に前記プラグと電気的に接続する電極 を形成する工程と、 前記電極上に強誘電体または高誘電体を主成分とする誘 電体膜を形成する工程と、 酸化性雰囲気中で前記誘電体膜を熱処理する工程とを有 することを特徴とする半導体装置の製造方法 (metal layer coupling area) 。 |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Å thick , said first sub interlevel dielectric (キャパシタ, 誘電体膜) layer is in a range of about 1 , 000 to 2 , 000 Å thick , said second etch stop layer is in a range of about 300 to 800 Å thick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Å thick . |
JP2002289810A CLAIM 2 【請求項２】半導体基板上に形成された導電性のプラグ と、 前記プラグの上面を覆う炭化珪素膜と、 前記炭化珪素膜を介して前記プラグと電気的に接続する 電極と、 前記電極上に形成され、強誘電体材料または高誘電体材 料を主成分とする誘電体膜 (interlevel dielectric, second interlevel dielectric layer) とを具備してなることを特徴 とする半導体装置。 JP2002289810A CLAIM 4 【請求項４】前記電極および前記誘電体膜はキャパシタ (interlevel dielectric, second interlevel dielectric layer) を構成するものであり、かつ前記電極は前記誘電体膜の 下に形成されたものであることを特徴とする請求項３に 記載の半導体装置。 |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region is a first range of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range (あること) of about 0 . 16 μm to 0 . 18 μm wide . |
JP2002289810A CLAIM 3 【請求項３】前記プラグは、前記半導体基板の表面に形 成されたトランジスタの活性領域に電気的に接続したも のであること (second range) を特徴とする請求項１または２に記載の半 導体装置。 |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | CN1418374A Filed: 2001-03-15 Issued: 2003-05-14 叠层中的垂直电互连 (Original Assignee) 薄膜电子有限公司 P·-E·诺达尔, H·G·古德森, G·I·雷斯塔德, G·古斯塔夫森 |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer (衬底中) over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
CN1418374A CLAIM 1 . 一种存储器和/或数据处理器件，具有至少两个相互部分或完全重叠的叠层，其中所述层由衬底支撑或通过交替地形成所述叠置层的夹层的自支撑结构，并且其中叠层中的至少两层包括电连接到至少另一层和/或所述衬底中 (second etch stop layer, second etch stop layers) 的存储器和/或处理电路的存储器和/或处理电路，特征在于：所述层相互关联设置，使邻接层在所述器件的至少一个边缘形成交错结构，所述结构中至少两层的边缘形成一组倾角或倾斜的台阶，其中每个台阶具有对应于每层厚度的高度，并且提供至少一个边缘电导体越过一层的边缘并一次下降一个台阶，能连接到交错结构中随后的任何层中的电导体。 |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer protects removal of a substrate material (层形成) by an etch process . |
CN1418374A CLAIM 4 . 一种存储器和/或数据处理器件的制造方法，所述器件具有至少两个相互部分或完全重叠的叠层，其中所述层由衬底支撑或通过交替地形成所述叠置层的夹层的自支撑结构，并且其中叠层中的至少两层包括电连接到至少另一层和/或衬底中的存储器和/或处理电路的存储器和/或处理电路，其中方法的特征在于：包括以下步骤：连续地添加所述各层，一次一层使各层形成 (substrate material) 交错结构；提供的一层或多层具有至少一个电接触焊盘，该电接触焊盘用于连接到一个或多个层间边缘连接体。 |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch stop layer (衬底中) protects lower layers during an etching process . |
CN1418374A CLAIM 1 . 一种存储器和/或数据处理器件，具有至少两个相互部分或完全重叠的叠层，其中所述层由衬底支撑或通过交替地形成所述叠置层的夹层的自支撑结构，并且其中叠层中的至少两层包括电连接到至少另一层和/或所述衬底中 (second etch stop layer, second etch stop layers) 的存储器和/或处理电路的存储器和/或处理电路，特征在于：所述层相互关联设置，使邻接层在所述器件的至少一个边缘形成交错结构，所述结构中至少两层的边缘形成一组倾角或倾斜的台阶，其中每个台阶具有对应于每层厚度的高度，并且提供至少一个边缘电导体越过一层的边缘并一次下降一个台阶，能连接到交错结构中随后的任何层中的电导体。 |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Å thick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Å thick , said second etch stop layer (衬底中) is in a range of about 300 to 800 Å thick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Å thick . |
CN1418374A CLAIM 1 . 一种存储器和/或数据处理器件，具有至少两个相互部分或完全重叠的叠层，其中所述层由衬底支撑或通过交替地形成所述叠置层的夹层的自支撑结构，并且其中叠层中的至少两层包括电连接到至少另一层和/或所述衬底中 (second etch stop layer, second etch stop layers) 的存储器和/或处理电路的存储器和/或处理电路，特征在于：所述层相互关联设置，使邻接层在所述器件的至少一个边缘形成交错结构，所述结构中至少两层的边缘形成一组倾角或倾斜的台阶，其中每个台阶具有对应于每层厚度的高度，并且提供至少一个边缘电导体越过一层的边缘并一次下降一个台阶，能连接到交错结构中随后的任何层中的电导体。 |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer (衬底中) wherein said first etch stop layer and said second etch stop layers (衬底中) have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process (一个或多个) ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
CN1418374A CLAIM 1 . 一种存储器和/或数据处理器件，具有至少两个相互部分或完全重叠的叠层，其中所述层由衬底支撑或通过交替地形成所述叠置层的夹层的自支撑结构，并且其中叠层中的至少两层包括电连接到至少另一层和/或所述衬底中 (second etch stop layer, second etch stop layers) 的存储器和/或处理电路的存储器和/或处理电路，特征在于：所述层相互关联设置，使邻接层在所述器件的至少一个边缘形成交错结构，所述结构中至少两层的边缘形成一组倾角或倾斜的台阶，其中每个台阶具有对应于每层厚度的高度，并且提供至少一个边缘电导体越过一层的边缘并一次下降一个台阶，能连接到交错结构中随后的任何层中的电导体。 CN1418374A CLAIM 4 . 一种存储器和/或数据处理器件的制造方法，所述器件具有至少两个相互部分或完全重叠的叠层，其中所述层由衬底支撑或通过交替地形成所述叠置层的夹层的自支撑结构，并且其中叠层中的至少两层包括电连接到至少另一层和/或衬底中的存储器和/或处理电路的存储器和/或处理电路，其中方法的特征在于：包括以下步骤：连续地添加所述各层，一次一层使各层形成交错结构；提供的一层或多层具有至少一个电接触焊盘，该电接触焊盘用于连接到一个或多个 (lithography process) 层间边缘连接体。 |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Å thick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Å thick , said second etch stop layer (衬底中) is in a range of about 300 to 800 Å thick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Å thick . |
CN1418374A CLAIM 1 . 一种存储器和/或数据处理器件，具有至少两个相互部分或完全重叠的叠层，其中所述层由衬底支撑或通过交替地形成所述叠置层的夹层的自支撑结构，并且其中叠层中的至少两层包括电连接到至少另一层和/或所述衬底中 (second etch stop layer, second etch stop layers) 的存储器和/或处理电路的存储器和/或处理电路，特征在于：所述层相互关联设置，使邻接层在所述器件的至少一个边缘形成交错结构，所述结构中至少两层的边缘形成一组倾角或倾斜的台阶，其中每个台阶具有对应于每层厚度的高度，并且提供至少一个边缘电导体越过一层的边缘并一次下降一个台阶，能连接到交错结构中随后的任何层中的电导体。 |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US6383857B2 Filed: 2001-02-22 Issued: 2002-05-07 Semiconductor device and method for manufacturing the same (Original Assignee) Mitsubishi Electric Corp (Current Assignee) Mitsubishi Electric Corp Takashi Terauchi, Hiroki Shinkawata |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (film side) of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch (first etch) stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch (second etch) stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US6383857B2 CLAIM 1 . A method for manufacturing a semiconductor device comprising the steps of : forming an oxide film on a semiconductor substrate ; forming a wiring layer on said oxide film ; forming a nitride film top wall layer on said wiring layer ; forming wiring patterns and nitride film top walls by shaping said wiring layer and said nitride film top wall layer into suitable wiring pattern shape ; forming nitride film side (metal layer coupling area) walls laterally to said wiring patterns and to said nitride film top walls ; after depositing an interlayer oxide film , forming contact holes interposingly between said wiring patterns so that said nitride film top walls and said nitride film side walls will remain and that a side edge surface of said oxide film will be retracted from a frontal edge of the corresponding nitride film side wall into the corresponding wiring pattern ; and forming contacts inside said contact holes . US6383857B2 CLAIM 2 . The method for manufacturing a semiconductor device according to claim 1 , wherein said step for forming the wiring pattern includes a first etch (first etch) ing step for etching said oxide film so that a top of the oxide film not covered with said wiring patterns will be lower than a top of the oxide film under said wiring patterns . US6383857B2 CLAIM 3 . The method for manufacturing a semiconductor device according to claim 2 , wherein said step for forming the contact hole includes a second etch (second etch) ing step for etching said oxide film so that a side edge surface of said oxide film will be located beneath of the corresponding nitride film side wall . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch (first etch) stop layer protects removal of a substrate material (forming contact holes) by an etch process . |
US6383857B2 CLAIM 1 . A method for manufacturing a semiconductor device comprising the steps of : forming an oxide film on a semiconductor substrate ; forming a wiring layer on said oxide film ; forming a nitride film top wall layer on said wiring layer ; forming wiring patterns and nitride film top walls by shaping said wiring layer and said nitride film top wall layer into suitable wiring pattern shape ; forming nitride film side walls laterally to said wiring patterns and to said nitride film top walls ; after depositing an interlayer oxide film , forming contact holes (substrate material) interposingly between said wiring patterns so that said nitride film top walls and said nitride film side walls will remain and that a side edge surface of said oxide film will be retracted from a frontal edge of the corresponding nitride film side wall into the corresponding wiring pattern ; and forming contacts inside said contact holes . US6383857B2 CLAIM 2 . The method for manufacturing a semiconductor device according to claim 1 , wherein said step for forming the wiring pattern includes a first etch (first etch) ing step for etching said oxide film so that a top of the oxide film not covered with said wiring patterns will be lower than a top of the oxide film under said wiring patterns . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch (second etch) stop layer protects lower layers during an etching process . |
US6383857B2 CLAIM 3 . The method for manufacturing a semiconductor device according to claim 2 , wherein said step for forming the contact hole includes a second etch (second etch) ing step for etching said oxide film so that a side edge surface of said oxide film will be located beneath of the corresponding nitride film side wall . |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area of said contact region permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area (film side) of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
US6383857B2 CLAIM 1 . A method for manufacturing a semiconductor device comprising the steps of : forming an oxide film on a semiconductor substrate ; forming a wiring layer on said oxide film ; forming a nitride film top wall layer on said wiring layer ; forming wiring patterns and nitride film top walls by shaping said wiring layer and said nitride film top wall layer into suitable wiring pattern shape ; forming nitride film side (metal layer coupling area) walls laterally to said wiring patterns and to said nitride film top walls ; after depositing an interlayer oxide film , forming contact holes interposingly between said wiring patterns so that said nitride film top walls and said nitride film side walls will remain and that a side edge surface of said oxide film will be retracted from a frontal edge of the corresponding nitride film side wall into the corresponding wiring pattern ; and forming contacts inside said contact holes . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch (first etch) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (second etch) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6383857B2 CLAIM 2 . The method for manufacturing a semiconductor device according to claim 1 , wherein said step for forming the wiring pattern includes a first etch (first etch) ing step for etching said oxide film so that a top of the oxide film not covered with said wiring patterns will be lower than a top of the oxide film under said wiring patterns . US6383857B2 CLAIM 3 . The method for manufacturing a semiconductor device according to claim 2 , wherein said step for forming the contact hole includes a second etch (second etch) ing step for etching said oxide film so that a side edge surface of said oxide film will be located beneath of the corresponding nitride film side wall . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US6383857B2 CLAIM 1 . A method for manufacturing a semiconductor device comprising the steps of : forming an oxide film on a semiconductor substrate ; forming a wiring layer on said oxide film ; forming a nitride film top wall layer on said wiring layer ; forming wiring patterns and nitride film top walls by shaping said wiring layer and said nitride film top wall layer into suitable wiring pattern shape ; forming nitride film side walls laterally to said wiring patterns and to said nitride film top walls ; after depositing an interlayer oxide film , forming contact holes interposingly between said wiring patterns so that said nitride film top walls and said nitride film side walls will remain and that a side edge surface of said oxide film will be retracted from a frontal edge of the corresponding nitride film side wall into the corresponding wiring pattern ; and forming (anti reflective coating) contacts inside said contact holes . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch (first etch) stop layer and a second etch (second etch) stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom (bottom walls) , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (film side) of said contact region . |
US6383857B2 CLAIM 1 . A method for manufacturing a semiconductor device comprising the steps of : forming an oxide film on a semiconductor substrate ; forming a wiring layer on said oxide film ; forming a nitride film top wall layer on said wiring layer ; forming wiring patterns and nitride film top walls by shaping said wiring layer and said nitride film top wall layer into suitable wiring pattern shape ; forming nitride film side (metal layer coupling area) walls laterally to said wiring patterns and to said nitride film top walls ; after depositing an interlayer oxide film , forming contact holes interposingly between said wiring patterns so that said nitride film top walls and said nitride film side walls will remain and that a side edge surface of said oxide film will be retracted from a frontal edge of the corresponding nitride film side wall into the corresponding wiring pattern ; and forming contacts inside said contact holes . US6383857B2 CLAIM 2 . The method for manufacturing a semiconductor device according to claim 1 , wherein said step for forming the wiring pattern includes a first etch (first etch) ing step for etching said oxide film so that a top of the oxide film not covered with said wiring patterns will be lower than a top of the oxide film under said wiring patterns . US6383857B2 CLAIM 3 . The method for manufacturing a semiconductor device according to claim 2 , wherein said step for forming the contact hole includes a second etch (second etch) ing step for etching said oxide film so that a side edge surface of said oxide film will be located beneath of the corresponding nitride film side wall . US6383857B2 CLAIM 4 . The method for manufacturing a semiconductor device according to claim 1 , further comprising the step of forming a nitride film bottom wall layer on top of said oxide film ; wherein said step for forming the wiring layer is arranged to form said wiring layer on said nitride film bottom wall layer ; and wherein said step for forming the wiring patterns and the nitride film top walls includes a step for forming nitride film bottom walls (contact bottom) by shaping said nitride film bottom wall layer into the suitable wiring pattern shape in the same manner as with said wiring layer and said nitride film top wall layer . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch (first etch) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (second etch) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6383857B2 CLAIM 2 . The method for manufacturing a semiconductor device according to claim 1 , wherein said step for forming the wiring pattern includes a first etch (first etch) ing step for etching said oxide film so that a top of the oxide film not covered with said wiring patterns will be lower than a top of the oxide film under said wiring patterns . US6383857B2 CLAIM 3 . The method for manufacturing a semiconductor device according to claim 2 , wherein said step for forming the contact hole includes a second etch (second etch) ing step for etching said oxide film so that a side edge surface of said oxide film will be located beneath of the corresponding nitride film side wall . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US6383857B2 CLAIM 1 . A method for manufacturing a semiconductor device comprising the steps of : forming an oxide film on a semiconductor substrate ; forming a wiring layer on said oxide film ; forming a nitride film top wall layer on said wiring layer ; forming wiring patterns and nitride film top walls by shaping said wiring layer and said nitride film top wall layer into suitable wiring pattern shape ; forming nitride film side walls laterally to said wiring patterns and to said nitride film top walls ; after depositing an interlayer oxide film , forming contact holes interposingly between said wiring patterns so that said nitride film top walls and said nitride film side walls will remain and that a side edge surface of said oxide film will be retracted from a frontal edge of the corresponding nitride film side wall into the corresponding wiring pattern ; and forming (anti reflective coating) contacts inside said contact holes . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US20020025669A1 Filed: 2001-01-05 Issued: 2002-02-28 Methods of forming a contact structure in a semiconductor device (Original Assignee) Samsung Electronics Co Ltd (Current Assignee) Samsung Electronics Co Ltd Min-wk Hwang, Jun-Yong Noh |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch (etch stop layer, gate pattern) stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer (entire surface) over said first etch stop layer ; a second etch (etch stop layer, gate pattern) stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US20020025669A1 CLAIM 2 . The method according to claim 1 , wherein prior to forming the interlayer insulating layer , the method comprises : forming a plurality of parallel interconnection patterns on the semiconductor substrate ; and forming a conformal etch stop layer (second etch, multiple etch, second etch stop layer) on the entire surface (first sub interlevel dielectric layer) of the resultant structure having the interconnection patterns . US20020025669A1 CLAIM 11 . A method of forming a contact structure in a semiconductor device having a cell array region and a peripheral region , the method comprising : forming an isolation layer at a predetermined portion of a semiconductor substrate to define active regions ; forming a gate insulating layer on the active regions ; sequentially forming a conductive layer and a capping insulating layer on the resultant stricture having the gate insulating layer ; sequentially patterning the capping insulating layer and the conductive layer to form a plurality of parallel word line patterns crossing over the active regions in the cell array region and to form at least one gate pattern (second etch, multiple etch, second etch stop layer) crossing over the active region in the peripheral region ; forming an insulating layer on the resultant structure having the word line patterns and the gate pattern ; forming a photoresist pattern to expose the peripheral region ; anisotropically etching the insulating layer using the photoresist pattern as an etching mask to form a spacer on a sidewall of the gate pattern ; removing the photoresist pattern ; forming an etch stop layer on the resultant structure where the phtoresist pattern is removed ; forming an interlayer insulating layer on the etch stop layer to fill gap regions between the word line patterns , the interlayer insulating layer containing impurities ; sequentially patterning the interlayer insulating layer , the etch stop layer and the insulating layer to form a plurality of pad contact holes exposing the active region in the cell array region ; forming conductive pads in the pad contact holes ; and thermally oxidizing the resultant structure having the conductive pads , thereby forming a thermal oxide layer on a top surface of the conductive pad and at an interface between the conductive pad and the interlayer insulating layer . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric layer (entire surface) insulates said contact region . |
US20020025669A1 CLAIM 2 . The method according to claim 1 , wherein prior to forming the interlayer insulating layer , the method comprises : forming a plurality of parallel interconnection patterns on the semiconductor substrate ; and forming a conformal etch stop layer on the entire surface (first sub interlevel dielectric layer) of the resultant structure having the interconnection patterns . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch (etch stop layer, gate pattern) stop layer protects lower layers during an etching process (doped polysilicon) . |
US20020025669A1 CLAIM 2 . The method according to claim 1 , wherein prior to forming the interlayer insulating layer , the method comprises : forming a plurality of parallel interconnection patterns on the semiconductor substrate ; and forming a conformal etch stop layer (second etch, multiple etch, second etch stop layer) on the entire surface of the resultant structure having the interconnection patterns . US20020025669A1 CLAIM 10 . The method according to claim 1 , wherein the conductive pad is formed of a doped polysilicon (etching process) layer . US20020025669A1 CLAIM 11 . A method of forming a contact structure in a semiconductor device having a cell array region and a peripheral region , the method comprising : forming an isolation layer at a predetermined portion of a semiconductor substrate to define active regions ; forming a gate insulating layer on the active regions ; sequentially forming a conductive layer and a capping insulating layer on the resultant stricture having the gate insulating layer ; sequentially patterning the capping insulating layer and the conductive layer to form a plurality of parallel word line patterns crossing over the active regions in the cell array region and to form at least one gate pattern (second etch, multiple etch, second etch stop layer) crossing over the active region in the peripheral region ; forming an insulating layer on the resultant structure having the word line patterns and the gate pattern ; forming a photoresist pattern to expose the peripheral region ; anisotropically etching the insulating layer using the photoresist pattern as an etching mask to form a spacer on a sidewall of the gate pattern ; removing the photoresist pattern ; forming an etch stop layer on the resultant structure where the phtoresist pattern is removed ; forming an interlayer insulating layer on the etch stop layer to fill gap regions between the word line patterns , the interlayer insulating layer containing impurities ; sequentially patterning the interlayer insulating layer , the etch stop layer and the insulating layer to form a plurality of pad contact holes exposing the active region in the cell array region ; forming conductive pads in the pad contact holes ; and thermally oxidizing the resultant structure having the conductive pads , thereby forming a thermal oxide layer on a top surface of the conductive pad and at an interface between the conductive pad and the interlayer insulating layer . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer (entire surface) is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (etch stop layer, gate pattern) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US20020025669A1 CLAIM 2 . The method according to claim 1 , wherein prior to forming the interlayer insulating layer , the method comprises : forming a plurality of parallel interconnection patterns on the semiconductor substrate ; and forming a conformal etch stop layer (second etch, multiple etch, second etch stop layer) on the entire surface (first sub interlevel dielectric layer) of the resultant structure having the interconnection patterns . US20020025669A1 CLAIM 11 . A method of forming a contact structure in a semiconductor device having a cell array region and a peripheral region , the method comprising : forming an isolation layer at a predetermined portion of a semiconductor substrate to define active regions ; forming a gate insulating layer on the active regions ; sequentially forming a conductive layer and a capping insulating layer on the resultant stricture having the gate insulating layer ; sequentially patterning the capping insulating layer and the conductive layer to form a plurality of parallel word line patterns crossing over the active regions in the cell array region and to form at least one gate pattern (second etch, multiple etch, second etch stop layer) crossing over the active region in the peripheral region ; forming an insulating layer on the resultant structure having the word line patterns and the gate pattern ; forming a photoresist pattern to expose the peripheral region ; anisotropically etching the insulating layer using the photoresist pattern as an etching mask to form a spacer on a sidewall of the gate pattern ; removing the photoresist pattern ; forming an etch stop layer on the resultant structure where the phtoresist pattern is removed ; forming an interlayer insulating layer on the etch stop layer to fill gap regions between the word line patterns , the interlayer insulating layer containing impurities ; sequentially patterning the interlayer insulating layer , the etch stop layer and the insulating layer to form a plurality of pad contact holes exposing the active region in the cell array region ; forming conductive pads in the pad contact holes ; and thermally oxidizing the resultant structure having the conductive pads , thereby forming a thermal oxide layer on a top surface of the conductive pad and at an interface between the conductive pad and the interlayer insulating layer . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric layer (entire surface) for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space (storage node, drain region) in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US20020025669A1 CLAIM 2 . The method according to claim 1 , wherein prior to forming the interlayer insulating layer , the method comprises : forming a plurality of parallel interconnection patterns on the semiconductor substrate ; and forming a conformal etch stop layer on the entire surface (first sub interlevel dielectric layer) of the resultant structure having the interconnection patterns . US20020025669A1 CLAIM 12 . The method according to claim 11 , further comprising implanting impurities into the active region using the word line patterns and the gate pattern as implantation masks to form a common drain region (second space, floating gate) and source regions at the active region in the cell array region and to concurrently form a low concentration impurity regions at the active region in the peripheral region , prior to formation of the insulating layer , wherein the pad contact holes expose the common drain region and the source regions , wherein the pad contact hole exposing the common drain region is a bit line pad contact hole and the pad contact hole exposing the source regions is a storage node (second space, floating gate) pad contact hole , wherein the conductive pad in the bit line pad contact hole is a bit line pad , and the conductive pad in the storage node pad contact hole is a storage node pad . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US20020025669A1 CLAIM 2 . The method according to claim 1 , wherein prior to forming the interlayer insulating layer , the method comprises : forming a plurality of parallel interconnection patterns on the semiconductor substrate ; and forming (anti reflective coating) a conformal etch stop layer on the entire surface of the resultant structure having the interconnection patterns . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch (etch stop layer, gate pattern) stop insulation layer comprising a first etch stop layer and a second etch (etch stop layer, gate pattern) stop layer wherein said first etch stop layer and said second etch stop layers (silicon nitride layer) have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer (entire surface) and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US20020025669A1 CLAIM 2 . The method according to claim 1 , wherein prior to forming the interlayer insulating layer , the method comprises : forming a plurality of parallel interconnection patterns on the semiconductor substrate ; and forming a conformal etch stop layer (second etch, multiple etch, second etch stop layer) on the entire surface (first sub interlevel dielectric layer) of the resultant structure having the interconnection patterns . US20020025669A1 CLAIM 4 . The method according to claim 2 , wherein the etch stop layer is formed of a silicon nitride layer (second etch stop layers) . US20020025669A1 CLAIM 11 . A method of forming a contact structure in a semiconductor device having a cell array region and a peripheral region , the method comprising : forming an isolation layer at a predetermined portion of a semiconductor substrate to define active regions ; forming a gate insulating layer on the active regions ; sequentially forming a conductive layer and a capping insulating layer on the resultant stricture having the gate insulating layer ; sequentially patterning the capping insulating layer and the conductive layer to form a plurality of parallel word line patterns crossing over the active regions in the cell array region and to form at least one gate pattern (second etch, multiple etch, second etch stop layer) crossing over the active region in the peripheral region ; forming an insulating layer on the resultant structure having the word line patterns and the gate pattern ; forming a photoresist pattern to expose the peripheral region ; anisotropically etching the insulating layer using the photoresist pattern as an etching mask to form a spacer on a sidewall of the gate pattern ; removing the photoresist pattern ; forming an etch stop layer on the resultant structure where the phtoresist pattern is removed ; forming an interlayer insulating layer on the etch stop layer to fill gap regions between the word line patterns , the interlayer insulating layer containing impurities ; sequentially patterning the interlayer insulating layer , the etch stop layer and the insulating layer to form a plurality of pad contact holes exposing the active region in the cell array region ; forming conductive pads in the pad contact holes ; and thermally oxidizing the resultant structure having the conductive pads , thereby forming a thermal oxide layer on a top surface of the conductive pad and at an interface between the conductive pad and the interlayer insulating layer . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer (entire surface) is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (etch stop layer, gate pattern) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US20020025669A1 CLAIM 2 . The method according to claim 1 , wherein prior to forming the interlayer insulating layer , the method comprises : forming a plurality of parallel interconnection patterns on the semiconductor substrate ; and forming a conformal etch stop layer (second etch, multiple etch, second etch stop layer) on the entire surface (first sub interlevel dielectric layer) of the resultant structure having the interconnection patterns . US20020025669A1 CLAIM 11 . A method of forming a contact structure in a semiconductor device having a cell array region and a peripheral region , the method comprising : forming an isolation layer at a predetermined portion of a semiconductor substrate to define active regions ; forming a gate insulating layer on the active regions ; sequentially forming a conductive layer and a capping insulating layer on the resultant stricture having the gate insulating layer ; sequentially patterning the capping insulating layer and the conductive layer to form a plurality of parallel word line patterns crossing over the active regions in the cell array region and to form at least one gate pattern (second etch, multiple etch, second etch stop layer) crossing over the active region in the peripheral region ; forming an insulating layer on the resultant structure having the word line patterns and the gate pattern ; forming a photoresist pattern to expose the peripheral region ; anisotropically etching the insulating layer using the photoresist pattern as an etching mask to form a spacer on a sidewall of the gate pattern ; removing the photoresist pattern ; forming an etch stop layer on the resultant structure where the phtoresist pattern is removed ; forming an interlayer insulating layer on the etch stop layer to fill gap regions between the word line patterns , the interlayer insulating layer containing impurities ; sequentially patterning the interlayer insulating layer , the etch stop layer and the insulating layer to form a plurality of pad contact holes exposing the active region in the cell array region ; forming conductive pads in the pad contact holes ; and thermally oxidizing the resultant structure having the conductive pads , thereby forming a thermal oxide layer on a top surface of the conductive pad and at an interface between the conductive pad and the interlayer insulating layer . |
| US7977797B2 CLAIM 13 . An integrated circuit of claim 11 further comprising a floating gate (storage node, drain region) . |
US20020025669A1 CLAIM 12 . The method according to claim 11 , further comprising implanting impurities into the active region using the word line patterns and the gate pattern as implantation masks to form a common drain region (second space, floating gate) and source regions at the active region in the cell array region and to concurrently form a low concentration impurity regions at the active region in the peripheral region , prior to formation of the insulating layer , wherein the pad contact holes expose the common drain region and the source regions , wherein the pad contact hole exposing the common drain region is a bit line pad contact hole and the pad contact hole exposing the source regions is a storage node (second space, floating gate) pad contact hole , wherein the conductive pad in the bit line pad contact hole is a bit line pad , and the conductive pad in the storage node pad contact hole is a storage node pad . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US20020025669A1 CLAIM 2 . The method according to claim 1 , wherein prior to forming the interlayer insulating layer , the method comprises : forming a plurality of parallel interconnection patterns on the semiconductor substrate ; and forming (anti reflective coating) a conformal etch stop layer on the entire surface of the resultant structure having the interconnection patterns . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US6429123B1 Filed: 2000-10-04 Issued: 2002-08-06 Method of manufacturing buried metal lines having ultra fine features (Original Assignee) Vanguard International Semiconductor Corp (Current Assignee) Vanguard International Semiconductor Corp Horng-Huei Tseng |
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| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer protects removal of a substrate material (silicon oxide) by an etch process (etching stop layer) . |
US6429123B1 CLAIM 2 . The method of claim 1 , wherein said dielectric layer is formed of silicon oxide (substrate material) . US6429123B1 CLAIM 5 . The method of claim 1 further comprising a step to form a silicon nitride layer on said dielectric layer before forming said insulator blocks , wherein said silicon nitride layer is used to serve as an etching stop layer (etch process) to protect said underneath dielectric layer . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers (second sidewall spacer, silicon nitride layer) have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US6429123B1 CLAIM 1 . A method for manufacturing a plurality of buried metal lines on a semiconductor substrate , the method comprises the steps of : forming a dielectric layer on a semiconductor substrate ; forming a plurality of insulator blocks on said dielectric layer , wherein each said insulator block has a width of 3 unit (3×) , and each gap between two adjacent said insulator blocks has a width of 5 unit (5×) ; forming first sidewall spacers on sidewalls of said insulator blocks , wherein each said first sidewall spacer has a width of 1 unit (1×) ; removing said plurality of said insulator blocks ; forming second sidewall spacer (second etch stop layers, floating gate) s on sidewalls of said first sidewall spacers , wherein each said second sidewall spacer has a width of 1 unit (1×) ; forming studs into gaps between two adjacent said second sidewall spacers , wherein each said stud has a width of 1 unit (1×) ; removing said second sidewall spacers ; etching said dielectric layer anisotropically to form a plurality of trenches in said dielectric layer by using said first sidewall spacers and said studs to serve as etching masks ; and filling metal into said trenches to form a plurality of metal lines . US6429123B1 CLAIM 5 . The method of claim 1 further comprising a step to form a silicon nitride layer (second etch stop layers, floating gate) on said dielectric layer before forming said insulator blocks , wherein said silicon nitride layer is used to serve as an etching stop layer to protect said underneath dielectric layer . |
| US7977797B2 CLAIM 13 . An integrated circuit of claim 11 further comprising a floating gate (second sidewall spacer, silicon nitride layer) . |
US6429123B1 CLAIM 1 . A method for manufacturing a plurality of buried metal lines on a semiconductor substrate , the method comprises the steps of : forming a dielectric layer on a semiconductor substrate ; forming a plurality of insulator blocks on said dielectric layer , wherein each said insulator block has a width of 3 unit (3×) , and each gap between two adjacent said insulator blocks has a width of 5 unit (5×) ; forming first sidewall spacers on sidewalls of said insulator blocks , wherein each said first sidewall spacer has a width of 1 unit (1×) ; removing said plurality of said insulator blocks ; forming second sidewall spacer (second etch stop layers, floating gate) s on sidewalls of said first sidewall spacers , wherein each said second sidewall spacer has a width of 1 unit (1×) ; forming studs into gaps between two adjacent said second sidewall spacers , wherein each said stud has a width of 1 unit (1×) ; removing said second sidewall spacers ; etching said dielectric layer anisotropically to form a plurality of trenches in said dielectric layer by using said first sidewall spacers and said studs to serve as etching masks ; and filling metal into said trenches to form a plurality of metal lines . US6429123B1 CLAIM 5 . The method of claim 1 further comprising a step to form a silicon nitride layer (second etch stop layers, floating gate) on said dielectric layer before forming said insulator blocks , wherein said silicon nitride layer is used to serve as an etching stop layer to protect said underneath dielectric layer . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | JP2002064140A Filed: 2000-08-22 Issued: 2002-02-28 半導体装置およびその製造方法 (Original Assignee) Nec Corp; 日本電気株式会社 Masayuki Hiroi, 政幸 廣井 |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation (の絶縁) between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
JP2002064140A CLAIM 15 【請求項１５】前記溝及び孔を、所定のバリア膜を挟ん で形成される複数の絶縁 (electrical insulation) 膜層に形成することを特徴とす る請求項１４記載の半導体装置の製造方法。 |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range (あること) of about 0 . 16 μm to 0 . 18 μm wide . |
JP2002064140A CLAIM 16 【請求項１６】前記第３のバリア膜が導体であること (second range) を 特徴とする請求項３乃至１５のいずれか一に記載の半導 体装置の製造方法。 |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region is a first range of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range (あること) of about 0 . 16 μm to 0 . 18 μm wide . |
JP2002064140A CLAIM 16 【請求項１６】前記第３のバリア膜が導体であること (second range) を 特徴とする請求項３乃至１５のいずれか一に記載の半導 体装置の製造方法。 |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US6373123B1 Filed: 2000-07-10 Issued: 2002-04-16 Semiconductor structure having more usable substrate area and method for forming same (Original Assignee) Micron Technology Inc (Current Assignee) Micron Technology Inc Darwin A. Clampitt |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region (monocrystalline silicon) such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch (memory array) stop layer directly on said substrate in said contact region ; a first sub (first sub) interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub (second sub) interlevel dielectric layer over said second etch stop layer . |
US6373123B1 CLAIM 2 . The semiconductor structure of claim 1 wherein the substrate comprises monocrystalline silicon (spacer region) . US6373123B1 CLAIM 5 . A semiconductor structure , comprising : a first portion of a substrate having a surface occupying a first area ; first active regions disposed in the first sub (first sub) strate portion and occupying a second area ; isolation regions disposed on the first substrate portion outside of the first active regions and extending out from the surface of the first substrate portion , the isolation regions occupying a third area ; a second portion of the substrate disposed on the isolation regions ; and second active regions disposed in the second sub (second sub) strate portion and occupying a fourth area , the sum of the second and fourth areas being significantly greater than the difference between the first and third areas . US6373123B1 CLAIM 9 . A memory array (first etch, first etch stop layer) , comprising : a first portion of a substrate having a surface ; dielectric runners extending out from the surface and being substantially parallel to one another , the dielectric runners defining trenches therebetween , the trenches having bottoms formed by the surface ; recessed memory cells disposed in the trench bottoms ; a second portion of the substrate disposed on the dielectric runners ; elevated memory cells disposed in the second substrate portion ; and word lines each extending substantially orthogonal to the dielectric runners and disposed over recessed and elevated memory cells to define a respective row of memory cells . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch (memory array) stop layer protects removal of a substrate material by an etch process . |
US6373123B1 CLAIM 9 . A memory array (first etch, first etch stop layer) , comprising : a first portion of a substrate having a surface ; dielectric runners extending out from the surface and being substantially parallel to one another , the dielectric runners defining trenches therebetween , the trenches having bottoms formed by the surface ; recessed memory cells disposed in the trench bottoms ; a second portion of the substrate disposed on the dielectric runners ; elevated memory cells disposed in the second substrate portion ; and word lines each extending substantially orthogonal to the dielectric runners and disposed over recessed and elevated memory cells to define a respective row of memory cells . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub (first sub) interlevel dielectric layer insulates said contact region . |
US6373123B1 CLAIM 5 . A semiconductor structure , comprising : a first portion of a substrate having a surface occupying a first area ; first active regions disposed in the first sub (first sub) strate portion and occupying a second area ; isolation regions disposed on the first substrate portion outside of the first active regions and extending out from the surface of the first substrate portion , the isolation regions occupying a third area ; a second portion of the substrate disposed on the isolation regions ; and second active regions disposed in the second substrate portion and occupying a fourth area , the sum of the second and fourth areas being significantly greater than the difference between the first and third areas . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch stop layer protects lower layers during an etching process (second area) . |
US6373123B1 CLAIM 5 . A semiconductor structure , comprising : a first portion of a substrate having a surface occupying a first area ; first active regions disposed in the first substrate portion and occupying a second area (etching process) ; isolation regions disposed on the first substrate portion outside of the first active regions and extending out from the surface of the first substrate portion , the isolation regions occupying a third area ; a second portion of the substrate disposed on the isolation regions ; and second active regions disposed in the second substrate portion and occupying a fourth area , the sum of the second and fourth areas being significantly greater than the difference between the first and third areas . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub (second sub) interlevel dielectric layer insulates said contact region . |
US6373123B1 CLAIM 5 . A semiconductor structure , comprising : a first portion of a substrate having a surface occupying a first area ; first active regions disposed in the first substrate portion and occupying a second area ; isolation regions disposed on the first substrate portion outside of the first active regions and extending out from the surface of the first substrate portion , the isolation regions occupying a third area ; a second portion of the substrate disposed on the isolation regions ; and second active regions disposed in the second sub (second sub) strate portion and occupying a fourth area , the sum of the second and fourth areas being significantly greater than the difference between the first and third areas . |
| US7977797B2 CLAIM 6 . An integrated circuit of claim 1 wherein said spacer region (monocrystalline silicon) insulates said contact region . |
US6373123B1 CLAIM 2 . The semiconductor structure of claim 1 wherein the substrate comprises monocrystalline silicon (spacer region) . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch (memory array) stop layer is in a range of about 300 to 800 Šthick , said first sub (first sub) interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub (second sub) interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6373123B1 CLAIM 5 . A semiconductor structure , comprising : a first portion of a substrate having a surface occupying a first area ; first active regions disposed in the first sub (first sub) strate portion and occupying a second area ; isolation regions disposed on the first substrate portion outside of the first active regions and extending out from the surface of the first substrate portion , the isolation regions occupying a third area ; a second portion of the substrate disposed on the isolation regions ; and second active regions disposed in the second sub (second sub) strate portion and occupying a fourth area , the sum of the second and fourth areas being significantly greater than the difference between the first and third areas . US6373123B1 CLAIM 9 . A memory array (first etch, first etch stop layer) , comprising : a first portion of a substrate having a surface ; dielectric runners extending out from the surface and being substantially parallel to one another , the dielectric runners defining trenches therebetween , the trenches having bottoms formed by the surface ; recessed memory cells disposed in the trench bottoms ; a second portion of the substrate disposed on the dielectric runners ; elevated memory cells disposed in the second substrate portion ; and word lines each extending substantially orthogonal to the dielectric runners and disposed over recessed and elevated memory cells to define a respective row of memory cells . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub (first sub) interlevel dielectric layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub (second sub) interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US6373123B1 CLAIM 5 . A semiconductor structure , comprising : a first portion of a substrate having a surface occupying a first area ; first active regions disposed in the first sub (first sub) strate portion and occupying a second area ; isolation regions disposed on the first substrate portion outside of the first active regions and extending out from the surface of the first substrate portion , the isolation regions occupying a third area ; a second portion of the substrate disposed on the isolation regions ; and second active regions disposed in the second sub (second sub) strate portion and occupying a fourth area , the sum of the second and fourth areas being significantly greater than the difference between the first and third areas . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch (memory array) stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers (adjacent pair) have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub (first sub) interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub (second sub) interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US6373123B1 CLAIM 5 . A semiconductor structure , comprising : a first portion of a substrate having a surface occupying a first area ; first active regions disposed in the first sub (first sub) strate portion and occupying a second area ; isolation regions disposed on the first substrate portion outside of the first active regions and extending out from the surface of the first substrate portion , the isolation regions occupying a third area ; a second portion of the substrate disposed on the isolation regions ; and second active regions disposed in the second sub (second sub) strate portion and occupying a fourth area , the sum of the second and fourth areas being significantly greater than the difference between the first and third areas . US6373123B1 CLAIM 9 . A memory array (first etch, first etch stop layer) , comprising : a first portion of a substrate having a surface ; dielectric runners extending out from the surface and being substantially parallel to one another , the dielectric runners defining trenches therebetween , the trenches having bottoms formed by the surface ; recessed memory cells disposed in the trench bottoms ; a second portion of the substrate disposed on the dielectric runners ; elevated memory cells disposed in the second substrate portion ; and word lines each extending substantially orthogonal to the dielectric runners and disposed over recessed and elevated memory cells to define a respective row of memory cells . US6373123B1 CLAIM 11 . The memory array of claim 9 , further comprising : recessed isolation regions disposed in the trench bottoms to respectively isolate adjacent pair (second etch stop layers) s of the recessed memory cells from one another ; and elevated isolation regions disposed in the second portion of the substrate to respectively isolate adjacent pairs of the elevated memory cells from one another . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch (memory array) stop layer is in a range of about 300 to 800 Šthick , said first sub (first sub) interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub (second sub) interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6373123B1 CLAIM 5 . A semiconductor structure , comprising : a first portion of a substrate having a surface occupying a first area ; first active regions disposed in the first sub (first sub) strate portion and occupying a second area ; isolation regions disposed on the first substrate portion outside of the first active regions and extending out from the surface of the first substrate portion , the isolation regions occupying a third area ; a second portion of the substrate disposed on the isolation regions ; and second active regions disposed in the second sub (second sub) strate portion and occupying a fourth area , the sum of the second and fourth areas being significantly greater than the difference between the first and third areas . US6373123B1 CLAIM 9 . A memory array (first etch, first etch stop layer) , comprising : a first portion of a substrate having a surface ; dielectric runners extending out from the surface and being substantially parallel to one another , the dielectric runners defining trenches therebetween , the trenches having bottoms formed by the surface ; recessed memory cells disposed in the trench bottoms ; a second portion of the substrate disposed on the dielectric runners ; elevated memory cells disposed in the second substrate portion ; and word lines each extending substantially orthogonal to the dielectric runners and disposed over recessed and elevated memory cells to define a respective row of memory cells . |
| US7977797B2 CLAIM 13 . An integrated circuit of claim 11 further comprising a floating gate (semiconductor structure) . |
US6373123B1 CLAIM 1 . A semiconductor structure (floating gate) , comprising : a first portion of a substrate having a surface ; a first active region disposed in the first portion of the substrate ; an isolation region disposed on the first portion of the substrate outside of the first active region and extending out from the surface ; a second portion of the substrate disposed on the isolation region ; and a second active region disposed in the second portion of the substrate . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | JP2001057386A Filed: 2000-06-29 Issued: 2001-02-27 エッチバックを用いた多結晶シリコンコンタクトプラグ形成方法およびこれを用いた半導体素子の製造方法 (Original Assignee) Samsung Electronics Co Ltd; 三星電子株式会社 Takashi Jo, Woo-Sik Kim, Young-Woo Park, Jong-Heui Song, 鍾 希 宋, 俊 徐, 泳 雨 朴, 佑 ▲しく▼ 金 |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (製造方法) of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
JP2001057386A CLAIM 13 【請求項１３】 （ａ）トランジスタ、下部電極コンタ クト用パッド及びビットラインが形成された半導体基板 上に層間絶縁膜を形成する段階と、（ｂ）前記層間絶縁 膜をエッチングして前記下部電極コンタクト用パッドを 露出させる下部電極コンタクトホールを形成する段階 と、（ｃ）前記下部電極コンタクトホールを埋め込むよ うに前記下部電極コンタクトホール及び前記層間絶縁膜 の表面に多結晶シリコン層を形成する段階と、（ｄ）前 記多結晶シリコン層をエッチバックすることにより前記 層間絶縁膜を露出させ、多結晶シリコンからなる下部電 極コンタクトプラグを形成する段階と、（ｅ）前記露出 した層間絶縁膜を全面エッチングしてその一部を除去す ることにより前記下部電極コンタクトプラグを突出させ る段階と、（ｆ）前記下部電極コンタクトプラグ上に下 部電極、誘電膜及び上部電極を形成する段階とを含むこ とを特徴とする半導体素子の製造方法 (metal layer coupling area) 。 |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch stop layer protects lower layers during an etching process (１００) . |
JP2001057386A CLAIM 5 【請求項５】 前記（ｅ１）段階において、前記ＣＨＦ 3 及びＣＦ 4 の流量はそれぞれ５〜１００ (etching process) ｓｃｃｍ、５〜 ５０ｓｃｃｍであることを特徴とする請求項３または４ に記載の半導体素子のコンタクトプラグ形成方法。 |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area of said contact region permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area (製造方法) of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
JP2001057386A CLAIM 13 【請求項１３】 （ａ）トランジスタ、下部電極コンタ クト用パッド及びビットラインが形成された半導体基板 上に層間絶縁膜を形成する段階と、（ｂ）前記層間絶縁 膜をエッチングして前記下部電極コンタクト用パッドを 露出させる下部電極コンタクトホールを形成する段階 と、（ｃ）前記下部電極コンタクトホールを埋め込むよ うに前記下部電極コンタクトホール及び前記層間絶縁膜 の表面に多結晶シリコン層を形成する段階と、（ｄ）前 記多結晶シリコン層をエッチバックすることにより前記 層間絶縁膜を露出させ、多結晶シリコンからなる下部電 極コンタクトプラグを形成する段階と、（ｅ）前記露出 した層間絶縁膜を全面エッチングしてその一部を除去す ることにより前記下部電極コンタクトプラグを突出させ る段階と、（ｆ）前記下部電極コンタクトプラグ上に下 部電極、誘電膜及び上部電極を形成する段階とを含むこ とを特徴とする半導体素子の製造方法 (metal layer coupling area) 。 |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range (あること) of about 0 . 16 μm to 0 . 18 μm wide . |
JP2001057386A CLAIM 2 【請求項２】 前記（ｄ）段階のＳＦ 6 、ＣＨＦ 3 及びＣ Ｆ 4 の流量はそれぞれ５〜２０ｓｃｃｍ、１０〜４０ｓ ｃｃｍ及び１０〜４０ｓｃｃｍであること (second range) を特徴とする 請求項１に記載の半導体素子のコンタクトプラグ形成方 法。 |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (製造方法) of said contact region . |
JP2001057386A CLAIM 13 【請求項１３】 （ａ）トランジスタ、下部電極コンタ クト用パッド及びビットラインが形成された半導体基板 上に層間絶縁膜を形成する段階と、（ｂ）前記層間絶縁 膜をエッチングして前記下部電極コンタクト用パッドを 露出させる下部電極コンタクトホールを形成する段階 と、（ｃ）前記下部電極コンタクトホールを埋め込むよ うに前記下部電極コンタクトホール及び前記層間絶縁膜 の表面に多結晶シリコン層を形成する段階と、（ｄ）前 記多結晶シリコン層をエッチバックすることにより前記 層間絶縁膜を露出させ、多結晶シリコンからなる下部電 極コンタクトプラグを形成する段階と、（ｅ）前記露出 した層間絶縁膜を全面エッチングしてその一部を除去す ることにより前記下部電極コンタクトプラグを突出させ る段階と、（ｆ）前記下部電極コンタクトプラグ上に下 部電極、誘電膜及び上部電極を形成する段階とを含むこ とを特徴とする半導体素子の製造方法 (metal layer coupling area) 。 |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region is a first range of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range (あること) of about 0 . 16 μm to 0 . 18 μm wide . |
JP2001057386A CLAIM 2 【請求項２】 前記（ｄ）段階のＳＦ 6 、ＣＨＦ 3 及びＣ Ｆ 4 の流量はそれぞれ５〜２０ｓｃｃｍ、１０〜４０ｓ ｃｃｍ及び１０〜４０ｓｃｃｍであること (second range) を特徴とする 請求項１に記載の半導体素子のコンタクトプラグ形成方 法。 |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | JP2001326286A Filed: 2000-05-16 Issued: 2001-11-22 半導体装置及びその製造方法 (Original Assignee) Halo Lsi Design & Device Technol Inc; Matsushita Electric Ind Co Ltd; ヘイロー エルエスアイ デザイン アンド デバイステクノロジー インコーポレイテッド; 松下電器産業株式会社 Seiki Ogura, Akio Shimano, 正気 小椋, 彰男 嶋野 |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (製造方法) of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation (なる第２) between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer (少なくとも) over said second etch stop layer . |
JP2001326286A CLAIM 5 【請求項５】 半導体基板上に、互いに隣接する側辺部 同士の間に間隙を設けるように第１の電極パターンと孤 立パターンとを形成する工程と、 前記第１の電極パターン及び孤立パターンの上に前記間 隙を残すように絶縁膜を形成する工程と、 前記半導体基板上に、前記第１の電極パターン及び孤立 パターンを含む全面にわたって前記間隙が充填されるよ うに第２の電極パターン形成膜を形成する工程と、 前記第２の電極パターン形成膜に対してエッチバックを 行なって、前記第２の電極パターン形成膜から、前記第 １の電極パターンの側面に形成された側壁部と前記間隙 に充填された充填部とからなる第２ (electrical insulation) の電極パターンを形 成する工程と、 前記充填部の上に該充填部と電気的に接続されるコンタ クトを形成する工程とを備えていることを特徴とする半 導体装置の製造方法 (metal layer coupling area) 。 JP2001326286A CLAIM 8 【請求項８】 半導体基板上に、第１の電極パターン と、該第１の電極パターンと隣接し且つ互いに対向する 側辺部同士の間に間隙を設けた少なくとも (second sub interlevel dielectric layer) ２つの孤立パ ターンを形成する工程と、 前記第１の電極パターン及び各孤立パターンの上に前記 間隙を残すように絶縁膜を形成する工程と、 前記半導体基板上に、前記第１の電極パターン及び各孤 立パターンを含む全面にわたって少なくとも１つの間隙 が充填されるように第２の電極パターン形成膜を形成す る工程と、 前記第２の電極パターン形成膜に対してエッチバックを 行なって、前記第２の電極パターン形成膜から、前記第 １の電極パターンの側面に形成された側壁部と前記各孤 立パターン同士の間の少なくとも１つの間隙に充填され た充填部とからなる第２の電極パターンを形成する工程 と、 前記充填部の上に該充填部と電気的に接続されるコンタ クトを形成する工程とを備えていることを特徴とする半 導体装置の製造方法。 |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric layer (少なくとも) insulates said contact region . |
JP2001326286A CLAIM 8 【請求項８】 半導体基板上に、第１の電極パターン と、該第１の電極パターンと隣接し且つ互いに対向する 側辺部同士の間に間隙を設けた少なくとも (second sub interlevel dielectric layer) ２つの孤立パ ターンを形成する工程と、 前記第１の電極パターン及び各孤立パターンの上に前記 間隙を残すように絶縁膜を形成する工程と、 前記半導体基板上に、前記第１の電極パターン及び各孤 立パターンを含む全面にわたって少なくとも１つの間隙 が充填されるように第２の電極パターン形成膜を形成す る工程と、 前記第２の電極パターン形成膜に対してエッチバックを 行なって、前記第２の電極パターン形成膜から、前記第 １の電極パターンの側面に形成された側壁部と前記各孤 立パターン同士の間の少なくとも１つの間隙に充填され た充填部とからなる第２の電極パターンを形成する工程 と、 前記充填部の上に該充填部と電気的に接続されるコンタ クトを形成する工程とを備えていることを特徴とする半 導体装置の製造方法。 |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area of said contact region permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area (製造方法) of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
JP2001326286A CLAIM 5 【請求項５】 半導体基板上に、互いに隣接する側辺部 同士の間に間隙を設けるように第１の電極パターンと孤 立パターンとを形成する工程と、 前記第１の電極パターン及び孤立パターンの上に前記間 隙を残すように絶縁膜を形成する工程と、 前記半導体基板上に、前記第１の電極パターン及び孤立 パターンを含む全面にわたって前記間隙が充填されるよ うに第２の電極パターン形成膜を形成する工程と、 前記第２の電極パターン形成膜に対してエッチバックを 行なって、前記第２の電極パターン形成膜から、前記第 １の電極パターンの側面に形成された側壁部と前記間隙 に充填された充填部とからなる第２の電極パターンを形 成する工程と、 前記充填部の上に該充填部と電気的に接続されるコンタ クトを形成する工程とを備えていることを特徴とする半 導体装置の製造方法 (metal layer coupling area) 。 |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Å thick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Å thick , said second etch stop layer is in a range of about 300 to 800 Å thick and said second sub interlevel dielectric layer (少なくとも) is in a range of about 10K ű1K Å thick . |
JP2001326286A CLAIM 8 【請求項８】 半導体基板上に、第１の電極パターン と、該第１の電極パターンと隣接し且つ互いに対向する 側辺部同士の間に間隙を設けた少なくとも (second sub interlevel dielectric layer) ２つの孤立パ ターンを形成する工程と、 前記第１の電極パターン及び各孤立パターンの上に前記 間隙を残すように絶縁膜を形成する工程と、 前記半導体基板上に、前記第１の電極パターン及び各孤 立パターンを含む全面にわたって少なくとも１つの間隙 が充填されるように第２の電極パターン形成膜を形成す る工程と、 前記第２の電極パターン形成膜に対してエッチバックを 行なって、前記第２の電極パターン形成膜から、前記第 １の電極パターンの側面に形成された側壁部と前記各孤 立パターン同士の間の少なくとも１つの間隙に充填され た充填部とからなる第２の電極パターンを形成する工程 と、 前記充填部の上に該充填部と電気的に接続されるコンタ クトを形成する工程とを備えていることを特徴とする半 導体装置の製造方法。 |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer (少なくとも) for said contact region is in a second range (あること) of about 0 . 16 μm to 0 . 18 μm wide . |
JP2001326286A CLAIM 6 【請求項６】 前記第１の電極パターンはコントロール ゲートであり、前記第２の電極パターンは浮遊ゲートで あること (second range) を特徴とする請求項５に記載の半導体装置の製 造方法。 JP2001326286A CLAIM 8 【請求項８】 半導体基板上に、第１の電極パターン と、該第１の電極パターンと隣接し且つ互いに対向する 側辺部同士の間に間隙を設けた少なくとも (second sub interlevel dielectric layer) ２つの孤立パ ターンを形成する工程と、 前記第１の電極パターン及び各孤立パターンの上に前記 間隙を残すように絶縁膜を形成する工程と、 前記半導体基板上に、前記第１の電極パターン及び各孤 立パターンを含む全面にわたって少なくとも１つの間隙 が充填されるように第２の電極パターン形成膜を形成す る工程と、 前記第２の電極パターン形成膜に対してエッチバックを 行なって、前記第２の電極パターン形成膜から、前記第 １の電極パターンの側面に形成された側壁部と前記各孤 立パターン同士の間の少なくとも１つの間隙に充填され た充填部とからなる第２の電極パターンを形成する工程 と、 前記充填部の上に該充填部と電気的に接続されるコンタ クトを形成する工程とを備えていることを特徴とする半 導体装置の製造方法。 |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer (少なくとも) and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (製造方法) of said contact region . |
JP2001326286A CLAIM 5 【請求項５】 半導体基板上に、互いに隣接する側辺部 同士の間に間隙を設けるように第１の電極パターンと孤 立パターンとを形成する工程と、 前記第１の電極パターン及び孤立パターンの上に前記間 隙を残すように絶縁膜を形成する工程と、 前記半導体基板上に、前記第１の電極パターン及び孤立 パターンを含む全面にわたって前記間隙が充填されるよ うに第２の電極パターン形成膜を形成する工程と、 前記第２の電極パターン形成膜に対してエッチバックを 行なって、前記第２の電極パターン形成膜から、前記第 １の電極パターンの側面に形成された側壁部と前記間隙 に充填された充填部とからなる第２の電極パターンを形 成する工程と、 前記充填部の上に該充填部と電気的に接続されるコンタ クトを形成する工程とを備えていることを特徴とする半 導体装置の製造方法 (metal layer coupling area) 。 JP2001326286A CLAIM 8 【請求項８】 半導体基板上に、第１の電極パターン と、該第１の電極パターンと隣接し且つ互いに対向する 側辺部同士の間に間隙を設けた少なくとも (second sub interlevel dielectric layer) ２つの孤立パ ターンを形成する工程と、 前記第１の電極パターン及び各孤立パターンの上に前記 間隙を残すように絶縁膜を形成する工程と、 前記半導体基板上に、前記第１の電極パターン及び各孤 立パターンを含む全面にわたって少なくとも１つの間隙 が充填されるように第２の電極パターン形成膜を形成す る工程と、 前記第２の電極パターン形成膜に対してエッチバックを 行なって、前記第２の電極パターン形成膜から、前記第 １の電極パターンの側面に形成された側壁部と前記各孤 立パターン同士の間の少なくとも１つの間隙に充填され た充填部とからなる第２の電極パターンを形成する工程 と、 前記充填部の上に該充填部と電気的に接続されるコンタ クトを形成する工程とを備えていることを特徴とする半 導体装置の製造方法。 |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Å thick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Å thick , said second etch stop layer is in a range of about 300 to 800 Å thick and said second sub interlevel dielectric layer (少なくとも) is in a range of about 10K ű1K Å thick . |
JP2001326286A CLAIM 8 【請求項８】 半導体基板上に、第１の電極パターン と、該第１の電極パターンと隣接し且つ互いに対向する 側辺部同士の間に間隙を設けた少なくとも (second sub interlevel dielectric layer) ２つの孤立パ ターンを形成する工程と、 前記第１の電極パターン及び各孤立パターンの上に前記 間隙を残すように絶縁膜を形成する工程と、 前記半導体基板上に、前記第１の電極パターン及び各孤 立パターンを含む全面にわたって少なくとも１つの間隙 が充填されるように第２の電極パターン形成膜を形成す る工程と、 前記第２の電極パターン形成膜に対してエッチバックを 行なって、前記第２の電極パターン形成膜から、前記第 １の電極パターンの側面に形成された側壁部と前記各孤 立パターン同士の間の少なくとも１つの間隙に充填され た充填部とからなる第２の電極パターンを形成する工程 と、 前記充填部の上に該充填部と電気的に接続されるコンタ クトを形成する工程とを備えていることを特徴とする半 導体装置の製造方法。 |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region is a first range of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range (あること) of about 0 . 16 μm to 0 . 18 μm wide . |
JP2001326286A CLAIM 6 【請求項６】 前記第１の電極パターンはコントロール ゲートであり、前記第２の電極パターンは浮遊ゲートで あること (second range) を特徴とする請求項５に記載の半導体装置の製 造方法。 |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | JP2001298154A Filed: 2000-04-12 Issued: 2001-10-26 半導体装置およびその製造方法 (Original Assignee) Sony Corp; ソニー株式会社 Tetsuya Oishi, 哲也 大石 |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (製造方法) of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation (の絶縁) between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (バリアメタル) layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
JP2001298154A CLAIM 1 【請求項１】半導体基板上に形成された層間絶縁膜と、 前記層間絶縁膜上に形成された第１の導電体層からなる 下部電極と、 前記下部電極上に形成されたキャパシタ絶縁膜と、 少なくとも (second sub interlevel dielectric layer) 前記下部電極の側面を被覆して前記キャパシ タ絶縁膜と接する絶縁体サイドウォールと、 前記キャパシタ絶縁膜上および前記絶縁体サイドウォー ルの表面に形成された第２の導電体層からなる上部電極 とを有する半導体装置。 JP2001298154A CLAIM 5 【請求項５】前記上部電極は前記キャパシタ絶縁膜上お よび前記絶縁体サイドウォールの表面にバリアメタル (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer) 層 を介して形成されている請求項１記載の半導体装置。 JP2001298154A CLAIM 11 【請求項１１】半導体基板上に層間絶縁膜を形成する工 程と、 前記層間絶縁膜上に第１の導電体層からなる下部電極を 形成し、前記下部電極上にキャパシタ絶縁膜を形成する 工程と、 少なくとも前記下部電極の側面を被覆して前記キャパシ タ絶縁膜と接する絶縁体サイドウォールを形成する工程 と、 前記キャパシタ絶縁膜上および前記絶縁体サイドウォー ルの表面に第２の導電体層からなる上部電極を形成する 工程とを有する半導体装置の製造方法 (metal layer coupling area) 。 JP2001298154A CLAIM 12 【請求項１２】前記下部電極および前記キャパシタ絶縁 膜を形成する工程は、前記層間絶縁膜上に第１の導電体 層を形成する工程と、 前記第１の導電体層上に第１の絶縁 (electrical insulation) 膜を形成する工程 と、 前記第１の絶縁膜上にフォトリソグラフィにより所定の パターンを有するレジストを形成する工程と、 前記レジストをマスクとして前記第１の絶縁膜および前 記第１の導電体層にエッチングを行い、前記キャパシタ 絶縁膜および前記下部電極をそれぞれ形成する工程とを 有する請求項１１記載の半導体装置の製造方法。 |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer protects removal of a substrate material (ウォール) by an etch process . |
JP2001298154A CLAIM 1 【請求項１】半導体基板上に形成された層間絶縁膜と、 前記層間絶縁膜上に形成された第１の導電体層からなる 下部電極と、 前記下部電極上に形成されたキャパシタ絶縁膜と、 少なくとも前記下部電極の側面を被覆して前記キャパシ タ絶縁膜と接する絶縁体サイドウォール (substrate material) と、 前記キャパシタ絶縁膜上および前記絶縁体サイドウォー ルの表面に形成された第２の導電体層からなる上部電極 とを有する半導体装置。 |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (バリアメタル) layer insulates said contact region . |
JP2001298154A CLAIM 5 【請求項５】前記上部電極は前記キャパシタ絶縁膜上お よび前記絶縁体サイドウォールの表面にバリアメタル (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer) 層 を介して形成されている請求項１記載の半導体装置。 |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (バリアメタル) layer insulates said contact region . |
JP2001298154A CLAIM 1 【請求項１】半導体基板上に形成された層間絶縁膜と、 前記層間絶縁膜上に形成された第１の導電体層からなる 下部電極と、 前記下部電極上に形成されたキャパシタ絶縁膜と、 少なくとも (second sub interlevel dielectric layer) 前記下部電極の側面を被覆して前記キャパシ タ絶縁膜と接する絶縁体サイドウォールと、 前記キャパシタ絶縁膜上および前記絶縁体サイドウォー ルの表面に形成された第２の導電体層からなる上部電極 とを有する半導体装置。 JP2001298154A CLAIM 5 【請求項５】前記上部電極は前記キャパシタ絶縁膜上お よび前記絶縁体サイドウォールの表面にバリアメタル (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer) 層 を介して形成されている請求項１記載の半導体装置。 |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area of said contact region permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area (製造方法) of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
JP2001298154A CLAIM 11 【請求項１１】半導体基板上に層間絶縁膜を形成する工 程と、 前記層間絶縁膜上に第１の導電体層からなる下部電極を 形成し、前記下部電極上にキャパシタ絶縁膜を形成する 工程と、 少なくとも前記下部電極の側面を被覆して前記キャパシ タ絶縁膜と接する絶縁体サイドウォールを形成する工程 と、 前記キャパシタ絶縁膜上および前記絶縁体サイドウォー ルの表面に第２の導電体層からなる上部電極を形成する 工程とを有する半導体装置の製造方法 (metal layer coupling area) 。 |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Å thick , said first sub interlevel dielectric (バリアメタル) layer is in a range of about 1 , 000 to 2 , 000 Å thick , said second etch stop layer is in a range of about 300 to 800 Å thick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Å thick . |
JP2001298154A CLAIM 1 【請求項１】半導体基板上に形成された層間絶縁膜と、 前記層間絶縁膜上に形成された第１の導電体層からなる 下部電極と、 前記下部電極上に形成されたキャパシタ絶縁膜と、 少なくとも (second sub interlevel dielectric layer) 前記下部電極の側面を被覆して前記キャパシ タ絶縁膜と接する絶縁体サイドウォールと、 前記キャパシタ絶縁膜上および前記絶縁体サイドウォー ルの表面に形成された第２の導電体層からなる上部電極 とを有する半導体装置。 JP2001298154A CLAIM 5 【請求項５】前記上部電極は前記キャパシタ絶縁膜上お よび前記絶縁体サイドウォールの表面にバリアメタル (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer) 層 を介して形成されている請求項１記載の半導体装置。 |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space (前記保) in a portion of said first sub interlevel dielectric (バリアメタル) layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
JP2001298154A CLAIM 1 【請求項１】半導体基板上に形成された層間絶縁膜と、 前記層間絶縁膜上に形成された第１の導電体層からなる 下部電極と、 前記下部電極上に形成されたキャパシタ絶縁膜と、 少なくとも (second sub interlevel dielectric layer) 前記下部電極の側面を被覆して前記キャパシ タ絶縁膜と接する絶縁体サイドウォールと、 前記キャパシタ絶縁膜上および前記絶縁体サイドウォー ルの表面に形成された第２の導電体層からなる上部電極 とを有する半導体装置。 JP2001298154A CLAIM 3 【請求項３】前記保 (first space) 護層は前記上部電極との導電性を有 する材料からなる請求項２記載の半導体装置。 JP2001298154A CLAIM 5 【請求項５】前記上部電極は前記キャパシタ絶縁膜上お よび前記絶縁体サイドウォールの表面にバリアメタル (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer) 層 を介して形成されている請求項１記載の半導体装置。 |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (バリアメタル) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (製造方法) of said contact region . |
JP2001298154A CLAIM 1 【請求項１】半導体基板上に形成された層間絶縁膜と、 前記層間絶縁膜上に形成された第１の導電体層からなる 下部電極と、 前記下部電極上に形成されたキャパシタ絶縁膜と、 少なくとも (second sub interlevel dielectric layer) 前記下部電極の側面を被覆して前記キャパシ タ絶縁膜と接する絶縁体サイドウォールと、 前記キャパシタ絶縁膜上および前記絶縁体サイドウォー ルの表面に形成された第２の導電体層からなる上部電極 とを有する半導体装置。 JP2001298154A CLAIM 5 【請求項５】前記上部電極は前記キャパシタ絶縁膜上お よび前記絶縁体サイドウォールの表面にバリアメタル (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer) 層 を介して形成されている請求項１記載の半導体装置。 JP2001298154A CLAIM 11 【請求項１１】半導体基板上に層間絶縁膜を形成する工 程と、 前記層間絶縁膜上に第１の導電体層からなる下部電極を 形成し、前記下部電極上にキャパシタ絶縁膜を形成する 工程と、 少なくとも前記下部電極の側面を被覆して前記キャパシ タ絶縁膜と接する絶縁体サイドウォールを形成する工程 と、 前記キャパシタ絶縁膜上および前記絶縁体サイドウォー ルの表面に第２の導電体層からなる上部電極を形成する 工程とを有する半導体装置の製造方法 (metal layer coupling area) 。 |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Å thick , said first sub interlevel dielectric (バリアメタル) layer is in a range of about 1 , 000 to 2 , 000 Å thick , said second etch stop layer is in a range of about 300 to 800 Å thick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Å thick . |
JP2001298154A CLAIM 1 【請求項１】半導体基板上に形成された層間絶縁膜と、 前記層間絶縁膜上に形成された第１の導電体層からなる 下部電極と、 前記下部電極上に形成されたキャパシタ絶縁膜と、 少なくとも (second sub interlevel dielectric layer) 前記下部電極の側面を被覆して前記キャパシ タ絶縁膜と接する絶縁体サイドウォールと、 前記キャパシタ絶縁膜上および前記絶縁体サイドウォー ルの表面に形成された第２の導電体層からなる上部電極 とを有する半導体装置。 JP2001298154A CLAIM 5 【請求項５】前記上部電極は前記キャパシタ絶縁膜上お よび前記絶縁体サイドウォールの表面にバリアメタル (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer) 層 を介して形成されている請求項１記載の半導体装置。 |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | JP2001291846A Filed: 2000-04-10 Issued: 2001-10-19 半導体記憶装置及びその製造方法 (Original Assignee) Nec Corp; 日本電気株式会社 Yuichi Takada, 祐一 高田 |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (製造方法) of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation (絶縁層) between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
JP2001291846A CLAIM 4 【請求項４】 ワード線間にプラグ領域を設けて半導体 基板と電気的に接続し、該ワード線及び該プラグ領域上 に、第１の絶縁膜、該第１の絶縁膜に対して小さいエッ チングレートを有する第２の絶縁膜、ビット線となる導 電層、該第１の絶縁膜に対して小さいエッチングレート を有する第３の絶縁膜を形成する第１の工程と、 前記第２の絶縁膜、前記導電層及び第３の絶縁膜をパタ ーン化して前記プラグ領域間上にビット線を形成する第 ２の工程と、 パターン化された前記導電層の側壁部に前記第１の絶縁 膜に対して小さいエッチングレートを有する第４の絶縁 膜を形成する第３の工程と、 露出している前記第１の絶縁層 (electrical insulation) を異方性エッチング除去 する第４の工程と、 露出した前記プラグ領域の表面を等方性エッチング処理 する第５の工程と、 を備えたことを特徴とする半導体記憶装置の製造方法 (metal layer coupling area) 。 |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area of said contact region permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area (製造方法) of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
JP2001291846A CLAIM 4 【請求項４】 ワード線間にプラグ領域を設けて半導体 基板と電気的に接続し、該ワード線及び該プラグ領域上 に、第１の絶縁膜、該第１の絶縁膜に対して小さいエッ チングレートを有する第２の絶縁膜、ビット線となる導 電層、該第１の絶縁膜に対して小さいエッチングレート を有する第３の絶縁膜を形成する第１の工程と、 前記第２の絶縁膜、前記導電層及び第３の絶縁膜をパタ ーン化して前記プラグ領域間上にビット線を形成する第 ２の工程と、 パターン化された前記導電層の側壁部に前記第１の絶縁 膜に対して小さいエッチングレートを有する第４の絶縁 膜を形成する第３の工程と、 露出している前記第１の絶縁層を異方性エッチング除去 する第４の工程と、 露出した前記プラグ領域の表面を等方性エッチング処理 する第５の工程と、 を備えたことを特徴とする半導体記憶装置の製造方法 (metal layer coupling area) 。 |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (製造方法) of said contact region . |
JP2001291846A CLAIM 4 【請求項４】 ワード線間にプラグ領域を設けて半導体 基板と電気的に接続し、該ワード線及び該プラグ領域上 に、第１の絶縁膜、該第１の絶縁膜に対して小さいエッ チングレートを有する第２の絶縁膜、ビット線となる導 電層、該第１の絶縁膜に対して小さいエッチングレート を有する第３の絶縁膜を形成する第１の工程と、 前記第２の絶縁膜、前記導電層及び第３の絶縁膜をパタ ーン化して前記プラグ領域間上にビット線を形成する第 ２の工程と、 パターン化された前記導電層の側壁部に前記第１の絶縁 膜に対して小さいエッチングレートを有する第４の絶縁 膜を形成する第３の工程と、 露出している前記第１の絶縁層を異方性エッチング除去 する第４の工程と、 露出した前記プラグ領域の表面を等方性エッチング処理 する第５の工程と、 を備えたことを特徴とする半導体記憶装置の製造方法 (metal layer coupling area) 。 |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US6323130B1 Filed: 2000-03-06 Issued: 2001-11-27 Method for self-aligned formation of silicide contacts using metal silicon alloys for limited silicon consumption and for reduction of bridging (Original Assignee) International Business Machines Corp (Current Assignee) GlobalFoundries Inc Stephen Bruce Brodsky, Cyril Cabral, Jr., Roy Arthur Carruthers, James Mckell Edwin Harper, Christian Lavoie, Patricia Ann O'Neil, Yun Yu Wang |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch (etch process, wet etch) stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch (etch process, wet etch) stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer (etch process, wet etch) over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub (electronic device) interlevel dielectric layer over said second etch stop layer . |
US6323130B1 CLAIM 1 . A method for reducing the silicon consumption and the bridging during metal silicide contact formation comprising the steps of : (a) forming a metal silicon alloy layer over a silicon-containing substrate containing an electronic device (second sub) to be electrically contacted , said silicon in said alloy layer being less than about 30 atomic % and said metal is Co , Ni or mixtures thereof ; (b) annealing said metal silicon alloy layer at a temperature of from about 300° to about 500° C . so as to form a metal rich silicide layer that is substantially non-etchable compared to the metal silicon alloy or pure metal ; (c) selectively removing any non-reacted metal silicon alloy over non-silicon regions ; and (d) annealing said metal rich silicide layer under conditions effective in forming a metal silicide phase that is in its lowest resistance phase . US6323130B1 CLAIM 12 . The method of claim 1 wherein step (c) includes a wet etch process (etch process, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, second etch stop layers) , wherein a chemical etchant is employed . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch (etch process, wet etch) stop layer protects removal of a substrate material by an etch process (etch process, wet etch) . |
US6323130B1 CLAIM 12 . The method of claim 1 wherein step (c) includes a wet etch process (etch process, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, second etch stop layers) , wherein a chemical etchant is employed . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch stop layer (etch process, wet etch) protects lower layers during an etching process (alloy layer) . |
US6323130B1 CLAIM 1 . A method for reducing the silicon consumption and the bridging during metal silicide contact formation comprising the steps of : (a) forming a metal silicon alloy layer (etching process) over a silicon-containing substrate containing an electronic device to be electrically contacted , said silicon in said alloy layer being less than about 30 atomic % and said metal is Co , Ni or mixtures thereof ; (b) annealing said metal silicon alloy layer at a temperature of from about 300° to about 500° C . so as to form a metal rich silicide layer that is substantially non-etchable compared to the metal silicon alloy or pure metal ; (c) selectively removing any non-reacted metal silicon alloy over non-silicon regions ; and (d) annealing said metal rich silicide layer under conditions effective in forming a metal silicide phase that is in its lowest resistance phase . US6323130B1 CLAIM 12 . The method of claim 1 wherein step (c) includes a wet etch process (etch process, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, second etch stop layers) , wherein a chemical etchant is employed . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub (electronic device) interlevel dielectric layer insulates said contact region . |
US6323130B1 CLAIM 1 . A method for reducing the silicon consumption and the bridging during metal silicide contact formation comprising the steps of : (a) forming a metal silicon alloy layer over a silicon-containing substrate containing an electronic device (second sub) to be electrically contacted , said silicon in said alloy layer being less than about 30 atomic % and said metal is Co , Ni or mixtures thereof ; (b) annealing said metal silicon alloy layer at a temperature of from about 300° to about 500° C . so as to form a metal rich silicide layer that is substantially non-etchable compared to the metal silicon alloy or pure metal ; (c) selectively removing any non-reacted metal silicon alloy over non-silicon regions ; and (d) annealing said metal rich silicide layer under conditions effective in forming a metal silicide phase that is in its lowest resistance phase . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch (etch process, wet etch) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer (etch process, wet etch) is in a range of about 300 to 800 Šthick and said second sub (electronic device) interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6323130B1 CLAIM 1 . A method for reducing the silicon consumption and the bridging during metal silicide contact formation comprising the steps of : (a) forming a metal silicon alloy layer over a silicon-containing substrate containing an electronic device (second sub) to be electrically contacted , said silicon in said alloy layer being less than about 30 atomic % and said metal is Co , Ni or mixtures thereof ; (b) annealing said metal silicon alloy layer at a temperature of from about 300° to about 500° C . so as to form a metal rich silicide layer that is substantially non-etchable compared to the metal silicon alloy or pure metal ; (c) selectively removing any non-reacted metal silicon alloy over non-silicon regions ; and (d) annealing said metal rich silicide layer under conditions effective in forming a metal silicide phase that is in its lowest resistance phase . US6323130B1 CLAIM 12 . The method of claim 1 wherein step (c) includes a wet etch process (etch process, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, second etch stop layers) , wherein a chemical etchant is employed . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub (electronic device) interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US6323130B1 CLAIM 1 . A method for reducing the silicon consumption and the bridging during metal silicide contact formation comprising the steps of : (a) forming a metal silicon alloy layer over a silicon-containing substrate containing an electronic device (second sub) to be electrically contacted , said silicon in said alloy layer being less than about 30 atomic % and said metal is Co , Ni or mixtures thereof ; (b) annealing said metal silicon alloy layer at a temperature of from about 300° to about 500° C . so as to form a metal rich silicide layer that is substantially non-etchable compared to the metal silicon alloy or pure metal ; (c) selectively removing any non-reacted metal silicon alloy over non-silicon regions ; and (d) annealing said metal rich silicide layer under conditions effective in forming a metal silicide phase that is in its lowest resistance phase . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch (etch process, wet etch) stop insulation layer comprising a first etch (etch process, wet etch) stop layer and a second etch stop layer (etch process, wet etch) wherein said first etch stop layer and said second etch stop layers (etch process, wet etch) have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric (oxygen barrier layer) layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub (electronic device) interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US6323130B1 CLAIM 1 . A method for reducing the silicon consumption and the bridging during metal silicide contact formation comprising the steps of : (a) forming a metal silicon alloy layer over a silicon-containing substrate containing an electronic device (second sub) to be electrically contacted , said silicon in said alloy layer being less than about 30 atomic % and said metal is Co , Ni or mixtures thereof ; (b) annealing said metal silicon alloy layer at a temperature of from about 300° to about 500° C . so as to form a metal rich silicide layer that is substantially non-etchable compared to the metal silicon alloy or pure metal ; (c) selectively removing any non-reacted metal silicon alloy over non-silicon regions ; and (d) annealing said metal rich silicide layer under conditions effective in forming a metal silicide phase that is in its lowest resistance phase . US6323130B1 CLAIM 8 . The method of claim 3 wherein said optional oxygen barrier layer (second interlevel dielectric, second interlevel dielectric layer) is composed of TiN . US6323130B1 CLAIM 12 . The method of claim 1 wherein step (c) includes a wet etch process (etch process, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, second etch stop layers) , wherein a chemical etchant is employed . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch (etch process, wet etch) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer (etch process, wet etch) is in a range of about 300 to 800 Šthick and said second sub (electronic device) interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6323130B1 CLAIM 1 . A method for reducing the silicon consumption and the bridging during metal silicide contact formation comprising the steps of : (a) forming a metal silicon alloy layer over a silicon-containing substrate containing an electronic device (second sub) to be electrically contacted , said silicon in said alloy layer being less than about 30 atomic % and said metal is Co , Ni or mixtures thereof ; (b) annealing said metal silicon alloy layer at a temperature of from about 300° to about 500° C . so as to form a metal rich silicide layer that is substantially non-etchable compared to the metal silicon alloy or pure metal ; (c) selectively removing any non-reacted metal silicon alloy over non-silicon regions ; and (d) annealing said metal rich silicide layer under conditions effective in forming a metal silicide phase that is in its lowest resistance phase . US6323130B1 CLAIM 12 . The method of claim 1 wherein step (c) includes a wet etch process (etch process, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, second etch stop layers) , wherein a chemical etchant is employed . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | JP2001223269A Filed: 2000-02-10 Issued: 2001-08-17 半導体装置およびその製造方法 (Original Assignee) Nec Corp; 日本電気株式会社 Tatsuya Usami, 達矢 宇佐美 |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area (前記層) of said contact region is smaller than a metal layer coupling area (製造方法) of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer (少なくとも) over said second etch stop layer . |
JP2001223269A CLAIM 3 【請求項３】 前記層 (substrate coupling area) 間絶縁膜、第１の層間絶縁膜およ び第２の層間絶縁膜は、シルセスキオキサン類、あるい は、Ｓｉ−Ｈ結合、Ｓｉ−ＣＨ 3 結合、Ｓｉ−Ｆ結合の うち少なくとも (second sub interlevel dielectric layer) １つの結合を含むポーラスシリカで構成 されて、前記改質層は過剰シリコンを含有するシリコン 酸化膜、あるいは二酸化シリコン膜で構成されているこ とを特徴とする請求項１または請求項２記載の半導体装 置。 JP2001223269A CLAIM 7 【請求項７】 半導体基板上にシルセスキオキサン類、 あるいは、Ｓｉ−Ｈ結合、Ｓｉ−ＣＨ 3 結合、Ｓｉ−Ｆ 結合のうち少なくとも１つの結合を含むポーラスシリカ から成る層間絶縁膜を形成する工程と、前記層間絶縁膜 表面に荷電ビームを照射し前記層間絶縁膜の表面を過剰 シリコンを含有するシリコン酸化膜あるいは二酸化シリ コン膜に改質する工程とを含むことを特徴とする半導体 装置の製造方法 (metal layer coupling area) 。 |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric layer (少なくとも) insulates said contact region . |
JP2001223269A CLAIM 3 【請求項３】 前記層間絶縁膜、第１の層間絶縁膜およ び第２の層間絶縁膜は、シルセスキオキサン類、あるい は、Ｓｉ−Ｈ結合、Ｓｉ−ＣＨ 3 結合、Ｓｉ−Ｆ結合の うち少なくとも (second sub interlevel dielectric layer) １つの結合を含むポーラスシリカで構成 されて、前記改質層は過剰シリコンを含有するシリコン 酸化膜、あるいは二酸化シリコン膜で構成されているこ とを特徴とする請求項１または請求項２記載の半導体装 置。 |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area (前記層) of said contact region permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area (製造方法) of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
JP2001223269A CLAIM 3 【請求項３】 前記層 (substrate coupling area) 間絶縁膜、第１の層間絶縁膜およ び第２の層間絶縁膜は、シルセスキオキサン類、あるい は、Ｓｉ−Ｈ結合、Ｓｉ−ＣＨ 3 結合、Ｓｉ−Ｆ結合の うち少なくとも１つの結合を含むポーラスシリカで構成 されて、前記改質層は過剰シリコンを含有するシリコン 酸化膜、あるいは二酸化シリコン膜で構成されているこ とを特徴とする請求項１または請求項２記載の半導体装 置。 JP2001223269A CLAIM 7 【請求項７】 半導体基板上にシルセスキオキサン類、 あるいは、Ｓｉ−Ｈ結合、Ｓｉ−ＣＨ 3 結合、Ｓｉ−Ｆ 結合のうち少なくとも１つの結合を含むポーラスシリカ から成る層間絶縁膜を形成する工程と、前記層間絶縁膜 表面に荷電ビームを照射し前記層間絶縁膜の表面を過剰 シリコンを含有するシリコン酸化膜あるいは二酸化シリ コン膜に改質する工程とを含むことを特徴とする半導体 装置の製造方法 (metal layer coupling area) 。 |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Å thick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Å thick , said second etch stop layer is in a range of about 300 to 800 Å thick and said second sub interlevel dielectric layer (少なくとも) is in a range of about 10K ű1K Å thick . |
JP2001223269A CLAIM 3 【請求項３】 前記層間絶縁膜、第１の層間絶縁膜およ び第２の層間絶縁膜は、シルセスキオキサン類、あるい は、Ｓｉ−Ｈ結合、Ｓｉ−ＣＨ 3 結合、Ｓｉ−Ｆ結合の うち少なくとも (second sub interlevel dielectric layer) １つの結合を含むポーラスシリカで構成 されて、前記改質層は過剰シリコンを含有するシリコン 酸化膜、あるいは二酸化シリコン膜で構成されているこ とを特徴とする請求項１または請求項２記載の半導体装 置。 |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer (少なくとも) for said contact region is in a second range (あること) of about 0 . 16 μm to 0 . 18 μm wide . |
JP2001223269A CLAIM 3 【請求項３】 前記層間絶縁膜、第１の層間絶縁膜およ び第２の層間絶縁膜は、シルセスキオキサン類、あるい は、Ｓｉ−Ｈ結合、Ｓｉ−ＣＨ 3 結合、Ｓｉ−Ｆ結合の うち少なくとも (second sub interlevel dielectric layer) １つの結合を含むポーラスシリカで構成 されて、前記改質層は過剰シリコンを含有するシリコン 酸化膜、あるいは二酸化シリコン膜で構成されているこ とを特徴とする請求項１または請求項２記載の半導体装 置。 JP2001223269A CLAIM 4 【請求項４】 前記シルセスキオキサン類は、ハイドロ ゲンシルセスキオキサン（Hydrogen Silsesquioxan e）、メチルシルセスキオキサン（Methyl Silsesquioxa ne）、メチレーテッドハイドロゲンシルセスキオキサン （Methylated Hydrogen Silsesquioxane）、フルオリネ ーテッドシルセスキオキサン（Furuorinated Silsesqui oxane）であること (second range) を特徴とする請求項３記載の半導体 装置。 |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer (少なくとも) and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area (前記層) of said contact region is smaller than a metal layer coupling area (製造方法) of said contact region . |
JP2001223269A CLAIM 3 【請求項３】 前記層 (substrate coupling area) 間絶縁膜、第１の層間絶縁膜およ び第２の層間絶縁膜は、シルセスキオキサン類、あるい は、Ｓｉ−Ｈ結合、Ｓｉ−ＣＨ 3 結合、Ｓｉ−Ｆ結合の うち少なくとも (second sub interlevel dielectric layer) １つの結合を含むポーラスシリカで構成 されて、前記改質層は過剰シリコンを含有するシリコン 酸化膜、あるいは二酸化シリコン膜で構成されているこ とを特徴とする請求項１または請求項２記載の半導体装 置。 JP2001223269A CLAIM 7 【請求項７】 半導体基板上にシルセスキオキサン類、 あるいは、Ｓｉ−Ｈ結合、Ｓｉ−ＣＨ 3 結合、Ｓｉ−Ｆ 結合のうち少なくとも１つの結合を含むポーラスシリカ から成る層間絶縁膜を形成する工程と、前記層間絶縁膜 表面に荷電ビームを照射し前記層間絶縁膜の表面を過剰 シリコンを含有するシリコン酸化膜あるいは二酸化シリ コン膜に改質する工程とを含むことを特徴とする半導体 装置の製造方法 (metal layer coupling area) 。 |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Å thick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Å thick , said second etch stop layer is in a range of about 300 to 800 Å thick and said second sub interlevel dielectric layer (少なくとも) is in a range of about 10K ű1K Å thick . |
JP2001223269A CLAIM 3 【請求項３】 前記層間絶縁膜、第１の層間絶縁膜およ び第２の層間絶縁膜は、シルセスキオキサン類、あるい は、Ｓｉ−Ｈ結合、Ｓｉ−ＣＨ 3 結合、Ｓｉ−Ｆ結合の うち少なくとも (second sub interlevel dielectric layer) １つの結合を含むポーラスシリカで構成 されて、前記改質層は過剰シリコンを含有するシリコン 酸化膜、あるいは二酸化シリコン膜で構成されているこ とを特徴とする請求項１または請求項２記載の半導体装 置。 |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region is a first range of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range (あること) of about 0 . 16 μm to 0 . 18 μm wide . |
JP2001223269A CLAIM 4 【請求項４】 前記シルセスキオキサン類は、ハイドロ ゲンシルセスキオキサン（Hydrogen Silsesquioxan e）、メチルシルセスキオキサン（Methyl Silsesquioxa ne）、メチレーテッドハイドロゲンシルセスキオキサン （Methylated Hydrogen Silsesquioxane）、フルオリネ ーテッドシルセスキオキサン（Furuorinated Silsesqui oxane）であること (second range) を特徴とする請求項３記載の半導体 装置。 |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US6177318B1 Filed: 1999-10-18 Issued: 2001-01-23 Integration method for sidewall split gate monos transistor (Original Assignee) Halo LSI Design and Device Technology Inc (Current Assignee) Halo LSI Design and Device Technology Inc Seiki Ogura, Yutaka Hayashi, Tomoko Ogura |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (said stack) of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US6177318B1 CLAIM 1 . A method of fabricating an electrically programmable read only memory device which is a word gate and a control gate wherein the word gate is on the sidewall of the control gate comprising : providing a stack of layers on a silicon substrate , which layers include a gate silicon oxide layer , a conductive polysilicon gate layer , a silicon oxide layer and a silicon nitride layer ; etching said silicon nitride layer to the dimension of said word gate ; forming a block out mask over said silicon nitride layer of the dimension of said control/word gate to allow only the side uncovered to which said word gate is to be formed ; vertically etching said stack (metal layer coupling area) of layers to said gate silicon oxide layer to form a vertical sidewall while using said silicon nitride layer on said side uncovered as the mask ; removing said block out mask ; forming a insulator layer on said vertical sidewall ; forming a disposable sidewall spacer layer on said vertical sidewall over said insulator layer , wherein the width of said spacer layer is the channel for said device ; ion implanting a N type dopant into said substrate to form a device region therein ; removing said disposable sidewall spacer layer ; removing the exposed gate silicon oxide layer ; forming a composite layer of silicon oxide , silicon nitride and silicon oxide over said vertical sidewall and device region ; and forming said control gate sidewall spacer on said vertical sidewall and said composite layer . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer protects removal of a substrate material by an etch process (ion implantation) . |
US6177318B1 CLAIM 11 . A method of fabricating an electrically programmable read only memory device which is a word gate and a MONOS control gate on the sidewall of the word gate while also fabricating logic gates associated therewith in the same silicon substrate comprising : providing a stack of layers on a silicon substrate , which layers include a gate silicon oxide layer , a conductive polysilicon gate layer , a silicon oxide layer and a silicon nitride layer ; etching said silicon nitride layer to the dimension of said control/word gate in the memory cell area and to the dimension of the logic gate in the non-memory areas ; forming a block out mask over said silicon nitride layer of the dimension of said word gate to allow only the side uncovered to which said control gate is to be formed ; vertically etching said stack of layers to said gate silicon oxide layer to form a vertical sidewall while using said silicon nitride layer on said side uncovered as the mask ; removing said block out mask ; forming a insulator layer on said vertical sidewall ; simultaneously ion implanting boron and arsenic ions into the exposed substrate which results in doping the control gate channel region in the finished device and enhances ballistic injection ; forming a disposable sidewall spacer layer on said vertical sidewall and over said insulator layer , wherein the width of said spacer layer is the channel for said device ; ion implanting a N type dopant into said substrate to form a device region therein ; removing said disposable sidewall spacer layer and the exposed said gate silicon oxide layer ; forming a composite layer of silicon oxide , silicon nitride and silicon oxide over said vertical sidewall and over said channel and said device region ; forming said control gate sidewall spacer on said vertical sidewall and over said composite layer , and over the channel ; forming a second block out mask over said silicon nitride layer to cover and protect said control/word gate and said control gate and to allow all other areas to be uncovered ; removing the exposed said silicon oxide layer ; vertically etching said polysilicon layer to said gate silicon oxide layer to form a vertical sidewall on the opposite side of said control gate in the memory device area and to form the logic device gates in the said logic areas while using said silicon nitride layer on said side uncovered as the mask ; removing said second block out mask ; and forming lightly doped drain devices by ion implantation (etch process) and forming sidewall spaces using a sidewall spacer technique in said logic areas at said logic gates . |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area of said contact region permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area (said stack) of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
US6177318B1 CLAIM 1 . A method of fabricating an electrically programmable read only memory device which is a word gate and a control gate wherein the word gate is on the sidewall of the control gate comprising : providing a stack of layers on a silicon substrate , which layers include a gate silicon oxide layer , a conductive polysilicon gate layer , a silicon oxide layer and a silicon nitride layer ; etching said silicon nitride layer to the dimension of said word gate ; forming a block out mask over said silicon nitride layer of the dimension of said control/word gate to allow only the side uncovered to which said word gate is to be formed ; vertically etching said stack (metal layer coupling area) of layers to said gate silicon oxide layer to form a vertical sidewall while using said silicon nitride layer on said side uncovered as the mask ; removing said block out mask ; forming a insulator layer on said vertical sidewall ; forming a disposable sidewall spacer layer on said vertical sidewall over said insulator layer , wherein the width of said spacer layer is the channel for said device ; ion implanting a N type dopant into said substrate to form a device region therein ; removing said disposable sidewall spacer layer ; removing the exposed gate silicon oxide layer ; forming a composite layer of silicon oxide , silicon nitride and silicon oxide over said vertical sidewall and device region ; and forming said control gate sidewall spacer on said vertical sidewall and said composite layer . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space (said sub) in a portion of said first sub interlevel dielectric layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US6177318B1 CLAIM 1 . A method of fabricating an electrically programmable read only memory device which is a word gate and a control gate wherein the word gate is on the sidewall of the control gate comprising : providing a stack of layers on a silicon substrate , which layers include a gate silicon oxide layer , a conductive polysilicon gate layer , a silicon oxide layer and a silicon nitride layer ; etching said silicon nitride layer to the dimension of said word gate ; forming a block out mask over said silicon nitride layer of the dimension of said control/word gate to allow only the side uncovered to which said word gate is to be formed ; vertically etching said stack of layers to said gate silicon oxide layer to form a vertical sidewall while using said silicon nitride layer on said side uncovered as the mask ; removing said block out mask ; forming a insulator layer on said vertical sidewall ; forming a disposable sidewall spacer layer on said vertical sidewall over said insulator layer , wherein the width of said spacer layer is the channel for said device ; ion implanting a N type dopant into said sub (first space) strate to form a device region therein ; removing said disposable sidewall spacer layer ; removing the exposed gate silicon oxide layer ; forming a composite layer of silicon oxide , silicon nitride and silicon oxide over said vertical sidewall and device region ; and forming said control gate sidewall spacer on said vertical sidewall and said composite layer . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US6177318B1 CLAIM 1 . A method of fabricating an electrically programmable read only memory device which is a word gate and a control gate wherein the word gate is on the sidewall of the control gate comprising : providing a stack of layers on a silicon substrate , which layers include a gate silicon oxide layer , a conductive polysilicon gate layer , a silicon oxide layer and a silicon nitride layer ; etching said silicon nitride layer to the dimension of said word gate ; forming a block out mask over said silicon nitride layer of the dimension of said control/word gate to allow only the side uncovered to which said word gate is to be formed ; vertically etching said stack of layers to said gate silicon oxide layer to form a vertical sidewall while using said silicon nitride layer on said side uncovered as the mask ; removing said block out mask ; forming a insulator layer on said vertical sidewall ; forming a disposable sidewall spacer layer on said vertical sidewall over said insulator layer , wherein the width of said spacer layer is the channel for said device ; ion implanting a N type dopant into said substrate to form a device region therein ; removing said disposable sidewall spacer layer ; removing the exposed gate silicon oxide layer ; forming a composite layer of silicon oxide , silicon nitride and silicon oxide over said vertical sidewall and device region ; and forming (anti reflective coating) said control gate sidewall spacer on said vertical sidewall and said composite layer . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (said stack) of said contact region . |
US6177318B1 CLAIM 1 . A method of fabricating an electrically programmable read only memory device which is a word gate and a control gate wherein the word gate is on the sidewall of the control gate comprising : providing a stack of layers on a silicon substrate , which layers include a gate silicon oxide layer , a conductive polysilicon gate layer , a silicon oxide layer and a silicon nitride layer ; etching said silicon nitride layer to the dimension of said word gate ; forming a block out mask over said silicon nitride layer of the dimension of said control/word gate to allow only the side uncovered to which said word gate is to be formed ; vertically etching said stack (metal layer coupling area) of layers to said gate silicon oxide layer to form a vertical sidewall while using said silicon nitride layer on said side uncovered as the mask ; removing said block out mask ; forming a insulator layer on said vertical sidewall ; forming a disposable sidewall spacer layer on said vertical sidewall over said insulator layer , wherein the width of said spacer layer is the channel for said device ; ion implanting a N type dopant into said substrate to form a device region therein ; removing said disposable sidewall spacer layer ; removing the exposed gate silicon oxide layer ; forming a composite layer of silicon oxide , silicon nitride and silicon oxide over said vertical sidewall and device region ; and forming said control gate sidewall spacer on said vertical sidewall and said composite layer . |
| US7977797B2 CLAIM 13 . An integrated circuit of claim 11 further comprising a floating gate (floating gate) . |
US6177318B1 CLAIM 18 . A method of fabricating an electrically programmable read only memory device which is a word gate , and a MONOS control gate on the sidewall of the word gate , and an ultra short , non-planar channel comprising : providing a stack of layers on a silicon substrate , which layers include a gate silicon oxide layer , a conductive polysilicon gate layer , a silicon oxide layer and a silicon nitride layer ; etching said silicon nitride layer to the dimension of said word gate ; forming a block out mask over said silicon nitride layer of the dimension of said control/word gate to allow only the side uncovered to which said control gate is to be formed ; vertically etching said stack of layers to said gate silicon oxide layer to form a vertical sidewall while using said silicon nitride layer on said side uncovered as the mask ; removing said block out mask ; forming a insulator layer on said vertical sidewall ; forming a disposable sidewall spacer layer on said vertical sidewall over said insulator layer , wherein the width of said spacer layer is the channel for said device ; vertically etching into said substrate to form a step within said substrate ; ion implanting a N type dopant into said step within said substrate to form a device region therein having said non-planar channel ; removing said disposable sidewall spacer layer and the exposed said silicon oxide gate layer ; forming a composite layer of silicon oxide , silicon nitride and silicon oxide over said vertical sidewall and over said channel and said device region ; and forming said floating gate (floating gate) sidewall spacer over said composite layer and said vertical sidewall and over said channel . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US6177318B1 CLAIM 1 . A method of fabricating an electrically programmable read only memory device which is a word gate and a control gate wherein the word gate is on the sidewall of the control gate comprising : providing a stack of layers on a silicon substrate , which layers include a gate silicon oxide layer , a conductive polysilicon gate layer , a silicon oxide layer and a silicon nitride layer ; etching said silicon nitride layer to the dimension of said word gate ; forming a block out mask over said silicon nitride layer of the dimension of said control/word gate to allow only the side uncovered to which said word gate is to be formed ; vertically etching said stack of layers to said gate silicon oxide layer to form a vertical sidewall while using said silicon nitride layer on said side uncovered as the mask ; removing said block out mask ; forming a insulator layer on said vertical sidewall ; forming a disposable sidewall spacer layer on said vertical sidewall over said insulator layer , wherein the width of said spacer layer is the channel for said device ; ion implanting a N type dopant into said substrate to form a device region therein ; removing said disposable sidewall spacer layer ; removing the exposed gate silicon oxide layer ; forming a composite layer of silicon oxide , silicon nitride and silicon oxide over said vertical sidewall and device region ; and forming (anti reflective coating) said control gate sidewall spacer on said vertical sidewall and said composite layer . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | JP2001053144A Filed: 1999-08-16 Issued: 2001-02-23 半導体装置及びその製造方法 (Original Assignee) Matsushita Electronics Industry Corp; 松下電子工業株式会社 Shinichi Domae, Isao Miyanaga, Tetsuya Ueda, 哲也 上田, 伸一 堂前, 績 宮永 |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area (前記層) of said contact region is smaller than a metal layer coupling area (製造方法) of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation (の絶縁) between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
JP2001053144A CLAIM 1 【請求項１】 半導体基板上に形成された複数の配線 と、該複数の配線の上に堆積された層間絶縁膜に前記配 線と接続するように埋め込まれたヴィアコンタクトとを 備えた半導体装置の製造方法 (metal layer coupling area) であって、 前記半導体基板の上に前記複数の配線を形成する工程 と、 前記複数の配線の上面及び側面並びに前記半導体基板の 上に、前記層 (substrate coupling area) 間絶縁膜に対してエッチング選択性を有す る絶縁膜を堆積する工程と、 前記絶縁膜の上に前記層間絶縁膜を、前記複数の配線の うち互いに近接している前記配線同士の間に空孔が形成 されるように堆積する工程と、 前記層間絶縁膜及び前記絶縁膜に前記配線の上面を露出 させるヴィアホールを形成する工程と、 前記ヴィアホールに導電性材料を充填することにより、 該導電性材料からなる前記ヴィアコンタクトを形成する 工程とを備えていることを特徴とする半導体装置の製造 方法。 JP2001053144A CLAIM 3 【請求項３】 複数の埋め込み配線と、該複数の埋め込 み配線の上に堆積された層間絶縁膜とを備えた半導体装 置の製造方法であって、 半導体基板上に堆積された第１の絶縁 (electrical insulation) 膜に複数の配線溝 を形成する工程と、 前記複数の配線溝に導電性材料を埋め込むことにより、 前記導電性材料からなる前記複数の埋め込み配線を形成 する工程と、 前記第１の絶縁膜における前記複数の埋め込み配線同士 の間の部分を除去した後、前記複数の埋め込み配線の上 面及び側面に第２の絶縁膜を堆積する工程と、 前記第２の絶縁膜の上を含む前記半導体基板の上に前記 層間絶縁膜を、前記複数の埋め込み配線のうち互いに近 接している前記埋め込み配線同士の間に空孔が形成され るように堆積する工程とを備えていることを特徴とする 半導体装置の製造方法。 |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area (前記層) of said contact region permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area (製造方法) of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
JP2001053144A CLAIM 1 【請求項１】 半導体基板上に形成された複数の配線 と、該複数の配線の上に堆積された層間絶縁膜に前記配 線と接続するように埋め込まれたヴィアコンタクトとを 備えた半導体装置の製造方法 (metal layer coupling area) であって、 前記半導体基板の上に前記複数の配線を形成する工程 と、 前記複数の配線の上面及び側面並びに前記半導体基板の 上に、前記層 (substrate coupling area) 間絶縁膜に対してエッチング選択性を有す る絶縁膜を堆積する工程と、 前記絶縁膜の上に前記層間絶縁膜を、前記複数の配線の うち互いに近接している前記配線同士の間に空孔が形成 されるように堆積する工程と、 前記層間絶縁膜及び前記絶縁膜に前記配線の上面を露出 させるヴィアホールを形成する工程と、 前記ヴィアホールに導電性材料を充填することにより、 該導電性材料からなる前記ヴィアコンタクトを形成する 工程とを備えていることを特徴とする半導体装置の製造 方法。 |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area (前記層) of said contact region is smaller than a metal layer coupling area (製造方法) of said contact region . |
JP2001053144A CLAIM 1 【請求項１】 半導体基板上に形成された複数の配線 と、該複数の配線の上に堆積された層間絶縁膜に前記配 線と接続するように埋め込まれたヴィアコンタクトとを 備えた半導体装置の製造方法 (metal layer coupling area) であって、 前記半導体基板の上に前記複数の配線を形成する工程 と、 前記複数の配線の上面及び側面並びに前記半導体基板の 上に、前記層 (substrate coupling area) 間絶縁膜に対してエッチング選択性を有す る絶縁膜を堆積する工程と、 前記絶縁膜の上に前記層間絶縁膜を、前記複数の配線の うち互いに近接している前記配線同士の間に空孔が形成 されるように堆積する工程と、 前記層間絶縁膜及び前記絶縁膜に前記配線の上面を露出 させるヴィアホールを形成する工程と、 前記ヴィアホールに導電性材料を充填することにより、 該導電性材料からなる前記ヴィアコンタクトを形成する 工程とを備えていることを特徴とする半導体装置の製造 方法。 |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US6117725A Filed: 1999-08-11 Issued: 2000-09-12 Method for making cost-effective embedded DRAM structures compatible with logic circuit processing (Original Assignee) Taiwan Semiconductor Manufacturing Co TSMC Ltd (Current Assignee) Taiwan Semiconductor Manufacturing Co TSMC Ltd Jenn Ming Huang |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer (bottom electrode) over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US6117725A CLAIM 1 . A method for fabricating embedded DRAM circuits with logic circuits comprising the steps of : providing a semiconductor substrate having logic regions and memory regions having device areas , said logic regions having salicide FETS ; forming a planar first insulating layer on said substrate ; etching first openings in said first insulating layer for contacts to said salicide FETs and concurrently etching openings for bit-line contacts and capacitor node contacts in said memory regions ; forming metal plugs in said openings ; forming a patterned first metal layer for a first level of metal interconnections including bit lines for said DRAM circuits ; forming a planar second insulating layer and etching second openings over and to said capacitor node contacts , and etching via holes for said salicide FETs , and forming metal bottom electrode (second interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) s in said second openings and metal contacts in said via holes ; depositing and patterning an interelectrode dielectric layer leaving portions over said capacitor bottom electrodes ; depositing and patterning a second metal layer to form a second level of interconnections and concurrently forming capacitor top electrodes . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer protects removal of a substrate material (silicon oxide) by an etch process . |
US6117725A CLAIM 4 . The method of claim 1 , wherein said second insulating layer is silicon oxide (substrate material) , deposited by plasma-enhanced chemical vapor deposition at a temperature of between about 100 and 400° C . , and is planarized by chemical-mechanical polishing to have a thickness of between about 8000 and 12000 Angstroms over said patterned first metal layer . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric layer (bottom electrode) insulates said contact region . |
US6117725A CLAIM 1 . A method for fabricating embedded DRAM circuits with logic circuits comprising the steps of : providing a semiconductor substrate having logic regions and memory regions having device areas , said logic regions having salicide FETS ; forming a planar first insulating layer on said substrate ; etching first openings in said first insulating layer for contacts to said salicide FETs and concurrently etching openings for bit-line contacts and capacitor node contacts in said memory regions ; forming metal plugs in said openings ; forming a patterned first metal layer for a first level of metal interconnections including bit lines for said DRAM circuits ; forming a planar second insulating layer and etching second openings over and to said capacitor node contacts , and etching via holes for said salicide FETs , and forming metal bottom electrode (second interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) s in said second openings and metal contacts in said via holes ; depositing and patterning an interelectrode dielectric layer leaving portions over said capacitor bottom electrodes ; depositing and patterning a second metal layer to form a second level of interconnections and concurrently forming capacitor top electrodes . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer (bottom electrode) is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6117725A CLAIM 1 . A method for fabricating embedded DRAM circuits with logic circuits comprising the steps of : providing a semiconductor substrate having logic regions and memory regions having device areas , said logic regions having salicide FETS ; forming a planar first insulating layer on said substrate ; etching first openings in said first insulating layer for contacts to said salicide FETs and concurrently etching openings for bit-line contacts and capacitor node contacts in said memory regions ; forming metal plugs in said openings ; forming a patterned first metal layer for a first level of metal interconnections including bit lines for said DRAM circuits ; forming a planar second insulating layer and etching second openings over and to said capacitor node contacts , and etching via holes for said salicide FETs , and forming metal bottom electrode (second interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) s in said second openings and metal contacts in said via holes ; depositing and patterning an interelectrode dielectric layer leaving portions over said capacitor bottom electrodes ; depositing and patterning a second metal layer to form a second level of interconnections and concurrently forming capacitor top electrodes . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space (said sub) in a portion of said first sub interlevel dielectric layer (bottom electrode) for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US6117725A CLAIM 1 . A method for fabricating embedded DRAM circuits with logic circuits comprising the steps of : providing a semiconductor substrate having logic regions and memory regions having device areas , said logic regions having salicide FETS ; forming a planar first insulating layer on said sub (first space) strate ; etching first openings in said first insulating layer for contacts to said salicide FETs and concurrently etching openings for bit-line contacts and capacitor node contacts in said memory regions ; forming metal plugs in said openings ; forming a patterned first metal layer for a first level of metal interconnections including bit lines for said DRAM circuits ; forming a planar second insulating layer and etching second openings over and to said capacitor node contacts , and etching via holes for said salicide FETs , and forming metal bottom electrode (second interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) s in said second openings and metal contacts in said via holes ; depositing and patterning an interelectrode dielectric layer leaving portions over said capacitor bottom electrodes ; depositing and patterning a second metal layer to form a second level of interconnections and concurrently forming capacitor top electrodes . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US6117725A CLAIM 1 . A method for fabricating embedded DRAM circuits with logic circuits comprising the steps of : providing a semiconductor substrate having logic regions and memory regions having device areas , said logic regions having salicide FETS ; forming a planar first insulating layer on said substrate ; etching first openings in said first insulating layer for contacts to said salicide FETs and concurrently etching openings for bit-line contacts and capacitor node contacts in said memory regions ; forming metal plugs in said openings ; forming a patterned first metal layer for a first level of metal interconnections including bit lines for said DRAM circuits ; forming a planar second insulating layer and etching second openings over and to said capacitor node contacts , and etching via holes for said salicide FETs , and forming (anti reflective coating) metal bottom electrodes in said second openings and metal contacts in said via holes ; depositing and patterning an interelectrode dielectric layer leaving portions over said capacitor bottom electrodes ; depositing and patterning a second metal layer to form a second level of interconnections and concurrently forming capacitor top electrodes . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer (bottom electrode) and said second etch stop layer formed under a second interlevel dielectric (bottom electrode) layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US6117725A CLAIM 1 . A method for fabricating embedded DRAM circuits with logic circuits comprising the steps of : providing a semiconductor substrate having logic regions and memory regions having device areas , said logic regions having salicide FETS ; forming a planar first insulating layer on said substrate ; etching first openings in said first insulating layer for contacts to said salicide FETs and concurrently etching openings for bit-line contacts and capacitor node contacts in said memory regions ; forming metal plugs in said openings ; forming a patterned first metal layer for a first level of metal interconnections including bit lines for said DRAM circuits ; forming a planar second insulating layer and etching second openings over and to said capacitor node contacts , and etching via holes for said salicide FETs , and forming metal bottom electrode (second interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) s in said second openings and metal contacts in said via holes ; depositing and patterning an interelectrode dielectric layer leaving portions over said capacitor bottom electrodes ; depositing and patterning a second metal layer to form a second level of interconnections and concurrently forming capacitor top electrodes . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer (bottom electrode) is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6117725A CLAIM 1 . A method for fabricating embedded DRAM circuits with logic circuits comprising the steps of : providing a semiconductor substrate having logic regions and memory regions having device areas , said logic regions having salicide FETS ; forming a planar first insulating layer on said substrate ; etching first openings in said first insulating layer for contacts to said salicide FETs and concurrently etching openings for bit-line contacts and capacitor node contacts in said memory regions ; forming metal plugs in said openings ; forming a patterned first metal layer for a first level of metal interconnections including bit lines for said DRAM circuits ; forming a planar second insulating layer and etching second openings over and to said capacitor node contacts , and etching via holes for said salicide FETs , and forming metal bottom electrode (second interlevel dielectric, first sub interlevel dielectric layer, second interlevel dielectric layer) s in said second openings and metal contacts in said via holes ; depositing and patterning an interelectrode dielectric layer leaving portions over said capacitor bottom electrodes ; depositing and patterning a second metal layer to form a second level of interconnections and concurrently forming capacitor top electrodes . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US6117725A CLAIM 1 . A method for fabricating embedded DRAM circuits with logic circuits comprising the steps of : providing a semiconductor substrate having logic regions and memory regions having device areas , said logic regions having salicide FETS ; forming a planar first insulating layer on said substrate ; etching first openings in said first insulating layer for contacts to said salicide FETs and concurrently etching openings for bit-line contacts and capacitor node contacts in said memory regions ; forming metal plugs in said openings ; forming a patterned first metal layer for a first level of metal interconnections including bit lines for said DRAM circuits ; forming a planar second insulating layer and etching second openings over and to said capacitor node contacts , and etching via holes for said salicide FETs , and forming (anti reflective coating) metal bottom electrodes in said second openings and metal contacts in said via holes ; depositing and patterning an interelectrode dielectric layer leaving portions over said capacitor bottom electrodes ; depositing and patterning a second metal layer to form a second level of interconnections and concurrently forming capacitor top electrodes . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US6251790B1 Filed: 1999-07-09 Issued: 2001-06-26 Method for fabricating contacts in a semiconductor device (Original Assignee) Samsung Electronics Co Ltd (Current Assignee) Samsung Electronics Co Ltd In-kwon Jeong |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch (tungsten nitride) stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (contact hole, contact plug) layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US6251790B1 CLAIM 1 . A method of forming a contact between conductors in a semiconductor device comprising : forming an insulating layer on a semiconductor substrate having a first conductor region ; etching said insulating layer down to said first conductor region to form an opening ; forming a contact plug (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) to be recessed a predetermined depth from a top surface of said insulating layer in said opening ; forming a sidewall spacer on both sidewalls of a remainder of said opening ; forming a conductive layer in said remainder of said opening and on said insulating layer ; and patterning said conductive layer to form a second conductor region that is electrically connected to said first conductor region through said contact plug . US6251790B1 CLAIM 3 . The method according to claim 1 , wherein said contact plug is made of a material selected from the group consisting of silicon , tungsten , aluminum , titanium , titanium nitride , tungsten nitride (multiple etch) , copper , platinum , Au (gold) and Ag (silver) . US6251790B1 CLAIM 9 . A method for fabricating a semiconductor device comprising : forming a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) in an insulating layer which is formed on a semiconductor substrate ; forming a contact plug to be recessed a predetermined depth from a top surface of said insulating layer in said contact hole ; forming a sidewall spacer on both sidewalls of a remainder of said contact hole ; and planarization etching a partial thickness of said insulating layer and said spacer so as to obtain uniform thickness of said sidewall spacer . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer protects removal of a substrate material (silicon oxide) by an etch process . |
US6251790B1 CLAIM 5 . The method according to claim 1 , wherein said sidewall spacer is made of at least one material selected from the group consisting of tungsten , titanium , silicon and compounds such as silicon oxide (substrate material) (Si—O) , silicon oxynitride (Si—O—N) , silicon nitride (Si—N) , aluminum oxide (Al—O) , aluminum nitride (Al—N) , boron nitride (B—N) , titanium nitride (Ti—N) , tungsten silicide (W—Si) and tungsten nitride (W—N) . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (contact hole, contact plug) layer insulates said contact region . |
US6251790B1 CLAIM 1 . A method of forming a contact between conductors in a semiconductor device comprising : forming an insulating layer on a semiconductor substrate having a first conductor region ; etching said insulating layer down to said first conductor region to form an opening ; forming a contact plug (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) to be recessed a predetermined depth from a top surface of said insulating layer in said opening ; forming a sidewall spacer on both sidewalls of a remainder of said opening ; forming a conductive layer in said remainder of said opening and on said insulating layer ; and patterning said conductive layer to form a second conductor region that is electrically connected to said first conductor region through said contact plug . US6251790B1 CLAIM 9 . A method for fabricating a semiconductor device comprising : forming a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) in an insulating layer which is formed on a semiconductor substrate ; forming a contact plug to be recessed a predetermined depth from a top surface of said insulating layer in said contact hole ; forming a sidewall spacer on both sidewalls of a remainder of said contact hole ; and planarization etching a partial thickness of said insulating layer and said spacer so as to obtain uniform thickness of said sidewall spacer . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch stop layer protects lower layers during an etching process (uniform thickness) . |
US6251790B1 CLAIM 7 . The method according to claim 6 , wherein said forming said conductive layer is preceded by completely filling said opening with a conductive material , planarizing said conductive material and a partial thickness of said insulating layer so as to obtain uniform thickness (etching process) of said sidewall spacer at a top portion and a bottom portion . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (contact hole, contact plug) layer insulates said contact region . |
US6251790B1 CLAIM 1 . A method of forming a contact between conductors in a semiconductor device comprising : forming an insulating layer on a semiconductor substrate having a first conductor region ; etching said insulating layer down to said first conductor region to form an opening ; forming a contact plug (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) to be recessed a predetermined depth from a top surface of said insulating layer in said opening ; forming a sidewall spacer on both sidewalls of a remainder of said opening ; forming a conductive layer in said remainder of said opening and on said insulating layer ; and patterning said conductive layer to form a second conductor region that is electrically connected to said first conductor region through said contact plug . US6251790B1 CLAIM 9 . A method for fabricating a semiconductor device comprising : forming a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) in an insulating layer which is formed on a semiconductor substrate ; forming a contact plug to be recessed a predetermined depth from a top surface of said insulating layer in said contact hole ; forming a sidewall spacer on both sidewalls of a remainder of said contact hole ; and planarization etching a partial thickness of said insulating layer and said spacer so as to obtain uniform thickness of said sidewall spacer . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (contact hole, contact plug) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6251790B1 CLAIM 1 . A method of forming a contact between conductors in a semiconductor device comprising : forming an insulating layer on a semiconductor substrate having a first conductor region ; etching said insulating layer down to said first conductor region to form an opening ; forming a contact plug (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) to be recessed a predetermined depth from a top surface of said insulating layer in said opening ; forming a sidewall spacer on both sidewalls of a remainder of said opening ; forming a conductive layer in said remainder of said opening and on said insulating layer ; and patterning said conductive layer to form a second conductor region that is electrically connected to said first conductor region through said contact plug . US6251790B1 CLAIM 9 . A method for fabricating a semiconductor device comprising : forming a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) in an insulating layer which is formed on a semiconductor substrate ; forming a contact plug to be recessed a predetermined depth from a top surface of said insulating layer in said contact hole ; forming a sidewall spacer on both sidewalls of a remainder of said contact hole ; and planarization etching a partial thickness of said insulating layer and said spacer so as to obtain uniform thickness of said sidewall spacer . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric (contact hole, contact plug) layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US6251790B1 CLAIM 1 . A method of forming a contact between conductors in a semiconductor device comprising : forming an insulating layer on a semiconductor substrate having a first conductor region ; etching said insulating layer down to said first conductor region to form an opening ; forming a contact plug (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) to be recessed a predetermined depth from a top surface of said insulating layer in said opening ; forming a sidewall spacer on both sidewalls of a remainder of said opening ; forming a conductive layer in said remainder of said opening and on said insulating layer ; and patterning said conductive layer to form a second conductor region that is electrically connected to said first conductor region through said contact plug . US6251790B1 CLAIM 9 . A method for fabricating a semiconductor device comprising : forming a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) in an insulating layer which is formed on a semiconductor substrate ; forming a contact plug to be recessed a predetermined depth from a top surface of said insulating layer in said contact hole ; forming a sidewall spacer on both sidewalls of a remainder of said contact hole ; and planarization etching a partial thickness of said insulating layer and said spacer so as to obtain uniform thickness of said sidewall spacer . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US6251790B1 CLAIM 6 . The method according to claim 1 , wherein said forming (anti reflective coating) a sidewall spacer comprises depositing a spacer material layer in said remainder of said opening and on said insulating layer , etching back said spacer material layer . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch (tungsten nitride) stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (contact hole, contact plug) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom (top portion) , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US6251790B1 CLAIM 1 . A method of forming a contact between conductors in a semiconductor device comprising : forming an insulating layer on a semiconductor substrate having a first conductor region ; etching said insulating layer down to said first conductor region to form an opening ; forming a contact plug (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) to be recessed a predetermined depth from a top surface of said insulating layer in said opening ; forming a sidewall spacer on both sidewalls of a remainder of said opening ; forming a conductive layer in said remainder of said opening and on said insulating layer ; and patterning said conductive layer to form a second conductor region that is electrically connected to said first conductor region through said contact plug . US6251790B1 CLAIM 3 . The method according to claim 1 , wherein said contact plug is made of a material selected from the group consisting of silicon , tungsten , aluminum , titanium , titanium nitride , tungsten nitride (multiple etch) , copper , platinum , Au (gold) and Ag (silver) . US6251790B1 CLAIM 7 . The method according to claim 6 , wherein said forming said conductive layer is preceded by completely filling said opening with a conductive material , planarizing said conductive material and a partial thickness of said insulating layer so as to obtain uniform thickness of said sidewall spacer at a top portion (contact bottom) and a bottom portion . US6251790B1 CLAIM 9 . A method for fabricating a semiconductor device comprising : forming a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) in an insulating layer which is formed on a semiconductor substrate ; forming a contact plug to be recessed a predetermined depth from a top surface of said insulating layer in said contact hole ; forming a sidewall spacer on both sidewalls of a remainder of said contact hole ; and planarization etching a partial thickness of said insulating layer and said spacer so as to obtain uniform thickness of said sidewall spacer . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (contact hole, contact plug) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6251790B1 CLAIM 1 . A method of forming a contact between conductors in a semiconductor device comprising : forming an insulating layer on a semiconductor substrate having a first conductor region ; etching said insulating layer down to said first conductor region to form an opening ; forming a contact plug (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) to be recessed a predetermined depth from a top surface of said insulating layer in said opening ; forming a sidewall spacer on both sidewalls of a remainder of said opening ; forming a conductive layer in said remainder of said opening and on said insulating layer ; and patterning said conductive layer to form a second conductor region that is electrically connected to said first conductor region through said contact plug . US6251790B1 CLAIM 9 . A method for fabricating a semiconductor device comprising : forming a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) in an insulating layer which is formed on a semiconductor substrate ; forming a contact plug to be recessed a predetermined depth from a top surface of said insulating layer in said contact hole ; forming a sidewall spacer on both sidewalls of a remainder of said contact hole ; and planarization etching a partial thickness of said insulating layer and said spacer so as to obtain uniform thickness of said sidewall spacer . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US6251790B1 CLAIM 6 . The method according to claim 1 , wherein said forming (anti reflective coating) a sidewall spacer comprises depositing a spacer material layer in said remainder of said opening and on said insulating layer , etching back said spacer material layer . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US6355567B1 Filed: 1999-06-30 Issued: 2002-03-12 Retrograde openings in thin films (Original Assignee) International Business Machines Corp (Current Assignee) International Business Machines Corp Scott D. Halle, Paul C. Jamison, David E. Kotecki, Richard S. Wise |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch (first etch) stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch (second etch) stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US6355567B1 CLAIM 1 . A process for forming a retrograde opening in a film , comprising the steps of ; (a) forming a film having : (1) a top , (2) bottom , and (3) characteristic that varies in the same sense from the top of the film to the bottom of the film ; (b) applying a first etch (first etch) ant to anisotropically etch an opening in the film extending downward from the top of the film ; and (c) applying a second etch (second etch) ant : (1) to isotropically etch the opening in the film , and (2) having a composition based on the characteristic of the film to produce further etching of the film at a first etch rate at a lower portion of the opening that is greater than a second etch rate at a higher portion of the opening resulting in a tapered retrograde opening having a top width and a bottom width greater than the top width . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch (first etch) stop layer protects removal of a substrate material (active ion) by an etch process (chemical etching) . |
US6355567B1 CLAIM 1 . A process for forming a retrograde opening in a film , comprising the steps of ; (a) forming a film having : (1) a top , (2) bottom , and (3) characteristic that varies in the same sense from the top of the film to the bottom of the film ; (b) applying a first etch (first etch) ant to anisotropically etch an opening in the film extending downward from the top of the film ; and (c) applying a second etchant : (1) to isotropically etch the opening in the film , and (2) having a composition based on the characteristic of the film to produce further etching of the film at a first etch rate at a lower portion of the opening that is greater than a second etch rate at a higher portion of the opening resulting in a tapered retrograde opening having a top width and a bottom width greater than the top width . US6355567B1 CLAIM 5 . The process as in claim 1 , wherein the step (b) comprises reactive ion (substrate material) etching which is non-selective to the characteristic . US6355567B1 CLAIM 9 . The process as in claim 1 , wherein the step (c) comprises dry chemical etching (etch process) . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch (second etch) stop layer protects lower layers during an etching process . |
US6355567B1 CLAIM 1 . A process for forming a retrograde opening in a film , comprising the steps of ; (a) forming a film having : (1) a top , (2) bottom , and (3) characteristic that varies in the same sense from the top of the film to the bottom of the film ; (b) applying a first etchant to anisotropically etch an opening in the film extending downward from the top of the film ; and (c) applying a second etch (second etch) ant : (1) to isotropically etch the opening in the film , and (2) having a composition based on the characteristic of the film to produce further etching of the film at a first etch rate at a lower portion of the opening that is greater than a second etch rate at a higher portion of the opening resulting in a tapered retrograde opening having a top width and a bottom width greater than the top width . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch (first etch) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (second etch) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6355567B1 CLAIM 1 . A process for forming a retrograde opening in a film , comprising the steps of ; (a) forming a film having : (1) a top , (2) bottom , and (3) characteristic that varies in the same sense from the top of the film to the bottom of the film ; (b) applying a first etch (first etch) ant to anisotropically etch an opening in the film extending downward from the top of the film ; and (c) applying a second etch (second etch) ant : (1) to isotropically etch the opening in the film , and (2) having a composition based on the characteristic of the film to produce further etching of the film at a first etch rate at a lower portion of the opening that is greater than a second etch rate at a higher portion of the opening resulting in a tapered retrograde opening having a top width and a bottom width greater than the top width . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch (first etch) stop layer and a second etch (second etch) stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US6355567B1 CLAIM 1 . A process for forming a retrograde opening in a film , comprising the steps of ; (a) forming a film having : (1) a top , (2) bottom , and (3) characteristic that varies in the same sense from the top of the film to the bottom of the film ; (b) applying a first etch (first etch) ant to anisotropically etch an opening in the film extending downward from the top of the film ; and (c) applying a second etch (second etch) ant : (1) to isotropically etch the opening in the film , and (2) having a composition based on the characteristic of the film to produce further etching of the film at a first etch rate at a lower portion of the opening that is greater than a second etch rate at a higher portion of the opening resulting in a tapered retrograde opening having a top width and a bottom width greater than the top width . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch (first etch) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (second etch) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6355567B1 CLAIM 1 . A process for forming a retrograde opening in a film , comprising the steps of ; (a) forming a film having : (1) a top , (2) bottom , and (3) characteristic that varies in the same sense from the top of the film to the bottom of the film ; (b) applying a first etch (first etch) ant to anisotropically etch an opening in the film extending downward from the top of the film ; and (c) applying a second etch (second etch) ant : (1) to isotropically etch the opening in the film , and (2) having a composition based on the characteristic of the film to produce further etching of the film at a first etch rate at a lower portion of the opening that is greater than a second etch rate at a higher portion of the opening resulting in a tapered retrograde opening having a top width and a bottom width greater than the top width . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US6074908A Filed: 1999-05-26 Issued: 2000-06-13 Process for making merged integrated circuits having salicide FETS and embedded DRAM circuits (Original Assignee) Taiwan Semiconductor Manufacturing Co TSMC Ltd (Current Assignee) Taiwan Semiconductor Manufacturing Co TSMC Ltd Jenn Ming Huang |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region (second contact) coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region (interlevel dielectric layer) such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (said stack) of said contact region ; and a multiple etch (wet etch, silicon oxide layer, ion implantation) stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch (wet etch, silicon oxide layer, ion implantation) stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (stacked capacitor) layer over said first etch stop layer ; a second etch (etch stop layer, gate oxide) stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US6074908A CLAIM 2 . The method of claim 1 , wherein said first gate oxide (second etch) is grown to a thickness of between about 20 and 100 Angstroms . US6074908A CLAIM 6 . The method of claim 1 , wherein said hard-mask layer consists of a silicon oxide layer (first etch, second etch stop layers, etch process, first etch stop layer, multiple etch, multiple etch stop insulation layer, second etch stop layer) deposited to a thickness of between about 200 and 400 Angstroms and an upper silicon nitride layer deposited to a thickness of between about 1500 and 2000 Angstroms . US6074908A CLAIM 9 . The method of claim 1 , wherein said metal silicide is formed by : depositing a titanium layer to a thickness of between about 200 and 400 Angstroms ; rapid thermal annealing at a temperature of about 500 to 700° C . for about 30 seconds to form titanium silicide ; removing said unreacted titanium metal by a wet etch (first etch, second etch stop layers, etch process, first etch stop layer, multiple etch, multiple etch stop insulation layer, second etch stop layer) ing in a solution of NH 4 OH and H 2 O 2 ; carrying out a second rapid thermal annealing at a temperature of about 700 to 900° C . for about 30 seconds to complete the phase formation of said titanium silicide . US6074908A CLAIM 20 . The method of claim 11 , wherein said blanket etch stop layer (second etch) is silicon oxynitride deposited to a thickness of between about 200 and 500 Angstroms , and is used as an etch-stop layer for etching said fourth contact openings to said second source/drain areas for said metal contacts . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch (wet etch, silicon oxide layer, ion implantation) stop layer protects removal of a substrate material by an etch process (wet etch, silicon oxide layer, ion implantation) . |
US6074908A CLAIM 6 . The method of claim 1 , wherein said hard-mask layer consists of a silicon oxide layer (first etch, second etch stop layers, etch process, first etch stop layer, multiple etch, multiple etch stop insulation layer, second etch stop layer) deposited to a thickness of between about 200 and 400 Angstroms and an upper silicon nitride layer deposited to a thickness of between about 1500 and 2000 Angstroms . US6074908A CLAIM 9 . The method of claim 1 , wherein said metal silicide is formed by : depositing a titanium layer to a thickness of between about 200 and 400 Angstroms ; rapid thermal annealing at a temperature of about 500 to 700° C . for about 30 seconds to form titanium silicide ; removing said unreacted titanium metal by a wet etch (first etch, second etch stop layers, etch process, first etch stop layer, multiple etch, multiple etch stop insulation layer, second etch stop layer) ing in a solution of NH 4 OH and H 2 O 2 ; carrying out a second rapid thermal annealing at a temperature of about 700 to 900° C . for about 30 seconds to complete the phase formation of said titanium silicide . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch (etch stop layer, gate oxide) stop layer protects lower layers during an etching process (doped polysilicon) . |
US6074908A CLAIM 2 . The method of claim 1 , wherein said first gate oxide (second etch) is grown to a thickness of between about 20 and 100 Angstroms . US6074908A CLAIM 6 . The method of claim 1 , wherein said hard-mask layer consists of a silicon oxide layer (first etch, second etch stop layers, etch process, first etch stop layer, multiple etch, multiple etch stop insulation layer, second etch stop layer) deposited to a thickness of between about 200 and 400 Angstroms and an upper silicon nitride layer deposited to a thickness of between about 1500 and 2000 Angstroms . US6074908A CLAIM 9 . The method of claim 1 , wherein said metal silicide is formed by : depositing a titanium layer to a thickness of between about 200 and 400 Angstroms ; rapid thermal annealing at a temperature of about 500 to 700° C . for about 30 seconds to form titanium silicide ; removing said unreacted titanium metal by a wet etch (first etch, second etch stop layers, etch process, first etch stop layer, multiple etch, multiple etch stop insulation layer, second etch stop layer) ing in a solution of NH 4 OH and H 2 O 2 ; carrying out a second rapid thermal annealing at a temperature of about 700 to 900° C . for about 30 seconds to complete the phase formation of said titanium silicide . US6074908A CLAIM 20 . The method of claim 11 , wherein said blanket etch stop layer (second etch) is silicon oxynitride deposited to a thickness of between about 200 and 500 Angstroms , and is used as an etch-stop layer for etching said fourth contact openings to said second source/drain areas for said metal contacts . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch (wet etch, silicon oxide layer, ion implantation) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (stacked capacitor) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (etch stop layer, gate oxide) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6074908A CLAIM 2 . The method of claim 1 , wherein said first gate oxide (second etch) is grown to a thickness of between about 20 and 100 Angstroms . US6074908A CLAIM 6 . The method of claim 1 , wherein said hard-mask layer consists of a silicon oxide layer (first etch, second etch stop layers, etch process, first etch stop layer, multiple etch, multiple etch stop insulation layer, second etch stop layer) deposited to a thickness of between about 200 and 400 Angstroms and an upper silicon nitride layer deposited to a thickness of between about 1500 and 2000 Angstroms . US6074908A CLAIM 9 . The method of claim 1 , wherein said metal silicide is formed by : depositing a titanium layer to a thickness of between about 200 and 400 Angstroms ; rapid thermal annealing at a temperature of about 500 to 700° C . for about 30 seconds to form titanium silicide ; removing said unreacted titanium metal by a wet etch (first etch, second etch stop layers, etch process, first etch stop layer, multiple etch, multiple etch stop insulation layer, second etch stop layer) ing in a solution of NH 4 OH and H 2 O 2 ; carrying out a second rapid thermal annealing at a temperature of about 700 to 900° C . for about 30 seconds to complete the phase formation of said titanium silicide . US6074908A CLAIM 20 . The method of claim 11 , wherein said blanket etch stop layer (second etch) is silicon oxynitride deposited to a thickness of between about 200 and 500 Angstroms , and is used as an etch-stop layer for etching said fourth contact openings to said second source/drain areas for said metal contacts . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch (wet etch, silicon oxide layer, ion implantation) stop insulation layer comprising a first etch (wet etch, silicon oxide layer, ion implantation) stop layer and a second etch (etch stop layer, gate oxide) stop layer wherein said first etch stop layer and said second etch stop layers (wet etch, silicon oxide layer, ion implantation) have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region (second contact) and under a first sub interlevel dielectric (stacked capacitor) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (said stack) of said contact region . |
US6074908A CLAIM 2 . The method of claim 1 , wherein said first gate oxide (second etch) is grown to a thickness of between about 20 and 100 Angstroms . US6074908A CLAIM 6 . The method of claim 1 , wherein said hard-mask layer consists of a silicon oxide layer (first etch, second etch stop layers, etch process, first etch stop layer, multiple etch, multiple etch stop insulation layer, second etch stop layer) deposited to a thickness of between about 200 and 400 Angstroms and an upper silicon nitride layer deposited to a thickness of between about 1500 and 2000 Angstroms . US6074908A CLAIM 9 . The method of claim 1 , wherein said metal silicide is formed by : depositing a titanium layer to a thickness of between about 200 and 400 Angstroms ; rapid thermal annealing at a temperature of about 500 to 700° C . for about 30 seconds to form titanium silicide ; removing said unreacted titanium metal by a wet etch (first etch, second etch stop layers, etch process, first etch stop layer, multiple etch, multiple etch stop insulation layer, second etch stop layer) ing in a solution of NH 4 OH and H 2 O 2 ; carrying out a second rapid thermal annealing at a temperature of about 700 to 900° C . for about 30 seconds to complete the phase formation of said titanium silicide . US6074908A CLAIM 20 . The method of claim 11 , wherein said blanket etch stop layer (second etch) is silicon oxynitride deposited to a thickness of between about 200 and 500 Angstroms , and is used as an etch-stop layer for etching said fourth contact openings to said second source/drain areas for said metal contacts . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch (wet etch, silicon oxide layer, ion implantation) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (stacked capacitor) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (etch stop layer, gate oxide) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6074908A CLAIM 2 . The method of claim 1 , wherein said first gate oxide (second etch) is grown to a thickness of between about 20 and 100 Angstroms . US6074908A CLAIM 6 . The method of claim 1 , wherein said hard-mask layer consists of a silicon oxide layer (first etch, second etch stop layers, etch process, first etch stop layer, multiple etch, multiple etch stop insulation layer, second etch stop layer) deposited to a thickness of between about 200 and 400 Angstroms and an upper silicon nitride layer deposited to a thickness of between about 1500 and 2000 Angstroms . US6074908A CLAIM 9 . The method of claim 1 , wherein said metal silicide is formed by : depositing a titanium layer to a thickness of between about 200 and 400 Angstroms ; rapid thermal annealing at a temperature of about 500 to 700° C . for about 30 seconds to form titanium silicide ; removing said unreacted titanium metal by a wet etch (first etch, second etch stop layers, etch process, first etch stop layer, multiple etch, multiple etch stop insulation layer, second etch stop layer) ing in a solution of NH 4 OH and H 2 O 2 ; carrying out a second rapid thermal annealing at a temperature of about 700 to 900° C . for about 30 seconds to complete the phase formation of said titanium silicide . US6074908A CLAIM 20 . The method of claim 11 , wherein said blanket etch stop layer (second etch) is silicon oxynitride deposited to a thickness of between about 200 and 500 Angstroms , and is used as an etch-stop layer for etching said fourth contact openings to said second source/drain areas for said metal contacts . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US6096595A Filed: 1999-05-12 Issued: 2000-08-01 Integration of a salicide process for MOS logic devices, and a self-aligned contact process for MOS memory devices (Original Assignee) Taiwan Semiconductor Manufacturing Co TSMC Ltd (Current Assignee) Taiwan Semiconductor Manufacturing Co TSMC Ltd Jenn Ming Huang |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch (said second polysilicon layer, said first polysilicon layer) stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (silicon nitride layer, capacitor structure, first interlevel, upper electrode, contact hole, n storage) layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US6096595A CLAIM 1 . A method of fabricating MOS memory devices , and MOS logic devices on a single semiconductor substrate , comprising the steps of : forming silicon nitride capped , polycide gate structures , on a first gate insulator layer , on a first region of said semiconductor substrate , to be used for said MOS memory devices ; forming first lightly doped source/drain regions , in an area of said first region of said semiconductor substrate , not covered by said silicon nitride capped , polycide gate structures ; forming first insulator spacers on the sides of said silicon nitride capped , polycide gate structures ; depositing a first interlevel (second etch stop layers, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) planarization , (IPO) , layer ; forming self-aligned contact , (SAC) , openings , in said first IPO layer , located in said first region of said semiconductor substrate , exposing said first lightly doped source/drain regions , located between said silicon nitride capped , polycide gate structures ; forming a first polysilicon plug structure , in a first SAC opening , and forming a second polysilicon plug structure , in a second SAC opening ; removing said first IPO layer , from said second region of said semiconductor substrate ; forming polysilicon gate structures , on a second gate insulator layer , on a second region of said semiconductor substrate , to be used for said MOS logic devices ; forming second lightly doped source/drain regions , in an area of said second region of said semiconductor substrate , not covered by said polysilicon gate structures ; forming second insulator spacers on the sides of said polysilicon gate structures ; forming heavily doped source/drain regions , in an area of said second region of said semiconductor substrate , not covered by said polysilicon gate structures , and not covered by said second insulator spacers ; performing a rapid thermal anneal procedure ; forming a protective insulator layer , in said first region of said semiconductor substrate , overlying the top surface of the polysilicon plug structures ; selectively forming a metal silicide layer on the top surface of said polysilicon gate structures , and on the top surface of said heavily doped source/drain regions ; depositing a second IPO layer ; forming a bit line opening , in said second IPO layer , and in said protective insulator layer , exposing a portion of the top surface of said first polysilicon plug structure , and forming a storage node opening in said second IPO layer , and in said protective insulator layer , exposing a portion of the top surface of said second polysilicon plug structure ; forming a bit line structure in said bit line opening , and forming a storage node contact structure , in said storage node opening ; depositing a third IPO layer ; forming a capacitor opening , in said third IPO layer , exposing the top surface of said storage node contact structure ; and forming a capacitor structure (second etch stop layers, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) in said capacitor opening . US6096595A CLAIM 5 . The method of claim 1 , wherein said first insulator spacers , on the sides of said silicon nitride capped , polycide gate structures , are formed from a silicon nitride layer (second etch stop layers, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) , obtained via LPCVD or PECVD procedures , at a thickness between about 500 to 1000 Angstroms , followed by an anisotropic RIE procedure , using CF 4 as an etchant . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch (said second polysilicon layer, said first polysilicon layer) stop layer protects removal of a substrate material by an etch process (silicon oxide layer, ion implantation) . |
US6096595A CLAIM 3 . The method of claim 1 , wherein the polycide component , of said silicon nitride capped , polycide gate structures , is : comprised of an underlying polysilicon layer , obtained via LPCVD procedures , to a thickness between about 500 to 1500 Angstroms , and either doped in situ , during deposition via the addition of arsine , or phosphine , to a silane ambient , or deposited intrinsically , then doped via ion implantation (etch process) of arsenic or phosphorous ions ; and comprised of an overlying tungsten silicide layer , obtained via LPCVD procedures , at a thickness between about 500 to 1500 Angstroms . US6096595A CLAIM 6 . The method of claim 1 , wherein said first IPO layer is either a silicon oxide layer (etch process) , or a borophosphosilicate glass , (BPSG) , layer , obtained via PECVD procedures , at a thickness between about 4000 to 8000 Angstroms . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (silicon nitride layer, capacitor structure, first interlevel, upper electrode, contact hole, n storage) layer insulates said contact region . |
US6096595A CLAIM 5 . The method of claim 1 , wherein said first insulator spacers , on the sides of said silicon nitride capped , polycide gate structures , are formed from a silicon nitride layer (second etch stop layers, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) , obtained via LPCVD or PECVD procedures , at a thickness between about 500 to 1000 Angstroms , followed by an anisotropic RIE procedure , using CF 4 as an etchant . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (silicon nitride layer, capacitor structure, first interlevel, upper electrode, contact hole, n storage) layer insulates said contact region . |
US6096595A CLAIM 5 . The method of claim 1 , wherein said first insulator spacers , on the sides of said silicon nitride capped , polycide gate structures , are formed from a silicon nitride layer (second etch stop layers, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) , obtained via LPCVD or PECVD procedures , at a thickness between about 500 to 1000 Angstroms , followed by an anisotropic RIE procedure , using CF 4 as an etchant . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch (said second polysilicon layer, said first polysilicon layer) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (silicon nitride layer, capacitor structure, first interlevel, upper electrode, contact hole, n storage) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6096595A CLAIM 5 . The method of claim 1 , wherein said first insulator spacers , on the sides of said silicon nitride capped , polycide gate structures , are formed from a silicon nitride layer (second etch stop layers, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) , obtained via LPCVD or PECVD procedures , at a thickness between about 500 to 1000 Angstroms , followed by an anisotropic RIE procedure , using CF 4 as an etchant . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric (silicon nitride layer, capacitor structure, first interlevel, upper electrode, contact hole, n storage) layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space (storage node) in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US6096595A CLAIM 5 . The method of claim 1 , wherein said first insulator spacers , on the sides of said silicon nitride capped , polycide gate structures , are formed from a silicon nitride layer (second etch stop layers, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) , obtained via LPCVD or PECVD procedures , at a thickness between about 500 to 1000 Angstroms , followed by an anisotropic RIE procedure , using CF 4 as an etchant . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch (said second polysilicon layer, said first polysilicon layer) stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers (silicon nitride layer, capacitor structure, first interlevel, upper electrode, contact hole, n storage) have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (silicon nitride layer, capacitor structure, first interlevel, upper electrode, contact hole, n storage) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US6096595A CLAIM 5 . The method of claim 1 , wherein said first insulator spacers , on the sides of said silicon nitride capped , polycide gate structures , are formed from a silicon nitride layer (second etch stop layers, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) , obtained via LPCVD or PECVD procedures , at a thickness between about 500 to 1000 Angstroms , followed by an anisotropic RIE procedure , using CF 4 as an etchant . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch (said second polysilicon layer, said first polysilicon layer) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (silicon nitride layer, capacitor structure, first interlevel, upper electrode, contact hole, n storage) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6096595A CLAIM 5 . The method of claim 1 , wherein said first insulator spacers , on the sides of said silicon nitride capped , polycide gate structures , are formed from a silicon nitride layer (second etch stop layers, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) , obtained via LPCVD or PECVD procedures , at a thickness between about 500 to 1000 Angstroms , followed by an anisotropic RIE procedure , using CF 4 as an etchant . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US6043529A Filed: 1999-03-30 Issued: 2000-03-28 Semiconductor configuration with a protected barrier for a stacked cell (Original Assignee) Siemens AG (Current Assignee) Siemens AG ; Qimonda AG Walter Hartner, Gunther Schindler, Carlos Mazure-Espejo |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (upper electrodes) of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (conductive oxides, contact hole) layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US6043529A CLAIM 1 . A semiconductor configuration for an integrated circuit , comprising : a capacitor including a lower and an upper electrode , and a dielectric selected from the group consisting of a superparaelectric , a paraelectric , and a ferroelectric material disposed between said lower and upper electrodes (metal layer coupling area) ; an insulating layer formed with a contact hole (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) therethrough ; a filler material disposed in said contact hole ; a silicon nitride layer disposed on a wall of said contact hole ; a barrier layer having a top surface , said barrier layer being disposed in said contact hole and disposed directly on said filler material , said barrier layer disposed between and electrically connecting said filler material and said lower electrode of said capacitor ; and a silicon nitride layer having a top surface , said silicon nitride layer being disposed on said insulating layer and laterally surrounding said barrier layer ; said top surface of said barrier layer and said top surface of said silicon nitride layer substantially forming a plane with said capacitor disposed thereon . US6043529A CLAIM 3 . The semiconductor configuration according to claim 2 , wherein at least one of said lower electrode and said upper electrode is a conductive material selected from the group consisting of platinum , ruthenium , iridium , palladium and conductive oxides (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) thereof . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (conductive oxides, contact hole) layer insulates said contact region . |
US6043529A CLAIM 1 . A semiconductor configuration for an integrated circuit , comprising : a capacitor including a lower and an upper electrode , and a dielectric selected from the group consisting of a superparaelectric , a paraelectric , and a ferroelectric material disposed between said lower and upper electrodes ; an insulating layer formed with a contact hole (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) therethrough ; a filler material disposed in said contact hole ; a silicon nitride layer disposed on a wall of said contact hole ; a barrier layer having a top surface , said barrier layer being disposed in said contact hole and disposed directly on said filler material , said barrier layer disposed between and electrically connecting said filler material and said lower electrode of said capacitor ; and a silicon nitride layer having a top surface , said silicon nitride layer being disposed on said insulating layer and laterally surrounding said barrier layer ; said top surface of said barrier layer and said top surface of said silicon nitride layer substantially forming a plane with said capacitor disposed thereon . US6043529A CLAIM 3 . The semiconductor configuration according to claim 2 , wherein at least one of said lower electrode and said upper electrode is a conductive material selected from the group consisting of platinum , ruthenium , iridium , palladium and conductive oxides (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) thereof . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (conductive oxides, contact hole) layer insulates said contact region . |
US6043529A CLAIM 1 . A semiconductor configuration for an integrated circuit , comprising : a capacitor including a lower and an upper electrode , and a dielectric selected from the group consisting of a superparaelectric , a paraelectric , and a ferroelectric material disposed between said lower and upper electrodes ; an insulating layer formed with a contact hole (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) therethrough ; a filler material disposed in said contact hole ; a silicon nitride layer disposed on a wall of said contact hole ; a barrier layer having a top surface , said barrier layer being disposed in said contact hole and disposed directly on said filler material , said barrier layer disposed between and electrically connecting said filler material and said lower electrode of said capacitor ; and a silicon nitride layer having a top surface , said silicon nitride layer being disposed on said insulating layer and laterally surrounding said barrier layer ; said top surface of said barrier layer and said top surface of said silicon nitride layer substantially forming a plane with said capacitor disposed thereon . US6043529A CLAIM 3 . The semiconductor configuration according to claim 2 , wherein at least one of said lower electrode and said upper electrode is a conductive material selected from the group consisting of platinum , ruthenium , iridium , palladium and conductive oxides (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) thereof . |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area of said contact region permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area (upper electrodes) of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
US6043529A CLAIM 1 . A semiconductor configuration for an integrated circuit , comprising : a capacitor including a lower and an upper electrode , and a dielectric selected from the group consisting of a superparaelectric , a paraelectric , and a ferroelectric material disposed between said lower and upper electrodes (metal layer coupling area) ; an insulating layer formed with a contact hole therethrough ; a filler material disposed in said contact hole ; a silicon nitride layer disposed on a wall of said contact hole ; a barrier layer having a top surface , said barrier layer being disposed in said contact hole and disposed directly on said filler material , said barrier layer disposed between and electrically connecting said filler material and said lower electrode of said capacitor ; and a silicon nitride layer having a top surface , said silicon nitride layer being disposed on said insulating layer and laterally surrounding said barrier layer ; said top surface of said barrier layer and said top surface of said silicon nitride layer substantially forming a plane with said capacitor disposed thereon . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (conductive oxides, contact hole) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6043529A CLAIM 1 . A semiconductor configuration for an integrated circuit , comprising : a capacitor including a lower and an upper electrode , and a dielectric selected from the group consisting of a superparaelectric , a paraelectric , and a ferroelectric material disposed between said lower and upper electrodes ; an insulating layer formed with a contact hole (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) therethrough ; a filler material disposed in said contact hole ; a silicon nitride layer disposed on a wall of said contact hole ; a barrier layer having a top surface , said barrier layer being disposed in said contact hole and disposed directly on said filler material , said barrier layer disposed between and electrically connecting said filler material and said lower electrode of said capacitor ; and a silicon nitride layer having a top surface , said silicon nitride layer being disposed on said insulating layer and laterally surrounding said barrier layer ; said top surface of said barrier layer and said top surface of said silicon nitride layer substantially forming a plane with said capacitor disposed thereon . US6043529A CLAIM 3 . The semiconductor configuration according to claim 2 , wherein at least one of said lower electrode and said upper electrode is a conductive material selected from the group consisting of platinum , ruthenium , iridium , palladium and conductive oxides (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) thereof . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric (conductive oxides, contact hole) layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US6043529A CLAIM 1 . A semiconductor configuration for an integrated circuit , comprising : a capacitor including a lower and an upper electrode , and a dielectric selected from the group consisting of a superparaelectric , a paraelectric , and a ferroelectric material disposed between said lower and upper electrodes ; an insulating layer formed with a contact hole (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) therethrough ; a filler material disposed in said contact hole ; a silicon nitride layer disposed on a wall of said contact hole ; a barrier layer having a top surface , said barrier layer being disposed in said contact hole and disposed directly on said filler material , said barrier layer disposed between and electrically connecting said filler material and said lower electrode of said capacitor ; and a silicon nitride layer having a top surface , said silicon nitride layer being disposed on said insulating layer and laterally surrounding said barrier layer ; said top surface of said barrier layer and said top surface of said silicon nitride layer substantially forming a plane with said capacitor disposed thereon . US6043529A CLAIM 3 . The semiconductor configuration according to claim 2 , wherein at least one of said lower electrode and said upper electrode is a conductive material selected from the group consisting of platinum , ruthenium , iridium , palladium and conductive oxides (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) thereof . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers (silicon nitride layer) have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (conductive oxides, contact hole) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom (lower electrode) , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (upper electrodes) of said contact region . |
US6043529A CLAIM 1 . A semiconductor configuration for an integrated circuit , comprising : a capacitor including a lower and an upper electrode , and a dielectric selected from the group consisting of a superparaelectric , a paraelectric , and a ferroelectric material disposed between said lower and upper electrodes (metal layer coupling area) ; an insulating layer formed with a contact hole (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) therethrough ; a filler material disposed in said contact hole ; a silicon nitride layer (second etch stop layers) disposed on a wall of said contact hole ; a barrier layer having a top surface , said barrier layer being disposed in said contact hole and disposed directly on said filler material , said barrier layer disposed between and electrically connecting said filler material and said lower electrode (contact bottom) of said capacitor ; and a silicon nitride layer having a top surface , said silicon nitride layer being disposed on said insulating layer and laterally surrounding said barrier layer ; said top surface of said barrier layer and said top surface of said silicon nitride layer substantially forming a plane with said capacitor disposed thereon . US6043529A CLAIM 3 . The semiconductor configuration according to claim 2 , wherein at least one of said lower electrode and said upper electrode is a conductive material selected from the group consisting of platinum , ruthenium , iridium , palladium and conductive oxides (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) thereof . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (conductive oxides, contact hole) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6043529A CLAIM 1 . A semiconductor configuration for an integrated circuit , comprising : a capacitor including a lower and an upper electrode , and a dielectric selected from the group consisting of a superparaelectric , a paraelectric , and a ferroelectric material disposed between said lower and upper electrodes ; an insulating layer formed with a contact hole (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) therethrough ; a filler material disposed in said contact hole ; a silicon nitride layer disposed on a wall of said contact hole ; a barrier layer having a top surface , said barrier layer being disposed in said contact hole and disposed directly on said filler material , said barrier layer disposed between and electrically connecting said filler material and said lower electrode of said capacitor ; and a silicon nitride layer having a top surface , said silicon nitride layer being disposed on said insulating layer and laterally surrounding said barrier layer ; said top surface of said barrier layer and said top surface of said silicon nitride layer substantially forming a plane with said capacitor disposed thereon . US6043529A CLAIM 3 . The semiconductor configuration according to claim 2 , wherein at least one of said lower electrode and said upper electrode is a conductive material selected from the group consisting of platinum , ruthenium , iridium , palladium and conductive oxides (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) thereof . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US6232225B1 Filed: 1999-03-24 Issued: 2001-05-15 Method of fabricating contact window of semiconductor device (Original Assignee) Samsung Electronics Co Ltd (Current Assignee) Samsung Electronics Co Ltd Chil-kun Pong, Joo-hyun Jin |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch (wet etch rate, dry etch) stop insulation layer (wet etch rate, dry etch) coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer (wet etch rate, dry etch) directly on said substrate in said contact region ; a first sub interlevel dielectric layer (entire surface) over said first etch stop layer ; a second etch (wet etch rate, dry etch) stop layer (wet etch rate, dry etch) over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US6232225B1 CLAIM 1 . A method of fabricating a contact window of a semiconductor device , comprising the steps of : forming a lower conductive member on a semiconductor substrate ; forming a first insulative film on the lower conductive member , the first insulative film being formed of an insulative material doped with impurities at a first level of concentration , the first insulative film having a wet etch rate (multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers, multiple etch, second etch) that is proportional to the level of concentration of impurities ; forming a second insulative film on the first insulative film , the second insulative film being formed of an insulative material doped with impurities at a second level of concentration that is lower than the first level of concentration of impurities , the second insulative film also having a wet etch rate that is proportional to the level of concentration of impurities , opening a contact window and exposing the lower conductive member by dry etch (multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers, multiple etch, second etch) ing the second and first insulative films ; and wet etching the second and first insulative films through which the contact window has been formed to increase an exposed area of the lower conductive member . US6232225B1 CLAIM 9 . A method of fabricating a contact window of a semiconductor device , comprising the steps of : forming a lower conductive member on a semiconductor substrate ; forming an interlayer insulative film on the resulting structure ; forming a conductive film pattern on the interlayer insulative film ; forming a first insulative film on the entire surface (first sub interlevel dielectric layer) of the resultant structure on which the conductive film pattern is formed , the first insulative film being formed of an insulative material doped with impurities at a first level of concentration ; forming a second insulative film on the first insulative film , the second insulative film being formed of an insulative material doped with impurities at a second level of concentration the second insulative film also having a wet etch rate that is proportional to the level of concentration of impurities that is lower than the first level of concentration ; opening a contact window and exposing the lower conductive member by dry etching the second and first insulative films ; and increasing an exposed area of the lower conductive member by wet etching the second and first insulative films through which the contact window has been formed . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer (wet etch rate, dry etch) protects removal of a substrate material by an etch process (wet etch rate, dry etch) . |
US6232225B1 CLAIM 1 . A method of fabricating a contact window of a semiconductor device , comprising the steps of : forming a lower conductive member on a semiconductor substrate ; forming a first insulative film on the lower conductive member , the first insulative film being formed of an insulative material doped with impurities at a first level of concentration , the first insulative film having a wet etch rate (multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers, multiple etch, second etch) that is proportional to the level of concentration of impurities ; forming a second insulative film on the first insulative film , the second insulative film being formed of an insulative material doped with impurities at a second level of concentration that is lower than the first level of concentration of impurities , the second insulative film also having a wet etch rate that is proportional to the level of concentration of impurities , opening a contact window and exposing the lower conductive member by dry etch (multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers, multiple etch, second etch) ing the second and first insulative films ; and wet etching the second and first insulative films through which the contact window has been formed to increase an exposed area of the lower conductive member . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric layer (entire surface) insulates said contact region . |
US6232225B1 CLAIM 9 . A method of fabricating a contact window of a semiconductor device , comprising the steps of : forming a lower conductive member on a semiconductor substrate ; forming an interlayer insulative film on the resulting structure ; forming a conductive film pattern on the interlayer insulative film ; forming a first insulative film on the entire surface (first sub interlevel dielectric layer) of the resultant structure on which the conductive film pattern is formed , the first insulative film being formed of an insulative material doped with impurities at a first level of concentration ; forming a second insulative film on the first insulative film , the second insulative film being formed of an insulative material doped with impurities at a second level of concentration the second insulative film also having a wet etch rate that is proportional to the level of concentration of impurities that is lower than the first level of concentration ; opening a contact window and exposing the lower conductive member by dry etching the second and first insulative films ; and increasing an exposed area of the lower conductive member by wet etching the second and first insulative films through which the contact window has been formed . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch (wet etch rate, dry etch) stop layer (wet etch rate, dry etch) protects lower layers during an etching process . |
US6232225B1 CLAIM 1 . A method of fabricating a contact window of a semiconductor device , comprising the steps of : forming a lower conductive member on a semiconductor substrate ; forming a first insulative film on the lower conductive member , the first insulative film being formed of an insulative material doped with impurities at a first level of concentration , the first insulative film having a wet etch rate (multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers, multiple etch, second etch) that is proportional to the level of concentration of impurities ; forming a second insulative film on the first insulative film , the second insulative film being formed of an insulative material doped with impurities at a second level of concentration that is lower than the first level of concentration of impurities , the second insulative film also having a wet etch rate that is proportional to the level of concentration of impurities , opening a contact window and exposing the lower conductive member by dry etch (multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers, multiple etch, second etch) ing the second and first insulative films ; and wet etching the second and first insulative films through which the contact window has been formed to increase an exposed area of the lower conductive member . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer (wet etch rate, dry etch) is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer (entire surface) is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (wet etch rate, dry etch) stop layer (wet etch rate, dry etch) is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6232225B1 CLAIM 1 . A method of fabricating a contact window of a semiconductor device , comprising the steps of : forming a lower conductive member on a semiconductor substrate ; forming a first insulative film on the lower conductive member , the first insulative film being formed of an insulative material doped with impurities at a first level of concentration , the first insulative film having a wet etch rate (multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers, multiple etch, second etch) that is proportional to the level of concentration of impurities ; forming a second insulative film on the first insulative film , the second insulative film being formed of an insulative material doped with impurities at a second level of concentration that is lower than the first level of concentration of impurities , the second insulative film also having a wet etch rate that is proportional to the level of concentration of impurities , opening a contact window and exposing the lower conductive member by dry etch (multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers, multiple etch, second etch) ing the second and first insulative films ; and wet etching the second and first insulative films through which the contact window has been formed to increase an exposed area of the lower conductive member . US6232225B1 CLAIM 9 . A method of fabricating a contact window of a semiconductor device , comprising the steps of : forming a lower conductive member on a semiconductor substrate ; forming an interlayer insulative film on the resulting structure ; forming a conductive film pattern on the interlayer insulative film ; forming a first insulative film on the entire surface (first sub interlevel dielectric layer) of the resultant structure on which the conductive film pattern is formed , the first insulative film being formed of an insulative material doped with impurities at a first level of concentration ; forming a second insulative film on the first insulative film , the second insulative film being formed of an insulative material doped with impurities at a second level of concentration the second insulative film also having a wet etch rate that is proportional to the level of concentration of impurities that is lower than the first level of concentration ; opening a contact window and exposing the lower conductive member by dry etching the second and first insulative films ; and increasing an exposed area of the lower conductive member by wet etching the second and first insulative films through which the contact window has been formed . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric layer (entire surface) for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US6232225B1 CLAIM 9 . A method of fabricating a contact window of a semiconductor device , comprising the steps of : forming a lower conductive member on a semiconductor substrate ; forming an interlayer insulative film on the resulting structure ; forming a conductive film pattern on the interlayer insulative film ; forming a first insulative film on the entire surface (first sub interlevel dielectric layer) of the resultant structure on which the conductive film pattern is formed , the first insulative film being formed of an insulative material doped with impurities at a first level of concentration ; forming a second insulative film on the first insulative film , the second insulative film being formed of an insulative material doped with impurities at a second level of concentration the second insulative film also having a wet etch rate that is proportional to the level of concentration of impurities that is lower than the first level of concentration ; opening a contact window and exposing the lower conductive member by dry etching the second and first insulative films ; and increasing an exposed area of the lower conductive member by wet etching the second and first insulative films through which the contact window has been formed . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch (wet etch rate, dry etch) stop insulation layer (wet etch rate, dry etch) comprising a first etch stop layer (wet etch rate, dry etch) and a second etch (wet etch rate, dry etch) stop layer (wet etch rate, dry etch) wherein said first etch stop layer and said second etch stop layers (wet etch rate, dry etch) have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer (entire surface) and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US6232225B1 CLAIM 1 . A method of fabricating a contact window of a semiconductor device , comprising the steps of : forming a lower conductive member on a semiconductor substrate ; forming a first insulative film on the lower conductive member , the first insulative film being formed of an insulative material doped with impurities at a first level of concentration , the first insulative film having a wet etch rate (multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers, multiple etch, second etch) that is proportional to the level of concentration of impurities ; forming a second insulative film on the first insulative film , the second insulative film being formed of an insulative material doped with impurities at a second level of concentration that is lower than the first level of concentration of impurities , the second insulative film also having a wet etch rate that is proportional to the level of concentration of impurities , opening a contact window and exposing the lower conductive member by dry etch (multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers, multiple etch, second etch) ing the second and first insulative films ; and wet etching the second and first insulative films through which the contact window has been formed to increase an exposed area of the lower conductive member . US6232225B1 CLAIM 9 . A method of fabricating a contact window of a semiconductor device , comprising the steps of : forming a lower conductive member on a semiconductor substrate ; forming an interlayer insulative film on the resulting structure ; forming a conductive film pattern on the interlayer insulative film ; forming a first insulative film on the entire surface (first sub interlevel dielectric layer) of the resultant structure on which the conductive film pattern is formed , the first insulative film being formed of an insulative material doped with impurities at a first level of concentration ; forming a second insulative film on the first insulative film , the second insulative film being formed of an insulative material doped with impurities at a second level of concentration the second insulative film also having a wet etch rate that is proportional to the level of concentration of impurities that is lower than the first level of concentration ; opening a contact window and exposing the lower conductive member by dry etching the second and first insulative films ; and increasing an exposed area of the lower conductive member by wet etching the second and first insulative films through which the contact window has been formed . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer (wet etch rate, dry etch) is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer (entire surface) is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (wet etch rate, dry etch) stop layer (wet etch rate, dry etch) is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6232225B1 CLAIM 1 . A method of fabricating a contact window of a semiconductor device , comprising the steps of : forming a lower conductive member on a semiconductor substrate ; forming a first insulative film on the lower conductive member , the first insulative film being formed of an insulative material doped with impurities at a first level of concentration , the first insulative film having a wet etch rate (multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers, multiple etch, second etch) that is proportional to the level of concentration of impurities ; forming a second insulative film on the first insulative film , the second insulative film being formed of an insulative material doped with impurities at a second level of concentration that is lower than the first level of concentration of impurities , the second insulative film also having a wet etch rate that is proportional to the level of concentration of impurities , opening a contact window and exposing the lower conductive member by dry etch (multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers, multiple etch, second etch) ing the second and first insulative films ; and wet etching the second and first insulative films through which the contact window has been formed to increase an exposed area of the lower conductive member . US6232225B1 CLAIM 9 . A method of fabricating a contact window of a semiconductor device , comprising the steps of : forming a lower conductive member on a semiconductor substrate ; forming an interlayer insulative film on the resulting structure ; forming a conductive film pattern on the interlayer insulative film ; forming a first insulative film on the entire surface (first sub interlevel dielectric layer) of the resultant structure on which the conductive film pattern is formed , the first insulative film being formed of an insulative material doped with impurities at a first level of concentration ; forming a second insulative film on the first insulative film , the second insulative film being formed of an insulative material doped with impurities at a second level of concentration the second insulative film also having a wet etch rate that is proportional to the level of concentration of impurities that is lower than the first level of concentration ; opening a contact window and exposing the lower conductive member by dry etching the second and first insulative films ; and increasing an exposed area of the lower conductive member by wet etching the second and first insulative films through which the contact window has been formed . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US6156648A Filed: 1999-03-10 Issued: 2000-12-05 Method for fabricating dual damascene (Original Assignee) United Microelectronics Corp (Current Assignee) United Microelectronics Corp Yimin Huang |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area (second conductive layer) of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US6156648A CLAIM 8 . The method of claim 1 , the step of filling the second conductive material into the trench and the via hole further comprising : forming a second conductive layer (substrate coupling area) over the substrate that fills the trench and the via hole ; and removing a portion of the second conductive layer and the adhesion layer to expose the dielectric layer . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer protects removal of a substrate material (active ion) by an etch process . |
US6156648A CLAIM 15 . The method of claim 10 , wherein the step of removing the cap layer exposed by the via hole includes reactive ion (substrate material) etching . |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area (second conductive layer) of said contact region permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
US6156648A CLAIM 8 . The method of claim 1 , the step of filling the second conductive material into the trench and the via hole further comprising : forming a second conductive layer (substrate coupling area) over the substrate that fills the trench and the via hole ; and removing a portion of the second conductive layer and the adhesion layer to expose the dielectric layer . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area (second conductive layer) of said contact region is smaller than a metal layer coupling area of said contact region . |
US6156648A CLAIM 8 . The method of claim 1 , the step of filling the second conductive material into the trench and the via hole further comprising : forming a second conductive layer (substrate coupling area) over the substrate that fills the trench and the via hole ; and removing a portion of the second conductive layer and the adhesion layer to expose the dielectric layer . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | JP2000183313A Filed: 1998-12-21 Issued: 2000-06-30 半導体集積回路装置およびその製造方法 (Original Assignee) Thin Film Research Center, Hitachi''s Central Research Laboratory, Hitachi, Ibaraki, Japan; 株式会社日立製作所 Shuji Ikeda, Masayuki Kojima, Akira Takamatsu, Yasuko Yoshida, 雅之 児島, 安子 吉田, 修二 池田, 朗 高松 |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area (前記層) of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer (絶縁材料, なる第２, の絶縁) coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation (絶縁材料, なる第２, の絶縁) between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (メモリ素子) layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
JP2000183313A CLAIM 6 【請求項６】 半導体基板の第１領域にメモリ素子 (interlevel dielectric) を構 成する第１ＭＩＳＦＥＴが形成され、第２領域にｎチャ ネル型の第２ＭＩＳＦＥＴが形成され、第３領域にｐチ ャネル型の第３ＭＩＳＦＥＴが形成された半導体集積回 路装置であって、前記第１〜第３ＭＩＳＦＥＴのそれぞ れのゲート電極は、ＳｉＧｅ層とその上部に形成された メタル層またはメタルシリサイド層とを含んで構成さ れ、前記それぞれのゲート電極の上部には、第１絶縁層 が形成されていることを特徴とする半導体集積回路装 置。 JP2000183313A CLAIM 10 【請求項１０】 請求項８記載の半導体集積回路装置に おいて、前記第１〜第３ＭＩＳＦＥＴの上層には、前記 第１絶縁層とはエッチング速度が異なる層間絶縁膜を介 して第１層配線が形成され、前記第１層配線は、前記層 (substrate coupling area) 間絶縁膜に形成されたコンタクトホールを通じて前記第 １〜第３ＭＩＳＦＥＴのそれぞれのソース、ドレインと 電気的に接続されていることを特徴とする半導体集積回 路装置。 JP2000183313A CLAIM 11 【請求項１１】 請求項１０記載の半導体集積回路装置 において、前記第１絶縁層および前記第２絶縁層は、窒 化シリコン系の絶縁材料 (electrical insulation, multiple etch stop insulation layer) からなり、前記層間絶縁膜は、 酸化シリコン系の絶縁材料からなることを特徴とする半 導体集積回路装置。 JP2000183313A CLAIM 23 【請求項２３】 請求項２２記載の半導体集積回路装置 の製造方法において、前記第１〜第３ＭＩＳＦＥＴのそ れぞれのゲート電極を形成した後、さらに、（ａ）前記 それぞれのゲート電極の側壁に、前記第１絶縁層と略同 一の材料からなる第２ (electrical insulation, multiple etch stop insulation layer) 絶縁層を形成する工程、（ｂ）前 記第１〜第３ＭＩＳＦＥＴの上層に、前記第１絶縁層お よび前記第２絶縁層とはエッチング速度が異なる層間絶 縁膜を形成する工程、（ｃ）前記層間絶縁膜をエッチン グすることにより、前記第１ＭＩＳＦＥＴのソース、ド レインの上部に、前記第１ＭＩＳＦＥＴのゲート電極に 対して自己整合的に第１コンタクトホールを形成する工 程、を含むことを特徴とする半導体集積回路装置の製造 方法。 |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (メモリ素子) layer insulates said contact region . |
JP2000183313A CLAIM 6 【請求項６】 半導体基板の第１領域にメモリ素子 (interlevel dielectric) を構 成する第１ＭＩＳＦＥＴが形成され、第２領域にｎチャ ネル型の第２ＭＩＳＦＥＴが形成され、第３領域にｐチ ャネル型の第３ＭＩＳＦＥＴが形成された半導体集積回 路装置であって、前記第１〜第３ＭＩＳＦＥＴのそれぞ れのゲート電極は、ＳｉＧｅ層とその上部に形成された メタル層またはメタルシリサイド層とを含んで構成さ れ、前記それぞれのゲート電極の上部には、第１絶縁層 が形成されていることを特徴とする半導体集積回路装 置。 |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (メモリ素子) layer insulates said contact region . |
JP2000183313A CLAIM 6 【請求項６】 半導体基板の第１領域にメモリ素子 (interlevel dielectric) を構 成する第１ＭＩＳＦＥＴが形成され、第２領域にｎチャ ネル型の第２ＭＩＳＦＥＴが形成され、第３領域にｐチ ャネル型の第３ＭＩＳＦＥＴが形成された半導体集積回 路装置であって、前記第１〜第３ＭＩＳＦＥＴのそれぞ れのゲート電極は、ＳｉＧｅ層とその上部に形成された メタル層またはメタルシリサイド層とを含んで構成さ れ、前記それぞれのゲート電極の上部には、第１絶縁層 が形成されていることを特徴とする半導体集積回路装 置。 |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area (前記層) of said contact region permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
JP2000183313A CLAIM 10 【請求項１０】 請求項８記載の半導体集積回路装置に おいて、前記第１〜第３ＭＩＳＦＥＴの上層には、前記 第１絶縁層とはエッチング速度が異なる層間絶縁膜を介 して第１層配線が形成され、前記第１層配線は、前記層 (substrate coupling area) 間絶縁膜に形成されたコンタクトホールを通じて前記第 １〜第３ＭＩＳＦＥＴのそれぞれのソース、ドレインと 電気的に接続されていることを特徴とする半導体集積回 路装置。 |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Å thick , said first sub interlevel dielectric (メモリ素子) layer is in a range of about 1 , 000 to 2 , 000 Å thick , said second etch stop layer is in a range of about 300 to 800 Å thick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Å thick . |
JP2000183313A CLAIM 6 【請求項６】 半導体基板の第１領域にメモリ素子 (interlevel dielectric) を構 成する第１ＭＩＳＦＥＴが形成され、第２領域にｎチャ ネル型の第２ＭＩＳＦＥＴが形成され、第３領域にｐチ ャネル型の第３ＭＩＳＦＥＴが形成された半導体集積回 路装置であって、前記第１〜第３ＭＩＳＦＥＴのそれぞ れのゲート電極は、ＳｉＧｅ層とその上部に形成された メタル層またはメタルシリサイド層とを含んで構成さ れ、前記それぞれのゲート電極の上部には、第１絶縁層 が形成されていることを特徴とする半導体集積回路装 置。 |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric (メモリ素子) layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range (あること) of about 0 . 16 μm to 0 . 18 μm wide . |
JP2000183313A CLAIM 6 【請求項６】 半導体基板の第１領域にメモリ素子 (interlevel dielectric) を構 成する第１ＭＩＳＦＥＴが形成され、第２領域にｎチャ ネル型の第２ＭＩＳＦＥＴが形成され、第３領域にｐチ ャネル型の第３ＭＩＳＦＥＴが形成された半導体集積回 路装置であって、前記第１〜第３ＭＩＳＦＥＴのそれぞ れのゲート電極は、ＳｉＧｅ層とその上部に形成された メタル層またはメタルシリサイド層とを含んで構成さ れ、前記それぞれのゲート電極の上部には、第１絶縁層 が形成されていることを特徴とする半導体集積回路装 置。 JP2000183313A CLAIM 7 【請求項７】 請求項６記載の半導体集積回路装置にお いて、前記第２ＭＩＳＦＥＴおよび前記第３ＭＩＳＦＥ Ｔは、ロジック回路を構成する素子であること (second range) を特徴と する半導体集積回路装置。 |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer (絶縁材料, なる第２, の絶縁) comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (メモリ素子) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area (前記層) of said contact region is smaller than a metal layer coupling area of said contact region . |
JP2000183313A CLAIM 6 【請求項６】 半導体基板の第１領域にメモリ素子 (interlevel dielectric) を構 成する第１ＭＩＳＦＥＴが形成され、第２領域にｎチャ ネル型の第２ＭＩＳＦＥＴが形成され、第３領域にｐチ ャネル型の第３ＭＩＳＦＥＴが形成された半導体集積回 路装置であって、前記第１〜第３ＭＩＳＦＥＴのそれぞ れのゲート電極は、ＳｉＧｅ層とその上部に形成された メタル層またはメタルシリサイド層とを含んで構成さ れ、前記それぞれのゲート電極の上部には、第１絶縁層 が形成されていることを特徴とする半導体集積回路装 置。 JP2000183313A CLAIM 10 【請求項１０】 請求項８記載の半導体集積回路装置に おいて、前記第１〜第３ＭＩＳＦＥＴの上層には、前記 第１絶縁層とはエッチング速度が異なる層間絶縁膜を介 して第１層配線が形成され、前記第１層配線は、前記層 (substrate coupling area) 間絶縁膜に形成されたコンタクトホールを通じて前記第 １〜第３ＭＩＳＦＥＴのそれぞれのソース、ドレインと 電気的に接続されていることを特徴とする半導体集積回 路装置。 JP2000183313A CLAIM 11 【請求項１１】 請求項１０記載の半導体集積回路装置 において、前記第１絶縁層および前記第２絶縁層は、窒 化シリコン系の絶縁材料 (electrical insulation, multiple etch stop insulation layer) からなり、前記層間絶縁膜は、 酸化シリコン系の絶縁材料からなることを特徴とする半 導体集積回路装置。 JP2000183313A CLAIM 23 【請求項２３】 請求項２２記載の半導体集積回路装置 の製造方法において、前記第１〜第３ＭＩＳＦＥＴのそ れぞれのゲート電極を形成した後、さらに、（ａ）前記 それぞれのゲート電極の側壁に、前記第１絶縁層と略同 一の材料からなる第２ (electrical insulation, multiple etch stop insulation layer) 絶縁層を形成する工程、（ｂ）前 記第１〜第３ＭＩＳＦＥＴの上層に、前記第１絶縁層お よび前記第２絶縁層とはエッチング速度が異なる層間絶 縁膜を形成する工程、（ｃ）前記層間絶縁膜をエッチン グすることにより、前記第１ＭＩＳＦＥＴのソース、ド レインの上部に、前記第１ＭＩＳＦＥＴのゲート電極に 対して自己整合的に第１コンタクトホールを形成する工 程、を含むことを特徴とする半導体集積回路装置の製造 方法。 |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Å thick , said first sub interlevel dielectric (メモリ素子) layer is in a range of about 1 , 000 to 2 , 000 Å thick , said second etch stop layer is in a range of about 300 to 800 Å thick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Å thick . |
JP2000183313A CLAIM 6 【請求項６】 半導体基板の第１領域にメモリ素子 (interlevel dielectric) を構 成する第１ＭＩＳＦＥＴが形成され、第２領域にｎチャ ネル型の第２ＭＩＳＦＥＴが形成され、第３領域にｐチ ャネル型の第３ＭＩＳＦＥＴが形成された半導体集積回 路装置であって、前記第１〜第３ＭＩＳＦＥＴのそれぞ れのゲート電極は、ＳｉＧｅ層とその上部に形成された メタル層またはメタルシリサイド層とを含んで構成さ れ、前記それぞれのゲート電極の上部には、第１絶縁層 が形成されていることを特徴とする半導体集積回路装 置。 |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region is a first range of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range (あること) of about 0 . 16 μm to 0 . 18 μm wide . |
JP2000183313A CLAIM 7 【請求項７】 請求項６記載の半導体集積回路装置にお いて、前記第２ＭＩＳＦＥＴおよび前記第３ＭＩＳＦＥ Ｔは、ロジック回路を構成する素子であること (second range) を特徴と する半導体集積回路装置。 |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | JP2000150516A Filed: 1998-10-27 Issued: 2000-05-30 半導体装置の製造方法 (Original Assignee) Tokyo Electron Ltd; 東京エレクトロン株式会社 Takashi Akahori, Masaaki Hagiwara, Koichiro Inasawa, Koji Senoo, 幸治 妹尾, 剛一郎 稲沢, 正明 萩原, 孝 赤堀 |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (製造方法) of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer (少なくとも) over said second etch stop layer . |
JP2000150516A CLAIM 1 【請求項１】 被処理体上に絶縁膜を形成する工程と、 前記絶縁膜にビアホ−ルをエッチングする工程と、 ビアホ−ルが形成された絶縁膜の表面に、埋め込み特性 の悪い成膜材料を用いて上部絶縁膜を形成する工程と、 前記上部絶縁膜に、金属を埋め込むことにより配線を形 成するための溝を前記ビアホ−ルの少なくとも (second sub interlevel dielectric layer) 一部に接 触するようにエッチングする工程と、を含むことを特徴 とする半導体装置の製造方法 (metal layer coupling area) 。 |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric layer (少なくとも) insulates said contact region . |
JP2000150516A CLAIM 1 【請求項１】 被処理体上に絶縁膜を形成する工程と、 前記絶縁膜にビアホ−ルをエッチングする工程と、 ビアホ−ルが形成された絶縁膜の表面に、埋め込み特性 の悪い成膜材料を用いて上部絶縁膜を形成する工程と、 前記上部絶縁膜に、金属を埋め込むことにより配線を形 成するための溝を前記ビアホ−ルの少なくとも (second sub interlevel dielectric layer) 一部に接 触するようにエッチングする工程と、を含むことを特徴 とする半導体装置の製造方法。 |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area of said contact region permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area (製造方法) of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
JP2000150516A CLAIM 1 【請求項１】 被処理体上に絶縁膜を形成する工程と、 前記絶縁膜にビアホ−ルをエッチングする工程と、 ビアホ−ルが形成された絶縁膜の表面に、埋め込み特性 の悪い成膜材料を用いて上部絶縁膜を形成する工程と、 前記上部絶縁膜に、金属を埋め込むことにより配線を形 成するための溝を前記ビアホ−ルの少なくとも一部に接 触するようにエッチングする工程と、を含むことを特徴 とする半導体装置の製造方法 (metal layer coupling area) 。 |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Å thick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Å thick , said second etch stop layer is in a range of about 300 to 800 Å thick and said second sub interlevel dielectric layer (少なくとも) is in a range of about 10K ű1K Å thick . |
JP2000150516A CLAIM 1 【請求項１】 被処理体上に絶縁膜を形成する工程と、 前記絶縁膜にビアホ−ルをエッチングする工程と、 ビアホ−ルが形成された絶縁膜の表面に、埋め込み特性 の悪い成膜材料を用いて上部絶縁膜を形成する工程と、 前記上部絶縁膜に、金属を埋め込むことにより配線を形 成するための溝を前記ビアホ−ルの少なくとも (second sub interlevel dielectric layer) 一部に接 触するようにエッチングする工程と、を含むことを特徴 とする半導体装置の製造方法。 |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer (少なくとも) for said contact region is in a second range (あること) of about 0 . 16 μm to 0 . 18 μm wide . |
JP2000150516A CLAIM 1 【請求項１】 被処理体上に絶縁膜を形成する工程と、 前記絶縁膜にビアホ−ルをエッチングする工程と、 ビアホ−ルが形成された絶縁膜の表面に、埋め込み特性 の悪い成膜材料を用いて上部絶縁膜を形成する工程と、 前記上部絶縁膜に、金属を埋め込むことにより配線を形 成するための溝を前記ビアホ−ルの少なくとも (second sub interlevel dielectric layer) 一部に接 触するようにエッチングする工程と、を含むことを特徴 とする半導体装置の製造方法。 JP2000150516A CLAIM 4 【請求項４】 前記炭素とフッ素との化合物であって埋 め込み特性の悪い成膜材料はヘキサフルオロベンゼンで あること (second range) を特徴とする請求項２又は３記載の半導体装置 の製造方法 |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer (少なくとも) and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (製造方法) of said contact region . |
JP2000150516A CLAIM 1 【請求項１】 被処理体上に絶縁膜を形成する工程と、 前記絶縁膜にビアホ−ルをエッチングする工程と、 ビアホ−ルが形成された絶縁膜の表面に、埋め込み特性 の悪い成膜材料を用いて上部絶縁膜を形成する工程と、 前記上部絶縁膜に、金属を埋め込むことにより配線を形 成するための溝を前記ビアホ−ルの少なくとも (second sub interlevel dielectric layer) 一部に接 触するようにエッチングする工程と、を含むことを特徴 とする半導体装置の製造方法 (metal layer coupling area) 。 |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Å thick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Å thick , said second etch stop layer is in a range of about 300 to 800 Å thick and said second sub interlevel dielectric layer (少なくとも) is in a range of about 10K ű1K Å thick . |
JP2000150516A CLAIM 1 【請求項１】 被処理体上に絶縁膜を形成する工程と、 前記絶縁膜にビアホ−ルをエッチングする工程と、 ビアホ−ルが形成された絶縁膜の表面に、埋め込み特性 の悪い成膜材料を用いて上部絶縁膜を形成する工程と、 前記上部絶縁膜に、金属を埋め込むことにより配線を形 成するための溝を前記ビアホ−ルの少なくとも (second sub interlevel dielectric layer) 一部に接 触するようにエッチングする工程と、を含むことを特徴 とする半導体装置の製造方法。 |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region is a first range of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range (あること) of about 0 . 16 μm to 0 . 18 μm wide . |
JP2000150516A CLAIM 4 【請求項４】 前記炭素とフッ素との化合物であって埋 め込み特性の悪い成膜材料はヘキサフルオロベンゼンで あること (second range) を特徴とする請求項２又は３記載の半導体装置 の製造方法 |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US6255215B1 Filed: 1998-10-20 Issued: 2001-07-03 Semiconductor device having silicide layers formed using a collimated metal layer (Original Assignee) Advanced Micro Devices Inc (Current Assignee) GlobalFoundries Inc Fred Hause, Charles E. May, William S. Brennan |
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| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US6255215B1 CLAIM 14 . A process of fabricating a silicide layer for a semiconductor device , comprising : forming one or more silicon active regions on a substrate ; arranging a filter over and spaced above the device ; sputter depositing metal particles through the filter and forming (anti reflective coating) a metal layer on the one or more silicon active regions ; and reacting the metal layer with the silicon active regions to form metal silicide layers on the silicon active regions . |
| US7977797B2 CLAIM 13 . An integrated circuit of claim 11 further comprising a floating gate (drain region) . |
US6255215B1 CLAIM 10 . The process of claim 1 , wherein the silicon active region is a source/drain region (floating gate) . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US6255215B1 CLAIM 14 . A process of fabricating a silicide layer for a semiconductor device , comprising : forming one or more silicon active regions on a substrate ; arranging a filter over and spaced above the device ; sputter depositing metal particles through the filter and forming (anti reflective coating) a metal layer on the one or more silicon active regions ; and reacting the metal layer with the silicon active regions to form metal silicide layers on the silicon active regions . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US6163059A Filed: 1998-09-04 Issued: 2000-12-19 Integrated circuit including source implant self-aligned to contact via (Original Assignee) Advanced Micro Devices Inc (Current Assignee) Advanced Micro Devices Inc Frederick N. Hause, Mark I. Gardner |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer (drain side) directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch (gate oxide) stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US6163059A CLAIM 1 . An integrated circuit chip including an integrated circuit formed using the method of fabricating an integrated circuit comprising : forming a plurality of lightly-doped drain (LDD) MOSFET structures including a gate on a substrate over a gate oxide (second etch) layer , spacers abutting sides of the gate from a silicon dioxide material that is susceptible to oxide etching , and LDD doping of the substrate in a source region and a drain region self-aligned with the gate , the LDD MOSFET structures including LDD P-MOSFET structures and LDD N-MOSFET structures , the LDD N-MOSFETs having a heavily-doped drain doping in the drain region self-aligned with the gate and spacers , the LDD P-MOSFETs being undoped in a drain region ; forming an oxide layer over the substrate and the LDD P-MOSFET structures and the LDD N-MOSFET structures ; for the LDD P-MOSFET structures and the LDD N-MOSFET structures , cutting a contact via through the oxide layer to the substrate surface in the vicinity of the gate and spacer and abutting the source region of the substrate , the contact via being cut through the spacer on a source side of the gate overlying the source region , removing at least a portion of the source-side spacer so that the heavily-doped source implant is adjacent to the gate ; and implanting a source implant through the contact via into the source of the LDD P-MOSFET structure . US6163059A CLAIM 15 . An integrated circuit according to claim 14 , wherein : the first side is a drain side (first etch stop layer) and the first high concentration impurity region is a drain region ; and the second side is a source side and the second high concentration impurity diffusion region is a source region . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer (drain side) protects removal of a substrate material by an etch process (silicon dioxide material) . |
US6163059A CLAIM 1 . An integrated circuit chip including an integrated circuit formed using the method of fabricating an integrated circuit comprising : forming a plurality of lightly-doped drain (LDD) MOSFET structures including a gate on a substrate over a gate oxide layer , spacers abutting sides of the gate from a silicon dioxide material (etch process) that is susceptible to oxide etching , and LDD doping of the substrate in a source region and a drain region self-aligned with the gate , the LDD MOSFET structures including LDD P-MOSFET structures and LDD N-MOSFET structures , the LDD N-MOSFETs having a heavily-doped drain doping in the drain region self-aligned with the gate and spacers , the LDD P-MOSFETs being undoped in a drain region ; forming an oxide layer over the substrate and the LDD P-MOSFET structures and the LDD N-MOSFET structures ; for the LDD P-MOSFET structures and the LDD N-MOSFET structures , cutting a contact via through the oxide layer to the substrate surface in the vicinity of the gate and spacer and abutting the source region of the substrate , the contact via being cut through the spacer on a source side of the gate overlying the source region , removing at least a portion of the source-side spacer so that the heavily-doped source implant is adjacent to the gate ; and implanting a source implant through the contact via into the source of the LDD P-MOSFET structure . US6163059A CLAIM 15 . An integrated circuit according to claim 14 , wherein : the first side is a drain side (first etch stop layer) and the first high concentration impurity region is a drain region ; and the second side is a source side and the second high concentration impurity diffusion region is a source region . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch (gate oxide) stop layer protects lower layers during an etching process . |
US6163059A CLAIM 1 . An integrated circuit chip including an integrated circuit formed using the method of fabricating an integrated circuit comprising : forming a plurality of lightly-doped drain (LDD) MOSFET structures including a gate on a substrate over a gate oxide (second etch) layer , spacers abutting sides of the gate from a silicon dioxide material that is susceptible to oxide etching , and LDD doping of the substrate in a source region and a drain region self-aligned with the gate , the LDD MOSFET structures including LDD P-MOSFET structures and LDD N-MOSFET structures , the LDD N-MOSFETs having a heavily-doped drain doping in the drain region self-aligned with the gate and spacers , the LDD P-MOSFETs being undoped in a drain region ; forming an oxide layer over the substrate and the LDD P-MOSFET structures and the LDD N-MOSFET structures ; for the LDD P-MOSFET structures and the LDD N-MOSFET structures , cutting a contact via through the oxide layer to the substrate surface in the vicinity of the gate and spacer and abutting the source region of the substrate , the contact via being cut through the spacer on a source side of the gate overlying the source region , removing at least a portion of the source-side spacer so that the heavily-doped source implant is adjacent to the gate ; and implanting a source implant through the contact via into the source of the LDD P-MOSFET structure . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer (drain side) is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (gate oxide) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6163059A CLAIM 1 . An integrated circuit chip including an integrated circuit formed using the method of fabricating an integrated circuit comprising : forming a plurality of lightly-doped drain (LDD) MOSFET structures including a gate on a substrate over a gate oxide (second etch) layer , spacers abutting sides of the gate from a silicon dioxide material that is susceptible to oxide etching , and LDD doping of the substrate in a source region and a drain region self-aligned with the gate , the LDD MOSFET structures including LDD P-MOSFET structures and LDD N-MOSFET structures , the LDD N-MOSFETs having a heavily-doped drain doping in the drain region self-aligned with the gate and spacers , the LDD P-MOSFETs being undoped in a drain region ; forming an oxide layer over the substrate and the LDD P-MOSFET structures and the LDD N-MOSFET structures ; for the LDD P-MOSFET structures and the LDD N-MOSFET structures , cutting a contact via through the oxide layer to the substrate surface in the vicinity of the gate and spacer and abutting the source region of the substrate , the contact via being cut through the spacer on a source side of the gate overlying the source region , removing at least a portion of the source-side spacer so that the heavily-doped source implant is adjacent to the gate ; and implanting a source implant through the contact via into the source of the LDD P-MOSFET structure . US6163059A CLAIM 15 . An integrated circuit according to claim 14 , wherein : the first side is a drain side (first etch stop layer) and the first high concentration impurity region is a drain region ; and the second side is a source side and the second high concentration impurity diffusion region is a source region . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US6163059A CLAIM 17 . An integrated circuit chip including an integrated circuit formed using the method of fabricating an integrated circuit comprising : forming a plurality of lightly-doped drain (LDD) MOSFET structures , the individual MOSFET structures including a gate on a substrate over a gate oxide layer , spacers on sides of the gate , and LDD doping of the substrate in a source region and a drain region self-aligned with the gate , the LDD MOSFET structures including LDD P-MOSFET structures and LDD N-MOSFET structures , the LDD N-MOSFETs having a heavily-doped source and drain doping in the respective source region and drain region self-aligned with the LDD N-MOSFET gate and spacers , the LDD P-MOSFETs being heavily-doped in a drain region with absence of heavy doping in a source region self-aligned with the LDD P-MOSFET gate and spacers ; forming an oxide layer over the substrate and the LDD P-MOSFET structures and the LDD N-MOSFET structures ; for the LDD P-MOSFET structures and the LDD N-MOSFET structures , cutting a contact via through the oxide layer to the substrate surface in the vicinity of the gate and spacer and abutting the source region of the substrate ; implanting a source implant through the contact via into the source of the LDD P-MOSFET structure ; cutting a drain contact via through the oxide layer to the substrate surface in the vicinity of the gate and spacer but removed from the gate and spacer and abutting the drain region of the substrate ; and forming (anti reflective coating) a drain contact in the drain contact via . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer (drain side) and a second etch (gate oxide) stop layer wherein said first etch stop layer and said second etch stop layers (second sidewall spacer, first sidewall spacer) have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US6163059A CLAIM 1 . An integrated circuit chip including an integrated circuit formed using the method of fabricating an integrated circuit comprising : forming a plurality of lightly-doped drain (LDD) MOSFET structures including a gate on a substrate over a gate oxide (second etch) layer , spacers abutting sides of the gate from a silicon dioxide material that is susceptible to oxide etching , and LDD doping of the substrate in a source region and a drain region self-aligned with the gate , the LDD MOSFET structures including LDD P-MOSFET structures and LDD N-MOSFET structures , the LDD N-MOSFETs having a heavily-doped drain doping in the drain region self-aligned with the gate and spacers , the LDD P-MOSFETs being undoped in a drain region ; forming an oxide layer over the substrate and the LDD P-MOSFET structures and the LDD N-MOSFET structures ; for the LDD P-MOSFET structures and the LDD N-MOSFET structures , cutting a contact via through the oxide layer to the substrate surface in the vicinity of the gate and spacer and abutting the source region of the substrate , the contact via being cut through the spacer on a source side of the gate overlying the source region , removing at least a portion of the source-side spacer so that the heavily-doped source implant is adjacent to the gate ; and implanting a source implant through the contact via into the source of the LDD P-MOSFET structure . US6163059A CLAIM 12 . An integrated circuit comprising : a substrate ; a lightly-doped drain (LDD) MOSFET structure including a gate electrode on the substrate over a gate oxide layer , and a first sidewall spacer (second etch stop layers, floating gate) and a second sidewall spacer (second etch stop layers, floating gate) lateral to and abutting the gate electrode on a first side and a second side of the gate electrode , respectively , the first and second sidewall spacers being constructed of a silicon dioxide material that is susceptible to oxide etching , the substrate having light doping with low concentration impurity regions self-aligned with the gate electrode ; an oxide layer overlying the substrate and the LDD MOSFET structure , the oxide layer being etched to the substrate surface to form a contact via lateral to the gate electrode that is cut through at least a portion of the second sidewall spacer on the second side of the gate electrode ; and a high concentration impurity diffusion region that is self-aligned with the contact via by implanting a dopant through the contact via into a portion of the low concentration impurity region exposed by the contact via . US6163059A CLAIM 15 . An integrated circuit according to claim 14 , wherein : the first side is a drain side (first etch stop layer) and the first high concentration impurity region is a drain region ; and the second side is a source side and the second high concentration impurity diffusion region is a source region . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer (drain side) is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (gate oxide) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6163059A CLAIM 1 . An integrated circuit chip including an integrated circuit formed using the method of fabricating an integrated circuit comprising : forming a plurality of lightly-doped drain (LDD) MOSFET structures including a gate on a substrate over a gate oxide (second etch) layer , spacers abutting sides of the gate from a silicon dioxide material that is susceptible to oxide etching , and LDD doping of the substrate in a source region and a drain region self-aligned with the gate , the LDD MOSFET structures including LDD P-MOSFET structures and LDD N-MOSFET structures , the LDD N-MOSFETs having a heavily-doped drain doping in the drain region self-aligned with the gate and spacers , the LDD P-MOSFETs being undoped in a drain region ; forming an oxide layer over the substrate and the LDD P-MOSFET structures and the LDD N-MOSFET structures ; for the LDD P-MOSFET structures and the LDD N-MOSFET structures , cutting a contact via through the oxide layer to the substrate surface in the vicinity of the gate and spacer and abutting the source region of the substrate , the contact via being cut through the spacer on a source side of the gate overlying the source region , removing at least a portion of the source-side spacer so that the heavily-doped source implant is adjacent to the gate ; and implanting a source implant through the contact via into the source of the LDD P-MOSFET structure . US6163059A CLAIM 15 . An integrated circuit according to claim 14 , wherein : the first side is a drain side (first etch stop layer) and the first high concentration impurity region is a drain region ; and the second side is a source side and the second high concentration impurity diffusion region is a source region . |
| US7977797B2 CLAIM 13 . An integrated circuit of claim 11 further comprising a floating gate (second sidewall spacer, first sidewall spacer) . |
US6163059A CLAIM 12 . An integrated circuit comprising : a substrate ; a lightly-doped drain (LDD) MOSFET structure including a gate electrode on the substrate over a gate oxide layer , and a first sidewall spacer (second etch stop layers, floating gate) and a second sidewall spacer (second etch stop layers, floating gate) lateral to and abutting the gate electrode on a first side and a second side of the gate electrode , respectively , the first and second sidewall spacers being constructed of a silicon dioxide material that is susceptible to oxide etching , the substrate having light doping with low concentration impurity regions self-aligned with the gate electrode ; an oxide layer overlying the substrate and the LDD MOSFET structure , the oxide layer being etched to the substrate surface to form a contact via lateral to the gate electrode that is cut through at least a portion of the second sidewall spacer on the second side of the gate electrode ; and a high concentration impurity diffusion region that is self-aligned with the contact via by implanting a dopant through the contact via into a portion of the low concentration impurity region exposed by the contact via . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US6163059A CLAIM 17 . An integrated circuit chip including an integrated circuit formed using the method of fabricating an integrated circuit comprising : forming a plurality of lightly-doped drain (LDD) MOSFET structures , the individual MOSFET structures including a gate on a substrate over a gate oxide layer , spacers on sides of the gate , and LDD doping of the substrate in a source region and a drain region self-aligned with the gate , the LDD MOSFET structures including LDD P-MOSFET structures and LDD N-MOSFET structures , the LDD N-MOSFETs having a heavily-doped source and drain doping in the respective source region and drain region self-aligned with the LDD N-MOSFET gate and spacers , the LDD P-MOSFETs being heavily-doped in a drain region with absence of heavy doping in a source region self-aligned with the LDD P-MOSFET gate and spacers ; forming an oxide layer over the substrate and the LDD P-MOSFET structures and the LDD N-MOSFET structures ; for the LDD P-MOSFET structures and the LDD N-MOSFET structures , cutting a contact via through the oxide layer to the substrate surface in the vicinity of the gate and spacer and abutting the source region of the substrate ; implanting a source implant through the contact via into the source of the LDD P-MOSFET structure ; cutting a drain contact via through the oxide layer to the substrate surface in the vicinity of the gate and spacer but removed from the gate and spacer and abutting the drain region of the substrate ; and forming (anti reflective coating) a drain contact in the drain contact via . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US6127276A Filed: 1998-08-24 Issued: 2000-10-03 Method of formation for a via opening (Original Assignee) United Microelectronics Corp (Current Assignee) United Microelectronics Corp Shih-Yao Lin, Chih-Hsiang Chi |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch (wet etch, dry etch) stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch (wet etch, dry etch) stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch (wet etch, dry etch) stop layer (wet etch, dry etch) over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US6127276A CLAIM 1 . A method of forming an opening , the method comprising : forming an oxide layer over a metal layer ; patterning the oxide layer to form a first stage opening by a photolithography process and a wet etch (multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers, second etch) ing process ; forming a second stage opening on the first stage opening by an anisotropic dry etch (multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers, second etch) ing process , wherein the second stage opening does not expose the metal layer yet ; and performing an additional wet etching process on the second stage opening to just expose the metal layer , wherein an etchant used in the additional wet etching process comprises a property of high relative etching selectivity on the oxide layer to the metal layer . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch (wet etch, dry etch) stop layer protects removal of a substrate material by an etch process (wet etch, dry etch) . |
US6127276A CLAIM 1 . A method of forming an opening , the method comprising : forming an oxide layer over a metal layer ; patterning the oxide layer to form a first stage opening by a photolithography process and a wet etch (multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers, second etch) ing process ; forming a second stage opening on the first stage opening by an anisotropic dry etch (multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers, second etch) ing process , wherein the second stage opening does not expose the metal layer yet ; and performing an additional wet etching process on the second stage opening to just expose the metal layer , wherein an etchant used in the additional wet etching process comprises a property of high relative etching selectivity on the oxide layer to the metal layer . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch (wet etch, dry etch) stop layer (wet etch, dry etch) protects lower layers during an etching process . |
US6127276A CLAIM 1 . A method of forming an opening , the method comprising : forming an oxide layer over a metal layer ; patterning the oxide layer to form a first stage opening by a photolithography process and a wet etch (multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers, second etch) ing process ; forming a second stage opening on the first stage opening by an anisotropic dry etch (multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers, second etch) ing process , wherein the second stage opening does not expose the metal layer yet ; and performing an additional wet etching process on the second stage opening to just expose the metal layer , wherein an etchant used in the additional wet etching process comprises a property of high relative etching selectivity on the oxide layer to the metal layer . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch (wet etch, dry etch) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (wet etch, dry etch) stop layer (wet etch, dry etch) is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6127276A CLAIM 1 . A method of forming an opening , the method comprising : forming an oxide layer over a metal layer ; patterning the oxide layer to form a first stage opening by a photolithography process and a wet etch (multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers, second etch) ing process ; forming a second stage opening on the first stage opening by an anisotropic dry etch (multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers, second etch) ing process , wherein the second stage opening does not expose the metal layer yet ; and performing an additional wet etching process on the second stage opening to just expose the metal layer , wherein an etchant used in the additional wet etching process comprises a property of high relative etching selectivity on the oxide layer to the metal layer . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch (wet etch, dry etch) stop insulation layer comprising a first etch (wet etch, dry etch) stop layer and a second etch (wet etch, dry etch) stop layer (wet etch, dry etch) wherein said first etch stop layer and said second etch stop layers (wet etch, dry etch) have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process (lithography process) ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US6127276A CLAIM 1 . A method of forming an opening , the method comprising : forming an oxide layer over a metal layer ; patterning the oxide layer to form a first stage opening by a photolithography process (lithography process) and a wet etch (multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers, second etch) ing process ; forming a second stage opening on the first stage opening by an anisotropic dry etch (multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers, second etch) ing process , wherein the second stage opening does not expose the metal layer yet ; and performing an additional wet etching process on the second stage opening to just expose the metal layer , wherein an etchant used in the additional wet etching process comprises a property of high relative etching selectivity on the oxide layer to the metal layer . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch (wet etch, dry etch) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (wet etch, dry etch) stop layer (wet etch, dry etch) is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6127276A CLAIM 1 . A method of forming an opening , the method comprising : forming an oxide layer over a metal layer ; patterning the oxide layer to form a first stage opening by a photolithography process and a wet etch (multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers, second etch) ing process ; forming a second stage opening on the first stage opening by an anisotropic dry etch (multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers, second etch) ing process , wherein the second stage opening does not expose the metal layer yet ; and performing an additional wet etching process on the second stage opening to just expose the metal layer , wherein an etchant used in the additional wet etching process comprises a property of high relative etching selectivity on the oxide layer to the metal layer . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US6121083A Filed: 1998-08-14 Issued: 2000-09-19 Semiconductor device and method of fabricating the same (Original Assignee) NEC Corp (Current Assignee) Renesas Electronics Corp Takeo Matsuki |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (interlayer insulating film, upper electrode, contact hole, first film, second film) layer over said first etch stop layer ; a second etch stop layer (interlayer insulating film, upper electrode, contact hole, first film, second film) over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US6121083A CLAIM 1 . A method of fabricating a semiconductor device , comprising the steps of : (a) forming a multi-layered interlayer insulating film (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer, second sub interlevel dielectric layer, second etch stop layer) on a semiconductor substrate , said multi-layered interlayer insulating film including a first film (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer, second sub interlevel dielectric layer, second etch stop layer) , as an uppermost film , composed of a first material through which hydrogen is not allowed to pass ; (b) forming a plurality of contact hole (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer, second sub interlevel dielectric layer, second etch stop layer) s in a row through said multi-layered interlayer insulating film to said semiconductor substrate ; (c) forming a second film (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer, second sub interlevel dielectric layer, second etch stop layer) on an inner wall of said contact holes , said second film being composed of a second material through which hydrogen is not allowed to pass ; (d) forming a plug layer in said contact holes , said plug layer being composed of an electrically conductive material ; (e) forming a lower electrode on said semiconductor substrate over said plug layer in such a manner that said lower electrode is more extensive than a cross-section of said contact holes ; (f) forming a capacitive film entirely covering said lower electrode therewith and further covering said first film therewith ; (g) forming an upper electrode (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer, second sub interlevel dielectric layer, second etch stop layer) over said capacitive film ; (h) forming a third film on said upper electrode ; (i) etching said third film in such a manner that an end surface of said third film , a side surface of said upper electrode , a side surface of said capacitive film , and said first film are exposed , and that said upper electrode is co-owned by a plurality of said lower electrodes , said third film being composed of a third material through which hydrogen is not allowed to pass ; and (j) forming a fourth film covering both said end surface of said third film and said side surface of said capacitive film therewith , said fourth film being composed of a fourth material through which hydrogen is not allowed to pass . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (interlayer insulating film, upper electrode, contact hole, first film, second film) layer insulates said contact region . |
US6121083A CLAIM 1 . A method of fabricating a semiconductor device , comprising the steps of : (a) forming a multi-layered interlayer insulating film (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer, second sub interlevel dielectric layer, second etch stop layer) on a semiconductor substrate , said multi-layered interlayer insulating film including a first film (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer, second sub interlevel dielectric layer, second etch stop layer) , as an uppermost film , composed of a first material through which hydrogen is not allowed to pass ; (b) forming a plurality of contact hole (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer, second sub interlevel dielectric layer, second etch stop layer) s in a row through said multi-layered interlayer insulating film to said semiconductor substrate ; (c) forming a second film (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer, second sub interlevel dielectric layer, second etch stop layer) on an inner wall of said contact holes , said second film being composed of a second material through which hydrogen is not allowed to pass ; (d) forming a plug layer in said contact holes , said plug layer being composed of an electrically conductive material ; (e) forming a lower electrode on said semiconductor substrate over said plug layer in such a manner that said lower electrode is more extensive than a cross-section of said contact holes ; (f) forming a capacitive film entirely covering said lower electrode therewith and further covering said first film therewith ; (g) forming an upper electrode (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer, second sub interlevel dielectric layer, second etch stop layer) over said capacitive film ; (h) forming a third film on said upper electrode ; (i) etching said third film in such a manner that an end surface of said third film , a side surface of said upper electrode , a side surface of said capacitive film , and said first film are exposed , and that said upper electrode is co-owned by a plurality of said lower electrodes , said third film being composed of a third material through which hydrogen is not allowed to pass ; and (j) forming a fourth film covering both said end surface of said third film and said side surface of said capacitive film therewith , said fourth film being composed of a fourth material through which hydrogen is not allowed to pass . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch stop layer (interlayer insulating film, upper electrode, contact hole, first film, second film) protects lower layers during an etching process . |
US6121083A CLAIM 1 . A method of fabricating a semiconductor device , comprising the steps of : (a) forming a multi-layered interlayer insulating film (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer, second sub interlevel dielectric layer, second etch stop layer) on a semiconductor substrate , said multi-layered interlayer insulating film including a first film (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer, second sub interlevel dielectric layer, second etch stop layer) , as an uppermost film , composed of a first material through which hydrogen is not allowed to pass ; (b) forming a plurality of contact hole (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer, second sub interlevel dielectric layer, second etch stop layer) s in a row through said multi-layered interlayer insulating film to said semiconductor substrate ; (c) forming a second film (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer, second sub interlevel dielectric layer, second etch stop layer) on an inner wall of said contact holes , said second film being composed of a second material through which hydrogen is not allowed to pass ; (d) forming a plug layer in said contact holes , said plug layer being composed of an electrically conductive material ; (e) forming a lower electrode on said semiconductor substrate over said plug layer in such a manner that said lower electrode is more extensive than a cross-section of said contact holes ; (f) forming a capacitive film entirely covering said lower electrode therewith and further covering said first film therewith ; (g) forming an upper electrode (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer, second sub interlevel dielectric layer, second etch stop layer) over said capacitive film ; (h) forming a third film on said upper electrode ; (i) etching said third film in such a manner that an end surface of said third film , a side surface of said upper electrode , a side surface of said capacitive film , and said first film are exposed , and that said upper electrode is co-owned by a plurality of said lower electrodes , said third film being composed of a third material through which hydrogen is not allowed to pass ; and (j) forming a fourth film covering both said end surface of said third film and said side surface of said capacitive film therewith , said fourth film being composed of a fourth material through which hydrogen is not allowed to pass . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (interlayer insulating film, upper electrode, contact hole, first film, second film) layer insulates said contact region . |
US6121083A CLAIM 1 . A method of fabricating a semiconductor device , comprising the steps of : (a) forming a multi-layered interlayer insulating film (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer, second sub interlevel dielectric layer, second etch stop layer) on a semiconductor substrate , said multi-layered interlayer insulating film including a first film (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer, second sub interlevel dielectric layer, second etch stop layer) , as an uppermost film , composed of a first material through which hydrogen is not allowed to pass ; (b) forming a plurality of contact hole (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer, second sub interlevel dielectric layer, second etch stop layer) s in a row through said multi-layered interlayer insulating film to said semiconductor substrate ; (c) forming a second film (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer, second sub interlevel dielectric layer, second etch stop layer) on an inner wall of said contact holes , said second film being composed of a second material through which hydrogen is not allowed to pass ; (d) forming a plug layer in said contact holes , said plug layer being composed of an electrically conductive material ; (e) forming a lower electrode on said semiconductor substrate over said plug layer in such a manner that said lower electrode is more extensive than a cross-section of said contact holes ; (f) forming a capacitive film entirely covering said lower electrode therewith and further covering said first film therewith ; (g) forming an upper electrode (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer, second sub interlevel dielectric layer, second etch stop layer) over said capacitive film ; (h) forming a third film on said upper electrode ; (i) etching said third film in such a manner that an end surface of said third film , a side surface of said upper electrode , a side surface of said capacitive film , and said first film are exposed , and that said upper electrode is co-owned by a plurality of said lower electrodes , said third film being composed of a third material through which hydrogen is not allowed to pass ; and (j) forming a fourth film covering both said end surface of said third film and said side surface of said capacitive film therewith , said fourth film being composed of a fourth material through which hydrogen is not allowed to pass . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (interlayer insulating film, upper electrode, contact hole, first film, second film) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer (interlayer insulating film, upper electrode, contact hole, first film, second film) is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6121083A CLAIM 1 . A method of fabricating a semiconductor device , comprising the steps of : (a) forming a multi-layered interlayer insulating film (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer, second sub interlevel dielectric layer, second etch stop layer) on a semiconductor substrate , said multi-layered interlayer insulating film including a first film (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer, second sub interlevel dielectric layer, second etch stop layer) , as an uppermost film , composed of a first material through which hydrogen is not allowed to pass ; (b) forming a plurality of contact hole (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer, second sub interlevel dielectric layer, second etch stop layer) s in a row through said multi-layered interlayer insulating film to said semiconductor substrate ; (c) forming a second film (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer, second sub interlevel dielectric layer, second etch stop layer) on an inner wall of said contact holes , said second film being composed of a second material through which hydrogen is not allowed to pass ; (d) forming a plug layer in said contact holes , said plug layer being composed of an electrically conductive material ; (e) forming a lower electrode on said semiconductor substrate over said plug layer in such a manner that said lower electrode is more extensive than a cross-section of said contact holes ; (f) forming a capacitive film entirely covering said lower electrode therewith and further covering said first film therewith ; (g) forming an upper electrode (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer, second sub interlevel dielectric layer, second etch stop layer) over said capacitive film ; (h) forming a third film on said upper electrode ; (i) etching said third film in such a manner that an end surface of said third film , a side surface of said upper electrode , a side surface of said capacitive film , and said first film are exposed , and that said upper electrode is co-owned by a plurality of said lower electrodes , said third film being composed of a third material through which hydrogen is not allowed to pass ; and (j) forming a fourth film covering both said end surface of said third film and said side surface of said capacitive film therewith , said fourth film being composed of a fourth material through which hydrogen is not allowed to pass . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric (interlayer insulating film, upper electrode, contact hole, first film, second film) layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range (second material) of about 0 . 16 μm to 0 . 18 μm wide . |
US6121083A CLAIM 1 . A method of fabricating a semiconductor device , comprising the steps of : (a) forming a multi-layered interlayer insulating film (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer, second sub interlevel dielectric layer, second etch stop layer) on a semiconductor substrate , said multi-layered interlayer insulating film including a first film (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer, second sub interlevel dielectric layer, second etch stop layer) , as an uppermost film , composed of a first material through which hydrogen is not allowed to pass ; (b) forming a plurality of contact hole (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer, second sub interlevel dielectric layer, second etch stop layer) s in a row through said multi-layered interlayer insulating film to said semiconductor substrate ; (c) forming a second film (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer, second sub interlevel dielectric layer, second etch stop layer) on an inner wall of said contact holes , said second film being composed of a second material (second range) through which hydrogen is not allowed to pass ; (d) forming a plug layer in said contact holes , said plug layer being composed of an electrically conductive material ; (e) forming a lower electrode on said semiconductor substrate over said plug layer in such a manner that said lower electrode is more extensive than a cross-section of said contact holes ; (f) forming a capacitive film entirely covering said lower electrode therewith and further covering said first film therewith ; (g) forming an upper electrode (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer, second sub interlevel dielectric layer, second etch stop layer) over said capacitive film ; (h) forming a third film on said upper electrode ; (i) etching said third film in such a manner that an end surface of said third film , a side surface of said upper electrode , a side surface of said capacitive film , and said first film are exposed , and that said upper electrode is co-owned by a plurality of said lower electrodes , said third film being composed of a third material through which hydrogen is not allowed to pass ; and (j) forming a fourth film covering both said end surface of said third film and said side surface of said capacitive film therewith , said fourth film being composed of a fourth material through which hydrogen is not allowed to pass . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer (interlayer insulating film, upper electrode, contact hole, first film, second film) wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (interlayer insulating film, upper electrode, contact hole, first film, second film) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom (lower electrode) , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US6121083A CLAIM 1 . A method of fabricating a semiconductor device , comprising the steps of : (a) forming a multi-layered interlayer insulating film (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer, second sub interlevel dielectric layer, second etch stop layer) on a semiconductor substrate , said multi-layered interlayer insulating film including a first film (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer, second sub interlevel dielectric layer, second etch stop layer) , as an uppermost film , composed of a first material through which hydrogen is not allowed to pass ; (b) forming a plurality of contact hole (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer, second sub interlevel dielectric layer, second etch stop layer) s in a row through said multi-layered interlayer insulating film to said semiconductor substrate ; (c) forming a second film (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer, second sub interlevel dielectric layer, second etch stop layer) on an inner wall of said contact holes , said second film being composed of a second material through which hydrogen is not allowed to pass ; (d) forming a plug layer in said contact holes , said plug layer being composed of an electrically conductive material ; (e) forming a lower electrode (contact bottom) on said semiconductor substrate over said plug layer in such a manner that said lower electrode is more extensive than a cross-section of said contact holes ; (f) forming a capacitive film entirely covering said lower electrode therewith and further covering said first film therewith ; (g) forming an upper electrode (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer, second sub interlevel dielectric layer, second etch stop layer) over said capacitive film ; (h) forming a third film on said upper electrode ; (i) etching said third film in such a manner that an end surface of said third film , a side surface of said upper electrode , a side surface of said capacitive film , and said first film are exposed , and that said upper electrode is co-owned by a plurality of said lower electrodes , said third film being composed of a third material through which hydrogen is not allowed to pass ; and (j) forming a fourth film covering both said end surface of said third film and said side surface of said capacitive film therewith , said fourth film being composed of a fourth material through which hydrogen is not allowed to pass . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (interlayer insulating film, upper electrode, contact hole, first film, second film) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer (interlayer insulating film, upper electrode, contact hole, first film, second film) is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6121083A CLAIM 1 . A method of fabricating a semiconductor device , comprising the steps of : (a) forming a multi-layered interlayer insulating film (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer, second sub interlevel dielectric layer, second etch stop layer) on a semiconductor substrate , said multi-layered interlayer insulating film including a first film (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer, second sub interlevel dielectric layer, second etch stop layer) , as an uppermost film , composed of a first material through which hydrogen is not allowed to pass ; (b) forming a plurality of contact hole (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer, second sub interlevel dielectric layer, second etch stop layer) s in a row through said multi-layered interlayer insulating film to said semiconductor substrate ; (c) forming a second film (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer, second sub interlevel dielectric layer, second etch stop layer) on an inner wall of said contact holes , said second film being composed of a second material through which hydrogen is not allowed to pass ; (d) forming a plug layer in said contact holes , said plug layer being composed of an electrically conductive material ; (e) forming a lower electrode on said semiconductor substrate over said plug layer in such a manner that said lower electrode is more extensive than a cross-section of said contact holes ; (f) forming a capacitive film entirely covering said lower electrode therewith and further covering said first film therewith ; (g) forming an upper electrode (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer, second sub interlevel dielectric layer, second etch stop layer) over said capacitive film ; (h) forming a third film on said upper electrode ; (i) etching said third film in such a manner that an end surface of said third film , a side surface of said upper electrode , a side surface of said capacitive film , and said first film are exposed , and that said upper electrode is co-owned by a plurality of said lower electrodes , said third film being composed of a third material through which hydrogen is not allowed to pass ; and (j) forming a fourth film covering both said end surface of said third film and said side surface of said capacitive film therewith , said fourth film being composed of a fourth material through which hydrogen is not allowed to pass . |
| US7977797B2 CLAIM 13 . An integrated circuit of claim 11 further comprising a floating gate (drain region) . |
US6121083A CLAIM 9 . The method as set forth in claim 1 , wherein said contact holes is formed in said step (b) so as to electrically connect said capacitive film to a source or drain region (floating gate) formed in said semiconductor substrate . |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region is a first range of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range (second material) of about 0 . 16 μm to 0 . 18 μm wide . |
US6121083A CLAIM 1 . A method of fabricating a semiconductor device , comprising the steps of : (a) forming a multi-layered interlayer insulating film on a semiconductor substrate , said multi-layered interlayer insulating film including a first film , as an uppermost film , composed of a first material through which hydrogen is not allowed to pass ; (b) forming a plurality of contact holes in a row through said multi-layered interlayer insulating film to said semiconductor substrate ; (c) forming a second film on an inner wall of said contact holes , said second film being composed of a second material (second range) through which hydrogen is not allowed to pass ; (d) forming a plug layer in said contact holes , said plug layer being composed of an electrically conductive material ; (e) forming a lower electrode on said semiconductor substrate over said plug layer in such a manner that said lower electrode is more extensive than a cross-section of said contact holes ; (f) forming a capacitive film entirely covering said lower electrode therewith and further covering said first film therewith ; (g) forming an upper electrode over said capacitive film ; (h) forming a third film on said upper electrode ; (i) etching said third film in such a manner that an end surface of said third film , a side surface of said upper electrode , a side surface of said capacitive film , and said first film are exposed , and that said upper electrode is co-owned by a plurality of said lower electrodes , said third film being composed of a third material through which hydrogen is not allowed to pass ; and (j) forming a fourth film covering both said end surface of said third film and said side surface of said capacitive film therewith , said fourth film being composed of a fourth material through which hydrogen is not allowed to pass . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US6051462A Filed: 1998-08-05 Issued: 2000-04-18 Process for producing semiconductor device comprising a memory element and a logic element (Original Assignee) Sony Corp (Current Assignee) Sony Corp Keiichi Ohno |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer (fourth insulating) directly on said substrate in said contact region ; a first sub interlevel dielectric (upper electrode, contact hole) layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US6051462A CLAIM 1 . A process for producing a semiconductor device comprising : a first step , in which a conductive pattern is formed on a first region and a second region of a semiconductor substrate , a first insulating film is formed along a shape of said conductive pattern on said semiconductor substrate , and a second insulating film comprising a material that ensures an etching selectivity with said first insulating film is formed on said first insulating film to make its surface flat ; a second step , in which a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) is formed at least in said first insulating film and said second insulating film in said first region , and a side wall comprising a material that ensures an etching selectivity with said second insulating film and prevents its own silicidation is formed on an inner wall of said contact hole ; a third step , in which a plug is formed by embedding a conductive material in said contact hole via said side wall ; a fourth step , in which said second insulating film is removed by etching , to expose said plug and said first insulating film , and said first insulating film only in said second region is subjected to etch back , to form a spacer side wall comprising said first insulating film on a side wall of said conductive pattern in said second region , and to expose a surface of said semiconductor substrate in said second region ; a fifth step , in which a silicide layer is formed on said exposed surface of said semiconductor substrate ; and a sixth step , in which a third insulating film comprising a material that ensures an etching selectivity with said first insulating film is formed over said plug , said first insulating film and said conductive pattern , and a surface of said third insulating film is flattened to expose an upper surface of said plug . US6051462A CLAIM 3 . A process for producing a semiconductor device as claimed in claim 2 , wherein in said step of forming a capacitor , a lower electrode comprising a metallic material is formed above said third insulating film , a capacitor insulating film is formed on a surface of said lower electrode , and an upper electrode (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) comprising a metallic material is formed on a surface of said capacitor insulating film . US6051462A CLAIM 4 . A process for producing a semiconductor device comprising : a first step , in which a conductive pattern is formed on a first region and a second region of a semiconductor substrate , a first insulating film is formed along a shape of said conductive pattern on said semiconductor substrate , and a second insulating film comprising a material that ensures an etching selectivity with said first insulating film is formed on said first insulating film to make its surface flat ; a second step , in which a contact hole reaching said semiconductor substrate is formed at least in said insulating film and said second insulating film in said first region , and a plug is formed by embedding a conductive material in said contact hole ; a third step , in which said second insulating film is removed by etching , to expose said plug and said first insulating film , and a third insulating film is formed over said plug and said first insulating film ; a fourth step , in which said third insulating film and said first insulating film only in said second region is subjected to etch back , to form a spacer side wall comprising said third insulating film and said first insulating film on a side wall of said conductive pattern in said second region , and to expose a surface of said semiconductor substrate in said second region ; a fifth step , in which a silicide layer is formed on said exposed surface of said semiconductor substrate ; and a sixth step , in which a fourth insulating (first etch stop layer) film comprising a material that ensures an etching selectivity with said third insulating film is formed over said plug and said first insulating film , and a surface of said fourth insulating film is flattened to expose an upper surface of said plug . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer (fourth insulating) protects removal of a substrate material by an etch process . |
US6051462A CLAIM 4 . A process for producing a semiconductor device comprising : a first step , in which a conductive pattern is formed on a first region and a second region of a semiconductor substrate , a first insulating film is formed along a shape of said conductive pattern on said semiconductor substrate , and a second insulating film comprising a material that ensures an etching selectivity with said first insulating film is formed on said first insulating film to make its surface flat ; a second step , in which a contact hole reaching said semiconductor substrate is formed at least in said insulating film and said second insulating film in said first region , and a plug is formed by embedding a conductive material in said contact hole ; a third step , in which said second insulating film is removed by etching , to expose said plug and said first insulating film , and a third insulating film is formed over said plug and said first insulating film ; a fourth step , in which said third insulating film and said first insulating film only in said second region is subjected to etch back , to form a spacer side wall comprising said third insulating film and said first insulating film on a side wall of said conductive pattern in said second region , and to expose a surface of said semiconductor substrate in said second region ; a fifth step , in which a silicide layer is formed on said exposed surface of said semiconductor substrate ; and a sixth step , in which a fourth insulating (first etch stop layer) film comprising a material that ensures an etching selectivity with said third insulating film is formed over said plug and said first insulating film , and a surface of said fourth insulating film is flattened to expose an upper surface of said plug . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (upper electrode, contact hole) layer insulates said contact region . |
US6051462A CLAIM 1 . A process for producing a semiconductor device comprising : a first step , in which a conductive pattern is formed on a first region and a second region of a semiconductor substrate , a first insulating film is formed along a shape of said conductive pattern on said semiconductor substrate , and a second insulating film comprising a material that ensures an etching selectivity with said first insulating film is formed on said first insulating film to make its surface flat ; a second step , in which a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) is formed at least in said first insulating film and said second insulating film in said first region , and a side wall comprising a material that ensures an etching selectivity with said second insulating film and prevents its own silicidation is formed on an inner wall of said contact hole ; a third step , in which a plug is formed by embedding a conductive material in said contact hole via said side wall ; a fourth step , in which said second insulating film is removed by etching , to expose said plug and said first insulating film , and said first insulating film only in said second region is subjected to etch back , to form a spacer side wall comprising said first insulating film on a side wall of said conductive pattern in said second region , and to expose a surface of said semiconductor substrate in said second region ; a fifth step , in which a silicide layer is formed on said exposed surface of said semiconductor substrate ; and a sixth step , in which a third insulating film comprising a material that ensures an etching selectivity with said first insulating film is formed over said plug , said first insulating film and said conductive pattern , and a surface of said third insulating film is flattened to expose an upper surface of said plug . US6051462A CLAIM 3 . A process for producing a semiconductor device as claimed in claim 2 , wherein in said step of forming a capacitor , a lower electrode comprising a metallic material is formed above said third insulating film , a capacitor insulating film is formed on a surface of said lower electrode , and an upper electrode (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) comprising a metallic material is formed on a surface of said capacitor insulating film . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (upper electrode, contact hole) layer insulates said contact region . |
US6051462A CLAIM 1 . A process for producing a semiconductor device comprising : a first step , in which a conductive pattern is formed on a first region and a second region of a semiconductor substrate , a first insulating film is formed along a shape of said conductive pattern on said semiconductor substrate , and a second insulating film comprising a material that ensures an etching selectivity with said first insulating film is formed on said first insulating film to make its surface flat ; a second step , in which a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) is formed at least in said first insulating film and said second insulating film in said first region , and a side wall comprising a material that ensures an etching selectivity with said second insulating film and prevents its own silicidation is formed on an inner wall of said contact hole ; a third step , in which a plug is formed by embedding a conductive material in said contact hole via said side wall ; a fourth step , in which said second insulating film is removed by etching , to expose said plug and said first insulating film , and said first insulating film only in said second region is subjected to etch back , to form a spacer side wall comprising said first insulating film on a side wall of said conductive pattern in said second region , and to expose a surface of said semiconductor substrate in said second region ; a fifth step , in which a silicide layer is formed on said exposed surface of said semiconductor substrate ; and a sixth step , in which a third insulating film comprising a material that ensures an etching selectivity with said first insulating film is formed over said plug , said first insulating film and said conductive pattern , and a surface of said third insulating film is flattened to expose an upper surface of said plug . US6051462A CLAIM 3 . A process for producing a semiconductor device as claimed in claim 2 , wherein in said step of forming a capacitor , a lower electrode comprising a metallic material is formed above said third insulating film , a capacitor insulating film is formed on a surface of said lower electrode , and an upper electrode (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) comprising a metallic material is formed on a surface of said capacitor insulating film . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer (fourth insulating) is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (upper electrode, contact hole) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6051462A CLAIM 1 . A process for producing a semiconductor device comprising : a first step , in which a conductive pattern is formed on a first region and a second region of a semiconductor substrate , a first insulating film is formed along a shape of said conductive pattern on said semiconductor substrate , and a second insulating film comprising a material that ensures an etching selectivity with said first insulating film is formed on said first insulating film to make its surface flat ; a second step , in which a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) is formed at least in said first insulating film and said second insulating film in said first region , and a side wall comprising a material that ensures an etching selectivity with said second insulating film and prevents its own silicidation is formed on an inner wall of said contact hole ; a third step , in which a plug is formed by embedding a conductive material in said contact hole via said side wall ; a fourth step , in which said second insulating film is removed by etching , to expose said plug and said first insulating film , and said first insulating film only in said second region is subjected to etch back , to form a spacer side wall comprising said first insulating film on a side wall of said conductive pattern in said second region , and to expose a surface of said semiconductor substrate in said second region ; a fifth step , in which a silicide layer is formed on said exposed surface of said semiconductor substrate ; and a sixth step , in which a third insulating film comprising a material that ensures an etching selectivity with said first insulating film is formed over said plug , said first insulating film and said conductive pattern , and a surface of said third insulating film is flattened to expose an upper surface of said plug . US6051462A CLAIM 3 . A process for producing a semiconductor device as claimed in claim 2 , wherein in said step of forming a capacitor , a lower electrode comprising a metallic material is formed above said third insulating film , a capacitor insulating film is formed on a surface of said lower electrode , and an upper electrode (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) comprising a metallic material is formed on a surface of said capacitor insulating film . US6051462A CLAIM 4 . A process for producing a semiconductor device comprising : a first step , in which a conductive pattern is formed on a first region and a second region of a semiconductor substrate , a first insulating film is formed along a shape of said conductive pattern on said semiconductor substrate , and a second insulating film comprising a material that ensures an etching selectivity with said first insulating film is formed on said first insulating film to make its surface flat ; a second step , in which a contact hole reaching said semiconductor substrate is formed at least in said insulating film and said second insulating film in said first region , and a plug is formed by embedding a conductive material in said contact hole ; a third step , in which said second insulating film is removed by etching , to expose said plug and said first insulating film , and a third insulating film is formed over said plug and said first insulating film ; a fourth step , in which said third insulating film and said first insulating film only in said second region is subjected to etch back , to form a spacer side wall comprising said third insulating film and said first insulating film on a side wall of said conductive pattern in said second region , and to expose a surface of said semiconductor substrate in said second region ; a fifth step , in which a silicide layer is formed on said exposed surface of said semiconductor substrate ; and a sixth step , in which a fourth insulating (first etch stop layer) film comprising a material that ensures an etching selectivity with said third insulating film is formed over said plug and said first insulating film , and a surface of said fourth insulating film is flattened to expose an upper surface of said plug . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric (upper electrode, contact hole) layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US6051462A CLAIM 1 . A process for producing a semiconductor device comprising : a first step , in which a conductive pattern is formed on a first region and a second region of a semiconductor substrate , a first insulating film is formed along a shape of said conductive pattern on said semiconductor substrate , and a second insulating film comprising a material that ensures an etching selectivity with said first insulating film is formed on said first insulating film to make its surface flat ; a second step , in which a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) is formed at least in said first insulating film and said second insulating film in said first region , and a side wall comprising a material that ensures an etching selectivity with said second insulating film and prevents its own silicidation is formed on an inner wall of said contact hole ; a third step , in which a plug is formed by embedding a conductive material in said contact hole via said side wall ; a fourth step , in which said second insulating film is removed by etching , to expose said plug and said first insulating film , and said first insulating film only in said second region is subjected to etch back , to form a spacer side wall comprising said first insulating film on a side wall of said conductive pattern in said second region , and to expose a surface of said semiconductor substrate in said second region ; a fifth step , in which a silicide layer is formed on said exposed surface of said semiconductor substrate ; and a sixth step , in which a third insulating film comprising a material that ensures an etching selectivity with said first insulating film is formed over said plug , said first insulating film and said conductive pattern , and a surface of said third insulating film is flattened to expose an upper surface of said plug . US6051462A CLAIM 3 . A process for producing a semiconductor device as claimed in claim 2 , wherein in said step of forming a capacitor , a lower electrode comprising a metallic material is formed above said third insulating film , a capacitor insulating film is formed on a surface of said lower electrode , and an upper electrode (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) comprising a metallic material is formed on a surface of said capacitor insulating film . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer (fourth insulating) and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (upper electrode, contact hole) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom (lower electrode) , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US6051462A CLAIM 1 . A process for producing a semiconductor device comprising : a first step , in which a conductive pattern is formed on a first region and a second region of a semiconductor substrate , a first insulating film is formed along a shape of said conductive pattern on said semiconductor substrate , and a second insulating film comprising a material that ensures an etching selectivity with said first insulating film is formed on said first insulating film to make its surface flat ; a second step , in which a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) is formed at least in said first insulating film and said second insulating film in said first region , and a side wall comprising a material that ensures an etching selectivity with said second insulating film and prevents its own silicidation is formed on an inner wall of said contact hole ; a third step , in which a plug is formed by embedding a conductive material in said contact hole via said side wall ; a fourth step , in which said second insulating film is removed by etching , to expose said plug and said first insulating film , and said first insulating film only in said second region is subjected to etch back , to form a spacer side wall comprising said first insulating film on a side wall of said conductive pattern in said second region , and to expose a surface of said semiconductor substrate in said second region ; a fifth step , in which a silicide layer is formed on said exposed surface of said semiconductor substrate ; and a sixth step , in which a third insulating film comprising a material that ensures an etching selectivity with said first insulating film is formed over said plug , said first insulating film and said conductive pattern , and a surface of said third insulating film is flattened to expose an upper surface of said plug . US6051462A CLAIM 3 . A process for producing a semiconductor device as claimed in claim 2 , wherein in said step of forming a capacitor , a lower electrode (contact bottom) comprising a metallic material is formed above said third insulating film , a capacitor insulating film is formed on a surface of said lower electrode , and an upper electrode (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) comprising a metallic material is formed on a surface of said capacitor insulating film . US6051462A CLAIM 4 . A process for producing a semiconductor device comprising : a first step , in which a conductive pattern is formed on a first region and a second region of a semiconductor substrate , a first insulating film is formed along a shape of said conductive pattern on said semiconductor substrate , and a second insulating film comprising a material that ensures an etching selectivity with said first insulating film is formed on said first insulating film to make its surface flat ; a second step , in which a contact hole reaching said semiconductor substrate is formed at least in said insulating film and said second insulating film in said first region , and a plug is formed by embedding a conductive material in said contact hole ; a third step , in which said second insulating film is removed by etching , to expose said plug and said first insulating film , and a third insulating film is formed over said plug and said first insulating film ; a fourth step , in which said third insulating film and said first insulating film only in said second region is subjected to etch back , to form a spacer side wall comprising said third insulating film and said first insulating film on a side wall of said conductive pattern in said second region , and to expose a surface of said semiconductor substrate in said second region ; a fifth step , in which a silicide layer is formed on said exposed surface of said semiconductor substrate ; and a sixth step , in which a fourth insulating (first etch stop layer) film comprising a material that ensures an etching selectivity with said third insulating film is formed over said plug and said first insulating film , and a surface of said fourth insulating film is flattened to expose an upper surface of said plug . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer (fourth insulating) is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (upper electrode, contact hole) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6051462A CLAIM 1 . A process for producing a semiconductor device comprising : a first step , in which a conductive pattern is formed on a first region and a second region of a semiconductor substrate , a first insulating film is formed along a shape of said conductive pattern on said semiconductor substrate , and a second insulating film comprising a material that ensures an etching selectivity with said first insulating film is formed on said first insulating film to make its surface flat ; a second step , in which a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) is formed at least in said first insulating film and said second insulating film in said first region , and a side wall comprising a material that ensures an etching selectivity with said second insulating film and prevents its own silicidation is formed on an inner wall of said contact hole ; a third step , in which a plug is formed by embedding a conductive material in said contact hole via said side wall ; a fourth step , in which said second insulating film is removed by etching , to expose said plug and said first insulating film , and said first insulating film only in said second region is subjected to etch back , to form a spacer side wall comprising said first insulating film on a side wall of said conductive pattern in said second region , and to expose a surface of said semiconductor substrate in said second region ; a fifth step , in which a silicide layer is formed on said exposed surface of said semiconductor substrate ; and a sixth step , in which a third insulating film comprising a material that ensures an etching selectivity with said first insulating film is formed over said plug , said first insulating film and said conductive pattern , and a surface of said third insulating film is flattened to expose an upper surface of said plug . US6051462A CLAIM 3 . A process for producing a semiconductor device as claimed in claim 2 , wherein in said step of forming a capacitor , a lower electrode comprising a metallic material is formed above said third insulating film , a capacitor insulating film is formed on a surface of said lower electrode , and an upper electrode (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) comprising a metallic material is formed on a surface of said capacitor insulating film . US6051462A CLAIM 4 . A process for producing a semiconductor device comprising : a first step , in which a conductive pattern is formed on a first region and a second region of a semiconductor substrate , a first insulating film is formed along a shape of said conductive pattern on said semiconductor substrate , and a second insulating film comprising a material that ensures an etching selectivity with said first insulating film is formed on said first insulating film to make its surface flat ; a second step , in which a contact hole reaching said semiconductor substrate is formed at least in said insulating film and said second insulating film in said first region , and a plug is formed by embedding a conductive material in said contact hole ; a third step , in which said second insulating film is removed by etching , to expose said plug and said first insulating film , and a third insulating film is formed over said plug and said first insulating film ; a fourth step , in which said third insulating film and said first insulating film only in said second region is subjected to etch back , to form a spacer side wall comprising said third insulating film and said first insulating film on a side wall of said conductive pattern in said second region , and to expose a surface of said semiconductor substrate in said second region ; a fifth step , in which a silicide layer is formed on said exposed surface of said semiconductor substrate ; and a sixth step , in which a fourth insulating (first etch stop layer) film comprising a material that ensures an etching selectivity with said third insulating film is formed over said plug and said first insulating film , and a surface of said fourth insulating film is flattened to expose an upper surface of said plug . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US6066541A Filed: 1998-04-27 Issued: 2000-05-23 Method for fabricating a cylindrical capacitor (Original Assignee) Nanya Technology Corp (Current Assignee) Nanya Technology Corp Ming-Teng Hsieh, Tsu-An Lin, Pei-Ying Lee, Hsing-Chuan Tsai |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area (second conductive layer) of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (contact hole) layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US6066541A CLAIM 1 . A method for fabricating a cylindrical capacitor on a substrate having a source region , a drain region , and a gate electrode , comprising the steps of : (a) forming an insulating layer over surface of said substrate ; (b) forming sequentially a barrier layer , a sacrificing layer and a mask layer over said insulating layer ; (c) forming a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) through said mask layer , said sacrificing layer , said barrier layer , and said insulating layer exposing said source region ; (d) forming spacers on the sidewalls of said contact hole ; (e) forming a first conductive layer over said mask layer and filling said contact hole thereby forming an electrical connection to said source region ; (f) patterning said first conductive layer to form a storage electrode of said capacitor , said patterning forming exposed portions and unexposed portions of said mask layer ; (g) removing said exposed portions of said mask layer ; (h) isotropically etching said sacrificing layer using said unexposed portions , said spacers and said barrier layer as stopping layers ; (i) forming a dielectric layer over said storage electrode ; and (j) forming a second conductive layer (substrate coupling area) as an opposite electrode over said dielectric layer thereby completing said capacitor . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (contact hole) layer insulates said contact region . |
US6066541A CLAIM 1 . A method for fabricating a cylindrical capacitor on a substrate having a source region , a drain region , and a gate electrode , comprising the steps of : (a) forming an insulating layer over surface of said substrate ; (b) forming sequentially a barrier layer , a sacrificing layer and a mask layer over said insulating layer ; (c) forming a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) through said mask layer , said sacrificing layer , said barrier layer , and said insulating layer exposing said source region ; (d) forming spacers on the sidewalls of said contact hole ; (e) forming a first conductive layer over said mask layer and filling said contact hole thereby forming an electrical connection to said source region ; (f) patterning said first conductive layer to form a storage electrode of said capacitor , said patterning forming exposed portions and unexposed portions of said mask layer ; (g) removing said exposed portions of said mask layer ; (h) isotropically etching said sacrificing layer using said unexposed portions , said spacers and said barrier layer as stopping layers ; (i) forming a dielectric layer over said storage electrode ; and (j) forming a second conductive layer as an opposite electrode over said dielectric layer thereby completing said capacitor . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (contact hole) layer insulates said contact region . |
US6066541A CLAIM 1 . A method for fabricating a cylindrical capacitor on a substrate having a source region , a drain region , and a gate electrode , comprising the steps of : (a) forming an insulating layer over surface of said substrate ; (b) forming sequentially a barrier layer , a sacrificing layer and a mask layer over said insulating layer ; (c) forming a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) through said mask layer , said sacrificing layer , said barrier layer , and said insulating layer exposing said source region ; (d) forming spacers on the sidewalls of said contact hole ; (e) forming a first conductive layer over said mask layer and filling said contact hole thereby forming an electrical connection to said source region ; (f) patterning said first conductive layer to form a storage electrode of said capacitor , said patterning forming exposed portions and unexposed portions of said mask layer ; (g) removing said exposed portions of said mask layer ; (h) isotropically etching said sacrificing layer using said unexposed portions , said spacers and said barrier layer as stopping layers ; (i) forming a dielectric layer over said storage electrode ; and (j) forming a second conductive layer as an opposite electrode over said dielectric layer thereby completing said capacitor . |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area (second conductive layer) of said contact region permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
US6066541A CLAIM 1 . A method for fabricating a cylindrical capacitor on a substrate having a source region , a drain region , and a gate electrode , comprising the steps of : (a) forming an insulating layer over surface of said substrate ; (b) forming sequentially a barrier layer , a sacrificing layer and a mask layer over said insulating layer ; (c) forming a contact hole through said mask layer , said sacrificing layer , said barrier layer , and said insulating layer exposing said source region ; (d) forming spacers on the sidewalls of said contact hole ; (e) forming a first conductive layer over said mask layer and filling said contact hole thereby forming an electrical connection to said source region ; (f) patterning said first conductive layer to form a storage electrode of said capacitor , said patterning forming exposed portions and unexposed portions of said mask layer ; (g) removing said exposed portions of said mask layer ; (h) isotropically etching said sacrificing layer using said unexposed portions , said spacers and said barrier layer as stopping layers ; (i) forming a dielectric layer over said storage electrode ; and (j) forming a second conductive layer (substrate coupling area) as an opposite electrode over said dielectric layer thereby completing said capacitor . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (contact hole) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6066541A CLAIM 1 . A method for fabricating a cylindrical capacitor on a substrate having a source region , a drain region , and a gate electrode , comprising the steps of : (a) forming an insulating layer over surface of said substrate ; (b) forming sequentially a barrier layer , a sacrificing layer and a mask layer over said insulating layer ; (c) forming a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) through said mask layer , said sacrificing layer , said barrier layer , and said insulating layer exposing said source region ; (d) forming spacers on the sidewalls of said contact hole ; (e) forming a first conductive layer over said mask layer and filling said contact hole thereby forming an electrical connection to said source region ; (f) patterning said first conductive layer to form a storage electrode of said capacitor , said patterning forming exposed portions and unexposed portions of said mask layer ; (g) removing said exposed portions of said mask layer ; (h) isotropically etching said sacrificing layer using said unexposed portions , said spacers and said barrier layer as stopping layers ; (i) forming a dielectric layer over said storage electrode ; and (j) forming a second conductive layer as an opposite electrode over said dielectric layer thereby completing said capacitor . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space (first space, said sub) in a portion of said first sub interlevel dielectric (contact hole) layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space (second space) in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US6066541A CLAIM 1 . A method for fabricating a cylindrical capacitor on a substrate having a source region , a drain region , and a gate electrode , comprising the steps of : (a) forming an insulating layer over surface of said sub (first space) strate ; (b) forming sequentially a barrier layer , a sacrificing layer and a mask layer over said insulating layer ; (c) forming a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) through said mask layer , said sacrificing layer , said barrier layer , and said insulating layer exposing said source region ; (d) forming spacers on the sidewalls of said contact hole ; (e) forming a first conductive layer over said mask layer and filling said contact hole thereby forming an electrical connection to said source region ; (f) patterning said first conductive layer to form a storage electrode of said capacitor , said patterning forming exposed portions and unexposed portions of said mask layer ; (g) removing said exposed portions of said mask layer ; (h) isotropically etching said sacrificing layer using said unexposed portions , said spacers and said barrier layer as stopping layers ; (i) forming a dielectric layer over said storage electrode ; and (j) forming a second conductive layer as an opposite electrode over said dielectric layer thereby completing said capacitor . US6066541A CLAIM 12 . A method for fabricating a cylindrical capacitor on a substrate having a source region , a drain region , and a gate electrode , comprising the steps of : (a) forming an insulating layer over surface of said substrate ; (b) forming sequentially a barrier layer , a sacrificing layer and a mask layer over said insulating layer ; (c) forming an opening through said mask layer , said sacrificing layer , and said barrier layer exposing said insulating layer ; (d) forming first space (first space) rs on the sidewalls of said opening ; (e) anisotropically etching said exposed insulating layer using said mask layer and said first spacers as a mask , thereby forming a contact hole that exposes said source region ; (f) forming second space (second space) rs on the sidewalls of said contact hole ; (g) forming a first conductive layer over said mask layer and filling said contact hole thereby forming an electrical connection to said source region ; (h) patterning said first conductive layer to form a storage electrode of said capacitor , said patterning forming exposed portions and unexposed portions of said mask layer ; (i) removing said exposed portions of said mask layer ; (j) isotropically etching said sacrificing layer using said unexposed portions , said first spacers and said barrier layer as stopping layers ; (k) forming a dielectric layer over said storage electrode ; and (l) forming a second conductive layer as an opposite electrode over said dielectric layer thereby completing said capacitor . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US6066541A CLAIM 9 . The method for fabricating a cylindrical capacitor as claimed in claim 1 , wherein said first conductive layer is formed by the following steps of : forming a polysilicon plug in said contact hole to electrically connect to the source region ; and forming (anti reflective coating) a polysilicon layer over said polysilicon plug nd said mask layer . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (contact hole) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area (second conductive layer) of said contact region is smaller than a metal layer coupling area of said contact region . |
US6066541A CLAIM 1 . A method for fabricating a cylindrical capacitor on a substrate having a source region , a drain region , and a gate electrode , comprising the steps of : (a) forming an insulating layer over surface of said substrate ; (b) forming sequentially a barrier layer , a sacrificing layer and a mask layer over said insulating layer ; (c) forming a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) through said mask layer , said sacrificing layer , said barrier layer , and said insulating layer exposing said source region ; (d) forming spacers on the sidewalls of said contact hole ; (e) forming a first conductive layer over said mask layer and filling said contact hole thereby forming an electrical connection to said source region ; (f) patterning said first conductive layer to form a storage electrode of said capacitor , said patterning forming exposed portions and unexposed portions of said mask layer ; (g) removing said exposed portions of said mask layer ; (h) isotropically etching said sacrificing layer using said unexposed portions , said spacers and said barrier layer as stopping layers ; (i) forming a dielectric layer over said storage electrode ; and (j) forming a second conductive layer (substrate coupling area) as an opposite electrode over said dielectric layer thereby completing said capacitor . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (contact hole) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6066541A CLAIM 1 . A method for fabricating a cylindrical capacitor on a substrate having a source region , a drain region , and a gate electrode , comprising the steps of : (a) forming an insulating layer over surface of said substrate ; (b) forming sequentially a barrier layer , a sacrificing layer and a mask layer over said insulating layer ; (c) forming a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) through said mask layer , said sacrificing layer , said barrier layer , and said insulating layer exposing said source region ; (d) forming spacers on the sidewalls of said contact hole ; (e) forming a first conductive layer over said mask layer and filling said contact hole thereby forming an electrical connection to said source region ; (f) patterning said first conductive layer to form a storage electrode of said capacitor , said patterning forming exposed portions and unexposed portions of said mask layer ; (g) removing said exposed portions of said mask layer ; (h) isotropically etching said sacrificing layer using said unexposed portions , said spacers and said barrier layer as stopping layers ; (i) forming a dielectric layer over said storage electrode ; and (j) forming a second conductive layer as an opposite electrode over said dielectric layer thereby completing said capacitor . |
| US7977797B2 CLAIM 13 . An integrated circuit of claim 11 further comprising a floating gate (drain region) . |
US6066541A CLAIM 1 . A method for fabricating a cylindrical capacitor on a substrate having a source region , a drain region (floating gate) , and a gate electrode , comprising the steps of : (a) forming an insulating layer over surface of said substrate ; (b) forming sequentially a barrier layer , a sacrificing layer and a mask layer over said insulating layer ; (c) forming a contact hole through said mask layer , said sacrificing layer , said barrier layer , and said insulating layer exposing said source region ; (d) forming spacers on the sidewalls of said contact hole ; (e) forming a first conductive layer over said mask layer and filling said contact hole thereby forming an electrical connection to said source region ; (f) patterning said first conductive layer to form a storage electrode of said capacitor , said patterning forming exposed portions and unexposed portions of said mask layer ; (g) removing said exposed portions of said mask layer ; (h) isotropically etching said sacrificing layer using said unexposed portions , said spacers and said barrier layer as stopping layers ; (i) forming a dielectric layer over said storage electrode ; and (j) forming a second conductive layer as an opposite electrode over said dielectric layer thereby completing said capacitor . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US6066541A CLAIM 9 . The method for fabricating a cylindrical capacitor as claimed in claim 1 , wherein said first conductive layer is formed by the following steps of : forming a polysilicon plug in said contact hole to electrically connect to the source region ; and forming (anti reflective coating) a polysilicon layer over said polysilicon plug nd said mask layer . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5899721A Filed: 1998-03-09 Issued: 1999-05-04 Method of based spacer formation for ultra-small sapcer geometries (Original Assignee) Advanced Micro Devices Inc (Current Assignee) Advanced Micro Devices Inc Mark I. Gardner, Derrick J. Wristers |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub (upper surfaces) interlevel dielectric layer over said first etch stop layer ; a second etch (dielectric materials) stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5899721A CLAIM 1 . A method for fabricating a transistor , comprising : depositing a first dielectric material upon a semiconductor topography comprising a gate conductor and a substrate ; while maintaining the first dielectric material upon the substrate , partially removing the first dielectric material to expose an upper portion of the gate conductor ; depositing a second dielectric material different from the first dielectric material across exposed portions of the gate conductor and the first dielectric material ; and subsequent to said depositing a second dielectric material , removing portions of the first and second dielectric materials (second etch, etch process) except in regions laterally adjacent sidewall surfaces of the gate conductor . US5899721A CLAIM 11 . The method of claim 10 , further comprising forming a metal silicide layer on upper surfaces (first sub, first sub interlevel dielectric layer) of the gate conductor and the source/drain regions . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer protects removal of a substrate material by an etch process (dielectric materials) . |
US5899721A CLAIM 1 . A method for fabricating a transistor , comprising : depositing a first dielectric material upon a semiconductor topography comprising a gate conductor and a substrate ; while maintaining the first dielectric material upon the substrate , partially removing the first dielectric material to expose an upper portion of the gate conductor ; depositing a second dielectric material different from the first dielectric material across exposed portions of the gate conductor and the first dielectric material ; and subsequent to said depositing a second dielectric material , removing portions of the first and second dielectric materials (second etch, etch process) except in regions laterally adjacent sidewall surfaces of the gate conductor . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub (upper surfaces) interlevel dielectric layer insulates said contact region . |
US5899721A CLAIM 11 . The method of claim 10 , further comprising forming a metal silicide layer on upper surfaces (first sub, first sub interlevel dielectric layer) of the gate conductor and the source/drain regions . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch (dielectric materials) stop layer protects lower layers during an etching process . |
US5899721A CLAIM 1 . A method for fabricating a transistor , comprising : depositing a first dielectric material upon a semiconductor topography comprising a gate conductor and a substrate ; while maintaining the first dielectric material upon the substrate , partially removing the first dielectric material to expose an upper portion of the gate conductor ; depositing a second dielectric material different from the first dielectric material across exposed portions of the gate conductor and the first dielectric material ; and subsequent to said depositing a second dielectric material , removing portions of the first and second dielectric materials (second etch, etch process) except in regions laterally adjacent sidewall surfaces of the gate conductor . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub (upper surfaces) interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (dielectric materials) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5899721A CLAIM 1 . A method for fabricating a transistor , comprising : depositing a first dielectric material upon a semiconductor topography comprising a gate conductor and a substrate ; while maintaining the first dielectric material upon the substrate , partially removing the first dielectric material to expose an upper portion of the gate conductor ; depositing a second dielectric material different from the first dielectric material across exposed portions of the gate conductor and the first dielectric material ; and subsequent to said depositing a second dielectric material , removing portions of the first and second dielectric materials (second etch, etch process) except in regions laterally adjacent sidewall surfaces of the gate conductor . US5899721A CLAIM 11 . The method of claim 10 , further comprising forming a metal silicide layer on upper surfaces (first sub, first sub interlevel dielectric layer) of the gate conductor and the source/drain regions . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub (upper surfaces) interlevel dielectric layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space (adjacent sidewall) in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5899721A CLAIM 1 . A method for fabricating a transistor , comprising : depositing a first dielectric material upon a semiconductor topography comprising a gate conductor and a substrate ; while maintaining the first dielectric material upon the substrate , partially removing the first dielectric material to expose an upper portion of the gate conductor ; depositing a second dielectric material different from the first dielectric material across exposed portions of the gate conductor and the first dielectric material ; and subsequent to said depositing a second dielectric material , removing portions of the first and second dielectric materials except in regions laterally adjacent sidewall (second space) surfaces of the gate conductor . US5899721A CLAIM 11 . The method of claim 10 , further comprising forming a metal silicide layer on upper surfaces (first sub, first sub interlevel dielectric layer) of the gate conductor and the source/drain regions . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch (dielectric materials) stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub (upper surfaces) interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US5899721A CLAIM 1 . A method for fabricating a transistor , comprising : depositing a first dielectric material upon a semiconductor topography comprising a gate conductor and a substrate ; while maintaining the first dielectric material upon the substrate , partially removing the first dielectric material to expose an upper portion of the gate conductor ; depositing a second dielectric material different from the first dielectric material across exposed portions of the gate conductor and the first dielectric material ; and subsequent to said depositing a second dielectric material , removing portions of the first and second dielectric materials (second etch, etch process) except in regions laterally adjacent sidewall surfaces of the gate conductor . US5899721A CLAIM 11 . The method of claim 10 , further comprising forming a metal silicide layer on upper surfaces (first sub, first sub interlevel dielectric layer) of the gate conductor and the source/drain regions . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub (upper surfaces) interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (dielectric materials) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5899721A CLAIM 1 . A method for fabricating a transistor , comprising : depositing a first dielectric material upon a semiconductor topography comprising a gate conductor and a substrate ; while maintaining the first dielectric material upon the substrate , partially removing the first dielectric material to expose an upper portion of the gate conductor ; depositing a second dielectric material different from the first dielectric material across exposed portions of the gate conductor and the first dielectric material ; and subsequent to said depositing a second dielectric material , removing portions of the first and second dielectric materials (second etch, etch process) except in regions laterally adjacent sidewall surfaces of the gate conductor . US5899721A CLAIM 11 . The method of claim 10 , further comprising forming a metal silicide layer on upper surfaces (first sub, first sub interlevel dielectric layer) of the gate conductor and the source/drain regions . |
| US7977797B2 CLAIM 13 . An integrated circuit of claim 11 further comprising a floating gate (drain regions) . |
US5899721A CLAIM 3 . The method of claim 1 , further comprising forming lightly doped drain regions (floating gate) self-aligned with the sidewall surfaces of the gate conductor prior to depositing said first dielectric material . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | EP0854508A2 Filed: 1997-12-19 Issued: 1998-07-22 Method of forming contact structure (Original Assignee) International Business Machines Corp (Current Assignee) International Business Machines Corp Nancy Anne Greco, Stephen Edward Greco, Tina Jane Wagner |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch (dielectric materials) stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
EP0854508A2 CLAIM 3 The method as recited in claim 1 wherein the first and second layers respectively comprise first and second dielectric materials (second etch, etch process) . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer protects removal of a substrate material (active ion) by an etch process (dielectric materials) . |
EP0854508A2 CLAIM 3 The method as recited in claim 1 wherein the first and second layers respectively comprise first and second dielectric materials (second etch, etch process) . EP0854508A2 CLAIM 12 The method as recited in claim 11 wherein the step of removing portions of the first layer comprises reactive ion (substrate material) etching . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch (dielectric materials) stop layer protects lower layers during an etching process . |
EP0854508A2 CLAIM 3 The method as recited in claim 1 wherein the first and second layers respectively comprise first and second dielectric materials (second etch, etch process) . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (dielectric materials) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
EP0854508A2 CLAIM 3 The method as recited in claim 1 wherein the first and second layers respectively comprise first and second dielectric materials (second etch, etch process) . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch (dielectric materials) stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
EP0854508A2 CLAIM 3 The method as recited in claim 1 wherein the first and second layers respectively comprise first and second dielectric materials (second etch, etch process) . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (dielectric materials) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
EP0854508A2 CLAIM 3 The method as recited in claim 1 wherein the first and second layers respectively comprise first and second dielectric materials (second etch, etch process) . |
| US7977797B2 CLAIM 13 . An integrated circuit of claim 11 further comprising a floating gate (semiconductor structure) . |
EP0854508A2 CLAIM 1 A method of forming a semiconductor structure (floating gate) having features of differing sizes , the method comprising the steps : forming a first layer on a semiconductor substrate ; patterning only a first plurality of features of a first feature size on the first layer ; removing portions of the first layer , the portions corresponding to the first plurality of features , thus forming in the first layer a first plurality of openings corresponding to the first plurality of patterned features ; filling the first plurality of openings ; forming a second layer , the second layer overlying the first layer and the filled openings ; patterning a second plurality of features of a second feature size on the second layer ; removing portions of the first layer and second layer , the portions corresponding to the second plurality of features , thus forming in the second layer a second plurality of openings corresponding to the second plurality of patterned features , the second plurality of openings extending through the first and second layers ; filling the second plurality of openings . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | EP0926726A1 Filed: 1997-12-16 Issued: 1999-06-30 Fabrication process and electronic device having front-back through contacts for bonding onto boards (Original Assignee) STMicroelectronics SRL; SGS Thomson Microelectronics SRL (Current Assignee) STMicroelectronics SRL ; STMicroelectronics SRL Ubaldo Mastermatteo, Bruno Murari |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region (contact region) coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub (electronic device) interlevel dielectric layer over said second etch stop layer . |
EP0926726A1 CLAIM 1 A process for fabricating an electronic device (second sub) formed in a body (1) comprising regions of semiconductor material (4 , 5 , 10) and regions of insulating material (5 , 9 , 11) , said body (1) having an upper surface (11a) and a surface zone (7) close to said upper surface and housing electronic components (2) , characterized in that it comprises the steps of : producing a blind hole (18 ; 49) in a drill region (15) of said body (1) , said blind hole extending starting from said upper surface (11a) ; forming an insulating region (19' ; ; 47) of electrically insulating material , extending in said drill region (15) laterally to said blind hole (18 ; 49) ; forming a through contact (20) of conductive material filling said blind hole ; forming an electrical connection structure (23 ; 40' ; ) extending on top of said upper surface (11a) between and in electrical contact with said through contact (20) and said electronic component (2) ; removing a lower portion of said body (1) at least as far as a lower wall of said through contact (20) and forming a lower bonding surface (38) ; forming contact region (contact region) s (34) on said lower bonding surface (38) at said through contact (20) . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer protects removal of a substrate material (silicon oxide) by an etch process . |
EP0926726A1 CLAIM 7 A process according to any one of the preceding Claims , characterized in that said electrically insulating material is silicon oxide (substrate material) . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric layer insulates said contact region (contact region) . |
EP0926726A1 CLAIM 1 A process for fabricating an electronic device formed in a body (1) comprising regions of semiconductor material (4 , 5 , 10) and regions of insulating material (5 , 9 , 11) , said body (1) having an upper surface (11a) and a surface zone (7) close to said upper surface and housing electronic components (2) , characterized in that it comprises the steps of : producing a blind hole (18 ; 49) in a drill region (15) of said body (1) , said blind hole extending starting from said upper surface (11a) ; forming an insulating region (19' ; ; 47) of electrically insulating material , extending in said drill region (15) laterally to said blind hole (18 ; 49) ; forming a through contact (20) of conductive material filling said blind hole ; forming an electrical connection structure (23 ; 40' ; ) extending on top of said upper surface (11a) between and in electrical contact with said through contact (20) and said electronic component (2) ; removing a lower portion of said body (1) at least as far as a lower wall of said through contact (20) and forming a lower bonding surface (38) ; forming contact region (contact region) s (34) on said lower bonding surface (38) at said through contact (20) . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub (electronic device) interlevel dielectric layer insulates said contact region (contact region) . |
EP0926726A1 CLAIM 1 A process for fabricating an electronic device (second sub) formed in a body (1) comprising regions of semiconductor material (4 , 5 , 10) and regions of insulating material (5 , 9 , 11) , said body (1) having an upper surface (11a) and a surface zone (7) close to said upper surface and housing electronic components (2) , characterized in that it comprises the steps of : producing a blind hole (18 ; 49) in a drill region (15) of said body (1) , said blind hole extending starting from said upper surface (11a) ; forming an insulating region (19' ; ; 47) of electrically insulating material , extending in said drill region (15) laterally to said blind hole (18 ; 49) ; forming a through contact (20) of conductive material filling said blind hole ; forming an electrical connection structure (23 ; 40' ; ) extending on top of said upper surface (11a) between and in electrical contact with said through contact (20) and said electronic component (2) ; removing a lower portion of said body (1) at least as far as a lower wall of said through contact (20) and forming a lower bonding surface (38) ; forming contact region (contact region) s (34) on said lower bonding surface (38) at said through contact (20) . |
| US7977797B2 CLAIM 6 . An integrated circuit of claim 1 wherein said spacer region insulates said contact region (contact region) . |
EP0926726A1 CLAIM 1 A process for fabricating an electronic device formed in a body (1) comprising regions of semiconductor material (4 , 5 , 10) and regions of insulating material (5 , 9 , 11) , said body (1) having an upper surface (11a) and a surface zone (7) close to said upper surface and housing electronic components (2) , characterized in that it comprises the steps of : producing a blind hole (18 ; 49) in a drill region (15) of said body (1) , said blind hole extending starting from said upper surface (11a) ; forming an insulating region (19' ; ; 47) of electrically insulating material , extending in said drill region (15) laterally to said blind hole (18 ; 49) ; forming a through contact (20) of conductive material filling said blind hole ; forming an electrical connection structure (23 ; 40' ; ) extending on top of said upper surface (11a) between and in electrical contact with said through contact (20) and said electronic component (2) ; removing a lower portion of said body (1) at least as far as a lower wall of said through contact (20) and forming a lower bonding surface (38) ; forming contact region (contact region) s (34) on said lower bonding surface (38) at said through contact (20) . |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area of said contact region (contact region) permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
EP0926726A1 CLAIM 1 A process for fabricating an electronic device formed in a body (1) comprising regions of semiconductor material (4 , 5 , 10) and regions of insulating material (5 , 9 , 11) , said body (1) having an upper surface (11a) and a surface zone (7) close to said upper surface and housing electronic components (2) , characterized in that it comprises the steps of : producing a blind hole (18 ; 49) in a drill region (15) of said body (1) , said blind hole extending starting from said upper surface (11a) ; forming an insulating region (19' ; ; 47) of electrically insulating material , extending in said drill region (15) laterally to said blind hole (18 ; 49) ; forming a through contact (20) of conductive material filling said blind hole ; forming an electrical connection structure (23 ; 40' ; ) extending on top of said upper surface (11a) between and in electrical contact with said through contact (20) and said electronic component (2) ; removing a lower portion of said body (1) at least as far as a lower wall of said through contact (20) and forming a lower bonding surface (38) ; forming contact region (contact region) s (34) on said lower bonding surface (38) at said through contact (20) . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub (electronic device) interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
EP0926726A1 CLAIM 1 A process for fabricating an electronic device (second sub) formed in a body (1) comprising regions of semiconductor material (4 , 5 , 10) and regions of insulating material (5 , 9 , 11) , said body (1) having an upper surface (11a) and a surface zone (7) close to said upper surface and housing electronic components (2) , characterized in that it comprises the steps of : producing a blind hole (18 ; 49) in a drill region (15) of said body (1) , said blind hole extending starting from said upper surface (11a) ; forming an insulating region (19' ; ; 47) of electrically insulating material , extending in said drill region (15) laterally to said blind hole (18 ; 49) ; forming a through contact (20) of conductive material filling said blind hole ; forming an electrical connection structure (23 ; 40' ; ) extending on top of said upper surface (11a) between and in electrical contact with said through contact (20) and said electronic component (2) ; removing a lower portion of said body (1) at least as far as a lower wall of said through contact (20) and forming a lower bonding surface (38) ; forming contact regions (34) on said lower bonding surface (38) at said through contact (20) . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space (said sub) in a portion of said first sub interlevel dielectric layer for said contact region (contact region) is in a first range (surface zone) of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub (electronic device) interlevel dielectric layer for said contact region is in a second range (support wafer) of about 0 . 16 μm to 0 . 18 μm wide . |
EP0926726A1 CLAIM 1 A process for fabricating an electronic device (second sub) formed in a body (1) comprising regions of semiconductor material (4 , 5 , 10) and regions of insulating material (5 , 9 , 11) , said body (1) having an upper surface (11a) and a surface zone (first range) (7) close to said upper surface and housing electronic components (2) , characterized in that it comprises the steps of : producing a blind hole (18 ; 49) in a drill region (15) of said body (1) , said blind hole extending starting from said upper surface (11a) ; forming an insulating region (19' ; ; 47) of electrically insulating material , extending in said drill region (15) laterally to said blind hole (18 ; 49) ; forming a through contact (20) of conductive material filling said blind hole ; forming an electrical connection structure (23 ; 40' ; ) extending on top of said upper surface (11a) between and in electrical contact with said through contact (20) and said electronic component (2) ; removing a lower portion of said body (1) at least as far as a lower wall of said through contact (20) and forming a lower bonding surface (38) ; forming contact region (contact region) s (34) on said lower bonding surface (38) at said through contact (20) . EP0926726A1 CLAIM 14 A process according to any one of the preceding Claims , characterized in that the steps of forming a protective layer (25) on top of said body (1) and bonding said protective layer to a support wafer (second range) (30) are carried out before said step of removing a lower portion . EP0926726A1 CLAIM 17 An integrated electronic device (35) for bonding to a motherboard (36) of dimensions much larger than said device , comprising a substrate (3) of semiconductor material housing conductivity regions (4 , 6) ; an insulating and protective layer (11 , 25) above said sub (first space) strate and housing electrical connection structures (23 ; 40' ; ) inside it ; characterized in that it comprises at least one solid through contact (20) extending through said substrate (3) and at least part of said insulating and protective layer (11 , 25) ; said through contact (20) having a first end (21) extending in said insulating and protective layer and in direct electrical contact with at least one electrical connection structure (23 ; 40' ; ) and a second end projecting from said substrate (3) . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
EP0926726A1 CLAIM 1 A process for fabricating an electronic device formed in a body (1) comprising regions of semiconductor material (4 , 5 , 10) and regions of insulating material (5 , 9 , 11) , said body (1) having an upper surface (11a) and a surface zone (7) close to said upper surface and housing electronic components (2) , characterized in that it comprises the steps of : producing a blind hole (18 ; 49) in a drill region (15) of said body (1) , said blind hole extending starting from said upper surface (11a) ; forming an insulating region (19' ; ; 47) of electrically insulating material , extending in said drill region (15) laterally to said blind hole (18 ; 49) ; forming a through contact (20) of conductive material filling said blind hole ; forming an electrical connection structure (23 ; 40' ; ) extending on top of said upper surface (11a) between and in electrical contact with said through contact (20) and said electronic component (2) ; removing a lower portion of said body (1) at least as far as a lower wall of said through contact (20) and forming (anti reflective coating) a lower bonding surface (38) ; forming contact regions (34) on said lower bonding surface (38) at said through contact (20) . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region (contact region) and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub (electronic device) interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
EP0926726A1 CLAIM 1 A process for fabricating an electronic device (second sub) formed in a body (1) comprising regions of semiconductor material (4 , 5 , 10) and regions of insulating material (5 , 9 , 11) , said body (1) having an upper surface (11a) and a surface zone (7) close to said upper surface and housing electronic components (2) , characterized in that it comprises the steps of : producing a blind hole (18 ; 49) in a drill region (15) of said body (1) , said blind hole extending starting from said upper surface (11a) ; forming an insulating region (19' ; ; 47) of electrically insulating material , extending in said drill region (15) laterally to said blind hole (18 ; 49) ; forming a through contact (20) of conductive material filling said blind hole ; forming an electrical connection structure (23 ; 40' ; ) extending on top of said upper surface (11a) between and in electrical contact with said through contact (20) and said electronic component (2) ; removing a lower portion of said body (1) at least as far as a lower wall of said through contact (20) and forming a lower bonding surface (38) ; forming contact region (contact region) s (34) on said lower bonding surface (38) at said through contact (20) . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub (electronic device) interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
EP0926726A1 CLAIM 1 A process for fabricating an electronic device (second sub) formed in a body (1) comprising regions of semiconductor material (4 , 5 , 10) and regions of insulating material (5 , 9 , 11) , said body (1) having an upper surface (11a) and a surface zone (7) close to said upper surface and housing electronic components (2) , characterized in that it comprises the steps of : producing a blind hole (18 ; 49) in a drill region (15) of said body (1) , said blind hole extending starting from said upper surface (11a) ; forming an insulating region (19' ; ; 47) of electrically insulating material , extending in said drill region (15) laterally to said blind hole (18 ; 49) ; forming a through contact (20) of conductive material filling said blind hole ; forming an electrical connection structure (23 ; 40' ; ) extending on top of said upper surface (11a) between and in electrical contact with said through contact (20) and said electronic component (2) ; removing a lower portion of said body (1) at least as far as a lower wall of said through contact (20) and forming a lower bonding surface (38) ; forming contact regions (34) on said lower bonding surface (38) at said through contact (20) . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
EP0926726A1 CLAIM 1 A process for fabricating an electronic device formed in a body (1) comprising regions of semiconductor material (4 , 5 , 10) and regions of insulating material (5 , 9 , 11) , said body (1) having an upper surface (11a) and a surface zone (7) close to said upper surface and housing electronic components (2) , characterized in that it comprises the steps of : producing a blind hole (18 ; 49) in a drill region (15) of said body (1) , said blind hole extending starting from said upper surface (11a) ; forming an insulating region (19' ; ; 47) of electrically insulating material , extending in said drill region (15) laterally to said blind hole (18 ; 49) ; forming a through contact (20) of conductive material filling said blind hole ; forming an electrical connection structure (23 ; 40' ; ) extending on top of said upper surface (11a) between and in electrical contact with said through contact (20) and said electronic component (2) ; removing a lower portion of said body (1) at least as far as a lower wall of said through contact (20) and forming (anti reflective coating) a lower bonding surface (38) ; forming contact regions (34) on said lower bonding surface (38) at said through contact (20) . |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region (contact region) is a first range (surface zone) of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range (support wafer) of about 0 . 16 μm to 0 . 18 μm wide . |
EP0926726A1 CLAIM 1 A process for fabricating an electronic device formed in a body (1) comprising regions of semiconductor material (4 , 5 , 10) and regions of insulating material (5 , 9 , 11) , said body (1) having an upper surface (11a) and a surface zone (first range) (7) close to said upper surface and housing electronic components (2) , characterized in that it comprises the steps of : producing a blind hole (18 ; 49) in a drill region (15) of said body (1) , said blind hole extending starting from said upper surface (11a) ; forming an insulating region (19' ; ; 47) of electrically insulating material , extending in said drill region (15) laterally to said blind hole (18 ; 49) ; forming a through contact (20) of conductive material filling said blind hole ; forming an electrical connection structure (23 ; 40' ; ) extending on top of said upper surface (11a) between and in electrical contact with said through contact (20) and said electronic component (2) ; removing a lower portion of said body (1) at least as far as a lower wall of said through contact (20) and forming a lower bonding surface (38) ; forming contact region (contact region) s (34) on said lower bonding surface (38) at said through contact (20) . EP0926726A1 CLAIM 14 A process according to any one of the preceding Claims , characterized in that the steps of forming a protective layer (25) on top of said body (1) and bonding said protective layer to a support wafer (second range) (30) are carried out before said step of removing a lower portion . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | EP0847081A1 Filed: 1997-12-09 Issued: 1998-06-10 Improvements in or relating to semiconductor devices (Original Assignee) Texas Instruments Inc (Current Assignee) Texas Instruments Inc Takayuki Niuya, (Nmi) |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region (second contact) coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch (local interconnect) stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (local interconnect) layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
EP0847081A1 CLAIM 8 A method for forming a local interconnect (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) between a first current guiding region and a second current guiding region separated by a field oxide , the method comprising : forming a first contact gate at least partially overlying the field oxide adjacent the first current guiding region ; forming a second contact (contact region) gate at least partially overlying the field oxide adjacent to the second current guiding region ; forming a polysilicon layer overlying the first contact gate , the second contact gate , the first current guiding region , and the second current guiding region ; and forming a conductive layer overlying the polysilicon layer . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch (local interconnect) stop layer protects removal of a substrate material by an etch process . |
EP0847081A1 CLAIM 8 A method for forming a local interconnect (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) between a first current guiding region and a second current guiding region separated by a field oxide , the method comprising : forming a first contact gate at least partially overlying the field oxide adjacent the first current guiding region ; forming a second contact gate at least partially overlying the field oxide adjacent to the second current guiding region ; forming a polysilicon layer overlying the first contact gate , the second contact gate , the first current guiding region , and the second current guiding region ; and forming a conductive layer overlying the polysilicon layer . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (local interconnect) layer insulates said contact region (second contact) . |
EP0847081A1 CLAIM 8 A method for forming a local interconnect (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) between a first current guiding region and a second current guiding region separated by a field oxide , the method comprising : forming a first contact gate at least partially overlying the field oxide adjacent the first current guiding region ; forming a second contact (contact region) gate at least partially overlying the field oxide adjacent to the second current guiding region ; forming a polysilicon layer overlying the first contact gate , the second contact gate , the first current guiding region , and the second current guiding region ; and forming a conductive layer overlying the polysilicon layer . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch stop layer protects lower layers during an etching process (doped polysilicon) . |
EP0847081A1 CLAIM 5 The method of Claim 1 or Claim 2 , wherein the step of forming the polysilicon layer comprises : forming a non-doped polysilicon (etching process) layer overlying the contact gate and the current guiding region ; and doping the non-doped polysilicon layer to form the polysilicon layer . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (local interconnect) layer insulates said contact region (second contact) . |
EP0847081A1 CLAIM 8 A method for forming a local interconnect (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) between a first current guiding region and a second current guiding region separated by a field oxide , the method comprising : forming a first contact gate at least partially overlying the field oxide adjacent the first current guiding region ; forming a second contact (contact region) gate at least partially overlying the field oxide adjacent to the second current guiding region ; forming a polysilicon layer overlying the first contact gate , the second contact gate , the first current guiding region , and the second current guiding region ; and forming a conductive layer overlying the polysilicon layer . |
| US7977797B2 CLAIM 6 . An integrated circuit of claim 1 wherein said spacer region insulates said contact region (second contact) . |
EP0847081A1 CLAIM 8 A method for forming a local interconnect between a first current guiding region and a second current guiding region separated by a field oxide , the method comprising : forming a first contact gate at least partially overlying the field oxide adjacent the first current guiding region ; forming a second contact (contact region) gate at least partially overlying the field oxide adjacent to the second current guiding region ; forming a polysilicon layer overlying the first contact gate , the second contact gate , the first current guiding region , and the second current guiding region ; and forming a conductive layer overlying the polysilicon layer . |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area of said contact region (second contact) permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
EP0847081A1 CLAIM 8 A method for forming a local interconnect between a first current guiding region and a second current guiding region separated by a field oxide , the method comprising : forming a first contact gate at least partially overlying the field oxide adjacent the first current guiding region ; forming a second contact (contact region) gate at least partially overlying the field oxide adjacent to the second current guiding region ; forming a polysilicon layer overlying the first contact gate , the second contact gate , the first current guiding region , and the second current guiding region ; and forming a conductive layer overlying the polysilicon layer . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch (local interconnect) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (local interconnect) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
EP0847081A1 CLAIM 8 A method for forming a local interconnect (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) between a first current guiding region and a second current guiding region separated by a field oxide , the method comprising : forming a first contact gate at least partially overlying the field oxide adjacent the first current guiding region ; forming a second contact gate at least partially overlying the field oxide adjacent to the second current guiding region ; forming a polysilicon layer overlying the first contact gate , the second contact gate , the first current guiding region , and the second current guiding region ; and forming a conductive layer overlying the polysilicon layer . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric (local interconnect) layer for said contact region (second contact) is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
EP0847081A1 CLAIM 8 A method for forming a local interconnect (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) between a first current guiding region and a second current guiding region separated by a field oxide , the method comprising : forming a first contact gate at least partially overlying the field oxide adjacent the first current guiding region ; forming a second contact (contact region) gate at least partially overlying the field oxide adjacent to the second current guiding region ; forming a polysilicon layer overlying the first contact gate , the second contact gate , the first current guiding region , and the second current guiding region ; and forming a conductive layer overlying the polysilicon layer . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
EP0847081A1 CLAIM 1 A method for forming a contact to a current guiding region adjacent a field oxide , the method comprising : forming a contact gate at least partially overlying the field oxide ; forming a polysilicon layer substantially overlying the contact gate and the current guiding region ; and forming (anti reflective coating) a conductive layer substantially overlying the polysilicon layer . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch (local interconnect) stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region (second contact) and under a first sub interlevel dielectric (local interconnect) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
EP0847081A1 CLAIM 8 A method for forming a local interconnect (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) between a first current guiding region and a second current guiding region separated by a field oxide , the method comprising : forming a first contact gate at least partially overlying the field oxide adjacent the first current guiding region ; forming a second contact (contact region) gate at least partially overlying the field oxide adjacent to the second current guiding region ; forming a polysilicon layer overlying the first contact gate , the second contact gate , the first current guiding region , and the second current guiding region ; and forming a conductive layer overlying the polysilicon layer . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch (local interconnect) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (local interconnect) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
EP0847081A1 CLAIM 8 A method for forming a local interconnect (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) between a first current guiding region and a second current guiding region separated by a field oxide , the method comprising : forming a first contact gate at least partially overlying the field oxide adjacent the first current guiding region ; forming a second contact gate at least partially overlying the field oxide adjacent to the second current guiding region ; forming a polysilicon layer overlying the first contact gate , the second contact gate , the first current guiding region , and the second current guiding region ; and forming a conductive layer overlying the polysilicon layer . |
| US7977797B2 CLAIM 13 . An integrated circuit of claim 11 further comprising a floating gate (drain region) . |
EP0847081A1 CLAIM 13 The method of Claim 8 or Claim 9 , wherein the step of forming a polysilicon layer comprises : forming a non-doped polysilicon layer substantially overlying the first contact gate , the second contact gate , the first current guiding region , and the second current guiding region ; masking the second contact gate and the second source/drain region (floating gate) ; doping the non-doped polysilicon layer overlying the first contact gate and the first source/drain region with a first dopant species ; masking the first contact gate and the first current guiding region ; doping the non-doped polysilicon layer overlying the second contact gate and the second current guiding region with a second dopant species . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
EP0847081A1 CLAIM 1 A method for forming a contact to a current guiding region adjacent a field oxide , the method comprising : forming a contact gate at least partially overlying the field oxide ; forming a polysilicon layer substantially overlying the contact gate and the current guiding region ; and forming (anti reflective coating) a conductive layer substantially overlying the polysilicon layer . |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region (second contact) is a first range of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
EP0847081A1 CLAIM 8 A method for forming a local interconnect between a first current guiding region and a second current guiding region separated by a field oxide , the method comprising : forming a first contact gate at least partially overlying the field oxide adjacent the first current guiding region ; forming a second contact (contact region) gate at least partially overlying the field oxide adjacent to the second current guiding region ; forming a polysilicon layer overlying the first contact gate , the second contact gate , the first current guiding region , and the second current guiding region ; and forming a conductive layer overlying the polysilicon layer . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5953609A Filed: 1997-10-31 Issued: 1999-09-14 Method of manufacturing a semiconductor memory device (Original Assignee) NEC Corp (Current Assignee) NEC Electronics Corp Kuniaki Koyama, John Mark Drynan |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region (said element) coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area (second conductive layer) of said contact region is smaller than a metal layer coupling area (conductive oxide) of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch (gate oxide) stop layer (zirconium nitride) over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5953609A CLAIM 1 . A method of manufacturing a semiconductor memory device in which a memory cell is composed of a capacitor and a transistor , said method comprising the steps of : forming an impurity region for said transistor in a semiconductor substrate ; forming an insulating layer on said semiconductor substrate , said insulating layer having a contact hole for exposing a part of said impurity region ; forming a first conductive layer at least in a part of a surface of said insulating layer ; forming a first capacitive insulating film on said first conductive layer ; forming a second conductive layer (substrate coupling area) , which contacts with a part of said impurity region via said contact hole and faces said first conductive layer via said first capacitive insulating film ; selectively forming a second capacitive insulating film , which contact with said first capacitive insulating film and covers a surface of said second conductive layer ; and forming a third conductive layer , which electrically connects with said first conductive layer at an uncovered first and second capacitive insulating films and covers said second capacitive insulating film , wherein said first and third conductive layer , said first and second capacitive insulating films and said second conductive layer respectively constitute a first electrode , a capacitive insulating film and a second electrode of said capacitor . US5953609A CLAIM 7 . A manufacturing method of a semiconductor memory device according to claim 4 , wherein said first and second nitride metal films are films selected from any one of a titanium nitride film (TiN) , a tantalum nitride film (TaN) , a zirconium nitride (second etch stop layer) film (ZrN) , and a niobium nitride film (NbN) . US5953609A CLAIM 9 . A manufacturing method of a semiconductor memory device according to claim 7 , wherein formation of said first conductive film is composed of forming of a barrier film and forming of one metal film selected from a ruthenium (Ru) film , an iridium (Ir) film , a rhodium (Rh) film , a rhenium (Re) film or an osmium (Os) film , a conductive oxide (metal layer coupling area) of said metal film is formed at least in an upper surface of said contact plug , which fills said lower node contact hole , and at least second , third and fifth conductive films are formed by N type silicon films . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch (gate oxide) stop layer (zirconium nitride) protects lower layers during an etching process . |
US5953609A CLAIM 7 . A manufacturing method of a semiconductor memory device according to claim 4 , wherein said first and second nitride metal films are films selected from any one of a titanium nitride film (TiN) , a tantalum nitride film (TaN) , a zirconium nitride (second etch stop layer) film (ZrN) , and a niobium nitride film (NbN) . |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area (second conductive layer) of said contact region (said element) permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area (conductive oxide) of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
US5953609A CLAIM 1 . A method of manufacturing a semiconductor memory device in which a memory cell is composed of a capacitor and a transistor , said method comprising the steps of : forming an impurity region for said transistor in a semiconductor substrate ; forming an insulating layer on said semiconductor substrate , said insulating layer having a contact hole for exposing a part of said impurity region ; forming a first conductive layer at least in a part of a surface of said insulating layer ; forming a first capacitive insulating film on said first conductive layer ; forming a second conductive layer (substrate coupling area) , which contacts with a part of said impurity region via said contact hole and faces said first conductive layer via said first capacitive insulating film ; selectively forming a second capacitive insulating film , which contact with said first capacitive insulating film and covers a surface of said second conductive layer ; and forming a third conductive layer , which electrically connects with said first conductive layer at an uncovered first and second capacitive insulating films and covers said second capacitive insulating film , wherein said first and third conductive layer , said first and second capacitive insulating films and said second conductive layer respectively constitute a first electrode , a capacitive insulating film and a second electrode of said capacitor . US5953609A CLAIM 9 . A manufacturing method of a semiconductor memory device according to claim 7 , wherein formation of said first conductive film is composed of forming of a barrier film and forming of one metal film selected from a ruthenium (Ru) film , an iridium (Ir) film , a rhodium (Rh) film , a rhenium (Re) film or an osmium (Os) film , a conductive oxide (metal layer coupling area) of said metal film is formed at least in an upper surface of said contact plug , which fills said lower node contact hole , and at least second , third and fifth conductive films are formed by N type silicon films . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (gate oxide) stop layer (zirconium nitride) is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5953609A CLAIM 7 . A manufacturing method of a semiconductor memory device according to claim 4 , wherein said first and second nitride metal films are films selected from any one of a titanium nitride film (TiN) , a tantalum nitride film (TaN) , a zirconium nitride (second etch stop layer) film (ZrN) , and a niobium nitride film (NbN) . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch (gate oxide) stop layer (zirconium nitride) wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region (said element) and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area (second conductive layer) of said contact region is smaller than a metal layer coupling area (conductive oxide) of said contact region . |
US5953609A CLAIM 1 . A method of manufacturing a semiconductor memory device in which a memory cell is composed of a capacitor and a transistor , said method comprising the steps of : forming an impurity region for said transistor in a semiconductor substrate ; forming an insulating layer on said semiconductor substrate , said insulating layer having a contact hole for exposing a part of said impurity region ; forming a first conductive layer at least in a part of a surface of said insulating layer ; forming a first capacitive insulating film on said first conductive layer ; forming a second conductive layer (substrate coupling area) , which contacts with a part of said impurity region via said contact hole and faces said first conductive layer via said first capacitive insulating film ; selectively forming a second capacitive insulating film , which contact with said first capacitive insulating film and covers a surface of said second conductive layer ; and forming a third conductive layer , which electrically connects with said first conductive layer at an uncovered first and second capacitive insulating films and covers said second capacitive insulating film , wherein said first and third conductive layer , said first and second capacitive insulating films and said second conductive layer respectively constitute a first electrode , a capacitive insulating film and a second electrode of said capacitor . US5953609A CLAIM 7 . A manufacturing method of a semiconductor memory device according to claim 4 , wherein said first and second nitride metal films are films selected from any one of a titanium nitride film (TiN) , a tantalum nitride film (TaN) , a zirconium nitride (second etch stop layer) film (ZrN) , and a niobium nitride film (NbN) . US5953609A CLAIM 9 . A manufacturing method of a semiconductor memory device according to claim 7 , wherein formation of said first conductive film is composed of forming of a barrier film and forming of one metal film selected from a ruthenium (Ru) film , an iridium (Ir) film , a rhodium (Rh) film , a rhenium (Re) film or an osmium (Os) film , a conductive oxide (metal layer coupling area) of said metal film is formed at least in an upper surface of said contact plug , which fills said lower node contact hole , and at least second , third and fifth conductive films are formed by N type silicon films . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (gate oxide) stop layer (zirconium nitride) is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5953609A CLAIM 7 . A manufacturing method of a semiconductor memory device according to claim 4 , wherein said first and second nitride metal films are films selected from any one of a titanium nitride film (TiN) , a tantalum nitride film (TaN) , a zirconium nitride (second etch stop layer) film (ZrN) , and a niobium nitride film (NbN) . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US6740584B2 Filed: 1997-09-23 Issued: 2004-05-25 Semiconductor device and method of fabricating the same (Original Assignee) Mitsubishi Electric Corp (Current Assignee) Renesas Electronics Corp Takahisa Eimori |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch (etching rate) stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (interlayer insulating film, contact hole) layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US6740584B2 CLAIM 1 . A semiconductor device fabricating method comprising : a first step of forming a plurality of conductive elements on a surface of a semiconductor base layer having a thin insulating film thereon , upper surfaces (first sub, first sub interlevel dielectric layer) and side surfaces of said conductive elements being covered with a silicon oxide film ; a second step of forming an etching resistant film on the surface of said semiconductor base layer and the side surfaces of said conductive elements ; a third step of forming an interlayer insulating film (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer, second sub interlevel dielectric layer) so as to cover said etching resistant film , the interlayer insulating film comprising a lower interlayer contiguous with an upper interlayer , the lower interlayer having a higher etching rate (first etch, etch process) than the upper interlayer ; a fourth step of forming a hole in said interlayer insulating film , reaching at least to said etching resistant film between said plurality of conductive elements ; a fifth step of extending said hole by removing said etching resistant film to reach said semiconductor base layer for forming a contact hole (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer, second sub interlevel dielectric layer) to said semiconductor base layer ; and a sixth step of expanding a bottom portion of the hole in a lateral direction by isotropic etching . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch (etching rate) stop layer protects removal of a substrate material (silicon oxide) by an etch process (etching rate) . |
US6740584B2 CLAIM 1 . A semiconductor device fabricating method comprising : a first step of forming a plurality of conductive elements on a surface of a semiconductor base layer having a thin insulating film thereon , upper surfaces and side surfaces of said conductive elements being covered with a silicon oxide (substrate material) film ; a second step of forming an etching resistant film on the surface of said semiconductor base layer and the side surfaces of said conductive elements ; a third step of forming an interlayer insulating film so as to cover said etching resistant film , the interlayer insulating film comprising a lower interlayer contiguous with an upper interlayer , the lower interlayer having a higher etching rate (first etch, etch process) than the upper interlayer ; a fourth step of forming a hole in said interlayer insulating film , reaching at least to said etching resistant film between said plurality of conductive elements ; a fifth step of extending said hole by removing said etching resistant film to reach said semiconductor base layer for forming a contact hole to said semiconductor base layer ; and a sixth step of expanding a bottom portion of the hole in a lateral direction by isotropic etching . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (interlayer insulating film, contact hole) layer insulates said contact region . |
US6740584B2 CLAIM 1 . A semiconductor device fabricating method comprising : a first step of forming a plurality of conductive elements on a surface of a semiconductor base layer having a thin insulating film thereon , upper surfaces (first sub, first sub interlevel dielectric layer) and side surfaces of said conductive elements being covered with a silicon oxide film ; a second step of forming an etching resistant film on the surface of said semiconductor base layer and the side surfaces of said conductive elements ; a third step of forming an interlayer insulating film (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer, second sub interlevel dielectric layer) so as to cover said etching resistant film , the interlayer insulating film comprising a lower interlayer contiguous with an upper interlayer , the lower interlayer having a higher etching rate than the upper interlayer ; a fourth step of forming a hole in said interlayer insulating film , reaching at least to said etching resistant film between said plurality of conductive elements ; a fifth step of extending said hole by removing said etching resistant film to reach said semiconductor base layer for forming a contact hole (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer, second sub interlevel dielectric layer) to said semiconductor base layer ; and a sixth step of expanding a bottom portion of the hole in a lateral direction by isotropic etching . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (interlayer insulating film, contact hole) layer insulates said contact region . |
US6740584B2 CLAIM 1 . A semiconductor device fabricating method comprising : a first step of forming a plurality of conductive elements on a surface of a semiconductor base layer having a thin insulating film thereon , upper surfaces and side surfaces of said conductive elements being covered with a silicon oxide film ; a second step of forming an etching resistant film on the surface of said semiconductor base layer and the side surfaces of said conductive elements ; a third step of forming an interlayer insulating film (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer, second sub interlevel dielectric layer) so as to cover said etching resistant film , the interlayer insulating film comprising a lower interlayer contiguous with an upper interlayer , the lower interlayer having a higher etching rate than the upper interlayer ; a fourth step of forming a hole in said interlayer insulating film , reaching at least to said etching resistant film between said plurality of conductive elements ; a fifth step of extending said hole by removing said etching resistant film to reach said semiconductor base layer for forming a contact hole (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer, second sub interlevel dielectric layer) to said semiconductor base layer ; and a sixth step of expanding a bottom portion of the hole in a lateral direction by isotropic etching . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch (etching rate) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (interlayer insulating film, contact hole) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6740584B2 CLAIM 1 . A semiconductor device fabricating method comprising : a first step of forming a plurality of conductive elements on a surface of a semiconductor base layer having a thin insulating film thereon , upper surfaces (first sub, first sub interlevel dielectric layer) and side surfaces of said conductive elements being covered with a silicon oxide film ; a second step of forming an etching resistant film on the surface of said semiconductor base layer and the side surfaces of said conductive elements ; a third step of forming an interlayer insulating film (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer, second sub interlevel dielectric layer) so as to cover said etching resistant film , the interlayer insulating film comprising a lower interlayer contiguous with an upper interlayer , the lower interlayer having a higher etching rate (first etch, etch process) than the upper interlayer ; a fourth step of forming a hole in said interlayer insulating film , reaching at least to said etching resistant film between said plurality of conductive elements ; a fifth step of extending said hole by removing said etching resistant film to reach said semiconductor base layer for forming a contact hole (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer, second sub interlevel dielectric layer) to said semiconductor base layer ; and a sixth step of expanding a bottom portion of the hole in a lateral direction by isotropic etching . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric (interlayer insulating film, contact hole) layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US6740584B2 CLAIM 1 . A semiconductor device fabricating method comprising : a first step of forming a plurality of conductive elements on a surface of a semiconductor base layer having a thin insulating film thereon , upper surfaces (first sub, first sub interlevel dielectric layer) and side surfaces of said conductive elements being covered with a silicon oxide film ; a second step of forming an etching resistant film on the surface of said semiconductor base layer and the side surfaces of said conductive elements ; a third step of forming an interlayer insulating film (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer, second sub interlevel dielectric layer) so as to cover said etching resistant film , the interlayer insulating film comprising a lower interlayer contiguous with an upper interlayer , the lower interlayer having a higher etching rate than the upper interlayer ; a fourth step of forming a hole in said interlayer insulating film , reaching at least to said etching resistant film between said plurality of conductive elements ; a fifth step of extending said hole by removing said etching resistant film to reach said semiconductor base layer for forming a contact hole (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer, second sub interlevel dielectric layer) to said semiconductor base layer ; and a sixth step of expanding a bottom portion of the hole in a lateral direction by isotropic etching . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch (etching rate) stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (interlayer insulating film, contact hole) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US6740584B2 CLAIM 1 . A semiconductor device fabricating method comprising : a first step of forming a plurality of conductive elements on a surface of a semiconductor base layer having a thin insulating film thereon , upper surfaces (first sub, first sub interlevel dielectric layer) and side surfaces of said conductive elements being covered with a silicon oxide film ; a second step of forming an etching resistant film on the surface of said semiconductor base layer and the side surfaces of said conductive elements ; a third step of forming an interlayer insulating film (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer, second sub interlevel dielectric layer) so as to cover said etching resistant film , the interlayer insulating film comprising a lower interlayer contiguous with an upper interlayer , the lower interlayer having a higher etching rate (first etch, etch process) than the upper interlayer ; a fourth step of forming a hole in said interlayer insulating film , reaching at least to said etching resistant film between said plurality of conductive elements ; a fifth step of extending said hole by removing said etching resistant film to reach said semiconductor base layer for forming a contact hole (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer, second sub interlevel dielectric layer) to said semiconductor base layer ; and a sixth step of expanding a bottom portion of the hole in a lateral direction by isotropic etching . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch (etching rate) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (interlayer insulating film, contact hole) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6740584B2 CLAIM 1 . A semiconductor device fabricating method comprising : a first step of forming a plurality of conductive elements on a surface of a semiconductor base layer having a thin insulating film thereon , upper surfaces (first sub, first sub interlevel dielectric layer) and side surfaces of said conductive elements being covered with a silicon oxide film ; a second step of forming an etching resistant film on the surface of said semiconductor base layer and the side surfaces of said conductive elements ; a third step of forming an interlayer insulating film (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer, second sub interlevel dielectric layer) so as to cover said etching resistant film , the interlayer insulating film comprising a lower interlayer contiguous with an upper interlayer , the lower interlayer having a higher etching rate (first etch, etch process) than the upper interlayer ; a fourth step of forming a hole in said interlayer insulating film , reaching at least to said etching resistant film between said plurality of conductive elements ; a fifth step of extending said hole by removing said etching resistant film to reach said semiconductor base layer for forming a contact hole (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer, second sub interlevel dielectric layer) to said semiconductor base layer ; and a sixth step of expanding a bottom portion of the hole in a lateral direction by isotropic etching . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5989952A Filed: 1997-09-22 Issued: 1999-11-23 Method for fabricating a crown-type capacitor of a DRAM cell (Original Assignee) Nanya Technology Corp (Current Assignee) Nanya Technology Corp Tean-Sen Jen, Shiou-Yu Wang, Jia-Shyong Cheng, Chi-Hui Lin |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region (contact region) coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5989952A CLAIM 1 . A method for fabricating a DRAM cell with a crown-type capacitor over a semiconductor substrate , comprising the steps of : (a) forming a transistor including a gate , a drain and a source over the semiconductor substrate ; (b) forming an insulating layer over the transistor ; (c) selectively etching the insulating layer to form a contact opening in which either the source or the drain of the transistor is exposed as a contact region (contact region) ; (d) forming a first conducting layer over the insulating layer and filling into the contact opening to electrically connect the contact region ; (e) successively forming an etching stop layer and a mask layer over the first conducting layer , wherein the etching stop layer and the first conducting layer consist of different materials ; (f) patterning the mask layer to form a plurality of openings in which regions for separating different memory cells are exposed ; (g) forming a dielectric spacer on the sidewall of the mask layer , and removing exposed portions of the etching stop layer ; (h) anisotropically etching the mask layer and the first conducting layer by using the dielectric spacer as a mask , to expose , respectively , the etching stop layer and the insulating layer , for defining a capacitor region ; (i) removing the uncovered etching stop layer to expose the first conducting layer ; (j) anisotropically etching the first conducting layer to a predetermined depth by using the dielectric spacer as a mask , thereby forming a crown-type storage electrode ; (k) removing the dielectric spacer and the etching stop layer ; (l) forming a dielectric layer over exposed portions of the storage electrode ; and (m) forming a second conducting layer as an opposite electrode over the dielectric layer . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric layer insulates said contact region (contact region) . |
US5989952A CLAIM 1 . A method for fabricating a DRAM cell with a crown-type capacitor over a semiconductor substrate , comprising the steps of : (a) forming a transistor including a gate , a drain and a source over the semiconductor substrate ; (b) forming an insulating layer over the transistor ; (c) selectively etching the insulating layer to form a contact opening in which either the source or the drain of the transistor is exposed as a contact region (contact region) ; (d) forming a first conducting layer over the insulating layer and filling into the contact opening to electrically connect the contact region ; (e) successively forming an etching stop layer and a mask layer over the first conducting layer , wherein the etching stop layer and the first conducting layer consist of different materials ; (f) patterning the mask layer to form a plurality of openings in which regions for separating different memory cells are exposed ; (g) forming a dielectric spacer on the sidewall of the mask layer , and removing exposed portions of the etching stop layer ; (h) anisotropically etching the mask layer and the first conducting layer by using the dielectric spacer as a mask , to expose , respectively , the etching stop layer and the insulating layer , for defining a capacitor region ; (i) removing the uncovered etching stop layer to expose the first conducting layer ; (j) anisotropically etching the first conducting layer to a predetermined depth by using the dielectric spacer as a mask , thereby forming a crown-type storage electrode ; (k) removing the dielectric spacer and the etching stop layer ; (l) forming a dielectric layer over exposed portions of the storage electrode ; and (m) forming a second conducting layer as an opposite electrode over the dielectric layer . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch stop layer protects lower layers during an etching process (capacitor region) . |
US5989952A CLAIM 1 . A method for fabricating a DRAM cell with a crown-type capacitor over a semiconductor substrate , comprising the steps of : (a) forming a transistor including a gate , a drain and a source over the semiconductor substrate ; (b) forming an insulating layer over the transistor ; (c) selectively etching the insulating layer to form a contact opening in which either the source or the drain of the transistor is exposed as a contact region ; (d) forming a first conducting layer over the insulating layer and filling into the contact opening to electrically connect the contact region ; (e) successively forming an etching stop layer and a mask layer over the first conducting layer , wherein the etching stop layer and the first conducting layer consist of different materials ; (f) patterning the mask layer to form a plurality of openings in which regions for separating different memory cells are exposed ; (g) forming a dielectric spacer on the sidewall of the mask layer , and removing exposed portions of the etching stop layer ; (h) anisotropically etching the mask layer and the first conducting layer by using the dielectric spacer as a mask , to expose , respectively , the etching stop layer and the insulating layer , for defining a capacitor region (etching process) ; (i) removing the uncovered etching stop layer to expose the first conducting layer ; (j) anisotropically etching the first conducting layer to a predetermined depth by using the dielectric spacer as a mask , thereby forming a crown-type storage electrode ; (k) removing the dielectric spacer and the etching stop layer ; (l) forming a dielectric layer over exposed portions of the storage electrode ; and (m) forming a second conducting layer as an opposite electrode over the dielectric layer . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric layer insulates said contact region (contact region) . |
US5989952A CLAIM 1 . A method for fabricating a DRAM cell with a crown-type capacitor over a semiconductor substrate , comprising the steps of : (a) forming a transistor including a gate , a drain and a source over the semiconductor substrate ; (b) forming an insulating layer over the transistor ; (c) selectively etching the insulating layer to form a contact opening in which either the source or the drain of the transistor is exposed as a contact region (contact region) ; (d) forming a first conducting layer over the insulating layer and filling into the contact opening to electrically connect the contact region ; (e) successively forming an etching stop layer and a mask layer over the first conducting layer , wherein the etching stop layer and the first conducting layer consist of different materials ; (f) patterning the mask layer to form a plurality of openings in which regions for separating different memory cells are exposed ; (g) forming a dielectric spacer on the sidewall of the mask layer , and removing exposed portions of the etching stop layer ; (h) anisotropically etching the mask layer and the first conducting layer by using the dielectric spacer as a mask , to expose , respectively , the etching stop layer and the insulating layer , for defining a capacitor region ; (i) removing the uncovered etching stop layer to expose the first conducting layer ; (j) anisotropically etching the first conducting layer to a predetermined depth by using the dielectric spacer as a mask , thereby forming a crown-type storage electrode ; (k) removing the dielectric spacer and the etching stop layer ; (l) forming a dielectric layer over exposed portions of the storage electrode ; and (m) forming a second conducting layer as an opposite electrode over the dielectric layer . |
| US7977797B2 CLAIM 6 . An integrated circuit of claim 1 wherein said spacer region insulates said contact region (contact region) . |
US5989952A CLAIM 1 . A method for fabricating a DRAM cell with a crown-type capacitor over a semiconductor substrate , comprising the steps of : (a) forming a transistor including a gate , a drain and a source over the semiconductor substrate ; (b) forming an insulating layer over the transistor ; (c) selectively etching the insulating layer to form a contact opening in which either the source or the drain of the transistor is exposed as a contact region (contact region) ; (d) forming a first conducting layer over the insulating layer and filling into the contact opening to electrically connect the contact region ; (e) successively forming an etching stop layer and a mask layer over the first conducting layer , wherein the etching stop layer and the first conducting layer consist of different materials ; (f) patterning the mask layer to form a plurality of openings in which regions for separating different memory cells are exposed ; (g) forming a dielectric spacer on the sidewall of the mask layer , and removing exposed portions of the etching stop layer ; (h) anisotropically etching the mask layer and the first conducting layer by using the dielectric spacer as a mask , to expose , respectively , the etching stop layer and the insulating layer , for defining a capacitor region ; (i) removing the uncovered etching stop layer to expose the first conducting layer ; (j) anisotropically etching the first conducting layer to a predetermined depth by using the dielectric spacer as a mask , thereby forming a crown-type storage electrode ; (k) removing the dielectric spacer and the etching stop layer ; (l) forming a dielectric layer over exposed portions of the storage electrode ; and (m) forming a second conducting layer as an opposite electrode over the dielectric layer . |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area of said contact region (contact region) permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
US5989952A CLAIM 1 . A method for fabricating a DRAM cell with a crown-type capacitor over a semiconductor substrate , comprising the steps of : (a) forming a transistor including a gate , a drain and a source over the semiconductor substrate ; (b) forming an insulating layer over the transistor ; (c) selectively etching the insulating layer to form a contact opening in which either the source or the drain of the transistor is exposed as a contact region (contact region) ; (d) forming a first conducting layer over the insulating layer and filling into the contact opening to electrically connect the contact region ; (e) successively forming an etching stop layer and a mask layer over the first conducting layer , wherein the etching stop layer and the first conducting layer consist of different materials ; (f) patterning the mask layer to form a plurality of openings in which regions for separating different memory cells are exposed ; (g) forming a dielectric spacer on the sidewall of the mask layer , and removing exposed portions of the etching stop layer ; (h) anisotropically etching the mask layer and the first conducting layer by using the dielectric spacer as a mask , to expose , respectively , the etching stop layer and the insulating layer , for defining a capacitor region ; (i) removing the uncovered etching stop layer to expose the first conducting layer ; (j) anisotropically etching the first conducting layer to a predetermined depth by using the dielectric spacer as a mask , thereby forming a crown-type storage electrode ; (k) removing the dielectric spacer and the etching stop layer ; (l) forming a dielectric layer over exposed portions of the storage electrode ; and (m) forming a second conducting layer as an opposite electrode over the dielectric layer . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric layer for said contact region (contact region) is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5989952A CLAIM 1 . A method for fabricating a DRAM cell with a crown-type capacitor over a semiconductor substrate , comprising the steps of : (a) forming a transistor including a gate , a drain and a source over the semiconductor substrate ; (b) forming an insulating layer over the transistor ; (c) selectively etching the insulating layer to form a contact opening in which either the source or the drain of the transistor is exposed as a contact region (contact region) ; (d) forming a first conducting layer over the insulating layer and filling into the contact opening to electrically connect the contact region ; (e) successively forming an etching stop layer and a mask layer over the first conducting layer , wherein the etching stop layer and the first conducting layer consist of different materials ; (f) patterning the mask layer to form a plurality of openings in which regions for separating different memory cells are exposed ; (g) forming a dielectric spacer on the sidewall of the mask layer , and removing exposed portions of the etching stop layer ; (h) anisotropically etching the mask layer and the first conducting layer by using the dielectric spacer as a mask , to expose , respectively , the etching stop layer and the insulating layer , for defining a capacitor region ; (i) removing the uncovered etching stop layer to expose the first conducting layer ; (j) anisotropically etching the first conducting layer to a predetermined depth by using the dielectric spacer as a mask , thereby forming a crown-type storage electrode ; (k) removing the dielectric spacer and the etching stop layer ; (l) forming a dielectric layer over exposed portions of the storage electrode ; and (m) forming a second conducting layer as an opposite electrode over the dielectric layer . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers (silicon nitride layer) have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region (contact region) and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US5989952A CLAIM 1 . A method for fabricating a DRAM cell with a crown-type capacitor over a semiconductor substrate , comprising the steps of : (a) forming a transistor including a gate , a drain and a source over the semiconductor substrate ; (b) forming an insulating layer over the transistor ; (c) selectively etching the insulating layer to form a contact opening in which either the source or the drain of the transistor is exposed as a contact region (contact region) ; (d) forming a first conducting layer over the insulating layer and filling into the contact opening to electrically connect the contact region ; (e) successively forming an etching stop layer and a mask layer over the first conducting layer , wherein the etching stop layer and the first conducting layer consist of different materials ; (f) patterning the mask layer to form a plurality of openings in which regions for separating different memory cells are exposed ; (g) forming a dielectric spacer on the sidewall of the mask layer , and removing exposed portions of the etching stop layer ; (h) anisotropically etching the mask layer and the first conducting layer by using the dielectric spacer as a mask , to expose , respectively , the etching stop layer and the insulating layer , for defining a capacitor region ; (i) removing the uncovered etching stop layer to expose the first conducting layer ; (j) anisotropically etching the first conducting layer to a predetermined depth by using the dielectric spacer as a mask , thereby forming a crown-type storage electrode ; (k) removing the dielectric spacer and the etching stop layer ; (l) forming a dielectric layer over exposed portions of the storage electrode ; and (m) forming a second conducting layer as an opposite electrode over the dielectric layer . US5989952A CLAIM 5 . The method as claimed in claim 1 , wherein the dielectric spacer includes a silicon dioxide layer , a silicon nitride layer (second etch stop layers) or an oxynitride layer . |
| US7977797B2 CLAIM 13 . An integrated circuit of claim 11 further comprising a floating gate (amorphous silicon layer) . |
US5989952A CLAIM 4 . The method as claimed in claim 1 , wherein the mask layer is a polysilicon layer or an amorphous silicon layer (floating gate) . |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region (contact region) is a first range of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5989952A CLAIM 1 . A method for fabricating a DRAM cell with a crown-type capacitor over a semiconductor substrate , comprising the steps of : (a) forming a transistor including a gate , a drain and a source over the semiconductor substrate ; (b) forming an insulating layer over the transistor ; (c) selectively etching the insulating layer to form a contact opening in which either the source or the drain of the transistor is exposed as a contact region (contact region) ; (d) forming a first conducting layer over the insulating layer and filling into the contact opening to electrically connect the contact region ; (e) successively forming an etching stop layer and a mask layer over the first conducting layer , wherein the etching stop layer and the first conducting layer consist of different materials ; (f) patterning the mask layer to form a plurality of openings in which regions for separating different memory cells are exposed ; (g) forming a dielectric spacer on the sidewall of the mask layer , and removing exposed portions of the etching stop layer ; (h) anisotropically etching the mask layer and the first conducting layer by using the dielectric spacer as a mask , to expose , respectively , the etching stop layer and the insulating layer , for defining a capacitor region ; (i) removing the uncovered etching stop layer to expose the first conducting layer ; (j) anisotropically etching the first conducting layer to a predetermined depth by using the dielectric spacer as a mask , thereby forming a crown-type storage electrode ; (k) removing the dielectric spacer and the etching stop layer ; (l) forming a dielectric layer over exposed portions of the storage electrode ; and (m) forming a second conducting layer as an opposite electrode over the dielectric layer . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5972747A Filed: 1997-09-16 Issued: 1999-10-26 Method of fabricating semiconductor memory device (Original Assignee) LG Semicon Co Ltd (Current Assignee) SK Hynix Inc Ki-Gak Hong |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region (diffusion regions) such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (contact hole) layer (entire surface) over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5972747A CLAIM 1 . A method of fabricating a semiconductor memory device having a substrate , the method comprising the steps of : forming first and second isolation layers on the substrate , the first isolation layer isolating a cell from other cells and the second isolation layer isolating a cell array region from a periphery circuit region ; forming a plurality of word-lines on the cell array region and the periphery circuit region including the first and second isolation layers ; forming first and second impurity diffusion regions (spacer region) on the semiconductor substrate ; forming first and second bit-lines over the cell array region and the periphery circuit region , respectively , the first bit-line contacting the first impurity region and the second bit-line overlapping the word-line on the second isolation layer ; forming an insulting layer on an entire surface (first sub interlevel dielectric layer) including the bit-lines ; forming a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) to expose the second impurity diffusion region ; and forming a capacitor to contact the second impurity diffusion region . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (contact hole) layer (entire surface) insulates said contact region . |
US5972747A CLAIM 1 . A method of fabricating a semiconductor memory device having a substrate , the method comprising the steps of : forming first and second isolation layers on the substrate , the first isolation layer isolating a cell from other cells and the second isolation layer isolating a cell array region from a periphery circuit region ; forming a plurality of word-lines on the cell array region and the periphery circuit region including the first and second isolation layers ; forming first and second impurity diffusion regions on the semiconductor substrate ; forming first and second bit-lines over the cell array region and the periphery circuit region , respectively , the first bit-line contacting the first impurity region and the second bit-line overlapping the word-line on the second isolation layer ; forming an insulting layer on an entire surface (first sub interlevel dielectric layer) including the bit-lines ; forming a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) to expose the second impurity diffusion region ; and forming a capacitor to contact the second impurity diffusion region . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (contact hole) layer insulates said contact region . |
US5972747A CLAIM 1 . A method of fabricating a semiconductor memory device having a substrate , the method comprising the steps of : forming first and second isolation layers on the substrate , the first isolation layer isolating a cell from other cells and the second isolation layer isolating a cell array region from a periphery circuit region ; forming a plurality of word-lines on the cell array region and the periphery circuit region including the first and second isolation layers ; forming first and second impurity diffusion regions on the semiconductor substrate ; forming first and second bit-lines over the cell array region and the periphery circuit region , respectively , the first bit-line contacting the first impurity region and the second bit-line overlapping the word-line on the second isolation layer ; forming an insulting layer on an entire surface including the bit-lines ; forming a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) to expose the second impurity diffusion region ; and forming a capacitor to contact the second impurity diffusion region . |
| US7977797B2 CLAIM 6 . An integrated circuit of claim 1 wherein said spacer region (diffusion regions) insulates said contact region . |
US5972747A CLAIM 1 . A method of fabricating a semiconductor memory device having a substrate , the method comprising the steps of : forming first and second isolation layers on the substrate , the first isolation layer isolating a cell from other cells and the second isolation layer isolating a cell array region from a periphery circuit region ; forming a plurality of word-lines on the cell array region and the periphery circuit region including the first and second isolation layers ; forming first and second impurity diffusion regions (spacer region) on the semiconductor substrate ; forming first and second bit-lines over the cell array region and the periphery circuit region , respectively , the first bit-line contacting the first impurity region and the second bit-line overlapping the word-line on the second isolation layer ; forming an insulting layer on an entire surface including the bit-lines ; forming a contact hole to expose the second impurity diffusion region ; and forming a capacitor to contact the second impurity diffusion region . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (contact hole) layer (entire surface) is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5972747A CLAIM 1 . A method of fabricating a semiconductor memory device having a substrate , the method comprising the steps of : forming first and second isolation layers on the substrate , the first isolation layer isolating a cell from other cells and the second isolation layer isolating a cell array region from a periphery circuit region ; forming a plurality of word-lines on the cell array region and the periphery circuit region including the first and second isolation layers ; forming first and second impurity diffusion regions on the semiconductor substrate ; forming first and second bit-lines over the cell array region and the periphery circuit region , respectively , the first bit-line contacting the first impurity region and the second bit-line overlapping the word-line on the second isolation layer ; forming an insulting layer on an entire surface (first sub interlevel dielectric layer) including the bit-lines ; forming a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) to expose the second impurity diffusion region ; and forming a capacitor to contact the second impurity diffusion region . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric (contact hole) layer (entire surface) for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5972747A CLAIM 1 . A method of fabricating a semiconductor memory device having a substrate , the method comprising the steps of : forming first and second isolation layers on the substrate , the first isolation layer isolating a cell from other cells and the second isolation layer isolating a cell array region from a periphery circuit region ; forming a plurality of word-lines on the cell array region and the periphery circuit region including the first and second isolation layers ; forming first and second impurity diffusion regions on the semiconductor substrate ; forming first and second bit-lines over the cell array region and the periphery circuit region , respectively , the first bit-line contacting the first impurity region and the second bit-line overlapping the word-line on the second isolation layer ; forming an insulting layer on an entire surface (first sub interlevel dielectric layer) including the bit-lines ; forming a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) to expose the second impurity diffusion region ; and forming a capacitor to contact the second impurity diffusion region . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US5972747A CLAIM 1 . A method of fabricating a semiconductor memory device having a substrate , the method comprising the steps of : forming first and second isolation layers on the substrate , the first isolation layer isolating a cell from other cells and the second isolation layer isolating a cell array region from a periphery circuit region ; forming a plurality of word-lines on the cell array region and the periphery circuit region including the first and second isolation layers ; forming first and second impurity diffusion regions on the semiconductor substrate ; forming first and second bit-lines over the cell array region and the periphery circuit region , respectively , the first bit-line contacting the first impurity region and the second bit-line overlapping the word-line on the second isolation layer ; forming an insulting layer on an entire surface including the bit-lines ; forming a contact hole to expose the second impurity diffusion region ; and forming (anti reflective coating) a capacitor to contact the second impurity diffusion region . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (contact hole) layer (entire surface) and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US5972747A CLAIM 1 . A method of fabricating a semiconductor memory device having a substrate , the method comprising the steps of : forming first and second isolation layers on the substrate , the first isolation layer isolating a cell from other cells and the second isolation layer isolating a cell array region from a periphery circuit region ; forming a plurality of word-lines on the cell array region and the periphery circuit region including the first and second isolation layers ; forming first and second impurity diffusion regions on the semiconductor substrate ; forming first and second bit-lines over the cell array region and the periphery circuit region , respectively , the first bit-line contacting the first impurity region and the second bit-line overlapping the word-line on the second isolation layer ; forming an insulting layer on an entire surface (first sub interlevel dielectric layer) including the bit-lines ; forming a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) to expose the second impurity diffusion region ; and forming a capacitor to contact the second impurity diffusion region . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (contact hole) layer (entire surface) is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5972747A CLAIM 1 . A method of fabricating a semiconductor memory device having a substrate , the method comprising the steps of : forming first and second isolation layers on the substrate , the first isolation layer isolating a cell from other cells and the second isolation layer isolating a cell array region from a periphery circuit region ; forming a plurality of word-lines on the cell array region and the periphery circuit region including the first and second isolation layers ; forming first and second impurity diffusion regions on the semiconductor substrate ; forming first and second bit-lines over the cell array region and the periphery circuit region , respectively , the first bit-line contacting the first impurity region and the second bit-line overlapping the word-line on the second isolation layer ; forming an insulting layer on an entire surface (first sub interlevel dielectric layer) including the bit-lines ; forming a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) to expose the second impurity diffusion region ; and forming a capacitor to contact the second impurity diffusion region . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US5972747A CLAIM 1 . A method of fabricating a semiconductor memory device having a substrate , the method comprising the steps of : forming first and second isolation layers on the substrate , the first isolation layer isolating a cell from other cells and the second isolation layer isolating a cell array region from a periphery circuit region ; forming a plurality of word-lines on the cell array region and the periphery circuit region including the first and second isolation layers ; forming first and second impurity diffusion regions on the semiconductor substrate ; forming first and second bit-lines over the cell array region and the periphery circuit region , respectively , the first bit-line contacting the first impurity region and the second bit-line overlapping the word-line on the second isolation layer ; forming an insulting layer on an entire surface including the bit-lines ; forming a contact hole to expose the second impurity diffusion region ; and forming (anti reflective coating) a capacitor to contact the second impurity diffusion region . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5801082A Filed: 1997-08-18 Issued: 1998-09-01 Method for making improved shallow trench isolation with dielectric studs for semiconductor integrated circuits (Original Assignee) Vanguard International Semiconductor Corp (Current Assignee) Vanguard International Semiconductor Corp Horng-Huei Tseng |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region (raised surface) coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region (gate electrodes) such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch (wet etch) stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch (wet etch) stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch (gate oxide) stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5801082A CLAIM 1 . A method for fabricating raised shallow trench isolation regions in a semiconductor substrate comprising the steps of : forming a pad oxide layer composed of silicon oxide on said substrate ; depositing a silicon nitride layer on said pad oxide layer ; forming openings in said silicon nitride layer and said pad oxide layer surrounding device areas using a photoresist mask and anisotropic plasma etching ; removing said photoresist mask ; forming trenches by selectively anisotropic plasma etching said silicon substrate in said openings while leaving portions of said silicon nitride layer over said device areas ; forming a liner oxide by thermal oxidation on exposed surfaces of said trenches in said substrate ; forming a channel-stop implant in said trenches ; depositing a conformal chemical vapor deposited gap-fill silicon oxide to fill said trenches ; chemical/mechanically polishing back said gap-fill silicon oxide to said silicon nitride layer ; removing said silicon nitride layer over said device areas , thereby forming raised dielectric studs in said trenches extending above said substrate surface ; depositing a spin-on glass by spin coating thereby forming disposable spin-on glass spacers on said raised dielectric studs ; curing said spin-on glass by thermal annealing ; wet etch (multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers) ing back said spin-on glass and said pad oxide to said device areas and concurrently etching back said raised dielectric studs and said spin-on glass spacers thereby completing said shallow trench isolation regions having a convex raised surface (contact region) relative to said substrate surface . US5801082A CLAIM 13 . A method for fabricating raised shallow trench isolation regions in a semiconductor substrate , and gate electrodes (spacer region) for field effect transistors comprising the steps of : forming a pad oxide layer composed of silicon oxide on said substrate ; depositing a silicon nitride layer on said pad oxide layer ; forming openings in said silicon nitride layer and said pad oxide layer surrounding device areas using a photoresist mask and anisotropic plasma etching ; removing said photoresist mask ; forming trenches by selectively anisotropic plasma etching said silicon substrate in said openings while leaving portions of said silicon nitride layer over said device areas ; forming a liner oxide by thermal oxidation on exposed surfaces of said trenches in said substrate ; forming a channel-stop implant in said trenches ; depositing a conformal chemical vapor deposited gap-fill silicon oxide to fill said trenches ; chemical/mechanically polishing back said gap-fill silicon oxide to said silicon nitride layer ; removing said silicon nitride layer over said device areas , thereby forming raised dielectric studs in said trenches extending above said substrate surface ; depositing a spin-on glass by spin coating thereby forming disposable spin-on glass spacers on said raised dielectric studs ; curing said spin-on glass by thermal annealing ; wet etching back said spin-on glass and said pad oxide to said device areas and concurrently etching back said raised dielectric studs and said spin-on glass spacers thereby forming said shallow trench isolation regions having a convex raised surface relative to said substrate surface ; forming a gate oxide (second etch) by thermal oxidation on said device areas ; depositing a polysilicon layer on said substrate ; patterning said polysilicon layer and completing said gate electrodes for said field effect transistors . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch (wet etch) stop layer protects removal of a substrate material (silicon oxide, spin coating) by an etch process (wet etch) . |
US5801082A CLAIM 1 . A method for fabricating raised shallow trench isolation regions in a semiconductor substrate comprising the steps of : forming a pad oxide layer composed of silicon oxide (substrate material) on said substrate ; depositing a silicon nitride layer on said pad oxide layer ; forming openings in said silicon nitride layer and said pad oxide layer surrounding device areas using a photoresist mask and anisotropic plasma etching ; removing said photoresist mask ; forming trenches by selectively anisotropic plasma etching said silicon substrate in said openings while leaving portions of said silicon nitride layer over said device areas ; forming a liner oxide by thermal oxidation on exposed surfaces of said trenches in said substrate ; forming a channel-stop implant in said trenches ; depositing a conformal chemical vapor deposited gap-fill silicon oxide to fill said trenches ; chemical/mechanically polishing back said gap-fill silicon oxide to said silicon nitride layer ; removing said silicon nitride layer over said device areas , thereby forming raised dielectric studs in said trenches extending above said substrate surface ; depositing a spin-on glass by spin coating (substrate material) thereby forming disposable spin-on glass spacers on said raised dielectric studs ; curing said spin-on glass by thermal annealing ; wet etch (multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers) ing back said spin-on glass and said pad oxide to said device areas and concurrently etching back said raised dielectric studs and said spin-on glass spacers thereby completing said shallow trench isolation regions having a convex raised surface relative to said substrate surface . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric layer insulates said contact region (raised surface) . |
US5801082A CLAIM 1 . A method for fabricating raised shallow trench isolation regions in a semiconductor substrate comprising the steps of : forming a pad oxide layer composed of silicon oxide on said substrate ; depositing a silicon nitride layer on said pad oxide layer ; forming openings in said silicon nitride layer and said pad oxide layer surrounding device areas using a photoresist mask and anisotropic plasma etching ; removing said photoresist mask ; forming trenches by selectively anisotropic plasma etching said silicon substrate in said openings while leaving portions of said silicon nitride layer over said device areas ; forming a liner oxide by thermal oxidation on exposed surfaces of said trenches in said substrate ; forming a channel-stop implant in said trenches ; depositing a conformal chemical vapor deposited gap-fill silicon oxide to fill said trenches ; chemical/mechanically polishing back said gap-fill silicon oxide to said silicon nitride layer ; removing said silicon nitride layer over said device areas , thereby forming raised dielectric studs in said trenches extending above said substrate surface ; depositing a spin-on glass by spin coating thereby forming disposable spin-on glass spacers on said raised dielectric studs ; curing said spin-on glass by thermal annealing ; wet etching back said spin-on glass and said pad oxide to said device areas and concurrently etching back said raised dielectric studs and said spin-on glass spacers thereby completing said shallow trench isolation regions having a convex raised surface (contact region) relative to said substrate surface . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch (gate oxide) stop layer protects lower layers during an etching process . |
US5801082A CLAIM 1 . A method for fabricating raised shallow trench isolation regions in a semiconductor substrate comprising the steps of : forming a pad oxide layer composed of silicon oxide on said substrate ; depositing a silicon nitride layer on said pad oxide layer ; forming openings in said silicon nitride layer and said pad oxide layer surrounding device areas using a photoresist mask and anisotropic plasma etching ; removing said photoresist mask ; forming trenches by selectively anisotropic plasma etching said silicon substrate in said openings while leaving portions of said silicon nitride layer over said device areas ; forming a liner oxide by thermal oxidation on exposed surfaces of said trenches in said substrate ; forming a channel-stop implant in said trenches ; depositing a conformal chemical vapor deposited gap-fill silicon oxide to fill said trenches ; chemical/mechanically polishing back said gap-fill silicon oxide to said silicon nitride layer ; removing said silicon nitride layer over said device areas , thereby forming raised dielectric studs in said trenches extending above said substrate surface ; depositing a spin-on glass by spin coating thereby forming disposable spin-on glass spacers on said raised dielectric studs ; curing said spin-on glass by thermal annealing ; wet etch (multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers) ing back said spin-on glass and said pad oxide to said device areas and concurrently etching back said raised dielectric studs and said spin-on glass spacers thereby completing said shallow trench isolation regions having a convex raised surface relative to said substrate surface . US5801082A CLAIM 13 . A method for fabricating raised shallow trench isolation regions in a semiconductor substrate , and gate electrodes for field effect transistors comprising the steps of : forming a pad oxide layer composed of silicon oxide on said substrate ; depositing a silicon nitride layer on said pad oxide layer ; forming openings in said silicon nitride layer and said pad oxide layer surrounding device areas using a photoresist mask and anisotropic plasma etching ; removing said photoresist mask ; forming trenches by selectively anisotropic plasma etching said silicon substrate in said openings while leaving portions of said silicon nitride layer over said device areas ; forming a liner oxide by thermal oxidation on exposed surfaces of said trenches in said substrate ; forming a channel-stop implant in said trenches ; depositing a conformal chemical vapor deposited gap-fill silicon oxide to fill said trenches ; chemical/mechanically polishing back said gap-fill silicon oxide to said silicon nitride layer ; removing said silicon nitride layer over said device areas , thereby forming raised dielectric studs in said trenches extending above said substrate surface ; depositing a spin-on glass by spin coating thereby forming disposable spin-on glass spacers on said raised dielectric studs ; curing said spin-on glass by thermal annealing ; wet etching back said spin-on glass and said pad oxide to said device areas and concurrently etching back said raised dielectric studs and said spin-on glass spacers thereby forming said shallow trench isolation regions having a convex raised surface relative to said substrate surface ; forming a gate oxide (second etch) by thermal oxidation on said device areas ; depositing a polysilicon layer on said substrate ; patterning said polysilicon layer and completing said gate electrodes for said field effect transistors . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric layer insulates said contact region (raised surface) . |
US5801082A CLAIM 1 . A method for fabricating raised shallow trench isolation regions in a semiconductor substrate comprising the steps of : forming a pad oxide layer composed of silicon oxide on said substrate ; depositing a silicon nitride layer on said pad oxide layer ; forming openings in said silicon nitride layer and said pad oxide layer surrounding device areas using a photoresist mask and anisotropic plasma etching ; removing said photoresist mask ; forming trenches by selectively anisotropic plasma etching said silicon substrate in said openings while leaving portions of said silicon nitride layer over said device areas ; forming a liner oxide by thermal oxidation on exposed surfaces of said trenches in said substrate ; forming a channel-stop implant in said trenches ; depositing a conformal chemical vapor deposited gap-fill silicon oxide to fill said trenches ; chemical/mechanically polishing back said gap-fill silicon oxide to said silicon nitride layer ; removing said silicon nitride layer over said device areas , thereby forming raised dielectric studs in said trenches extending above said substrate surface ; depositing a spin-on glass by spin coating thereby forming disposable spin-on glass spacers on said raised dielectric studs ; curing said spin-on glass by thermal annealing ; wet etching back said spin-on glass and said pad oxide to said device areas and concurrently etching back said raised dielectric studs and said spin-on glass spacers thereby completing said shallow trench isolation regions having a convex raised surface (contact region) relative to said substrate surface . |
| US7977797B2 CLAIM 6 . An integrated circuit of claim 1 wherein said spacer region (gate electrodes) insulates said contact region (raised surface) . |
US5801082A CLAIM 1 . A method for fabricating raised shallow trench isolation regions in a semiconductor substrate comprising the steps of : forming a pad oxide layer composed of silicon oxide on said substrate ; depositing a silicon nitride layer on said pad oxide layer ; forming openings in said silicon nitride layer and said pad oxide layer surrounding device areas using a photoresist mask and anisotropic plasma etching ; removing said photoresist mask ; forming trenches by selectively anisotropic plasma etching said silicon substrate in said openings while leaving portions of said silicon nitride layer over said device areas ; forming a liner oxide by thermal oxidation on exposed surfaces of said trenches in said substrate ; forming a channel-stop implant in said trenches ; depositing a conformal chemical vapor deposited gap-fill silicon oxide to fill said trenches ; chemical/mechanically polishing back said gap-fill silicon oxide to said silicon nitride layer ; removing said silicon nitride layer over said device areas , thereby forming raised dielectric studs in said trenches extending above said substrate surface ; depositing a spin-on glass by spin coating thereby forming disposable spin-on glass spacers on said raised dielectric studs ; curing said spin-on glass by thermal annealing ; wet etching back said spin-on glass and said pad oxide to said device areas and concurrently etching back said raised dielectric studs and said spin-on glass spacers thereby completing said shallow trench isolation regions having a convex raised surface (contact region) relative to said substrate surface . US5801082A CLAIM 13 . A method for fabricating raised shallow trench isolation regions in a semiconductor substrate , and gate electrodes (spacer region) for field effect transistors comprising the steps of : forming a pad oxide layer composed of silicon oxide on said substrate ; depositing a silicon nitride layer on said pad oxide layer ; forming openings in said silicon nitride layer and said pad oxide layer surrounding device areas using a photoresist mask and anisotropic plasma etching ; removing said photoresist mask ; forming trenches by selectively anisotropic plasma etching said silicon substrate in said openings while leaving portions of said silicon nitride layer over said device areas ; forming a liner oxide by thermal oxidation on exposed surfaces of said trenches in said substrate ; forming a channel-stop implant in said trenches ; depositing a conformal chemical vapor deposited gap-fill silicon oxide to fill said trenches ; chemical/mechanically polishing back said gap-fill silicon oxide to said silicon nitride layer ; removing said silicon nitride layer over said device areas , thereby forming raised dielectric studs in said trenches extending above said substrate surface ; depositing a spin-on glass by spin coating thereby forming disposable spin-on glass spacers on said raised dielectric studs ; curing said spin-on glass by thermal annealing ; wet etching back said spin-on glass and said pad oxide to said device areas and concurrently etching back said raised dielectric studs and said spin-on glass spacers thereby forming said shallow trench isolation regions having a convex raised surface relative to said substrate surface ; forming a gate oxide by thermal oxidation on said device areas ; depositing a polysilicon layer on said substrate ; patterning said polysilicon layer and completing said gate electrodes for said field effect transistors . |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area of said contact region (raised surface) permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
US5801082A CLAIM 1 . A method for fabricating raised shallow trench isolation regions in a semiconductor substrate comprising the steps of : forming a pad oxide layer composed of silicon oxide on said substrate ; depositing a silicon nitride layer on said pad oxide layer ; forming openings in said silicon nitride layer and said pad oxide layer surrounding device areas using a photoresist mask and anisotropic plasma etching ; removing said photoresist mask ; forming trenches by selectively anisotropic plasma etching said silicon substrate in said openings while leaving portions of said silicon nitride layer over said device areas ; forming a liner oxide by thermal oxidation on exposed surfaces of said trenches in said substrate ; forming a channel-stop implant in said trenches ; depositing a conformal chemical vapor deposited gap-fill silicon oxide to fill said trenches ; chemical/mechanically polishing back said gap-fill silicon oxide to said silicon nitride layer ; removing said silicon nitride layer over said device areas , thereby forming raised dielectric studs in said trenches extending above said substrate surface ; depositing a spin-on glass by spin coating thereby forming disposable spin-on glass spacers on said raised dielectric studs ; curing said spin-on glass by thermal annealing ; wet etching back said spin-on glass and said pad oxide to said device areas and concurrently etching back said raised dielectric studs and said spin-on glass spacers thereby completing said shallow trench isolation regions having a convex raised surface (contact region) relative to said substrate surface . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch (wet etch) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (gate oxide) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5801082A CLAIM 1 . A method for fabricating raised shallow trench isolation regions in a semiconductor substrate comprising the steps of : forming a pad oxide layer composed of silicon oxide on said substrate ; depositing a silicon nitride layer on said pad oxide layer ; forming openings in said silicon nitride layer and said pad oxide layer surrounding device areas using a photoresist mask and anisotropic plasma etching ; removing said photoresist mask ; forming trenches by selectively anisotropic plasma etching said silicon substrate in said openings while leaving portions of said silicon nitride layer over said device areas ; forming a liner oxide by thermal oxidation on exposed surfaces of said trenches in said substrate ; forming a channel-stop implant in said trenches ; depositing a conformal chemical vapor deposited gap-fill silicon oxide to fill said trenches ; chemical/mechanically polishing back said gap-fill silicon oxide to said silicon nitride layer ; removing said silicon nitride layer over said device areas , thereby forming raised dielectric studs in said trenches extending above said substrate surface ; depositing a spin-on glass by spin coating thereby forming disposable spin-on glass spacers on said raised dielectric studs ; curing said spin-on glass by thermal annealing ; wet etch (multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers) ing back said spin-on glass and said pad oxide to said device areas and concurrently etching back said raised dielectric studs and said spin-on glass spacers thereby completing said shallow trench isolation regions having a convex raised surface relative to said substrate surface . US5801082A CLAIM 13 . A method for fabricating raised shallow trench isolation regions in a semiconductor substrate , and gate electrodes for field effect transistors comprising the steps of : forming a pad oxide layer composed of silicon oxide on said substrate ; depositing a silicon nitride layer on said pad oxide layer ; forming openings in said silicon nitride layer and said pad oxide layer surrounding device areas using a photoresist mask and anisotropic plasma etching ; removing said photoresist mask ; forming trenches by selectively anisotropic plasma etching said silicon substrate in said openings while leaving portions of said silicon nitride layer over said device areas ; forming a liner oxide by thermal oxidation on exposed surfaces of said trenches in said substrate ; forming a channel-stop implant in said trenches ; depositing a conformal chemical vapor deposited gap-fill silicon oxide to fill said trenches ; chemical/mechanically polishing back said gap-fill silicon oxide to said silicon nitride layer ; removing said silicon nitride layer over said device areas , thereby forming raised dielectric studs in said trenches extending above said substrate surface ; depositing a spin-on glass by spin coating thereby forming disposable spin-on glass spacers on said raised dielectric studs ; curing said spin-on glass by thermal annealing ; wet etching back said spin-on glass and said pad oxide to said device areas and concurrently etching back said raised dielectric studs and said spin-on glass spacers thereby forming said shallow trench isolation regions having a convex raised surface relative to said substrate surface ; forming a gate oxide (second etch) by thermal oxidation on said device areas ; depositing a polysilicon layer on said substrate ; patterning said polysilicon layer and completing said gate electrodes for said field effect transistors . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space (trench isolation regions) in a portion of said first sub interlevel dielectric layer for said contact region (raised surface) is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5801082A CLAIM 1 . A method for fabricating raised shallow trench isolation regions (first space) in a semiconductor substrate comprising the steps of : forming a pad oxide layer composed of silicon oxide on said substrate ; depositing a silicon nitride layer on said pad oxide layer ; forming openings in said silicon nitride layer and said pad oxide layer surrounding device areas using a photoresist mask and anisotropic plasma etching ; removing said photoresist mask ; forming trenches by selectively anisotropic plasma etching said silicon substrate in said openings while leaving portions of said silicon nitride layer over said device areas ; forming a liner oxide by thermal oxidation on exposed surfaces of said trenches in said substrate ; forming a channel-stop implant in said trenches ; depositing a conformal chemical vapor deposited gap-fill silicon oxide to fill said trenches ; chemical/mechanically polishing back said gap-fill silicon oxide to said silicon nitride layer ; removing said silicon nitride layer over said device areas , thereby forming raised dielectric studs in said trenches extending above said substrate surface ; depositing a spin-on glass by spin coating thereby forming disposable spin-on glass spacers on said raised dielectric studs ; curing said spin-on glass by thermal annealing ; wet etching back said spin-on glass and said pad oxide to said device areas and concurrently etching back said raised dielectric studs and said spin-on glass spacers thereby completing said shallow trench isolation regions having a convex raised surface (contact region) relative to said substrate surface . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch (wet etch) stop insulation layer comprising a first etch (wet etch) stop layer and a second etch (gate oxide) stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region (raised surface) and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US5801082A CLAIM 1 . A method for fabricating raised shallow trench isolation regions in a semiconductor substrate comprising the steps of : forming a pad oxide layer composed of silicon oxide on said substrate ; depositing a silicon nitride layer on said pad oxide layer ; forming openings in said silicon nitride layer and said pad oxide layer surrounding device areas using a photoresist mask and anisotropic plasma etching ; removing said photoresist mask ; forming trenches by selectively anisotropic plasma etching said silicon substrate in said openings while leaving portions of said silicon nitride layer over said device areas ; forming a liner oxide by thermal oxidation on exposed surfaces of said trenches in said substrate ; forming a channel-stop implant in said trenches ; depositing a conformal chemical vapor deposited gap-fill silicon oxide to fill said trenches ; chemical/mechanically polishing back said gap-fill silicon oxide to said silicon nitride layer ; removing said silicon nitride layer over said device areas , thereby forming raised dielectric studs in said trenches extending above said substrate surface ; depositing a spin-on glass by spin coating thereby forming disposable spin-on glass spacers on said raised dielectric studs ; curing said spin-on glass by thermal annealing ; wet etch (multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers) ing back said spin-on glass and said pad oxide to said device areas and concurrently etching back said raised dielectric studs and said spin-on glass spacers thereby completing said shallow trench isolation regions having a convex raised surface (contact region) relative to said substrate surface . US5801082A CLAIM 13 . A method for fabricating raised shallow trench isolation regions in a semiconductor substrate , and gate electrodes for field effect transistors comprising the steps of : forming a pad oxide layer composed of silicon oxide on said substrate ; depositing a silicon nitride layer on said pad oxide layer ; forming openings in said silicon nitride layer and said pad oxide layer surrounding device areas using a photoresist mask and anisotropic plasma etching ; removing said photoresist mask ; forming trenches by selectively anisotropic plasma etching said silicon substrate in said openings while leaving portions of said silicon nitride layer over said device areas ; forming a liner oxide by thermal oxidation on exposed surfaces of said trenches in said substrate ; forming a channel-stop implant in said trenches ; depositing a conformal chemical vapor deposited gap-fill silicon oxide to fill said trenches ; chemical/mechanically polishing back said gap-fill silicon oxide to said silicon nitride layer ; removing said silicon nitride layer over said device areas , thereby forming raised dielectric studs in said trenches extending above said substrate surface ; depositing a spin-on glass by spin coating thereby forming disposable spin-on glass spacers on said raised dielectric studs ; curing said spin-on glass by thermal annealing ; wet etching back said spin-on glass and said pad oxide to said device areas and concurrently etching back said raised dielectric studs and said spin-on glass spacers thereby forming said shallow trench isolation regions having a convex raised surface relative to said substrate surface ; forming a gate oxide (second etch) by thermal oxidation on said device areas ; depositing a polysilicon layer on said substrate ; patterning said polysilicon layer and completing said gate electrodes for said field effect transistors . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch (wet etch) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (gate oxide) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5801082A CLAIM 1 . A method for fabricating raised shallow trench isolation regions in a semiconductor substrate comprising the steps of : forming a pad oxide layer composed of silicon oxide on said substrate ; depositing a silicon nitride layer on said pad oxide layer ; forming openings in said silicon nitride layer and said pad oxide layer surrounding device areas using a photoresist mask and anisotropic plasma etching ; removing said photoresist mask ; forming trenches by selectively anisotropic plasma etching said silicon substrate in said openings while leaving portions of said silicon nitride layer over said device areas ; forming a liner oxide by thermal oxidation on exposed surfaces of said trenches in said substrate ; forming a channel-stop implant in said trenches ; depositing a conformal chemical vapor deposited gap-fill silicon oxide to fill said trenches ; chemical/mechanically polishing back said gap-fill silicon oxide to said silicon nitride layer ; removing said silicon nitride layer over said device areas , thereby forming raised dielectric studs in said trenches extending above said substrate surface ; depositing a spin-on glass by spin coating thereby forming disposable spin-on glass spacers on said raised dielectric studs ; curing said spin-on glass by thermal annealing ; wet etch (multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers) ing back said spin-on glass and said pad oxide to said device areas and concurrently etching back said raised dielectric studs and said spin-on glass spacers thereby completing said shallow trench isolation regions having a convex raised surface relative to said substrate surface . US5801082A CLAIM 13 . A method for fabricating raised shallow trench isolation regions in a semiconductor substrate , and gate electrodes for field effect transistors comprising the steps of : forming a pad oxide layer composed of silicon oxide on said substrate ; depositing a silicon nitride layer on said pad oxide layer ; forming openings in said silicon nitride layer and said pad oxide layer surrounding device areas using a photoresist mask and anisotropic plasma etching ; removing said photoresist mask ; forming trenches by selectively anisotropic plasma etching said silicon substrate in said openings while leaving portions of said silicon nitride layer over said device areas ; forming a liner oxide by thermal oxidation on exposed surfaces of said trenches in said substrate ; forming a channel-stop implant in said trenches ; depositing a conformal chemical vapor deposited gap-fill silicon oxide to fill said trenches ; chemical/mechanically polishing back said gap-fill silicon oxide to said silicon nitride layer ; removing said silicon nitride layer over said device areas , thereby forming raised dielectric studs in said trenches extending above said substrate surface ; depositing a spin-on glass by spin coating thereby forming disposable spin-on glass spacers on said raised dielectric studs ; curing said spin-on glass by thermal annealing ; wet etching back said spin-on glass and said pad oxide to said device areas and concurrently etching back said raised dielectric studs and said spin-on glass spacers thereby forming said shallow trench isolation regions having a convex raised surface relative to said substrate surface ; forming a gate oxide (second etch) by thermal oxidation on said device areas ; depositing a polysilicon layer on said substrate ; patterning said polysilicon layer and completing said gate electrodes for said field effect transistors . |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region (raised surface) is a first range of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5801082A CLAIM 1 . A method for fabricating raised shallow trench isolation regions in a semiconductor substrate comprising the steps of : forming a pad oxide layer composed of silicon oxide on said substrate ; depositing a silicon nitride layer on said pad oxide layer ; forming openings in said silicon nitride layer and said pad oxide layer surrounding device areas using a photoresist mask and anisotropic plasma etching ; removing said photoresist mask ; forming trenches by selectively anisotropic plasma etching said silicon substrate in said openings while leaving portions of said silicon nitride layer over said device areas ; forming a liner oxide by thermal oxidation on exposed surfaces of said trenches in said substrate ; forming a channel-stop implant in said trenches ; depositing a conformal chemical vapor deposited gap-fill silicon oxide to fill said trenches ; chemical/mechanically polishing back said gap-fill silicon oxide to said silicon nitride layer ; removing said silicon nitride layer over said device areas , thereby forming raised dielectric studs in said trenches extending above said substrate surface ; depositing a spin-on glass by spin coating thereby forming disposable spin-on glass spacers on said raised dielectric studs ; curing said spin-on glass by thermal annealing ; wet etching back said spin-on glass and said pad oxide to said device areas and concurrently etching back said raised dielectric studs and said spin-on glass spacers thereby completing said shallow trench isolation regions having a convex raised surface (contact region) relative to said substrate surface . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5883010A Filed: 1997-08-07 Issued: 1999-03-16 Method for protecting nonsilicided surfaces from silicide formation using spacer oxide mask (Original Assignee) National Semiconductor Corp (Current Assignee) National Semiconductor Corp Richard B. Merrill, C. S. Teng, John M. Pierce |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region (contact region) coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5883010A CLAIM 4 . A method for forming silicides in accordance with claim 3 , wherein the unmasked regions correspond to contact region (contact region) s of a resistor . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric layer insulates said contact region (contact region) . |
US5883010A CLAIM 4 . A method for forming silicides in accordance with claim 3 , wherein the unmasked regions correspond to contact region (contact region) s of a resistor . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric layer insulates said contact region (contact region) . |
US5883010A CLAIM 4 . A method for forming silicides in accordance with claim 3 , wherein the unmasked regions correspond to contact region (contact region) s of a resistor . |
| US7977797B2 CLAIM 6 . An integrated circuit of claim 1 wherein said spacer region insulates said contact region (contact region) . |
US5883010A CLAIM 4 . A method for forming silicides in accordance with claim 3 , wherein the unmasked regions correspond to contact region (contact region) s of a resistor . |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area of said contact region (contact region) permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
US5883010A CLAIM 4 . A method for forming silicides in accordance with claim 3 , wherein the unmasked regions correspond to contact region (contact region) s of a resistor . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric layer for said contact region (contact region) is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5883010A CLAIM 4 . A method for forming silicides in accordance with claim 3 , wherein the unmasked regions correspond to contact region (contact region) s of a resistor . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers (exposed regions) have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region (contact region) and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US5883010A CLAIM 4 . A method for forming silicides in accordance with claim 3 , wherein the unmasked regions correspond to contact region (contact region) s of a resistor . US5883010A CLAIM 9 . A method for forming a resistor having silicided contact regions , comprising the steps of : implanting conductivity-altering impurity into a lightly doped silicon substrate ; depositing a spacer oxide layer over the silicon substrate ; developing a silicide exclusion photoresistive mask upon selected regions of the spacer oxide layer , such that unmasked regions correspond to regions expected to bear suicides ; etching the spacer oxide layer from unmasked regions , thereby exposing the silicon substrate in unmasked regions ; implanting concentrated conductivity-altering impurity into the exposed regions (second etch stop layers) of the silicon substrate ; forming a layer of silicide-forming metal upon the exposed silicon substrate ; and causing the silicide-forming metal layer and silicon substrate to react to form silicides . |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region (contact region) is a first range of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5883010A CLAIM 4 . A method for forming silicides in accordance with claim 3 , wherein the unmasked regions correspond to contact region (contact region) s of a resistor . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | JPH1154724A Filed: 1997-08-06 Issued: 1999-02-26 半導体装置の製造方法 (Original Assignee) Sony Corp; ソニー株式会社 Keiichi Ono, 圭一 大野 |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (製造方法) of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation (なる第２) between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (メモリ素子, キャパシタ) layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
JPH1154724A CLAIM 1 【請求項１】 第１領域と第２領域とを備えた半導体基 板を用い、前記第１領域の半導体基板上と第２領域の半 導体基板上とにそれぞれ導電パターンを形成し、前記導 電パターンの形状に沿う状態で前記半導体基板上に第１ 絶縁膜を形成し、該第１絶縁膜上にこの第１絶縁膜とエ ッチング選択比がとれる材料からなる第２ (electrical insulation) 絶縁膜をその 表面が平坦になるように形成する第１工程と、 少なくとも (second sub interlevel dielectric layer) 前記第１領域における前記第１絶縁膜と前記 第２絶縁膜とに、前記半導体基板に達するコンタクトホ ールを形成し、該コンタクトホールの内壁に前記第２絶 縁膜とエッチング選択比がとれかつ自身のシリサイド化 を防止する材料からなるサイドウォールを形成する第２ 工程と、 前記コンタクトホール内部に前記サイドウォールを介し て導電材料を埋め込むことによりプラグを形成する第３ 工程と、 エッチングによって前記第２絶縁膜を除去することによ り前記プラグおよび前記第１絶縁膜を露出させ、次いで 前記第２領域の前記第１絶縁膜のみをエッチバックし て、該第２領域における導電パターンの側壁に前記第１ 絶縁膜からなるスペーササイドウォールを形成するとと もに前記第２領域の半導体基板の表面を露出させる第４ 工程と、 前記露出した半導体基板の表面にシリサイド層を形成す る第５工程と、 前記プラグと前記第１絶縁膜と前記導電パターンとを覆 う状態で前記半導体基板上に、前記第１絶縁膜とエッチ ング選択比のとれる材料からなる第３絶縁膜を形成した 後、該第３絶縁膜の表面を平坦化するとともに前記プラ グの上面を露出させる第６工程とを有することを特徴と する半導体装置の製造方法 (metal layer coupling area) 。 JPH1154724A CLAIM 2 【請求項２】 前記半導体基板にメモリ素子 (interlevel dielectric) とロジック 素子とを混載した半導体装置の製造方法であって、 前記半導体基板は、前記第１領域であるメモリ素子の形 成領域と、前記第２領域であるロジック素子の形成領域 とを備えており、 前記第６工程の後、前記メモリ素子の形成領域にキャパ シタを形成する工程を有していることを特徴とする請求 項１記載の半導体装置の製造方法。 JPH1154724A CLAIM 3 【請求項３】 前記キャパシタ (interlevel dielectric) を形成する工程では、前 記第３絶縁膜の上方に金属材料からなる下部電極を形成 し、該下部電極の表面にキャパシタ絶縁膜を形成し、該 キャパシタ絶縁膜の表面に金属材料からなる上部電極を 形成してキャパシタを得ることを特徴とする請求項２記 載の半導体装置の製造方法。 |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer protects removal of a substrate material (ウォール, ６工程) by an etch process . |
JPH1154724A CLAIM 1 【請求項１】 第１領域と第２領域とを備えた半導体基 板を用い、前記第１領域の半導体基板上と第２領域の半 導体基板上とにそれぞれ導電パターンを形成し、前記導 電パターンの形状に沿う状態で前記半導体基板上に第１ 絶縁膜を形成し、該第１絶縁膜上にこの第１絶縁膜とエ ッチング選択比がとれる材料からなる第２絶縁膜をその 表面が平坦になるように形成する第１工程と、 少なくとも前記第１領域における前記第１絶縁膜と前記 第２絶縁膜とに、前記半導体基板に達するコンタクトホ ールを形成し、該コンタクトホールの内壁に前記第２絶 縁膜とエッチング選択比がとれかつ自身のシリサイド化 を防止する材料からなるサイドウォール (substrate material) を形成する第２ 工程と、 前記コンタクトホール内部に前記サイドウォールを介し て導電材料を埋め込むことによりプラグを形成する第３ 工程と、 エッチングによって前記第２絶縁膜を除去することによ り前記プラグおよび前記第１絶縁膜を露出させ、次いで 前記第２領域の前記第１絶縁膜のみをエッチバックし て、該第２領域における導電パターンの側壁に前記第１ 絶縁膜からなるスペーササイドウォールを形成するとと もに前記第２領域の半導体基板の表面を露出させる第４ 工程と、 前記露出した半導体基板の表面にシリサイド層を形成す る第５工程と、 前記プラグと前記第１絶縁膜と前記導電パターンとを覆 う状態で前記半導体基板上に、前記第１絶縁膜とエッチ ング選択比のとれる材料からなる第３絶縁膜を形成した 後、該第３絶縁膜の表面を平坦化するとともに前記プラ グの上面を露出させる第６工程 (substrate material) とを有することを特徴と する半導体装置の製造方法。 |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (メモリ素子, キャパシタ) layer insulates said contact region . |
JPH1154724A CLAIM 2 【請求項２】 前記半導体基板にメモリ素子 (interlevel dielectric) とロジック 素子とを混載した半導体装置の製造方法であって、 前記半導体基板は、前記第１領域であるメモリ素子の形 成領域と、前記第２領域であるロジック素子の形成領域 とを備えており、 前記第６工程の後、前記メモリ素子の形成領域にキャパ シタを形成する工程を有していることを特徴とする請求 項１記載の半導体装置の製造方法。 JPH1154724A CLAIM 3 【請求項３】 前記キャパシタ (interlevel dielectric) を形成する工程では、前 記第３絶縁膜の上方に金属材料からなる下部電極を形成 し、該下部電極の表面にキャパシタ絶縁膜を形成し、該 キャパシタ絶縁膜の表面に金属材料からなる上部電極を 形成してキャパシタを得ることを特徴とする請求項２記 載の半導体装置の製造方法。 |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (メモリ素子, キャパシタ) layer insulates said contact region . |
JPH1154724A CLAIM 1 【請求項１】 第１領域と第２領域とを備えた半導体基 板を用い、前記第１領域の半導体基板上と第２領域の半 導体基板上とにそれぞれ導電パターンを形成し、前記導 電パターンの形状に沿う状態で前記半導体基板上に第１ 絶縁膜を形成し、該第１絶縁膜上にこの第１絶縁膜とエ ッチング選択比がとれる材料からなる第２絶縁膜をその 表面が平坦になるように形成する第１工程と、 少なくとも (second sub interlevel dielectric layer) 前記第１領域における前記第１絶縁膜と前記 第２絶縁膜とに、前記半導体基板に達するコンタクトホ ールを形成し、該コンタクトホールの内壁に前記第２絶 縁膜とエッチング選択比がとれかつ自身のシリサイド化 を防止する材料からなるサイドウォールを形成する第２ 工程と、 前記コンタクトホール内部に前記サイドウォールを介し て導電材料を埋め込むことによりプラグを形成する第３ 工程と、 エッチングによって前記第２絶縁膜を除去することによ り前記プラグおよび前記第１絶縁膜を露出させ、次いで 前記第２領域の前記第１絶縁膜のみをエッチバックし て、該第２領域における導電パターンの側壁に前記第１ 絶縁膜からなるスペーササイドウォールを形成するとと もに前記第２領域の半導体基板の表面を露出させる第４ 工程と、 前記露出した半導体基板の表面にシリサイド層を形成す る第５工程と、 前記プラグと前記第１絶縁膜と前記導電パターンとを覆 う状態で前記半導体基板上に、前記第１絶縁膜とエッチ ング選択比のとれる材料からなる第３絶縁膜を形成した 後、該第３絶縁膜の表面を平坦化するとともに前記プラ グの上面を露出させる第６工程とを有することを特徴と する半導体装置の製造方法。 JPH1154724A CLAIM 2 【請求項２】 前記半導体基板にメモリ素子 (interlevel dielectric) とロジック 素子とを混載した半導体装置の製造方法であって、 前記半導体基板は、前記第１領域であるメモリ素子の形 成領域と、前記第２領域であるロジック素子の形成領域 とを備えており、 前記第６工程の後、前記メモリ素子の形成領域にキャパ シタを形成する工程を有していることを特徴とする請求 項１記載の半導体装置の製造方法。 JPH1154724A CLAIM 3 【請求項３】 前記キャパシタ (interlevel dielectric) を形成する工程では、前 記第３絶縁膜の上方に金属材料からなる下部電極を形成 し、該下部電極の表面にキャパシタ絶縁膜を形成し、該 キャパシタ絶縁膜の表面に金属材料からなる上部電極を 形成してキャパシタを得ることを特徴とする請求項２記 載の半導体装置の製造方法。 |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area of said contact region permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area (製造方法) of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
JPH1154724A CLAIM 1 【請求項１】 第１領域と第２領域とを備えた半導体基 板を用い、前記第１領域の半導体基板上と第２領域の半 導体基板上とにそれぞれ導電パターンを形成し、前記導 電パターンの形状に沿う状態で前記半導体基板上に第１ 絶縁膜を形成し、該第１絶縁膜上にこの第１絶縁膜とエ ッチング選択比がとれる材料からなる第２絶縁膜をその 表面が平坦になるように形成する第１工程と、 少なくとも前記第１領域における前記第１絶縁膜と前記 第２絶縁膜とに、前記半導体基板に達するコンタクトホ ールを形成し、該コンタクトホールの内壁に前記第２絶 縁膜とエッチング選択比がとれかつ自身のシリサイド化 を防止する材料からなるサイドウォールを形成する第２ 工程と、 前記コンタクトホール内部に前記サイドウォールを介し て導電材料を埋め込むことによりプラグを形成する第３ 工程と、 エッチングによって前記第２絶縁膜を除去することによ り前記プラグおよび前記第１絶縁膜を露出させ、次いで 前記第２領域の前記第１絶縁膜のみをエッチバックし て、該第２領域における導電パターンの側壁に前記第１ 絶縁膜からなるスペーササイドウォールを形成するとと もに前記第２領域の半導体基板の表面を露出させる第４ 工程と、 前記露出した半導体基板の表面にシリサイド層を形成す る第５工程と、 前記プラグと前記第１絶縁膜と前記導電パターンとを覆 う状態で前記半導体基板上に、前記第１絶縁膜とエッチ ング選択比のとれる材料からなる第３絶縁膜を形成した 後、該第３絶縁膜の表面を平坦化するとともに前記プラ グの上面を露出させる第６工程とを有することを特徴と する半導体装置の製造方法 (metal layer coupling area) 。 |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Å thick , said first sub interlevel dielectric (メモリ素子, キャパシタ) layer is in a range of about 1 , 000 to 2 , 000 Å thick , said second etch stop layer is in a range of about 300 to 800 Å thick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Å thick . |
JPH1154724A CLAIM 1 【請求項１】 第１領域と第２領域とを備えた半導体基 板を用い、前記第１領域の半導体基板上と第２領域の半 導体基板上とにそれぞれ導電パターンを形成し、前記導 電パターンの形状に沿う状態で前記半導体基板上に第１ 絶縁膜を形成し、該第１絶縁膜上にこの第１絶縁膜とエ ッチング選択比がとれる材料からなる第２絶縁膜をその 表面が平坦になるように形成する第１工程と、 少なくとも (second sub interlevel dielectric layer) 前記第１領域における前記第１絶縁膜と前記 第２絶縁膜とに、前記半導体基板に達するコンタクトホ ールを形成し、該コンタクトホールの内壁に前記第２絶 縁膜とエッチング選択比がとれかつ自身のシリサイド化 を防止する材料からなるサイドウォールを形成する第２ 工程と、 前記コンタクトホール内部に前記サイドウォールを介し て導電材料を埋め込むことによりプラグを形成する第３ 工程と、 エッチングによって前記第２絶縁膜を除去することによ り前記プラグおよび前記第１絶縁膜を露出させ、次いで 前記第２領域の前記第１絶縁膜のみをエッチバックし て、該第２領域における導電パターンの側壁に前記第１ 絶縁膜からなるスペーササイドウォールを形成するとと もに前記第２領域の半導体基板の表面を露出させる第４ 工程と、 前記露出した半導体基板の表面にシリサイド層を形成す る第５工程と、 前記プラグと前記第１絶縁膜と前記導電パターンとを覆 う状態で前記半導体基板上に、前記第１絶縁膜とエッチ ング選択比のとれる材料からなる第３絶縁膜を形成した 後、該第３絶縁膜の表面を平坦化するとともに前記プラ グの上面を露出させる第６工程とを有することを特徴と する半導体装置の製造方法。 JPH1154724A CLAIM 2 【請求項２】 前記半導体基板にメモリ素子 (interlevel dielectric) とロジック 素子とを混載した半導体装置の製造方法であって、 前記半導体基板は、前記第１領域であるメモリ素子の形 成領域と、前記第２領域であるロジック素子の形成領域 とを備えており、 前記第６工程の後、前記メモリ素子の形成領域にキャパ シタを形成する工程を有していることを特徴とする請求 項１記載の半導体装置の製造方法。 JPH1154724A CLAIM 3 【請求項３】 前記キャパシタ (interlevel dielectric) を形成する工程では、前 記第３絶縁膜の上方に金属材料からなる下部電極を形成 し、該下部電極の表面にキャパシタ絶縁膜を形成し、該 キャパシタ絶縁膜の表面に金属材料からなる上部電極を 形成してキャパシタを得ることを特徴とする請求項２記 載の半導体装置の製造方法。 |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric (メモリ素子, キャパシタ) layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
JPH1154724A CLAIM 1 【請求項１】 第１領域と第２領域とを備えた半導体基 板を用い、前記第１領域の半導体基板上と第２領域の半 導体基板上とにそれぞれ導電パターンを形成し、前記導 電パターンの形状に沿う状態で前記半導体基板上に第１ 絶縁膜を形成し、該第１絶縁膜上にこの第１絶縁膜とエ ッチング選択比がとれる材料からなる第２絶縁膜をその 表面が平坦になるように形成する第１工程と、 少なくとも (second sub interlevel dielectric layer) 前記第１領域における前記第１絶縁膜と前記 第２絶縁膜とに、前記半導体基板に達するコンタクトホ ールを形成し、該コンタクトホールの内壁に前記第２絶 縁膜とエッチング選択比がとれかつ自身のシリサイド化 を防止する材料からなるサイドウォールを形成する第２ 工程と、 前記コンタクトホール内部に前記サイドウォールを介し て導電材料を埋め込むことによりプラグを形成する第３ 工程と、 エッチングによって前記第２絶縁膜を除去することによ り前記プラグおよび前記第１絶縁膜を露出させ、次いで 前記第２領域の前記第１絶縁膜のみをエッチバックし て、該第２領域における導電パターンの側壁に前記第１ 絶縁膜からなるスペーササイドウォールを形成するとと もに前記第２領域の半導体基板の表面を露出させる第４ 工程と、 前記露出した半導体基板の表面にシリサイド層を形成す る第５工程と、 前記プラグと前記第１絶縁膜と前記導電パターンとを覆 う状態で前記半導体基板上に、前記第１絶縁膜とエッチ ング選択比のとれる材料からなる第３絶縁膜を形成した 後、該第３絶縁膜の表面を平坦化するとともに前記プラ グの上面を露出させる第６工程とを有することを特徴と する半導体装置の製造方法。 JPH1154724A CLAIM 2 【請求項２】 前記半導体基板にメモリ素子 (interlevel dielectric) とロジック 素子とを混載した半導体装置の製造方法であって、 前記半導体基板は、前記第１領域であるメモリ素子の形 成領域と、前記第２領域であるロジック素子の形成領域 とを備えており、 前記第６工程の後、前記メモリ素子の形成領域にキャパ シタを形成する工程を有していることを特徴とする請求 項１記載の半導体装置の製造方法。 JPH1154724A CLAIM 3 【請求項３】 前記キャパシタ (interlevel dielectric) を形成する工程では、前 記第３絶縁膜の上方に金属材料からなる下部電極を形成 し、該下部電極の表面にキャパシタ絶縁膜を形成し、該 キャパシタ絶縁膜の表面に金属材料からなる上部電極を 形成してキャパシタを得ることを特徴とする請求項２記 載の半導体装置の製造方法。 |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (メモリ素子, キャパシタ) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (製造方法) of said contact region . |
JPH1154724A CLAIM 1 【請求項１】 第１領域と第２領域とを備えた半導体基 板を用い、前記第１領域の半導体基板上と第２領域の半 導体基板上とにそれぞれ導電パターンを形成し、前記導 電パターンの形状に沿う状態で前記半導体基板上に第１ 絶縁膜を形成し、該第１絶縁膜上にこの第１絶縁膜とエ ッチング選択比がとれる材料からなる第２絶縁膜をその 表面が平坦になるように形成する第１工程と、 少なくとも (second sub interlevel dielectric layer) 前記第１領域における前記第１絶縁膜と前記 第２絶縁膜とに、前記半導体基板に達するコンタクトホ ールを形成し、該コンタクトホールの内壁に前記第２絶 縁膜とエッチング選択比がとれかつ自身のシリサイド化 を防止する材料からなるサイドウォールを形成する第２ 工程と、 前記コンタクトホール内部に前記サイドウォールを介し て導電材料を埋め込むことによりプラグを形成する第３ 工程と、 エッチングによって前記第２絶縁膜を除去することによ り前記プラグおよび前記第１絶縁膜を露出させ、次いで 前記第２領域の前記第１絶縁膜のみをエッチバックし て、該第２領域における導電パターンの側壁に前記第１ 絶縁膜からなるスペーササイドウォールを形成するとと もに前記第２領域の半導体基板の表面を露出させる第４ 工程と、 前記露出した半導体基板の表面にシリサイド層を形成す る第５工程と、 前記プラグと前記第１絶縁膜と前記導電パターンとを覆 う状態で前記半導体基板上に、前記第１絶縁膜とエッチ ング選択比のとれる材料からなる第３絶縁膜を形成した 後、該第３絶縁膜の表面を平坦化するとともに前記プラ グの上面を露出させる第６工程とを有することを特徴と する半導体装置の製造方法 (metal layer coupling area) 。 JPH1154724A CLAIM 2 【請求項２】 前記半導体基板にメモリ素子 (interlevel dielectric) とロジック 素子とを混載した半導体装置の製造方法であって、 前記半導体基板は、前記第１領域であるメモリ素子の形 成領域と、前記第２領域であるロジック素子の形成領域 とを備えており、 前記第６工程の後、前記メモリ素子の形成領域にキャパ シタを形成する工程を有していることを特徴とする請求 項１記載の半導体装置の製造方法。 JPH1154724A CLAIM 3 【請求項３】 前記キャパシタ (interlevel dielectric) を形成する工程では、前 記第３絶縁膜の上方に金属材料からなる下部電極を形成 し、該下部電極の表面にキャパシタ絶縁膜を形成し、該 キャパシタ絶縁膜の表面に金属材料からなる上部電極を 形成してキャパシタを得ることを特徴とする請求項２記 載の半導体装置の製造方法。 |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Å thick , said first sub interlevel dielectric (メモリ素子, キャパシタ) layer is in a range of about 1 , 000 to 2 , 000 Å thick , said second etch stop layer is in a range of about 300 to 800 Å thick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Å thick . |
JPH1154724A CLAIM 1 【請求項１】 第１領域と第２領域とを備えた半導体基 板を用い、前記第１領域の半導体基板上と第２領域の半 導体基板上とにそれぞれ導電パターンを形成し、前記導 電パターンの形状に沿う状態で前記半導体基板上に第１ 絶縁膜を形成し、該第１絶縁膜上にこの第１絶縁膜とエ ッチング選択比がとれる材料からなる第２絶縁膜をその 表面が平坦になるように形成する第１工程と、 少なくとも (second sub interlevel dielectric layer) 前記第１領域における前記第１絶縁膜と前記 第２絶縁膜とに、前記半導体基板に達するコンタクトホ ールを形成し、該コンタクトホールの内壁に前記第２絶 縁膜とエッチング選択比がとれかつ自身のシリサイド化 を防止する材料からなるサイドウォールを形成する第２ 工程と、 前記コンタクトホール内部に前記サイドウォールを介し て導電材料を埋め込むことによりプラグを形成する第３ 工程と、 エッチングによって前記第２絶縁膜を除去することによ り前記プラグおよび前記第１絶縁膜を露出させ、次いで 前記第２領域の前記第１絶縁膜のみをエッチバックし て、該第２領域における導電パターンの側壁に前記第１ 絶縁膜からなるスペーササイドウォールを形成するとと もに前記第２領域の半導体基板の表面を露出させる第４ 工程と、 前記露出した半導体基板の表面にシリサイド層を形成す る第５工程と、 前記プラグと前記第１絶縁膜と前記導電パターンとを覆 う状態で前記半導体基板上に、前記第１絶縁膜とエッチ ング選択比のとれる材料からなる第３絶縁膜を形成した 後、該第３絶縁膜の表面を平坦化するとともに前記プラ グの上面を露出させる第６工程とを有することを特徴と する半導体装置の製造方法。 JPH1154724A CLAIM 2 【請求項２】 前記半導体基板にメモリ素子 (interlevel dielectric) とロジック 素子とを混載した半導体装置の製造方法であって、 前記半導体基板は、前記第１領域であるメモリ素子の形 成領域と、前記第２領域であるロジック素子の形成領域 とを備えており、 前記第６工程の後、前記メモリ素子の形成領域にキャパ シタを形成する工程を有していることを特徴とする請求 項１記載の半導体装置の製造方法。 JPH1154724A CLAIM 3 【請求項３】 前記キャパシタ (interlevel dielectric) を形成する工程では、前 記第３絶縁膜の上方に金属材料からなる下部電極を形成 し、該下部電極の表面にキャパシタ絶縁膜を形成し、該 キャパシタ絶縁膜の表面に金属材料からなる上部電極を 形成してキャパシタを得ることを特徴とする請求項２記 載の半導体装置の製造方法。 |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US6097052A Filed: 1997-06-25 Issued: 2000-08-01 Semiconductor device and a method of manufacturing thereof (Original Assignee) Mitsubishi Electric Corp (Current Assignee) Renesas Electronics Corp Yoshinori Tanaka, Mitsuya Kinoshita, Shinya Watanabe, Tatsuo Kasaoka, Moriaki Akazawa, Toshiaki Ogawa |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch (layers stack) stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US6097052A CLAIM 22 . A semiconductor memory device comprising : a semiconductor substrate having a main surface , a MOS transistor having a pair of impurity regions forming source/drain regions at the main surface of said semiconductor substrate , an insulating film covering said MOS transistor , and having a hole reaching to said impurity region , a storage node formed on said insulating film so as to be connected to said impurity region via said hole , a capacitor dielectric film covering said storage node , and cell plate formed on said capacitor dielectric film , wherein said hole is formed by forming a first hole having a first dimension using photolithography , reducing the first dimension to a second dimension less than the first dimension , and using the first hole with the second dimension to form said hole , wherein said storage node has an extending portion on said insulating film , extending in a direction along the upper surface of said insulating film , said extending portion having at least two layers stack (first etch, first etch stop layer, etch process) ed substantially parallel to the main surface of said semiconductor substrate and extending in said direction , wherein said storage node comprises a first portion , a second portion , and a third portion , said first portion being formed on the upper surface of said insulating film to surround the circumference of said hole , said second portion being formed on the upper surface of said insulating film in contact with said first portion and surrounding said first portion , said third portion extending in contact with the upper surface of said first and second portions , and connected to said impurity region via said hole . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch (layers stack) stop layer protects removal of a substrate material (silicon oxide) by an etch process (layers stack) . |
US6097052A CLAIM 1 . A semiconductor device comprising : a semiconductor substrate having a main surface , a conductive region formed at the main surface of said semiconductor substrate , an insulating film formed on said conductive region , and having a hole reaching to said conductive region , and an interconnection film formed on said insulating film , and connected to said conductive region via said hole , wherein said hole is formed by forming a first hole having a first dimension using photolithography , reducing the first dimension to a second dimension less than the first dimension , and using the first hole with the second dimension to form said hole , wherein said interconnection film comprises first and second portions , comprising stacked first and second layers , respectively , extending in a direction along the upper surface of the insulating film , the first portion extending entirely in contact with the upper surface of the insulating film and in the direction substantially parallel to the upper surface of the insulating film , and the second portion extending above the first portion , and wherein there is a boundary between said first and second portions , said boundary including a silicon oxide (substrate material) film . US6097052A CLAIM 22 . A semiconductor memory device comprising : a semiconductor substrate having a main surface , a MOS transistor having a pair of impurity regions forming source/drain regions at the main surface of said semiconductor substrate , an insulating film covering said MOS transistor , and having a hole reaching to said impurity region , a storage node formed on said insulating film so as to be connected to said impurity region via said hole , a capacitor dielectric film covering said storage node , and cell plate formed on said capacitor dielectric film , wherein said hole is formed by forming a first hole having a first dimension using photolithography , reducing the first dimension to a second dimension less than the first dimension , and using the first hole with the second dimension to form said hole , wherein said storage node has an extending portion on said insulating film , extending in a direction along the upper surface of said insulating film , said extending portion having at least two layers stack (first etch, first etch stop layer, etch process) ed substantially parallel to the main surface of said semiconductor substrate and extending in said direction , wherein said storage node comprises a first portion , a second portion , and a third portion , said first portion being formed on the upper surface of said insulating film to surround the circumference of said hole , said second portion being formed on the upper surface of said insulating film in contact with said first portion and surrounding said first portion , said third portion extending in contact with the upper surface of said first and second portions , and connected to said impurity region via said hole . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch (layers stack) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6097052A CLAIM 22 . A semiconductor memory device comprising : a semiconductor substrate having a main surface , a MOS transistor having a pair of impurity regions forming source/drain regions at the main surface of said semiconductor substrate , an insulating film covering said MOS transistor , and having a hole reaching to said impurity region , a storage node formed on said insulating film so as to be connected to said impurity region via said hole , a capacitor dielectric film covering said storage node , and cell plate formed on said capacitor dielectric film , wherein said hole is formed by forming a first hole having a first dimension using photolithography , reducing the first dimension to a second dimension less than the first dimension , and using the first hole with the second dimension to form said hole , wherein said storage node has an extending portion on said insulating film , extending in a direction along the upper surface of said insulating film , said extending portion having at least two layers stack (first etch, first etch stop layer, etch process) ed substantially parallel to the main surface of said semiconductor substrate and extending in said direction , wherein said storage node comprises a first portion , a second portion , and a third portion , said first portion being formed on the upper surface of said insulating film to surround the circumference of said hole , said second portion being formed on the upper surface of said insulating film in contact with said first portion and surrounding said first portion , said third portion extending in contact with the upper surface of said first and second portions , and connected to said impurity region via said hole . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch (layers stack) stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom (two layers) , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US6097052A CLAIM 6 . A semiconductor memory device comprising : a semiconductor substrate having a main surface , a MOS transistor having a pair of impurity regions forming source/drain regions at the main surface of said semiconductor substrate , an insulating film covering said MOS transistor , and having a hole reaching to said impurity region , a storage node formed on said insulating film so as to be connected to said impurity region via said hole , a capacitor dielectric film covering said storage node , and cell plate formed on said capacitor dielectric film , wherein said hole is formed by forming a first hole having a first dimension using photolithography , reducing the first dimension to a second dimension less than the first dimension , and using the first hole with the second dimension to form said hole , wherein said storage node has a portion extending on said insulating film along the upper surface thereof , said extending portion stacked in at least two layers (contact bottom) and extending in said direction , wherein said storage node includes a first portion , a second portion , and a third portion , wherein said first portion is formed at a first level of height on the upper face of said insulating film so as to surround the circumference of said hole , wherein said second portion is formed extending on the upper face of said insulating film at a second level of height lower than said first level of height so as to come into contact with the lower end of said first portion and surrounding said first portion , wherein said third portion extends in contact with the upper face of said first and second portions , and is connected to said impurity region via said hole . US6097052A CLAIM 22 . A semiconductor memory device comprising : a semiconductor substrate having a main surface , a MOS transistor having a pair of impurity regions forming source/drain regions at the main surface of said semiconductor substrate , an insulating film covering said MOS transistor , and having a hole reaching to said impurity region , a storage node formed on said insulating film so as to be connected to said impurity region via said hole , a capacitor dielectric film covering said storage node , and cell plate formed on said capacitor dielectric film , wherein said hole is formed by forming a first hole having a first dimension using photolithography , reducing the first dimension to a second dimension less than the first dimension , and using the first hole with the second dimension to form said hole , wherein said storage node has an extending portion on said insulating film , extending in a direction along the upper surface of said insulating film , said extending portion having at least two layers stack (first etch, first etch stop layer, etch process) ed substantially parallel to the main surface of said semiconductor substrate and extending in said direction , wherein said storage node comprises a first portion , a second portion , and a third portion , said first portion being formed on the upper surface of said insulating film to surround the circumference of said hole , said second portion being formed on the upper surface of said insulating film in contact with said first portion and surrounding said first portion , said third portion extending in contact with the upper surface of said first and second portions , and connected to said impurity region via said hole . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch (layers stack) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6097052A CLAIM 22 . A semiconductor memory device comprising : a semiconductor substrate having a main surface , a MOS transistor having a pair of impurity regions forming source/drain regions at the main surface of said semiconductor substrate , an insulating film covering said MOS transistor , and having a hole reaching to said impurity region , a storage node formed on said insulating film so as to be connected to said impurity region via said hole , a capacitor dielectric film covering said storage node , and cell plate formed on said capacitor dielectric film , wherein said hole is formed by forming a first hole having a first dimension using photolithography , reducing the first dimension to a second dimension less than the first dimension , and using the first hole with the second dimension to form said hole , wherein said storage node has an extending portion on said insulating film , extending in a direction along the upper surface of said insulating film , said extending portion having at least two layers stack (first etch, first etch stop layer, etch process) ed substantially parallel to the main surface of said semiconductor substrate and extending in said direction , wherein said storage node comprises a first portion , a second portion , and a third portion , said first portion being formed on the upper surface of said insulating film to surround the circumference of said hole , said second portion being formed on the upper surface of said insulating film in contact with said first portion and surrounding said first portion , said third portion extending in contact with the upper surface of said first and second portions , and connected to said impurity region via said hole . |
| US7977797B2 CLAIM 13 . An integrated circuit of claim 11 further comprising a floating gate (drain regions) . |
US6097052A CLAIM 6 . A semiconductor memory device comprising : a semiconductor substrate having a main surface , a MOS transistor having a pair of impurity regions forming source/drain regions (floating gate) at the main surface of said semiconductor substrate , an insulating film covering said MOS transistor , and having a hole reaching to said impurity region , a storage node formed on said insulating film so as to be connected to said impurity region via said hole , a capacitor dielectric film covering said storage node , and cell plate formed on said capacitor dielectric film , wherein said hole is formed by forming a first hole having a first dimension using photolithography , reducing the first dimension to a second dimension less than the first dimension , and using the first hole with the second dimension to form said hole , wherein said storage node has a portion extending on said insulating film along the upper surface thereof , said extending portion stacked in at least two layers and extending in said direction , wherein said storage node includes a first portion , a second portion , and a third portion , wherein said first portion is formed at a first level of height on the upper face of said insulating film so as to surround the circumference of said hole , wherein said second portion is formed extending on the upper face of said insulating film at a second level of height lower than said first level of height so as to come into contact with the lower end of said first portion and surrounding said first portion , wherein said third portion extends in contact with the upper face of said first and second portions , and is connected to said impurity region via said hole . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5801094A Filed: 1997-06-12 Issued: 1998-09-01 Dual damascene process (Original Assignee) United Microelectronics Corp (Current Assignee) United Microelectronics Corp Tri-Rung Yew, Meng-Chang Liu, Water Lur, Shih-Wei Sun |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch (layer dielectric, hard mask) stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub (upper surfaces) interlevel dielectric layer over said first etch stop layer ; a second etch (layer dielectric, hard mask) stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5801094A CLAIM 1 . A method of making an integrated circuit having first level conductor structures and second level conductor structures , the method comprising : providing a substrate incorporating one or more integrated circuit devices ; providing an interlayer dielectric (multiple etch, etch process, second etch, etching process, second etch stop layers) layer over the substrate ; providing an etch stop layer over the interlayer dielectric layer ; patterning the etch stop layer to define openings in the patterned etch stop layer corresponding to positions where first level conductor structures are to be formed ; providing an intermetal dielectric layer over the patterned etch stop layer ; forming a second level mask over the intermetal dielectric layer , the second level mask having openings corresponding to positions where second level conductor structures are to be formed ; etching through the openings in the second level mask to form second level conductor openings in the intermetal dielectric layer , and etching through the openings in the patterned etch stop layer to form first level conductor openings in the interlayer dielectric layer and to provide edges of the openings , in the patterned etch stop layer , with a tapered configuration , so that the openings in the patterned etch stop layer provide for a step-free transition between respective ones of the second level conductor openings in the intermetal dielectric layer and the first level conductor openings in the interlayer dielectric layer ; and depositing metal into the second level conductor openings and into the first level conductor openings . US5801094A CLAIM 3 . The method of claim 2 , wherein the removing metal leaves metal plugs in the second level conductor openings having upper surfaces (first sub, first sub interlevel dielectric layer) coplanar with surrounding portions of the intermetal dielectric layer . US5801094A CLAIM 10 . The method of claim 1 , wherein the patterned etch stop layer acts as a hard mask (multiple etch, etch process, second etch, etching process, second etch stop layers) for etching the interlayer dielectric . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer protects removal of a substrate material (silicon oxide) by an etch process (layer dielectric, hard mask) . |
US5801094A CLAIM 1 . A method of making an integrated circuit having first level conductor structures and second level conductor structures , the method comprising : providing a substrate incorporating one or more integrated circuit devices ; providing an interlayer dielectric (multiple etch, etch process, second etch, etching process, second etch stop layers) layer over the substrate ; providing an etch stop layer over the interlayer dielectric layer ; patterning the etch stop layer to define openings in the patterned etch stop layer corresponding to positions where first level conductor structures are to be formed ; providing an intermetal dielectric layer over the patterned etch stop layer ; forming a second level mask over the intermetal dielectric layer , the second level mask having openings corresponding to positions where second level conductor structures are to be formed ; etching through the openings in the second level mask to form second level conductor openings in the intermetal dielectric layer , and etching through the openings in the patterned etch stop layer to form first level conductor openings in the interlayer dielectric layer and to provide edges of the openings , in the patterned etch stop layer , with a tapered configuration , so that the openings in the patterned etch stop layer provide for a step-free transition between respective ones of the second level conductor openings in the intermetal dielectric layer and the first level conductor openings in the interlayer dielectric layer ; and depositing metal into the second level conductor openings and into the first level conductor openings . US5801094A CLAIM 7 . The method of claim 1 , wherein the interlayer dielectric and the intermetal dielectric comprise silicon oxide (substrate material) . US5801094A CLAIM 10 . The method of claim 1 , wherein the patterned etch stop layer acts as a hard mask (multiple etch, etch process, second etch, etching process, second etch stop layers) for etching the interlayer dielectric . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub (upper surfaces) interlevel dielectric layer insulates said contact region . |
US5801094A CLAIM 3 . The method of claim 2 , wherein the removing metal leaves metal plugs in the second level conductor openings having upper surfaces (first sub, first sub interlevel dielectric layer) coplanar with surrounding portions of the intermetal dielectric layer . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch (layer dielectric, hard mask) stop layer protects lower layers during an etching process (layer dielectric, hard mask) . |
US5801094A CLAIM 1 . A method of making an integrated circuit having first level conductor structures and second level conductor structures , the method comprising : providing a substrate incorporating one or more integrated circuit devices ; providing an interlayer dielectric (multiple etch, etch process, second etch, etching process, second etch stop layers) layer over the substrate ; providing an etch stop layer over the interlayer dielectric layer ; patterning the etch stop layer to define openings in the patterned etch stop layer corresponding to positions where first level conductor structures are to be formed ; providing an intermetal dielectric layer over the patterned etch stop layer ; forming a second level mask over the intermetal dielectric layer , the second level mask having openings corresponding to positions where second level conductor structures are to be formed ; etching through the openings in the second level mask to form second level conductor openings in the intermetal dielectric layer , and etching through the openings in the patterned etch stop layer to form first level conductor openings in the interlayer dielectric layer and to provide edges of the openings , in the patterned etch stop layer , with a tapered configuration , so that the openings in the patterned etch stop layer provide for a step-free transition between respective ones of the second level conductor openings in the intermetal dielectric layer and the first level conductor openings in the interlayer dielectric layer ; and depositing metal into the second level conductor openings and into the first level conductor openings . US5801094A CLAIM 10 . The method of claim 1 , wherein the patterned etch stop layer acts as a hard mask (multiple etch, etch process, second etch, etching process, second etch stop layers) for etching the interlayer dielectric . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub (upper surfaces) interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (layer dielectric, hard mask) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5801094A CLAIM 1 . A method of making an integrated circuit having first level conductor structures and second level conductor structures , the method comprising : providing a substrate incorporating one or more integrated circuit devices ; providing an interlayer dielectric (multiple etch, etch process, second etch, etching process, second etch stop layers) layer over the substrate ; providing an etch stop layer over the interlayer dielectric layer ; patterning the etch stop layer to define openings in the patterned etch stop layer corresponding to positions where first level conductor structures are to be formed ; providing an intermetal dielectric layer over the patterned etch stop layer ; forming a second level mask over the intermetal dielectric layer , the second level mask having openings corresponding to positions where second level conductor structures are to be formed ; etching through the openings in the second level mask to form second level conductor openings in the intermetal dielectric layer , and etching through the openings in the patterned etch stop layer to form first level conductor openings in the interlayer dielectric layer and to provide edges of the openings , in the patterned etch stop layer , with a tapered configuration , so that the openings in the patterned etch stop layer provide for a step-free transition between respective ones of the second level conductor openings in the intermetal dielectric layer and the first level conductor openings in the interlayer dielectric layer ; and depositing metal into the second level conductor openings and into the first level conductor openings . US5801094A CLAIM 3 . The method of claim 2 , wherein the removing metal leaves metal plugs in the second level conductor openings having upper surfaces (first sub, first sub interlevel dielectric layer) coplanar with surrounding portions of the intermetal dielectric layer . US5801094A CLAIM 10 . The method of claim 1 , wherein the patterned etch stop layer acts as a hard mask (multiple etch, etch process, second etch, etching process, second etch stop layers) for etching the interlayer dielectric . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub (upper surfaces) interlevel dielectric layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5801094A CLAIM 3 . The method of claim 2 , wherein the removing metal leaves metal plugs in the second level conductor openings having upper surfaces (first sub, first sub interlevel dielectric layer) coplanar with surrounding portions of the intermetal dielectric layer . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch (layer dielectric, hard mask) stop insulation layer comprising a first etch stop layer and a second etch (layer dielectric, hard mask) stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub (upper surfaces) interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US5801094A CLAIM 1 . A method of making an integrated circuit having first level conductor structures and second level conductor structures , the method comprising : providing a substrate incorporating one or more integrated circuit devices ; providing an interlayer dielectric (multiple etch, etch process, second etch, etching process, second etch stop layers) layer over the substrate ; providing an etch stop layer over the interlayer dielectric layer ; patterning the etch stop layer to define openings in the patterned etch stop layer corresponding to positions where first level conductor structures are to be formed ; providing an intermetal dielectric layer over the patterned etch stop layer ; forming a second level mask over the intermetal dielectric layer , the second level mask having openings corresponding to positions where second level conductor structures are to be formed ; etching through the openings in the second level mask to form second level conductor openings in the intermetal dielectric layer , and etching through the openings in the patterned etch stop layer to form first level conductor openings in the interlayer dielectric layer and to provide edges of the openings , in the patterned etch stop layer , with a tapered configuration , so that the openings in the patterned etch stop layer provide for a step-free transition between respective ones of the second level conductor openings in the intermetal dielectric layer and the first level conductor openings in the interlayer dielectric layer ; and depositing metal into the second level conductor openings and into the first level conductor openings . US5801094A CLAIM 3 . The method of claim 2 , wherein the removing metal leaves metal plugs in the second level conductor openings having upper surfaces (first sub, first sub interlevel dielectric layer) coplanar with surrounding portions of the intermetal dielectric layer . US5801094A CLAIM 10 . The method of claim 1 , wherein the patterned etch stop layer acts as a hard mask (multiple etch, etch process, second etch, etching process, second etch stop layers) for etching the interlayer dielectric . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub (upper surfaces) interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (layer dielectric, hard mask) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5801094A CLAIM 1 . A method of making an integrated circuit having first level conductor structures and second level conductor structures , the method comprising : providing a substrate incorporating one or more integrated circuit devices ; providing an interlayer dielectric (multiple etch, etch process, second etch, etching process, second etch stop layers) layer over the substrate ; providing an etch stop layer over the interlayer dielectric layer ; patterning the etch stop layer to define openings in the patterned etch stop layer corresponding to positions where first level conductor structures are to be formed ; providing an intermetal dielectric layer over the patterned etch stop layer ; forming a second level mask over the intermetal dielectric layer , the second level mask having openings corresponding to positions where second level conductor structures are to be formed ; etching through the openings in the second level mask to form second level conductor openings in the intermetal dielectric layer , and etching through the openings in the patterned etch stop layer to form first level conductor openings in the interlayer dielectric layer and to provide edges of the openings , in the patterned etch stop layer , with a tapered configuration , so that the openings in the patterned etch stop layer provide for a step-free transition between respective ones of the second level conductor openings in the intermetal dielectric layer and the first level conductor openings in the interlayer dielectric layer ; and depositing metal into the second level conductor openings and into the first level conductor openings . US5801094A CLAIM 3 . The method of claim 2 , wherein the removing metal leaves metal plugs in the second level conductor openings having upper surfaces (first sub, first sub interlevel dielectric layer) coplanar with surrounding portions of the intermetal dielectric layer . US5801094A CLAIM 10 . The method of claim 1 , wherein the patterned etch stop layer acts as a hard mask (multiple etch, etch process, second etch, etching process, second etch stop layers) for etching the interlayer dielectric . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5880019A Filed: 1997-04-17 Issued: 1999-03-09 Insitu contact descum for self-aligned contact process (Original Assignee) Taiwan Semiconductor Manufacturing Co TSMC Ltd (Current Assignee) Taiwan Semiconductor Manufacturing Co TSMC Ltd Chin-Chuan Hsieh, Chi-Hsin Lo, Sheng-Liang Pan |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region (second contact) coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5880019A CLAIM 1 . A method of forming a self-aligned contact opening with fewer process steps comprising the steps of : a) forming an insulating layer over a semiconductor structure ; b) coating , exposing , and developing a photoresist layer over said insulating layer ; said photoresist layer having a photoresist opening over said insulating layer ; c) baking said photoresist layer ; d) Performing , insitu in a dry etcher , a three stage etch process comprising (1) a first descum step , (2) a dry etch step and (3) a second descum step ; 1) said first descum step removing any trace amount of said photoresist layer which remains in said photoresist opening ; 2) said dry etch step etching said insulating layer using said photoresist layer as a mask forming a first contact opening ; said dry etch step forming a polymer at least on the sidewalls of said first contact opening ; 3) said second descum treatment removing said polymer remaining in said first contact opening ; e) isotropically etching said insulating layer through said photoresist opening forming a second contact (contact region) opening ; f) removing said photoresist layer ; and g) depositing a conductive layer in said second contact opening . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer protects removal of a substrate material by an etch process (etch process) . |
US5880019A CLAIM 1 . A method of forming a self-aligned contact opening with fewer process steps comprising the steps of : a) forming an insulating layer over a semiconductor structure ; b) coating , exposing , and developing a photoresist layer over said insulating layer ; said photoresist layer having a photoresist opening over said insulating layer ; c) baking said photoresist layer ; d) Performing , insitu in a dry etcher , a three stage etch process (etch process) comprising (1) a first descum step , (2) a dry etch step and (3) a second descum step ; 1) said first descum step removing any trace amount of said photoresist layer which remains in said photoresist opening ; 2) said dry etch step etching said insulating layer using said photoresist layer as a mask forming a first contact opening ; said dry etch step forming a polymer at least on the sidewalls of said first contact opening ; 3) said second descum treatment removing said polymer remaining in said first contact opening ; e) isotropically etching said insulating layer through said photoresist opening forming a second contact opening ; f) removing said photoresist layer ; and g) depositing a conductive layer in said second contact opening . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric layer insulates said contact region (second contact) . |
US5880019A CLAIM 1 . A method of forming a self-aligned contact opening with fewer process steps comprising the steps of : a) forming an insulating layer over a semiconductor structure ; b) coating , exposing , and developing a photoresist layer over said insulating layer ; said photoresist layer having a photoresist opening over said insulating layer ; c) baking said photoresist layer ; d) Performing , insitu in a dry etcher , a three stage etch process comprising (1) a first descum step , (2) a dry etch step and (3) a second descum step ; 1) said first descum step removing any trace amount of said photoresist layer which remains in said photoresist opening ; 2) said dry etch step etching said insulating layer using said photoresist layer as a mask forming a first contact opening ; said dry etch step forming a polymer at least on the sidewalls of said first contact opening ; 3) said second descum treatment removing said polymer remaining in said first contact opening ; e) isotropically etching said insulating layer through said photoresist opening forming a second contact (contact region) opening ; f) removing said photoresist layer ; and g) depositing a conductive layer in said second contact opening . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric layer insulates said contact region (second contact) . |
US5880019A CLAIM 1 . A method of forming a self-aligned contact opening with fewer process steps comprising the steps of : a) forming an insulating layer over a semiconductor structure ; b) coating , exposing , and developing a photoresist layer over said insulating layer ; said photoresist layer having a photoresist opening over said insulating layer ; c) baking said photoresist layer ; d) Performing , insitu in a dry etcher , a three stage etch process comprising (1) a first descum step , (2) a dry etch step and (3) a second descum step ; 1) said first descum step removing any trace amount of said photoresist layer which remains in said photoresist opening ; 2) said dry etch step etching said insulating layer using said photoresist layer as a mask forming a first contact opening ; said dry etch step forming a polymer at least on the sidewalls of said first contact opening ; 3) said second descum treatment removing said polymer remaining in said first contact opening ; e) isotropically etching said insulating layer through said photoresist opening forming a second contact (contact region) opening ; f) removing said photoresist layer ; and g) depositing a conductive layer in said second contact opening . |
| US7977797B2 CLAIM 6 . An integrated circuit of claim 1 wherein said spacer region insulates said contact region (second contact) . |
US5880019A CLAIM 1 . A method of forming a self-aligned contact opening with fewer process steps comprising the steps of : a) forming an insulating layer over a semiconductor structure ; b) coating , exposing , and developing a photoresist layer over said insulating layer ; said photoresist layer having a photoresist opening over said insulating layer ; c) baking said photoresist layer ; d) Performing , insitu in a dry etcher , a three stage etch process comprising (1) a first descum step , (2) a dry etch step and (3) a second descum step ; 1) said first descum step removing any trace amount of said photoresist layer which remains in said photoresist opening ; 2) said dry etch step etching said insulating layer using said photoresist layer as a mask forming a first contact opening ; said dry etch step forming a polymer at least on the sidewalls of said first contact opening ; 3) said second descum treatment removing said polymer remaining in said first contact opening ; e) isotropically etching said insulating layer through said photoresist opening forming a second contact (contact region) opening ; f) removing said photoresist layer ; and g) depositing a conductive layer in said second contact opening . |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area of said contact region (second contact) permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
US5880019A CLAIM 1 . A method of forming a self-aligned contact opening with fewer process steps comprising the steps of : a) forming an insulating layer over a semiconductor structure ; b) coating , exposing , and developing a photoresist layer over said insulating layer ; said photoresist layer having a photoresist opening over said insulating layer ; c) baking said photoresist layer ; d) Performing , insitu in a dry etcher , a three stage etch process comprising (1) a first descum step , (2) a dry etch step and (3) a second descum step ; 1) said first descum step removing any trace amount of said photoresist layer which remains in said photoresist opening ; 2) said dry etch step etching said insulating layer using said photoresist layer as a mask forming a first contact opening ; said dry etch step forming a polymer at least on the sidewalls of said first contact opening ; 3) said second descum treatment removing said polymer remaining in said first contact opening ; e) isotropically etching said insulating layer through said photoresist opening forming a second contact (contact region) opening ; f) removing said photoresist layer ; and g) depositing a conductive layer in said second contact opening . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space (said sub) in a portion of said first sub interlevel dielectric layer for said contact region (second contact) is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5880019A CLAIM 1 . A method of forming a self-aligned contact opening with fewer process steps comprising the steps of : a) forming an insulating layer over a semiconductor structure ; b) coating , exposing , and developing a photoresist layer over said insulating layer ; said photoresist layer having a photoresist opening over said insulating layer ; c) baking said photoresist layer ; d) Performing , insitu in a dry etcher , a three stage etch process comprising (1) a first descum step , (2) a dry etch step and (3) a second descum step ; 1) said first descum step removing any trace amount of said photoresist layer which remains in said photoresist opening ; 2) said dry etch step etching said insulating layer using said photoresist layer as a mask forming a first contact opening ; said dry etch step forming a polymer at least on the sidewalls of said first contact opening ; 3) said second descum treatment removing said polymer remaining in said first contact opening ; e) isotropically etching said insulating layer through said photoresist opening forming a second contact (contact region) opening ; f) removing said photoresist layer ; and g) depositing a conductive layer in said second contact opening . US5880019A CLAIM 2 . The method of claim 1 wherein said semiconductor structure comprises a substrate and said conductive layer making contact to said sub (first space) strate in said second self aligned contact opening . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US5880019A CLAIM 13 . A method of forming a self-aligned contact comprising the steps of : a) forming an insulating layer over a semiconductor structure ; said insulating layer having a thickness in a range of between about 2700 and 4000 Å and composed of a material selected from the group consisting of TetraEthylOrthoSilicate (TEOS) , borophosphosilicate glass and oxide ; b) coating , exposing , and developing a photoresist layer over said insulating layer ; said photoresist layer having a photoresist opening over said insulating layer ; said photoresist opening having an open dimension in a range of between about 1 and 3 μm ; c) performing an after developer Inspection of said photoresist layer of said photoresist layer ; d) baking said photoresist layer at a temperature in a range of between about 110° and 130° C . for a time in a range of between about 30 and 50 minutes ; e) performing an insitu a first descum step removing any trace amount of said photoresist layer remaining in said photoresist opening ; and removing between about 100 to 300 Å of said photoresist layer ; f) performing a dry etch step RIE etching said insulating layer using said photoresist layer as a mask forming a first self aligned contact opening and forming (anti reflective coating) a polymer on the sidewalls of said first self aligned contact opening and leaving a thin insulating layer portion on the bottom of said self aligned contact opening ; said thin insulating layer portion having a thickness in a range of between about 100 and 700 Å ; g) performing a second descum treatment removing said polymer remaining in said first self aligned contact opening ; said first descum treatment , said dry etch step and said second descum treatment performed insitu in a dry etcher ; h) isotropically etching said insulating layer through said photoresist opening to enlarge said first self aligned contact opening forming a second self aligned contact opening and removing said thin insulating layer portion ; the isotropic etch of said insulating layer comprises a buffered oxide etch (BOE) comprised of a 10 : 1 HF etch for a time between about 1 and 2 minutes ; i) removing said photoresist layer using an ashing process ; j) depositing a conductive layer in said second self aligned contact opening . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region (second contact) and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US5880019A CLAIM 1 . A method of forming a self-aligned contact opening with fewer process steps comprising the steps of : a) forming an insulating layer over a semiconductor structure ; b) coating , exposing , and developing a photoresist layer over said insulating layer ; said photoresist layer having a photoresist opening over said insulating layer ; c) baking said photoresist layer ; d) Performing , insitu in a dry etcher , a three stage etch process comprising (1) a first descum step , (2) a dry etch step and (3) a second descum step ; 1) said first descum step removing any trace amount of said photoresist layer which remains in said photoresist opening ; 2) said dry etch step etching said insulating layer using said photoresist layer as a mask forming a first contact opening ; said dry etch step forming a polymer at least on the sidewalls of said first contact opening ; 3) said second descum treatment removing said polymer remaining in said first contact opening ; e) isotropically etching said insulating layer through said photoresist opening forming a second contact (contact region) opening ; f) removing said photoresist layer ; and g) depositing a conductive layer in said second contact opening . |
| US7977797B2 CLAIM 13 . An integrated circuit of claim 11 further comprising a floating gate (semiconductor structure) . |
US5880019A CLAIM 1 . A method of forming a self-aligned contact opening with fewer process steps comprising the steps of : a) forming an insulating layer over a semiconductor structure (floating gate) ; b) coating , exposing , and developing a photoresist layer over said insulating layer ; said photoresist layer having a photoresist opening over said insulating layer ; c) baking said photoresist layer ; d) Performing , insitu in a dry etcher , a three stage etch process comprising (1) a first descum step , (2) a dry etch step and (3) a second descum step ; 1) said first descum step removing any trace amount of said photoresist layer which remains in said photoresist opening ; 2) said dry etch step etching said insulating layer using said photoresist layer as a mask forming a first contact opening ; said dry etch step forming a polymer at least on the sidewalls of said first contact opening ; 3) said second descum treatment removing said polymer remaining in said first contact opening ; e) isotropically etching said insulating layer through said photoresist opening forming a second contact opening ; f) removing said photoresist layer ; and g) depositing a conductive layer in said second contact opening . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US5880019A CLAIM 13 . A method of forming a self-aligned contact comprising the steps of : a) forming an insulating layer over a semiconductor structure ; said insulating layer having a thickness in a range of between about 2700 and 4000 Å and composed of a material selected from the group consisting of TetraEthylOrthoSilicate (TEOS) , borophosphosilicate glass and oxide ; b) coating , exposing , and developing a photoresist layer over said insulating layer ; said photoresist layer having a photoresist opening over said insulating layer ; said photoresist opening having an open dimension in a range of between about 1 and 3 μm ; c) performing an after developer Inspection of said photoresist layer of said photoresist layer ; d) baking said photoresist layer at a temperature in a range of between about 110° and 130° C . for a time in a range of between about 30 and 50 minutes ; e) performing an insitu a first descum step removing any trace amount of said photoresist layer remaining in said photoresist opening ; and removing between about 100 to 300 Å of said photoresist layer ; f) performing a dry etch step RIE etching said insulating layer using said photoresist layer as a mask forming a first self aligned contact opening and forming (anti reflective coating) a polymer on the sidewalls of said first self aligned contact opening and leaving a thin insulating layer portion on the bottom of said self aligned contact opening ; said thin insulating layer portion having a thickness in a range of between about 100 and 700 Å ; g) performing a second descum treatment removing said polymer remaining in said first self aligned contact opening ; said first descum treatment , said dry etch step and said second descum treatment performed insitu in a dry etcher ; h) isotropically etching said insulating layer through said photoresist opening to enlarge said first self aligned contact opening forming a second self aligned contact opening and removing said thin insulating layer portion ; the isotropic etch of said insulating layer comprises a buffered oxide etch (BOE) comprised of a 10 : 1 HF etch for a time between about 1 and 2 minutes ; i) removing said photoresist layer using an ashing process ; j) depositing a conductive layer in said second self aligned contact opening . |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region (second contact) is a first range of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5880019A CLAIM 1 . A method of forming a self-aligned contact opening with fewer process steps comprising the steps of : a) forming an insulating layer over a semiconductor structure ; b) coating , exposing , and developing a photoresist layer over said insulating layer ; said photoresist layer having a photoresist opening over said insulating layer ; c) baking said photoresist layer ; d) Performing , insitu in a dry etcher , a three stage etch process comprising (1) a first descum step , (2) a dry etch step and (3) a second descum step ; 1) said first descum step removing any trace amount of said photoresist layer which remains in said photoresist opening ; 2) said dry etch step etching said insulating layer using said photoresist layer as a mask forming a first contact opening ; said dry etch step forming a polymer at least on the sidewalls of said first contact opening ; 3) said second descum treatment removing said polymer remaining in said first contact opening ; e) isotropically etching said insulating layer through said photoresist opening forming a second contact (contact region) opening ; f) removing said photoresist layer ; and g) depositing a conductive layer in said second contact opening . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5935868A Filed: 1997-03-31 Issued: 1999-08-10 Interconnect structure and method to achieve unlanded vias for low dielectric constant materials (Original Assignee) Intel Corp (Current Assignee) Intel Corp Sychyi Fang, Chaunbin Pan, Sing-Mo Tzeng, Chien Chiang |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region (second photoresist layer, first photoresist layer) coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region (second photoresist layer, first photoresist layer) such that a substrate coupling area (second conductive layer) of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch (etch stop layer) stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5935868A CLAIM 4 . A method of forming an interconnect structure , comprising : forming a first conductive layer over a substrate ; forming a first inorganic insulator over said first conductive layer ; etching said first inorganic insulator to form a first inorganic insulator cap ; etching said first conductive layer to form a first conductive structure , wherein said first inorganic insulator cap covers a top surface of said first conductive structure ; forming a low dielectric constant material over said first conductive structure and said first inorganic insulator cap ; planarizing said low dielectric constant material until a top surface of said low dielectric constant material is substantially flush with a top surface of said first inorganic insulator cap , wherein said low dielectric constant material surrounds said first conductive structure ; forming a second inorganic insulator over said low dielectric constant material and said first inorganic insulator cap ; forming a third inorganic insulator over said second inorganic insulator ; patterning a photoresist layer disposed over said third inorganic insulator ; etching said third inorganic insulator , wherein said second inorganic insulator acts as an etch stop layer (second etch) ; removing said photoresist layer ; and etching said second inorganic insulator and said first inorganic insulator cap to form an unlanded via so that a portion of said second inorganic insulator , part of said first inorganic insulator cap , part of said low dielectric constant material and part of said first conductive layer are exposed . US5935868A CLAIM 5 . The method of claim 4 , further comprising : cleaning said unlanded via ; and forming a second conductive layer (substrate coupling area) in said unlanded via . US5935868A CLAIM 23 . A method of forming a damascene interconnect structure , comprising : forming a low dielectric constant material over a substrate ; forming a first inorganic insulator over said low dielectric constant material ; patterning a first photoresist layer (contact region, spacer region) that is disposed above said first inorganic insulator in order to form an opening ; etching said first inorganic insulator ; etching said low dielectric constant material to form said opening ; removing said first photoresist layer ; forming a first conductive layer in said opening and over said first inorganic insulator ; planarizing said first conductive layer until its top surface is substantially planar with a top surface of said first inorganic insulator ; forming a second inorganic insulator over said first conductive layer and said first inorganic insulator ; patterning a second photoresist layer (contact region, spacer region) disposed over said second inorganic insulator to form an unlanded via ; etching said second inorganic insulator to form said unlanded via , wherein said first inorganic insulator acts as an etch-stop layer ; and removing said second photoresist layer . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric layer insulates said contact region (second photoresist layer, first photoresist layer) . |
US5935868A CLAIM 23 . A method of forming a damascene interconnect structure , comprising : forming a low dielectric constant material over a substrate ; forming a first inorganic insulator over said low dielectric constant material ; patterning a first photoresist layer (contact region, spacer region) that is disposed above said first inorganic insulator in order to form an opening ; etching said first inorganic insulator ; etching said low dielectric constant material to form said opening ; removing said first photoresist layer ; forming a first conductive layer in said opening and over said first inorganic insulator ; planarizing said first conductive layer until its top surface is substantially planar with a top surface of said first inorganic insulator ; forming a second inorganic insulator over said first conductive layer and said first inorganic insulator ; patterning a second photoresist layer (contact region, spacer region) disposed over said second inorganic insulator to form an unlanded via ; etching said second inorganic insulator to form said unlanded via , wherein said first inorganic insulator acts as an etch-stop layer ; and removing said second photoresist layer . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch (etch stop layer) stop layer protects lower layers during an etching process . |
US5935868A CLAIM 4 . A method of forming an interconnect structure , comprising : forming a first conductive layer over a substrate ; forming a first inorganic insulator over said first conductive layer ; etching said first inorganic insulator to form a first inorganic insulator cap ; etching said first conductive layer to form a first conductive structure , wherein said first inorganic insulator cap covers a top surface of said first conductive structure ; forming a low dielectric constant material over said first conductive structure and said first inorganic insulator cap ; planarizing said low dielectric constant material until a top surface of said low dielectric constant material is substantially flush with a top surface of said first inorganic insulator cap , wherein said low dielectric constant material surrounds said first conductive structure ; forming a second inorganic insulator over said low dielectric constant material and said first inorganic insulator cap ; forming a third inorganic insulator over said second inorganic insulator ; patterning a photoresist layer disposed over said third inorganic insulator ; etching said third inorganic insulator , wherein said second inorganic insulator acts as an etch stop layer (second etch) ; removing said photoresist layer ; and etching said second inorganic insulator and said first inorganic insulator cap to form an unlanded via so that a portion of said second inorganic insulator , part of said first inorganic insulator cap , part of said low dielectric constant material and part of said first conductive layer are exposed . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric layer insulates said contact region (second photoresist layer, first photoresist layer) . |
US5935868A CLAIM 23 . A method of forming a damascene interconnect structure , comprising : forming a low dielectric constant material over a substrate ; forming a first inorganic insulator over said low dielectric constant material ; patterning a first photoresist layer (contact region, spacer region) that is disposed above said first inorganic insulator in order to form an opening ; etching said first inorganic insulator ; etching said low dielectric constant material to form said opening ; removing said first photoresist layer ; forming a first conductive layer in said opening and over said first inorganic insulator ; planarizing said first conductive layer until its top surface is substantially planar with a top surface of said first inorganic insulator ; forming a second inorganic insulator over said first conductive layer and said first inorganic insulator ; patterning a second photoresist layer (contact region, spacer region) disposed over said second inorganic insulator to form an unlanded via ; etching said second inorganic insulator to form said unlanded via , wherein said first inorganic insulator acts as an etch-stop layer ; and removing said second photoresist layer . |
| US7977797B2 CLAIM 6 . An integrated circuit of claim 1 wherein said spacer region (second photoresist layer, first photoresist layer) insulates said contact region (second photoresist layer, first photoresist layer) . |
US5935868A CLAIM 23 . A method of forming a damascene interconnect structure , comprising : forming a low dielectric constant material over a substrate ; forming a first inorganic insulator over said low dielectric constant material ; patterning a first photoresist layer (contact region, spacer region) that is disposed above said first inorganic insulator in order to form an opening ; etching said first inorganic insulator ; etching said low dielectric constant material to form said opening ; removing said first photoresist layer ; forming a first conductive layer in said opening and over said first inorganic insulator ; planarizing said first conductive layer until its top surface is substantially planar with a top surface of said first inorganic insulator ; forming a second inorganic insulator over said first conductive layer and said first inorganic insulator ; patterning a second photoresist layer (contact region, spacer region) disposed over said second inorganic insulator to form an unlanded via ; etching said second inorganic insulator to form said unlanded via , wherein said first inorganic insulator acts as an etch-stop layer ; and removing said second photoresist layer . |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area (second conductive layer) of said contact region (second photoresist layer, first photoresist layer) permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
US5935868A CLAIM 5 . The method of claim 4 , further comprising : cleaning said unlanded via ; and forming a second conductive layer (substrate coupling area) in said unlanded via . US5935868A CLAIM 23 . A method of forming a damascene interconnect structure , comprising : forming a low dielectric constant material over a substrate ; forming a first inorganic insulator over said low dielectric constant material ; patterning a first photoresist layer (contact region, spacer region) that is disposed above said first inorganic insulator in order to form an opening ; etching said first inorganic insulator ; etching said low dielectric constant material to form said opening ; removing said first photoresist layer ; forming a first conductive layer in said opening and over said first inorganic insulator ; planarizing said first conductive layer until its top surface is substantially planar with a top surface of said first inorganic insulator ; forming a second inorganic insulator over said first conductive layer and said first inorganic insulator ; patterning a second photoresist layer (contact region, spacer region) disposed over said second inorganic insulator to form an unlanded via ; etching said second inorganic insulator to form said unlanded via , wherein said first inorganic insulator acts as an etch-stop layer ; and removing said second photoresist layer . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (etch stop layer) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5935868A CLAIM 4 . A method of forming an interconnect structure , comprising : forming a first conductive layer over a substrate ; forming a first inorganic insulator over said first conductive layer ; etching said first inorganic insulator to form a first inorganic insulator cap ; etching said first conductive layer to form a first conductive structure , wherein said first inorganic insulator cap covers a top surface of said first conductive structure ; forming a low dielectric constant material over said first conductive structure and said first inorganic insulator cap ; planarizing said low dielectric constant material until a top surface of said low dielectric constant material is substantially flush with a top surface of said first inorganic insulator cap , wherein said low dielectric constant material surrounds said first conductive structure ; forming a second inorganic insulator over said low dielectric constant material and said first inorganic insulator cap ; forming a third inorganic insulator over said second inorganic insulator ; patterning a photoresist layer disposed over said third inorganic insulator ; etching said third inorganic insulator , wherein said second inorganic insulator acts as an etch stop layer (second etch) ; removing said photoresist layer ; and etching said second inorganic insulator and said first inorganic insulator cap to form an unlanded via so that a portion of said second inorganic insulator , part of said first inorganic insulator cap , part of said low dielectric constant material and part of said first conductive layer are exposed . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric layer for said contact region (second photoresist layer, first photoresist layer) is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5935868A CLAIM 23 . A method of forming a damascene interconnect structure , comprising : forming a low dielectric constant material over a substrate ; forming a first inorganic insulator over said low dielectric constant material ; patterning a first photoresist layer (contact region, spacer region) that is disposed above said first inorganic insulator in order to form an opening ; etching said first inorganic insulator ; etching said low dielectric constant material to form said opening ; removing said first photoresist layer ; forming a first conductive layer in said opening and over said first inorganic insulator ; planarizing said first conductive layer until its top surface is substantially planar with a top surface of said first inorganic insulator ; forming a second inorganic insulator over said first conductive layer and said first inorganic insulator ; patterning a second photoresist layer (contact region, spacer region) disposed over said second inorganic insulator to form an unlanded via ; etching said second inorganic insulator to form said unlanded via , wherein said first inorganic insulator acts as an etch-stop layer ; and removing said second photoresist layer . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US5935868A CLAIM 5 . The method of claim 4 , further comprising : cleaning said unlanded via ; and forming (anti reflective coating) a second conductive layer in said unlanded via . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch (etch stop layer) stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region (second photoresist layer, first photoresist layer) and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom (top portion) , such that a substrate coupling area (second conductive layer) of said contact region is smaller than a metal layer coupling area of said contact region . |
US5935868A CLAIM 4 . A method of forming an interconnect structure , comprising : forming a first conductive layer over a substrate ; forming a first inorganic insulator over said first conductive layer ; etching said first inorganic insulator to form a first inorganic insulator cap ; etching said first conductive layer to form a first conductive structure , wherein said first inorganic insulator cap covers a top surface of said first conductive structure ; forming a low dielectric constant material over said first conductive structure and said first inorganic insulator cap ; planarizing said low dielectric constant material until a top surface of said low dielectric constant material is substantially flush with a top surface of said first inorganic insulator cap , wherein said low dielectric constant material surrounds said first conductive structure ; forming a second inorganic insulator over said low dielectric constant material and said first inorganic insulator cap ; forming a third inorganic insulator over said second inorganic insulator ; patterning a photoresist layer disposed over said third inorganic insulator ; etching said third inorganic insulator , wherein said second inorganic insulator acts as an etch stop layer (second etch) ; removing said photoresist layer ; and etching said second inorganic insulator and said first inorganic insulator cap to form an unlanded via so that a portion of said second inorganic insulator , part of said first inorganic insulator cap , part of said low dielectric constant material and part of said first conductive layer are exposed . US5935868A CLAIM 5 . The method of claim 4 , further comprising : cleaning said unlanded via ; and forming a second conductive layer (substrate coupling area) in said unlanded via . US5935868A CLAIM 20 . The interconnect structure of claim 19 , wherein said unlanded via further includes a middle portion that exposes a second inorganic insulator , and a top portion (contact bottom) that exposes a third inorganic insulator that can be selectively etched without etching through said second inorganic insulator , wherein said middle portion is disposed above said lower portion but is disposed below said top portion . US5935868A CLAIM 23 . A method of forming a damascene interconnect structure , comprising : forming a low dielectric constant material over a substrate ; forming a first inorganic insulator over said low dielectric constant material ; patterning a first photoresist layer (contact region, spacer region) that is disposed above said first inorganic insulator in order to form an opening ; etching said first inorganic insulator ; etching said low dielectric constant material to form said opening ; removing said first photoresist layer ; forming a first conductive layer in said opening and over said first inorganic insulator ; planarizing said first conductive layer until its top surface is substantially planar with a top surface of said first inorganic insulator ; forming a second inorganic insulator over said first conductive layer and said first inorganic insulator ; patterning a second photoresist layer (contact region, spacer region) disposed over said second inorganic insulator to form an unlanded via ; etching said second inorganic insulator to form said unlanded via , wherein said first inorganic insulator acts as an etch-stop layer ; and removing said second photoresist layer . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (etch stop layer) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5935868A CLAIM 4 . A method of forming an interconnect structure , comprising : forming a first conductive layer over a substrate ; forming a first inorganic insulator over said first conductive layer ; etching said first inorganic insulator to form a first inorganic insulator cap ; etching said first conductive layer to form a first conductive structure , wherein said first inorganic insulator cap covers a top surface of said first conductive structure ; forming a low dielectric constant material over said first conductive structure and said first inorganic insulator cap ; planarizing said low dielectric constant material until a top surface of said low dielectric constant material is substantially flush with a top surface of said first inorganic insulator cap , wherein said low dielectric constant material surrounds said first conductive structure ; forming a second inorganic insulator over said low dielectric constant material and said first inorganic insulator cap ; forming a third inorganic insulator over said second inorganic insulator ; patterning a photoresist layer disposed over said third inorganic insulator ; etching said third inorganic insulator , wherein said second inorganic insulator acts as an etch stop layer (second etch) ; removing said photoresist layer ; and etching said second inorganic insulator and said first inorganic insulator cap to form an unlanded via so that a portion of said second inorganic insulator , part of said first inorganic insulator cap , part of said low dielectric constant material and part of said first conductive layer are exposed . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US5935868A CLAIM 5 . The method of claim 4 , further comprising : cleaning said unlanded via ; and forming (anti reflective coating) a second conductive layer in said unlanded via . |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region (second photoresist layer, first photoresist layer) is a first range of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5935868A CLAIM 23 . A method of forming a damascene interconnect structure , comprising : forming a low dielectric constant material over a substrate ; forming a first inorganic insulator over said low dielectric constant material ; patterning a first photoresist layer (contact region, spacer region) that is disposed above said first inorganic insulator in order to form an opening ; etching said first inorganic insulator ; etching said low dielectric constant material to form said opening ; removing said first photoresist layer ; forming a first conductive layer in said opening and over said first inorganic insulator ; planarizing said first conductive layer until its top surface is substantially planar with a top surface of said first inorganic insulator ; forming a second inorganic insulator over said first conductive layer and said first inorganic insulator ; patterning a second photoresist layer (contact region, spacer region) disposed over said second inorganic insulator to form an unlanded via ; etching said second inorganic insulator to form said unlanded via , wherein said first inorganic insulator acts as an etch-stop layer ; and removing said second photoresist layer . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5757045A Filed: 1997-03-24 Issued: 1998-05-26 CMOS device structure with reduced risk of salicide bridging and reduced resistance via use of a ultra shallow, junction extension, ion implantation (Original Assignee) Taiwan Semiconductor Manufacturing Co TSMC Ltd (Current Assignee) Taiwan Semiconductor Manufacturing Co TSMC Ltd Chaochieh Tsai, Shun-Liang Hsu |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (contact hole, MOS device) layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5757045A CLAIM 1 . A complimentary metal oxide semiconductor , (CMOS) device structure , on a semiconductor substrate , comprising : field oxide regions in said semiconductor substrate ; a device region between said field oxide regions ; a polysilicon gate structure on said semiconductor substrate , in the center of said device region , with metal silicide on the top surface of said polysilicon gate structure ; an insulator spacer , between about 100 to 400 Angstroms in thickness , comprised of a vertical spacer component , located on the sides of said polysilicon gate structure , and a horizontal spacer component , located on the top surface of said semiconductor substrate , extending between about 1000 to 3000 Angstroms , in length , from the side of said polysilicon gate structure ; a heavily doped source and drain region , located in the surface of said semiconductor substrate , between a field oxide region and said polysilicon gate structure , and underlying said overlying horizontal spacer component , at a point where said horizontal spacer component is between about 500 to 1500 Angstroms from the edge of said polysilicon gate structure ; a metal silicide layer on the region of said heavily source and drain region not covered by said horizontal spacer component ; a space in said semiconductor substrate , between region of said heavily doped source and drain region , located under said horizontal spacer component , and the edge of said polysilicon gate structure , used for a peripheral channel region ; a pocket ion implanted region , opposite in conductivity type to said heavily doped source and drain region , in said peripheral channel region , to a depth between the top surface of said semiconductor substrate , and the bottom of said heavily doped source and drain region ; an ultra lightly doped source and drain region , the same conductivity type as said heavily doped source and drain region , in said peripheral channel region , to a depth of about one half the depth of said pocket ion implanted region ; an ultra shallow junction extension region , in said peripheral channel region , to a depth of about one half the depth of said ultra lightly doped source and drain region , with same conductivity type as said ultra lightly doped source and drain region ; an insulator layer on the top surface of said semiconductor substrate , including said insulator layer on said polysilicon gate structure , on said metal silicide on said heavily doped source and drain region ; contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) s , in said insulator layer , to said metal silicide on said heavily doped source and drain regions , and to said metal silicide on said polysilicon gate structure ; and an metal interconnect structure , contacting said heavily doped source and drain region , and said polysilicon gate structure , in said contact hole . US5757045A CLAIM 2 . The CMOS device (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) structure of claim 1 , wherein said polysilicon gate structure is between about 1000 to 3500 Angstroms in width . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (contact hole, MOS device) layer insulates said contact region . |
US5757045A CLAIM 1 . A complimentary metal oxide semiconductor , (CMOS) device structure , on a semiconductor substrate , comprising : field oxide regions in said semiconductor substrate ; a device region between said field oxide regions ; a polysilicon gate structure on said semiconductor substrate , in the center of said device region , with metal silicide on the top surface of said polysilicon gate structure ; an insulator spacer , between about 100 to 400 Angstroms in thickness , comprised of a vertical spacer component , located on the sides of said polysilicon gate structure , and a horizontal spacer component , located on the top surface of said semiconductor substrate , extending between about 1000 to 3000 Angstroms , in length , from the side of said polysilicon gate structure ; a heavily doped source and drain region , located in the surface of said semiconductor substrate , between a field oxide region and said polysilicon gate structure , and underlying said overlying horizontal spacer component , at a point where said horizontal spacer component is between about 500 to 1500 Angstroms from the edge of said polysilicon gate structure ; a metal silicide layer on the region of said heavily source and drain region not covered by said horizontal spacer component ; a space in said semiconductor substrate , between region of said heavily doped source and drain region , located under said horizontal spacer component , and the edge of said polysilicon gate structure , used for a peripheral channel region ; a pocket ion implanted region , opposite in conductivity type to said heavily doped source and drain region , in said peripheral channel region , to a depth between the top surface of said semiconductor substrate , and the bottom of said heavily doped source and drain region ; an ultra lightly doped source and drain region , the same conductivity type as said heavily doped source and drain region , in said peripheral channel region , to a depth of about one half the depth of said pocket ion implanted region ; an ultra shallow junction extension region , in said peripheral channel region , to a depth of about one half the depth of said ultra lightly doped source and drain region , with same conductivity type as said ultra lightly doped source and drain region ; an insulator layer on the top surface of said semiconductor substrate , including said insulator layer on said polysilicon gate structure , on said metal silicide on said heavily doped source and drain region ; contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) s , in said insulator layer , to said metal silicide on said heavily doped source and drain regions , and to said metal silicide on said polysilicon gate structure ; and an metal interconnect structure , contacting said heavily doped source and drain region , and said polysilicon gate structure , in said contact hole . US5757045A CLAIM 2 . The CMOS device (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) structure of claim 1 , wherein said polysilicon gate structure is between about 1000 to 3500 Angstroms in width . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (contact hole, MOS device) layer insulates said contact region . |
US5757045A CLAIM 1 . A complimentary metal oxide semiconductor , (CMOS) device structure , on a semiconductor substrate , comprising : field oxide regions in said semiconductor substrate ; a device region between said field oxide regions ; a polysilicon gate structure on said semiconductor substrate , in the center of said device region , with metal silicide on the top surface of said polysilicon gate structure ; an insulator spacer , between about 100 to 400 Angstroms in thickness , comprised of a vertical spacer component , located on the sides of said polysilicon gate structure , and a horizontal spacer component , located on the top surface of said semiconductor substrate , extending between about 1000 to 3000 Angstroms , in length , from the side of said polysilicon gate structure ; a heavily doped source and drain region , located in the surface of said semiconductor substrate , between a field oxide region and said polysilicon gate structure , and underlying said overlying horizontal spacer component , at a point where said horizontal spacer component is between about 500 to 1500 Angstroms from the edge of said polysilicon gate structure ; a metal silicide layer on the region of said heavily source and drain region not covered by said horizontal spacer component ; a space in said semiconductor substrate , between region of said heavily doped source and drain region , located under said horizontal spacer component , and the edge of said polysilicon gate structure , used for a peripheral channel region ; a pocket ion implanted region , opposite in conductivity type to said heavily doped source and drain region , in said peripheral channel region , to a depth between the top surface of said semiconductor substrate , and the bottom of said heavily doped source and drain region ; an ultra lightly doped source and drain region , the same conductivity type as said heavily doped source and drain region , in said peripheral channel region , to a depth of about one half the depth of said pocket ion implanted region ; an ultra shallow junction extension region , in said peripheral channel region , to a depth of about one half the depth of said ultra lightly doped source and drain region , with same conductivity type as said ultra lightly doped source and drain region ; an insulator layer on the top surface of said semiconductor substrate , including said insulator layer on said polysilicon gate structure , on said metal silicide on said heavily doped source and drain region ; contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) s , in said insulator layer , to said metal silicide on said heavily doped source and drain regions , and to said metal silicide on said polysilicon gate structure ; and an metal interconnect structure , contacting said heavily doped source and drain region , and said polysilicon gate structure , in said contact hole . US5757045A CLAIM 2 . The CMOS device (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) structure of claim 1 , wherein said polysilicon gate structure is between about 1000 to 3500 Angstroms in width . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (contact hole, MOS device) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5757045A CLAIM 2 . The CMOS device (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) structure of claim 1 , wherein said polysilicon gate structure is between about 1000 to 3500 Angstroms in width . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric (contact hole, MOS device) layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5757045A CLAIM 2 . The CMOS device (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) structure of claim 1 , wherein said polysilicon gate structure is between about 1000 to 3500 Angstroms in width . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (contact hole, MOS device) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US5757045A CLAIM 2 . The CMOS device (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) structure of claim 1 , wherein said polysilicon gate structure is between about 1000 to 3500 Angstroms in width . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (contact hole, MOS device) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5757045A CLAIM 2 . The CMOS device (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) structure of claim 1 , wherein said polysilicon gate structure is between about 1000 to 3500 Angstroms in width . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US6077774A Filed: 1997-03-19 Issued: 2000-06-20 Method of forming ultra-thin and conformal diffusion barriers encapsulating copper (Original Assignee) Texas Instruments Inc (Current Assignee) Texas Instruments Inc Qi-Zhong Hong, Wei-Yung Hsu |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch (tetraethyl orthosilicate) stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch (tetraethyl orthosilicate) stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US6077774A CLAIM 13 . The method of claim 10 , wherein said transforming step further comprises depositing a layer of silicon dioxide , plasma-enhanced tetraethyl orthosilicate (multiple etch, second etch) , borophosphosilicate glass , low-k spin-on glass , or polymer over said surface of said metal conductor . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch (tetraethyl orthosilicate) stop layer protects lower layers during an etching process . |
US6077774A CLAIM 13 . The method of claim 10 , wherein said transforming step further comprises depositing a layer of silicon dioxide , plasma-enhanced tetraethyl orthosilicate (multiple etch, second etch) , borophosphosilicate glass , low-k spin-on glass , or polymer over said surface of said metal conductor . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (tetraethyl orthosilicate) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6077774A CLAIM 13 . The method of claim 10 , wherein said transforming step further comprises depositing a layer of silicon dioxide , plasma-enhanced tetraethyl orthosilicate (multiple etch, second etch) , borophosphosilicate glass , low-k spin-on glass , or polymer over said surface of said metal conductor . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space (said sub) in a portion of said first sub interlevel dielectric layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US6077774A CLAIM 15 . A method of forming diffusion barrier around a metal conductor in a semiconductor device , comprising the steps of : flowing a first metal precursor gas onto a first dielectric layer of a substrate of material , wherein said first dielectric layer comprises a material selected from the group consisting of oxides , carbides and combinations thereof ; heating said first metal precursor and said first dielectric layer to a first temperature , to form a first diffusion barrier on a surface of said first dielectric layer ; forming the metal conductor on said sub (first space) strate ; flowing a second metal precursor gas onto a surface of the metal conductor to form a metal layer on said metal conductor ; and heating said metal layer to a second temperature , to form a second diffusion barrier on said surface of the metal conductor by reacting said metal layer with a material selected from the group consisting of oxides and carbides to form a second diffusion barrier . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch (tetraethyl orthosilicate) stop insulation layer comprising a first etch stop layer and a second etch (tetraethyl orthosilicate) stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US6077774A CLAIM 13 . The method of claim 10 , wherein said transforming step further comprises depositing a layer of silicon dioxide , plasma-enhanced tetraethyl orthosilicate (multiple etch, second etch) , borophosphosilicate glass , low-k spin-on glass , or polymer over said surface of said metal conductor . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (tetraethyl orthosilicate) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6077774A CLAIM 13 . The method of claim 10 , wherein said transforming step further comprises depositing a layer of silicon dioxide , plasma-enhanced tetraethyl orthosilicate (multiple etch, second etch) , borophosphosilicate glass , low-k spin-on glass , or polymer over said surface of said metal conductor . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5789316A Filed: 1997-03-10 Issued: 1998-08-04 Self-aligned method for forming a narrow via (Original Assignee) Vanguard International Semiconductor Corp (Current Assignee) Vanguard International Semiconductor Corp Chih-Yuan Lu |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region (gate electrodes) such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5789316A CLAIM 16 . A method for forming a via through a dielectric layer formed between a pair of gate electrodes (spacer region) within an adjoining pair of field effect transistors (FETs) comprising : forming within and upon a semiconductor substrate an adjoining pair of field effect transistors (FETs) which share a source/drain region formed within the semiconductor substrate , the pair of field effect transistors (FETs) having a pair of gate electrodes separated by a separation width over the semiconductor substrate , the separation width over the semiconductor substrate being no less than the width of a narrow via desired to be formed through a portion of a first dielectric layer formed between the pair of gate electrodes plus two times a registration tolerance of a photoexposure apparatus employed in defining the location of a wide via from which is formed the narrow via plus two times a minimum integrated circuit layer width separating the narrow via from each gate electrode within the pair of gate electrodes ; forming upon the semiconductor substrate including the pair of field effect transistors (FETs) the first dielectric layer ; forming through the portion of the first dielectric layer separated by the pair of gate electrodes the wide via , the wide via having a width equal to the width of the narrow via plus two times the minimum integrated circuit layer width separating the narrow via from each gate electrode within the pair of gate electrodes ; forming conformally into the wide via a conformal second dielectric layer of thickness substantially equal to the minimum integrated circuit layer width separating the narrow via from each gate electrode within the pair of gate electrodes ; and anisotropically etching the conformal second dielectric layer to remove completely a central portion of the conformal second dielectric layer from the bottom of the wide via while not substantially etching the portions of the conformal second dielectric layer formed upon the sidewalls of the wide via , thus forming a narrow via coaxial through the first dielectric layer at the location of the wide via . |
| US7977797B2 CLAIM 6 . An integrated circuit of claim 1 wherein said spacer region (gate electrodes) insulates said contact region . |
US5789316A CLAIM 16 . A method for forming a via through a dielectric layer formed between a pair of gate electrodes (spacer region) within an adjoining pair of field effect transistors (FETs) comprising : forming within and upon a semiconductor substrate an adjoining pair of field effect transistors (FETs) which share a source/drain region formed within the semiconductor substrate , the pair of field effect transistors (FETs) having a pair of gate electrodes separated by a separation width over the semiconductor substrate , the separation width over the semiconductor substrate being no less than the width of a narrow via desired to be formed through a portion of a first dielectric layer formed between the pair of gate electrodes plus two times a registration tolerance of a photoexposure apparatus employed in defining the location of a wide via from which is formed the narrow via plus two times a minimum integrated circuit layer width separating the narrow via from each gate electrode within the pair of gate electrodes ; forming upon the semiconductor substrate including the pair of field effect transistors (FETs) the first dielectric layer ; forming through the portion of the first dielectric layer separated by the pair of gate electrodes the wide via , the wide via having a width equal to the width of the narrow via plus two times the minimum integrated circuit layer width separating the narrow via from each gate electrode within the pair of gate electrodes ; forming conformally into the wide via a conformal second dielectric layer of thickness substantially equal to the minimum integrated circuit layer width separating the narrow via from each gate electrode within the pair of gate electrodes ; and anisotropically etching the conformal second dielectric layer to remove completely a central portion of the conformal second dielectric layer from the bottom of the wide via while not substantially etching the portions of the conformal second dielectric layer formed upon the sidewalls of the wide via , thus forming a narrow via coaxial through the first dielectric layer at the location of the wide via . |
| US7977797B2 CLAIM 13 . An integrated circuit of claim 11 further comprising a floating gate (semiconductor structure, drain region) . |
US5789316A CLAIM 8 . The method of claim 5 wherein the integrated circuit structures are chosen from the group of integrated circuit structures consisting of integrated circuit conductor structures , integrated circuit semiconductor structure (floating gate) s and integrated circuit insulator structures . US5789316A CLAIM 16 . A method for forming a via through a dielectric layer formed between a pair of gate electrodes within an adjoining pair of field effect transistors (FETs) comprising : forming within and upon a semiconductor substrate an adjoining pair of field effect transistors (FETs) which share a source/drain region (floating gate) formed within the semiconductor substrate , the pair of field effect transistors (FETs) having a pair of gate electrodes separated by a separation width over the semiconductor substrate , the separation width over the semiconductor substrate being no less than the width of a narrow via desired to be formed through a portion of a first dielectric layer formed between the pair of gate electrodes plus two times a registration tolerance of a photoexposure apparatus employed in defining the location of a wide via from which is formed the narrow via plus two times a minimum integrated circuit layer width separating the narrow via from each gate electrode within the pair of gate electrodes ; forming upon the semiconductor substrate including the pair of field effect transistors (FETs) the first dielectric layer ; forming through the portion of the first dielectric layer separated by the pair of gate electrodes the wide via , the wide via having a width equal to the width of the narrow via plus two times the minimum integrated circuit layer width separating the narrow via from each gate electrode within the pair of gate electrodes ; forming conformally into the wide via a conformal second dielectric layer of thickness substantially equal to the minimum integrated circuit layer width separating the narrow via from each gate electrode within the pair of gate electrodes ; and anisotropically etching the conformal second dielectric layer to remove completely a central portion of the conformal second dielectric layer from the bottom of the wide via while not substantially etching the portions of the conformal second dielectric layer formed upon the sidewalls of the wide via , thus forming a narrow via coaxial through the first dielectric layer at the location of the wide via . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5874358A Filed: 1997-02-25 Issued: 1999-02-23 Via hole profile and method of fabrication (Original Assignee) Intel Corp (Current Assignee) Intel Corp Alan M. Myers, Peter K. Charvat, Thomas A. Letson, Shi-Ning Yang, Peng Bai |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area (second conductive layer) of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch (wet etch, dry etch, first etch) stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch (wet etch, dry etch, first etch) stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch (wet etch, dry etch, first etch) stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5874358A CLAIM 1 . A method of forming an interconnection structure of an integrated circuit formed on a semiconductor substrate comprising the steps of : forming a first conductive layer comprising a first metal above said substrate ; forming a second conductive layer (substrate coupling area) on said first conductive layer said second conductive layer comprising a second metal-first metal compound ; forming an insulating layer over said second conductive layer ; forming a first opening through said insulating layer , and said second conductive layer ; and forming a second opening in said first conductive layer beneath said first opening wherein said second opening is wider than said first opening in said second conductive layer . US5874358A CLAIM 3 . The method of claim 2 wherein said etchant is a wet etch (multiple etch, etch process, second etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, second etch stop layers) ant . US5874358A CLAIM 10 . The process of claim 8 wherein said first etch (multiple etch, etch process, second etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, second etch stop layers) is a dry etch (multiple etch, etch process, second etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, second etch stop layers) . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch (wet etch, dry etch, first etch) stop layer protects removal of a substrate material by an etch process (wet etch, dry etch, first etch) . |
US5874358A CLAIM 3 . The method of claim 2 wherein said etchant is a wet etch (multiple etch, etch process, second etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, second etch stop layers) ant . US5874358A CLAIM 10 . The process of claim 8 wherein said first etch (multiple etch, etch process, second etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, second etch stop layers) is a dry etch (multiple etch, etch process, second etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, second etch stop layers) . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch (wet etch, dry etch, first etch) stop layer protects lower layers during an etching process (alloy layer) . |
US5874358A CLAIM 3 . The method of claim 2 wherein said etchant is a wet etch (multiple etch, etch process, second etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, second etch stop layers) ant . US5874358A CLAIM 5 . The method of claim 1 wherein said first conductive layer is an aluminum alloy layer (etching process) . US5874358A CLAIM 10 . The process of claim 8 wherein said first etch (multiple etch, etch process, second etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, second etch stop layers) is a dry etch (multiple etch, etch process, second etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, second etch stop layers) . |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area (second conductive layer) of said contact region permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
US5874358A CLAIM 1 . A method of forming an interconnection structure of an integrated circuit formed on a semiconductor substrate comprising the steps of : forming a first conductive layer comprising a first metal above said substrate ; forming a second conductive layer (substrate coupling area) on said first conductive layer said second conductive layer comprising a second metal-first metal compound ; forming an insulating layer over said second conductive layer ; forming a first opening through said insulating layer , and said second conductive layer ; and forming a second opening in said first conductive layer beneath said first opening wherein said second opening is wider than said first opening in said second conductive layer . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch (wet etch, dry etch, first etch) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (wet etch, dry etch, first etch) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5874358A CLAIM 3 . The method of claim 2 wherein said etchant is a wet etch (multiple etch, etch process, second etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, second etch stop layers) ant . US5874358A CLAIM 10 . The process of claim 8 wherein said first etch (multiple etch, etch process, second etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, second etch stop layers) is a dry etch (multiple etch, etch process, second etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, second etch stop layers) . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space (said sub) in a portion of said first sub interlevel dielectric layer for said contact region is in a first range (time t) of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5874358A CLAIM 1 . A method of forming an interconnection structure of an integrated circuit formed on a semiconductor substrate comprising the steps of : forming a first conductive layer comprising a first metal above said sub (first space) strate ; forming a second conductive layer on said first conductive layer said second conductive layer comprising a second metal-first metal compound ; forming an insulating layer over said second conductive layer ; forming a first opening through said insulating layer , and said second conductive layer ; and forming a second opening in said first conductive layer beneath said first opening wherein said second opening is wider than said first opening in said second conductive layer . US5874358A CLAIM 8 . A process for forming an interconnection structure comprising the steps of : forming an interconnection having a bulk conductor comprising a first metal and a capping layer comprising a second metal-first metal compound ; etching said interconnection a first time t (first range) o form a first opening having a first width in said capping layer ; and etching said interconnection a second time beneath said first opening such that said bulk conductor is etched laterally to form a second opening which extends laterally further into said interconnection than said first opening . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US5874358A CLAIM 1 . A method of forming an interconnection structure of an integrated circuit formed on a semiconductor substrate comprising the steps of : forming a first conductive layer comprising a first metal above said substrate ; forming a second conductive layer on said first conductive layer said second conductive layer comprising a second metal-first metal compound ; forming an insulating layer over said second conductive layer ; forming a first opening through said insulating layer , and said second conductive layer ; and forming (anti reflective coating) a second opening in said first conductive layer beneath said first opening wherein said second opening is wider than said first opening in said second conductive layer . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch (wet etch, dry etch, first etch) stop insulation layer comprising a first etch (wet etch, dry etch, first etch) stop layer and a second etch (wet etch, dry etch, first etch) stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area (second conductive layer) of said contact region is smaller than a metal layer coupling area of said contact region . |
US5874358A CLAIM 1 . A method of forming an interconnection structure of an integrated circuit formed on a semiconductor substrate comprising the steps of : forming a first conductive layer comprising a first metal above said substrate ; forming a second conductive layer (substrate coupling area) on said first conductive layer said second conductive layer comprising a second metal-first metal compound ; forming an insulating layer over said second conductive layer ; forming a first opening through said insulating layer , and said second conductive layer ; and forming a second opening in said first conductive layer beneath said first opening wherein said second opening is wider than said first opening in said second conductive layer . US5874358A CLAIM 3 . The method of claim 2 wherein said etchant is a wet etch (multiple etch, etch process, second etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, second etch stop layers) ant . US5874358A CLAIM 10 . The process of claim 8 wherein said first etch (multiple etch, etch process, second etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, second etch stop layers) is a dry etch (multiple etch, etch process, second etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, second etch stop layers) . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch (wet etch, dry etch, first etch) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (wet etch, dry etch, first etch) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5874358A CLAIM 3 . The method of claim 2 wherein said etchant is a wet etch (multiple etch, etch process, second etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, second etch stop layers) ant . US5874358A CLAIM 10 . The process of claim 8 wherein said first etch (multiple etch, etch process, second etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, second etch stop layers) is a dry etch (multiple etch, etch process, second etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, second etch stop layers) . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US5874358A CLAIM 1 . A method of forming an interconnection structure of an integrated circuit formed on a semiconductor substrate comprising the steps of : forming a first conductive layer comprising a first metal above said substrate ; forming a second conductive layer on said first conductive layer said second conductive layer comprising a second metal-first metal compound ; forming an insulating layer over said second conductive layer ; forming a first opening through said insulating layer , and said second conductive layer ; and forming (anti reflective coating) a second opening in said first conductive layer beneath said first opening wherein said second opening is wider than said first opening in said second conductive layer . |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region is a first range (time t) of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5874358A CLAIM 8 . A process for forming an interconnection structure comprising the steps of : forming an interconnection having a bulk conductor comprising a first metal and a capping layer comprising a second metal-first metal compound ; etching said interconnection a first time t (first range) o form a first opening having a first width in said capping layer ; and etching said interconnection a second time beneath said first opening such that said bulk conductor is etched laterally to form a second opening which extends laterally further into said interconnection than said first opening . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5854104A Filed: 1997-01-30 Issued: 1998-12-29 Process for fabricating nonvolatile semiconductor memory device having a ferroelectric capacitor (Original Assignee) Sharp Corp (Current Assignee) Sharp Corp Shigeo Onishi, Takao Kinoshita, Jun Kudo |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch (first etch) stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (layer insulating film, ferroelectric film, upper electrode, contact hole, contact plug, entire surface) layer over said first etch stop layer ; a second etch (second etch) stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5854104A CLAIM 1 . A process for fabricating a nonvolatile semiconductor memory device having one transistor and one ferroelectric capacitor electrically connected to each other by a contact plug (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) , which comprising forming a transistor ; forming an inter-layer insulating film (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) , at least an upper surface portion thereof being a titanium oxide film ; forming a capacitor lower electrode ; and forming a capacitor insulating film and a capacitor upper electrode (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) , wherein the lower electrode forming step comprises : depositing a titanium nitride film and a platinum film on the titanium oxide film ; etching the platinum film with a first etch (first etch) ing gas adapted to suppress deposition of substances including platinum ; and etching the titanium nitride film with a second etch (second etch) ing gas having a high etching selectivity to the titanium oxide film . US5854104A CLAIM 6 . A process as set forth in claim 1 , wherein the capacitor insulating film/upper electrode forming step comprises : (i) depositing a ferroelectric film (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) , a platinum film , a titanium nitride film and an aluminum film over the entire surface (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) of the inter-layer insulating film including the capacitor lower electrode ; (ii) etching the aluminum film and the titanium nitride film with a third etching gas , and etching the platinum film with a fourth etching gas adapted to suppress deposition of substances including platinum for formation of the capacitor upper electrode ; and (iii) etching the ferroelectric film with a fifth etching gas less reactive to aluminum by employing the resulting upper electrode as a mask for formation of the capacitor insulating film . US5854104A CLAIM 12 . A process as set forth in claim 1 , wherein a contact plug is formed by opening a contact hole (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) in the inter-layer insulating film , depositing a titanium film and a titanium nitride film sequentially over the inter-layer insulating film including the contact hole , depositing a tungsten film on the titanium nitride film so as to fill the contact hole , and etching back the titanium film , the titanium nitride film and the tungsten film by a CMP method to such an extent that the inter-layer insulating film is exposed . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch (first etch) stop layer protects removal of a substrate material by an etch process (high etching) . |
US5854104A CLAIM 1 . A process for fabricating a nonvolatile semiconductor memory device having one transistor and one ferroelectric capacitor electrically connected to each other by a contact plug , which comprising forming a transistor ; forming an inter-layer insulating film , at least an upper surface portion thereof being a titanium oxide film ; forming a capacitor lower electrode ; and forming a capacitor insulating film and a capacitor upper electrode , wherein the lower electrode forming step comprises : depositing a titanium nitride film and a platinum film on the titanium oxide film ; etching the platinum film with a first etch (first etch) ing gas adapted to suppress deposition of substances including platinum ; and etching the titanium nitride film with a second etching gas having a high etching (etch process) selectivity to the titanium oxide film . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (layer insulating film, ferroelectric film, upper electrode, contact hole, contact plug, entire surface) layer insulates said contact region . |
US5854104A CLAIM 1 . A process for fabricating a nonvolatile semiconductor memory device having one transistor and one ferroelectric capacitor electrically connected to each other by a contact plug (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) , which comprising forming a transistor ; forming an inter-layer insulating film (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) , at least an upper surface portion thereof being a titanium oxide film ; forming a capacitor lower electrode ; and forming a capacitor insulating film and a capacitor upper electrode (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) , wherein the lower electrode forming step comprises : depositing a titanium nitride film and a platinum film on the titanium oxide film ; etching the platinum film with a first etching gas adapted to suppress deposition of substances including platinum ; and etching the titanium nitride film with a second etching gas having a high etching selectivity to the titanium oxide film . US5854104A CLAIM 6 . A process as set forth in claim 1 , wherein the capacitor insulating film/upper electrode forming step comprises : (i) depositing a ferroelectric film (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) , a platinum film , a titanium nitride film and an aluminum film over the entire surface (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) of the inter-layer insulating film including the capacitor lower electrode ; (ii) etching the aluminum film and the titanium nitride film with a third etching gas , and etching the platinum film with a fourth etching gas adapted to suppress deposition of substances including platinum for formation of the capacitor upper electrode ; and (iii) etching the ferroelectric film with a fifth etching gas less reactive to aluminum by employing the resulting upper electrode as a mask for formation of the capacitor insulating film . US5854104A CLAIM 12 . A process as set forth in claim 1 , wherein a contact plug is formed by opening a contact hole (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) in the inter-layer insulating film , depositing a titanium film and a titanium nitride film sequentially over the inter-layer insulating film including the contact hole , depositing a tungsten film on the titanium nitride film so as to fill the contact hole , and etching back the titanium film , the titanium nitride film and the tungsten film by a CMP method to such an extent that the inter-layer insulating film is exposed . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch (second etch) stop layer protects lower layers during an etching process . |
US5854104A CLAIM 1 . A process for fabricating a nonvolatile semiconductor memory device having one transistor and one ferroelectric capacitor electrically connected to each other by a contact plug , which comprising forming a transistor ; forming an inter-layer insulating film , at least an upper surface portion thereof being a titanium oxide film ; forming a capacitor lower electrode ; and forming a capacitor insulating film and a capacitor upper electrode , wherein the lower electrode forming step comprises : depositing a titanium nitride film and a platinum film on the titanium oxide film ; etching the platinum film with a first etching gas adapted to suppress deposition of substances including platinum ; and etching the titanium nitride film with a second etch (second etch) ing gas having a high etching selectivity to the titanium oxide film . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (layer insulating film, ferroelectric film, upper electrode, contact hole, contact plug, entire surface) layer insulates said contact region . |
US5854104A CLAIM 1 . A process for fabricating a nonvolatile semiconductor memory device having one transistor and one ferroelectric capacitor electrically connected to each other by a contact plug (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) , which comprising forming a transistor ; forming an inter-layer insulating film (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) , at least an upper surface portion thereof being a titanium oxide film ; forming a capacitor lower electrode ; and forming a capacitor insulating film and a capacitor upper electrode (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) , wherein the lower electrode forming step comprises : depositing a titanium nitride film and a platinum film on the titanium oxide film ; etching the platinum film with a first etching gas adapted to suppress deposition of substances including platinum ; and etching the titanium nitride film with a second etching gas having a high etching selectivity to the titanium oxide film . US5854104A CLAIM 6 . A process as set forth in claim 1 , wherein the capacitor insulating film/upper electrode forming step comprises : (i) depositing a ferroelectric film (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) , a platinum film , a titanium nitride film and an aluminum film over the entire surface (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) of the inter-layer insulating film including the capacitor lower electrode ; (ii) etching the aluminum film and the titanium nitride film with a third etching gas , and etching the platinum film with a fourth etching gas adapted to suppress deposition of substances including platinum for formation of the capacitor upper electrode ; and (iii) etching the ferroelectric film with a fifth etching gas less reactive to aluminum by employing the resulting upper electrode as a mask for formation of the capacitor insulating film . US5854104A CLAIM 12 . A process as set forth in claim 1 , wherein a contact plug is formed by opening a contact hole (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) in the inter-layer insulating film , depositing a titanium film and a titanium nitride film sequentially over the inter-layer insulating film including the contact hole , depositing a tungsten film on the titanium nitride film so as to fill the contact hole , and etching back the titanium film , the titanium nitride film and the tungsten film by a CMP method to such an extent that the inter-layer insulating film is exposed . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch (first etch) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (layer insulating film, ferroelectric film, upper electrode, contact hole, contact plug, entire surface) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (second etch) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5854104A CLAIM 1 . A process for fabricating a nonvolatile semiconductor memory device having one transistor and one ferroelectric capacitor electrically connected to each other by a contact plug (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) , which comprising forming a transistor ; forming an inter-layer insulating film (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) , at least an upper surface portion thereof being a titanium oxide film ; forming a capacitor lower electrode ; and forming a capacitor insulating film and a capacitor upper electrode (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) , wherein the lower electrode forming step comprises : depositing a titanium nitride film and a platinum film on the titanium oxide film ; etching the platinum film with a first etch (first etch) ing gas adapted to suppress deposition of substances including platinum ; and etching the titanium nitride film with a second etch (second etch) ing gas having a high etching selectivity to the titanium oxide film . US5854104A CLAIM 6 . A process as set forth in claim 1 , wherein the capacitor insulating film/upper electrode forming step comprises : (i) depositing a ferroelectric film (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) , a platinum film , a titanium nitride film and an aluminum film over the entire surface (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) of the inter-layer insulating film including the capacitor lower electrode ; (ii) etching the aluminum film and the titanium nitride film with a third etching gas , and etching the platinum film with a fourth etching gas adapted to suppress deposition of substances including platinum for formation of the capacitor upper electrode ; and (iii) etching the ferroelectric film with a fifth etching gas less reactive to aluminum by employing the resulting upper electrode as a mask for formation of the capacitor insulating film . US5854104A CLAIM 12 . A process as set forth in claim 1 , wherein a contact plug is formed by opening a contact hole (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) in the inter-layer insulating film , depositing a titanium film and a titanium nitride film sequentially over the inter-layer insulating film including the contact hole , depositing a tungsten film on the titanium nitride film so as to fill the contact hole , and etching back the titanium film , the titanium nitride film and the tungsten film by a CMP method to such an extent that the inter-layer insulating film is exposed . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric (layer insulating film, ferroelectric film, upper electrode, contact hole, contact plug, entire surface) layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5854104A CLAIM 1 . A process for fabricating a nonvolatile semiconductor memory device having one transistor and one ferroelectric capacitor electrically connected to each other by a contact plug (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) , which comprising forming a transistor ; forming an inter-layer insulating film (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) , at least an upper surface portion thereof being a titanium oxide film ; forming a capacitor lower electrode ; and forming a capacitor insulating film and a capacitor upper electrode (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) , wherein the lower electrode forming step comprises : depositing a titanium nitride film and a platinum film on the titanium oxide film ; etching the platinum film with a first etching gas adapted to suppress deposition of substances including platinum ; and etching the titanium nitride film with a second etching gas having a high etching selectivity to the titanium oxide film . US5854104A CLAIM 6 . A process as set forth in claim 1 , wherein the capacitor insulating film/upper electrode forming step comprises : (i) depositing a ferroelectric film (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) , a platinum film , a titanium nitride film and an aluminum film over the entire surface (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) of the inter-layer insulating film including the capacitor lower electrode ; (ii) etching the aluminum film and the titanium nitride film with a third etching gas , and etching the platinum film with a fourth etching gas adapted to suppress deposition of substances including platinum for formation of the capacitor upper electrode ; and (iii) etching the ferroelectric film with a fifth etching gas less reactive to aluminum by employing the resulting upper electrode as a mask for formation of the capacitor insulating film . US5854104A CLAIM 12 . A process as set forth in claim 1 , wherein a contact plug is formed by opening a contact hole (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) in the inter-layer insulating film , depositing a titanium film and a titanium nitride film sequentially over the inter-layer insulating film including the contact hole , depositing a tungsten film on the titanium nitride film so as to fill the contact hole , and etching back the titanium film , the titanium nitride film and the tungsten film by a CMP method to such an extent that the inter-layer insulating film is exposed . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US5854104A CLAIM 1 . A process for fabricating a nonvolatile semiconductor memory device having one transistor and one ferroelectric capacitor electrically connected to each other by a contact plug , which comprising forming a transistor ; forming an inter-layer insulating film , at least an upper surface portion thereof being a titanium oxide film ; forming a capacitor lower electrode ; and forming (anti reflective coating) a capacitor insulating film and a capacitor upper electrode , wherein the lower electrode forming step comprises : depositing a titanium nitride film and a platinum film on the titanium oxide film ; etching the platinum film with a first etching gas adapted to suppress deposition of substances including platinum ; and etching the titanium nitride film with a second etching gas having a high etching selectivity to the titanium oxide film . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch (first etch) stop layer and a second etch (second etch) stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (layer insulating film, ferroelectric film, upper electrode, contact hole, contact plug, entire surface) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom (lower electrode) , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US5854104A CLAIM 1 . A process for fabricating a nonvolatile semiconductor memory device having one transistor and one ferroelectric capacitor electrically connected to each other by a contact plug (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) , which comprising forming a transistor ; forming an inter-layer insulating film (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) , at least an upper surface portion thereof being a titanium oxide film ; forming a capacitor lower electrode (contact bottom) ; and forming a capacitor insulating film and a capacitor upper electrode (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) , wherein the lower electrode forming step comprises : depositing a titanium nitride film and a platinum film on the titanium oxide film ; etching the platinum film with a first etch (first etch) ing gas adapted to suppress deposition of substances including platinum ; and etching the titanium nitride film with a second etch (second etch) ing gas having a high etching selectivity to the titanium oxide film . US5854104A CLAIM 6 . A process as set forth in claim 1 , wherein the capacitor insulating film/upper electrode forming step comprises : (i) depositing a ferroelectric film (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) , a platinum film , a titanium nitride film and an aluminum film over the entire surface (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) of the inter-layer insulating film including the capacitor lower electrode ; (ii) etching the aluminum film and the titanium nitride film with a third etching gas , and etching the platinum film with a fourth etching gas adapted to suppress deposition of substances including platinum for formation of the capacitor upper electrode ; and (iii) etching the ferroelectric film with a fifth etching gas less reactive to aluminum by employing the resulting upper electrode as a mask for formation of the capacitor insulating film . US5854104A CLAIM 12 . A process as set forth in claim 1 , wherein a contact plug is formed by opening a contact hole (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) in the inter-layer insulating film , depositing a titanium film and a titanium nitride film sequentially over the inter-layer insulating film including the contact hole , depositing a tungsten film on the titanium nitride film so as to fill the contact hole , and etching back the titanium film , the titanium nitride film and the tungsten film by a CMP method to such an extent that the inter-layer insulating film is exposed . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch (first etch) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (layer insulating film, ferroelectric film, upper electrode, contact hole, contact plug, entire surface) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (second etch) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5854104A CLAIM 1 . A process for fabricating a nonvolatile semiconductor memory device having one transistor and one ferroelectric capacitor electrically connected to each other by a contact plug (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) , which comprising forming a transistor ; forming an inter-layer insulating film (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) , at least an upper surface portion thereof being a titanium oxide film ; forming a capacitor lower electrode ; and forming a capacitor insulating film and a capacitor upper electrode (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) , wherein the lower electrode forming step comprises : depositing a titanium nitride film and a platinum film on the titanium oxide film ; etching the platinum film with a first etch (first etch) ing gas adapted to suppress deposition of substances including platinum ; and etching the titanium nitride film with a second etch (second etch) ing gas having a high etching selectivity to the titanium oxide film . US5854104A CLAIM 6 . A process as set forth in claim 1 , wherein the capacitor insulating film/upper electrode forming step comprises : (i) depositing a ferroelectric film (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) , a platinum film , a titanium nitride film and an aluminum film over the entire surface (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) of the inter-layer insulating film including the capacitor lower electrode ; (ii) etching the aluminum film and the titanium nitride film with a third etching gas , and etching the platinum film with a fourth etching gas adapted to suppress deposition of substances including platinum for formation of the capacitor upper electrode ; and (iii) etching the ferroelectric film with a fifth etching gas less reactive to aluminum by employing the resulting upper electrode as a mask for formation of the capacitor insulating film . US5854104A CLAIM 12 . A process as set forth in claim 1 , wherein a contact plug is formed by opening a contact hole (interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) in the inter-layer insulating film , depositing a titanium film and a titanium nitride film sequentially over the inter-layer insulating film including the contact hole , depositing a tungsten film on the titanium nitride film so as to fill the contact hole , and etching back the titanium film , the titanium nitride film and the tungsten film by a CMP method to such an extent that the inter-layer insulating film is exposed . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US5854104A CLAIM 1 . A process for fabricating a nonvolatile semiconductor memory device having one transistor and one ferroelectric capacitor electrically connected to each other by a contact plug , which comprising forming a transistor ; forming an inter-layer insulating film , at least an upper surface portion thereof being a titanium oxide film ; forming a capacitor lower electrode ; and forming (anti reflective coating) a capacitor insulating film and a capacitor upper electrode , wherein the lower electrode forming step comprises : depositing a titanium nitride film and a platinum film on the titanium oxide film ; etching the platinum film with a first etching gas adapted to suppress deposition of substances including platinum ; and etching the titanium nitride film with a second etching gas having a high etching selectivity to the titanium oxide film . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5874357A Filed: 1996-12-19 Issued: 1999-02-23 Method of forming wiring structure of semiconductor device (Original Assignee) LG Semicon Co Ltd (Current Assignee) SK Hynix Inc Young-Kwon Jun, Yong-Kwon Kim |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region (second contact) coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area (second conductive layer) of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch (dry etch, wet etch) stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch (dry etch, wet etch) stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (contact hole) layer over said first etch stop layer ; a second etch (dry etch, wet etch) stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5874357A CLAIM 1 . A method of forming a wiring structure of a semiconductor device , comprising the steps of : forming a first conductive layer and a sacrificial layer sequentially on a substrate ; patterning the first conductive layer and the sacrificial layer ; forming an insulation film on the substrate including the first conductive layer and the victim layer ; forming a first contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) in the insulation film by removing a portion of the insulation film so as to expose a portion of the upper surface of the sacrificial layer therethrough ; removing the sacrificial layer entirely to form a second contact (contact region) hole below the first contact hole , the second contact hole having a width wider than that of the first contact hole and the size of the second contact hole being equal to the space left after removing the victim layer ; and forming a second conductive layer (substrate coupling area) on the insulation film so as to thoroughly fill the first contact hole . US5874357A CLAIM 9 . The method according to claim 1 , wherein the portion of the insulation film is removed therefrom by an anisotropic dry etch (second etch, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers) ing technique . US5874357A CLAIM 10 . The method according to claim 1 , wherein the sacrificial layer is removed therefrom using a wet etch (second etch, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers) ing technique . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch (dry etch, wet etch) stop layer protects removal of a substrate material (silicon oxide) by an etch process (dry etch, wet etch) . |
US5874357A CLAIM 5 . The method according to claim 1 , wherein the insulation film includes a silicon oxide (substrate material) film formed using a plasma enhanced chemical vapor deposition (PECVD) technique . US5874357A CLAIM 9 . The method according to claim 1 , wherein the portion of the insulation film is removed therefrom by an anisotropic dry etch (second etch, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers) ing technique . US5874357A CLAIM 10 . The method according to claim 1 , wherein the sacrificial layer is removed therefrom using a wet etch (second etch, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers) ing technique . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (contact hole) layer insulates said contact region (second contact) . |
US5874357A CLAIM 1 . A method of forming a wiring structure of a semiconductor device , comprising the steps of : forming a first conductive layer and a sacrificial layer sequentially on a substrate ; patterning the first conductive layer and the sacrificial layer ; forming an insulation film on the substrate including the first conductive layer and the victim layer ; forming a first contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) in the insulation film by removing a portion of the insulation film so as to expose a portion of the upper surface of the sacrificial layer therethrough ; removing the sacrificial layer entirely to form a second contact (contact region) hole below the first contact hole , the second contact hole having a width wider than that of the first contact hole and the size of the second contact hole being equal to the space left after removing the victim layer ; and forming a second conductive layer on the insulation film so as to thoroughly fill the first contact hole . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch (dry etch, wet etch) stop layer protects lower layers during an etching process . |
US5874357A CLAIM 9 . The method according to claim 1 , wherein the portion of the insulation film is removed therefrom by an anisotropic dry etch (second etch, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers) ing technique . US5874357A CLAIM 10 . The method according to claim 1 , wherein the sacrificial layer is removed therefrom using a wet etch (second etch, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers) ing technique . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (contact hole) layer insulates said contact region (second contact) . |
US5874357A CLAIM 1 . A method of forming a wiring structure of a semiconductor device , comprising the steps of : forming a first conductive layer and a sacrificial layer sequentially on a substrate ; patterning the first conductive layer and the sacrificial layer ; forming an insulation film on the substrate including the first conductive layer and the victim layer ; forming a first contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) in the insulation film by removing a portion of the insulation film so as to expose a portion of the upper surface of the sacrificial layer therethrough ; removing the sacrificial layer entirely to form a second contact (contact region) hole below the first contact hole , the second contact hole having a width wider than that of the first contact hole and the size of the second contact hole being equal to the space left after removing the victim layer ; and forming a second conductive layer on the insulation film so as to thoroughly fill the first contact hole . |
| US7977797B2 CLAIM 6 . An integrated circuit of claim 1 wherein said spacer region insulates said contact region (second contact) . |
US5874357A CLAIM 1 . A method of forming a wiring structure of a semiconductor device , comprising the steps of : forming a first conductive layer and a sacrificial layer sequentially on a substrate ; patterning the first conductive layer and the sacrificial layer ; forming an insulation film on the substrate including the first conductive layer and the victim layer ; forming a first contact hole in the insulation film by removing a portion of the insulation film so as to expose a portion of the upper surface of the sacrificial layer therethrough ; removing the sacrificial layer entirely to form a second contact (contact region) hole below the first contact hole , the second contact hole having a width wider than that of the first contact hole and the size of the second contact hole being equal to the space left after removing the victim layer ; and forming a second conductive layer on the insulation film so as to thoroughly fill the first contact hole . |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area (second conductive layer) of said contact region (second contact) permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
US5874357A CLAIM 1 . A method of forming a wiring structure of a semiconductor device , comprising the steps of : forming a first conductive layer and a sacrificial layer sequentially on a substrate ; patterning the first conductive layer and the sacrificial layer ; forming an insulation film on the substrate including the first conductive layer and the victim layer ; forming a first contact hole in the insulation film by removing a portion of the insulation film so as to expose a portion of the upper surface of the sacrificial layer therethrough ; removing the sacrificial layer entirely to form a second contact (contact region) hole below the first contact hole , the second contact hole having a width wider than that of the first contact hole and the size of the second contact hole being equal to the space left after removing the victim layer ; and forming a second conductive layer (substrate coupling area) on the insulation film so as to thoroughly fill the first contact hole . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch (dry etch, wet etch) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (contact hole) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (dry etch, wet etch) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5874357A CLAIM 1 . A method of forming a wiring structure of a semiconductor device , comprising the steps of : forming a first conductive layer and a sacrificial layer sequentially on a substrate ; patterning the first conductive layer and the sacrificial layer ; forming an insulation film on the substrate including the first conductive layer and the victim layer ; forming a first contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) in the insulation film by removing a portion of the insulation film so as to expose a portion of the upper surface of the sacrificial layer therethrough ; removing the sacrificial layer entirely to form a second contact hole below the first contact hole , the second contact hole having a width wider than that of the first contact hole and the size of the second contact hole being equal to the space left after removing the victim layer ; and forming a second conductive layer on the insulation film so as to thoroughly fill the first contact hole . US5874357A CLAIM 9 . The method according to claim 1 , wherein the portion of the insulation film is removed therefrom by an anisotropic dry etch (second etch, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers) ing technique . US5874357A CLAIM 10 . The method according to claim 1 , wherein the sacrificial layer is removed therefrom using a wet etch (second etch, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers) ing technique . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric (contact hole) layer for said contact region (second contact) is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5874357A CLAIM 1 . A method of forming a wiring structure of a semiconductor device , comprising the steps of : forming a first conductive layer and a sacrificial layer sequentially on a substrate ; patterning the first conductive layer and the sacrificial layer ; forming an insulation film on the substrate including the first conductive layer and the victim layer ; forming a first contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) in the insulation film by removing a portion of the insulation film so as to expose a portion of the upper surface of the sacrificial layer therethrough ; removing the sacrificial layer entirely to form a second contact (contact region) hole below the first contact hole , the second contact hole having a width wider than that of the first contact hole and the size of the second contact hole being equal to the space left after removing the victim layer ; and forming a second conductive layer on the insulation film so as to thoroughly fill the first contact hole . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US5874357A CLAIM 1 . A method of forming a wiring structure of a semiconductor device , comprising the steps of : forming a first conductive layer and a sacrificial layer sequentially on a substrate ; patterning the first conductive layer and the sacrificial layer ; forming an insulation film on the substrate including the first conductive layer and the victim layer ; forming a first contact hole in the insulation film by removing a portion of the insulation film so as to expose a portion of the upper surface of the sacrificial layer therethrough ; removing the sacrificial layer entirely to form a second contact hole below the first contact hole , the second contact hole having a width wider than that of the first contact hole and the size of the second contact hole being equal to the space left after removing the victim layer ; and forming (anti reflective coating) a second conductive layer on the insulation film so as to thoroughly fill the first contact hole . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch (dry etch, wet etch) stop insulation layer comprising a first etch (dry etch, wet etch) stop layer and a second etch (dry etch, wet etch) stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region (second contact) and under a first sub interlevel dielectric (contact hole) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area (second conductive layer) of said contact region is smaller than a metal layer coupling area of said contact region . |
US5874357A CLAIM 1 . A method of forming a wiring structure of a semiconductor device , comprising the steps of : forming a first conductive layer and a sacrificial layer sequentially on a substrate ; patterning the first conductive layer and the sacrificial layer ; forming an insulation film on the substrate including the first conductive layer and the victim layer ; forming a first contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) in the insulation film by removing a portion of the insulation film so as to expose a portion of the upper surface of the sacrificial layer therethrough ; removing the sacrificial layer entirely to form a second contact (contact region) hole below the first contact hole , the second contact hole having a width wider than that of the first contact hole and the size of the second contact hole being equal to the space left after removing the victim layer ; and forming a second conductive layer (substrate coupling area) on the insulation film so as to thoroughly fill the first contact hole . US5874357A CLAIM 9 . The method according to claim 1 , wherein the portion of the insulation film is removed therefrom by an anisotropic dry etch (second etch, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers) ing technique . US5874357A CLAIM 10 . The method according to claim 1 , wherein the sacrificial layer is removed therefrom using a wet etch (second etch, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers) ing technique . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch (dry etch, wet etch) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (contact hole) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (dry etch, wet etch) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5874357A CLAIM 1 . A method of forming a wiring structure of a semiconductor device , comprising the steps of : forming a first conductive layer and a sacrificial layer sequentially on a substrate ; patterning the first conductive layer and the sacrificial layer ; forming an insulation film on the substrate including the first conductive layer and the victim layer ; forming a first contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) in the insulation film by removing a portion of the insulation film so as to expose a portion of the upper surface of the sacrificial layer therethrough ; removing the sacrificial layer entirely to form a second contact hole below the first contact hole , the second contact hole having a width wider than that of the first contact hole and the size of the second contact hole being equal to the space left after removing the victim layer ; and forming a second conductive layer on the insulation film so as to thoroughly fill the first contact hole . US5874357A CLAIM 9 . The method according to claim 1 , wherein the portion of the insulation film is removed therefrom by an anisotropic dry etch (second etch, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers) ing technique . US5874357A CLAIM 10 . The method according to claim 1 , wherein the sacrificial layer is removed therefrom using a wet etch (second etch, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch stop layers) ing technique . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US5874357A CLAIM 1 . A method of forming a wiring structure of a semiconductor device , comprising the steps of : forming a first conductive layer and a sacrificial layer sequentially on a substrate ; patterning the first conductive layer and the sacrificial layer ; forming an insulation film on the substrate including the first conductive layer and the victim layer ; forming a first contact hole in the insulation film by removing a portion of the insulation film so as to expose a portion of the upper surface of the sacrificial layer therethrough ; removing the sacrificial layer entirely to form a second contact hole below the first contact hole , the second contact hole having a width wider than that of the first contact hole and the size of the second contact hole being equal to the space left after removing the victim layer ; and forming (anti reflective coating) a second conductive layer on the insulation film so as to thoroughly fill the first contact hole . |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region (second contact) is a first range of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5874357A CLAIM 1 . A method of forming a wiring structure of a semiconductor device , comprising the steps of : forming a first conductive layer and a sacrificial layer sequentially on a substrate ; patterning the first conductive layer and the sacrificial layer ; forming an insulation film on the substrate including the first conductive layer and the victim layer ; forming a first contact hole in the insulation film by removing a portion of the insulation film so as to expose a portion of the upper surface of the sacrificial layer therethrough ; removing the sacrificial layer entirely to form a second contact (contact region) hole below the first contact hole , the second contact hole having a width wider than that of the first contact hole and the size of the second contact hole being equal to the space left after removing the victim layer ; and forming a second conductive layer on the insulation film so as to thoroughly fill the first contact hole . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5795823A Filed: 1996-11-20 Issued: 1998-08-18 Self aligned via dual damascene (Original Assignee) Advanced Micro Devices Inc (Current Assignee) GlobalFoundries Inc Steven Avanzino, Subhash Gupta, Rich Klein, Scott D. Luning, Ming-Ren Lin |
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| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space (lower half) in a portion of said first sub interlevel dielectric layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5795823A CLAIM 1 . A method of fabricating interconnecting conductive lines and conductive vias in a layer of insulating material comprising the steps of : creating a pattern for a conductive line opening having enlarged regions at sections in the line opening to be via openings and about half of the width of the width of the conductive line ; etching said pattern partially through the insulating layer so that a conductive line opening is formed in the upper half of the layer ; depositing a material having etch selectivity different from the material of the insulating layer ; etching said deposited material to form sidewalls in the enlarged regions and to expose the insulating layer between the sidewalls ; etching said exposed insulating layer between the sidewalls with the sidewalls and the deposited material at each end of the sidewalls serving as an etch mask so that a via opening is formed in the lower half (first space) of the insulating layer ; and filling said conductive line opening and via opening with conductive material . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom (two layers) , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US5795823A CLAIM 2 . The method of claim 1 wherein said insulating layer is two layers (contact bottom) , one for the via and the other for the conductive line . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US6077763A Filed: 1996-11-19 Issued: 2000-06-20 Process for fabricating a self-aligned contact (Original Assignee) United Microelectronics Corp (Current Assignee) United Microelectronics Corp Hwi-Huang Chen, Gary Hong |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub (upper surfaces, cell unit) interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US6077763A CLAIM 1 . A process for fabricating self-aligned contacts for a semiconductor memory integrated circuit device in a substrate , wherein the substrate has formed thereon a plurality of regularly spaced apart gate structures of memory cell unit (first sub, first sub interlevel dielectric layer) s of the memory device , the gate structures having upper surfaces (first sub, first sub interlevel dielectric layer) above a substrate surface and sidewalls between the upper surfaces and the substrate surface , first sidewall spacers being located on sidewalls of the gate structures , and source/drain regions of the memory cell units being located in the substrate in regions between consecutive gate structures ; the process comprising : forming an insulating layer over the substrate surface ; anisotropically etching back the insulating layer until the insulating layer over the top surface of the gate structure has a predetermined thickness measured normal to the substrate ; forming a photoresist layer over a surface of the insulating layer , with openings defined in the photoresist layer exposing the insulating layer over the source/drain regions ; etching into the insulating layer through the openings so as to expose the source/drain regions and form second sidewall spacers covering the first sidewall ; and forming the contacts for the memory cell units in direct electrical contact with the source/drain regions . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer protects removal of a substrate material by an etch process (silicon oxide layer) . |
US6077763A CLAIM 3 . The process of fabricating self-aligned contacts of claim 2 , wherein the insulating layer is a silicon oxide layer (etch process) with a thickness in the range of about 3 , 000-6 , 000 Å . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub (upper surfaces, cell unit) interlevel dielectric layer insulates said contact region . |
US6077763A CLAIM 1 . A process for fabricating self-aligned contacts for a semiconductor memory integrated circuit device in a substrate , wherein the substrate has formed thereon a plurality of regularly spaced apart gate structures of memory cell unit (first sub, first sub interlevel dielectric layer) s of the memory device , the gate structures having upper surfaces (first sub, first sub interlevel dielectric layer) above a substrate surface and sidewalls between the upper surfaces and the substrate surface , first sidewall spacers being located on sidewalls of the gate structures , and source/drain regions of the memory cell units being located in the substrate in regions between consecutive gate structures ; the process comprising : forming an insulating layer over the substrate surface ; anisotropically etching back the insulating layer until the insulating layer over the top surface of the gate structure has a predetermined thickness measured normal to the substrate ; forming a photoresist layer over a surface of the insulating layer , with openings defined in the photoresist layer exposing the insulating layer over the source/drain regions ; etching into the insulating layer through the openings so as to expose the source/drain regions and form second sidewall spacers covering the first sidewall ; and forming the contacts for the memory cell units in direct electrical contact with the source/drain regions . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub (upper surfaces, cell unit) interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6077763A CLAIM 1 . A process for fabricating self-aligned contacts for a semiconductor memory integrated circuit device in a substrate , wherein the substrate has formed thereon a plurality of regularly spaced apart gate structures of memory cell unit (first sub, first sub interlevel dielectric layer) s of the memory device , the gate structures having upper surfaces (first sub, first sub interlevel dielectric layer) above a substrate surface and sidewalls between the upper surfaces and the substrate surface , first sidewall spacers being located on sidewalls of the gate structures , and source/drain regions of the memory cell units being located in the substrate in regions between consecutive gate structures ; the process comprising : forming an insulating layer over the substrate surface ; anisotropically etching back the insulating layer until the insulating layer over the top surface of the gate structure has a predetermined thickness measured normal to the substrate ; forming a photoresist layer over a surface of the insulating layer , with openings defined in the photoresist layer exposing the insulating layer over the source/drain regions ; etching into the insulating layer through the openings so as to expose the source/drain regions and form second sidewall spacers covering the first sidewall ; and forming the contacts for the memory cell units in direct electrical contact with the source/drain regions . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub (upper surfaces, cell unit) interlevel dielectric layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US6077763A CLAIM 1 . A process for fabricating self-aligned contacts for a semiconductor memory integrated circuit device in a substrate , wherein the substrate has formed thereon a plurality of regularly spaced apart gate structures of memory cell unit (first sub, first sub interlevel dielectric layer) s of the memory device , the gate structures having upper surfaces (first sub, first sub interlevel dielectric layer) above a substrate surface and sidewalls between the upper surfaces and the substrate surface , first sidewall spacers being located on sidewalls of the gate structures , and source/drain regions of the memory cell units being located in the substrate in regions between consecutive gate structures ; the process comprising : forming an insulating layer over the substrate surface ; anisotropically etching back the insulating layer until the insulating layer over the top surface of the gate structure has a predetermined thickness measured normal to the substrate ; forming a photoresist layer over a surface of the insulating layer , with openings defined in the photoresist layer exposing the insulating layer over the source/drain regions ; etching into the insulating layer through the openings so as to expose the source/drain regions and form second sidewall spacers covering the first sidewall ; and forming the contacts for the memory cell units in direct electrical contact with the source/drain regions . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US6077763A CLAIM 1 . A process for fabricating self-aligned contacts for a semiconductor memory integrated circuit device in a substrate , wherein the substrate has formed thereon a plurality of regularly spaced apart gate structures of memory cell units of the memory device , the gate structures having upper surfaces above a substrate surface and sidewalls between the upper surfaces and the substrate surface , first sidewall spacers being located on sidewalls of the gate structures , and source/drain regions of the memory cell units being located in the substrate in regions between consecutive gate structures ; the process comprising : forming an insulating layer over the substrate surface ; anisotropically etching back the insulating layer until the insulating layer over the top surface of the gate structure has a predetermined thickness measured normal to the substrate ; forming a photoresist layer over a surface of the insulating layer , with openings defined in the photoresist layer exposing the insulating layer over the source/drain regions ; etching into the insulating layer through the openings so as to expose the source/drain regions and form second sidewall spacers covering the first sidewall ; and forming (anti reflective coating) the contacts for the memory cell units in direct electrical contact with the source/drain regions . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers (second sidewall spacer, first sidewall spacer, drain regions) have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub (upper surfaces, cell unit) interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US6077763A CLAIM 1 . A process for fabricating self-aligned contacts for a semiconductor memory integrated circuit device in a substrate , wherein the substrate has formed thereon a plurality of regularly spaced apart gate structures of memory cell unit (first sub, first sub interlevel dielectric layer) s of the memory device , the gate structures having upper surfaces (first sub, first sub interlevel dielectric layer) above a substrate surface and sidewalls between the upper surfaces and the substrate surface , first sidewall spacer (second etch stop layers, floating gate) s being located on sidewalls of the gate structures , and source/drain regions (second etch stop layers, floating gate) of the memory cell units being located in the substrate in regions between consecutive gate structures ; the process comprising : forming an insulating layer over the substrate surface ; anisotropically etching back the insulating layer until the insulating layer over the top surface of the gate structure has a predetermined thickness measured normal to the substrate ; forming a photoresist layer over a surface of the insulating layer , with openings defined in the photoresist layer exposing the insulating layer over the source/drain regions ; etching into the insulating layer through the openings so as to expose the source/drain regions and form second sidewall spacer (second etch stop layers, floating gate) s covering the first sidewall ; and forming the contacts for the memory cell units in direct electrical contact with the source/drain regions . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub (upper surfaces, cell unit) interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6077763A CLAIM 1 . A process for fabricating self-aligned contacts for a semiconductor memory integrated circuit device in a substrate , wherein the substrate has formed thereon a plurality of regularly spaced apart gate structures of memory cell unit (first sub, first sub interlevel dielectric layer) s of the memory device , the gate structures having upper surfaces (first sub, first sub interlevel dielectric layer) above a substrate surface and sidewalls between the upper surfaces and the substrate surface , first sidewall spacers being located on sidewalls of the gate structures , and source/drain regions of the memory cell units being located in the substrate in regions between consecutive gate structures ; the process comprising : forming an insulating layer over the substrate surface ; anisotropically etching back the insulating layer until the insulating layer over the top surface of the gate structure has a predetermined thickness measured normal to the substrate ; forming a photoresist layer over a surface of the insulating layer , with openings defined in the photoresist layer exposing the insulating layer over the source/drain regions ; etching into the insulating layer through the openings so as to expose the source/drain regions and form second sidewall spacers covering the first sidewall ; and forming the contacts for the memory cell units in direct electrical contact with the source/drain regions . |
| US7977797B2 CLAIM 13 . An integrated circuit of claim 11 further comprising a floating gate (second sidewall spacer, first sidewall spacer, drain regions) . |
US6077763A CLAIM 1 . A process for fabricating self-aligned contacts for a semiconductor memory integrated circuit device in a substrate , wherein the substrate has formed thereon a plurality of regularly spaced apart gate structures of memory cell units of the memory device , the gate structures having upper surfaces above a substrate surface and sidewalls between the upper surfaces and the substrate surface , first sidewall spacer (second etch stop layers, floating gate) s being located on sidewalls of the gate structures , and source/drain regions (second etch stop layers, floating gate) of the memory cell units being located in the substrate in regions between consecutive gate structures ; the process comprising : forming an insulating layer over the substrate surface ; anisotropically etching back the insulating layer until the insulating layer over the top surface of the gate structure has a predetermined thickness measured normal to the substrate ; forming a photoresist layer over a surface of the insulating layer , with openings defined in the photoresist layer exposing the insulating layer over the source/drain regions ; etching into the insulating layer through the openings so as to expose the source/drain regions and form second sidewall spacer (second etch stop layers, floating gate) s covering the first sidewall ; and forming the contacts for the memory cell units in direct electrical contact with the source/drain regions . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US6077763A CLAIM 1 . A process for fabricating self-aligned contacts for a semiconductor memory integrated circuit device in a substrate , wherein the substrate has formed thereon a plurality of regularly spaced apart gate structures of memory cell units of the memory device , the gate structures having upper surfaces above a substrate surface and sidewalls between the upper surfaces and the substrate surface , first sidewall spacers being located on sidewalls of the gate structures , and source/drain regions of the memory cell units being located in the substrate in regions between consecutive gate structures ; the process comprising : forming an insulating layer over the substrate surface ; anisotropically etching back the insulating layer until the insulating layer over the top surface of the gate structure has a predetermined thickness measured normal to the substrate ; forming a photoresist layer over a surface of the insulating layer , with openings defined in the photoresist layer exposing the insulating layer over the source/drain regions ; etching into the insulating layer through the openings so as to expose the source/drain regions and form second sidewall spacers covering the first sidewall ; and forming (anti reflective coating) the contacts for the memory cell units in direct electrical contact with the source/drain regions . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5677557A Filed: 1996-10-31 Issued: 1997-10-14 Method for forming buried plug contacts on semiconductor integrated circuits (Original Assignee) Taiwan Semiconductor Manufacturing Co TSMC Ltd (Current Assignee) Taiwan Semiconductor Manufacturing Co TSMC Ltd Shou-Gwo Wuu, Chen-Jong Wang, Mong-Song Liang, Chung-Hui Su |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region (gate electrodes) such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch (said second polysilicon layer, first polysilicon layer) stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (vertical sidewalls) layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5677557A CLAIM 1 . A buried metal plug structures on a semiconductor substrate for making electrical interconnections , comprising : a semiconductor substrate having device areas and field oxide areas and further having field effect transistor devices having gate electrodes (spacer region) composed of a patterned first polysilicon layer (first etch) and sidewall spacer formed from a sidewall material layer and source/drain contact areas in said device areas ; a blanket first insulating layer on said semiconductor devices and elsewhere on said substrate ; a patterned second polysilicon layer on said first insulating layer having openings aligned over said source/drain areas and said patterned second polysilicon layer providing electrically conducting portions elsewhere on said first insulating layer ; a second insulating layer on said patterned second polysilicon layer , and elsewhere on said first insulating layer , said second insulating layer being a low flow temperature glass that provides a planar surface ; said second insulating layer having contact openings aligned over and larger in width than said openings in said second polysilicon layer (first etch) ; and furthermore said first insulating layer having opening within said openings of said second polysilicon layer extending to said source/drain contact areas , said contact openings in said first insulating layer being self-aligned to the edge of said second polysilicon layer openings and having vertical sidewalls (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) ; and furthermore said second insulating layer having other contact openings elsewhere over and extend to the surface of said patterned second polysilicon layer , and said second and first insulating layers having contact openings to the surface of said substrate in regions free of said second polysilicon layer ; said contact openings having metal plugs the surface of which are coplanar with the surface of said second insulating layer ; a patterned first metal layer on said second insulating layer providing electrical interconnects to said substrate and said patterned second polysilicon layer by contacting said metal plugs while said self-aligned metal plug form interconnects between said patterned second polysilicon layer and said source/drain contact areas of said field effect transistors devices , thereby providing said completed buried metal plug structure . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch (said second polysilicon layer, first polysilicon layer) stop layer protects removal of a substrate material (silicon oxide) by an etch process . |
US5677557A CLAIM 1 . A buried metal plug structures on a semiconductor substrate for making electrical interconnections , comprising : a semiconductor substrate having device areas and field oxide areas and further having field effect transistor devices having gate electrodes composed of a patterned first polysilicon layer (first etch) and sidewall spacer formed from a sidewall material layer and source/drain contact areas in said device areas ; a blanket first insulating layer on said semiconductor devices and elsewhere on said substrate ; a patterned second polysilicon layer on said first insulating layer having openings aligned over said source/drain areas and said patterned second polysilicon layer providing electrically conducting portions elsewhere on said first insulating layer ; a second insulating layer on said patterned second polysilicon layer , and elsewhere on said first insulating layer , said second insulating layer being a low flow temperature glass that provides a planar surface ; said second insulating layer having contact openings aligned over and larger in width than said openings in said second polysilicon layer (first etch) ; and furthermore said first insulating layer having opening within said openings of said second polysilicon layer extending to said source/drain contact areas , said contact openings in said first insulating layer being self-aligned to the edge of said second polysilicon layer openings and having vertical sidewalls ; and furthermore said second insulating layer having other contact openings elsewhere over and extend to the surface of said patterned second polysilicon layer , and said second and first insulating layers having contact openings to the surface of said substrate in regions free of said second polysilicon layer ; said contact openings having metal plugs the surface of which are coplanar with the surface of said second insulating layer ; a patterned first metal layer on said second insulating layer providing electrical interconnects to said substrate and said patterned second polysilicon layer by contacting said metal plugs while said self-aligned metal plug form interconnects between said patterned second polysilicon layer and said source/drain contact areas of said field effect transistors devices , thereby providing said completed buried metal plug structure . US5677557A CLAIM 2 . The buried plug structure of claim 1 , wherein said sidewall material layer is composed of silicon oxide (substrate material) s having a thickness of between about 1400 to 2800 Angstroms . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (vertical sidewalls) layer insulates said contact region . |
US5677557A CLAIM 1 . A buried metal plug structures on a semiconductor substrate for making electrical interconnections , comprising : a semiconductor substrate having device areas and field oxide areas and further having field effect transistor devices having gate electrodes composed of a patterned first polysilicon layer and sidewall spacer formed from a sidewall material layer and source/drain contact areas in said device areas ; a blanket first insulating layer on said semiconductor devices and elsewhere on said substrate ; a patterned second polysilicon layer on said first insulating layer having openings aligned over said source/drain areas and said patterned second polysilicon layer providing electrically conducting portions elsewhere on said first insulating layer ; a second insulating layer on said patterned second polysilicon layer , and elsewhere on said first insulating layer , said second insulating layer being a low flow temperature glass that provides a planar surface ; said second insulating layer having contact openings aligned over and larger in width than said openings in said second polysilicon layer ; and furthermore said first insulating layer having opening within said openings of said second polysilicon layer extending to said source/drain contact areas , said contact openings in said first insulating layer being self-aligned to the edge of said second polysilicon layer openings and having vertical sidewalls (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) ; and furthermore said second insulating layer having other contact openings elsewhere over and extend to the surface of said patterned second polysilicon layer , and said second and first insulating layers having contact openings to the surface of said substrate in regions free of said second polysilicon layer ; said contact openings having metal plugs the surface of which are coplanar with the surface of said second insulating layer ; a patterned first metal layer on said second insulating layer providing electrical interconnects to said substrate and said patterned second polysilicon layer by contacting said metal plugs while said self-aligned metal plug form interconnects between said patterned second polysilicon layer and said source/drain contact areas of said field effect transistors devices , thereby providing said completed buried metal plug structure . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch stop layer protects lower layers during an etching process (doped polysilicon) . |
US5677557A CLAIM 3 . The buried plug structure of claim 1 , wherein said sidewall material layer is composed of a silicon oxide having a thickness of between about 400 to 800 Angstroms and an upper layer composed of undoped polysilicon (etching process) having a thickness of between about 1000 to 2000 Angstroms . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (vertical sidewalls) layer insulates said contact region . |
US5677557A CLAIM 1 . A buried metal plug structures on a semiconductor substrate for making electrical interconnections , comprising : a semiconductor substrate having device areas and field oxide areas and further having field effect transistor devices having gate electrodes composed of a patterned first polysilicon layer and sidewall spacer formed from a sidewall material layer and source/drain contact areas in said device areas ; a blanket first insulating layer on said semiconductor devices and elsewhere on said substrate ; a patterned second polysilicon layer on said first insulating layer having openings aligned over said source/drain areas and said patterned second polysilicon layer providing electrically conducting portions elsewhere on said first insulating layer ; a second insulating layer on said patterned second polysilicon layer , and elsewhere on said first insulating layer , said second insulating layer being a low flow temperature glass that provides a planar surface ; said second insulating layer having contact openings aligned over and larger in width than said openings in said second polysilicon layer ; and furthermore said first insulating layer having opening within said openings of said second polysilicon layer extending to said source/drain contact areas , said contact openings in said first insulating layer being self-aligned to the edge of said second polysilicon layer openings and having vertical sidewalls (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) ; and furthermore said second insulating layer having other contact openings elsewhere over and extend to the surface of said patterned second polysilicon layer , and said second and first insulating layers having contact openings to the surface of said substrate in regions free of said second polysilicon layer ; said contact openings having metal plugs the surface of which are coplanar with the surface of said second insulating layer ; a patterned first metal layer on said second insulating layer providing electrical interconnects to said substrate and said patterned second polysilicon layer by contacting said metal plugs while said self-aligned metal plug form interconnects between said patterned second polysilicon layer and said source/drain contact areas of said field effect transistors devices , thereby providing said completed buried metal plug structure . |
| US7977797B2 CLAIM 6 . An integrated circuit of claim 1 wherein said spacer region (gate electrodes) insulates said contact region . |
US5677557A CLAIM 1 . A buried metal plug structures on a semiconductor substrate for making electrical interconnections , comprising : a semiconductor substrate having device areas and field oxide areas and further having field effect transistor devices having gate electrodes (spacer region) composed of a patterned first polysilicon layer and sidewall spacer formed from a sidewall material layer and source/drain contact areas in said device areas ; a blanket first insulating layer on said semiconductor devices and elsewhere on said substrate ; a patterned second polysilicon layer on said first insulating layer having openings aligned over said source/drain areas and said patterned second polysilicon layer providing electrically conducting portions elsewhere on said first insulating layer ; a second insulating layer on said patterned second polysilicon layer , and elsewhere on said first insulating layer , said second insulating layer being a low flow temperature glass that provides a planar surface ; said second insulating layer having contact openings aligned over and larger in width than said openings in said second polysilicon layer ; and furthermore said first insulating layer having opening within said openings of said second polysilicon layer extending to said source/drain contact areas , said contact openings in said first insulating layer being self-aligned to the edge of said second polysilicon layer openings and having vertical sidewalls ; and furthermore said second insulating layer having other contact openings elsewhere over and extend to the surface of said patterned second polysilicon layer , and said second and first insulating layers having contact openings to the surface of said substrate in regions free of said second polysilicon layer ; said contact openings having metal plugs the surface of which are coplanar with the surface of said second insulating layer ; a patterned first metal layer on said second insulating layer providing electrical interconnects to said substrate and said patterned second polysilicon layer by contacting said metal plugs while said self-aligned metal plug form interconnects between said patterned second polysilicon layer and said source/drain contact areas of said field effect transistors devices , thereby providing said completed buried metal plug structure . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch (said second polysilicon layer, first polysilicon layer) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (vertical sidewalls) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5677557A CLAIM 1 . A buried metal plug structures on a semiconductor substrate for making electrical interconnections , comprising : a semiconductor substrate having device areas and field oxide areas and further having field effect transistor devices having gate electrodes composed of a patterned first polysilicon layer (first etch) and sidewall spacer formed from a sidewall material layer and source/drain contact areas in said device areas ; a blanket first insulating layer on said semiconductor devices and elsewhere on said substrate ; a patterned second polysilicon layer on said first insulating layer having openings aligned over said source/drain areas and said patterned second polysilicon layer providing electrically conducting portions elsewhere on said first insulating layer ; a second insulating layer on said patterned second polysilicon layer , and elsewhere on said first insulating layer , said second insulating layer being a low flow temperature glass that provides a planar surface ; said second insulating layer having contact openings aligned over and larger in width than said openings in said second polysilicon layer (first etch) ; and furthermore said first insulating layer having opening within said openings of said second polysilicon layer extending to said source/drain contact areas , said contact openings in said first insulating layer being self-aligned to the edge of said second polysilicon layer openings and having vertical sidewalls (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) ; and furthermore said second insulating layer having other contact openings elsewhere over and extend to the surface of said patterned second polysilicon layer , and said second and first insulating layers having contact openings to the surface of said substrate in regions free of said second polysilicon layer ; said contact openings having metal plugs the surface of which are coplanar with the surface of said second insulating layer ; a patterned first metal layer on said second insulating layer providing electrical interconnects to said substrate and said patterned second polysilicon layer by contacting said metal plugs while said self-aligned metal plug form interconnects between said patterned second polysilicon layer and said source/drain contact areas of said field effect transistors devices , thereby providing said completed buried metal plug structure . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space (said sub) in a portion of said first sub interlevel dielectric (vertical sidewalls) layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5677557A CLAIM 1 . A buried metal plug structures on a semiconductor substrate for making electrical interconnections , comprising : a semiconductor substrate having device areas and field oxide areas and further having field effect transistor devices having gate electrodes composed of a patterned first polysilicon layer and sidewall spacer formed from a sidewall material layer and source/drain contact areas in said device areas ; a blanket first insulating layer on said semiconductor devices and elsewhere on said sub (first space) strate ; a patterned second polysilicon layer on said first insulating layer having openings aligned over said source/drain areas and said patterned second polysilicon layer providing electrically conducting portions elsewhere on said first insulating layer ; a second insulating layer on said patterned second polysilicon layer , and elsewhere on said first insulating layer , said second insulating layer being a low flow temperature glass that provides a planar surface ; said second insulating layer having contact openings aligned over and larger in width than said openings in said second polysilicon layer ; and furthermore said first insulating layer having opening within said openings of said second polysilicon layer extending to said source/drain contact areas , said contact openings in said first insulating layer being self-aligned to the edge of said second polysilicon layer openings and having vertical sidewalls (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) ; and furthermore said second insulating layer having other contact openings elsewhere over and extend to the surface of said patterned second polysilicon layer , and said second and first insulating layers having contact openings to the surface of said substrate in regions free of said second polysilicon layer ; said contact openings having metal plugs the surface of which are coplanar with the surface of said second insulating layer ; a patterned first metal layer on said second insulating layer providing electrical interconnects to said substrate and said patterned second polysilicon layer by contacting said metal plugs while said self-aligned metal plug form interconnects between said patterned second polysilicon layer and said source/drain contact areas of said field effect transistors devices , thereby providing said completed buried metal plug structure . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch (said second polysilicon layer, first polysilicon layer) stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (vertical sidewalls) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US5677557A CLAIM 1 . A buried metal plug structures on a semiconductor substrate for making electrical interconnections , comprising : a semiconductor substrate having device areas and field oxide areas and further having field effect transistor devices having gate electrodes composed of a patterned first polysilicon layer (first etch) and sidewall spacer formed from a sidewall material layer and source/drain contact areas in said device areas ; a blanket first insulating layer on said semiconductor devices and elsewhere on said substrate ; a patterned second polysilicon layer on said first insulating layer having openings aligned over said source/drain areas and said patterned second polysilicon layer providing electrically conducting portions elsewhere on said first insulating layer ; a second insulating layer on said patterned second polysilicon layer , and elsewhere on said first insulating layer , said second insulating layer being a low flow temperature glass that provides a planar surface ; said second insulating layer having contact openings aligned over and larger in width than said openings in said second polysilicon layer (first etch) ; and furthermore said first insulating layer having opening within said openings of said second polysilicon layer extending to said source/drain contact areas , said contact openings in said first insulating layer being self-aligned to the edge of said second polysilicon layer openings and having vertical sidewalls (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) ; and furthermore said second insulating layer having other contact openings elsewhere over and extend to the surface of said patterned second polysilicon layer , and said second and first insulating layers having contact openings to the surface of said substrate in regions free of said second polysilicon layer ; said contact openings having metal plugs the surface of which are coplanar with the surface of said second insulating layer ; a patterned first metal layer on said second insulating layer providing electrical interconnects to said substrate and said patterned second polysilicon layer by contacting said metal plugs while said self-aligned metal plug form interconnects between said patterned second polysilicon layer and said source/drain contact areas of said field effect transistors devices , thereby providing said completed buried metal plug structure . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch (said second polysilicon layer, first polysilicon layer) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (vertical sidewalls) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5677557A CLAIM 1 . A buried metal plug structures on a semiconductor substrate for making electrical interconnections , comprising : a semiconductor substrate having device areas and field oxide areas and further having field effect transistor devices having gate electrodes composed of a patterned first polysilicon layer (first etch) and sidewall spacer formed from a sidewall material layer and source/drain contact areas in said device areas ; a blanket first insulating layer on said semiconductor devices and elsewhere on said substrate ; a patterned second polysilicon layer on said first insulating layer having openings aligned over said source/drain areas and said patterned second polysilicon layer providing electrically conducting portions elsewhere on said first insulating layer ; a second insulating layer on said patterned second polysilicon layer , and elsewhere on said first insulating layer , said second insulating layer being a low flow temperature glass that provides a planar surface ; said second insulating layer having contact openings aligned over and larger in width than said openings in said second polysilicon layer (first etch) ; and furthermore said first insulating layer having opening within said openings of said second polysilicon layer extending to said source/drain contact areas , said contact openings in said first insulating layer being self-aligned to the edge of said second polysilicon layer openings and having vertical sidewalls (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) ; and furthermore said second insulating layer having other contact openings elsewhere over and extend to the surface of said patterned second polysilicon layer , and said second and first insulating layers having contact openings to the surface of said substrate in regions free of said second polysilicon layer ; said contact openings having metal plugs the surface of which are coplanar with the surface of said second insulating layer ; a patterned first metal layer on said second insulating layer providing electrical interconnects to said substrate and said patterned second polysilicon layer by contacting said metal plugs while said self-aligned metal plug form interconnects between said patterned second polysilicon layer and said source/drain contact areas of said field effect transistors devices , thereby providing said completed buried metal plug structure . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5661084A Filed: 1996-10-04 Issued: 1997-08-26 Method for contact profile improvement (Original Assignee) Taiwan Semiconductor Manufacturing Co TSMC Ltd (Current Assignee) Taiwan Semiconductor Manufacturing Co TSMC Ltd So Wein Kuo, Tsu Shih |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region (conducting layer) such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer (etch rates, first etch) coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch (etch rates, first etch) stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch (second etch) stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5661084A CLAIM 1 . A method for making an electrical contact in the fabrication of an integrated circuit device comprising : providing semiconductor device structures in and on a semiconductor substrate ; forming an insulating layer structure comprising multiple layers of insulating material over said semiconductor device structures wherein there is a difference in etch rates (first etch (first etch, multiple etch stop insulation layer, first etch stop layer, etch process) , multiple etch stop insulation layer, first etch stop layer, etch process) between at least two of said multiple layers of insulating material wherein one of said insulating materials has a first etch rate and the other of said insulating materials has a second etch (second etch) rate ; forming a mask over said insulating layer structure with an opening above said semiconductor device structures to be electrically contacted ; etching a contact opening through said insulating layer structure not covered by said mask to said semiconductor device structures to be electrically contacted wherein because of said difference in etch rates between said at least two of said multiple layers of insulating material , the profile of said contact opening is not vertical because at least one of said insulating material layers having said first etch rate is etched horizontally more than the other said insulating material layers having said second etch rate and wherein native oxide builds up on the sidewalls of said contact opening ; dipping said substrate into a hydrofluoric acid solution to remove said native oxide on the sidewalls of said contact opening whereby said hydrofluoric acid etches said , insulating material layer having said first etch rate at a slower rate than said hydrofluoric acid etches said insulating material layers having said second etch rate whereby said contact profile is made vertical ; sputter depositing a glue layer over the surface of said insulating layer structure and within said contact opening ; and depositing a conducting layer (spacer region) over said glue layer wherein said conducting layer fills said contact opening completing said electrical contact in the fabrication of said integrated circuit device . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch (etch rates, first etch) stop layer protects removal of a substrate material by an etch process (etch rates, first etch) . |
US5661084A CLAIM 1 . A method for making an electrical contact in the fabrication of an integrated circuit device comprising : providing semiconductor device structures in and on a semiconductor substrate ; forming an insulating layer structure comprising multiple layers of insulating material over said semiconductor device structures wherein there is a difference in etch rates (first etch (first etch, multiple etch stop insulation layer, first etch stop layer, etch process) , multiple etch stop insulation layer, first etch stop layer, etch process) between at least two of said multiple layers of insulating material wherein one of said insulating materials has a first etch rate and the other of said insulating materials has a second etch rate ; forming a mask over said insulating layer structure with an opening above said semiconductor device structures to be electrically contacted ; etching a contact opening through said insulating layer structure not covered by said mask to said semiconductor device structures to be electrically contacted wherein because of said difference in etch rates between said at least two of said multiple layers of insulating material , the profile of said contact opening is not vertical because at least one of said insulating material layers having said first etch rate is etched horizontally more than the other said insulating material layers having said second etch rate and wherein native oxide builds up on the sidewalls of said contact opening ; dipping said substrate into a hydrofluoric acid solution to remove said native oxide on the sidewalls of said contact opening whereby said hydrofluoric acid etches said , insulating material layer having said first etch rate at a slower rate than said hydrofluoric acid etches said insulating material layers having said second etch rate whereby said contact profile is made vertical ; sputter depositing a glue layer over the surface of said insulating layer structure and within said contact opening ; and depositing a conducting layer over said glue layer wherein said conducting layer fills said contact opening completing said electrical contact in the fabrication of said integrated circuit device . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch (second etch) stop layer protects lower layers during an etching process . |
US5661084A CLAIM 1 . A method for making an electrical contact in the fabrication of an integrated circuit device comprising : providing semiconductor device structures in and on a semiconductor substrate ; forming an insulating layer structure comprising multiple layers of insulating material over said semiconductor device structures wherein there is a difference in etch rates between at least two of said multiple layers of insulating material wherein one of said insulating materials has a first etch rate and the other of said insulating materials has a second etch (second etch) rate ; forming a mask over said insulating layer structure with an opening above said semiconductor device structures to be electrically contacted ; etching a contact opening through said insulating layer structure not covered by said mask to said semiconductor device structures to be electrically contacted wherein because of said difference in etch rates between said at least two of said multiple layers of insulating material , the profile of said contact opening is not vertical because at least one of said insulating material layers having said first etch rate is etched horizontally more than the other said insulating material layers having said second etch rate and wherein native oxide builds up on the sidewalls of said contact opening ; dipping said substrate into a hydrofluoric acid solution to remove said native oxide on the sidewalls of said contact opening whereby said hydrofluoric acid etches said , insulating material layer having said first etch rate at a slower rate than said hydrofluoric acid etches said insulating material layers having said second etch rate whereby said contact profile is made vertical ; sputter depositing a glue layer over the surface of said insulating layer structure and within said contact opening ; and depositing a conducting layer over said glue layer wherein said conducting layer fills said contact opening completing said electrical contact in the fabrication of said integrated circuit device . |
| US7977797B2 CLAIM 6 . An integrated circuit of claim 1 wherein said spacer region (conducting layer) insulates said contact region . |
US5661084A CLAIM 1 . A method for making an electrical contact in the fabrication of an integrated circuit device comprising : providing semiconductor device structures in and on a semiconductor substrate ; forming an insulating layer structure comprising multiple layers of insulating material over said semiconductor device structures wherein there is a difference in etch rates between at least two of said multiple layers of insulating material wherein one of said insulating materials has a first etch rate and the other of said insulating materials has a second etch rate ; forming a mask over said insulating layer structure with an opening above said semiconductor device structures to be electrically contacted ; etching a contact opening through said insulating layer structure not covered by said mask to said semiconductor device structures to be electrically contacted wherein because of said difference in etch rates between said at least two of said multiple layers of insulating material , the profile of said contact opening is not vertical because at least one of said insulating material layers having said first etch rate is etched horizontally more than the other said insulating material layers having said second etch rate and wherein native oxide builds up on the sidewalls of said contact opening ; dipping said substrate into a hydrofluoric acid solution to remove said native oxide on the sidewalls of said contact opening whereby said hydrofluoric acid etches said , insulating material layer having said first etch rate at a slower rate than said hydrofluoric acid etches said insulating material layers having said second etch rate whereby said contact profile is made vertical ; sputter depositing a glue layer over the surface of said insulating layer structure and within said contact opening ; and depositing a conducting layer (spacer region) over said glue layer wherein said conducting layer fills said contact opening completing said electrical contact in the fabrication of said integrated circuit device . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch (etch rates, first etch) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (second etch) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5661084A CLAIM 1 . A method for making an electrical contact in the fabrication of an integrated circuit device comprising : providing semiconductor device structures in and on a semiconductor substrate ; forming an insulating layer structure comprising multiple layers of insulating material over said semiconductor device structures wherein there is a difference in etch rates (first etch (first etch, multiple etch stop insulation layer, first etch stop layer, etch process) , multiple etch stop insulation layer, first etch stop layer, etch process) between at least two of said multiple layers of insulating material wherein one of said insulating materials has a first etch rate and the other of said insulating materials has a second etch (second etch) rate ; forming a mask over said insulating layer structure with an opening above said semiconductor device structures to be electrically contacted ; etching a contact opening through said insulating layer structure not covered by said mask to said semiconductor device structures to be electrically contacted wherein because of said difference in etch rates between said at least two of said multiple layers of insulating material , the profile of said contact opening is not vertical because at least one of said insulating material layers having said first etch rate is etched horizontally more than the other said insulating material layers having said second etch rate and wherein native oxide builds up on the sidewalls of said contact opening ; dipping said substrate into a hydrofluoric acid solution to remove said native oxide on the sidewalls of said contact opening whereby said hydrofluoric acid etches said , insulating material layer having said first etch rate at a slower rate than said hydrofluoric acid etches said insulating material layers having said second etch rate whereby said contact profile is made vertical ; sputter depositing a glue layer over the surface of said insulating layer structure and within said contact opening ; and depositing a conducting layer over said glue layer wherein said conducting layer fills said contact opening completing said electrical contact in the fabrication of said integrated circuit device . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space (said sub) in a portion of said first sub interlevel dielectric layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5661084A CLAIM 1 . A method for making an electrical contact in the fabrication of an integrated circuit device comprising : providing semiconductor device structures in and on a semiconductor substrate ; forming an insulating layer structure comprising multiple layers of insulating material over said semiconductor device structures wherein there is a difference in etch rates between at least two of said multiple layers of insulating material wherein one of said insulating materials has a first etch rate and the other of said insulating materials has a second etch rate ; forming a mask over said insulating layer structure with an opening above said semiconductor device structures to be electrically contacted ; etching a contact opening through said insulating layer structure not covered by said mask to said semiconductor device structures to be electrically contacted wherein because of said difference in etch rates between said at least two of said multiple layers of insulating material , the profile of said contact opening is not vertical because at least one of said insulating material layers having said first etch rate is etched horizontally more than the other said insulating material layers having said second etch rate and wherein native oxide builds up on the sidewalls of said contact opening ; dipping said sub (first space) strate into a hydrofluoric acid solution to remove said native oxide on the sidewalls of said contact opening whereby said hydrofluoric acid etches said , insulating material layer having said first etch rate at a slower rate than said hydrofluoric acid etches said insulating material layers having said second etch rate whereby said contact profile is made vertical ; sputter depositing a glue layer over the surface of said insulating layer structure and within said contact opening ; and depositing a conducting layer over said glue layer wherein said conducting layer fills said contact opening completing said electrical contact in the fabrication of said integrated circuit device . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer (etch rates, first etch) comprising a first etch (etch rates, first etch) stop layer and a second etch (second etch) stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US5661084A CLAIM 1 . A method for making an electrical contact in the fabrication of an integrated circuit device comprising : providing semiconductor device structures in and on a semiconductor substrate ; forming an insulating layer structure comprising multiple layers of insulating material over said semiconductor device structures wherein there is a difference in etch rates (first etch (first etch, multiple etch stop insulation layer, first etch stop layer, etch process) , multiple etch stop insulation layer, first etch stop layer, etch process) between at least two of said multiple layers of insulating material wherein one of said insulating materials has a first etch rate and the other of said insulating materials has a second etch (second etch) rate ; forming a mask over said insulating layer structure with an opening above said semiconductor device structures to be electrically contacted ; etching a contact opening through said insulating layer structure not covered by said mask to said semiconductor device structures to be electrically contacted wherein because of said difference in etch rates between said at least two of said multiple layers of insulating material , the profile of said contact opening is not vertical because at least one of said insulating material layers having said first etch rate is etched horizontally more than the other said insulating material layers having said second etch rate and wherein native oxide builds up on the sidewalls of said contact opening ; dipping said substrate into a hydrofluoric acid solution to remove said native oxide on the sidewalls of said contact opening whereby said hydrofluoric acid etches said , insulating material layer having said first etch rate at a slower rate than said hydrofluoric acid etches said insulating material layers having said second etch rate whereby said contact profile is made vertical ; sputter depositing a glue layer over the surface of said insulating layer structure and within said contact opening ; and depositing a conducting layer over said glue layer wherein said conducting layer fills said contact opening completing said electrical contact in the fabrication of said integrated circuit device . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch (etch rates, first etch) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (second etch) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5661084A CLAIM 1 . A method for making an electrical contact in the fabrication of an integrated circuit device comprising : providing semiconductor device structures in and on a semiconductor substrate ; forming an insulating layer structure comprising multiple layers of insulating material over said semiconductor device structures wherein there is a difference in etch rates (first etch (first etch, multiple etch stop insulation layer, first etch stop layer, etch process) , multiple etch stop insulation layer, first etch stop layer, etch process) between at least two of said multiple layers of insulating material wherein one of said insulating materials has a first etch rate and the other of said insulating materials has a second etch (second etch) rate ; forming a mask over said insulating layer structure with an opening above said semiconductor device structures to be electrically contacted ; etching a contact opening through said insulating layer structure not covered by said mask to said semiconductor device structures to be electrically contacted wherein because of said difference in etch rates between said at least two of said multiple layers of insulating material , the profile of said contact opening is not vertical because at least one of said insulating material layers having said first etch rate is etched horizontally more than the other said insulating material layers having said second etch rate and wherein native oxide builds up on the sidewalls of said contact opening ; dipping said substrate into a hydrofluoric acid solution to remove said native oxide on the sidewalls of said contact opening whereby said hydrofluoric acid etches said , insulating material layer having said first etch rate at a slower rate than said hydrofluoric acid etches said insulating material layers having said second etch rate whereby said contact profile is made vertical ; sputter depositing a glue layer over the surface of said insulating layer structure and within said contact opening ; and depositing a conducting layer over said glue layer wherein said conducting layer fills said contact opening completing said electrical contact in the fabrication of said integrated circuit device . |
| US7977797B2 CLAIM 13 . An integrated circuit of claim 11 further comprising a floating gate (drain regions) . |
US5661084A CLAIM 2 . The method according to claim 1 wherein said semiconductor device structures to be electrically contacted are source/drain regions (floating gate) of a CMOS integrated circuit device . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US6033969A Filed: 1996-09-30 Issued: 2000-03-07 Method of forming a shallow trench isolation that has rounded and protected corners (Original Assignee) Taiwan Semiconductor Manufacturing Co TSMC Ltd (Current Assignee) TSMC China Co Ltd Chue-San Yoo, R. Y. Lee, J. H. Tsai |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch (silicon nitride layer, wet etch, dry etch) stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch (silicon nitride layer, wet etch, dry etch) stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch (silicon nitride layer, wet etch, dry etch) stop layer (silicon nitride layer, wet etch, dry etch) over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US6033969A CLAIM 1 . A method of forming a shallow trench isolation that has rounded and protected corners comprising the steps of : providing a silicon substrate , forming a layer of silicon nitride on said substrate , forming an opening through said layer of silicon nitride and exposing a first area of said silicon substrate , forming a bird' ; s beak field oxide layer in said first area of silicon substrate having a center portion having a thickness of at least about 500 Å and a substantially tapered edge portion , anisotropically etching said center portion of the field oxide layer not covered by said silicon nitride layer (second etch stop layers, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch) without using oxide sidewall spacers exposing a second area of said silicon substrate , anisotropically etching said silicon substrate in said exposed second area to a depth of not more than 5000 Å forming a shallow trench having rounded top and bottom corners , said substantially tapered edge portion of said field oxide layer protects said top corner of the trench from being etched , and filling said shallow trench with silicon oxide . US6033969A CLAIM 3 . A method according to claim 1 , wherein the opening through said layer of silicon nitride is formed by a wet etch (second etch stop layers, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch) or dry etch (second etch stop layers, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch) method . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch (silicon nitride layer, wet etch, dry etch) stop layer protects removal of a substrate material (silicon oxide) by an etch process (silicon nitride layer, wet etch, dry etch) . |
US6033969A CLAIM 1 . A method of forming a shallow trench isolation that has rounded and protected corners comprising the steps of : providing a silicon substrate , forming a layer of silicon nitride on said substrate , forming an opening through said layer of silicon nitride and exposing a first area of said silicon substrate , forming a bird' ; s beak field oxide layer in said first area of silicon substrate having a center portion having a thickness of at least about 500 Å and a substantially tapered edge portion , anisotropically etching said center portion of the field oxide layer not covered by said silicon nitride layer (second etch stop layers, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch) without using oxide sidewall spacers exposing a second area of said silicon substrate , anisotropically etching said silicon substrate in said exposed second area to a depth of not more than 5000 Å forming a shallow trench having rounded top and bottom corners , said substantially tapered edge portion of said field oxide layer protects said top corner of the trench from being etched , and filling said shallow trench with silicon oxide (substrate material) . US6033969A CLAIM 3 . A method according to claim 1 , wherein the opening through said layer of silicon nitride is formed by a wet etch (second etch stop layers, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch) or dry etch (second etch stop layers, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch) method . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch (silicon nitride layer, wet etch, dry etch) stop layer (silicon nitride layer, wet etch, dry etch) protects lower layers during an etching process (second area) . |
US6033969A CLAIM 1 . A method of forming a shallow trench isolation that has rounded and protected corners comprising the steps of : providing a silicon substrate , forming a layer of silicon nitride on said substrate , forming an opening through said layer of silicon nitride and exposing a first area of said silicon substrate , forming a bird' ; s beak field oxide layer in said first area of silicon substrate having a center portion having a thickness of at least about 500 Å and a substantially tapered edge portion , anisotropically etching said center portion of the field oxide layer not covered by said silicon nitride layer (second etch stop layers, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch) without using oxide sidewall spacers exposing a second area (etching process) of said silicon substrate , anisotropically etching said silicon substrate in said exposed second area to a depth of not more than 5000 Å forming a shallow trench having rounded top and bottom corners , said substantially tapered edge portion of said field oxide layer protects said top corner of the trench from being etched , and filling said shallow trench with silicon oxide . US6033969A CLAIM 3 . A method according to claim 1 , wherein the opening through said layer of silicon nitride is formed by a wet etch (second etch stop layers, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch) or dry etch (second etch stop layers, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch) method . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch (silicon nitride layer, wet etch, dry etch) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (silicon nitride layer, wet etch, dry etch) stop layer (silicon nitride layer, wet etch, dry etch) is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6033969A CLAIM 1 . A method of forming a shallow trench isolation that has rounded and protected corners comprising the steps of : providing a silicon substrate , forming a layer of silicon nitride on said substrate , forming an opening through said layer of silicon nitride and exposing a first area of said silicon substrate , forming a bird' ; s beak field oxide layer in said first area of silicon substrate having a center portion having a thickness of at least about 500 Å and a substantially tapered edge portion , anisotropically etching said center portion of the field oxide layer not covered by said silicon nitride layer (second etch stop layers, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch) without using oxide sidewall spacers exposing a second area of said silicon substrate , anisotropically etching said silicon substrate in said exposed second area to a depth of not more than 5000 Å forming a shallow trench having rounded top and bottom corners , said substantially tapered edge portion of said field oxide layer protects said top corner of the trench from being etched , and filling said shallow trench with silicon oxide . US6033969A CLAIM 3 . A method according to claim 1 , wherein the opening through said layer of silicon nitride is formed by a wet etch (second etch stop layers, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch) or dry etch (second etch stop layers, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch) method . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space (said sub) in a portion of said first sub interlevel dielectric layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US6033969A CLAIM 1 . A method of forming a shallow trench isolation that has rounded and protected corners comprising the steps of : providing a silicon substrate , forming a layer of silicon nitride on said sub (first space) strate , forming an opening through said layer of silicon nitride and exposing a first area of said silicon substrate , forming a bird' ; s beak field oxide layer in said first area of silicon substrate having a center portion having a thickness of at least about 500 Å and a substantially tapered edge portion , anisotropically etching said center portion of the field oxide layer not covered by said silicon nitride layer without using oxide sidewall spacers exposing a second area of said silicon substrate , anisotropically etching said silicon substrate in said exposed second area to a depth of not more than 5000 Å forming a shallow trench having rounded top and bottom corners , said substantially tapered edge portion of said field oxide layer protects said top corner of the trench from being etched , and filling said shallow trench with silicon oxide . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US6033969A CLAIM 10 . A method according to claim 1 further comprising the step of forming a paid oxide layer on said substrate prior to forming said nitride layer , and forming (anti reflective coating) an opening through said layers of pad oxide and silicon nitride to expose a first area of said silicon substrate . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch (silicon nitride layer, wet etch, dry etch) stop insulation layer comprising a first etch (silicon nitride layer, wet etch, dry etch) stop layer and a second etch (silicon nitride layer, wet etch, dry etch) stop layer (silicon nitride layer, wet etch, dry etch) wherein said first etch stop layer and said second etch stop layers (silicon nitride layer, wet etch, dry etch) have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US6033969A CLAIM 1 . A method of forming a shallow trench isolation that has rounded and protected corners comprising the steps of : providing a silicon substrate , forming a layer of silicon nitride on said substrate , forming an opening through said layer of silicon nitride and exposing a first area of said silicon substrate , forming a bird' ; s beak field oxide layer in said first area of silicon substrate having a center portion having a thickness of at least about 500 Å and a substantially tapered edge portion , anisotropically etching said center portion of the field oxide layer not covered by said silicon nitride layer (second etch stop layers, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch) without using oxide sidewall spacers exposing a second area of said silicon substrate , anisotropically etching said silicon substrate in said exposed second area to a depth of not more than 5000 Å forming a shallow trench having rounded top and bottom corners , said substantially tapered edge portion of said field oxide layer protects said top corner of the trench from being etched , and filling said shallow trench with silicon oxide . US6033969A CLAIM 3 . A method according to claim 1 , wherein the opening through said layer of silicon nitride is formed by a wet etch (second etch stop layers, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch) or dry etch (second etch stop layers, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch) method . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch (silicon nitride layer, wet etch, dry etch) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (silicon nitride layer, wet etch, dry etch) stop layer (silicon nitride layer, wet etch, dry etch) is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US6033969A CLAIM 1 . A method of forming a shallow trench isolation that has rounded and protected corners comprising the steps of : providing a silicon substrate , forming a layer of silicon nitride on said substrate , forming an opening through said layer of silicon nitride and exposing a first area of said silicon substrate , forming a bird' ; s beak field oxide layer in said first area of silicon substrate having a center portion having a thickness of at least about 500 Å and a substantially tapered edge portion , anisotropically etching said center portion of the field oxide layer not covered by said silicon nitride layer (second etch stop layers, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch) without using oxide sidewall spacers exposing a second area of said silicon substrate , anisotropically etching said silicon substrate in said exposed second area to a depth of not more than 5000 Å forming a shallow trench having rounded top and bottom corners , said substantially tapered edge portion of said field oxide layer protects said top corner of the trench from being etched , and filling said shallow trench with silicon oxide . US6033969A CLAIM 3 . A method according to claim 1 , wherein the opening through said layer of silicon nitride is formed by a wet etch (second etch stop layers, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch) or dry etch (second etch stop layers, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, second etch stop layer, etch process, second etch) method . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US6033969A CLAIM 10 . A method according to claim 1 further comprising the step of forming a paid oxide layer on said substrate prior to forming said nitride layer , and forming (anti reflective coating) an opening through said layers of pad oxide and silicon nitride to expose a first area of said silicon substrate . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5792687A Filed: 1996-08-01 Issued: 1998-08-11 Method for fabricating high density integrated circuits using oxide and polysilicon spacers (Original Assignee) Vanguard International Semiconductor Corp (Current Assignee) Vanguard International Semiconductor Corp Erik S. Jeng, Ing-Ruey Liaw |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region (gate electrodes) such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch (gate oxide) stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5792687A CLAIM 1 . A method of fabricating interconnects and capacitors on a semiconductor substrate having device areas and spaced isolation regions formed therein , comprising the steps of : a) providing a substrate having transistors in said active areas , said transistors comprising source regions , drain regions , and gate electrodes (spacer region) ; b) forming a conformal oxide layer over a resultant surface from step a ; c) forming an interlevel dielectric layer over said conformal oxide layer ; d) forming a first polysilicon layer over said interlevel dielectric layer ; e) masking and etching said first polysilicon layer and said interlevel dielectric layer forming first openings over said source and drain regions , said first openings defined by first sidewalls of said first polysilicon layer and said interlevel dielectric layer ; f) forming first sidewall spacers on said first sidewalls ; g) forming node contact holes and bitline contact holes by etching said interlevel dielectric layer using said first polysilicon layer and said first sidewall spacers as a mask , said node contact holes exposing said source regions and said bitline contact holes exposing said drain regions ; h) filling said node contact holes with node plugs and filling said bitline contact holes with bitline plugs ; i) forming a polycide layer over said interlevel dielectric layer , said bitline plugs and said node plugs ; j) forming a first oxide layer over said polycide layer ; k) patterning and etching said first oxide layer , said polycide layer , said first polysilicon layer , said first sidewall spacers , and portions of said node plugs forming capacitor openings and bit lines , said capacitor openings defined by second sidewalls of said first oxide layer , said polycide layer , and said first polysilicon layer ; l) forming second sidewall spacers on said second sidewalls ; and m) forming an electrode plate filling said first openings and forming an electrical contact to said node plugs thereby forming an interconnect to said source regions . US5792687A CLAIM 12 . A method of fabricating interconnects and capacitors on a semiconductor substrate having device areas and spaced isolation regions formed therein , comprising the steps of : a) forming a gate oxide (second etch) layer over said substrate ; b) forming a first conductive layer over said gate oxide layer ; c) forming a gate dielectric layer over said first conductive layer , said gate dielectric layer composed of silicon oxide ; d) patterning said gate oxide layer , said first conductive layer and said gate dielectric layer to form spaced gate electrodes over said device areas and conductive structures over said isolation regions ; e) forming a first isolation layer composed of silicon oxide over the substrate surface resulting from step d ; f) anisotropically etching said first isolation layer thereby forming gate sidewall spacers on sidewalls of said gate electrodes and on sidewalls of said conductive structures ; g) implanting impurity ions into said substrate using said gate electrodes and said gate sidewall spacers as a mask forming source regions and drain regions ; h) forming a conformal oxide layer over the resultant surface from step g ; i) forming an interlevel dielectric (ILD) layer over said conformal oxide layer , said interlevel dielectric layer formed of borophosphosilicate glass ; j) forming a first polysilicon layer over said interlevel dielectric (ILD) layer ; k) masking and etching said first polysilicon layer and said interlevel dielectric layer forming first openings over said source and drain regions , said first openings defined by first sidewalls of said first polysilicon layer and said interlevel dielectric layer ; l) forming first sidewall spacers of composed polysilicon on said first sidewalls ; m) forming node contact holes and bitline contact holes by etching said interlevel dielectric layer using said first polysilicon layer and said first sidewall spacers as a mask , said node contact holes exposing said source regions and said bitline contact holes exposing said drain regions ; n) filling said node contact holes with node plugs and filling said bitline contact holes with bitline plugs ; o) forming a tungsten silicide layer over said interlevel dielectric layer , said bitline plugs and said node plugs ; p) forming a first oxide layer over said tungsten silicide layer ; q) patterning and etching said first oxide layer , said tungsten silicide layer , said first polysilicon layer , said first sidewall spacers , and portions of said node plugs forming capacitor openings and bit lines , said capacitor openings defined by second sidewalls of said first oxide layer , said tungsten silicide layer , and said first polysilicon layer ; r) forming second sidewall spacers composed of silicon oxide on said second sidewalls ; s) forming an electrode plate filling said first openings and forming an electrical contact to said node plugs thereby forming an interconnect to said source regions ; t) forming a capacitor dielectric layer and a top electrode layer over said electrode plate thereby forming a capacitor and completing a memory cell . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer protects removal of a substrate material (silicon oxide) by an etch process . |
US5792687A CLAIM 3 . The method of claim 1 wherein said first sidewall spacers are comprised of polysilicon and said second sidewall spacers are formed of silicon oxide (substrate material) . |
| US7977797B2 CLAIM 6 . An integrated circuit of claim 1 wherein said spacer region (gate electrodes) insulates said contact region . |
US5792687A CLAIM 1 . A method of fabricating interconnects and capacitors on a semiconductor substrate having device areas and spaced isolation regions formed therein , comprising the steps of : a) providing a substrate having transistors in said active areas , said transistors comprising source regions , drain regions , and gate electrodes (spacer region) ; b) forming a conformal oxide layer over a resultant surface from step a ; c) forming an interlevel dielectric layer over said conformal oxide layer ; d) forming a first polysilicon layer over said interlevel dielectric layer ; e) masking and etching said first polysilicon layer and said interlevel dielectric layer forming first openings over said source and drain regions , said first openings defined by first sidewalls of said first polysilicon layer and said interlevel dielectric layer ; f) forming first sidewall spacers on said first sidewalls ; g) forming node contact holes and bitline contact holes by etching said interlevel dielectric layer using said first polysilicon layer and said first sidewall spacers as a mask , said node contact holes exposing said source regions and said bitline contact holes exposing said drain regions ; h) filling said node contact holes with node plugs and filling said bitline contact holes with bitline plugs ; i) forming a polycide layer over said interlevel dielectric layer , said bitline plugs and said node plugs ; j) forming a first oxide layer over said polycide layer ; k) patterning and etching said first oxide layer , said polycide layer , said first polysilicon layer , said first sidewall spacers , and portions of said node plugs forming capacitor openings and bit lines , said capacitor openings defined by second sidewalls of said first oxide layer , said polycide layer , and said first polysilicon layer ; l) forming second sidewall spacers on said second sidewalls ; and m) forming an electrode plate filling said first openings and forming an electrical contact to said node plugs thereby forming an interconnect to said source regions . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US5792687A CLAIM 1 . A method of fabricating interconnects and capacitors on a semiconductor substrate having device areas and spaced isolation regions formed therein , comprising the steps of : a) providing a substrate having transistors in said active areas , said transistors comprising source regions , drain regions , and gate electrodes ; b) forming a conformal oxide layer over a resultant surface from step a ; c) forming an interlevel dielectric layer over said conformal oxide layer ; d) forming a first polysilicon layer over said interlevel dielectric layer ; e) masking and etching said first polysilicon layer and said interlevel dielectric layer forming first openings over said source and drain regions , said first openings defined by first sidewalls of said first polysilicon layer and said interlevel dielectric layer ; f) forming first sidewall spacers on said first sidewalls ; g) forming node contact holes and bitline contact holes by etching said interlevel dielectric layer using said first polysilicon layer and said first sidewall spacers as a mask , said node contact holes exposing said source regions and said bitline contact holes exposing said drain regions ; h) filling said node contact holes with node plugs and filling said bitline contact holes with bitline plugs ; i) forming a polycide layer over said interlevel dielectric layer , said bitline plugs and said node plugs ; j) forming a first oxide layer over said polycide layer ; k) patterning and etching said first oxide layer , said polycide layer , said first polysilicon layer , said first sidewall spacers , and portions of said node plugs forming capacitor openings and bit lines , said capacitor openings defined by second sidewalls of said first oxide layer , said polycide layer , and said first polysilicon layer ; l) forming second sidewall spacers on said second sidewalls ; and m) forming an electrode plate filling said first openings and forming (anti reflective coating) an electrical contact to said node plugs thereby forming an interconnect to said source regions . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch (gate oxide) stop layer wherein said first etch stop layer and said second etch stop layers (second sidewall spacer, first sidewall spacer, drain regions) have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US5792687A CLAIM 1 . A method of fabricating interconnects and capacitors on a semiconductor substrate having device areas and spaced isolation regions formed therein , comprising the steps of : a) providing a substrate having transistors in said active areas , said transistors comprising source regions , drain regions (second etch stop layers, floating gate) , and gate electrodes ; b) forming a conformal oxide layer over a resultant surface from step a ; c) forming an interlevel dielectric layer over said conformal oxide layer ; d) forming a first polysilicon layer over said interlevel dielectric layer ; e) masking and etching said first polysilicon layer and said interlevel dielectric layer forming first openings over said source and drain regions , said first openings defined by first sidewalls of said first polysilicon layer and said interlevel dielectric layer ; f) forming first sidewall spacer (second etch stop layers, floating gate) s on said first sidewalls ; g) forming node contact holes and bitline contact holes by etching said interlevel dielectric layer using said first polysilicon layer and said first sidewall spacers as a mask , said node contact holes exposing said source regions and said bitline contact holes exposing said drain regions ; h) filling said node contact holes with node plugs and filling said bitline contact holes with bitline plugs ; i) forming a polycide layer over said interlevel dielectric layer , said bitline plugs and said node plugs ; j) forming a first oxide layer over said polycide layer ; k) patterning and etching said first oxide layer , said polycide layer , said first polysilicon layer , said first sidewall spacers , and portions of said node plugs forming capacitor openings and bit lines , said capacitor openings defined by second sidewalls of said first oxide layer , said polycide layer , and said first polysilicon layer ; l) forming second sidewall spacer (second etch stop layers, floating gate) s on said second sidewalls ; and m) forming an electrode plate filling said first openings and forming an electrical contact to said node plugs thereby forming an interconnect to said source regions . |
| US7977797B2 CLAIM 13 . An integrated circuit of claim 11 further comprising a floating gate (second sidewall spacer, first sidewall spacer, drain regions) . |
US5792687A CLAIM 1 . A method of fabricating interconnects and capacitors on a semiconductor substrate having device areas and spaced isolation regions formed therein , comprising the steps of : a) providing a substrate having transistors in said active areas , said transistors comprising source regions , drain regions (second etch stop layers, floating gate) , and gate electrodes ; b) forming a conformal oxide layer over a resultant surface from step a ; c) forming an interlevel dielectric layer over said conformal oxide layer ; d) forming a first polysilicon layer over said interlevel dielectric layer ; e) masking and etching said first polysilicon layer and said interlevel dielectric layer forming first openings over said source and drain regions , said first openings defined by first sidewalls of said first polysilicon layer and said interlevel dielectric layer ; f) forming first sidewall spacer (second etch stop layers, floating gate) s on said first sidewalls ; g) forming node contact holes and bitline contact holes by etching said interlevel dielectric layer using said first polysilicon layer and said first sidewall spacers as a mask , said node contact holes exposing said source regions and said bitline contact holes exposing said drain regions ; h) filling said node contact holes with node plugs and filling said bitline contact holes with bitline plugs ; i) forming a polycide layer over said interlevel dielectric layer , said bitline plugs and said node plugs ; j) forming a first oxide layer over said polycide layer ; k) patterning and etching said first oxide layer , said polycide layer , said first polysilicon layer , said first sidewall spacers , and portions of said node plugs forming capacitor openings and bit lines , said capacitor openings defined by second sidewalls of said first oxide layer , said polycide layer , and said first polysilicon layer ; l) forming second sidewall spacer (second etch stop layers, floating gate) s on said second sidewalls ; and m) forming an electrode plate filling said first openings and forming an electrical contact to said node plugs thereby forming an interconnect to said source regions . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US5792687A CLAIM 1 . A method of fabricating interconnects and capacitors on a semiconductor substrate having device areas and spaced isolation regions formed therein , comprising the steps of : a) providing a substrate having transistors in said active areas , said transistors comprising source regions , drain regions , and gate electrodes ; b) forming a conformal oxide layer over a resultant surface from step a ; c) forming an interlevel dielectric layer over said conformal oxide layer ; d) forming a first polysilicon layer over said interlevel dielectric layer ; e) masking and etching said first polysilicon layer and said interlevel dielectric layer forming first openings over said source and drain regions , said first openings defined by first sidewalls of said first polysilicon layer and said interlevel dielectric layer ; f) forming first sidewall spacers on said first sidewalls ; g) forming node contact holes and bitline contact holes by etching said interlevel dielectric layer using said first polysilicon layer and said first sidewall spacers as a mask , said node contact holes exposing said source regions and said bitline contact holes exposing said drain regions ; h) filling said node contact holes with node plugs and filling said bitline contact holes with bitline plugs ; i) forming a polycide layer over said interlevel dielectric layer , said bitline plugs and said node plugs ; j) forming a first oxide layer over said polycide layer ; k) patterning and etching said first oxide layer , said polycide layer , said first polysilicon layer , said first sidewall spacers , and portions of said node plugs forming capacitor openings and bit lines , said capacitor openings defined by second sidewalls of said first oxide layer , said polycide layer , and said first polysilicon layer ; l) forming second sidewall spacers on said second sidewalls ; and m) forming an electrode plate filling said first openings and forming (anti reflective coating) an electrical contact to said node plugs thereby forming an interconnect to said source regions . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5994762A Filed: 1996-07-26 Issued: 1999-11-30 Semiconductor integrated circuit device including boron-doped phospho silicate glass layer and manufacturing method thereof (Original Assignee) Thin Film Research Center, Hitachi''s Central Research Laboratory, Hitachi, Ibaraki, Japan (Current Assignee) Hitachi Hokkai Semiconductor Ltd ; Renesas Electronics Corp Naokatsu Suwanai, Yasuhide Fujioka |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region (first boundary) coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region (first boundary) such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer (n storage) over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5994762A CLAIM 9 . A semiconductor integrated circuit device comprising : an interlayer insulation film deposited on a semiconductor chip including a first boron-containing silicon oxide film and a second film , not containing boron , formed on the first boron-containing silicon oxide film ; a passivation film , having a higher rigidity than first boron-containing film , formed on the second film ; and a slit , disposed along the periphery of the semiconductor chip , to extend to a predetermined depth from an upper surface of the passivation film into the semiconductor integrated device , wherein the location and depth of the slit are selected to prevent the spread of cracks caused by poor adhesion between the first boron-containing silicon oxide film and the second film which does not contain boron , wherein the integrated semiconductor circuit is a DRAM having a memory cell of a stacked structure in which an information storage (first sub interlevel dielectric layer) capacitance device is disposed above a memory cell selecting MISFET . US5994762A CLAIM 24 . A method of manufacturing a semiconductor integrated circuit device on a semiconductor wafer at a device forming area which is surrounded by a scribe line comprising the steps of : forming a first insulation film over a main surface of the semiconductor wafer ; forming a second insulation film over the first insulation film ; forming a third insulation film over the main surface of the semiconductor wafer ; forming a fourth insulation film over the third insulation film ; forming a first conductor layer over the main surface of the semiconductor wafer ; forming a fifth insulation film of a silicon nitride film over the first conductor layer ; forming an aperture in the fifth insulation film to reveal the first conductor layer in order to form a bonding pad , and forming a slit at a periphery of the device forming area in the fifth insulation film ; and dicing the semiconductor wafer on the scribe line to provide a chip ; wherein the adhesion at a first boundary (contact region, spacer region) between the first insulation film and the second insulation film is lower than the adhesion at a second boundary between the third insulation film and the fourth insulation film , and the slit is located between the bonding pad and the scribe line on the chip to prevent the spread of cracks caused by the lower adhesion between the first insulation film and the second insulation film . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric layer (n storage) insulates said contact region (first boundary) . |
US5994762A CLAIM 9 . A semiconductor integrated circuit device comprising : an interlayer insulation film deposited on a semiconductor chip including a first boron-containing silicon oxide film and a second film , not containing boron , formed on the first boron-containing silicon oxide film ; a passivation film , having a higher rigidity than first boron-containing film , formed on the second film ; and a slit , disposed along the periphery of the semiconductor chip , to extend to a predetermined depth from an upper surface of the passivation film into the semiconductor integrated device , wherein the location and depth of the slit are selected to prevent the spread of cracks caused by poor adhesion between the first boron-containing silicon oxide film and the second film which does not contain boron , wherein the integrated semiconductor circuit is a DRAM having a memory cell of a stacked structure in which an information storage (first sub interlevel dielectric layer) capacitance device is disposed above a memory cell selecting MISFET . US5994762A CLAIM 24 . A method of manufacturing a semiconductor integrated circuit device on a semiconductor wafer at a device forming area which is surrounded by a scribe line comprising the steps of : forming a first insulation film over a main surface of the semiconductor wafer ; forming a second insulation film over the first insulation film ; forming a third insulation film over the main surface of the semiconductor wafer ; forming a fourth insulation film over the third insulation film ; forming a first conductor layer over the main surface of the semiconductor wafer ; forming a fifth insulation film of a silicon nitride film over the first conductor layer ; forming an aperture in the fifth insulation film to reveal the first conductor layer in order to form a bonding pad , and forming a slit at a periphery of the device forming area in the fifth insulation film ; and dicing the semiconductor wafer on the scribe line to provide a chip ; wherein the adhesion at a first boundary (contact region, spacer region) between the first insulation film and the second insulation film is lower than the adhesion at a second boundary between the third insulation film and the fourth insulation film , and the slit is located between the bonding pad and the scribe line on the chip to prevent the spread of cracks caused by the lower adhesion between the first insulation film and the second insulation film . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric layer insulates said contact region (first boundary) . |
US5994762A CLAIM 24 . A method of manufacturing a semiconductor integrated circuit device on a semiconductor wafer at a device forming area which is surrounded by a scribe line comprising the steps of : forming a first insulation film over a main surface of the semiconductor wafer ; forming a second insulation film over the first insulation film ; forming a third insulation film over the main surface of the semiconductor wafer ; forming a fourth insulation film over the third insulation film ; forming a first conductor layer over the main surface of the semiconductor wafer ; forming a fifth insulation film of a silicon nitride film over the first conductor layer ; forming an aperture in the fifth insulation film to reveal the first conductor layer in order to form a bonding pad , and forming a slit at a periphery of the device forming area in the fifth insulation film ; and dicing the semiconductor wafer on the scribe line to provide a chip ; wherein the adhesion at a first boundary (contact region, spacer region) between the first insulation film and the second insulation film is lower than the adhesion at a second boundary between the third insulation film and the fourth insulation film , and the slit is located between the bonding pad and the scribe line on the chip to prevent the spread of cracks caused by the lower adhesion between the first insulation film and the second insulation film . |
| US7977797B2 CLAIM 6 . An integrated circuit of claim 1 wherein said spacer region (first boundary) insulates said contact region (first boundary) . |
US5994762A CLAIM 24 . A method of manufacturing a semiconductor integrated circuit device on a semiconductor wafer at a device forming area which is surrounded by a scribe line comprising the steps of : forming a first insulation film over a main surface of the semiconductor wafer ; forming a second insulation film over the first insulation film ; forming a third insulation film over the main surface of the semiconductor wafer ; forming a fourth insulation film over the third insulation film ; forming a first conductor layer over the main surface of the semiconductor wafer ; forming a fifth insulation film of a silicon nitride film over the first conductor layer ; forming an aperture in the fifth insulation film to reveal the first conductor layer in order to form a bonding pad , and forming a slit at a periphery of the device forming area in the fifth insulation film ; and dicing the semiconductor wafer on the scribe line to provide a chip ; wherein the adhesion at a first boundary (contact region, spacer region) between the first insulation film and the second insulation film is lower than the adhesion at a second boundary between the third insulation film and the fourth insulation film , and the slit is located between the bonding pad and the scribe line on the chip to prevent the spread of cracks caused by the lower adhesion between the first insulation film and the second insulation film . |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area of said contact region (first boundary) permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
US5994762A CLAIM 24 . A method of manufacturing a semiconductor integrated circuit device on a semiconductor wafer at a device forming area which is surrounded by a scribe line comprising the steps of : forming a first insulation film over a main surface of the semiconductor wafer ; forming a second insulation film over the first insulation film ; forming a third insulation film over the main surface of the semiconductor wafer ; forming a fourth insulation film over the third insulation film ; forming a first conductor layer over the main surface of the semiconductor wafer ; forming a fifth insulation film of a silicon nitride film over the first conductor layer ; forming an aperture in the fifth insulation film to reveal the first conductor layer in order to form a bonding pad , and forming a slit at a periphery of the device forming area in the fifth insulation film ; and dicing the semiconductor wafer on the scribe line to provide a chip ; wherein the adhesion at a first boundary (contact region, spacer region) between the first insulation film and the second insulation film is lower than the adhesion at a second boundary between the third insulation film and the fourth insulation film , and the slit is located between the bonding pad and the scribe line on the chip to prevent the spread of cracks caused by the lower adhesion between the first insulation film and the second insulation film . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer (n storage) is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5994762A CLAIM 9 . A semiconductor integrated circuit device comprising : an interlayer insulation film deposited on a semiconductor chip including a first boron-containing silicon oxide film and a second film , not containing boron , formed on the first boron-containing silicon oxide film ; a passivation film , having a higher rigidity than first boron-containing film , formed on the second film ; and a slit , disposed along the periphery of the semiconductor chip , to extend to a predetermined depth from an upper surface of the passivation film into the semiconductor integrated device , wherein the location and depth of the slit are selected to prevent the spread of cracks caused by poor adhesion between the first boron-containing silicon oxide film and the second film which does not contain boron , wherein the integrated semiconductor circuit is a DRAM having a memory cell of a stacked structure in which an information storage (first sub interlevel dielectric layer) capacitance device is disposed above a memory cell selecting MISFET . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric layer (n storage) for said contact region (first boundary) is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5994762A CLAIM 9 . A semiconductor integrated circuit device comprising : an interlayer insulation film deposited on a semiconductor chip including a first boron-containing silicon oxide film and a second film , not containing boron , formed on the first boron-containing silicon oxide film ; a passivation film , having a higher rigidity than first boron-containing film , formed on the second film ; and a slit , disposed along the periphery of the semiconductor chip , to extend to a predetermined depth from an upper surface of the passivation film into the semiconductor integrated device , wherein the location and depth of the slit are selected to prevent the spread of cracks caused by poor adhesion between the first boron-containing silicon oxide film and the second film which does not contain boron , wherein the integrated semiconductor circuit is a DRAM having a memory cell of a stacked structure in which an information storage (first sub interlevel dielectric layer) capacitance device is disposed above a memory cell selecting MISFET . US5994762A CLAIM 24 . A method of manufacturing a semiconductor integrated circuit device on a semiconductor wafer at a device forming area which is surrounded by a scribe line comprising the steps of : forming a first insulation film over a main surface of the semiconductor wafer ; forming a second insulation film over the first insulation film ; forming a third insulation film over the main surface of the semiconductor wafer ; forming a fourth insulation film over the third insulation film ; forming a first conductor layer over the main surface of the semiconductor wafer ; forming a fifth insulation film of a silicon nitride film over the first conductor layer ; forming an aperture in the fifth insulation film to reveal the first conductor layer in order to form a bonding pad , and forming a slit at a periphery of the device forming area in the fifth insulation film ; and dicing the semiconductor wafer on the scribe line to provide a chip ; wherein the adhesion at a first boundary (contact region, spacer region) between the first insulation film and the second insulation film is lower than the adhesion at a second boundary between the third insulation film and the fourth insulation film , and the slit is located between the bonding pad and the scribe line on the chip to prevent the spread of cracks caused by the lower adhesion between the first insulation film and the second insulation film . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US5994762A CLAIM 24 . A method of manufacturing a semiconductor integrated circuit device on a semiconductor wafer at a device forming area which is surrounded by a scribe line comprising the steps of : forming a first insulation film over a main surface of the semiconductor wafer ; forming a second insulation film over the first insulation film ; forming a third insulation film over the main surface of the semiconductor wafer ; forming a fourth insulation film over the third insulation film ; forming a first conductor layer over the main surface of the semiconductor wafer ; forming a fifth insulation film of a silicon nitride film over the first conductor layer ; forming an aperture in the fifth insulation film to reveal the first conductor layer in order to form a bonding pad , and forming (anti reflective coating) a slit at a periphery of the device forming area in the fifth insulation film ; and dicing the semiconductor wafer on the scribe line to provide a chip ; wherein the adhesion at a first boundary between the first insulation film and the second insulation film is lower than the adhesion at a second boundary between the third insulation film and the fourth insulation film , and the slit is located between the bonding pad and the scribe line on the chip to prevent the spread of cracks caused by the lower adhesion between the first insulation film and the second insulation film . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region (first boundary) and under a first sub interlevel dielectric layer (n storage) and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US5994762A CLAIM 9 . A semiconductor integrated circuit device comprising : an interlayer insulation film deposited on a semiconductor chip including a first boron-containing silicon oxide film and a second film , not containing boron , formed on the first boron-containing silicon oxide film ; a passivation film , having a higher rigidity than first boron-containing film , formed on the second film ; and a slit , disposed along the periphery of the semiconductor chip , to extend to a predetermined depth from an upper surface of the passivation film into the semiconductor integrated device , wherein the location and depth of the slit are selected to prevent the spread of cracks caused by poor adhesion between the first boron-containing silicon oxide film and the second film which does not contain boron , wherein the integrated semiconductor circuit is a DRAM having a memory cell of a stacked structure in which an information storage (first sub interlevel dielectric layer) capacitance device is disposed above a memory cell selecting MISFET . US5994762A CLAIM 24 . A method of manufacturing a semiconductor integrated circuit device on a semiconductor wafer at a device forming area which is surrounded by a scribe line comprising the steps of : forming a first insulation film over a main surface of the semiconductor wafer ; forming a second insulation film over the first insulation film ; forming a third insulation film over the main surface of the semiconductor wafer ; forming a fourth insulation film over the third insulation film ; forming a first conductor layer over the main surface of the semiconductor wafer ; forming a fifth insulation film of a silicon nitride film over the first conductor layer ; forming an aperture in the fifth insulation film to reveal the first conductor layer in order to form a bonding pad , and forming a slit at a periphery of the device forming area in the fifth insulation film ; and dicing the semiconductor wafer on the scribe line to provide a chip ; wherein the adhesion at a first boundary (contact region, spacer region) between the first insulation film and the second insulation film is lower than the adhesion at a second boundary between the third insulation film and the fourth insulation film , and the slit is located between the bonding pad and the scribe line on the chip to prevent the spread of cracks caused by the lower adhesion between the first insulation film and the second insulation film . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer (n storage) is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5994762A CLAIM 9 . A semiconductor integrated circuit device comprising : an interlayer insulation film deposited on a semiconductor chip including a first boron-containing silicon oxide film and a second film , not containing boron , formed on the first boron-containing silicon oxide film ; a passivation film , having a higher rigidity than first boron-containing film , formed on the second film ; and a slit , disposed along the periphery of the semiconductor chip , to extend to a predetermined depth from an upper surface of the passivation film into the semiconductor integrated device , wherein the location and depth of the slit are selected to prevent the spread of cracks caused by poor adhesion between the first boron-containing silicon oxide film and the second film which does not contain boron , wherein the integrated semiconductor circuit is a DRAM having a memory cell of a stacked structure in which an information storage (first sub interlevel dielectric layer) capacitance device is disposed above a memory cell selecting MISFET . |
| US7977797B2 CLAIM 13 . An integrated circuit of claim 11 further comprising a floating gate (layer insulation film, drain region) . |
US5994762A CLAIM 1 . A semiconductor integrated circuit device in which an interlayer insulation film (floating gate) deposited on a semiconductor chip includes a first boron-containing silicon oxide film and a second film formed on the first boron-containing silicon oxide film , wherein a slit is disposed along the periphery of the semiconductor chip at a depth to extend at least into said second film , wherein the concentration of boron in the first boron-containing silicon oxide film is not less than 10 mol % . US5994762A CLAIM 3 . A semiconductor integrated circuit device comprising : a semiconductor substrate having a first region which is a peripheral portion of a main surface and a second region inside of the first region in said main surface , a plurality of MISFETs each formed in the second region and each having a source region , a drain region (floating gate) and a gate electrode , a boron containing silicon oxide film formed in the first region and the second region , and having a first connection opening in the first region for exposing a semiconductor region formed on the main surface of the semiconductor substrate and a second connection opening in the second region for exposing the source region or the drain region of at least one of the plurality of MISFETs , a first conductor layer formed in the first region , in the first connection opening and on the boron-containing silicon oxide film , a second conductor layer formed in the second connection opening and on the boron-containing silicon oxide film in the second region , a silicon oxide film not containing boron formed above the first and the second conductor layers , wherein at least a portion of the silicon oxide film not containing boron is in contact with the boron-containing silicon oxide film , wherein the first conductor layer is disposed continuously along the periphery of the main surface , and a groove penetrating a boundary between the boron-containing silicon oxide film and the silicon oxide film not containing boron is formed between the first conductor layer in the first region and the periphery of the main surface to prevent the spread of cracks caused by poor adhesion between the boron-containing silicon oxide film and the silicon oxide film not containing boron . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US5994762A CLAIM 24 . A method of manufacturing a semiconductor integrated circuit device on a semiconductor wafer at a device forming area which is surrounded by a scribe line comprising the steps of : forming a first insulation film over a main surface of the semiconductor wafer ; forming a second insulation film over the first insulation film ; forming a third insulation film over the main surface of the semiconductor wafer ; forming a fourth insulation film over the third insulation film ; forming a first conductor layer over the main surface of the semiconductor wafer ; forming a fifth insulation film of a silicon nitride film over the first conductor layer ; forming an aperture in the fifth insulation film to reveal the first conductor layer in order to form a bonding pad , and forming (anti reflective coating) a slit at a periphery of the device forming area in the fifth insulation film ; and dicing the semiconductor wafer on the scribe line to provide a chip ; wherein the adhesion at a first boundary between the first insulation film and the second insulation film is lower than the adhesion at a second boundary between the third insulation film and the fourth insulation film , and the slit is located between the bonding pad and the scribe line on the chip to prevent the spread of cracks caused by the lower adhesion between the first insulation film and the second insulation film . |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region (first boundary) is a first range of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5994762A CLAIM 24 . A method of manufacturing a semiconductor integrated circuit device on a semiconductor wafer at a device forming area which is surrounded by a scribe line comprising the steps of : forming a first insulation film over a main surface of the semiconductor wafer ; forming a second insulation film over the first insulation film ; forming a third insulation film over the main surface of the semiconductor wafer ; forming a fourth insulation film over the third insulation film ; forming a first conductor layer over the main surface of the semiconductor wafer ; forming a fifth insulation film of a silicon nitride film over the first conductor layer ; forming an aperture in the fifth insulation film to reveal the first conductor layer in order to form a bonding pad , and forming a slit at a periphery of the device forming area in the fifth insulation film ; and dicing the semiconductor wafer on the scribe line to provide a chip ; wherein the adhesion at a first boundary (contact region, spacer region) between the first insulation film and the second insulation film is lower than the adhesion at a second boundary between the third insulation film and the fourth insulation film , and the slit is located between the bonding pad and the scribe line on the chip to prevent the spread of cracks caused by the lower adhesion between the first insulation film and the second insulation film . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5668052A Filed: 1996-07-05 Issued: 1997-09-16 Method of manufacturing semiconductor device (Original Assignee) Mitsubishi Electric Corp (Current Assignee) Renesas Electronics Corp Junko Matsumoto, Shigenori Sakamori |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (insulating film, contact hole) layer (entire surface) over said first etch stop layer ; a second etch stop layer (insulating film, contact hole) over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5668052A CLAIM 1 . A method of manufacturing a semiconductor device comprising the steps of : forming a wiring on one major surface of a semiconductor substrate ; forming an insulating film (second etch stop layer, second interlevel dielectric layer, interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer) covering the upper and side surfaces of said wiring ; forming an etching stopper film on the entire surface (first sub interlevel dielectric layer) of said semiconductor substrate ; forming an insulating interlayer on said etching stopper film ; forming a reflection prevention film on said insulating interlayer ; forming a resist pattern having a pattern having the same shape as that of a contact hole (second etch stop layer, second interlevel dielectric layer, interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer) on said reflection prevention film ; removing said reflection prevention film and said insulating interlayer located on a contact formation region by using said resist pattern as an etching mask ; removing said resist pattern and simultaneously removing said reflection prevention film and said etching stopper film on the contact formation region by etching to form a contact hole ; and exposing one major surface of said semiconductor substrate of the contact hole formation region and burying a conductive material in said contact hole to form a contact . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (insulating film, contact hole) layer (entire surface) insulates said contact region . |
US5668052A CLAIM 1 . A method of manufacturing a semiconductor device comprising the steps of : forming a wiring on one major surface of a semiconductor substrate ; forming an insulating film (second etch stop layer, second interlevel dielectric layer, interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer) covering the upper and side surfaces of said wiring ; forming an etching stopper film on the entire surface (first sub interlevel dielectric layer) of said semiconductor substrate ; forming an insulating interlayer on said etching stopper film ; forming a reflection prevention film on said insulating interlayer ; forming a resist pattern having a pattern having the same shape as that of a contact hole (second etch stop layer, second interlevel dielectric layer, interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer) on said reflection prevention film ; removing said reflection prevention film and said insulating interlayer located on a contact formation region by using said resist pattern as an etching mask ; removing said resist pattern and simultaneously removing said reflection prevention film and said etching stopper film on the contact formation region by etching to form a contact hole ; and exposing one major surface of said semiconductor substrate of the contact hole formation region and burying a conductive material in said contact hole to form a contact . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch stop layer (insulating film, contact hole) protects lower layers during an etching process (film thickness) . |
US5668052A CLAIM 1 . A method of manufacturing a semiconductor device comprising the steps of : forming a wiring on one major surface of a semiconductor substrate ; forming an insulating film (second etch stop layer, second interlevel dielectric layer, interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer) covering the upper and side surfaces of said wiring ; forming an etching stopper film on the entire surface of said semiconductor substrate ; forming an insulating interlayer on said etching stopper film ; forming a reflection prevention film on said insulating interlayer ; forming a resist pattern having a pattern having the same shape as that of a contact hole (second etch stop layer, second interlevel dielectric layer, interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer) on said reflection prevention film ; removing said reflection prevention film and said insulating interlayer located on a contact formation region by using said resist pattern as an etching mask ; removing said resist pattern and simultaneously removing said reflection prevention film and said etching stopper film on the contact formation region by etching to form a contact hole ; and exposing one major surface of said semiconductor substrate of the contact hole formation region and burying a conductive material in said contact hole to form a contact . US5668052A CLAIM 3 . A method of manufacturing a semiconductor device according to claim 2 , wherein said etching stopper film and said reflection prevention film have film thickness (etching process) es which are almost equal to each other . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (insulating film, contact hole) layer insulates said contact region . |
US5668052A CLAIM 1 . A method of manufacturing a semiconductor device comprising the steps of : forming a wiring on one major surface of a semiconductor substrate ; forming an insulating film (second etch stop layer, second interlevel dielectric layer, interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer) covering the upper and side surfaces of said wiring ; forming an etching stopper film on the entire surface of said semiconductor substrate ; forming an insulating interlayer on said etching stopper film ; forming a reflection prevention film on said insulating interlayer ; forming a resist pattern having a pattern having the same shape as that of a contact hole (second etch stop layer, second interlevel dielectric layer, interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer) on said reflection prevention film ; removing said reflection prevention film and said insulating interlayer located on a contact formation region by using said resist pattern as an etching mask ; removing said resist pattern and simultaneously removing said reflection prevention film and said etching stopper film on the contact formation region by etching to form a contact hole ; and exposing one major surface of said semiconductor substrate of the contact hole formation region and burying a conductive material in said contact hole to form a contact . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (insulating film, contact hole) layer (entire surface) is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer (insulating film, contact hole) is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5668052A CLAIM 1 . A method of manufacturing a semiconductor device comprising the steps of : forming a wiring on one major surface of a semiconductor substrate ; forming an insulating film (second etch stop layer, second interlevel dielectric layer, interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer) covering the upper and side surfaces of said wiring ; forming an etching stopper film on the entire surface (first sub interlevel dielectric layer) of said semiconductor substrate ; forming an insulating interlayer on said etching stopper film ; forming a reflection prevention film on said insulating interlayer ; forming a resist pattern having a pattern having the same shape as that of a contact hole (second etch stop layer, second interlevel dielectric layer, interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer) on said reflection prevention film ; removing said reflection prevention film and said insulating interlayer located on a contact formation region by using said resist pattern as an etching mask ; removing said resist pattern and simultaneously removing said reflection prevention film and said etching stopper film on the contact formation region by etching to form a contact hole ; and exposing one major surface of said semiconductor substrate of the contact hole formation region and burying a conductive material in said contact hole to form a contact . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric (insulating film, contact hole) layer (entire surface) for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5668052A CLAIM 1 . A method of manufacturing a semiconductor device comprising the steps of : forming a wiring on one major surface of a semiconductor substrate ; forming an insulating film (second etch stop layer, second interlevel dielectric layer, interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer) covering the upper and side surfaces of said wiring ; forming an etching stopper film on the entire surface (first sub interlevel dielectric layer) of said semiconductor substrate ; forming an insulating interlayer on said etching stopper film ; forming a reflection prevention film on said insulating interlayer ; forming a resist pattern having a pattern having the same shape as that of a contact hole (second etch stop layer, second interlevel dielectric layer, interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer) on said reflection prevention film ; removing said reflection prevention film and said insulating interlayer located on a contact formation region by using said resist pattern as an etching mask ; removing said resist pattern and simultaneously removing said reflection prevention film and said etching stopper film on the contact formation region by etching to form a contact hole ; and exposing one major surface of said semiconductor substrate of the contact hole formation region and burying a conductive material in said contact hole to form a contact . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer (insulating film, contact hole) wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (insulating film, contact hole) layer (entire surface) and said second etch stop layer formed under a second interlevel dielectric layer (insulating film, contact hole) , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US5668052A CLAIM 1 . A method of manufacturing a semiconductor device comprising the steps of : forming a wiring on one major surface of a semiconductor substrate ; forming an insulating film (second etch stop layer, second interlevel dielectric layer, interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer) covering the upper and side surfaces of said wiring ; forming an etching stopper film on the entire surface (first sub interlevel dielectric layer) of said semiconductor substrate ; forming an insulating interlayer on said etching stopper film ; forming a reflection prevention film on said insulating interlayer ; forming a resist pattern having a pattern having the same shape as that of a contact hole (second etch stop layer, second interlevel dielectric layer, interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer) on said reflection prevention film ; removing said reflection prevention film and said insulating interlayer located on a contact formation region by using said resist pattern as an etching mask ; removing said resist pattern and simultaneously removing said reflection prevention film and said etching stopper film on the contact formation region by etching to form a contact hole ; and exposing one major surface of said semiconductor substrate of the contact hole formation region and burying a conductive material in said contact hole to form a contact . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (insulating film, contact hole) layer (entire surface) is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer (insulating film, contact hole) is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5668052A CLAIM 1 . A method of manufacturing a semiconductor device comprising the steps of : forming a wiring on one major surface of a semiconductor substrate ; forming an insulating film (second etch stop layer, second interlevel dielectric layer, interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer) covering the upper and side surfaces of said wiring ; forming an etching stopper film on the entire surface (first sub interlevel dielectric layer) of said semiconductor substrate ; forming an insulating interlayer on said etching stopper film ; forming a reflection prevention film on said insulating interlayer ; forming a resist pattern having a pattern having the same shape as that of a contact hole (second etch stop layer, second interlevel dielectric layer, interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer) on said reflection prevention film ; removing said reflection prevention film and said insulating interlayer located on a contact formation region by using said resist pattern as an etching mask ; removing said resist pattern and simultaneously removing said reflection prevention film and said etching stopper film on the contact formation region by etching to form a contact hole ; and exposing one major surface of said semiconductor substrate of the contact hole formation region and burying a conductive material in said contact hole to form a contact . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5719089A Filed: 1996-06-21 Issued: 1998-02-17 Method for etching polymer-assisted reduced small contacts for ultra large scale integration semiconductor devices (Original Assignee) Vanguard International Semiconductor Corp (Current Assignee) Vanguard International Semiconductor Corp Meng-Jaw Cherng, Pei-Wen Li |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region (semiconductor substrates) such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch (remaining portions) stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (vertical sidewalls) layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5719089A CLAIM 1 . A method for fabricating electrical contact openings on semiconductor substrates (spacer region) for integrated circuits , comprising the steps of : providing a semiconductor substrate having device contact areas in and on the surface of said substrate ; depositing an insulating layer on said substrate ; depositing a polysilicon layer on said insulating layer ; forming a photoresist layer on said polysilicon layer ; forming openings in said photoresist layer to said polysilicon layer over said device contact areas on said substrate ; using a first anisotropic plasma etch to etch said polysilicon layer to said insulating layer in said photoresist openings , and thereby forming openings having vertical sidewalls (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) in said polysilicon layer ; performing a second anisotropic plasma etch to etch said insulating layer exposed in said polysilicon openings using an etchant gas mixture that concurrently deposits a polymer layer forming polymer sidewall spacers on said polysilicon layer sidewalls , thereby forming contact openings in said insulating layer to said substrate surface having reduced sizes , said contact openings being less in size than said openings in said photoresist layer ; removing concurrently said polymer sidewall spacers and remaining portions (first etch) of said photoresist layer by plasma ashing in oxygen , and thereby completing said electrical contact openings on said substrate . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch (remaining portions) stop layer protects removal of a substrate material by an etch process . |
US5719089A CLAIM 1 . A method for fabricating electrical contact openings on semiconductor substrates for integrated circuits , comprising the steps of : providing a semiconductor substrate having device contact areas in and on the surface of said substrate ; depositing an insulating layer on said substrate ; depositing a polysilicon layer on said insulating layer ; forming a photoresist layer on said polysilicon layer ; forming openings in said photoresist layer to said polysilicon layer over said device contact areas on said substrate ; using a first anisotropic plasma etch to etch said polysilicon layer to said insulating layer in said photoresist openings , and thereby forming openings having vertical sidewalls in said polysilicon layer ; performing a second anisotropic plasma etch to etch said insulating layer exposed in said polysilicon openings using an etchant gas mixture that concurrently deposits a polymer layer forming polymer sidewall spacers on said polysilicon layer sidewalls , thereby forming contact openings in said insulating layer to said substrate surface having reduced sizes , said contact openings being less in size than said openings in said photoresist layer ; removing concurrently said polymer sidewall spacers and remaining portions (first etch) of said photoresist layer by plasma ashing in oxygen , and thereby completing said electrical contact openings on said substrate . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (vertical sidewalls) layer insulates said contact region . |
US5719089A CLAIM 1 . A method for fabricating electrical contact openings on semiconductor substrates for integrated circuits , comprising the steps of : providing a semiconductor substrate having device contact areas in and on the surface of said substrate ; depositing an insulating layer on said substrate ; depositing a polysilicon layer on said insulating layer ; forming a photoresist layer on said polysilicon layer ; forming openings in said photoresist layer to said polysilicon layer over said device contact areas on said substrate ; using a first anisotropic plasma etch to etch said polysilicon layer to said insulating layer in said photoresist openings , and thereby forming openings having vertical sidewalls (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) in said polysilicon layer ; performing a second anisotropic plasma etch to etch said insulating layer exposed in said polysilicon openings using an etchant gas mixture that concurrently deposits a polymer layer forming polymer sidewall spacers on said polysilicon layer sidewalls , thereby forming contact openings in said insulating layer to said substrate surface having reduced sizes , said contact openings being less in size than said openings in said photoresist layer ; removing concurrently said polymer sidewall spacers and remaining portions of said photoresist layer by plasma ashing in oxygen , and thereby completing said electrical contact openings on said substrate . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (vertical sidewalls) layer insulates said contact region . |
US5719089A CLAIM 1 . A method for fabricating electrical contact openings on semiconductor substrates for integrated circuits , comprising the steps of : providing a semiconductor substrate having device contact areas in and on the surface of said substrate ; depositing an insulating layer on said substrate ; depositing a polysilicon layer on said insulating layer ; forming a photoresist layer on said polysilicon layer ; forming openings in said photoresist layer to said polysilicon layer over said device contact areas on said substrate ; using a first anisotropic plasma etch to etch said polysilicon layer to said insulating layer in said photoresist openings , and thereby forming openings having vertical sidewalls (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) in said polysilicon layer ; performing a second anisotropic plasma etch to etch said insulating layer exposed in said polysilicon openings using an etchant gas mixture that concurrently deposits a polymer layer forming polymer sidewall spacers on said polysilicon layer sidewalls , thereby forming contact openings in said insulating layer to said substrate surface having reduced sizes , said contact openings being less in size than said openings in said photoresist layer ; removing concurrently said polymer sidewall spacers and remaining portions of said photoresist layer by plasma ashing in oxygen , and thereby completing said electrical contact openings on said substrate . |
| US7977797B2 CLAIM 6 . An integrated circuit of claim 1 wherein said spacer region (semiconductor substrates) insulates said contact region . |
US5719089A CLAIM 1 . A method for fabricating electrical contact openings on semiconductor substrates (spacer region) for integrated circuits , comprising the steps of : providing a semiconductor substrate having device contact areas in and on the surface of said substrate ; depositing an insulating layer on said substrate ; depositing a polysilicon layer on said insulating layer ; forming a photoresist layer on said polysilicon layer ; forming openings in said photoresist layer to said polysilicon layer over said device contact areas on said substrate ; using a first anisotropic plasma etch to etch said polysilicon layer to said insulating layer in said photoresist openings , and thereby forming openings having vertical sidewalls in said polysilicon layer ; performing a second anisotropic plasma etch to etch said insulating layer exposed in said polysilicon openings using an etchant gas mixture that concurrently deposits a polymer layer forming polymer sidewall spacers on said polysilicon layer sidewalls , thereby forming contact openings in said insulating layer to said substrate surface having reduced sizes , said contact openings being less in size than said openings in said photoresist layer ; removing concurrently said polymer sidewall spacers and remaining portions of said photoresist layer by plasma ashing in oxygen , and thereby completing said electrical contact openings on said substrate . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch (remaining portions) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (vertical sidewalls) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5719089A CLAIM 1 . A method for fabricating electrical contact openings on semiconductor substrates for integrated circuits , comprising the steps of : providing a semiconductor substrate having device contact areas in and on the surface of said substrate ; depositing an insulating layer on said substrate ; depositing a polysilicon layer on said insulating layer ; forming a photoresist layer on said polysilicon layer ; forming openings in said photoresist layer to said polysilicon layer over said device contact areas on said substrate ; using a first anisotropic plasma etch to etch said polysilicon layer to said insulating layer in said photoresist openings , and thereby forming openings having vertical sidewalls (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) in said polysilicon layer ; performing a second anisotropic plasma etch to etch said insulating layer exposed in said polysilicon openings using an etchant gas mixture that concurrently deposits a polymer layer forming polymer sidewall spacers on said polysilicon layer sidewalls , thereby forming contact openings in said insulating layer to said substrate surface having reduced sizes , said contact openings being less in size than said openings in said photoresist layer ; removing concurrently said polymer sidewall spacers and remaining portions (first etch) of said photoresist layer by plasma ashing in oxygen , and thereby completing said electrical contact openings on said substrate . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric (vertical sidewalls) layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5719089A CLAIM 1 . A method for fabricating electrical contact openings on semiconductor substrates for integrated circuits , comprising the steps of : providing a semiconductor substrate having device contact areas in and on the surface of said substrate ; depositing an insulating layer on said substrate ; depositing a polysilicon layer on said insulating layer ; forming a photoresist layer on said polysilicon layer ; forming openings in said photoresist layer to said polysilicon layer over said device contact areas on said substrate ; using a first anisotropic plasma etch to etch said polysilicon layer to said insulating layer in said photoresist openings , and thereby forming openings having vertical sidewalls (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) in said polysilicon layer ; performing a second anisotropic plasma etch to etch said insulating layer exposed in said polysilicon openings using an etchant gas mixture that concurrently deposits a polymer layer forming polymer sidewall spacers on said polysilicon layer sidewalls , thereby forming contact openings in said insulating layer to said substrate surface having reduced sizes , said contact openings being less in size than said openings in said photoresist layer ; removing concurrently said polymer sidewall spacers and remaining portions of said photoresist layer by plasma ashing in oxygen , and thereby completing said electrical contact openings on said substrate . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch (remaining portions) stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (vertical sidewalls) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US5719089A CLAIM 1 . A method for fabricating electrical contact openings on semiconductor substrates for integrated circuits , comprising the steps of : providing a semiconductor substrate having device contact areas in and on the surface of said substrate ; depositing an insulating layer on said substrate ; depositing a polysilicon layer on said insulating layer ; forming a photoresist layer on said polysilicon layer ; forming openings in said photoresist layer to said polysilicon layer over said device contact areas on said substrate ; using a first anisotropic plasma etch to etch said polysilicon layer to said insulating layer in said photoresist openings , and thereby forming openings having vertical sidewalls (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) in said polysilicon layer ; performing a second anisotropic plasma etch to etch said insulating layer exposed in said polysilicon openings using an etchant gas mixture that concurrently deposits a polymer layer forming polymer sidewall spacers on said polysilicon layer sidewalls , thereby forming contact openings in said insulating layer to said substrate surface having reduced sizes , said contact openings being less in size than said openings in said photoresist layer ; removing concurrently said polymer sidewall spacers and remaining portions (first etch) of said photoresist layer by plasma ashing in oxygen , and thereby completing said electrical contact openings on said substrate . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch (remaining portions) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (vertical sidewalls) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5719089A CLAIM 1 . A method for fabricating electrical contact openings on semiconductor substrates for integrated circuits , comprising the steps of : providing a semiconductor substrate having device contact areas in and on the surface of said substrate ; depositing an insulating layer on said substrate ; depositing a polysilicon layer on said insulating layer ; forming a photoresist layer on said polysilicon layer ; forming openings in said photoresist layer to said polysilicon layer over said device contact areas on said substrate ; using a first anisotropic plasma etch to etch said polysilicon layer to said insulating layer in said photoresist openings , and thereby forming openings having vertical sidewalls (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) in said polysilicon layer ; performing a second anisotropic plasma etch to etch said insulating layer exposed in said polysilicon openings using an etchant gas mixture that concurrently deposits a polymer layer forming polymer sidewall spacers on said polysilicon layer sidewalls , thereby forming contact openings in said insulating layer to said substrate surface having reduced sizes , said contact openings being less in size than said openings in said photoresist layer ; removing concurrently said polymer sidewall spacers and remaining portions (first etch) of said photoresist layer by plasma ashing in oxygen , and thereby completing said electrical contact openings on said substrate . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5656520A Filed: 1996-05-22 Issued: 1997-08-12 Semiconductor device and method of manufacturing the same (Original Assignee) NEC Corp (Current Assignee) NEC Electronics Corp Takeshi Watanabe |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer (insulating film) over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5656520A CLAIM 1 . A method of manufacturing a semiconductor device , comprising : the steps of sequentially forming a gate insulating film (second etch stop layer, second interlevel dielectric layer) , a gate electrode , and a stopper film in an element region on a semiconductor substrate ; forming an insulating interlayer on said semiconductor substrate , and etching and removing said insulating interlayer in the element region ; doping an impurity into said semiconductor substrate surrounded by said gate electrode and said insulating interlayer , and forming lightly doped diffusion layers ; forming a sidewall spacer on sidewalls of said gate electrode and said insulating interlayer ; doping an impurity into said semiconductor substrate surrounded by said sidewall spacer , and forming heavily doped diffusion layers ; and forming an electrode wiring on said semiconductor device surrounded by said sidewall spacer ; and also comprising the step of removing said stopper film by etching at the same time as said insulating interlayer is etched and removed . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer protects removal of a substrate material by an etch process (ion implantation) . |
US5656520A CLAIM 3 . A method according to claim 2 , wherein annealing is performed at 900° C . so as to activate said diffusion layers after ion implantation (etch process) . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch stop layer (insulating film) protects lower layers during an etching process . |
US5656520A CLAIM 1 . A method of manufacturing a semiconductor device , comprising : the steps of sequentially forming a gate insulating film (second etch stop layer, second interlevel dielectric layer) , a gate electrode , and a stopper film in an element region on a semiconductor substrate ; forming an insulating interlayer on said semiconductor substrate , and etching and removing said insulating interlayer in the element region ; doping an impurity into said semiconductor substrate surrounded by said gate electrode and said insulating interlayer , and forming lightly doped diffusion layers ; forming a sidewall spacer on sidewalls of said gate electrode and said insulating interlayer ; doping an impurity into said semiconductor substrate surrounded by said sidewall spacer , and forming heavily doped diffusion layers ; and forming an electrode wiring on said semiconductor device surrounded by said sidewall spacer ; and also comprising the step of removing said stopper film by etching at the same time as said insulating interlayer is etched and removed . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer (insulating film) is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5656520A CLAIM 1 . A method of manufacturing a semiconductor device , comprising : the steps of sequentially forming a gate insulating film (second etch stop layer, second interlevel dielectric layer) , a gate electrode , and a stopper film in an element region on a semiconductor substrate ; forming an insulating interlayer on said semiconductor substrate , and etching and removing said insulating interlayer in the element region ; doping an impurity into said semiconductor substrate surrounded by said gate electrode and said insulating interlayer , and forming lightly doped diffusion layers ; forming a sidewall spacer on sidewalls of said gate electrode and said insulating interlayer ; doping an impurity into said semiconductor substrate surrounded by said sidewall spacer , and forming heavily doped diffusion layers ; and forming an electrode wiring on said semiconductor device surrounded by said sidewall spacer ; and also comprising the step of removing said stopper film by etching at the same time as said insulating interlayer is etched and removed . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US5656520A CLAIM 1 . A method of manufacturing a semiconductor device , comprising : the steps of sequentially forming a gate insulating film , a gate electrode , and a stopper film in an element region on a semiconductor substrate ; forming an insulating interlayer on said semiconductor substrate , and etching and removing said insulating interlayer in the element region ; doping an impurity into said semiconductor substrate surrounded by said gate electrode and said insulating interlayer , and forming (anti reflective coating) lightly doped diffusion layers ; forming a sidewall spacer on sidewalls of said gate electrode and said insulating interlayer ; doping an impurity into said semiconductor substrate surrounded by said sidewall spacer , and forming heavily doped diffusion layers ; and forming an electrode wiring on said semiconductor device surrounded by said sidewall spacer ; and also comprising the step of removing said stopper film by etching at the same time as said insulating interlayer is etched and removed . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer (insulating film) wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer (insulating film) , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US5656520A CLAIM 1 . A method of manufacturing a semiconductor device , comprising : the steps of sequentially forming a gate insulating film (second etch stop layer, second interlevel dielectric layer) , a gate electrode , and a stopper film in an element region on a semiconductor substrate ; forming an insulating interlayer on said semiconductor substrate , and etching and removing said insulating interlayer in the element region ; doping an impurity into said semiconductor substrate surrounded by said gate electrode and said insulating interlayer , and forming lightly doped diffusion layers ; forming a sidewall spacer on sidewalls of said gate electrode and said insulating interlayer ; doping an impurity into said semiconductor substrate surrounded by said sidewall spacer , and forming heavily doped diffusion layers ; and forming an electrode wiring on said semiconductor device surrounded by said sidewall spacer ; and also comprising the step of removing said stopper film by etching at the same time as said insulating interlayer is etched and removed . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer (insulating film) is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5656520A CLAIM 1 . A method of manufacturing a semiconductor device , comprising : the steps of sequentially forming a gate insulating film (second etch stop layer, second interlevel dielectric layer) , a gate electrode , and a stopper film in an element region on a semiconductor substrate ; forming an insulating interlayer on said semiconductor substrate , and etching and removing said insulating interlayer in the element region ; doping an impurity into said semiconductor substrate surrounded by said gate electrode and said insulating interlayer , and forming lightly doped diffusion layers ; forming a sidewall spacer on sidewalls of said gate electrode and said insulating interlayer ; doping an impurity into said semiconductor substrate surrounded by said sidewall spacer , and forming heavily doped diffusion layers ; and forming an electrode wiring on said semiconductor device surrounded by said sidewall spacer ; and also comprising the step of removing said stopper film by etching at the same time as said insulating interlayer is etched and removed . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US5656520A CLAIM 1 . A method of manufacturing a semiconductor device , comprising : the steps of sequentially forming a gate insulating film , a gate electrode , and a stopper film in an element region on a semiconductor substrate ; forming an insulating interlayer on said semiconductor substrate , and etching and removing said insulating interlayer in the element region ; doping an impurity into said semiconductor substrate surrounded by said gate electrode and said insulating interlayer , and forming (anti reflective coating) lightly doped diffusion layers ; forming a sidewall spacer on sidewalls of said gate electrode and said insulating interlayer ; doping an impurity into said semiconductor substrate surrounded by said sidewall spacer , and forming heavily doped diffusion layers ; and forming an electrode wiring on said semiconductor device surrounded by said sidewall spacer ; and also comprising the step of removing said stopper film by etching at the same time as said insulating interlayer is etched and removed . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5741735A Filed: 1996-05-20 Issued: 1998-04-21 Local ground and VCC connection in an SRAM cell (Original Assignee) Micron Technology Inc (Current Assignee) Micron Technology Inc Michael P. Violette, Fernando Gonzalez |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch (ion energy) stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5741735A CLAIM 2 . The method described in claim 1 , wherein formation of said first retrograde well region includes the steps of : implanting first dopant particles in the substrate with high implantation energy (first etch, first etch stop layer, etch process) ; implanting second dopant particles in the substrate with low implantation energy ; and diffusing said first and second dopant particles into the substrate . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch (ion energy) stop layer protects removal of a substrate material by an etch process (ion energy) . |
US5741735A CLAIM 2 . The method described in claim 1 , wherein formation of said first retrograde well region includes the steps of : implanting first dopant particles in the substrate with high implantation energy (first etch, first etch stop layer, etch process) ; implanting second dopant particles in the substrate with low implantation energy ; and diffusing said first and second dopant particles into the substrate . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch (ion energy) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5741735A CLAIM 2 . The method described in claim 1 , wherein formation of said first retrograde well region includes the steps of : implanting first dopant particles in the substrate with high implantation energy (first etch, first etch stop layer, etch process) ; implanting second dopant particles in the substrate with low implantation energy ; and diffusing said first and second dopant particles into the substrate . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric layer for said contact region is in a first range (surface region) of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5741735A CLAIM 1 . A method for constructing a memory device in a semiconductor substrate , comprising the steps of : forming a first retrograde well region of a first conductivity type in the substrate , said first retrograde well including a first upper region of low conductivity and a first lower region of high conductivity ; forming a second retrograde well region of a second conductivity type in the substrate , said second retrograde well including a second upper region of low conductivity and a second lower region of high conductivity ; forming first and second isolated active area surface region (first range) s in the first and second upper regions of the first and second wells , all respectively ; forming an insulating layer on said active area surface regions ; forming a first conducting layer on said insulating layer ; forming a covering layer on said first conducting layer ; selectively etching away portions of said covering layer , underlying portions of said first conducting layer and underlying portions of said insulating layer , leaving exposed portions of said active area surface regions ; forming lightly doped drain and source extensions in the exposed portions of said first active area surface region ; forming first insulating sidewall spacers on remaining portions of said covering layer , underlying remaining portions of said first conducting layer and underlying remaining portions of said insulating layer ; selectively etching away portions of said covering layer , leaving exposed portions of said first conducting layer ; forming heavily doped drain and source regions in said first active area surface region ; selectively etching away portions of said first and second active area surface regions and underlying portions of the first and second upper regions of said first and second wells , leaving exposed portions of the first and second lower regions , all respectively ; forming doped drain and source regions in said second active area surface region ; forming a second conducting layer ; selectively etching away said second conducting layer , leaving first and second remaining portions , said first remaining portions selectively electrically connecting drain and source regions to the exposed portions of said first conducting layer , and said second remaining portions respectively selectively electrically connecting said first and second active area surface portions to the exposed portions of the first and second lower well regions ; and connecting the first and second lower regions of said first and second wells to first and second electric potential supplies . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US5741735A CLAIM 5 . A method of forming an integrated circuit in a semiconductor substrate comprising the steps of : forming a lower region of a first conductivity type in the semiconductor substrate ; forming an upper region of the first conductivity type in the semiconductor substrate , the upper region having a lesser conductivity than the lower region ; forming an active region in the upper region ; forming a first switching device in the active region ; removing a portion of the active region and underlying portion of the upper region , leaving exposed a portion of the lower forming a conducting layer electrically connecting a portion of the active region ; to the exposed portion of the lower region ; and forming (anti reflective coating) a second switching device in the active region , the second switching device having a switch input/output terminal region in common with the first switching device , and wherein the common switch input/output terminal region is formed in the portion of the active region electrically connected to the exposed portion of the lower region . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch (ion energy) stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers (second remaining portions, first sidewall spacer) have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US5741735A CLAIM 1 . A method for constructing a memory device in a semiconductor substrate , comprising the steps of : forming a first retrograde well region of a first conductivity type in the substrate , said first retrograde well including a first upper region of low conductivity and a first lower region of high conductivity ; forming a second retrograde well region of a second conductivity type in the substrate , said second retrograde well including a second upper region of low conductivity and a second lower region of high conductivity ; forming first and second isolated active area surface regions in the first and second upper regions of the first and second wells , all respectively ; forming an insulating layer on said active area surface regions ; forming a first conducting layer on said insulating layer ; forming a covering layer on said first conducting layer ; selectively etching away portions of said covering layer , underlying portions of said first conducting layer and underlying portions of said insulating layer , leaving exposed portions of said active area surface regions ; forming lightly doped drain and source extensions in the exposed portions of said first active area surface region ; forming first insulating sidewall spacers on remaining portions of said covering layer , underlying remaining portions of said first conducting layer and underlying remaining portions of said insulating layer ; selectively etching away portions of said covering layer , leaving exposed portions of said first conducting layer ; forming heavily doped drain and source regions in said first active area surface region ; selectively etching away portions of said first and second active area surface regions and underlying portions of the first and second upper regions of said first and second wells , leaving exposed portions of the first and second lower regions , all respectively ; forming doped drain and source regions in said second active area surface region ; forming a second conducting layer ; selectively etching away said second conducting layer , leaving first and second remaining portions (second etch stop layers, floating gate) , said first remaining portions selectively electrically connecting drain and source regions to the exposed portions of said first conducting layer , and said second remaining portions respectively selectively electrically connecting said first and second active area surface portions to the exposed portions of the first and second lower well regions ; and connecting the first and second lower regions of said first and second wells to first and second electric potential supplies . US5741735A CLAIM 2 . The method described in claim 1 , wherein formation of said first retrograde well region includes the steps of : implanting first dopant particles in the substrate with high implantation energy (first etch, first etch stop layer, etch process) ; implanting second dopant particles in the substrate with low implantation energy ; and diffusing said first and second dopant particles into the substrate . US5741735A CLAIM 4 . The method described in claim 1 , further comprising the step of forming second insulating sidewall spacers on selected first sidewall spacer (second etch stop layers, floating gate) s adjacent to those portions of said first and second active area surface regions subsequently selectively etched away . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch (ion energy) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5741735A CLAIM 2 . The method described in claim 1 , wherein formation of said first retrograde well region includes the steps of : implanting first dopant particles in the substrate with high implantation energy (first etch, first etch stop layer, etch process) ; implanting second dopant particles in the substrate with low implantation energy ; and diffusing said first and second dopant particles into the substrate . |
| US7977797B2 CLAIM 13 . An integrated circuit of claim 11 further comprising a floating gate (second remaining portions, first sidewall spacer) . |
US5741735A CLAIM 1 . A method for constructing a memory device in a semiconductor substrate , comprising the steps of : forming a first retrograde well region of a first conductivity type in the substrate , said first retrograde well including a first upper region of low conductivity and a first lower region of high conductivity ; forming a second retrograde well region of a second conductivity type in the substrate , said second retrograde well including a second upper region of low conductivity and a second lower region of high conductivity ; forming first and second isolated active area surface regions in the first and second upper regions of the first and second wells , all respectively ; forming an insulating layer on said active area surface regions ; forming a first conducting layer on said insulating layer ; forming a covering layer on said first conducting layer ; selectively etching away portions of said covering layer , underlying portions of said first conducting layer and underlying portions of said insulating layer , leaving exposed portions of said active area surface regions ; forming lightly doped drain and source extensions in the exposed portions of said first active area surface region ; forming first insulating sidewall spacers on remaining portions of said covering layer , underlying remaining portions of said first conducting layer and underlying remaining portions of said insulating layer ; selectively etching away portions of said covering layer , leaving exposed portions of said first conducting layer ; forming heavily doped drain and source regions in said first active area surface region ; selectively etching away portions of said first and second active area surface regions and underlying portions of the first and second upper regions of said first and second wells , leaving exposed portions of the first and second lower regions , all respectively ; forming doped drain and source regions in said second active area surface region ; forming a second conducting layer ; selectively etching away said second conducting layer , leaving first and second remaining portions (second etch stop layers, floating gate) , said first remaining portions selectively electrically connecting drain and source regions to the exposed portions of said first conducting layer , and said second remaining portions respectively selectively electrically connecting said first and second active area surface portions to the exposed portions of the first and second lower well regions ; and connecting the first and second lower regions of said first and second wells to first and second electric potential supplies . US5741735A CLAIM 4 . The method described in claim 1 , further comprising the step of forming second insulating sidewall spacers on selected first sidewall spacer (second etch stop layers, floating gate) s adjacent to those portions of said first and second active area surface regions subsequently selectively etched away . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US5741735A CLAIM 5 . A method of forming an integrated circuit in a semiconductor substrate comprising the steps of : forming a lower region of a first conductivity type in the semiconductor substrate ; forming an upper region of the first conductivity type in the semiconductor substrate , the upper region having a lesser conductivity than the lower region ; forming an active region in the upper region ; forming a first switching device in the active region ; removing a portion of the active region and underlying portion of the upper region , leaving exposed a portion of the lower forming a conducting layer electrically connecting a portion of the active region ; to the exposed portion of the lower region ; and forming (anti reflective coating) a second switching device in the active region , the second switching device having a switch input/output terminal region in common with the first switching device , and wherein the common switch input/output terminal region is formed in the portion of the active region electrically connected to the exposed portion of the lower region . |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region is a first range (surface region) of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5741735A CLAIM 1 . A method for constructing a memory device in a semiconductor substrate , comprising the steps of : forming a first retrograde well region of a first conductivity type in the substrate , said first retrograde well including a first upper region of low conductivity and a first lower region of high conductivity ; forming a second retrograde well region of a second conductivity type in the substrate , said second retrograde well including a second upper region of low conductivity and a second lower region of high conductivity ; forming first and second isolated active area surface region (first range) s in the first and second upper regions of the first and second wells , all respectively ; forming an insulating layer on said active area surface regions ; forming a first conducting layer on said insulating layer ; forming a covering layer on said first conducting layer ; selectively etching away portions of said covering layer , underlying portions of said first conducting layer and underlying portions of said insulating layer , leaving exposed portions of said active area surface regions ; forming lightly doped drain and source extensions in the exposed portions of said first active area surface region ; forming first insulating sidewall spacers on remaining portions of said covering layer , underlying remaining portions of said first conducting layer and underlying remaining portions of said insulating layer ; selectively etching away portions of said covering layer , leaving exposed portions of said first conducting layer ; forming heavily doped drain and source regions in said first active area surface region ; selectively etching away portions of said first and second active area surface regions and underlying portions of the first and second upper regions of said first and second wells , leaving exposed portions of the first and second lower regions , all respectively ; forming doped drain and source regions in said second active area surface region ; forming a second conducting layer ; selectively etching away said second conducting layer , leaving first and second remaining portions , said first remaining portions selectively electrically connecting drain and source regions to the exposed portions of said first conducting layer , and said second remaining portions respectively selectively electrically connecting said first and second active area surface portions to the exposed portions of the first and second lower well regions ; and connecting the first and second lower regions of said first and second wells to first and second electric potential supplies . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5801916A Filed: 1996-05-17 Issued: 1998-09-01 Pre-patterned contact fill capacitor for dielectric etch protection (Original Assignee) Micron Technology Inc (Current Assignee) Micron Technology Inc Daryl C. New |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (silicon nitride layer, capacitor structure) layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5801916A CLAIM 6 . A capacitor structure (second etch stop layers, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) in an integrated circuit comprising a bottom electrode , a dielectric layer overlying and in direct contact with a top surface of the bottom electrode , and a top electrode overlying and in direct contact with an upper surface of the dielectric layer , an insulating diffusion barrier layer completely surrounding a sidewall of the bottom electrode and partially surrounding a sidewall of the dielectric layer , and the bottom electrode sidewall continuous with the dielectric layer sidewall , and the dielectric layer partially protruding above the insulating diffusion barrier layer . US5801916A CLAIM 15 . A contact fill capacitor formed in an integrated circuit comprising : a conductive bottom electrode ; a silicon nitride layer (second etch stop layers, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) having a contact via therethrough , the via at least partially filled with a dielectric material having a dielectric constant of at least 100 ; the dielectric material having an upper surface , a lower surface over and directly contacting the bottom electrode , and a sidewall connecting said upper and lower surfaces , at least a part of the sidewall surrounded by the silicon nitride layer ; and a conductive top electrode over and directly contacting the dielectric material over an area at least extensive with the upper surface of the dielectric material . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (silicon nitride layer, capacitor structure) layer insulates said contact region . |
US5801916A CLAIM 6 . A capacitor structure (second etch stop layers, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) in an integrated circuit comprising a bottom electrode , a dielectric layer overlying and in direct contact with a top surface of the bottom electrode , and a top electrode overlying and in direct contact with an upper surface of the dielectric layer , an insulating diffusion barrier layer completely surrounding a sidewall of the bottom electrode and partially surrounding a sidewall of the dielectric layer , and the bottom electrode sidewall continuous with the dielectric layer sidewall , and the dielectric layer partially protruding above the insulating diffusion barrier layer . US5801916A CLAIM 15 . A contact fill capacitor formed in an integrated circuit comprising : a conductive bottom electrode ; a silicon nitride layer (second etch stop layers, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) having a contact via therethrough , the via at least partially filled with a dielectric material having a dielectric constant of at least 100 ; the dielectric material having an upper surface , a lower surface over and directly contacting the bottom electrode , and a sidewall connecting said upper and lower surfaces , at least a part of the sidewall surrounded by the silicon nitride layer ; and a conductive top electrode over and directly contacting the dielectric material over an area at least extensive with the upper surface of the dielectric material . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch stop layer protects lower layers during an etching process (uniform thickness) . |
US5801916A CLAIM 19 . The capacitor of claim 15 , wherein the dielectric material comprises a layer of uniform thickness (etching process) . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (silicon nitride layer, capacitor structure) layer insulates said contact region . |
US5801916A CLAIM 6 . A capacitor structure (second etch stop layers, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) in an integrated circuit comprising a bottom electrode , a dielectric layer overlying and in direct contact with a top surface of the bottom electrode , and a top electrode overlying and in direct contact with an upper surface of the dielectric layer , an insulating diffusion barrier layer completely surrounding a sidewall of the bottom electrode and partially surrounding a sidewall of the dielectric layer , and the bottom electrode sidewall continuous with the dielectric layer sidewall , and the dielectric layer partially protruding above the insulating diffusion barrier layer . US5801916A CLAIM 15 . A contact fill capacitor formed in an integrated circuit comprising : a conductive bottom electrode ; a silicon nitride layer (second etch stop layers, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) having a contact via therethrough , the via at least partially filled with a dielectric material having a dielectric constant of at least 100 ; the dielectric material having an upper surface , a lower surface over and directly contacting the bottom electrode , and a sidewall connecting said upper and lower surfaces , at least a part of the sidewall surrounded by the silicon nitride layer ; and a conductive top electrode over and directly contacting the dielectric material over an area at least extensive with the upper surface of the dielectric material . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (silicon nitride layer, capacitor structure) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5801916A CLAIM 6 . A capacitor structure (second etch stop layers, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) in an integrated circuit comprising a bottom electrode , a dielectric layer overlying and in direct contact with a top surface of the bottom electrode , and a top electrode overlying and in direct contact with an upper surface of the dielectric layer , an insulating diffusion barrier layer completely surrounding a sidewall of the bottom electrode and partially surrounding a sidewall of the dielectric layer , and the bottom electrode sidewall continuous with the dielectric layer sidewall , and the dielectric layer partially protruding above the insulating diffusion barrier layer . US5801916A CLAIM 15 . A contact fill capacitor formed in an integrated circuit comprising : a conductive bottom electrode ; a silicon nitride layer (second etch stop layers, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) having a contact via therethrough , the via at least partially filled with a dielectric material having a dielectric constant of at least 100 ; the dielectric material having an upper surface , a lower surface over and directly contacting the bottom electrode , and a sidewall connecting said upper and lower surfaces , at least a part of the sidewall surrounded by the silicon nitride layer ; and a conductive top electrode over and directly contacting the dielectric material over an area at least extensive with the upper surface of the dielectric material . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric (silicon nitride layer, capacitor structure) layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5801916A CLAIM 6 . A capacitor structure (second etch stop layers, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) in an integrated circuit comprising a bottom electrode , a dielectric layer overlying and in direct contact with a top surface of the bottom electrode , and a top electrode overlying and in direct contact with an upper surface of the dielectric layer , an insulating diffusion barrier layer completely surrounding a sidewall of the bottom electrode and partially surrounding a sidewall of the dielectric layer , and the bottom electrode sidewall continuous with the dielectric layer sidewall , and the dielectric layer partially protruding above the insulating diffusion barrier layer . US5801916A CLAIM 15 . A contact fill capacitor formed in an integrated circuit comprising : a conductive bottom electrode ; a silicon nitride layer (second etch stop layers, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) having a contact via therethrough , the via at least partially filled with a dielectric material having a dielectric constant of at least 100 ; the dielectric material having an upper surface , a lower surface over and directly contacting the bottom electrode , and a sidewall connecting said upper and lower surfaces , at least a part of the sidewall surrounded by the silicon nitride layer ; and a conductive top electrode over and directly contacting the dielectric material over an area at least extensive with the upper surface of the dielectric material . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers (silicon nitride layer, capacitor structure) have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (silicon nitride layer, capacitor structure) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US5801916A CLAIM 6 . A capacitor structure (second etch stop layers, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) in an integrated circuit comprising a bottom electrode , a dielectric layer overlying and in direct contact with a top surface of the bottom electrode , and a top electrode overlying and in direct contact with an upper surface of the dielectric layer , an insulating diffusion barrier layer completely surrounding a sidewall of the bottom electrode and partially surrounding a sidewall of the dielectric layer , and the bottom electrode sidewall continuous with the dielectric layer sidewall , and the dielectric layer partially protruding above the insulating diffusion barrier layer . US5801916A CLAIM 15 . A contact fill capacitor formed in an integrated circuit comprising : a conductive bottom electrode ; a silicon nitride layer (second etch stop layers, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) having a contact via therethrough , the via at least partially filled with a dielectric material having a dielectric constant of at least 100 ; the dielectric material having an upper surface , a lower surface over and directly contacting the bottom electrode , and a sidewall connecting said upper and lower surfaces , at least a part of the sidewall surrounded by the silicon nitride layer ; and a conductive top electrode over and directly contacting the dielectric material over an area at least extensive with the upper surface of the dielectric material . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (silicon nitride layer, capacitor structure) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5801916A CLAIM 6 . A capacitor structure (second etch stop layers, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) in an integrated circuit comprising a bottom electrode , a dielectric layer overlying and in direct contact with a top surface of the bottom electrode , and a top electrode overlying and in direct contact with an upper surface of the dielectric layer , an insulating diffusion barrier layer completely surrounding a sidewall of the bottom electrode and partially surrounding a sidewall of the dielectric layer , and the bottom electrode sidewall continuous with the dielectric layer sidewall , and the dielectric layer partially protruding above the insulating diffusion barrier layer . US5801916A CLAIM 15 . A contact fill capacitor formed in an integrated circuit comprising : a conductive bottom electrode ; a silicon nitride layer (second etch stop layers, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) having a contact via therethrough , the via at least partially filled with a dielectric material having a dielectric constant of at least 100 ; the dielectric material having an upper surface , a lower surface over and directly contacting the bottom electrode , and a sidewall connecting said upper and lower surfaces , at least a part of the sidewall surrounded by the silicon nitride layer ; and a conductive top electrode over and directly contacting the dielectric material over an area at least extensive with the upper surface of the dielectric material . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5717242A Filed: 1996-04-17 Issued: 1998-02-10 Integrated circuit having local interconnect for reduing signal cross coupled noise (Original Assignee) Advanced Micro Devices Inc (Current Assignee) Advanced Micro Devices Inc Mark W. Michael, Robert Dawson, Basab Bandyopadhyay, H. Jim Fulford, Jr., Fred N. Hause, William S. Brennan |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch (layer dielectric) stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5717242A CLAIM 12 . An interconnect structure , comprising : a local interconnect of a first conductivity placed across a local area of a semiconductor topography ; a single layer of dielectric placed upon the local interconnect ; a metal conductor of a second conductivity greater than said first conductivity placed upon said single layer of dielectric directly above the local interconnect , wherein the metal conductor occupies a conductor lateral area less than the local area , and wherein a portion of said local area which exceeds said conductor lateral area is occupied by a contact from a power supply conductor extending through said single layer dielectric (multiple etch, etch process) to said portion ; and a power supply coupled to said local interconnect . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer protects removal of a substrate material by an etch process (layer dielectric) . |
US5717242A CLAIM 12 . An interconnect structure , comprising : a local interconnect of a first conductivity placed across a local area of a semiconductor topography ; a single layer of dielectric placed upon the local interconnect ; a metal conductor of a second conductivity greater than said first conductivity placed upon said single layer of dielectric directly above the local interconnect , wherein the metal conductor occupies a conductor lateral area less than the local area , and wherein a portion of said local area which exceeds said conductor lateral area is occupied by a contact from a power supply conductor extending through said single layer dielectric (multiple etch, etch process) to said portion ; and a power supply coupled to said local interconnect . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch stop layer protects lower layers during an etching process (doped polysilicon) . |
US5717242A CLAIM 6 . The integrated circuit as recited in claim 1 , wherein said local interconnect comprises doped polysilicon (etching process) . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch (layer dielectric) stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US5717242A CLAIM 12 . An interconnect structure , comprising : a local interconnect of a first conductivity placed across a local area of a semiconductor topography ; a single layer of dielectric placed upon the local interconnect ; a metal conductor of a second conductivity greater than said first conductivity placed upon said single layer of dielectric directly above the local interconnect , wherein the metal conductor occupies a conductor lateral area less than the local area , and wherein a portion of said local area which exceeds said conductor lateral area is occupied by a contact from a power supply conductor extending through said single layer dielectric (multiple etch, etch process) to said portion ; and a power supply coupled to said local interconnect . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5874364A Filed: 1996-03-26 Issued: 1999-02-23 Thin film deposition method, capacitor device and method for fabricating the same, and semiconductor device and method for fabricating the same (Original Assignee) Fujitsu Ltd (Current Assignee) Fujitsu Semiconductor Ltd Masaaki Nakabayashi, Tetsuro Tamura, Hideyuki Noshiro |
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| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch stop layer protects lower layers during an etching process (film thickness) . |
US5874364A CLAIM 1 . A thin film forming method comprising the steps of : using 2 , 6-dimethyl 3 , 5-heptanedione (Ru(DMHPD) 3) as a source material for forming a film by chemical vapor deposition and vaporizing 2 , 6-dimethyl 3 , 5-heptanedione for application whereby disuniformity in film thickness (etching process) and sheet resistance of said film is decreased on a film substrate . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space (said sub) in a portion of said first sub interlevel dielectric layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5874364A CLAIM 7 . The thin film forming method according to claim 2 wherein the temperature of said sub (first space) strate is 300° C . to 600° C . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5717250A Filed: 1996-03-07 Issued: 1998-02-10 Sputter and CVD deposited titanium nitride barrier layer between a platinum layer and a polysilicon plug (Original Assignee) Micron Technology Inc (Current Assignee) Micron Technology Inc Paul J. Schuele, Pierre C. Fazan |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region (makes electrical contact) coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5717250A CLAIM 15 . A structure for making electrical contact from a conductive region in a semiconductor substrate , through a dielectric layer having an upper surface , to a superjacent capacitor having a platinum lower plate and a perovskite oxide capacitor dielectric layer overlying the lower plate , said structure comprising : (a) a vertically-oriented conductive polysilicon plug formed within said dielectric layer which makes electrical contact (contact region, contact bottom) with the conductive region , said polysilicon plug having a top surface that is recessed below the upper surface of said dielectric layer ; (c) a titanium silicide layer overlying and in contact with the top surface ; (d) a titanium carbonitride layer overlying and in contact with the titanium silicide layer ; (e) a titanium nitride layer superjacent a horizontal portion of the titanium carbonitride layer and in contact therewith , said titanium nitride layer also being in contact with the platinum lower capacitor plate . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric layer insulates said contact region (makes electrical contact) . |
US5717250A CLAIM 15 . A structure for making electrical contact from a conductive region in a semiconductor substrate , through a dielectric layer having an upper surface , to a superjacent capacitor having a platinum lower plate and a perovskite oxide capacitor dielectric layer overlying the lower plate , said structure comprising : (a) a vertically-oriented conductive polysilicon plug formed within said dielectric layer which makes electrical contact (contact region, contact bottom) with the conductive region , said polysilicon plug having a top surface that is recessed below the upper surface of said dielectric layer ; (c) a titanium silicide layer overlying and in contact with the top surface ; (d) a titanium carbonitride layer overlying and in contact with the titanium silicide layer ; (e) a titanium nitride layer superjacent a horizontal portion of the titanium carbonitride layer and in contact therewith , said titanium nitride layer also being in contact with the platinum lower capacitor plate . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric layer insulates said contact region (makes electrical contact) . |
US5717250A CLAIM 15 . A structure for making electrical contact from a conductive region in a semiconductor substrate , through a dielectric layer having an upper surface , to a superjacent capacitor having a platinum lower plate and a perovskite oxide capacitor dielectric layer overlying the lower plate , said structure comprising : (a) a vertically-oriented conductive polysilicon plug formed within said dielectric layer which makes electrical contact (contact region, contact bottom) with the conductive region , said polysilicon plug having a top surface that is recessed below the upper surface of said dielectric layer ; (c) a titanium silicide layer overlying and in contact with the top surface ; (d) a titanium carbonitride layer overlying and in contact with the titanium silicide layer ; (e) a titanium nitride layer superjacent a horizontal portion of the titanium carbonitride layer and in contact therewith , said titanium nitride layer also being in contact with the platinum lower capacitor plate . |
| US7977797B2 CLAIM 6 . An integrated circuit of claim 1 wherein said spacer region insulates said contact region (makes electrical contact) . |
US5717250A CLAIM 15 . A structure for making electrical contact from a conductive region in a semiconductor substrate , through a dielectric layer having an upper surface , to a superjacent capacitor having a platinum lower plate and a perovskite oxide capacitor dielectric layer overlying the lower plate , said structure comprising : (a) a vertically-oriented conductive polysilicon plug formed within said dielectric layer which makes electrical contact (contact region, contact bottom) with the conductive region , said polysilicon plug having a top surface that is recessed below the upper surface of said dielectric layer ; (c) a titanium silicide layer overlying and in contact with the top surface ; (d) a titanium carbonitride layer overlying and in contact with the titanium silicide layer ; (e) a titanium nitride layer superjacent a horizontal portion of the titanium carbonitride layer and in contact therewith , said titanium nitride layer also being in contact with the platinum lower capacitor plate . |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area of said contact region (makes electrical contact) permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
US5717250A CLAIM 15 . A structure for making electrical contact from a conductive region in a semiconductor substrate , through a dielectric layer having an upper surface , to a superjacent capacitor having a platinum lower plate and a perovskite oxide capacitor dielectric layer overlying the lower plate , said structure comprising : (a) a vertically-oriented conductive polysilicon plug formed within said dielectric layer which makes electrical contact (contact region, contact bottom) with the conductive region , said polysilicon plug having a top surface that is recessed below the upper surface of said dielectric layer ; (c) a titanium silicide layer overlying and in contact with the top surface ; (d) a titanium carbonitride layer overlying and in contact with the titanium silicide layer ; (e) a titanium nitride layer superjacent a horizontal portion of the titanium carbonitride layer and in contact therewith , said titanium nitride layer also being in contact with the platinum lower capacitor plate . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric layer for said contact region (makes electrical contact) is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5717250A CLAIM 15 . A structure for making electrical contact from a conductive region in a semiconductor substrate , through a dielectric layer having an upper surface , to a superjacent capacitor having a platinum lower plate and a perovskite oxide capacitor dielectric layer overlying the lower plate , said structure comprising : (a) a vertically-oriented conductive polysilicon plug formed within said dielectric layer which makes electrical contact (contact region, contact bottom) with the conductive region , said polysilicon plug having a top surface that is recessed below the upper surface of said dielectric layer ; (c) a titanium silicide layer overlying and in contact with the top surface ; (d) a titanium carbonitride layer overlying and in contact with the titanium silicide layer ; (e) a titanium nitride layer superjacent a horizontal portion of the titanium carbonitride layer and in contact therewith , said titanium nitride layer also being in contact with the platinum lower capacitor plate . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region (makes electrical contact) and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric (said structure) layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom (makes electrical contact) , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US5717250A CLAIM 1 . A contact structure for use in integrated circuits , said structure (second interlevel dielectric) comprising : (a) a dielectric layer overlying substrate-superjacent topography , said dielectric layer having an upper surface ; (b) a polysilicon plug which penetrates said dielectric layer and which makes contact with a transistor junction in the substrate , said polysilicon plug having an upper surface that is recessed below the level of said dielectric layer ; (c) a titanium silicide layer superjacent and in contact with the upper surface of the plug ; (d) a titanium carbonitride layer superjacent and in contact with the titanium silicide layer ; and (e) a titanium nitride layer superjacent a horizontal portion of the titanium carbonitride layer and in contact therewith . US5717250A CLAIM 15 . A structure for making electrical contact from a conductive region in a semiconductor substrate , through a dielectric layer having an upper surface , to a superjacent capacitor having a platinum lower plate and a perovskite oxide capacitor dielectric layer overlying the lower plate , said structure comprising : (a) a vertically-oriented conductive polysilicon plug formed within said dielectric layer which makes electrical contact (contact region, contact bottom) with the conductive region , said polysilicon plug having a top surface that is recessed below the upper surface of said dielectric layer ; (c) a titanium silicide layer overlying and in contact with the top surface ; (d) a titanium carbonitride layer overlying and in contact with the titanium silicide layer ; (e) a titanium nitride layer superjacent a horizontal portion of the titanium carbonitride layer and in contact therewith , said titanium nitride layer also being in contact with the platinum lower capacitor plate . |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region (makes electrical contact) is a first range of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5717250A CLAIM 15 . A structure for making electrical contact from a conductive region in a semiconductor substrate , through a dielectric layer having an upper surface , to a superjacent capacitor having a platinum lower plate and a perovskite oxide capacitor dielectric layer overlying the lower plate , said structure comprising : (a) a vertically-oriented conductive polysilicon plug formed within said dielectric layer which makes electrical contact (contact region, contact bottom) with the conductive region , said polysilicon plug having a top surface that is recessed below the upper surface of said dielectric layer ; (c) a titanium silicide layer overlying and in contact with the top surface ; (d) a titanium carbonitride layer overlying and in contact with the titanium silicide layer ; (e) a titanium nitride layer superjacent a horizontal portion of the titanium carbonitride layer and in contact therewith , said titanium nitride layer also being in contact with the platinum lower capacitor plate . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5733809A Filed: 1996-02-08 Issued: 1998-03-31 Split-polysilicon CMOS process for multi-megabit dynamic memories incorporating stacked container capacitor cells (Original Assignee) Micron Technology Inc (Current Assignee) Micron Technology Inc Charles H. Dennison, Aftab Ahmad |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area (second conductive layer) of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (vertical sidewalls, desired capacitor) layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5733809A CLAIM 3 . The process of claim 2 , wherein fabricating cell capacitors is accomplished with the steps of : (a) forming a second conductive layer (substrate coupling area) which blankets both N-type regions and P-type regions and lines each cavity ; (b) removing certain portions of said second conductive layer which are on an upper surface of said mold layer , while leaving other portions of said second conductive layer which line said storage-node contact openings , said other portions becoming individual storage-node capacitor plates for individual memory cells ; (c) forming a cell dielectric layer on exposed surfaces of each storage-node capacitor plate ; and (d) forming a third conductive layer which covers the cell dielectric layer . US5733809A CLAIM 6 . The process of claim 1 , wherein the gates for the transistors having a first channel type have vertical sidewalls (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) , and the process further comprises the step of forming dielectric spacers on the sidewall of each such transistor gate . US5733809A CLAIM 8 . A process for manufacturing on a semiconductor wafer a CMOS circuit which incorporates capacitors , said process comprising the steps of : (a) forming a first conductive layer superjacent an upper surface of the wafer ; (b) selectively etching a first portion of said first conductive layer to form gates for transistors having a channel of a first conductivity type , while leaving , unetched , a second portion of the conductive layer ; (c) performing at least one source/drain implant for the transistors having a channel of said first conductivity type ; (d) depositing an insulative mold layer which completely overlies said upper surface ; (e) etching a cavity within the insulative mold layer at each desired capacitor (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) location ; (f) forming a second conductive layer , a portion of which lines each cavity , the portion of said second conductive layer within each cavity forming a first plate for each capacitor ; (g) selectively etching said second portion of said first conductive layer to form gates for transistors having a channel of the second conductivity type ; and (h) performing at least one source/drain implant for the transistors having a channel of said second conductivity type . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer protects removal of a substrate material by an etch process (capacitor plates) . |
US5733809A CLAIM 3 . The process of claim 2 , wherein fabricating cell capacitors is accomplished with the steps of : (a) forming a second conductive layer which blankets both N-type regions and P-type regions and lines each cavity ; (b) removing certain portions of said second conductive layer which are on an upper surface of said mold layer , while leaving other portions of said second conductive layer which line said storage-node contact openings , said other portions becoming individual storage-node capacitor plates (etch process) for individual memory cells ; (c) forming a cell dielectric layer on exposed surfaces of each storage-node capacitor plate ; and (d) forming a third conductive layer which covers the cell dielectric layer . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (vertical sidewalls, desired capacitor) layer insulates said contact region . |
US5733809A CLAIM 6 . The process of claim 1 , wherein the gates for the transistors having a first channel type have vertical sidewalls (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) , and the process further comprises the step of forming dielectric spacers on the sidewall of each such transistor gate . US5733809A CLAIM 8 . A process for manufacturing on a semiconductor wafer a CMOS circuit which incorporates capacitors , said process comprising the steps of : (a) forming a first conductive layer superjacent an upper surface of the wafer ; (b) selectively etching a first portion of said first conductive layer to form gates for transistors having a channel of a first conductivity type , while leaving , unetched , a second portion of the conductive layer ; (c) performing at least one source/drain implant for the transistors having a channel of said first conductivity type ; (d) depositing an insulative mold layer which completely overlies said upper surface ; (e) etching a cavity within the insulative mold layer at each desired capacitor (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) location ; (f) forming a second conductive layer , a portion of which lines each cavity , the portion of said second conductive layer within each cavity forming a first plate for each capacitor ; (g) selectively etching said second portion of said first conductive layer to form gates for transistors having a channel of the second conductivity type ; and (h) performing at least one source/drain implant for the transistors having a channel of said second conductivity type . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (vertical sidewalls, desired capacitor) layer insulates said contact region . |
US5733809A CLAIM 6 . The process of claim 1 , wherein the gates for the transistors having a first channel type have vertical sidewalls (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) , and the process further comprises the step of forming dielectric spacers on the sidewall of each such transistor gate . US5733809A CLAIM 8 . A process for manufacturing on a semiconductor wafer a CMOS circuit which incorporates capacitors , said process comprising the steps of : (a) forming a first conductive layer superjacent an upper surface of the wafer ; (b) selectively etching a first portion of said first conductive layer to form gates for transistors having a channel of a first conductivity type , while leaving , unetched , a second portion of the conductive layer ; (c) performing at least one source/drain implant for the transistors having a channel of said first conductivity type ; (d) depositing an insulative mold layer which completely overlies said upper surface ; (e) etching a cavity within the insulative mold layer at each desired capacitor (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) location ; (f) forming a second conductive layer , a portion of which lines each cavity , the portion of said second conductive layer within each cavity forming a first plate for each capacitor ; (g) selectively etching said second portion of said first conductive layer to form gates for transistors having a channel of the second conductivity type ; and (h) performing at least one source/drain implant for the transistors having a channel of said second conductivity type . |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area (second conductive layer) of said contact region permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
US5733809A CLAIM 3 . The process of claim 2 , wherein fabricating cell capacitors is accomplished with the steps of : (a) forming a second conductive layer (substrate coupling area) which blankets both N-type regions and P-type regions and lines each cavity ; (b) removing certain portions of said second conductive layer which are on an upper surface of said mold layer , while leaving other portions of said second conductive layer which line said storage-node contact openings , said other portions becoming individual storage-node capacitor plates for individual memory cells ; (c) forming a cell dielectric layer on exposed surfaces of each storage-node capacitor plate ; and (d) forming a third conductive layer which covers the cell dielectric layer . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (vertical sidewalls, desired capacitor) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5733809A CLAIM 6 . The process of claim 1 , wherein the gates for the transistors having a first channel type have vertical sidewalls (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) , and the process further comprises the step of forming dielectric spacers on the sidewall of each such transistor gate . US5733809A CLAIM 8 . A process for manufacturing on a semiconductor wafer a CMOS circuit which incorporates capacitors , said process comprising the steps of : (a) forming a first conductive layer superjacent an upper surface of the wafer ; (b) selectively etching a first portion of said first conductive layer to form gates for transistors having a channel of a first conductivity type , while leaving , unetched , a second portion of the conductive layer ; (c) performing at least one source/drain implant for the transistors having a channel of said first conductivity type ; (d) depositing an insulative mold layer which completely overlies said upper surface ; (e) etching a cavity within the insulative mold layer at each desired capacitor (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) location ; (f) forming a second conductive layer , a portion of which lines each cavity , the portion of said second conductive layer within each cavity forming a first plate for each capacitor ; (g) selectively etching said second portion of said first conductive layer to form gates for transistors having a channel of the second conductivity type ; and (h) performing at least one source/drain implant for the transistors having a channel of said second conductivity type . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric (vertical sidewalls, desired capacitor) layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space (storage node, drain region) in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5733809A CLAIM 1 . A process for manufacturing a CMOS dynamic random access memory cell array on a semiconductor wafer , said process comprising the steps of : (a) forming a first conductive layer superjacent an upper surface of the wafer ; (b) selectively etching a first portion of said first conductive layer to form gates for transistors having a channel of a first conductivity type , while leaving unetched a second portion of the conductive layer ; (c) performing at least one source/drain implant for the transistors having a channel of said first conductivity type ; (d) depositing an insulative mold layer which completely overlies said upper surface ; (e) etching a cavity through the insulative mold layer at each memory cell location , each cavity having a floor in electrical contact with a source/drain region (second space, floating gate) of one of said transistors having a channel of said first conductivity type ; (f) fabricating a cell capacitor at each memory cell location by employing the cavity at each location as a mold in which at least one plate of each capacitor is formed ; (g) selectively etching said second portion of said conductive layer to form gates for transistors having a channel of the second conductivity type ; and (h) performing at least one source/drain implant for the transistors having a channel of said second conductivity type . US5733809A CLAIM 6 . The process of claim 1 , wherein the gates for the transistors having a first channel type have vertical sidewalls (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) , and the process further comprises the step of forming dielectric spacers on the sidewall of each such transistor gate . US5733809A CLAIM 8 . A process for manufacturing on a semiconductor wafer a CMOS circuit which incorporates capacitors , said process comprising the steps of : (a) forming a first conductive layer superjacent an upper surface of the wafer ; (b) selectively etching a first portion of said first conductive layer to form gates for transistors having a channel of a first conductivity type , while leaving , unetched , a second portion of the conductive layer ; (c) performing at least one source/drain implant for the transistors having a channel of said first conductivity type ; (d) depositing an insulative mold layer which completely overlies said upper surface ; (e) etching a cavity within the insulative mold layer at each desired capacitor (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) location ; (f) forming a second conductive layer , a portion of which lines each cavity , the portion of said second conductive layer within each cavity forming a first plate for each capacitor ; (g) selectively etching said second portion of said first conductive layer to form gates for transistors having a channel of the second conductivity type ; and (h) performing at least one source/drain implant for the transistors having a channel of said second conductivity type . US5733809A CLAIM 15 . A process for manufacturing a CMOS dynamic random access memory cell array on a semiconductor substrate , said process comprising the steps of : (a) forming both N-type regions and P-type regions within an upper stratum of the substrate ; (b) forming field isolation regions in said upper stratum ; (c) forming a gate dielectric layer which covers an upper surface of the substrate except where covered by field isolation regions ; (d) forming a first conductive layer which covers all field isolation regions and the gate dielectric layer ; (e) selectively etching a first portion of the first conductive layer to form gates for transistors having channels of a first conductivity type while leaving , unetched , a second portion of said first conductive layer , said first portion overlying said P-type regions and said second portion overlying said N-type regions ; (f) performing at least one source/drain implant for the transistors having a channel of said first conductivity type ; (g) depositing an insulative mold layer which blankets the entire the substrate and all structures existing thereon ; (h) etching a cavity within the insulative mold layer at each memory cell location , each cavity having a floor in electrical contact with a source/drain region of one of said transistors having a channel of said first conductivity type ; (i) fabricating a cell capacitor at each memory cell location by using the cavity at each location as a mold in which a storage node (second space, floating gate) plate for each capacitor is formed ; (j) selectively etching said second portion of said conductive layer to form gates for transistors having a channel of the second conductivity type ; and (k) performing at least one source/drain implant for the transistors having a channel of said second conductivity type . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (vertical sidewalls, desired capacitor) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area (second conductive layer) of said contact region is smaller than a metal layer coupling area of said contact region . |
US5733809A CLAIM 3 . The process of claim 2 , wherein fabricating cell capacitors is accomplished with the steps of : (a) forming a second conductive layer (substrate coupling area) which blankets both N-type regions and P-type regions and lines each cavity ; (b) removing certain portions of said second conductive layer which are on an upper surface of said mold layer , while leaving other portions of said second conductive layer which line said storage-node contact openings , said other portions becoming individual storage-node capacitor plates for individual memory cells ; (c) forming a cell dielectric layer on exposed surfaces of each storage-node capacitor plate ; and (d) forming a third conductive layer which covers the cell dielectric layer . US5733809A CLAIM 6 . The process of claim 1 , wherein the gates for the transistors having a first channel type have vertical sidewalls (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) , and the process further comprises the step of forming dielectric spacers on the sidewall of each such transistor gate . US5733809A CLAIM 8 . A process for manufacturing on a semiconductor wafer a CMOS circuit which incorporates capacitors , said process comprising the steps of : (a) forming a first conductive layer superjacent an upper surface of the wafer ; (b) selectively etching a first portion of said first conductive layer to form gates for transistors having a channel of a first conductivity type , while leaving , unetched , a second portion of the conductive layer ; (c) performing at least one source/drain implant for the transistors having a channel of said first conductivity type ; (d) depositing an insulative mold layer which completely overlies said upper surface ; (e) etching a cavity within the insulative mold layer at each desired capacitor (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) location ; (f) forming a second conductive layer , a portion of which lines each cavity , the portion of said second conductive layer within each cavity forming a first plate for each capacitor ; (g) selectively etching said second portion of said first conductive layer to form gates for transistors having a channel of the second conductivity type ; and (h) performing at least one source/drain implant for the transistors having a channel of said second conductivity type . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (vertical sidewalls, desired capacitor) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5733809A CLAIM 6 . The process of claim 1 , wherein the gates for the transistors having a first channel type have vertical sidewalls (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) , and the process further comprises the step of forming dielectric spacers on the sidewall of each such transistor gate . US5733809A CLAIM 8 . A process for manufacturing on a semiconductor wafer a CMOS circuit which incorporates capacitors , said process comprising the steps of : (a) forming a first conductive layer superjacent an upper surface of the wafer ; (b) selectively etching a first portion of said first conductive layer to form gates for transistors having a channel of a first conductivity type , while leaving , unetched , a second portion of the conductive layer ; (c) performing at least one source/drain implant for the transistors having a channel of said first conductivity type ; (d) depositing an insulative mold layer which completely overlies said upper surface ; (e) etching a cavity within the insulative mold layer at each desired capacitor (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) location ; (f) forming a second conductive layer , a portion of which lines each cavity , the portion of said second conductive layer within each cavity forming a first plate for each capacitor ; (g) selectively etching said second portion of said first conductive layer to form gates for transistors having a channel of the second conductivity type ; and (h) performing at least one source/drain implant for the transistors having a channel of said second conductivity type . |
| US7977797B2 CLAIM 13 . An integrated circuit of claim 11 further comprising a floating gate (storage node, drain region) . |
US5733809A CLAIM 1 . A process for manufacturing a CMOS dynamic random access memory cell array on a semiconductor wafer , said process comprising the steps of : (a) forming a first conductive layer superjacent an upper surface of the wafer ; (b) selectively etching a first portion of said first conductive layer to form gates for transistors having a channel of a first conductivity type , while leaving unetched a second portion of the conductive layer ; (c) performing at least one source/drain implant for the transistors having a channel of said first conductivity type ; (d) depositing an insulative mold layer which completely overlies said upper surface ; (e) etching a cavity through the insulative mold layer at each memory cell location , each cavity having a floor in electrical contact with a source/drain region (second space, floating gate) of one of said transistors having a channel of said first conductivity type ; (f) fabricating a cell capacitor at each memory cell location by employing the cavity at each location as a mold in which at least one plate of each capacitor is formed ; (g) selectively etching said second portion of said conductive layer to form gates for transistors having a channel of the second conductivity type ; and (h) performing at least one source/drain implant for the transistors having a channel of said second conductivity type . US5733809A CLAIM 15 . A process for manufacturing a CMOS dynamic random access memory cell array on a semiconductor substrate , said process comprising the steps of : (a) forming both N-type regions and P-type regions within an upper stratum of the substrate ; (b) forming field isolation regions in said upper stratum ; (c) forming a gate dielectric layer which covers an upper surface of the substrate except where covered by field isolation regions ; (d) forming a first conductive layer which covers all field isolation regions and the gate dielectric layer ; (e) selectively etching a first portion of the first conductive layer to form gates for transistors having channels of a first conductivity type while leaving , unetched , a second portion of said first conductive layer , said first portion overlying said P-type regions and said second portion overlying said N-type regions ; (f) performing at least one source/drain implant for the transistors having a channel of said first conductivity type ; (g) depositing an insulative mold layer which blankets the entire the substrate and all structures existing thereon ; (h) etching a cavity within the insulative mold layer at each memory cell location , each cavity having a floor in electrical contact with a source/drain region of one of said transistors having a channel of said first conductivity type ; (i) fabricating a cell capacitor at each memory cell location by using the cavity at each location as a mold in which a storage node (second space, floating gate) plate for each capacitor is formed ; (j) selectively etching said second portion of said conductive layer to form gates for transistors having a channel of the second conductivity type ; and (k) performing at least one source/drain implant for the transistors having a channel of said second conductivity type . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5700706A Filed: 1995-12-15 Issued: 1997-12-23 Self-aligned isolated polysilicon plugged contacts (Original Assignee) Micron Technology Inc (Current Assignee) Micron Technology Inc Werner Juengling |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch (second etch, dry etch) stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch (first etch) stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch (second etch, dry etch) stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub (second sub) interlevel dielectric layer over said second etch stop layer . |
US5700706A CLAIM 1 . A method for preparing an integrated circuit structure , said integrated circuit structure including a doped silicon substrate , and MOS device sealed under a layer of nitride having substantially vertical sides thereto and being in contact with the silicon substrate , there being a bitline contact on one side of the MOS device and a cellnode contact on an opposite side of the MOS device , the bitline and cellnode contacts being on the doped silicon substrate , the method comprises the steps of : (a) applying a passivation layer of oxide over the doped silicon substrate , the bitline contact , the cellnode contact and the MOS device ; (b) applying a first layer of photoresist over the passivation layer of oxide ; (c) exposing that the portion of the first layer of photoresist that is situated above and vertically aligned with the cellnode contact and at least a portion of the MOS device , and leaving unexposed that the portion of the first layer of photoresist that is above and vertically aligned with the bitline contact ; (d) developing the first layer of photoresist ; (e) etching with a first etch (first etch) chemistry selective to nitride , silicon , and polysilicon through the passivation layer of oxide to expose the cellnode contact ; (f) depositing a first layer of thin nitride film over the passivation oxide layer and the cellnode contact ; (g) etching anisotropically with a second etch (second etch, multiple etch, multiple etch stop insulation layer, second etch stop layer, second etch stop layers) chemistry the first layer of thin nitride film so as to form a substantially vertically oriented nitride spacer above the MOS device ; (h) applying a first conductive layer over the doped silicon substrate , the MOS device , passivation layer of oxide layer , and cellnode contact ; (i) applying a second layer of photoresist over the integrated circuit structure ; (j) exposing that the portion of the second layer of photoresist that is situated above and vertically aligned with : the bitline contact and at least a portion of the MOS device , and leaving unexposed that the portion of the second layer of photoresist that is above and vertically aligned with the cellnode contact ; (k) developing the second layer of photoresist ; (l) etching with a third etch chemistry through the first conductive layer with selectivity to oxide and to nitride ; (m) etching with a fourth etch chemistry selective to nitride , polysilicon , and silicon through the passivation layer of oxide to expose the bitline contact ; (n) depositing a second layer of thin nitride film ; (o) etching anisotropically with a fifth etch chemistry the second layer of thin nitride film ; (p) depositing a second conductive layer over the bitline contact and at least a portion of the MOS device ; and (q) performing a chemical-mechanical polishing step , whereby the first conductive layer forms a cellnode plug to the cellnode contact , the second conductive layer forms a bitline plug to the bitline contact , the cellnode plug and the bitline plug being separated by the nitride spacer above the MOS device . US5700706A CLAIM 20 . The method as defined in claim 18 , further comprising the steps of : (a) depositing a third layer of thin nitride film over the area extending from the field oxide region to the H MOS device after the step of etching with an eighth etch chemistry through the passivation layer of oxide over and to expose the FG and GH contacts ; and then (b) etching anisotropically with a ninth etch chemistry the third layer of thin nitride film so as to form : (1) first and second sub (second sub) stantially vertically oriented G nitride spacers above the nitride layer of the G MOS device and on opposite sides thereof , the first G nitride spacer being separated from the second G nitride spacer by the passivation layer of oxide , the first G nitride spacer being substantially aligned a side the FG device contact opposite the nitride spacer extending vertically above the field oxide region , the second G nitride spacer being substantially aligned with a side of the GH device contact opposite of the H MOS device ; and (2) first and second substantially vertically oriented H nitride spacers above the nitride layer of the H MOS device and on opposite sides thereof , the first H nitride spacer being substantially aligned a side the GH device contact opposite of the G MOS device , and the second H nitride spacer being separated from the first H nitride spacer by the passivation layer of oxide . US5700706A CLAIM 22 . The method as defined in claim 18 , further comprising the step of etching with a tenth etch chemistry the third conductive layer in a dry etch (second etch, multiple etch, multiple etch stop insulation layer, second etch stop layer, second etch stop layers) back process prior to the step of performing a chemical-mechanical polishing step to form a contact with the FG device contact and a separated contact to the GH device contact . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch (first etch) stop layer protects removal of a substrate material by an etch process . |
US5700706A CLAIM 1 . A method for preparing an integrated circuit structure , said integrated circuit structure including a doped silicon substrate , and MOS device sealed under a layer of nitride having substantially vertical sides thereto and being in contact with the silicon substrate , there being a bitline contact on one side of the MOS device and a cellnode contact on an opposite side of the MOS device , the bitline and cellnode contacts being on the doped silicon substrate , the method comprises the steps of : (a) applying a passivation layer of oxide over the doped silicon substrate , the bitline contact , the cellnode contact and the MOS device ; (b) applying a first layer of photoresist over the passivation layer of oxide ; (c) exposing that the portion of the first layer of photoresist that is situated above and vertically aligned with the cellnode contact and at least a portion of the MOS device , and leaving unexposed that the portion of the first layer of photoresist that is above and vertically aligned with the bitline contact ; (d) developing the first layer of photoresist ; (e) etching with a first etch (first etch) chemistry selective to nitride , silicon , and polysilicon through the passivation layer of oxide to expose the cellnode contact ; (f) depositing a first layer of thin nitride film over the passivation oxide layer and the cellnode contact ; (g) etching anisotropically with a second etch chemistry the first layer of thin nitride film so as to form a substantially vertically oriented nitride spacer above the MOS device ; (h) applying a first conductive layer over the doped silicon substrate , the MOS device , passivation layer of oxide layer , and cellnode contact ; (i) applying a second layer of photoresist over the integrated circuit structure ; (j) exposing that the portion of the second layer of photoresist that is situated above and vertically aligned with : the bitline contact and at least a portion of the MOS device , and leaving unexposed that the portion of the second layer of photoresist that is above and vertically aligned with the cellnode contact ; (k) developing the second layer of photoresist ; (l) etching with a third etch chemistry through the first conductive layer with selectivity to oxide and to nitride ; (m) etching with a fourth etch chemistry selective to nitride , polysilicon , and silicon through the passivation layer of oxide to expose the bitline contact ; (n) depositing a second layer of thin nitride film ; (o) etching anisotropically with a fifth etch chemistry the second layer of thin nitride film ; (p) depositing a second conductive layer over the bitline contact and at least a portion of the MOS device ; and (q) performing a chemical-mechanical polishing step , whereby the first conductive layer forms a cellnode plug to the cellnode contact , the second conductive layer forms a bitline plug to the bitline contact , the cellnode plug and the bitline plug being separated by the nitride spacer above the MOS device . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch (second etch, dry etch) stop layer protects lower layers during an etching process (doped polysilicon) . |
US5700706A CLAIM 9 . The method as defined in claim 1 , wherein the first and second conductive layers are composed essentially of N-doped polysilicon (etching process) . US5700706A CLAIM 11 . The method as defined in claim 10 , wherein the step of performing a chemical-mechanical polishing step reduces the height of the first and second conductive layers below the length of the C nitride spacer above and in contact with the nitride layer of the CMOS device formed by the step of etching with a second etch (second etch, multiple etch, multiple etch stop insulation layer, second etch stop layer, second etch stop layers) chemistry , whereby the isolation of the first conductive layer contacting the CD cellnode contact from the second conductive layer contacting the BC bitline contact is unaffected by the alignment of the area above the BC bitline contact that is opened up by the steps of etching with a third , fourth , and fifth etch chemistries to expose the BC bitline contact . US5700706A CLAIM 22 . The method as defined in claim 18 , further comprising the step of etching with a tenth etch chemistry the third conductive layer in a dry etch (second etch, multiple etch, multiple etch stop insulation layer, second etch stop layer, second etch stop layers) back process prior to the step of performing a chemical-mechanical polishing step to form a contact with the FG device contact and a separated contact to the GH device contact . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub (second sub) interlevel dielectric layer insulates said contact region . |
US5700706A CLAIM 20 . The method as defined in claim 18 , further comprising the steps of : (a) depositing a third layer of thin nitride film over the area extending from the field oxide region to the H MOS device after the step of etching with an eighth etch chemistry through the passivation layer of oxide over and to expose the FG and GH contacts ; and then (b) etching anisotropically with a ninth etch chemistry the third layer of thin nitride film so as to form : (1) first and second sub (second sub) stantially vertically oriented G nitride spacers above the nitride layer of the G MOS device and on opposite sides thereof , the first G nitride spacer being separated from the second G nitride spacer by the passivation layer of oxide , the first G nitride spacer being substantially aligned a side the FG device contact opposite the nitride spacer extending vertically above the field oxide region , the second G nitride spacer being substantially aligned with a side of the GH device contact opposite of the H MOS device ; and (2) first and second substantially vertically oriented H nitride spacers above the nitride layer of the H MOS device and on opposite sides thereof , the first H nitride spacer being substantially aligned a side the GH device contact opposite of the G MOS device , and the second H nitride spacer being separated from the first H nitride spacer by the passivation layer of oxide . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch (first etch) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (second etch, dry etch) stop layer is in a range of about 300 to 800 Šthick and said second sub (second sub) interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5700706A CLAIM 3 . The method as defined in claim 1 , wherein the area above the cellnode contact that is opened up by the step of etching with a first etch (first etch) chemistry to expose the cellnode contact is substantially the same area that is filled up by the cellnode plug , and the area above the bitline contact that is opened up by the steps of etching with a first , second and third etch chemistries to expose the bitline contact is greater than the that is filled up with the bitline plug . US5700706A CLAIM 11 . The method as defined in claim 10 , wherein the step of performing a chemical-mechanical polishing step reduces the height of the first and second conductive layers below the length of the C nitride spacer above and in contact with the nitride layer of the CMOS device formed by the step of etching with a second etch (second etch, multiple etch, multiple etch stop insulation layer, second etch stop layer, second etch stop layers) chemistry , whereby the isolation of the first conductive layer contacting the CD cellnode contact from the second conductive layer contacting the BC bitline contact is unaffected by the alignment of the area above the BC bitline contact that is opened up by the steps of etching with a third , fourth , and fifth etch chemistries to expose the BC bitline contact . US5700706A CLAIM 20 . The method as defined in claim 18 , further comprising the steps of : (a) depositing a third layer of thin nitride film over the area extending from the field oxide region to the H MOS device after the step of etching with an eighth etch chemistry through the passivation layer of oxide over and to expose the FG and GH contacts ; and then (b) etching anisotropically with a ninth etch chemistry the third layer of thin nitride film so as to form : (1) first and second sub (second sub) stantially vertically oriented G nitride spacers above the nitride layer of the G MOS device and on opposite sides thereof , the first G nitride spacer being separated from the second G nitride spacer by the passivation layer of oxide , the first G nitride spacer being substantially aligned a side the FG device contact opposite the nitride spacer extending vertically above the field oxide region , the second G nitride spacer being substantially aligned with a side of the GH device contact opposite of the H MOS device ; and (2) first and second substantially vertically oriented H nitride spacers above the nitride layer of the H MOS device and on opposite sides thereof , the first H nitride spacer being substantially aligned a side the GH device contact opposite of the G MOS device , and the second H nitride spacer being separated from the first H nitride spacer by the passivation layer of oxide . US5700706A CLAIM 22 . The method as defined in claim 18 , further comprising the step of etching with a tenth etch chemistry the third conductive layer in a dry etch (second etch, multiple etch, multiple etch stop insulation layer, second etch stop layer, second etch stop layers) back process prior to the step of performing a chemical-mechanical polishing step to form a contact with the FG device contact and a separated contact to the GH device contact . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub (second sub) interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5700706A CLAIM 20 . The method as defined in claim 18 , further comprising the steps of : (a) depositing a third layer of thin nitride film over the area extending from the field oxide region to the H MOS device after the step of etching with an eighth etch chemistry through the passivation layer of oxide over and to expose the FG and GH contacts ; and then (b) etching anisotropically with a ninth etch chemistry the third layer of thin nitride film so as to form : (1) first and second sub (second sub) stantially vertically oriented G nitride spacers above the nitride layer of the G MOS device and on opposite sides thereof , the first G nitride spacer being separated from the second G nitride spacer by the passivation layer of oxide , the first G nitride spacer being substantially aligned a side the FG device contact opposite the nitride spacer extending vertically above the field oxide region , the second G nitride spacer being substantially aligned with a side of the GH device contact opposite of the H MOS device ; and (2) first and second substantially vertically oriented H nitride spacers above the nitride layer of the H MOS device and on opposite sides thereof , the first H nitride spacer being substantially aligned a side the GH device contact opposite of the G MOS device , and the second H nitride spacer being separated from the first H nitride spacer by the passivation layer of oxide . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch (second etch, dry etch) stop insulation layer comprising a first etch (first etch) stop layer and a second etch (second etch, dry etch) stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub (second sub) interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US5700706A CLAIM 3 . The method as defined in claim 1 , wherein the area above the cellnode contact that is opened up by the step of etching with a first etch (first etch) chemistry to expose the cellnode contact is substantially the same area that is filled up by the cellnode plug , and the area above the bitline contact that is opened up by the steps of etching with a first , second and third etch chemistries to expose the bitline contact is greater than the that is filled up with the bitline plug . US5700706A CLAIM 11 . The method as defined in claim 10 , wherein the step of performing a chemical-mechanical polishing step reduces the height of the first and second conductive layers below the length of the C nitride spacer above and in contact with the nitride layer of the CMOS device formed by the step of etching with a second etch (second etch, multiple etch, multiple etch stop insulation layer, second etch stop layer, second etch stop layers) chemistry , whereby the isolation of the first conductive layer contacting the CD cellnode contact from the second conductive layer contacting the BC bitline contact is unaffected by the alignment of the area above the BC bitline contact that is opened up by the steps of etching with a third , fourth , and fifth etch chemistries to expose the BC bitline contact . US5700706A CLAIM 20 . The method as defined in claim 18 , further comprising the steps of : (a) depositing a third layer of thin nitride film over the area extending from the field oxide region to the H MOS device after the step of etching with an eighth etch chemistry through the passivation layer of oxide over and to expose the FG and GH contacts ; and then (b) etching anisotropically with a ninth etch chemistry the third layer of thin nitride film so as to form : (1) first and second sub (second sub) stantially vertically oriented G nitride spacers above the nitride layer of the G MOS device and on opposite sides thereof , the first G nitride spacer being separated from the second G nitride spacer by the passivation layer of oxide , the first G nitride spacer being substantially aligned a side the FG device contact opposite the nitride spacer extending vertically above the field oxide region , the second G nitride spacer being substantially aligned with a side of the GH device contact opposite of the H MOS device ; and (2) first and second substantially vertically oriented H nitride spacers above the nitride layer of the H MOS device and on opposite sides thereof , the first H nitride spacer being substantially aligned a side the GH device contact opposite of the G MOS device , and the second H nitride spacer being separated from the first H nitride spacer by the passivation layer of oxide . US5700706A CLAIM 22 . The method as defined in claim 18 , further comprising the step of etching with a tenth etch chemistry the third conductive layer in a dry etch (second etch, multiple etch, multiple etch stop insulation layer, second etch stop layer, second etch stop layers) back process prior to the step of performing a chemical-mechanical polishing step to form a contact with the FG device contact and a separated contact to the GH device contact . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch (first etch) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (second etch, dry etch) stop layer is in a range of about 300 to 800 Šthick and said second sub (second sub) interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5700706A CLAIM 3 . The method as defined in claim 1 , wherein the area above the cellnode contact that is opened up by the step of etching with a first etch (first etch) chemistry to expose the cellnode contact is substantially the same area that is filled up by the cellnode plug , and the area above the bitline contact that is opened up by the steps of etching with a first , second and third etch chemistries to expose the bitline contact is greater than the that is filled up with the bitline plug . US5700706A CLAIM 11 . The method as defined in claim 10 , wherein the step of performing a chemical-mechanical polishing step reduces the height of the first and second conductive layers below the length of the C nitride spacer above and in contact with the nitride layer of the CMOS device formed by the step of etching with a second etch (second etch, multiple etch, multiple etch stop insulation layer, second etch stop layer, second etch stop layers) chemistry , whereby the isolation of the first conductive layer contacting the CD cellnode contact from the second conductive layer contacting the BC bitline contact is unaffected by the alignment of the area above the BC bitline contact that is opened up by the steps of etching with a third , fourth , and fifth etch chemistries to expose the BC bitline contact . US5700706A CLAIM 20 . The method as defined in claim 18 , further comprising the steps of : (a) depositing a third layer of thin nitride film over the area extending from the field oxide region to the H MOS device after the step of etching with an eighth etch chemistry through the passivation layer of oxide over and to expose the FG and GH contacts ; and then (b) etching anisotropically with a ninth etch chemistry the third layer of thin nitride film so as to form : (1) first and second sub (second sub) stantially vertically oriented G nitride spacers above the nitride layer of the G MOS device and on opposite sides thereof , the first G nitride spacer being separated from the second G nitride spacer by the passivation layer of oxide , the first G nitride spacer being substantially aligned a side the FG device contact opposite the nitride spacer extending vertically above the field oxide region , the second G nitride spacer being substantially aligned with a side of the GH device contact opposite of the H MOS device ; and (2) first and second substantially vertically oriented H nitride spacers above the nitride layer of the H MOS device and on opposite sides thereof , the first H nitride spacer being substantially aligned a side the GH device contact opposite of the G MOS device , and the second H nitride spacer being separated from the first H nitride spacer by the passivation layer of oxide . US5700706A CLAIM 22 . The method as defined in claim 18 , further comprising the step of etching with a tenth etch chemistry the third conductive layer in a dry etch (second etch, multiple etch, multiple etch stop insulation layer, second etch stop layer, second etch stop layers) back process prior to the step of performing a chemical-mechanical polishing step to form a contact with the FG device contact and a separated contact to the GH device contact . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5734179A Filed: 1995-12-12 Issued: 1998-03-31 SRAM cell having single layer polysilicon thin film transistors (Original Assignee) Advanced Micro Devices Inc (Current Assignee) Advanced Micro Devices Inc Kuang-Yeh Chang, Yowjuang W. Liu |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (thin film) of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch (gate oxide) stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5734179A CLAIM 1 . An integrated circuit formed on a semiconductor substrate , comprising : a plurality of metal oxide semiconductor (MOS) transistors each comprising : source and drain regions formed of a first impurity in the semiconductor substrate , and a first conductive gate formed of a polysilicon layer overlying and insulated from said source and drain regions ; at least one thin film (metal layer coupling area) transistor (TFT) comprising : an insulating layer , a polysilicon body formed of said polysilicon layer and disposed on said insulating layer , said polysilicon body comprising source , gate and drain regions , the polysilicon source and drain regions containing a second impurity , a second conductive gate between said polysilicon source and drain regions , and a dielectric layer disposed between said second conductive gate and said polysilicon body ; and a local interconnect structure formed from a reaction between silicon deposited between at least one of said MOS transistors and said at least one TFT and a refractory metal silicide and interconnecting said at least one of said MOS transistors and said at least one TFT . US5734179A CLAIM 13 . An integrated circuit as recited in claim 1 , wherein the gate of each of said MOS transistors further comprises a gate oxide (second etch) layer disposed between said polysilicon layer and the semiconductor substrate , said semiconductor substrate implanted with said first impurity at areas corresponding to said source and drain regions . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch (gate oxide) stop layer protects lower layers during an etching process . |
US5734179A CLAIM 13 . An integrated circuit as recited in claim 1 , wherein the gate of each of said MOS transistors further comprises a gate oxide (second etch) layer disposed between said polysilicon layer and the semiconductor substrate , said semiconductor substrate implanted with said first impurity at areas corresponding to said source and drain regions . |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area of said contact region permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area (thin film) of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
US5734179A CLAIM 1 . An integrated circuit formed on a semiconductor substrate , comprising : a plurality of metal oxide semiconductor (MOS) transistors each comprising : source and drain regions formed of a first impurity in the semiconductor substrate , and a first conductive gate formed of a polysilicon layer overlying and insulated from said source and drain regions ; at least one thin film (metal layer coupling area) transistor (TFT) comprising : an insulating layer , a polysilicon body formed of said polysilicon layer and disposed on said insulating layer , said polysilicon body comprising source , gate and drain regions , the polysilicon source and drain regions containing a second impurity , a second conductive gate between said polysilicon source and drain regions , and a dielectric layer disposed between said second conductive gate and said polysilicon body ; and a local interconnect structure formed from a reaction between silicon deposited between at least one of said MOS transistors and said at least one TFT and a refractory metal silicide and interconnecting said at least one of said MOS transistors and said at least one TFT . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (gate oxide) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5734179A CLAIM 13 . An integrated circuit as recited in claim 1 , wherein the gate of each of said MOS transistors further comprises a gate oxide (second etch) layer disposed between said polysilicon layer and the semiconductor substrate , said semiconductor substrate implanted with said first impurity at areas corresponding to said source and drain regions . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch (gate oxide) stop layer wherein said first etch stop layer and said second etch stop layers (exposed regions) have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (thin film) of said contact region . |
US5734179A CLAIM 1 . An integrated circuit formed on a semiconductor substrate , comprising : a plurality of metal oxide semiconductor (MOS) transistors each comprising : source and drain regions formed of a first impurity in the semiconductor substrate , and a first conductive gate formed of a polysilicon layer overlying and insulated from said source and drain regions ; at least one thin film (metal layer coupling area) transistor (TFT) comprising : an insulating layer , a polysilicon body formed of said polysilicon layer and disposed on said insulating layer , said polysilicon body comprising source , gate and drain regions , the polysilicon source and drain regions containing a second impurity , a second conductive gate between said polysilicon source and drain regions , and a dielectric layer disposed between said second conductive gate and said polysilicon body ; and a local interconnect structure formed from a reaction between silicon deposited between at least one of said MOS transistors and said at least one TFT and a refractory metal silicide and interconnecting said at least one of said MOS transistors and said at least one TFT . US5734179A CLAIM 13 . An integrated circuit as recited in claim 1 , wherein the gate of each of said MOS transistors further comprises a gate oxide (second etch) layer disposed between said polysilicon layer and the semiconductor substrate , said semiconductor substrate implanted with said first impurity at areas corresponding to said source and drain regions . US5734179A CLAIM 22 . An integrated circuit comprising : a first group of transistors each comprising : a silicon substrate , a field oxidized layer formed on said silicon substrate ; a transistor gate formed of a polysilicon layer overlying a first exposed region of said field oxidized layer , and source and drain regions formed at respective second and third exposed regions (second etch stop layers) of said field oxidized layer , each containing a first impurity implanted into said silicon substrate ; a second group of thin film transistors each comprising : a polysilicon body formed of said polysilicon layer and disposed on said field oxidized layer , said polysilicon body comprising a source and drain region each containing a second implanted impurity , and a gate region containing a third implanted impurity , a gate conductor overlying said polysilicon gate region , and an insulating layer disposed between said polysilicon body and said gate conductor ; and a local interconnect pattern formed of a reaction between silicon deposited between respective regions of said first and second group of transistors and a refractory metal silicide and connecting said second group of transistors to said first group of transistors . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (gate oxide) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5734179A CLAIM 13 . An integrated circuit as recited in claim 1 , wherein the gate of each of said MOS transistors further comprises a gate oxide (second etch) layer disposed between said polysilicon layer and the semiconductor substrate , said semiconductor substrate implanted with said first impurity at areas corresponding to said source and drain regions . |
| US7977797B2 CLAIM 13 . An integrated circuit of claim 11 further comprising a floating gate (drain portion) . |
US5734179A CLAIM 17 . An integrated circuit as recited in claim 16 , wherein the drain region of said first and second TFTs comprises polycide and the drain region of the first MOS transistor comprises silicide , said local interconnecting portions further comprising a second interconnect portion electrically connecting the polycide of said first TFT drain portion (floating gate) to the silicide of said drain region of said first MOS transistor . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5731242A Filed: 1995-11-14 Issued: 1998-03-24 Self-aligned contact process in semiconductor fabrication (Original Assignee) Intel Corp (Current Assignee) Intel Corp Krishna K. Parat, Glen N. Wada, Gregory E. Atwood, Daniel N. Tang |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area (second conductive layer) of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance (forming two) of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch (first etch) stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch (second etch) stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5731242A CLAIM 2 . The method of claim 1 , wherein the forming steps (a) , (b) , and (c) comprise the steps of : forming a gate insulative layer over the semiconductor substrate ; depositing a conductive layer over the gate insulative layer ; forming the first insulative layer over the conductive layer ; forming a first etch (first etch) -stop layer over the first insulative layer , the first etch-stop layer forming a first portion of the stack etch-stop layer ; forming the stack from the gate insulative layer , the conductive layer , the first insulative layer , and the first etch-stop layer , wherein the gate comprises at least a portion of the conductive layer ; forming the first insulative layer on sides of the stack ; forming a second etch (second etch) -stop layer over the semiconductor substrate , the second etch-stop layer forming a second portion of the stack etch-stop layer ; and removing the second etch-stop layer at least from a region on the semiconductor substrate while leaving at least some of the second etch-stop layer on the sides of the stack and at least some of the first etch-stop layer on top of the stack to form the stack etch-stop layer . US5731242A CLAIM 13 . A method of forming a semiconductor device on a semiconductor substrate comprising the steps of : a) forming two (isolates guidance) stacks on the semiconductor substrate , each stack comprising a floating gate and a control gate ; b) forming a first insulative layer over at least exposed portions of the floating gate of each stack ; c) forming a stack etch-stop layer around each stack ; d) forming a second insulative layer over the semiconductor substrate and around the stacks wherein the etch-stop layer comprises a different material than the second insulative layer ; e) forming an opening in the second insulative layer between the stacks in an etch process that etches the second insulative layer at a greater rate than the etch-stop layer such that the gate of each stack is protected during the etch process ; and f) filling the opening with a conductive material . US5731242A CLAIM 14 . The method of claim 13 , wherein the forming steps (a) , (b) , and (c) comprise the steps of : forming a gate insulative layer over the semiconductor substrate ; depositing a first conductive layer over the gate insulative layer ; forming an inter-gate dielectric layer over the first conductive layer ; depositing a second conductive layer (substrate coupling area) over the inter-gate dielectric layer ; forming the first insulative layer over the second conductive layer ; forming a first etch-stop layer over the first insulative layer , the first etch-stop layer forming a first portion of the stack etch-stop layer ; forming the two stacks from the gate insulative layer , the first conductive layer , the inter-gate dielectric layer , the second conductive layer , the first insulative layer and the first etch-stop layer , wherein the floating gate of each stack comprises at least a portion of the first conductive layer and wherein the control gate of each stack comprises at least a portion of the second conductive layer ; forming the first insulative layer on sides of each stack ; forming a second etch-stop layer over the semiconductor substrate , the second etch-stop layer forming a second portion of the stack etch-stop layer ; and removing the second etch-stop layer at least from a region between the stacks while leaving at least some of the second etch-stop layer on the sides of each stack and at least some of the first etch-stop layer on top of each stack to form the stack etch-stop layer . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch (first etch) stop layer protects removal of a substrate material by an etch process (etch process) . |
US5731242A CLAIM 1 . A method of forming a semiconductor device on a semiconductor substrate comprising the steps of : a) forming a stack on the semiconductor substrate , the stack comprising a gate ; b) forming a first insulative layer over exposed portions of the gate ; c) forming a stack etch-stop layer around the stack ; d) forming a second insulative layer over the semiconductor substrate and around the stack wherein the etch-stop layer comprises a different material than the second insulative layer ; e) forming an opening in the second insulative layer over a region on the semiconductor substrate adjacent to the stack in an etch process (etch process) that etches the second insulative layer at a greater rate than the etch-stop layer such that the gate is protected during the etch process ; and f) filling the opening with a conductive material . US5731242A CLAIM 2 . The method of claim 1 , wherein the forming steps (a) , (b) , and (c) comprise the steps of : forming a gate insulative layer over the semiconductor substrate ; depositing a conductive layer over the gate insulative layer ; forming the first insulative layer over the conductive layer ; forming a first etch (first etch) -stop layer over the first insulative layer , the first etch-stop layer forming a first portion of the stack etch-stop layer ; forming the stack from the gate insulative layer , the conductive layer , the first insulative layer , and the first etch-stop layer , wherein the gate comprises at least a portion of the conductive layer ; forming the first insulative layer on sides of the stack ; forming a second etch-stop layer over the semiconductor substrate , the second etch-stop layer forming a second portion of the stack etch-stop layer ; and removing the second etch-stop layer at least from a region on the semiconductor substrate while leaving at least some of the second etch-stop layer on the sides of the stack and at least some of the first etch-stop layer on top of the stack to form the stack etch-stop layer . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch (second etch) stop layer protects lower layers during an etching process . |
US5731242A CLAIM 2 . The method of claim 1 , wherein the forming steps (a) , (b) , and (c) comprise the steps of : forming a gate insulative layer over the semiconductor substrate ; depositing a conductive layer over the gate insulative layer ; forming the first insulative layer over the conductive layer ; forming a first etch-stop layer over the first insulative layer , the first etch-stop layer forming a first portion of the stack etch-stop layer ; forming the stack from the gate insulative layer , the conductive layer , the first insulative layer , and the first etch-stop layer , wherein the gate comprises at least a portion of the conductive layer ; forming the first insulative layer on sides of the stack ; forming a second etch (second etch) -stop layer over the semiconductor substrate , the second etch-stop layer forming a second portion of the stack etch-stop layer ; and removing the second etch-stop layer at least from a region on the semiconductor substrate while leaving at least some of the second etch-stop layer on the sides of the stack and at least some of the first etch-stop layer on top of the stack to form the stack etch-stop layer . |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area (second conductive layer) of said contact region permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
US5731242A CLAIM 14 . The method of claim 13 , wherein the forming steps (a) , (b) , and (c) comprise the steps of : forming a gate insulative layer over the semiconductor substrate ; depositing a first conductive layer over the gate insulative layer ; forming an inter-gate dielectric layer over the first conductive layer ; depositing a second conductive layer (substrate coupling area) over the inter-gate dielectric layer ; forming the first insulative layer over the second conductive layer ; forming a first etch-stop layer over the first insulative layer , the first etch-stop layer forming a first portion of the stack etch-stop layer ; forming the two stacks from the gate insulative layer , the first conductive layer , the inter-gate dielectric layer , the second conductive layer , the first insulative layer and the first etch-stop layer , wherein the floating gate of each stack comprises at least a portion of the first conductive layer and wherein the control gate of each stack comprises at least a portion of the second conductive layer ; forming the first insulative layer on sides of each stack ; forming a second etch-stop layer over the semiconductor substrate , the second etch-stop layer forming a second portion of the stack etch-stop layer ; and removing the second etch-stop layer at least from a region between the stacks while leaving at least some of the second etch-stop layer on the sides of each stack and at least some of the first etch-stop layer on top of each stack to form the stack etch-stop layer . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch (first etch) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (second etch) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5731242A CLAIM 2 . The method of claim 1 , wherein the forming steps (a) , (b) , and (c) comprise the steps of : forming a gate insulative layer over the semiconductor substrate ; depositing a conductive layer over the gate insulative layer ; forming the first insulative layer over the conductive layer ; forming a first etch (first etch) -stop layer over the first insulative layer , the first etch-stop layer forming a first portion of the stack etch-stop layer ; forming the stack from the gate insulative layer , the conductive layer , the first insulative layer , and the first etch-stop layer , wherein the gate comprises at least a portion of the conductive layer ; forming the first insulative layer on sides of the stack ; forming a second etch (second etch) -stop layer over the semiconductor substrate , the second etch-stop layer forming a second portion of the stack etch-stop layer ; and removing the second etch-stop layer at least from a region on the semiconductor substrate while leaving at least some of the second etch-stop layer on the sides of the stack and at least some of the first etch-stop layer on top of the stack to form the stack etch-stop layer . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US5731242A CLAIM 4 . The method of claim 3 , further comprising the steps of depositing a metal silicide layer over the conductive layer , and forming (anti reflective coating) a buffer layer over the metal silicide layer , wherein the stack comprises a portion of the metal silicide layer and a portion of the buffer layer . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch (first etch) stop layer and a second etch (second etch) stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom (top portion) , such that a substrate coupling area (second conductive layer) of said contact region is smaller than a metal layer coupling area of said contact region . |
US5731242A CLAIM 2 . The method of claim 1 , wherein the forming steps (a) , (b) , and (c) comprise the steps of : forming a gate insulative layer over the semiconductor substrate ; depositing a conductive layer over the gate insulative layer ; forming the first insulative layer over the conductive layer ; forming a first etch (first etch) -stop layer over the first insulative layer , the first etch-stop layer forming a first portion of the stack etch-stop layer ; forming the stack from the gate insulative layer , the conductive layer , the first insulative layer , and the first etch-stop layer , wherein the gate comprises at least a portion of the conductive layer ; forming the first insulative layer on sides of the stack ; forming a second etch (second etch) -stop layer over the semiconductor substrate , the second etch-stop layer forming a second portion of the stack etch-stop layer ; and removing the second etch-stop layer at least from a region on the semiconductor substrate while leaving at least some of the second etch-stop layer on the sides of the stack and at least some of the first etch-stop layer on top of the stack to form the stack etch-stop layer . US5731242A CLAIM 12 . The method as described in claim 11 wherein the opening is formed such that the opening overlies a top portion (contact bottom) of the stack . US5731242A CLAIM 14 . The method of claim 13 , wherein the forming steps (a) , (b) , and (c) comprise the steps of : forming a gate insulative layer over the semiconductor substrate ; depositing a first conductive layer over the gate insulative layer ; forming an inter-gate dielectric layer over the first conductive layer ; depositing a second conductive layer (substrate coupling area) over the inter-gate dielectric layer ; forming the first insulative layer over the second conductive layer ; forming a first etch-stop layer over the first insulative layer , the first etch-stop layer forming a first portion of the stack etch-stop layer ; forming the two stacks from the gate insulative layer , the first conductive layer , the inter-gate dielectric layer , the second conductive layer , the first insulative layer and the first etch-stop layer , wherein the floating gate of each stack comprises at least a portion of the first conductive layer and wherein the control gate of each stack comprises at least a portion of the second conductive layer ; forming the first insulative layer on sides of each stack ; forming a second etch-stop layer over the semiconductor substrate , the second etch-stop layer forming a second portion of the stack etch-stop layer ; and removing the second etch-stop layer at least from a region between the stacks while leaving at least some of the second etch-stop layer on the sides of each stack and at least some of the first etch-stop layer on top of each stack to form the stack etch-stop layer . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch (first etch) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (second etch) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5731242A CLAIM 2 . The method of claim 1 , wherein the forming steps (a) , (b) , and (c) comprise the steps of : forming a gate insulative layer over the semiconductor substrate ; depositing a conductive layer over the gate insulative layer ; forming the first insulative layer over the conductive layer ; forming a first etch (first etch) -stop layer over the first insulative layer , the first etch-stop layer forming a first portion of the stack etch-stop layer ; forming the stack from the gate insulative layer , the conductive layer , the first insulative layer , and the first etch-stop layer , wherein the gate comprises at least a portion of the conductive layer ; forming the first insulative layer on sides of the stack ; forming a second etch (second etch) -stop layer over the semiconductor substrate , the second etch-stop layer forming a second portion of the stack etch-stop layer ; and removing the second etch-stop layer at least from a region on the semiconductor substrate while leaving at least some of the second etch-stop layer on the sides of the stack and at least some of the first etch-stop layer on top of the stack to form the stack etch-stop layer . |
| US7977797B2 CLAIM 13 . An integrated circuit of claim 11 further comprising a floating gate (floating gate) . |
US5731242A CLAIM 8 . The method of claim 1 , wherein the gate is a floating gate (floating gate) . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US5731242A CLAIM 4 . The method of claim 3 , further comprising the steps of depositing a metal silicide layer over the conductive layer , and forming (anti reflective coating) a buffer layer over the metal silicide layer , wherein the stack comprises a portion of the metal silicide layer and a portion of the buffer layer . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | JPH09102492A Filed: 1995-10-03 Issued: 1997-04-15 半導体装置の製造方法および半導体製造装置 (Original Assignee) Toshiba Corp; 株式会社東芝 Takeshi Sunada, 武 砂田 |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (製造方法) of said contact region ; and a multiple etch stop insulation layer (真空中) coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation (の絶縁) between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
JPH09102492A CLAIM 1 【請求項１】 半導体基板上の絶縁 (electrical insulation) 膜上に配線パターン を形成する工程と、上記配線パターンが形成された半導 体基板を収容した反応室内にＳｉＨ 4 ガスおよびＨ 2 Ｏ 2 を導入し、６６５Ｐａ以下の真空中 (multiple etch stop insulation layer) 、−１０℃以上＋ １０℃以下の温度範囲内で互いに反応させ、リフロー形 状を有するリフローＳｉＯ 2 膜を形成するリフロー膜形 成工程と、上記リフロー膜形成工程に引き続き、前記反 応室内にフッ素系ガスを導入し、所定の真空中でプラズ マ放電させて前記リフローＳｉＯ 2 膜の表面をプラズマ 処理するプラズマ処理工程と、この後、前記半導体基板 に対して所定の熱処理を行う熱処理工程とを具備するこ とを特徴とする半導体装置の製造方法 (metal layer coupling area) 。 |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area of said contact region permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area (製造方法) of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
JPH09102492A CLAIM 1 【請求項１】 半導体基板上の絶縁膜上に配線パターン を形成する工程と、上記配線パターンが形成された半導 体基板を収容した反応室内にＳｉＨ 4 ガスおよびＨ 2 Ｏ 2 を導入し、６６５Ｐａ以下の真空中、−１０℃以上＋ １０℃以下の温度範囲内で互いに反応させ、リフロー形 状を有するリフローＳｉＯ 2 膜を形成するリフロー膜形 成工程と、上記リフロー膜形成工程に引き続き、前記反 応室内にフッ素系ガスを導入し、所定の真空中でプラズ マ放電させて前記リフローＳｉＯ 2 膜の表面をプラズマ 処理するプラズマ処理工程と、この後、前記半導体基板 に対して所定の熱処理を行う熱処理工程とを具備するこ とを特徴とする半導体装置の製造方法 (metal layer coupling area) 。 |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range (温度範囲内) of about 0 . 16 μm to 0 . 18 μm wide . |
JPH09102492A CLAIM 1 【請求項１】 半導体基板上の絶縁膜上に配線パターン を形成する工程と、上記配線パターンが形成された半導 体基板を収容した反応室内にＳｉＨ 4 ガスおよびＨ 2 Ｏ 2 を導入し、６６５Ｐａ以下の真空中、−１０℃以上＋ １０℃以下の温度範囲内 (second range) で互いに反応させ、リフロー形 状を有するリフローＳｉＯ 2 膜を形成するリフロー膜形 成工程と、上記リフロー膜形成工程に引き続き、前記反 応室内にフッ素系ガスを導入し、所定の真空中でプラズ マ放電させて前記リフローＳｉＯ 2 膜の表面をプラズマ 処理するプラズマ処理工程と、この後、前記半導体基板 に対して所定の熱処理を行う熱処理工程とを具備するこ とを特徴とする半導体装置の製造方法。 |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer (真空中) comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (製造方法) of said contact region . |
JPH09102492A CLAIM 1 【請求項１】 半導体基板上の絶縁膜上に配線パターン を形成する工程と、上記配線パターンが形成された半導 体基板を収容した反応室内にＳｉＨ 4 ガスおよびＨ 2 Ｏ 2 を導入し、６６５Ｐａ以下の真空中 (multiple etch stop insulation layer) 、−１０℃以上＋ １０℃以下の温度範囲内で互いに反応させ、リフロー形 状を有するリフローＳｉＯ 2 膜を形成するリフロー膜形 成工程と、上記リフロー膜形成工程に引き続き、前記反 応室内にフッ素系ガスを導入し、所定の真空中でプラズ マ放電させて前記リフローＳｉＯ 2 膜の表面をプラズマ 処理するプラズマ処理工程と、この後、前記半導体基板 に対して所定の熱処理を行う熱処理工程とを具備するこ とを特徴とする半導体装置の製造方法 (metal layer coupling area) 。 |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region is a first range of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range (温度範囲内) of about 0 . 16 μm to 0 . 18 μm wide . |
JPH09102492A CLAIM 1 【請求項１】 半導体基板上の絶縁膜上に配線パターン を形成する工程と、上記配線パターンが形成された半導 体基板を収容した反応室内にＳｉＨ 4 ガスおよびＨ 2 Ｏ 2 を導入し、６６５Ｐａ以下の真空中、−１０℃以上＋ １０℃以下の温度範囲内 (second range) で互いに反応させ、リフロー形 状を有するリフローＳｉＯ 2 膜を形成するリフロー膜形 成工程と、上記リフロー膜形成工程に引き続き、前記反 応室内にフッ素系ガスを導入し、所定の真空中でプラズ マ放電させて前記リフローＳｉＯ 2 膜の表面をプラズマ 処理するプラズマ処理工程と、この後、前記半導体基板 に対して所定の熱処理を行う熱処理工程とを具備するこ とを特徴とする半導体装置の製造方法。 |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5898006A Filed: 1995-09-07 Issued: 1999-04-27 Method of manufacturing a semiconductor device having various types of MOSFETS (Original Assignee) NEC Corp (Current Assignee) NEC Electronics Corp Takaharu Kudoh |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch (non-volatile memory, said sub) stop layer directly on said substrate in said contact region ; a first sub (non-volatile memory, said sub) interlevel dielectric layer over said first etch stop layer ; a second etch stop layer (insulating film) over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5898006A CLAIM 1 . A method of manufacturing a semiconductor device including on a single chip a non-volatile memory (first etch, first sub, first space, first etch stop layer) element , an input protecting element and a logic circuit element , comprising the steps of : (a) forming a first gate of a first MOS transistor for said non-volatile memory element , a second gate of a second MOS transistor for said input protecting element and a third gate of a third MOS transistor for said logic circuit element on a substrate of a first conductivity type ; (b) simultaneously injecting a first impurity of a second conductivity type in said sub (first etch, first sub, first space, first etch stop layer) strate in self-alignment with said first gate of said first MOS transistor for said non-volatile memory element , said second gate of said second MOS transistor for said input protecting element and said third gate of said third MOS transistor for said logic circuit element with a first dose amount ; (c) after said step (b) for a first mask for masking said third MOS transistor for said logic circuit element ; (d) after said step (c) , injecting a second impurity of the second conductivity type in said substrate in self-alignment with said first and second gates of said first MOS transistor for said non-volatile memory and said second MOS transistor for said input protecting element with a second dose amount which is higher than said first dose amount so as to form source and drain regions of said first and second MOS transistors for said non-volatile memory element and input protecting element having single drain structure ; (e) removing said first mask , and forming first side wall insulating film (second etch stop layer, second interlevel dielectric layer) s on sidewalls of said third gate of said third MOS transistor for said logic circuit element ; (f) after said step (e) forming a second mask for masking said first and second MOS transistors for said non-volatile memory element and input protecting element ; and (g) injecting a third impurity of the second conductivity type in said source and drain regions of said third MOS transistor for said logic circuit in self-alignment with said third gate and said side wall insulating films with a bird dose amount which is higher than said first dose amount so as to form an LDD structure . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch (non-volatile memory, said sub) stop layer protects removal of a substrate material by an etch process . |
US5898006A CLAIM 1 . A method of manufacturing a semiconductor device including on a single chip a non-volatile memory (first etch, first sub, first space, first etch stop layer) element , an input protecting element and a logic circuit element , comprising the steps of : (a) forming a first gate of a first MOS transistor for said non-volatile memory element , a second gate of a second MOS transistor for said input protecting element and a third gate of a third MOS transistor for said logic circuit element on a substrate of a first conductivity type ; (b) simultaneously injecting a first impurity of a second conductivity type in said sub (first etch, first sub, first space, first etch stop layer) strate in self-alignment with said first gate of said first MOS transistor for said non-volatile memory element , said second gate of said second MOS transistor for said input protecting element and said third gate of said third MOS transistor for said logic circuit element with a first dose amount ; (c) after said step (b) for a first mask for masking said third MOS transistor for said logic circuit element ; (d) after said step (c) , injecting a second impurity of the second conductivity type in said substrate in self-alignment with said first and second gates of said first MOS transistor for said non-volatile memory and said second MOS transistor for said input protecting element with a second dose amount which is higher than said first dose amount so as to form source and drain regions of said first and second MOS transistors for said non-volatile memory element and input protecting element having single drain structure ; (e) removing said first mask , and forming first side wall insulating films on sidewalls of said third gate of said third MOS transistor for said logic circuit element ; (f) after said step (e) forming a second mask for masking said first and second MOS transistors for said non-volatile memory element and input protecting element ; and (g) injecting a third impurity of the second conductivity type in said source and drain regions of said third MOS transistor for said logic circuit in self-alignment with said third gate and said side wall insulating films with a bird dose amount which is higher than said first dose amount so as to form an LDD structure . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub (non-volatile memory, said sub) interlevel dielectric layer insulates said contact region . |
US5898006A CLAIM 1 . A method of manufacturing a semiconductor device including on a single chip a non-volatile memory (first etch, first sub, first space, first etch stop layer) element , an input protecting element and a logic circuit element , comprising the steps of : (a) forming a first gate of a first MOS transistor for said non-volatile memory element , a second gate of a second MOS transistor for said input protecting element and a third gate of a third MOS transistor for said logic circuit element on a substrate of a first conductivity type ; (b) simultaneously injecting a first impurity of a second conductivity type in said sub (first etch, first sub, first space, first etch stop layer) strate in self-alignment with said first gate of said first MOS transistor for said non-volatile memory element , said second gate of said second MOS transistor for said input protecting element and said third gate of said third MOS transistor for said logic circuit element with a first dose amount ; (c) after said step (b) for a first mask for masking said third MOS transistor for said logic circuit element ; (d) after said step (c) , injecting a second impurity of the second conductivity type in said substrate in self-alignment with said first and second gates of said first MOS transistor for said non-volatile memory and said second MOS transistor for said input protecting element with a second dose amount which is higher than said first dose amount so as to form source and drain regions of said first and second MOS transistors for said non-volatile memory element and input protecting element having single drain structure ; (e) removing said first mask , and forming first side wall insulating films on sidewalls of said third gate of said third MOS transistor for said logic circuit element ; (f) after said step (e) forming a second mask for masking said first and second MOS transistors for said non-volatile memory element and input protecting element ; and (g) injecting a third impurity of the second conductivity type in said source and drain regions of said third MOS transistor for said logic circuit in self-alignment with said third gate and said side wall insulating films with a bird dose amount which is higher than said first dose amount so as to form an LDD structure . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch stop layer (insulating film) protects lower layers during an etching process . |
US5898006A CLAIM 1 . A method of manufacturing a semiconductor device including on a single chip a non-volatile memory element , an input protecting element and a logic circuit element , comprising the steps of : (a) forming a first gate of a first MOS transistor for said non-volatile memory element , a second gate of a second MOS transistor for said input protecting element and a third gate of a third MOS transistor for said logic circuit element on a substrate of a first conductivity type ; (b) simultaneously injecting a first impurity of a second conductivity type in said substrate in self-alignment with said first gate of said first MOS transistor for said non-volatile memory element , said second gate of said second MOS transistor for said input protecting element and said third gate of said third MOS transistor for said logic circuit element with a first dose amount ; (c) after said step (b) for a first mask for masking said third MOS transistor for said logic circuit element ; (d) after said step (c) , injecting a second impurity of the second conductivity type in said substrate in self-alignment with said first and second gates of said first MOS transistor for said non-volatile memory and said second MOS transistor for said input protecting element with a second dose amount which is higher than said first dose amount so as to form source and drain regions of said first and second MOS transistors for said non-volatile memory element and input protecting element having single drain structure ; (e) removing said first mask , and forming first side wall insulating film (second etch stop layer, second interlevel dielectric layer) s on sidewalls of said third gate of said third MOS transistor for said logic circuit element ; (f) after said step (e) forming a second mask for masking said first and second MOS transistors for said non-volatile memory element and input protecting element ; and (g) injecting a third impurity of the second conductivity type in said source and drain regions of said third MOS transistor for said logic circuit in self-alignment with said third gate and said side wall insulating films with a bird dose amount which is higher than said first dose amount so as to form an LDD structure . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch (non-volatile memory, said sub) stop layer is in a range of about 300 to 800 Šthick , said first sub (non-volatile memory, said sub) interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer (insulating film) is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5898006A CLAIM 1 . A method of manufacturing a semiconductor device including on a single chip a non-volatile memory (first etch, first sub, first space, first etch stop layer) element , an input protecting element and a logic circuit element , comprising the steps of : (a) forming a first gate of a first MOS transistor for said non-volatile memory element , a second gate of a second MOS transistor for said input protecting element and a third gate of a third MOS transistor for said logic circuit element on a substrate of a first conductivity type ; (b) simultaneously injecting a first impurity of a second conductivity type in said sub (first etch, first sub, first space, first etch stop layer) strate in self-alignment with said first gate of said first MOS transistor for said non-volatile memory element , said second gate of said second MOS transistor for said input protecting element and said third gate of said third MOS transistor for said logic circuit element with a first dose amount ; (c) after said step (b) for a first mask for masking said third MOS transistor for said logic circuit element ; (d) after said step (c) , injecting a second impurity of the second conductivity type in said substrate in self-alignment with said first and second gates of said first MOS transistor for said non-volatile memory and said second MOS transistor for said input protecting element with a second dose amount which is higher than said first dose amount so as to form source and drain regions of said first and second MOS transistors for said non-volatile memory element and input protecting element having single drain structure ; (e) removing said first mask , and forming first side wall insulating film (second etch stop layer, second interlevel dielectric layer) s on sidewalls of said third gate of said third MOS transistor for said logic circuit element ; (f) after said step (e) forming a second mask for masking said first and second MOS transistors for said non-volatile memory element and input protecting element ; and (g) injecting a third impurity of the second conductivity type in said source and drain regions of said third MOS transistor for said logic circuit in self-alignment with said third gate and said side wall insulating films with a bird dose amount which is higher than said first dose amount so as to form an LDD structure . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space (non-volatile memory, said sub) in a portion of said first sub (non-volatile memory, said sub) interlevel dielectric layer for said contact region is in a first range (time t) of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5898006A CLAIM 1 . A method of manufacturing a semiconductor device including on a single chip a non-volatile memory (first etch, first sub, first space, first etch stop layer) element , an input protecting element and a logic circuit element , comprising the steps of : (a) forming a first gate of a first MOS transistor for said non-volatile memory element , a second gate of a second MOS transistor for said input protecting element and a third gate of a third MOS transistor for said logic circuit element on a substrate of a first conductivity type ; (b) simultaneously injecting a first impurity of a second conductivity type in said sub (first etch, first sub, first space, first etch stop layer) strate in self-alignment with said first gate of said first MOS transistor for said non-volatile memory element , said second gate of said second MOS transistor for said input protecting element and said third gate of said third MOS transistor for said logic circuit element with a first dose amount ; (c) after said step (b) for a first mask for masking said third MOS transistor for said logic circuit element ; (d) after said step (c) , injecting a second impurity of the second conductivity type in said substrate in self-alignment with said first and second gates of said first MOS transistor for said non-volatile memory and said second MOS transistor for said input protecting element with a second dose amount which is higher than said first dose amount so as to form source and drain regions of said first and second MOS transistors for said non-volatile memory element and input protecting element having single drain structure ; (e) removing said first mask , and forming first side wall insulating films on sidewalls of said third gate of said third MOS transistor for said logic circuit element ; (f) after said step (e) forming a second mask for masking said first and second MOS transistors for said non-volatile memory element and input protecting element ; and (g) injecting a third impurity of the second conductivity type in said source and drain regions of said third MOS transistor for said logic circuit in self-alignment with said third gate and said side wall insulating films with a bird dose amount which is higher than said first dose amount so as to form an LDD structure . US5898006A CLAIM 2 . The method of manufacturing a semiconductor device according to claim 1 , wherein said step (e) includes : forming other side wall insulating film on side walls of said first and second gates of said first and second MOS transistors for said non-volatile memory element and input protecting element at the same time t (first range) hat said first side wall insulating films are formed on said third MOS transistor for said logic circuit element . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US5898006A CLAIM 1 . A method of manufacturing a semiconductor device including on a single chip a non-volatile memory element , an input protecting element and a logic circuit element , comprising the steps of : (a) forming a first gate of a first MOS transistor for said non-volatile memory element , a second gate of a second MOS transistor for said input protecting element and a third gate of a third MOS transistor for said logic circuit element on a substrate of a first conductivity type ; (b) simultaneously injecting a first impurity of a second conductivity type in said substrate in self-alignment with said first gate of said first MOS transistor for said non-volatile memory element , said second gate of said second MOS transistor for said input protecting element and said third gate of said third MOS transistor for said logic circuit element with a first dose amount ; (c) after said step (b) for a first mask for masking said third MOS transistor for said logic circuit element ; (d) after said step (c) , injecting a second impurity of the second conductivity type in said substrate in self-alignment with said first and second gates of said first MOS transistor for said non-volatile memory and said second MOS transistor for said input protecting element with a second dose amount which is higher than said first dose amount so as to form source and drain regions of said first and second MOS transistors for said non-volatile memory element and input protecting element having single drain structure ; (e) removing said first mask , and forming (anti reflective coating) first side wall insulating films on sidewalls of said third gate of said third MOS transistor for said logic circuit element ; (f) after said step (e) forming a second mask for masking said first and second MOS transistors for said non-volatile memory element and input protecting element ; and (g) injecting a third impurity of the second conductivity type in said source and drain regions of said third MOS transistor for said logic circuit in self-alignment with said third gate and said side wall insulating films with a bird dose amount which is higher than said first dose amount so as to form an LDD structure . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch (non-volatile memory, said sub) stop layer and a second etch stop layer (insulating film) wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub (non-volatile memory, said sub) interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer (insulating film) , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US5898006A CLAIM 1 . A method of manufacturing a semiconductor device including on a single chip a non-volatile memory (first etch, first sub, first space, first etch stop layer) element , an input protecting element and a logic circuit element , comprising the steps of : (a) forming a first gate of a first MOS transistor for said non-volatile memory element , a second gate of a second MOS transistor for said input protecting element and a third gate of a third MOS transistor for said logic circuit element on a substrate of a first conductivity type ; (b) simultaneously injecting a first impurity of a second conductivity type in said sub (first etch, first sub, first space, first etch stop layer) strate in self-alignment with said first gate of said first MOS transistor for said non-volatile memory element , said second gate of said second MOS transistor for said input protecting element and said third gate of said third MOS transistor for said logic circuit element with a first dose amount ; (c) after said step (b) for a first mask for masking said third MOS transistor for said logic circuit element ; (d) after said step (c) , injecting a second impurity of the second conductivity type in said substrate in self-alignment with said first and second gates of said first MOS transistor for said non-volatile memory and said second MOS transistor for said input protecting element with a second dose amount which is higher than said first dose amount so as to form source and drain regions of said first and second MOS transistors for said non-volatile memory element and input protecting element having single drain structure ; (e) removing said first mask , and forming first side wall insulating film (second etch stop layer, second interlevel dielectric layer) s on sidewalls of said third gate of said third MOS transistor for said logic circuit element ; (f) after said step (e) forming a second mask for masking said first and second MOS transistors for said non-volatile memory element and input protecting element ; and (g) injecting a third impurity of the second conductivity type in said source and drain regions of said third MOS transistor for said logic circuit in self-alignment with said third gate and said side wall insulating films with a bird dose amount which is higher than said first dose amount so as to form an LDD structure . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch (non-volatile memory, said sub) stop layer is in a range of about 300 to 800 Šthick , said first sub (non-volatile memory, said sub) interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer (insulating film) is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5898006A CLAIM 1 . A method of manufacturing a semiconductor device including on a single chip a non-volatile memory (first etch, first sub, first space, first etch stop layer) element , an input protecting element and a logic circuit element , comprising the steps of : (a) forming a first gate of a first MOS transistor for said non-volatile memory element , a second gate of a second MOS transistor for said input protecting element and a third gate of a third MOS transistor for said logic circuit element on a substrate of a first conductivity type ; (b) simultaneously injecting a first impurity of a second conductivity type in said sub (first etch, first sub, first space, first etch stop layer) strate in self-alignment with said first gate of said first MOS transistor for said non-volatile memory element , said second gate of said second MOS transistor for said input protecting element and said third gate of said third MOS transistor for said logic circuit element with a first dose amount ; (c) after said step (b) for a first mask for masking said third MOS transistor for said logic circuit element ; (d) after said step (c) , injecting a second impurity of the second conductivity type in said substrate in self-alignment with said first and second gates of said first MOS transistor for said non-volatile memory and said second MOS transistor for said input protecting element with a second dose amount which is higher than said first dose amount so as to form source and drain regions of said first and second MOS transistors for said non-volatile memory element and input protecting element having single drain structure ; (e) removing said first mask , and forming first side wall insulating film (second etch stop layer, second interlevel dielectric layer) s on sidewalls of said third gate of said third MOS transistor for said logic circuit element ; (f) after said step (e) forming a second mask for masking said first and second MOS transistors for said non-volatile memory element and input protecting element ; and (g) injecting a third impurity of the second conductivity type in said source and drain regions of said third MOS transistor for said logic circuit in self-alignment with said third gate and said side wall insulating films with a bird dose amount which is higher than said first dose amount so as to form an LDD structure . |
| US7977797B2 CLAIM 13 . An integrated circuit of claim 11 further comprising a floating gate (drain regions) . |
US5898006A CLAIM 1 . A method of manufacturing a semiconductor device including on a single chip a non-volatile memory element , an input protecting element and a logic circuit element , comprising the steps of : (a) forming a first gate of a first MOS transistor for said non-volatile memory element , a second gate of a second MOS transistor for said input protecting element and a third gate of a third MOS transistor for said logic circuit element on a substrate of a first conductivity type ; (b) simultaneously injecting a first impurity of a second conductivity type in said substrate in self-alignment with said first gate of said first MOS transistor for said non-volatile memory element , said second gate of said second MOS transistor for said input protecting element and said third gate of said third MOS transistor for said logic circuit element with a first dose amount ; (c) after said step (b) for a first mask for masking said third MOS transistor for said logic circuit element ; (d) after said step (c) , injecting a second impurity of the second conductivity type in said substrate in self-alignment with said first and second gates of said first MOS transistor for said non-volatile memory and said second MOS transistor for said input protecting element with a second dose amount which is higher than said first dose amount so as to form source and drain regions (floating gate) of said first and second MOS transistors for said non-volatile memory element and input protecting element having single drain structure ; (e) removing said first mask , and forming first side wall insulating films on sidewalls of said third gate of said third MOS transistor for said logic circuit element ; (f) after said step (e) forming a second mask for masking said first and second MOS transistors for said non-volatile memory element and input protecting element ; and (g) injecting a third impurity of the second conductivity type in said source and drain regions of said third MOS transistor for said logic circuit in self-alignment with said third gate and said side wall insulating films with a bird dose amount which is higher than said first dose amount so as to form an LDD structure . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US5898006A CLAIM 1 . A method of manufacturing a semiconductor device including on a single chip a non-volatile memory element , an input protecting element and a logic circuit element , comprising the steps of : (a) forming a first gate of a first MOS transistor for said non-volatile memory element , a second gate of a second MOS transistor for said input protecting element and a third gate of a third MOS transistor for said logic circuit element on a substrate of a first conductivity type ; (b) simultaneously injecting a first impurity of a second conductivity type in said substrate in self-alignment with said first gate of said first MOS transistor for said non-volatile memory element , said second gate of said second MOS transistor for said input protecting element and said third gate of said third MOS transistor for said logic circuit element with a first dose amount ; (c) after said step (b) for a first mask for masking said third MOS transistor for said logic circuit element ; (d) after said step (c) , injecting a second impurity of the second conductivity type in said substrate in self-alignment with said first and second gates of said first MOS transistor for said non-volatile memory and said second MOS transistor for said input protecting element with a second dose amount which is higher than said first dose amount so as to form source and drain regions of said first and second MOS transistors for said non-volatile memory element and input protecting element having single drain structure ; (e) removing said first mask , and forming (anti reflective coating) first side wall insulating films on sidewalls of said third gate of said third MOS transistor for said logic circuit element ; (f) after said step (e) forming a second mask for masking said first and second MOS transistors for said non-volatile memory element and input protecting element ; and (g) injecting a third impurity of the second conductivity type in said source and drain regions of said third MOS transistor for said logic circuit in self-alignment with said third gate and said side wall insulating films with a bird dose amount which is higher than said first dose amount so as to form an LDD structure . |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region is a first range (time t) of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5898006A CLAIM 2 . The method of manufacturing a semiconductor device according to claim 1 , wherein said step (e) includes : forming other side wall insulating film on side walls of said first and second gates of said first and second MOS transistors for said non-volatile memory element and input protecting element at the same time t (first range) hat said first side wall insulating films are formed on said third MOS transistor for said logic circuit element . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5644166A Filed: 1995-07-17 Issued: 1997-07-01 Sacrificial CVD germanium layer for formation of high aspect ratio submicron VLSI contacts (Original Assignee) Micron Technology Inc (Current Assignee) Micron Technology Inc Jeffrey Honeycutt, Sujit Sharan |
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| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch stop layer protects lower layers during an etching process (high aspect ratio, silicon wafer) . |
US5644166A CLAIM 1 . A high aspect ratio (etching process) submicron VLSI contact on a substrate of a silicon wafer (etching process) , the contact having an opening , a bottom , and a plurality of sides and comprising : a doped active region in said silicon substrate ; an insulating layer on said silicon substrate adjacent to and above said active region ; a region of titanium germanosilicide located above the active region at the bottom of the contact opening ; and a metallization material substantially filling the contact opening : a layer of titanium germanide on the sides of the contact , and an layer of titanium nitride on the layer of titanium germanosilicide and on the layer of titanium germanide . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric (concentration level) layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US5644166A CLAIM 11 . A high aspect ratio submicron VLSI contact on a substrate of a silicon wafer , the contact having an opening , a bottom , and a plurality of sides and comprising : (a) an doped active region in the silicon substrate ; (b) a layer of BPSG adjacent to and above the active region on the silicon substrate ; (c) a region of titanium germanosilicide above the active region on the bottom of the contact , the titanium germosilicide having a thickness of about 75 Angstroms ; (d) a layer of titanium germanide on the sides of the contact , the titanium germanide having a thickness of about 100 Angstroms ; (e) a layer of titanium nitride on the layer of titanium germanosilicide and on the layer of titanium germanide , the layer of titanium nitride having a thickness of about 20 Angstroms ; and (f) a metal material substantially filling the center of the contact opening , wherein the contact opening has an aspect ratio greater than about 2 : 1 , and wherein the layer of germanium has a doping level compatible with the underlying active region whereby the concentration level (second interlevel dielectric, second interlevel dielectric layer) of the dopant in the active region is maintained at a substantially consistent level of concentration . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5589415A Filed: 1995-06-07 Issued: 1996-12-31 Method for forming a semiconductor structure with self-aligned contacts (Original Assignee) SGS Thomson Microelectronics Inc (Current Assignee) STMicroelectronics lnc USA Richard A. Blanchard |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region (interlevel dielectric) such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (thin film) of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (interlevel dielectric) layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5589415A CLAIM 1 . An integrated circuit fabrication method , comprising the steps of : (a .) forming a first patterned thin-film polycrystalline semiconductor layer to provide insulated gates over first and second crystalline semiconductor regions , said second crystalline semiconductor region having a first conductivity type and said first crystalline semiconductor region having a second conductivity type ; (b .) forming an interlevel dielectric (interlevel dielectric, spacer region) over said first patterned thin film (metal layer coupling area) polycrystalline semiconductor layer ; (c .) depositing a second polycrystalline semiconductor layer which at least partly overlies said interlevel dielectric , and patterning said second polycrystalline semiconductor layer to expose first portions , but not second portions , of said first and second crystalline semiconductor regions ; (d .) doping a first portion of said second polycrystalline semiconductor layer with first-conductivity-type dopants , and simultaneously doping any exposed portions of said first crystalline semiconductor regions ; (e .) doping a second portion of said second polycrystalline semiconductor layer with second-conductivity-type dopants , and simultaneously doping said first portions of said second crystalline semiconductor regions ; and (f .) cladding said second polycrystalline semiconductor layer with a cladding layer of metallic conductivity which shunts at least some of the lateral junctions between said first and second portions of said second polycrystalline layer ; whereby said steps c) , d) , and e) create an asymmetrical source/drain structure . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (interlevel dielectric) layer insulates said contact region . |
US5589415A CLAIM 1 . An integrated circuit fabrication method , comprising the steps of : (a . ) forming a first patterned thin-film polycrystalline semiconductor layer to provide insulated gates over first and second crystalline semiconductor regions , said second crystalline semiconductor region having a first conductivity type and said first crystalline semiconductor region having a second conductivity type ; (b . ) forming an interlevel dielectric (interlevel dielectric, spacer region) over said first patterned thin film polycrystalline semiconductor layer ; (c . ) depositing a second polycrystalline semiconductor layer which at least partly overlies said interlevel dielectric , and patterning said second polycrystalline semiconductor layer to expose first portions , but not second portions , of said first and second crystalline semiconductor regions ; (d . ) doping a first portion of said second polycrystalline semiconductor layer with first-conductivity-type dopants , and simultaneously doping any exposed portions of said first crystalline semiconductor regions ; (e . ) doping a second portion of said second polycrystalline semiconductor layer with second-conductivity-type dopants , and simultaneously doping said first portions of said second crystalline semiconductor regions ; and (f . ) cladding said second polycrystalline semiconductor layer with a cladding layer of metallic conductivity which shunts at least some of the lateral junctions between said first and second portions of said second polycrystalline layer ; whereby said steps c) , d) , and e) create an asymmetrical source/drain structure . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (interlevel dielectric) layer insulates said contact region . |
US5589415A CLAIM 1 . An integrated circuit fabrication method , comprising the steps of : (a . ) forming a first patterned thin-film polycrystalline semiconductor layer to provide insulated gates over first and second crystalline semiconductor regions , said second crystalline semiconductor region having a first conductivity type and said first crystalline semiconductor region having a second conductivity type ; (b . ) forming an interlevel dielectric (interlevel dielectric, spacer region) over said first patterned thin film polycrystalline semiconductor layer ; (c . ) depositing a second polycrystalline semiconductor layer which at least partly overlies said interlevel dielectric , and patterning said second polycrystalline semiconductor layer to expose first portions , but not second portions , of said first and second crystalline semiconductor regions ; (d . ) doping a first portion of said second polycrystalline semiconductor layer with first-conductivity-type dopants , and simultaneously doping any exposed portions of said first crystalline semiconductor regions ; (e . ) doping a second portion of said second polycrystalline semiconductor layer with second-conductivity-type dopants , and simultaneously doping said first portions of said second crystalline semiconductor regions ; and (f . ) cladding said second polycrystalline semiconductor layer with a cladding layer of metallic conductivity which shunts at least some of the lateral junctions between said first and second portions of said second polycrystalline layer ; whereby said steps c) , d) , and e) create an asymmetrical source/drain structure . |
| US7977797B2 CLAIM 6 . An integrated circuit of claim 1 wherein said spacer region (interlevel dielectric) insulates said contact region . |
US5589415A CLAIM 1 . An integrated circuit fabrication method , comprising the steps of : (a . ) forming a first patterned thin-film polycrystalline semiconductor layer to provide insulated gates over first and second crystalline semiconductor regions , said second crystalline semiconductor region having a first conductivity type and said first crystalline semiconductor region having a second conductivity type ; (b . ) forming an interlevel dielectric (interlevel dielectric, spacer region) over said first patterned thin film polycrystalline semiconductor layer ; (c . ) depositing a second polycrystalline semiconductor layer which at least partly overlies said interlevel dielectric , and patterning said second polycrystalline semiconductor layer to expose first portions , but not second portions , of said first and second crystalline semiconductor regions ; (d . ) doping a first portion of said second polycrystalline semiconductor layer with first-conductivity-type dopants , and simultaneously doping any exposed portions of said first crystalline semiconductor regions ; (e . ) doping a second portion of said second polycrystalline semiconductor layer with second-conductivity-type dopants , and simultaneously doping said first portions of said second crystalline semiconductor regions ; and (f . ) cladding said second polycrystalline semiconductor layer with a cladding layer of metallic conductivity which shunts at least some of the lateral junctions between said first and second portions of said second polycrystalline layer ; whereby said steps c) , d) , and e) create an asymmetrical source/drain structure . |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area of said contact region permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area (thin film) of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
US5589415A CLAIM 1 . An integrated circuit fabrication method , comprising the steps of : (a . ) forming a first patterned thin-film polycrystalline semiconductor layer to provide insulated gates over first and second crystalline semiconductor regions , said second crystalline semiconductor region having a first conductivity type and said first crystalline semiconductor region having a second conductivity type ; (b . ) forming an interlevel dielectric over said first patterned thin film (metal layer coupling area) polycrystalline semiconductor layer ; (c . ) depositing a second polycrystalline semiconductor layer which at least partly overlies said interlevel dielectric , and patterning said second polycrystalline semiconductor layer to expose first portions , but not second portions , of said first and second crystalline semiconductor regions ; (d . ) doping a first portion of said second polycrystalline semiconductor layer with first-conductivity-type dopants , and simultaneously doping any exposed portions of said first crystalline semiconductor regions ; (e . ) doping a second portion of said second polycrystalline semiconductor layer with second-conductivity-type dopants , and simultaneously doping said first portions of said second crystalline semiconductor regions ; and (f . ) cladding said second polycrystalline semiconductor layer with a cladding layer of metallic conductivity which shunts at least some of the lateral junctions between said first and second portions of said second polycrystalline layer ; whereby said steps c) , d) , and e) create an asymmetrical source/drain structure . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (interlevel dielectric) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5589415A CLAIM 1 . An integrated circuit fabrication method , comprising the steps of : (a . ) forming a first patterned thin-film polycrystalline semiconductor layer to provide insulated gates over first and second crystalline semiconductor regions , said second crystalline semiconductor region having a first conductivity type and said first crystalline semiconductor region having a second conductivity type ; (b . ) forming an interlevel dielectric (interlevel dielectric, spacer region) over said first patterned thin film polycrystalline semiconductor layer ; (c . ) depositing a second polycrystalline semiconductor layer which at least partly overlies said interlevel dielectric , and patterning said second polycrystalline semiconductor layer to expose first portions , but not second portions , of said first and second crystalline semiconductor regions ; (d . ) doping a first portion of said second polycrystalline semiconductor layer with first-conductivity-type dopants , and simultaneously doping any exposed portions of said first crystalline semiconductor regions ; (e . ) doping a second portion of said second polycrystalline semiconductor layer with second-conductivity-type dopants , and simultaneously doping said first portions of said second crystalline semiconductor regions ; and (f . ) cladding said second polycrystalline semiconductor layer with a cladding layer of metallic conductivity which shunts at least some of the lateral junctions between said first and second portions of said second polycrystalline layer ; whereby said steps c) , d) , and e) create an asymmetrical source/drain structure . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric (interlevel dielectric) layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5589415A CLAIM 1 . An integrated circuit fabrication method , comprising the steps of : (a . ) forming a first patterned thin-film polycrystalline semiconductor layer to provide insulated gates over first and second crystalline semiconductor regions , said second crystalline semiconductor region having a first conductivity type and said first crystalline semiconductor region having a second conductivity type ; (b . ) forming an interlevel dielectric (interlevel dielectric, spacer region) over said first patterned thin film polycrystalline semiconductor layer ; (c . ) depositing a second polycrystalline semiconductor layer which at least partly overlies said interlevel dielectric , and patterning said second polycrystalline semiconductor layer to expose first portions , but not second portions , of said first and second crystalline semiconductor regions ; (d . ) doping a first portion of said second polycrystalline semiconductor layer with first-conductivity-type dopants , and simultaneously doping any exposed portions of said first crystalline semiconductor regions ; (e . ) doping a second portion of said second polycrystalline semiconductor layer with second-conductivity-type dopants , and simultaneously doping said first portions of said second crystalline semiconductor regions ; and (f . ) cladding said second polycrystalline semiconductor layer with a cladding layer of metallic conductivity which shunts at least some of the lateral junctions between said first and second portions of said second polycrystalline layer ; whereby said steps c) , d) , and e) create an asymmetrical source/drain structure . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US5589415A CLAIM 9 . An integrated circuit fabrication method , comprising the steps of : (a . ) forming a first patterned thin-film polycrystalline semiconductor layer to provide insulated gates over first and second crystalline semiconductor regions , said second crystalline semiconductor region having a first conductivity type and said first crystalline semiconductor region having a second conductivity type , and forming (anti reflective coating) preliminary diffusions of said first conductivity type in said first crystalline semiconductor region and of said second conductivity type in said second crystal line semiconductor region , said preliminary diffusions being at least partly self-aligned to said first patterned thin-film polycrystalline semiconductor layer ; (b . ) forming a patterned interlevel dielectric over said first patterned thin-film polycrystalline semiconductor layer ; (c . ) depositing a second polycrystalline semiconductor layer which at least partly overlies said interlevel dielectric , and patterning said second polycrystalline semiconductor layer to expose first portions , but not second portions , of said first and second crystalline semiconductor regions ; (d . ) doping a first portion of said second polycrystalline semiconductor layer with first-conductivity-type dopants , and simultaneously doping said first portions of said first crystalline semiconductor regions ; and (e . ) doping a second portion of said second polycrystalline semiconductor layer with second-conductivity-type dopants ; whereby said steps c) , d) , and e) create an asymmetrical source/drain structure . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (interlevel dielectric) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (thin film) of said contact region . |
US5589415A CLAIM 1 . An integrated circuit fabrication method , comprising the steps of : (a . ) forming a first patterned thin-film polycrystalline semiconductor layer to provide insulated gates over first and second crystalline semiconductor regions , said second crystalline semiconductor region having a first conductivity type and said first crystalline semiconductor region having a second conductivity type ; (b . ) forming an interlevel dielectric (interlevel dielectric, spacer region) over said first patterned thin film (metal layer coupling area) polycrystalline semiconductor layer ; (c . ) depositing a second polycrystalline semiconductor layer which at least partly overlies said interlevel dielectric , and patterning said second polycrystalline semiconductor layer to expose first portions , but not second portions , of said first and second crystalline semiconductor regions ; (d . ) doping a first portion of said second polycrystalline semiconductor layer with first-conductivity-type dopants , and simultaneously doping any exposed portions of said first crystalline semiconductor regions ; (e . ) doping a second portion of said second polycrystalline semiconductor layer with second-conductivity-type dopants , and simultaneously doping said first portions of said second crystalline semiconductor regions ; and (f . ) cladding said second polycrystalline semiconductor layer with a cladding layer of metallic conductivity which shunts at least some of the lateral junctions between said first and second portions of said second polycrystalline layer ; whereby said steps c) , d) , and e) create an asymmetrical source/drain structure . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (interlevel dielectric) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5589415A CLAIM 1 . An integrated circuit fabrication method , comprising the steps of : (a . ) forming a first patterned thin-film polycrystalline semiconductor layer to provide insulated gates over first and second crystalline semiconductor regions , said second crystalline semiconductor region having a first conductivity type and said first crystalline semiconductor region having a second conductivity type ; (b . ) forming an interlevel dielectric (interlevel dielectric, spacer region) over said first patterned thin film polycrystalline semiconductor layer ; (c . ) depositing a second polycrystalline semiconductor layer which at least partly overlies said interlevel dielectric , and patterning said second polycrystalline semiconductor layer to expose first portions , but not second portions , of said first and second crystalline semiconductor regions ; (d . ) doping a first portion of said second polycrystalline semiconductor layer with first-conductivity-type dopants , and simultaneously doping any exposed portions of said first crystalline semiconductor regions ; (e . ) doping a second portion of said second polycrystalline semiconductor layer with second-conductivity-type dopants , and simultaneously doping said first portions of said second crystalline semiconductor regions ; and (f . ) cladding said second polycrystalline semiconductor layer with a cladding layer of metallic conductivity which shunts at least some of the lateral junctions between said first and second portions of said second polycrystalline layer ; whereby said steps c) , d) , and e) create an asymmetrical source/drain structure . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US5589415A CLAIM 9 . An integrated circuit fabrication method , comprising the steps of : (a . ) forming a first patterned thin-film polycrystalline semiconductor layer to provide insulated gates over first and second crystalline semiconductor regions , said second crystalline semiconductor region having a first conductivity type and said first crystalline semiconductor region having a second conductivity type , and forming (anti reflective coating) preliminary diffusions of said first conductivity type in said first crystalline semiconductor region and of said second conductivity type in said second crystal line semiconductor region , said preliminary diffusions being at least partly self-aligned to said first patterned thin-film polycrystalline semiconductor layer ; (b . ) forming a patterned interlevel dielectric over said first patterned thin-film polycrystalline semiconductor layer ; (c . ) depositing a second polycrystalline semiconductor layer which at least partly overlies said interlevel dielectric , and patterning said second polycrystalline semiconductor layer to expose first portions , but not second portions , of said first and second crystalline semiconductor regions ; (d . ) doping a first portion of said second polycrystalline semiconductor layer with first-conductivity-type dopants , and simultaneously doping said first portions of said first crystalline semiconductor regions ; and (e . ) doping a second portion of said second polycrystalline semiconductor layer with second-conductivity-type dopants ; whereby said steps c) , d) , and e) create an asymmetrical source/drain structure . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5612574A Filed: 1995-06-06 Issued: 1997-03-18 Semiconductor structures using high-dielectric-constant materials and an adhesion layer (Original Assignee) Texas Instruments Inc (Current Assignee) Texas Instruments Inc Scott R. Summerfelt, Howard R. Beratan |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch (tungsten nitride) stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer (zirconium nitride) over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub (electronic device) interlevel dielectric layer over said second etch stop layer . |
US5612574A CLAIM 6 . The device of claim 1 , wherein the conductive plug comprises a material selected from the group of materials consisting of poly-crystalline silicon which has been doped to be rendered conductive , titanium nitride , titanium silicide , zirconium nitride (second etch stop layer) , tantalum silicide , tungsten silicide , molybdenum silicide , nickel silicide , tantalum carbide , titanium boride , single-crystal silicon doped to be rendered conductive , germanium doped to be rendered conductive , tungsten , tantalum , titanium , aluminum molybdenum , boron carbide , gallium arsenide , and indium phosphide . US5612574A CLAIM 9 . The device of claim 7 , wherein the outer electrode comprises a material selected from the group consisting of platinum , palladium , ruthenium , rhodium , gold , iridium , silver , titanium nitride , ruthenium nitride , tin nitride , zirconium nitride , tungsten nitride (multiple etch) , ruthenium dioxide , tin oxide , zinc oxide , doped zinc oxide , iridium oxide , titanium silicide , tantalum silicide , tungsten silicide , molybdenum silicide , nickel silicide , tantalum carbide , titanium boride , tantalum titanium molybdenum , tungsten , aluminum , doped silicon , and doped germanium . US5612574A CLAIM 16 . The electronic device (second sub) of claim 10 , wherein the sidewall isolation ring comprises : a material selected from the group consisting of silicon dioxide and silicon nitride . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch stop layer (zirconium nitride) protects lower layers during an etching process . |
US5612574A CLAIM 6 . The device of claim 1 , wherein the conductive plug comprises a material selected from the group of materials consisting of poly-crystalline silicon which has been doped to be rendered conductive , titanium nitride , titanium silicide , zirconium nitride (second etch stop layer) , tantalum silicide , tungsten silicide , molybdenum silicide , nickel silicide , tantalum carbide , titanium boride , single-crystal silicon doped to be rendered conductive , germanium doped to be rendered conductive , tungsten , tantalum , titanium , aluminum molybdenum , boron carbide , gallium arsenide , and indium phosphide . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub (electronic device) interlevel dielectric layer insulates said contact region . |
US5612574A CLAIM 16 . The electronic device (second sub) of claim 10 , wherein the sidewall isolation ring comprises : a material selected from the group consisting of silicon dioxide and silicon nitride . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer (zirconium nitride) is in a range of about 300 to 800 Šthick and said second sub (electronic device) interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5612574A CLAIM 6 . The device of claim 1 , wherein the conductive plug comprises a material selected from the group of materials consisting of poly-crystalline silicon which has been doped to be rendered conductive , titanium nitride , titanium silicide , zirconium nitride (second etch stop layer) , tantalum silicide , tungsten silicide , molybdenum silicide , nickel silicide , tantalum carbide , titanium boride , single-crystal silicon doped to be rendered conductive , germanium doped to be rendered conductive , tungsten , tantalum , titanium , aluminum molybdenum , boron carbide , gallium arsenide , and indium phosphide . US5612574A CLAIM 16 . The electronic device (second sub) of claim 10 , wherein the sidewall isolation ring comprises : a material selected from the group consisting of silicon dioxide and silicon nitride . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub (electronic device) interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5612574A CLAIM 16 . The electronic device (second sub) of claim 10 , wherein the sidewall isolation ring comprises : a material selected from the group consisting of silicon dioxide and silicon nitride . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch (tungsten nitride) stop insulation layer comprising a first etch stop layer and a second etch stop layer (zirconium nitride) wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub (electronic device) interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US5612574A CLAIM 6 . The device of claim 1 , wherein the conductive plug comprises a material selected from the group of materials consisting of poly-crystalline silicon which has been doped to be rendered conductive , titanium nitride , titanium silicide , zirconium nitride (second etch stop layer) , tantalum silicide , tungsten silicide , molybdenum silicide , nickel silicide , tantalum carbide , titanium boride , single-crystal silicon doped to be rendered conductive , germanium doped to be rendered conductive , tungsten , tantalum , titanium , aluminum molybdenum , boron carbide , gallium arsenide , and indium phosphide . US5612574A CLAIM 9 . The device of claim 7 , wherein the outer electrode comprises a material selected from the group consisting of platinum , palladium , ruthenium , rhodium , gold , iridium , silver , titanium nitride , ruthenium nitride , tin nitride , zirconium nitride , tungsten nitride (multiple etch) , ruthenium dioxide , tin oxide , zinc oxide , doped zinc oxide , iridium oxide , titanium silicide , tantalum silicide , tungsten silicide , molybdenum silicide , nickel silicide , tantalum carbide , titanium boride , tantalum titanium molybdenum , tungsten , aluminum , doped silicon , and doped germanium . US5612574A CLAIM 16 . The electronic device (second sub) of claim 10 , wherein the sidewall isolation ring comprises : a material selected from the group consisting of silicon dioxide and silicon nitride . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer (zirconium nitride) is in a range of about 300 to 800 Šthick and said second sub (electronic device) interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5612574A CLAIM 6 . The device of claim 1 , wherein the conductive plug comprises a material selected from the group of materials consisting of poly-crystalline silicon which has been doped to be rendered conductive , titanium nitride , titanium silicide , zirconium nitride (second etch stop layer) , tantalum silicide , tungsten silicide , molybdenum silicide , nickel silicide , tantalum carbide , titanium boride , single-crystal silicon doped to be rendered conductive , germanium doped to be rendered conductive , tungsten , tantalum , titanium , aluminum molybdenum , boron carbide , gallium arsenide , and indium phosphide . US5612574A CLAIM 16 . The electronic device (second sub) of claim 10 , wherein the sidewall isolation ring comprises : a material selected from the group consisting of silicon dioxide and silicon nitride . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5596221A Filed: 1995-06-05 Issued: 1997-01-21 Bipolar transistor with emitter double contact structure (Original Assignee) Mitsubishi Electric Corp (Current Assignee) Mitsubishi Electric Corp Hiroki Honda |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region (second contact) coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (barrier layers) of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5596221A CLAIM 11 . A bipolar transistor comprising : a semiconductor substrate of a first conductivity type having a main surface , a collector region of a second conductivity type formed at the main surface of said semiconductor substrate , a base region of the first conductivity type formed at a surface of said collector region , an emitter region of the second conductivity type formed at a surface of said base region , an insulation layer formed on the main surface of said semiconductor substrate , having a first contact hole on a surface of said emitter region , a second contact (contact region) hole on a surface of said base region , and a third contact hole on a surface of said collector region , a polycrystalline silicon layer formed within said insulation layer and having a hole defining a portion of said first contact hole and forming a contact with a surface of said emitter region , a first metal electrode formed within said first contact hole so as to provide contact with a surface of said emitter region , a second metal electrode formed within said second contact hole , and a third metal electrode formed within said third contact hole . US5596221A CLAIM 15 . The bipolar transistor according to claim 14 , wherein said first , second and third silicide layers comprise titanium silicide layers , and said first , second and third barrier layers (metal layer coupling area) comprise titanium nitride layers . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric layer insulates said contact region (second contact) . |
US5596221A CLAIM 11 . A bipolar transistor comprising : a semiconductor substrate of a first conductivity type having a main surface , a collector region of a second conductivity type formed at the main surface of said semiconductor substrate , a base region of the first conductivity type formed at a surface of said collector region , an emitter region of the second conductivity type formed at a surface of said base region , an insulation layer formed on the main surface of said semiconductor substrate , having a first contact hole on a surface of said emitter region , a second contact (contact region) hole on a surface of said base region , and a third contact hole on a surface of said collector region , a polycrystalline silicon layer formed within said insulation layer and having a hole defining a portion of said first contact hole and forming a contact with a surface of said emitter region , a first metal electrode formed within said first contact hole so as to provide contact with a surface of said emitter region , a second metal electrode formed within said second contact hole , and a third metal electrode formed within said third contact hole . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric layer insulates said contact region (second contact) . |
US5596221A CLAIM 11 . A bipolar transistor comprising : a semiconductor substrate of a first conductivity type having a main surface , a collector region of a second conductivity type formed at the main surface of said semiconductor substrate , a base region of the first conductivity type formed at a surface of said collector region , an emitter region of the second conductivity type formed at a surface of said base region , an insulation layer formed on the main surface of said semiconductor substrate , having a first contact hole on a surface of said emitter region , a second contact (contact region) hole on a surface of said base region , and a third contact hole on a surface of said collector region , a polycrystalline silicon layer formed within said insulation layer and having a hole defining a portion of said first contact hole and forming a contact with a surface of said emitter region , a first metal electrode formed within said first contact hole so as to provide contact with a surface of said emitter region , a second metal electrode formed within said second contact hole , and a third metal electrode formed within said third contact hole . |
| US7977797B2 CLAIM 6 . An integrated circuit of claim 1 wherein said spacer region insulates said contact region (second contact) . |
US5596221A CLAIM 11 . A bipolar transistor comprising : a semiconductor substrate of a first conductivity type having a main surface , a collector region of a second conductivity type formed at the main surface of said semiconductor substrate , a base region of the first conductivity type formed at a surface of said collector region , an emitter region of the second conductivity type formed at a surface of said base region , an insulation layer formed on the main surface of said semiconductor substrate , having a first contact hole on a surface of said emitter region , a second contact (contact region) hole on a surface of said base region , and a third contact hole on a surface of said collector region , a polycrystalline silicon layer formed within said insulation layer and having a hole defining a portion of said first contact hole and forming a contact with a surface of said emitter region , a first metal electrode formed within said first contact hole so as to provide contact with a surface of said emitter region , a second metal electrode formed within said second contact hole , and a third metal electrode formed within said third contact hole . |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area of said contact region (second contact) permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area (barrier layers) of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
US5596221A CLAIM 11 . A bipolar transistor comprising : a semiconductor substrate of a first conductivity type having a main surface , a collector region of a second conductivity type formed at the main surface of said semiconductor substrate , a base region of the first conductivity type formed at a surface of said collector region , an emitter region of the second conductivity type formed at a surface of said base region , an insulation layer formed on the main surface of said semiconductor substrate , having a first contact hole on a surface of said emitter region , a second contact (contact region) hole on a surface of said base region , and a third contact hole on a surface of said collector region , a polycrystalline silicon layer formed within said insulation layer and having a hole defining a portion of said first contact hole and forming a contact with a surface of said emitter region , a first metal electrode formed within said first contact hole so as to provide contact with a surface of said emitter region , a second metal electrode formed within said second contact hole , and a third metal electrode formed within said third contact hole . US5596221A CLAIM 15 . The bipolar transistor according to claim 14 , wherein said first , second and third silicide layers comprise titanium silicide layers , and said first , second and third barrier layers (metal layer coupling area) comprise titanium nitride layers . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric layer for said contact region (second contact) is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5596221A CLAIM 11 . A bipolar transistor comprising : a semiconductor substrate of a first conductivity type having a main surface , a collector region of a second conductivity type formed at the main surface of said semiconductor substrate , a base region of the first conductivity type formed at a surface of said collector region , an emitter region of the second conductivity type formed at a surface of said base region , an insulation layer formed on the main surface of said semiconductor substrate , having a first contact hole on a surface of said emitter region , a second contact (contact region) hole on a surface of said base region , and a third contact hole on a surface of said collector region , a polycrystalline silicon layer formed within said insulation layer and having a hole defining a portion of said first contact hole and forming a contact with a surface of said emitter region , a first metal electrode formed within said first contact hole so as to provide contact with a surface of said emitter region , a second metal electrode formed within said second contact hole , and a third metal electrode formed within said third contact hole . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US5596221A CLAIM 11 . A bipolar transistor comprising : a semiconductor substrate of a first conductivity type having a main surface , a collector region of a second conductivity type formed at the main surface of said semiconductor substrate , a base region of the first conductivity type formed at a surface of said collector region , an emitter region of the second conductivity type formed at a surface of said base region , an insulation layer formed on the main surface of said semiconductor substrate , having a first contact hole on a surface of said emitter region , a second contact hole on a surface of said base region , and a third contact hole on a surface of said collector region , a polycrystalline silicon layer formed within said insulation layer and having a hole defining a portion of said first contact hole and forming (anti reflective coating) a contact with a surface of said emitter region , a first metal electrode formed within said first contact hole so as to provide contact with a surface of said emitter region , a second metal electrode formed within said second contact hole , and a third metal electrode formed within said third contact hole . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region (second contact) and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (barrier layers) of said contact region . |
US5596221A CLAIM 11 . A bipolar transistor comprising : a semiconductor substrate of a first conductivity type having a main surface , a collector region of a second conductivity type formed at the main surface of said semiconductor substrate , a base region of the first conductivity type formed at a surface of said collector region , an emitter region of the second conductivity type formed at a surface of said base region , an insulation layer formed on the main surface of said semiconductor substrate , having a first contact hole on a surface of said emitter region , a second contact (contact region) hole on a surface of said base region , and a third contact hole on a surface of said collector region , a polycrystalline silicon layer formed within said insulation layer and having a hole defining a portion of said first contact hole and forming a contact with a surface of said emitter region , a first metal electrode formed within said first contact hole so as to provide contact with a surface of said emitter region , a second metal electrode formed within said second contact hole , and a third metal electrode formed within said third contact hole . US5596221A CLAIM 15 . The bipolar transistor according to claim 14 , wherein said first , second and third silicide layers comprise titanium silicide layers , and said first , second and third barrier layers (metal layer coupling area) comprise titanium nitride layers . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US5596221A CLAIM 11 . A bipolar transistor comprising : a semiconductor substrate of a first conductivity type having a main surface , a collector region of a second conductivity type formed at the main surface of said semiconductor substrate , a base region of the first conductivity type formed at a surface of said collector region , an emitter region of the second conductivity type formed at a surface of said base region , an insulation layer formed on the main surface of said semiconductor substrate , having a first contact hole on a surface of said emitter region , a second contact hole on a surface of said base region , and a third contact hole on a surface of said collector region , a polycrystalline silicon layer formed within said insulation layer and having a hole defining a portion of said first contact hole and forming (anti reflective coating) a contact with a surface of said emitter region , a first metal electrode formed within said first contact hole so as to provide contact with a surface of said emitter region , a second metal electrode formed within said second contact hole , and a third metal electrode formed within said third contact hole . |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region (second contact) is a first range of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5596221A CLAIM 11 . A bipolar transistor comprising : a semiconductor substrate of a first conductivity type having a main surface , a collector region of a second conductivity type formed at the main surface of said semiconductor substrate , a base region of the first conductivity type formed at a surface of said collector region , an emitter region of the second conductivity type formed at a surface of said base region , an insulation layer formed on the main surface of said semiconductor substrate , having a first contact hole on a surface of said emitter region , a second contact (contact region) hole on a surface of said base region , and a third contact hole on a surface of said collector region , a polycrystalline silicon layer formed within said insulation layer and having a hole defining a portion of said first contact hole and forming a contact with a surface of said emitter region , a first metal electrode formed within said first contact hole so as to provide contact with a surface of said emitter region , a second metal electrode formed within said second contact hole , and a third metal electrode formed within said third contact hole . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5504038A Filed: 1995-05-25 Issued: 1996-04-02 Method for selective tungsten sidewall and bottom contact formation (Original Assignee) United Microelectronics Corp (Current Assignee) United Microelectronics Corp Sun-Chieh Chien, Jengping Lin |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (vertical sidewalls) layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5504038A CLAIM 1 . A method of forming an electrical interconnection for a multi-layer semiconductor circuit , the method comprising the steps of : forming a dielectric layer on a substrate ; etching a contact hole through said dielectric layer , said contact hole defined by substantially vertical sidewalls (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) of said dielectric layer and a bottom contact surface of the substrate ; forming a silicon oxide layer on said bottom contact surface ; depositing a silicon polysilicon layer on the substrate surface ; etching the polysilicon layer to form polysilicon sidewall spacers on said sidewalls and exposing portions of said silicon oxide layer on the bottom contact surface ; removing the exposed portions of said silicon oxide layer on said bottom contact surface ; depositing a metal layer on said spacers , on said bottom contact surface and on said dielectric layer ; forming a metal silicide layer and a first metal nitride layer on at least said spacers and said bottom contact surface by reacting said metal layer with said polysilicon layer and said bottom contact surface ; removing the first metal nitride layer and the remaining unreacted metal layer ; and filling only the contact hole with tungsten so that the tungsten forms electrical contact with the bottom surface without forming tungsten on other surfaces , thus forming the electrical interconnection of the invention . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer protects removal of a substrate material by an etch process (silicon oxide layer) . |
US5504038A CLAIM 1 . A method of forming an electrical interconnection for a multi-layer semiconductor circuit , the method comprising the steps of : forming a dielectric layer on a substrate ; etching a contact hole through said dielectric layer , said contact hole defined by substantially vertical sidewalls of said dielectric layer and a bottom contact surface of the substrate ; forming a silicon oxide layer (etch process) on said bottom contact surface ; depositing a silicon polysilicon layer on the substrate surface ; etching the polysilicon layer to form polysilicon sidewall spacers on said sidewalls and exposing portions of said silicon oxide layer on the bottom contact surface ; removing the exposed portions of said silicon oxide layer on said bottom contact surface ; depositing a metal layer on said spacers , on said bottom contact surface and on said dielectric layer ; forming a metal silicide layer and a first metal nitride layer on at least said spacers and said bottom contact surface by reacting said metal layer with said polysilicon layer and said bottom contact surface ; removing the first metal nitride layer and the remaining unreacted metal layer ; and filling only the contact hole with tungsten so that the tungsten forms electrical contact with the bottom surface without forming tungsten on other surfaces , thus forming the electrical interconnection of the invention . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (vertical sidewalls) layer insulates said contact region . |
US5504038A CLAIM 1 . A method of forming an electrical interconnection for a multi-layer semiconductor circuit , the method comprising the steps of : forming a dielectric layer on a substrate ; etching a contact hole through said dielectric layer , said contact hole defined by substantially vertical sidewalls (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) of said dielectric layer and a bottom contact surface of the substrate ; forming a silicon oxide layer on said bottom contact surface ; depositing a silicon polysilicon layer on the substrate surface ; etching the polysilicon layer to form polysilicon sidewall spacers on said sidewalls and exposing portions of said silicon oxide layer on the bottom contact surface ; removing the exposed portions of said silicon oxide layer on said bottom contact surface ; depositing a metal layer on said spacers , on said bottom contact surface and on said dielectric layer ; forming a metal silicide layer and a first metal nitride layer on at least said spacers and said bottom contact surface by reacting said metal layer with said polysilicon layer and said bottom contact surface ; removing the first metal nitride layer and the remaining unreacted metal layer ; and filling only the contact hole with tungsten so that the tungsten forms electrical contact with the bottom surface without forming tungsten on other surfaces , thus forming the electrical interconnection of the invention . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (vertical sidewalls) layer insulates said contact region . |
US5504038A CLAIM 1 . A method of forming an electrical interconnection for a multi-layer semiconductor circuit , the method comprising the steps of : forming a dielectric layer on a substrate ; etching a contact hole through said dielectric layer , said contact hole defined by substantially vertical sidewalls (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) of said dielectric layer and a bottom contact surface of the substrate ; forming a silicon oxide layer on said bottom contact surface ; depositing a silicon polysilicon layer on the substrate surface ; etching the polysilicon layer to form polysilicon sidewall spacers on said sidewalls and exposing portions of said silicon oxide layer on the bottom contact surface ; removing the exposed portions of said silicon oxide layer on said bottom contact surface ; depositing a metal layer on said spacers , on said bottom contact surface and on said dielectric layer ; forming a metal silicide layer and a first metal nitride layer on at least said spacers and said bottom contact surface by reacting said metal layer with said polysilicon layer and said bottom contact surface ; removing the first metal nitride layer and the remaining unreacted metal layer ; and filling only the contact hole with tungsten so that the tungsten forms electrical contact with the bottom surface without forming tungsten on other surfaces , thus forming the electrical interconnection of the invention . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (vertical sidewalls) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5504038A CLAIM 1 . A method of forming an electrical interconnection for a multi-layer semiconductor circuit , the method comprising the steps of : forming a dielectric layer on a substrate ; etching a contact hole through said dielectric layer , said contact hole defined by substantially vertical sidewalls (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) of said dielectric layer and a bottom contact surface of the substrate ; forming a silicon oxide layer on said bottom contact surface ; depositing a silicon polysilicon layer on the substrate surface ; etching the polysilicon layer to form polysilicon sidewall spacers on said sidewalls and exposing portions of said silicon oxide layer on the bottom contact surface ; removing the exposed portions of said silicon oxide layer on said bottom contact surface ; depositing a metal layer on said spacers , on said bottom contact surface and on said dielectric layer ; forming a metal silicide layer and a first metal nitride layer on at least said spacers and said bottom contact surface by reacting said metal layer with said polysilicon layer and said bottom contact surface ; removing the first metal nitride layer and the remaining unreacted metal layer ; and filling only the contact hole with tungsten so that the tungsten forms electrical contact with the bottom surface without forming tungsten on other surfaces , thus forming the electrical interconnection of the invention . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric (vertical sidewalls) layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5504038A CLAIM 1 . A method of forming an electrical interconnection for a multi-layer semiconductor circuit , the method comprising the steps of : forming a dielectric layer on a substrate ; etching a contact hole through said dielectric layer , said contact hole defined by substantially vertical sidewalls (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) of said dielectric layer and a bottom contact surface of the substrate ; forming a silicon oxide layer on said bottom contact surface ; depositing a silicon polysilicon layer on the substrate surface ; etching the polysilicon layer to form polysilicon sidewall spacers on said sidewalls and exposing portions of said silicon oxide layer on the bottom contact surface ; removing the exposed portions of said silicon oxide layer on said bottom contact surface ; depositing a metal layer on said spacers , on said bottom contact surface and on said dielectric layer ; forming a metal silicide layer and a first metal nitride layer on at least said spacers and said bottom contact surface by reacting said metal layer with said polysilicon layer and said bottom contact surface ; removing the first metal nitride layer and the remaining unreacted metal layer ; and filling only the contact hole with tungsten so that the tungsten forms electrical contact with the bottom surface without forming tungsten on other surfaces , thus forming the electrical interconnection of the invention . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (vertical sidewalls) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US5504038A CLAIM 1 . A method of forming an electrical interconnection for a multi-layer semiconductor circuit , the method comprising the steps of : forming a dielectric layer on a substrate ; etching a contact hole through said dielectric layer , said contact hole defined by substantially vertical sidewalls (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) of said dielectric layer and a bottom contact surface of the substrate ; forming a silicon oxide layer on said bottom contact surface ; depositing a silicon polysilicon layer on the substrate surface ; etching the polysilicon layer to form polysilicon sidewall spacers on said sidewalls and exposing portions of said silicon oxide layer on the bottom contact surface ; removing the exposed portions of said silicon oxide layer on said bottom contact surface ; depositing a metal layer on said spacers , on said bottom contact surface and on said dielectric layer ; forming a metal silicide layer and a first metal nitride layer on at least said spacers and said bottom contact surface by reacting said metal layer with said polysilicon layer and said bottom contact surface ; removing the first metal nitride layer and the remaining unreacted metal layer ; and filling only the contact hole with tungsten so that the tungsten forms electrical contact with the bottom surface without forming tungsten on other surfaces , thus forming the electrical interconnection of the invention . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (vertical sidewalls) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5504038A CLAIM 1 . A method of forming an electrical interconnection for a multi-layer semiconductor circuit , the method comprising the steps of : forming a dielectric layer on a substrate ; etching a contact hole through said dielectric layer , said contact hole defined by substantially vertical sidewalls (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) of said dielectric layer and a bottom contact surface of the substrate ; forming a silicon oxide layer on said bottom contact surface ; depositing a silicon polysilicon layer on the substrate surface ; etching the polysilicon layer to form polysilicon sidewall spacers on said sidewalls and exposing portions of said silicon oxide layer on the bottom contact surface ; removing the exposed portions of said silicon oxide layer on said bottom contact surface ; depositing a metal layer on said spacers , on said bottom contact surface and on said dielectric layer ; forming a metal silicide layer and a first metal nitride layer on at least said spacers and said bottom contact surface by reacting said metal layer with said polysilicon layer and said bottom contact surface ; removing the first metal nitride layer and the remaining unreacted metal layer ; and filling only the contact hole with tungsten so that the tungsten forms electrical contact with the bottom surface without forming tungsten on other surfaces , thus forming the electrical interconnection of the invention . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5841195A Filed: 1995-05-24 Issued: 1998-11-24 Semiconductor contact via structure (Original Assignee) STMicroelectronics lnc USA (Current Assignee) STMicroelectronics lnc USA Yih-Shung Lin, Lun-Tseng Lu, Fu-Tai Liou, Che-Chia Wei, John Leonard Walters |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch (first etch) stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (vertical sidewalls) layer over said first etch stop layer ; a second etch (second etch) stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5841195A CLAIM 1 . A via structure in an integrated circuit comprising : a base layer ; an undoped oxide layer overlying and in contact with the base layer ; a planarization layer of a planarizing material overlying the undoped oxide layer ; a first buffer layer overlying said planarization layer , the first buffer layer having a first level of dopants therein ; a second buffer layer overlying the first buffer layer at a buffer junction , the second buffer layer having a second level of dopants therein , the second level of dopants in the second buffer layer being substantially higher than the first level of dopants in the first buffer layer , and the first and second levels of dopants being unequal at the buffer junction ; an opening extending through the first buffer layer , the second buffer layer , the planarization layer and the undoped oxide layer , the opening exposing a portion of the base layer and the opening having an upper region at the first and second buffer layers having a gradually increasing diameter caused by the first and second buffer layers having a sloped profile at a less inclined angle (first sub interlevel dielectric layer) than the profile of the opening of said undoped oxide layer and said planarization layer ; and a conductive layer overlying portions of the second buffer layer and extending into the opening , and making electrical contact with the base layer . US5841195A CLAIM 3 . The via structure of claim 1 , wherein the opening has a lower portion adjacent to the planarization layer and wherein the lower portion of the opening has substantially vertical sidewalls (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) . US5841195A CLAIM 17 . In an integrated circuit , a via structure comprising : a substrate ; an insulating layer partially covering the substrate ; a first etch (first etch) ing layer covering the insulating layer , the first etching layer doped with a first concentration of dopant and etchable throughout the entire first layer at a first rate ; a second etch (second etch) ing layer covering a portion of the first etching layer , the second etching layer doped with a second concentration of dopant and etchable throughout the entire second etching layer at a second rate , the second rate being faster than the first rate ; an opening through the insulating layer and the first and second etching layers , the opening being substantially vertical through the insulating layer and being less vertical through the etching layers ; and a connection layer substantially filling the opening and contacting the substrate , insulating layer , and etching layers . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch (first etch) stop layer protects removal of a substrate material by an etch process . |
US5841195A CLAIM 17 . In an integrated circuit , a via structure comprising : a substrate ; an insulating layer partially covering the substrate ; a first etch (first etch) ing layer covering the insulating layer , the first etching layer doped with a first concentration of dopant and etchable throughout the entire first layer at a first rate ; a second etching layer covering a portion of the first etching layer , the second etching layer doped with a second concentration of dopant and etchable throughout the entire second etching layer at a second rate , the second rate being faster than the first rate ; an opening through the insulating layer and the first and second etching layers , the opening being substantially vertical through the insulating layer and being less vertical through the etching layers ; and a connection layer substantially filling the opening and contacting the substrate , insulating layer , and etching layers . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (vertical sidewalls) layer insulates said contact region . |
US5841195A CLAIM 1 . A via structure in an integrated circuit comprising : a base layer ; an undoped oxide layer overlying and in contact with the base layer ; a planarization layer of a planarizing material overlying the undoped oxide layer ; a first buffer layer overlying said planarization layer , the first buffer layer having a first level of dopants therein ; a second buffer layer overlying the first buffer layer at a buffer junction , the second buffer layer having a second level of dopants therein , the second level of dopants in the second buffer layer being substantially higher than the first level of dopants in the first buffer layer , and the first and second levels of dopants being unequal at the buffer junction ; an opening extending through the first buffer layer , the second buffer layer , the planarization layer and the undoped oxide layer , the opening exposing a portion of the base layer and the opening having an upper region at the first and second buffer layers having a gradually increasing diameter caused by the first and second buffer layers having a sloped profile at a less inclined angle (first sub interlevel dielectric layer) than the profile of the opening of said undoped oxide layer and said planarization layer ; and a conductive layer overlying portions of the second buffer layer and extending into the opening , and making electrical contact with the base layer . US5841195A CLAIM 3 . The via structure of claim 1 , wherein the opening has a lower portion adjacent to the planarization layer and wherein the lower portion of the opening has substantially vertical sidewalls (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch (second etch) stop layer protects lower layers during an etching process (planarization layer) . |
US5841195A CLAIM 1 . A via structure in an integrated circuit comprising : a base layer ; an undoped oxide layer overlying and in contact with the base layer ; a planarization layer (etching process) of a planarizing material overlying the undoped oxide layer ; a first buffer layer overlying said planarization layer , the first buffer layer having a first level of dopants therein ; a second buffer layer overlying the first buffer layer at a buffer junction , the second buffer layer having a second level of dopants therein , the second level of dopants in the second buffer layer being substantially higher than the first level of dopants in the first buffer layer , and the first and second levels of dopants being unequal at the buffer junction ; an opening extending through the first buffer layer , the second buffer layer , the planarization layer and the undoped oxide layer , the opening exposing a portion of the base layer and the opening having an upper region at the first and second buffer layers having a gradually increasing diameter caused by the first and second buffer layers having a sloped profile at a less inclined angle than the profile of the opening of said undoped oxide layer and said planarization layer ; and a conductive layer overlying portions of the second buffer layer and extending into the opening , and making electrical contact with the base layer . US5841195A CLAIM 17 . In an integrated circuit , a via structure comprising : a substrate ; an insulating layer partially covering the substrate ; a first etching layer covering the insulating layer , the first etching layer doped with a first concentration of dopant and etchable throughout the entire first layer at a first rate ; a second etch (second etch) ing layer covering a portion of the first etching layer , the second etching layer doped with a second concentration of dopant and etchable throughout the entire second etching layer at a second rate , the second rate being faster than the first rate ; an opening through the insulating layer and the first and second etching layers , the opening being substantially vertical through the insulating layer and being less vertical through the etching layers ; and a connection layer substantially filling the opening and contacting the substrate , insulating layer , and etching layers . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (vertical sidewalls) layer insulates said contact region . |
US5841195A CLAIM 3 . The via structure of claim 1 , wherein the opening has a lower portion adjacent to the planarization layer and wherein the lower portion of the opening has substantially vertical sidewalls (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch (first etch) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (vertical sidewalls) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (second etch) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5841195A CLAIM 1 . A via structure in an integrated circuit comprising : a base layer ; an undoped oxide layer overlying and in contact with the base layer ; a planarization layer of a planarizing material overlying the undoped oxide layer ; a first buffer layer overlying said planarization layer , the first buffer layer having a first level of dopants therein ; a second buffer layer overlying the first buffer layer at a buffer junction , the second buffer layer having a second level of dopants therein , the second level of dopants in the second buffer layer being substantially higher than the first level of dopants in the first buffer layer , and the first and second levels of dopants being unequal at the buffer junction ; an opening extending through the first buffer layer , the second buffer layer , the planarization layer and the undoped oxide layer , the opening exposing a portion of the base layer and the opening having an upper region at the first and second buffer layers having a gradually increasing diameter caused by the first and second buffer layers having a sloped profile at a less inclined angle (first sub interlevel dielectric layer) than the profile of the opening of said undoped oxide layer and said planarization layer ; and a conductive layer overlying portions of the second buffer layer and extending into the opening , and making electrical contact with the base layer . US5841195A CLAIM 3 . The via structure of claim 1 , wherein the opening has a lower portion adjacent to the planarization layer and wherein the lower portion of the opening has substantially vertical sidewalls (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) . US5841195A CLAIM 17 . In an integrated circuit , a via structure comprising : a substrate ; an insulating layer partially covering the substrate ; a first etch (first etch) ing layer covering the insulating layer , the first etching layer doped with a first concentration of dopant and etchable throughout the entire first layer at a first rate ; a second etch (second etch) ing layer covering a portion of the first etching layer , the second etching layer doped with a second concentration of dopant and etchable throughout the entire second etching layer at a second rate , the second rate being faster than the first rate ; an opening through the insulating layer and the first and second etching layers , the opening being substantially vertical through the insulating layer and being less vertical through the etching layers ; and a connection layer substantially filling the opening and contacting the substrate , insulating layer , and etching layers . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric (vertical sidewalls) layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5841195A CLAIM 1 . A via structure in an integrated circuit comprising : a base layer ; an undoped oxide layer overlying and in contact with the base layer ; a planarization layer of a planarizing material overlying the undoped oxide layer ; a first buffer layer overlying said planarization layer , the first buffer layer having a first level of dopants therein ; a second buffer layer overlying the first buffer layer at a buffer junction , the second buffer layer having a second level of dopants therein , the second level of dopants in the second buffer layer being substantially higher than the first level of dopants in the first buffer layer , and the first and second levels of dopants being unequal at the buffer junction ; an opening extending through the first buffer layer , the second buffer layer , the planarization layer and the undoped oxide layer , the opening exposing a portion of the base layer and the opening having an upper region at the first and second buffer layers having a gradually increasing diameter caused by the first and second buffer layers having a sloped profile at a less inclined angle (first sub interlevel dielectric layer) than the profile of the opening of said undoped oxide layer and said planarization layer ; and a conductive layer overlying portions of the second buffer layer and extending into the opening , and making electrical contact with the base layer . US5841195A CLAIM 3 . The via structure of claim 1 , wherein the opening has a lower portion adjacent to the planarization layer and wherein the lower portion of the opening has substantially vertical sidewalls (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch (first etch) stop layer and a second etch (second etch) stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (vertical sidewalls) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US5841195A CLAIM 1 . A via structure in an integrated circuit comprising : a base layer ; an undoped oxide layer overlying and in contact with the base layer ; a planarization layer of a planarizing material overlying the undoped oxide layer ; a first buffer layer overlying said planarization layer , the first buffer layer having a first level of dopants therein ; a second buffer layer overlying the first buffer layer at a buffer junction , the second buffer layer having a second level of dopants therein , the second level of dopants in the second buffer layer being substantially higher than the first level of dopants in the first buffer layer , and the first and second levels of dopants being unequal at the buffer junction ; an opening extending through the first buffer layer , the second buffer layer , the planarization layer and the undoped oxide layer , the opening exposing a portion of the base layer and the opening having an upper region at the first and second buffer layers having a gradually increasing diameter caused by the first and second buffer layers having a sloped profile at a less inclined angle (first sub interlevel dielectric layer) than the profile of the opening of said undoped oxide layer and said planarization layer ; and a conductive layer overlying portions of the second buffer layer and extending into the opening , and making electrical contact with the base layer . US5841195A CLAIM 3 . The via structure of claim 1 , wherein the opening has a lower portion adjacent to the planarization layer and wherein the lower portion of the opening has substantially vertical sidewalls (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) . US5841195A CLAIM 17 . In an integrated circuit , a via structure comprising : a substrate ; an insulating layer partially covering the substrate ; a first etch (first etch) ing layer covering the insulating layer , the first etching layer doped with a first concentration of dopant and etchable throughout the entire first layer at a first rate ; a second etch (second etch) ing layer covering a portion of the first etching layer , the second etching layer doped with a second concentration of dopant and etchable throughout the entire second etching layer at a second rate , the second rate being faster than the first rate ; an opening through the insulating layer and the first and second etching layers , the opening being substantially vertical through the insulating layer and being less vertical through the etching layers ; and a connection layer substantially filling the opening and contacting the substrate , insulating layer , and etching layers . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch (first etch) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (vertical sidewalls) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (second etch) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5841195A CLAIM 1 . A via structure in an integrated circuit comprising : a base layer ; an undoped oxide layer overlying and in contact with the base layer ; a planarization layer of a planarizing material overlying the undoped oxide layer ; a first buffer layer overlying said planarization layer , the first buffer layer having a first level of dopants therein ; a second buffer layer overlying the first buffer layer at a buffer junction , the second buffer layer having a second level of dopants therein , the second level of dopants in the second buffer layer being substantially higher than the first level of dopants in the first buffer layer , and the first and second levels of dopants being unequal at the buffer junction ; an opening extending through the first buffer layer , the second buffer layer , the planarization layer and the undoped oxide layer , the opening exposing a portion of the base layer and the opening having an upper region at the first and second buffer layers having a gradually increasing diameter caused by the first and second buffer layers having a sloped profile at a less inclined angle (first sub interlevel dielectric layer) than the profile of the opening of said undoped oxide layer and said planarization layer ; and a conductive layer overlying portions of the second buffer layer and extending into the opening , and making electrical contact with the base layer . US5841195A CLAIM 3 . The via structure of claim 1 , wherein the opening has a lower portion adjacent to the planarization layer and wherein the lower portion of the opening has substantially vertical sidewalls (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) . US5841195A CLAIM 17 . In an integrated circuit , a via structure comprising : a substrate ; an insulating layer partially covering the substrate ; a first etch (first etch) ing layer covering the insulating layer , the first etching layer doped with a first concentration of dopant and etchable throughout the entire first layer at a first rate ; a second etch (second etch) ing layer covering a portion of the first etching layer , the second etching layer doped with a second concentration of dopant and etchable throughout the entire second etching layer at a second rate , the second rate being faster than the first rate ; an opening through the insulating layer and the first and second etching layers , the opening being substantially vertical through the insulating layer and being less vertical through the etching layers ; and a connection layer substantially filling the opening and contacting the substrate , insulating layer , and etching layers . |
| US7977797B2 CLAIM 13 . An integrated circuit of claim 11 further comprising a floating gate (second doping concentration) . |
US5841195A CLAIM 15 . A via structure in an integrated circuit , comprising : a conductive element ; an oxide layer overlying the conductive element ; a spin on glass layer overlying the oxide layer ; a first buffer layer overlying the spin on glass layer and having a first doping concentration of a dopant that is substantially uniformly distributed within the first buffer layer ; a second buffer layer overlying the first buffer layer and having a second doping concentration (floating gate) of the dopant that is substantially uniformly distributed within the second buffer layer , the second doping concentration higher than the first doping concentration ; an opening through the first and second buffer layers , the spin on glass layer , and the oxide layer , the opening exposing a portion of the conductive element and having a first portion adjacent to the first and second buffer layers wherein the first portion of the opening has a sloped profile ; and a conductive layer overlying portions of the second buffer layer and extending into the opening , wherein the conductive layer makes an electrical contact with the conductive element . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5631184A Filed: 1995-03-27 Issued: 1997-05-20 Method of producing a semiconductor device having a fin type capacitor (Original Assignee) Fujitsu Ltd (Current Assignee) Fujitsu Ltd Shinichiro Ikemasu, Kouichi Hashimoto |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch (first etch) stop layer (one second, said sub) directly on said substrate in said contact region ; a first sub interlevel dielectric (contact hole) layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5631184A CLAIM 1 . A method of producing a semiconductor device comprising the steps of : (a) forming a planarizing layer on a substrate surface , wherein said planarizing layer has a planarized surface remote from and approximately parallel to said sub (first sub, first space, first range, first etch stop layer) strate surface ; (b) forming a first insulator layer having a thickness greater than or equal to (1/cosθ-1)·T+B on said planarized surface ; (c) alternately forming at least one first conductor layer and at least one second (first sub, first space, first range, first etch stop layer) insulator layer on said first insulator layer , so that a lowermost first conductor layer is formed on said first insulator layer and each second insulator layer is formed on a corresponding first conductor layer ; (d) forming a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) which penetrates each second insulator layer , each first conductor layer , said first insulator layer , and said planarizing layer , into contact with said substrate ; (e) forming a second conductor layer on an uppermost second insulator layer and in effective contact with side surfaces of each second insulator layer , each first conductor layer , said first insulator layer , and said planarizing layer , whereby defining said contact hole ; and (f) patterning the second conductor layer , each first conductor layer , and each second insulator layer ; wherein : θ denotes a largest inclination angle of said planarized surface , T denotes the thickness of a stacked structure comprising each first conductor layer , each second insulator layer and the second conductor layer , and B denotes the thickness of the first insulator layer required for protection of the first insulator layer against being over-etched . US5631184A CLAIM 6 . The method of producing a semiconductor device as claimed in claim 1 further comprising carrying out said step (d) by continuously etching from a conductor or insulator layer which is most remote from said planarized layer to a first conductor layer which is most proximate to said planarized layer at a first etch (first etch) ing speed ; and then selectively etching said first insulator layer . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch (first etch) stop layer (one second, said sub) protects removal of a substrate material (spin coating) by an etch process . |
US5631184A CLAIM 1 . A method of producing a semiconductor device comprising the steps of : (a) forming a planarizing layer on a substrate surface , wherein said planarizing layer has a planarized surface remote from and approximately parallel to said sub (first sub, first space, first range, first etch stop layer) strate surface ; (b) forming a first insulator layer having a thickness greater than or equal to (1/cosθ-1)·T+B on said planarized surface ; (c) alternately forming at least one first conductor layer and at least one second (first sub, first space, first range, first etch stop layer) insulator layer on said first insulator layer , so that a lowermost first conductor layer is formed on said first insulator layer and each second insulator layer is formed on a corresponding first conductor layer ; (d) forming a contact hole which penetrates each second insulator layer , each first conductor layer , said first insulator layer , and said planarizing layer , into contact with said substrate ; (e) forming a second conductor layer on an uppermost second insulator layer and in effective contact with side surfaces of each second insulator layer , each first conductor layer , said first insulator layer , and said planarizing layer , whereby defining said contact hole ; and (f) patterning the second conductor layer , each first conductor layer , and each second insulator layer ; wherein : θ denotes a largest inclination angle of said planarized surface , T denotes the thickness of a stacked structure comprising each first conductor layer , each second insulator layer and the second conductor layer , and B denotes the thickness of the first insulator layer required for protection of the first insulator layer against being over-etched . US5631184A CLAIM 6 . The method of producing a semiconductor device as claimed in claim 1 further comprising carrying out said step (d) by continuously etching from a conductor or insulator layer which is most remote from said planarized layer to a first conductor layer which is most proximate to said planarized layer at a first etch (first etch) ing speed ; and then selectively etching said first insulator layer . US5631184A CLAIM 18 . The method of producing a semiconductor device as claimed in claim 17 further comprising forming said first insulator layer by spin coating (substrate material) an insulator material onto said substrate . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (contact hole) layer insulates said contact region . |
US5631184A CLAIM 1 . A method of producing a semiconductor device comprising the steps of : (a) forming a planarizing layer on a substrate surface , wherein said planarizing layer has a planarized surface remote from and approximately parallel to said sub (first sub, first space, first range, first etch stop layer) strate surface ; (b) forming a first insulator layer having a thickness greater than or equal to (1/cosθ-1)·T+B on said planarized surface ; (c) alternately forming at least one first conductor layer and at least one second (first sub, first space, first range, first etch stop layer) insulator layer on said first insulator layer , so that a lowermost first conductor layer is formed on said first insulator layer and each second insulator layer is formed on a corresponding first conductor layer ; (d) forming a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) which penetrates each second insulator layer , each first conductor layer , said first insulator layer , and said planarizing layer , into contact with said substrate ; (e) forming a second conductor layer on an uppermost second insulator layer and in effective contact with side surfaces of each second insulator layer , each first conductor layer , said first insulator layer , and said planarizing layer , whereby defining said contact hole ; and (f) patterning the second conductor layer , each first conductor layer , and each second insulator layer ; wherein : θ denotes a largest inclination angle of said planarized surface , T denotes the thickness of a stacked structure comprising each first conductor layer , each second insulator layer and the second conductor layer , and B denotes the thickness of the first insulator layer required for protection of the first insulator layer against being over-etched . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (contact hole) layer insulates said contact region . |
US5631184A CLAIM 1 . A method of producing a semiconductor device comprising the steps of : (a) forming a planarizing layer on a substrate surface , wherein said planarizing layer has a planarized surface remote from and approximately parallel to said substrate surface ; (b) forming a first insulator layer having a thickness greater than or equal to (1/cosθ-1)·T+B on said planarized surface ; (c) alternately forming at least one first conductor layer and at least one second insulator layer on said first insulator layer , so that a lowermost first conductor layer is formed on said first insulator layer and each second insulator layer is formed on a corresponding first conductor layer ; (d) forming a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) which penetrates each second insulator layer , each first conductor layer , said first insulator layer , and said planarizing layer , into contact with said substrate ; (e) forming a second conductor layer on an uppermost second insulator layer and in effective contact with side surfaces of each second insulator layer , each first conductor layer , said first insulator layer , and said planarizing layer , whereby defining said contact hole ; and (f) patterning the second conductor layer , each first conductor layer , and each second insulator layer ; wherein : θ denotes a largest inclination angle of said planarized surface , T denotes the thickness of a stacked structure comprising each first conductor layer , each second insulator layer and the second conductor layer , and B denotes the thickness of the first insulator layer required for protection of the first insulator layer against being over-etched . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch (first etch) stop layer (one second, said sub) is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (contact hole) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5631184A CLAIM 1 . A method of producing a semiconductor device comprising the steps of : (a) forming a planarizing layer on a substrate surface , wherein said planarizing layer has a planarized surface remote from and approximately parallel to said sub (first sub, first space, first range, first etch stop layer) strate surface ; (b) forming a first insulator layer having a thickness greater than or equal to (1/cosθ-1)·T+B on said planarized surface ; (c) alternately forming at least one first conductor layer and at least one second (first sub, first space, first range, first etch stop layer) insulator layer on said first insulator layer , so that a lowermost first conductor layer is formed on said first insulator layer and each second insulator layer is formed on a corresponding first conductor layer ; (d) forming a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) which penetrates each second insulator layer , each first conductor layer , said first insulator layer , and said planarizing layer , into contact with said substrate ; (e) forming a second conductor layer on an uppermost second insulator layer and in effective contact with side surfaces of each second insulator layer , each first conductor layer , said first insulator layer , and said planarizing layer , whereby defining said contact hole ; and (f) patterning the second conductor layer , each first conductor layer , and each second insulator layer ; wherein : θ denotes a largest inclination angle of said planarized surface , T denotes the thickness of a stacked structure comprising each first conductor layer , each second insulator layer and the second conductor layer , and B denotes the thickness of the first insulator layer required for protection of the first insulator layer against being over-etched . US5631184A CLAIM 6 . The method of producing a semiconductor device as claimed in claim 1 further comprising carrying out said step (d) by continuously etching from a conductor or insulator layer which is most remote from said planarized layer to a first conductor layer which is most proximate to said planarized layer at a first etch (first etch) ing speed ; and then selectively etching said first insulator layer . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space (one second, said sub) in a portion of said first sub interlevel dielectric (contact hole) layer for said contact region is in a first range (one second, said sub) of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5631184A CLAIM 1 . A method of producing a semiconductor device comprising the steps of : (a) forming a planarizing layer on a substrate surface , wherein said planarizing layer has a planarized surface remote from and approximately parallel to said sub (first sub, first space, first range, first etch stop layer) strate surface ; (b) forming a first insulator layer having a thickness greater than or equal to (1/cosθ-1)·T+B on said planarized surface ; (c) alternately forming at least one first conductor layer and at least one second (first sub, first space, first range, first etch stop layer) insulator layer on said first insulator layer , so that a lowermost first conductor layer is formed on said first insulator layer and each second insulator layer is formed on a corresponding first conductor layer ; (d) forming a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) which penetrates each second insulator layer , each first conductor layer , said first insulator layer , and said planarizing layer , into contact with said substrate ; (e) forming a second conductor layer on an uppermost second insulator layer and in effective contact with side surfaces of each second insulator layer , each first conductor layer , said first insulator layer , and said planarizing layer , whereby defining said contact hole ; and (f) patterning the second conductor layer , each first conductor layer , and each second insulator layer ; wherein : θ denotes a largest inclination angle of said planarized surface , T denotes the thickness of a stacked structure comprising each first conductor layer , each second insulator layer and the second conductor layer , and B denotes the thickness of the first insulator layer required for protection of the first insulator layer against being over-etched . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US5631184A CLAIM 2 . The method of producing a semiconductor device as claimed in claim 1 further comprising forming a nitride layer on said planarized surface , and forming (anti reflective coating) said first insulator layer on said nitride layer . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch (first etch) stop layer (one second, said sub) and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (contact hole) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US5631184A CLAIM 1 . A method of producing a semiconductor device comprising the steps of : (a) forming a planarizing layer on a substrate surface , wherein said planarizing layer has a planarized surface remote from and approximately parallel to said sub (first sub, first space, first range, first etch stop layer) strate surface ; (b) forming a first insulator layer having a thickness greater than or equal to (1/cosθ-1)·T+B on said planarized surface ; (c) alternately forming at least one first conductor layer and at least one second (first sub, first space, first range, first etch stop layer) insulator layer on said first insulator layer , so that a lowermost first conductor layer is formed on said first insulator layer and each second insulator layer is formed on a corresponding first conductor layer ; (d) forming a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) which penetrates each second insulator layer , each first conductor layer , said first insulator layer , and said planarizing layer , into contact with said substrate ; (e) forming a second conductor layer on an uppermost second insulator layer and in effective contact with side surfaces of each second insulator layer , each first conductor layer , said first insulator layer , and said planarizing layer , whereby defining said contact hole ; and (f) patterning the second conductor layer , each first conductor layer , and each second insulator layer ; wherein : θ denotes a largest inclination angle of said planarized surface , T denotes the thickness of a stacked structure comprising each first conductor layer , each second insulator layer and the second conductor layer , and B denotes the thickness of the first insulator layer required for protection of the first insulator layer against being over-etched . US5631184A CLAIM 6 . The method of producing a semiconductor device as claimed in claim 1 further comprising carrying out said step (d) by continuously etching from a conductor or insulator layer which is most remote from said planarized layer to a first conductor layer which is most proximate to said planarized layer at a first etch (first etch) ing speed ; and then selectively etching said first insulator layer . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch (first etch) stop layer (one second, said sub) is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (contact hole) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5631184A CLAIM 1 . A method of producing a semiconductor device comprising the steps of : (a) forming a planarizing layer on a substrate surface , wherein said planarizing layer has a planarized surface remote from and approximately parallel to said sub (first sub, first space, first range, first etch stop layer) strate surface ; (b) forming a first insulator layer having a thickness greater than or equal to (1/cosθ-1)·T+B on said planarized surface ; (c) alternately forming at least one first conductor layer and at least one second (first sub, first space, first range, first etch stop layer) insulator layer on said first insulator layer , so that a lowermost first conductor layer is formed on said first insulator layer and each second insulator layer is formed on a corresponding first conductor layer ; (d) forming a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) which penetrates each second insulator layer , each first conductor layer , said first insulator layer , and said planarizing layer , into contact with said substrate ; (e) forming a second conductor layer on an uppermost second insulator layer and in effective contact with side surfaces of each second insulator layer , each first conductor layer , said first insulator layer , and said planarizing layer , whereby defining said contact hole ; and (f) patterning the second conductor layer , each first conductor layer , and each second insulator layer ; wherein : θ denotes a largest inclination angle of said planarized surface , T denotes the thickness of a stacked structure comprising each first conductor layer , each second insulator layer and the second conductor layer , and B denotes the thickness of the first insulator layer required for protection of the first insulator layer against being over-etched . US5631184A CLAIM 6 . The method of producing a semiconductor device as claimed in claim 1 further comprising carrying out said step (d) by continuously etching from a conductor or insulator layer which is most remote from said planarized layer to a first conductor layer which is most proximate to said planarized layer at a first etch (first etch) ing speed ; and then selectively etching said first insulator layer . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US5631184A CLAIM 2 . The method of producing a semiconductor device as claimed in claim 1 further comprising forming a nitride layer on said planarized surface , and forming (anti reflective coating) said first insulator layer on said nitride layer . |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region is a first range (one second, said sub) of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5631184A CLAIM 1 . A method of producing a semiconductor device comprising the steps of : (a) forming a planarizing layer on a substrate surface , wherein said planarizing layer has a planarized surface remote from and approximately parallel to said sub (first sub, first space, first range, first etch stop layer) strate surface ; (b) forming a first insulator layer having a thickness greater than or equal to (1/cosθ-1)·T+B on said planarized surface ; (c) alternately forming at least one first conductor layer and at least one second (first sub, first space, first range, first etch stop layer) insulator layer on said first insulator layer , so that a lowermost first conductor layer is formed on said first insulator layer and each second insulator layer is formed on a corresponding first conductor layer ; (d) forming a contact hole which penetrates each second insulator layer , each first conductor layer , said first insulator layer , and said planarizing layer , into contact with said substrate ; (e) forming a second conductor layer on an uppermost second insulator layer and in effective contact with side surfaces of each second insulator layer , each first conductor layer , said first insulator layer , and said planarizing layer , whereby defining said contact hole ; and (f) patterning the second conductor layer , each first conductor layer , and each second insulator layer ; wherein : θ denotes a largest inclination angle of said planarized surface , T denotes the thickness of a stacked structure comprising each first conductor layer , each second insulator layer and the second conductor layer , and B denotes the thickness of the first insulator layer required for protection of the first insulator layer against being over-etched . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5569948A Filed: 1994-12-20 Issued: 1996-10-29 Semiconductor device having a contact plug and contact pad (Original Assignee) SK Hynix Inc (Current Assignee) SK Hynix Inc Jae K. Kim |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region (second contact) coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (contact plug) layer over said first etch stop layer ; a second etch stop layer (insulating film) over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5569948A CLAIM 1 . A semiconductor device including a metal oxide semiconductor field effect transistor having a source and a drain formed in a semiconductor substrate , comprising : a first insulation layer disposed on the semiconductor substrate and having first and second contact (contact region) holes therein respectively corresponding to the source and the drain ; a contact plug (interlevel dielectric) formed in the second contact hole in electrical contact with the drain , the contact plug having a top surface substantially planar with an upper portion of the first insulation layer ; a contact pad formed in the first contact hole in electrical contact with the source , an upper edge of the contact pad overlapping adjacent portions of the first insulation layer surrounding the first contact hole ; a second insulation layer disposed on a surface of the first insulation layer and having third and fourth contact holes therein respectively corresponding to the contact plug and the contact pad ; a first conductive wiring being in electrical contact with the contact plug through the third contact hole ; and a second conductive wiring being in electrical contact with the contact pad through the fourth contact hole and being electrically insulated from the first conductive wiring . US5569948A CLAIM 3 . A semiconductor memory device including a metal oxide semiconductor field effect transistor , a capacitor being in contact with a source of the transistor , and a bit line being in contact with a drain of the transistor , comprising : a first insulating film (second etch stop layer, second interlevel dielectric layer) formed on a semiconductor substrate having contact holes therein corresponding to the source and drain of the transistor ; a contact plug formed in the contact hole corresponding to the drain and having an upper surface which is planar with an upper portion of the first insulating film , the contact plug being in electrical contact with the drain of the transistor ; a contact pad formed in the contact hole corresponding to the source and being in electrical contact with the source and having an upper edge of the contact pad overlapping an adjacent portion of the first insulating film surrounding the contact hole corresponding to the source ; a second insulating film , which has contact holes corresponding to the contact plug and the contact pad , disposed on a surface of the first insulating layer , the contact plug and the contact pad ; a bit line formed on the second insulating film being in electrical contact with the drain ; a third insulating film , which has a contact hole corresponding to the contact pad , disposed on the bit line and the second insulating film ; a storage electrode formed on the third insulating film being in electrical contact with the contact pad and being electrically insulated from the bit line ; and a dielectric film and a plate electrode both formed on the storage electrode . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (contact plug) layer insulates said contact region (second contact) . |
US5569948A CLAIM 1 . A semiconductor device including a metal oxide semiconductor field effect transistor having a source and a drain formed in a semiconductor substrate , comprising : a first insulation layer disposed on the semiconductor substrate and having first and second contact (contact region) holes therein respectively corresponding to the source and the drain ; a contact plug (interlevel dielectric) formed in the second contact hole in electrical contact with the drain , the contact plug having a top surface substantially planar with an upper portion of the first insulation layer ; a contact pad formed in the first contact hole in electrical contact with the source , an upper edge of the contact pad overlapping adjacent portions of the first insulation layer surrounding the first contact hole ; a second insulation layer disposed on a surface of the first insulation layer and having third and fourth contact holes therein respectively corresponding to the contact plug and the contact pad ; a first conductive wiring being in electrical contact with the contact plug through the third contact hole ; and a second conductive wiring being in electrical contact with the contact pad through the fourth contact hole and being electrically insulated from the first conductive wiring . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch stop layer (insulating film) protects lower layers during an etching process . |
US5569948A CLAIM 3 . A semiconductor memory device including a metal oxide semiconductor field effect transistor , a capacitor being in contact with a source of the transistor , and a bit line being in contact with a drain of the transistor , comprising : a first insulating film (second etch stop layer, second interlevel dielectric layer) formed on a semiconductor substrate having contact holes therein corresponding to the source and drain of the transistor ; a contact plug formed in the contact hole corresponding to the drain and having an upper surface which is planar with an upper portion of the first insulating film , the contact plug being in electrical contact with the drain of the transistor ; a contact pad formed in the contact hole corresponding to the source and being in electrical contact with the source and having an upper edge of the contact pad overlapping an adjacent portion of the first insulating film surrounding the contact hole corresponding to the source ; a second insulating film , which has contact holes corresponding to the contact plug and the contact pad , disposed on a surface of the first insulating layer , the contact plug and the contact pad ; a bit line formed on the second insulating film being in electrical contact with the drain ; a third insulating film , which has a contact hole corresponding to the contact pad , disposed on the bit line and the second insulating film ; a storage electrode formed on the third insulating film being in electrical contact with the contact pad and being electrically insulated from the bit line ; and a dielectric film and a plate electrode both formed on the storage electrode . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (contact plug) layer insulates said contact region (second contact) . |
US5569948A CLAIM 1 . A semiconductor device including a metal oxide semiconductor field effect transistor having a source and a drain formed in a semiconductor substrate , comprising : a first insulation layer disposed on the semiconductor substrate and having first and second contact (contact region) holes therein respectively corresponding to the source and the drain ; a contact plug (interlevel dielectric) formed in the second contact hole in electrical contact with the drain , the contact plug having a top surface substantially planar with an upper portion of the first insulation layer ; a contact pad formed in the first contact hole in electrical contact with the source , an upper edge of the contact pad overlapping adjacent portions of the first insulation layer surrounding the first contact hole ; a second insulation layer disposed on a surface of the first insulation layer and having third and fourth contact holes therein respectively corresponding to the contact plug and the contact pad ; a first conductive wiring being in electrical contact with the contact plug through the third contact hole ; and a second conductive wiring being in electrical contact with the contact pad through the fourth contact hole and being electrically insulated from the first conductive wiring . |
| US7977797B2 CLAIM 6 . An integrated circuit of claim 1 wherein said spacer region insulates said contact region (second contact) . |
US5569948A CLAIM 1 . A semiconductor device including a metal oxide semiconductor field effect transistor having a source and a drain formed in a semiconductor substrate , comprising : a first insulation layer disposed on the semiconductor substrate and having first and second contact (contact region) holes therein respectively corresponding to the source and the drain ; a contact plug formed in the second contact hole in electrical contact with the drain , the contact plug having a top surface substantially planar with an upper portion of the first insulation layer ; a contact pad formed in the first contact hole in electrical contact with the source , an upper edge of the contact pad overlapping adjacent portions of the first insulation layer surrounding the first contact hole ; a second insulation layer disposed on a surface of the first insulation layer and having third and fourth contact holes therein respectively corresponding to the contact plug and the contact pad ; a first conductive wiring being in electrical contact with the contact plug through the third contact hole ; and a second conductive wiring being in electrical contact with the contact pad through the fourth contact hole and being electrically insulated from the first conductive wiring . |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area of said contact region (second contact) permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
US5569948A CLAIM 1 . A semiconductor device including a metal oxide semiconductor field effect transistor having a source and a drain formed in a semiconductor substrate , comprising : a first insulation layer disposed on the semiconductor substrate and having first and second contact (contact region) holes therein respectively corresponding to the source and the drain ; a contact plug formed in the second contact hole in electrical contact with the drain , the contact plug having a top surface substantially planar with an upper portion of the first insulation layer ; a contact pad formed in the first contact hole in electrical contact with the source , an upper edge of the contact pad overlapping adjacent portions of the first insulation layer surrounding the first contact hole ; a second insulation layer disposed on a surface of the first insulation layer and having third and fourth contact holes therein respectively corresponding to the contact plug and the contact pad ; a first conductive wiring being in electrical contact with the contact plug through the third contact hole ; and a second conductive wiring being in electrical contact with the contact pad through the fourth contact hole and being electrically insulated from the first conductive wiring . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (contact plug) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer (insulating film) is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5569948A CLAIM 1 . A semiconductor device including a metal oxide semiconductor field effect transistor having a source and a drain formed in a semiconductor substrate , comprising : a first insulation layer disposed on the semiconductor substrate and having first and second contact holes therein respectively corresponding to the source and the drain ; a contact plug (interlevel dielectric) formed in the second contact hole in electrical contact with the drain , the contact plug having a top surface substantially planar with an upper portion of the first insulation layer ; a contact pad formed in the first contact hole in electrical contact with the source , an upper edge of the contact pad overlapping adjacent portions of the first insulation layer surrounding the first contact hole ; a second insulation layer disposed on a surface of the first insulation layer and having third and fourth contact holes therein respectively corresponding to the contact plug and the contact pad ; a first conductive wiring being in electrical contact with the contact plug through the third contact hole ; and a second conductive wiring being in electrical contact with the contact pad through the fourth contact hole and being electrically insulated from the first conductive wiring . US5569948A CLAIM 3 . A semiconductor memory device including a metal oxide semiconductor field effect transistor , a capacitor being in contact with a source of the transistor , and a bit line being in contact with a drain of the transistor , comprising : a first insulating film (second etch stop layer, second interlevel dielectric layer) formed on a semiconductor substrate having contact holes therein corresponding to the source and drain of the transistor ; a contact plug formed in the contact hole corresponding to the drain and having an upper surface which is planar with an upper portion of the first insulating film , the contact plug being in electrical contact with the drain of the transistor ; a contact pad formed in the contact hole corresponding to the source and being in electrical contact with the source and having an upper edge of the contact pad overlapping an adjacent portion of the first insulating film surrounding the contact hole corresponding to the source ; a second insulating film , which has contact holes corresponding to the contact plug and the contact pad , disposed on a surface of the first insulating layer , the contact plug and the contact pad ; a bit line formed on the second insulating film being in electrical contact with the drain ; a third insulating film , which has a contact hole corresponding to the contact pad , disposed on the bit line and the second insulating film ; a storage electrode formed on the third insulating film being in electrical contact with the contact pad and being electrically insulated from the bit line ; and a dielectric film and a plate electrode both formed on the storage electrode . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric (contact plug) layer for said contact region (second contact) is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5569948A CLAIM 1 . A semiconductor device including a metal oxide semiconductor field effect transistor having a source and a drain formed in a semiconductor substrate , comprising : a first insulation layer disposed on the semiconductor substrate and having first and second contact (contact region) holes therein respectively corresponding to the source and the drain ; a contact plug (interlevel dielectric) formed in the second contact hole in electrical contact with the drain , the contact plug having a top surface substantially planar with an upper portion of the first insulation layer ; a contact pad formed in the first contact hole in electrical contact with the source , an upper edge of the contact pad overlapping adjacent portions of the first insulation layer surrounding the first contact hole ; a second insulation layer disposed on a surface of the first insulation layer and having third and fourth contact holes therein respectively corresponding to the contact plug and the contact pad ; a first conductive wiring being in electrical contact with the contact plug through the third contact hole ; and a second conductive wiring being in electrical contact with the contact pad through the fourth contact hole and being electrically insulated from the first conductive wiring . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer (insulating film) wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region (second contact) and under a first sub interlevel dielectric (contact plug) layer and said second etch stop layer formed under a second interlevel dielectric layer (insulating film) , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US5569948A CLAIM 1 . A semiconductor device including a metal oxide semiconductor field effect transistor having a source and a drain formed in a semiconductor substrate , comprising : a first insulation layer disposed on the semiconductor substrate and having first and second contact (contact region) holes therein respectively corresponding to the source and the drain ; a contact plug (interlevel dielectric) formed in the second contact hole in electrical contact with the drain , the contact plug having a top surface substantially planar with an upper portion of the first insulation layer ; a contact pad formed in the first contact hole in electrical contact with the source , an upper edge of the contact pad overlapping adjacent portions of the first insulation layer surrounding the first contact hole ; a second insulation layer disposed on a surface of the first insulation layer and having third and fourth contact holes therein respectively corresponding to the contact plug and the contact pad ; a first conductive wiring being in electrical contact with the contact plug through the third contact hole ; and a second conductive wiring being in electrical contact with the contact pad through the fourth contact hole and being electrically insulated from the first conductive wiring . US5569948A CLAIM 3 . A semiconductor memory device including a metal oxide semiconductor field effect transistor , a capacitor being in contact with a source of the transistor , and a bit line being in contact with a drain of the transistor , comprising : a first insulating film (second etch stop layer, second interlevel dielectric layer) formed on a semiconductor substrate having contact holes therein corresponding to the source and drain of the transistor ; a contact plug formed in the contact hole corresponding to the drain and having an upper surface which is planar with an upper portion of the first insulating film , the contact plug being in electrical contact with the drain of the transistor ; a contact pad formed in the contact hole corresponding to the source and being in electrical contact with the source and having an upper edge of the contact pad overlapping an adjacent portion of the first insulating film surrounding the contact hole corresponding to the source ; a second insulating film , which has contact holes corresponding to the contact plug and the contact pad , disposed on a surface of the first insulating layer , the contact plug and the contact pad ; a bit line formed on the second insulating film being in electrical contact with the drain ; a third insulating film , which has a contact hole corresponding to the contact pad , disposed on the bit line and the second insulating film ; a storage electrode formed on the third insulating film being in electrical contact with the contact pad and being electrically insulated from the bit line ; and a dielectric film and a plate electrode both formed on the storage electrode . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (contact plug) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer (insulating film) is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5569948A CLAIM 1 . A semiconductor device including a metal oxide semiconductor field effect transistor having a source and a drain formed in a semiconductor substrate , comprising : a first insulation layer disposed on the semiconductor substrate and having first and second contact holes therein respectively corresponding to the source and the drain ; a contact plug (interlevel dielectric) formed in the second contact hole in electrical contact with the drain , the contact plug having a top surface substantially planar with an upper portion of the first insulation layer ; a contact pad formed in the first contact hole in electrical contact with the source , an upper edge of the contact pad overlapping adjacent portions of the first insulation layer surrounding the first contact hole ; a second insulation layer disposed on a surface of the first insulation layer and having third and fourth contact holes therein respectively corresponding to the contact plug and the contact pad ; a first conductive wiring being in electrical contact with the contact plug through the third contact hole ; and a second conductive wiring being in electrical contact with the contact pad through the fourth contact hole and being electrically insulated from the first conductive wiring . US5569948A CLAIM 3 . A semiconductor memory device including a metal oxide semiconductor field effect transistor , a capacitor being in contact with a source of the transistor , and a bit line being in contact with a drain of the transistor , comprising : a first insulating film (second etch stop layer, second interlevel dielectric layer) formed on a semiconductor substrate having contact holes therein corresponding to the source and drain of the transistor ; a contact plug formed in the contact hole corresponding to the drain and having an upper surface which is planar with an upper portion of the first insulating film , the contact plug being in electrical contact with the drain of the transistor ; a contact pad formed in the contact hole corresponding to the source and being in electrical contact with the source and having an upper edge of the contact pad overlapping an adjacent portion of the first insulating film surrounding the contact hole corresponding to the source ; a second insulating film , which has contact holes corresponding to the contact plug and the contact pad , disposed on a surface of the first insulating layer , the contact plug and the contact pad ; a bit line formed on the second insulating film being in electrical contact with the drain ; a third insulating film , which has a contact hole corresponding to the contact pad , disposed on the bit line and the second insulating film ; a storage electrode formed on the third insulating film being in electrical contact with the contact pad and being electrically insulated from the bit line ; and a dielectric film and a plate electrode both formed on the storage electrode . |
| US7977797B2 CLAIM 13 . An integrated circuit of claim 11 further comprising a floating gate (second insulation) . |
US5569948A CLAIM 1 . A semiconductor device including a metal oxide semiconductor field effect transistor having a source and a drain formed in a semiconductor substrate , comprising : a first insulation layer disposed on the semiconductor substrate and having first and second contact holes therein respectively corresponding to the source and the drain ; a contact plug formed in the second contact hole in electrical contact with the drain , the contact plug having a top surface substantially planar with an upper portion of the first insulation layer ; a contact pad formed in the first contact hole in electrical contact with the source , an upper edge of the contact pad overlapping adjacent portions of the first insulation layer surrounding the first contact hole ; a second insulation (floating gate) layer disposed on a surface of the first insulation layer and having third and fourth contact holes therein respectively corresponding to the contact plug and the contact pad ; a first conductive wiring being in electrical contact with the contact plug through the third contact hole ; and a second conductive wiring being in electrical contact with the contact pad through the fourth contact hole and being electrically insulated from the first conductive wiring . |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region (second contact) is a first range of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5569948A CLAIM 1 . A semiconductor device including a metal oxide semiconductor field effect transistor having a source and a drain formed in a semiconductor substrate , comprising : a first insulation layer disposed on the semiconductor substrate and having first and second contact (contact region) holes therein respectively corresponding to the source and the drain ; a contact plug formed in the second contact hole in electrical contact with the drain , the contact plug having a top surface substantially planar with an upper portion of the first insulation layer ; a contact pad formed in the first contact hole in electrical contact with the source , an upper edge of the contact pad overlapping adjacent portions of the first insulation layer surrounding the first contact hole ; a second insulation layer disposed on a surface of the first insulation layer and having third and fourth contact holes therein respectively corresponding to the contact plug and the contact pad ; a first conductive wiring being in electrical contact with the contact plug through the third contact hole ; and a second conductive wiring being in electrical contact with the contact pad through the fourth contact hole and being electrically insulated from the first conductive wiring . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5451804A Filed: 1994-11-16 Issued: 1995-09-19 VLSI device with global planarization (Original Assignee) United Microelectronics Corp (Current Assignee) United Microelectronics Corp Water Lur, Ben Chen |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region (fourth surface) coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region (gate electrodes) such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5451804A CLAIM 1 . The integrated circuit device having global planarization comprising : trenched isolation regions within a silicon substrate ; trenched polysilicon gate electrodes (spacer region) within said silicon substrate and within said trenched isolation regions ; source and drain regions within said silicon substrate wherein the top surfaces of said trenched isolation regions , said trenched polysilicon gate electrodes , and said source and drain regions form a planarized first surface of said silicon substrate ; a pre-metal dielectric layer over said planarized first surface of said silicon substrate ; metal plug contacts within said pre-metal dielectric layer wherein the top surfaces of said pre-metal dielectric and said tungsten plugs form a planarized second surface over said silicon substrate ; a first metal layer over said planarized second surface over said silicon substrate wherein portions of said first metal layer have been transformed into an insulator layer by the implantation of oxygen ions and wherein the top surface of said first metal layer form a planarized third surface over said silicon substrate ; an inter-metal dielectric layer over said third planarized surface over said silicon substrate ; metal plug contacts within said inter-metal dielectric layer wherein the top surfaces of said inter-metal dielectric and said metal plugs form a fourth planarized surface over said silicon substrate ; a second metal layer over said planarized fourth surface (contact region) over said silicon substrate wherein portions of said second metal layer have been transformed into an insulator layer by the implantation of oxygen ions and wherein the top surface of said second metal layer forms a planarized fifth surface over said silicon substrate ; and a passivation layer over said planarized fifth surface completing said integrated circuit device with global planarization . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric layer insulates said contact region (fourth surface) . |
US5451804A CLAIM 1 . The integrated circuit device having global planarization comprising : trenched isolation regions within a silicon substrate ; trenched polysilicon gate electrodes within said silicon substrate and within said trenched isolation regions ; source and drain regions within said silicon substrate wherein the top surfaces of said trenched isolation regions , said trenched polysilicon gate electrodes , and said source and drain regions form a planarized first surface of said silicon substrate ; a pre-metal dielectric layer over said planarized first surface of said silicon substrate ; metal plug contacts within said pre-metal dielectric layer wherein the top surfaces of said pre-metal dielectric and said tungsten plugs form a planarized second surface over said silicon substrate ; a first metal layer over said planarized second surface over said silicon substrate wherein portions of said first metal layer have been transformed into an insulator layer by the implantation of oxygen ions and wherein the top surface of said first metal layer form a planarized third surface over said silicon substrate ; an inter-metal dielectric layer over said third planarized surface over said silicon substrate ; metal plug contacts within said inter-metal dielectric layer wherein the top surfaces of said inter-metal dielectric and said metal plugs form a fourth planarized surface over said silicon substrate ; a second metal layer over said planarized fourth surface (contact region) over said silicon substrate wherein portions of said second metal layer have been transformed into an insulator layer by the implantation of oxygen ions and wherein the top surface of said second metal layer forms a planarized fifth surface over said silicon substrate ; and a passivation layer over said planarized fifth surface completing said integrated circuit device with global planarization . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric layer insulates said contact region (fourth surface) . |
US5451804A CLAIM 1 . The integrated circuit device having global planarization comprising : trenched isolation regions within a silicon substrate ; trenched polysilicon gate electrodes within said silicon substrate and within said trenched isolation regions ; source and drain regions within said silicon substrate wherein the top surfaces of said trenched isolation regions , said trenched polysilicon gate electrodes , and said source and drain regions form a planarized first surface of said silicon substrate ; a pre-metal dielectric layer over said planarized first surface of said silicon substrate ; metal plug contacts within said pre-metal dielectric layer wherein the top surfaces of said pre-metal dielectric and said tungsten plugs form a planarized second surface over said silicon substrate ; a first metal layer over said planarized second surface over said silicon substrate wherein portions of said first metal layer have been transformed into an insulator layer by the implantation of oxygen ions and wherein the top surface of said first metal layer form a planarized third surface over said silicon substrate ; an inter-metal dielectric layer over said third planarized surface over said silicon substrate ; metal plug contacts within said inter-metal dielectric layer wherein the top surfaces of said inter-metal dielectric and said metal plugs form a fourth planarized surface over said silicon substrate ; a second metal layer over said planarized fourth surface (contact region) over said silicon substrate wherein portions of said second metal layer have been transformed into an insulator layer by the implantation of oxygen ions and wherein the top surface of said second metal layer forms a planarized fifth surface over said silicon substrate ; and a passivation layer over said planarized fifth surface completing said integrated circuit device with global planarization . |
| US7977797B2 CLAIM 6 . An integrated circuit of claim 1 wherein said spacer region (gate electrodes) insulates said contact region (fourth surface) . |
US5451804A CLAIM 1 . The integrated circuit device having global planarization comprising : trenched isolation regions within a silicon substrate ; trenched polysilicon gate electrodes (spacer region) within said silicon substrate and within said trenched isolation regions ; source and drain regions within said silicon substrate wherein the top surfaces of said trenched isolation regions , said trenched polysilicon gate electrodes , and said source and drain regions form a planarized first surface of said silicon substrate ; a pre-metal dielectric layer over said planarized first surface of said silicon substrate ; metal plug contacts within said pre-metal dielectric layer wherein the top surfaces of said pre-metal dielectric and said tungsten plugs form a planarized second surface over said silicon substrate ; a first metal layer over said planarized second surface over said silicon substrate wherein portions of said first metal layer have been transformed into an insulator layer by the implantation of oxygen ions and wherein the top surface of said first metal layer form a planarized third surface over said silicon substrate ; an inter-metal dielectric layer over said third planarized surface over said silicon substrate ; metal plug contacts within said inter-metal dielectric layer wherein the top surfaces of said inter-metal dielectric and said metal plugs form a fourth planarized surface over said silicon substrate ; a second metal layer over said planarized fourth surface (contact region) over said silicon substrate wherein portions of said second metal layer have been transformed into an insulator layer by the implantation of oxygen ions and wherein the top surface of said second metal layer forms a planarized fifth surface over said silicon substrate ; and a passivation layer over said planarized fifth surface completing said integrated circuit device with global planarization . |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area of said contact region (fourth surface) permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
US5451804A CLAIM 1 . The integrated circuit device having global planarization comprising : trenched isolation regions within a silicon substrate ; trenched polysilicon gate electrodes within said silicon substrate and within said trenched isolation regions ; source and drain regions within said silicon substrate wherein the top surfaces of said trenched isolation regions , said trenched polysilicon gate electrodes , and said source and drain regions form a planarized first surface of said silicon substrate ; a pre-metal dielectric layer over said planarized first surface of said silicon substrate ; metal plug contacts within said pre-metal dielectric layer wherein the top surfaces of said pre-metal dielectric and said tungsten plugs form a planarized second surface over said silicon substrate ; a first metal layer over said planarized second surface over said silicon substrate wherein portions of said first metal layer have been transformed into an insulator layer by the implantation of oxygen ions and wherein the top surface of said first metal layer form a planarized third surface over said silicon substrate ; an inter-metal dielectric layer over said third planarized surface over said silicon substrate ; metal plug contacts within said inter-metal dielectric layer wherein the top surfaces of said inter-metal dielectric and said metal plugs form a fourth planarized surface over said silicon substrate ; a second metal layer over said planarized fourth surface (contact region) over said silicon substrate wherein portions of said second metal layer have been transformed into an insulator layer by the implantation of oxygen ions and wherein the top surface of said second metal layer forms a planarized fifth surface over said silicon substrate ; and a passivation layer over said planarized fifth surface completing said integrated circuit device with global planarization . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space (said sub) in a portion of said first sub interlevel dielectric layer for said contact region (fourth surface) is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5451804A CLAIM 1 . The integrated circuit device having global planarization comprising : trenched isolation regions within a silicon substrate ; trenched polysilicon gate electrodes within said silicon substrate and within said trenched isolation regions ; source and drain regions within said silicon substrate wherein the top surfaces of said trenched isolation regions , said trenched polysilicon gate electrodes , and said source and drain regions form a planarized first surface of said silicon substrate ; a pre-metal dielectric layer over said planarized first surface of said silicon substrate ; metal plug contacts within said pre-metal dielectric layer wherein the top surfaces of said pre-metal dielectric and said tungsten plugs form a planarized second surface over said silicon substrate ; a first metal layer over said planarized second surface over said silicon substrate wherein portions of said first metal layer have been transformed into an insulator layer by the implantation of oxygen ions and wherein the top surface of said first metal layer form a planarized third surface over said silicon substrate ; an inter-metal dielectric layer over said third planarized surface over said silicon substrate ; metal plug contacts within said inter-metal dielectric layer wherein the top surfaces of said inter-metal dielectric and said metal plugs form a fourth planarized surface over said silicon substrate ; a second metal layer over said planarized fourth surface (contact region) over said silicon substrate wherein portions of said second metal layer have been transformed into an insulator layer by the implantation of oxygen ions and wherein the top surface of said second metal layer forms a planarized fifth surface over said silicon substrate ; and a passivation layer over said planarized fifth surface completing said integrated circuit device with global planarization . US5451804A CLAIM 6 . The device of claim 1 wherein said metal plugs are formed by the steps of : deposition of a glue layer over the surface of said sub (first space) strate and within said contact openings ; blanket deposition of a tungsten layer ; and etching back said glue layer and said tungsten layer to form a planarized top surface of said silicon substrate . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region (fourth surface) and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US5451804A CLAIM 1 . The integrated circuit device having global planarization comprising : trenched isolation regions within a silicon substrate ; trenched polysilicon gate electrodes within said silicon substrate and within said trenched isolation regions ; source and drain regions within said silicon substrate wherein the top surfaces of said trenched isolation regions , said trenched polysilicon gate electrodes , and said source and drain regions form a planarized first surface of said silicon substrate ; a pre-metal dielectric layer over said planarized first surface of said silicon substrate ; metal plug contacts within said pre-metal dielectric layer wherein the top surfaces of said pre-metal dielectric and said tungsten plugs form a planarized second surface over said silicon substrate ; a first metal layer over said planarized second surface over said silicon substrate wherein portions of said first metal layer have been transformed into an insulator layer by the implantation of oxygen ions and wherein the top surface of said first metal layer form a planarized third surface over said silicon substrate ; an inter-metal dielectric layer over said third planarized surface over said silicon substrate ; metal plug contacts within said inter-metal dielectric layer wherein the top surfaces of said inter-metal dielectric and said metal plugs form a fourth planarized surface over said silicon substrate ; a second metal layer over said planarized fourth surface (contact region) over said silicon substrate wherein portions of said second metal layer have been transformed into an insulator layer by the implantation of oxygen ions and wherein the top surface of said second metal layer forms a planarized fifth surface over said silicon substrate ; and a passivation layer over said planarized fifth surface completing said integrated circuit device with global planarization . |
| US7977797B2 CLAIM 13 . An integrated circuit of claim 11 further comprising a floating gate (drain regions) . |
US5451804A CLAIM 1 . The integrated circuit device having global planarization comprising : trenched isolation regions within a silicon substrate ; trenched polysilicon gate electrodes within said silicon substrate and within said trenched isolation regions ; source and drain regions (floating gate) within said silicon substrate wherein the top surfaces of said trenched isolation regions , said trenched polysilicon gate electrodes , and said source and drain regions form a planarized first surface of said silicon substrate ; a pre-metal dielectric layer over said planarized first surface of said silicon substrate ; metal plug contacts within said pre-metal dielectric layer wherein the top surfaces of said pre-metal dielectric and said tungsten plugs form a planarized second surface over said silicon substrate ; a first metal layer over said planarized second surface over said silicon substrate wherein portions of said first metal layer have been transformed into an insulator layer by the implantation of oxygen ions and wherein the top surface of said first metal layer form a planarized third surface over said silicon substrate ; an inter-metal dielectric layer over said third planarized surface over said silicon substrate ; metal plug contacts within said inter-metal dielectric layer wherein the top surfaces of said inter-metal dielectric and said metal plugs form a fourth planarized surface over said silicon substrate ; a second metal layer over said planarized fourth surface over said silicon substrate wherein portions of said second metal layer have been transformed into an insulator layer by the implantation of oxygen ions and wherein the top surface of said second metal layer forms a planarized fifth surface over said silicon substrate ; and a passivation layer over said planarized fifth surface completing said integrated circuit device with global planarization . |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region (fourth surface) is a first range of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5451804A CLAIM 1 . The integrated circuit device having global planarization comprising : trenched isolation regions within a silicon substrate ; trenched polysilicon gate electrodes within said silicon substrate and within said trenched isolation regions ; source and drain regions within said silicon substrate wherein the top surfaces of said trenched isolation regions , said trenched polysilicon gate electrodes , and said source and drain regions form a planarized first surface of said silicon substrate ; a pre-metal dielectric layer over said planarized first surface of said silicon substrate ; metal plug contacts within said pre-metal dielectric layer wherein the top surfaces of said pre-metal dielectric and said tungsten plugs form a planarized second surface over said silicon substrate ; a first metal layer over said planarized second surface over said silicon substrate wherein portions of said first metal layer have been transformed into an insulator layer by the implantation of oxygen ions and wherein the top surface of said first metal layer form a planarized third surface over said silicon substrate ; an inter-metal dielectric layer over said third planarized surface over said silicon substrate ; metal plug contacts within said inter-metal dielectric layer wherein the top surfaces of said inter-metal dielectric and said metal plugs form a fourth planarized surface over said silicon substrate ; a second metal layer over said planarized fourth surface (contact region) over said silicon substrate wherein portions of said second metal layer have been transformed into an insulator layer by the implantation of oxygen ions and wherein the top surface of said second metal layer forms a planarized fifth surface over said silicon substrate ; and a passivation layer over said planarized fifth surface completing said integrated circuit device with global planarization . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5494841A Filed: 1994-10-13 Issued: 1996-02-27 Split-polysilicon CMOS process for multi-megabit dynamic memories incorporating stacked container capacitor cells (Original Assignee) Micron Semiconductor Inc (Current Assignee) Micron Technology Inc Charles H. Dennison, Aftab Ahmad |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area (second conductive layer) of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (vertical sidewalls) layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5494841A CLAIM 1 . A CMOS DRAM manufacturing process comprising the following sequence of steps : (a) forming both N-type regions and P-type regions within an upper stratum of a silicon substrate ; (b) forming field isolation regions ; (c) forming a gate dielectric layer which covers an upper surface of the substrate except where covered by field isolation regions ; (d) forming a first conductive layer which covers all field isolation regions and the gate dielectric layer ; (e) patterning N-channel gates from a first portion of said first conductive layer , said first portion overlying said P-type regions , while leaving an unetched second portion of said first conductive layer , said second portion overlying the N-type regions ; (f) performing at least one N-channel source/drain implant ; (g) depositing an insulative mold layer which blankets both N-type regions and P-type regions ; (h) etching storage-node contact openings through said insulative mold layer ; (i) forming a second conductive layer (substrate coupling area) which blankets both N-type regions and P-type regions and lines said storage-node contact openings ; (j) removing those portions of said second conductive layer which are on an upper surface of said mold layer , while leaving other portions of said second conductive layer which line said storage-node contact openings , said other portions becoming individual storage-node capacitor plates for individual memory cells ; (k) forming a cell dielectric layer superjacent said second conductive layer ; (l) forming a third conductive layer superjacent said cell dielectric layer ; (m) patterning P-channel gates having vertical sidewalls (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) from the unetched expanse of said first conductive layer ; and (n) depositing a dielectric spacer layer ; (o) anisotropically etching the spacer layer to form spacers on the vertical sidewalls of the P-channel gates ; and (p) performing a blanket P-channel source/drain implant . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer protects removal of a substrate material by an etch process (capacitor plates) . |
US5494841A CLAIM 1 . A CMOS DRAM manufacturing process comprising the following sequence of steps : (a) forming both N-type regions and P-type regions within an upper stratum of a silicon substrate ; (b) forming field isolation regions ; (c) forming a gate dielectric layer which covers an upper surface of the substrate except where covered by field isolation regions ; (d) forming a first conductive layer which covers all field isolation regions and the gate dielectric layer ; (e) patterning N-channel gates from a first portion of said first conductive layer , said first portion overlying said P-type regions , while leaving an unetched second portion of said first conductive layer , said second portion overlying the N-type regions ; (f) performing at least one N-channel source/drain implant ; (g) depositing an insulative mold layer which blankets both N-type regions and P-type regions ; (h) etching storage-node contact openings through said insulative mold layer ; (i) forming a second conductive layer which blankets both N-type regions and P-type regions and lines said storage-node contact openings ; (j) removing those portions of said second conductive layer which are on an upper surface of said mold layer , while leaving other portions of said second conductive layer which line said storage-node contact openings , said other portions becoming individual storage-node capacitor plates (etch process) for individual memory cells ; (k) forming a cell dielectric layer superjacent said second conductive layer ; (l) forming a third conductive layer superjacent said cell dielectric layer ; (m) patterning P-channel gates having vertical sidewalls from the unetched expanse of said first conductive layer ; and (n) depositing a dielectric spacer layer ; (o) anisotropically etching the spacer layer to form spacers on the vertical sidewalls of the P-channel gates ; and (p) performing a blanket P-channel source/drain implant . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (vertical sidewalls) layer insulates said contact region . |
US5494841A CLAIM 1 . A CMOS DRAM manufacturing process comprising the following sequence of steps : (a) forming both N-type regions and P-type regions within an upper stratum of a silicon substrate ; (b) forming field isolation regions ; (c) forming a gate dielectric layer which covers an upper surface of the substrate except where covered by field isolation regions ; (d) forming a first conductive layer which covers all field isolation regions and the gate dielectric layer ; (e) patterning N-channel gates from a first portion of said first conductive layer , said first portion overlying said P-type regions , while leaving an unetched second portion of said first conductive layer , said second portion overlying the N-type regions ; (f) performing at least one N-channel source/drain implant ; (g) depositing an insulative mold layer which blankets both N-type regions and P-type regions ; (h) etching storage-node contact openings through said insulative mold layer ; (i) forming a second conductive layer which blankets both N-type regions and P-type regions and lines said storage-node contact openings ; (j) removing those portions of said second conductive layer which are on an upper surface of said mold layer , while leaving other portions of said second conductive layer which line said storage-node contact openings , said other portions becoming individual storage-node capacitor plates for individual memory cells ; (k) forming a cell dielectric layer superjacent said second conductive layer ; (l) forming a third conductive layer superjacent said cell dielectric layer ; (m) patterning P-channel gates having vertical sidewalls (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) from the unetched expanse of said first conductive layer ; and (n) depositing a dielectric spacer layer ; (o) anisotropically etching the spacer layer to form spacers on the vertical sidewalls of the P-channel gates ; and (p) performing a blanket P-channel source/drain implant . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch stop layer protects lower layers during an etching process (doped polysilicon, silicon wafer) . |
US5494841A CLAIM 4 . The CMOS DRAM manufacturing process of claim 1 , wherein the first conductive layer is conductively-doped polysilicon (etching process) . US5494841A CLAIM 8 . A process for manufacturing a CMOS dynamic random access memory on a silicon wafer (etching process) , said process comprising the following steps : (a) forming a first conductive layer on an upper surface of the wafer ; (b) patterning N-channel gates from a first portion of the first conductive layer , while leaving an unetched second portion of said first conductive layer from which P-channel gates will later be patterned ; (c) performing at least one N-channel source/drain implant ; (d) depositing an insulative mold layer which completely overlies said upper surface ; (e) etching storage-node contact openings through said mold layer ; (f) forming storage-node plates within the storage-node contact openings from a second conductive layer ; (g) forming a cell dielectric layer on exposed surfaces of said storage-node plates ; (h) forming a third conductive layer which overlies said cell dielectric layer ; (i) patterning P-channel gates from said second portion of the first conductive layer , said P-channel gates having vertical sidewalls ; (j) depositing a dielectric spacer layer which overlies the upper surface of the wafer ; (k) anisotropically etching the spacer layer to form spacers on the vertical sidewalls of the P-channel gates ; and (l) performing a P-channel source/drain implant , which is offset from the sidewalls of the P-channel gates by the spacers . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (vertical sidewalls) layer insulates said contact region . |
US5494841A CLAIM 1 . A CMOS DRAM manufacturing process comprising the following sequence of steps : (a) forming both N-type regions and P-type regions within an upper stratum of a silicon substrate ; (b) forming field isolation regions ; (c) forming a gate dielectric layer which covers an upper surface of the substrate except where covered by field isolation regions ; (d) forming a first conductive layer which covers all field isolation regions and the gate dielectric layer ; (e) patterning N-channel gates from a first portion of said first conductive layer , said first portion overlying said P-type regions , while leaving an unetched second portion of said first conductive layer , said second portion overlying the N-type regions ; (f) performing at least one N-channel source/drain implant ; (g) depositing an insulative mold layer which blankets both N-type regions and P-type regions ; (h) etching storage-node contact openings through said insulative mold layer ; (i) forming a second conductive layer which blankets both N-type regions and P-type regions and lines said storage-node contact openings ; (j) removing those portions of said second conductive layer which are on an upper surface of said mold layer , while leaving other portions of said second conductive layer which line said storage-node contact openings , said other portions becoming individual storage-node capacitor plates for individual memory cells ; (k) forming a cell dielectric layer superjacent said second conductive layer ; (l) forming a third conductive layer superjacent said cell dielectric layer ; (m) patterning P-channel gates having vertical sidewalls (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) from the unetched expanse of said first conductive layer ; and (n) depositing a dielectric spacer layer ; (o) anisotropically etching the spacer layer to form spacers on the vertical sidewalls of the P-channel gates ; and (p) performing a blanket P-channel source/drain implant . |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area (second conductive layer) of said contact region permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
US5494841A CLAIM 1 . A CMOS DRAM manufacturing process comprising the following sequence of steps : (a) forming both N-type regions and P-type regions within an upper stratum of a silicon substrate ; (b) forming field isolation regions ; (c) forming a gate dielectric layer which covers an upper surface of the substrate except where covered by field isolation regions ; (d) forming a first conductive layer which covers all field isolation regions and the gate dielectric layer ; (e) patterning N-channel gates from a first portion of said first conductive layer , said first portion overlying said P-type regions , while leaving an unetched second portion of said first conductive layer , said second portion overlying the N-type regions ; (f) performing at least one N-channel source/drain implant ; (g) depositing an insulative mold layer which blankets both N-type regions and P-type regions ; (h) etching storage-node contact openings through said insulative mold layer ; (i) forming a second conductive layer (substrate coupling area) which blankets both N-type regions and P-type regions and lines said storage-node contact openings ; (j) removing those portions of said second conductive layer which are on an upper surface of said mold layer , while leaving other portions of said second conductive layer which line said storage-node contact openings , said other portions becoming individual storage-node capacitor plates for individual memory cells ; (k) forming a cell dielectric layer superjacent said second conductive layer ; (l) forming a third conductive layer superjacent said cell dielectric layer ; (m) patterning P-channel gates having vertical sidewalls from the unetched expanse of said first conductive layer ; and (n) depositing a dielectric spacer layer ; (o) anisotropically etching the spacer layer to form spacers on the vertical sidewalls of the P-channel gates ; and (p) performing a blanket P-channel source/drain implant . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (vertical sidewalls) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5494841A CLAIM 1 . A CMOS DRAM manufacturing process comprising the following sequence of steps : (a) forming both N-type regions and P-type regions within an upper stratum of a silicon substrate ; (b) forming field isolation regions ; (c) forming a gate dielectric layer which covers an upper surface of the substrate except where covered by field isolation regions ; (d) forming a first conductive layer which covers all field isolation regions and the gate dielectric layer ; (e) patterning N-channel gates from a first portion of said first conductive layer , said first portion overlying said P-type regions , while leaving an unetched second portion of said first conductive layer , said second portion overlying the N-type regions ; (f) performing at least one N-channel source/drain implant ; (g) depositing an insulative mold layer which blankets both N-type regions and P-type regions ; (h) etching storage-node contact openings through said insulative mold layer ; (i) forming a second conductive layer which blankets both N-type regions and P-type regions and lines said storage-node contact openings ; (j) removing those portions of said second conductive layer which are on an upper surface of said mold layer , while leaving other portions of said second conductive layer which line said storage-node contact openings , said other portions becoming individual storage-node capacitor plates for individual memory cells ; (k) forming a cell dielectric layer superjacent said second conductive layer ; (l) forming a third conductive layer superjacent said cell dielectric layer ; (m) patterning P-channel gates having vertical sidewalls (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) from the unetched expanse of said first conductive layer ; and (n) depositing a dielectric spacer layer ; (o) anisotropically etching the spacer layer to form spacers on the vertical sidewalls of the P-channel gates ; and (p) performing a blanket P-channel source/drain implant . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric (vertical sidewalls) layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5494841A CLAIM 1 . A CMOS DRAM manufacturing process comprising the following sequence of steps : (a) forming both N-type regions and P-type regions within an upper stratum of a silicon substrate ; (b) forming field isolation regions ; (c) forming a gate dielectric layer which covers an upper surface of the substrate except where covered by field isolation regions ; (d) forming a first conductive layer which covers all field isolation regions and the gate dielectric layer ; (e) patterning N-channel gates from a first portion of said first conductive layer , said first portion overlying said P-type regions , while leaving an unetched second portion of said first conductive layer , said second portion overlying the N-type regions ; (f) performing at least one N-channel source/drain implant ; (g) depositing an insulative mold layer which blankets both N-type regions and P-type regions ; (h) etching storage-node contact openings through said insulative mold layer ; (i) forming a second conductive layer which blankets both N-type regions and P-type regions and lines said storage-node contact openings ; (j) removing those portions of said second conductive layer which are on an upper surface of said mold layer , while leaving other portions of said second conductive layer which line said storage-node contact openings , said other portions becoming individual storage-node capacitor plates for individual memory cells ; (k) forming a cell dielectric layer superjacent said second conductive layer ; (l) forming a third conductive layer superjacent said cell dielectric layer ; (m) patterning P-channel gates having vertical sidewalls (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) from the unetched expanse of said first conductive layer ; and (n) depositing a dielectric spacer layer ; (o) anisotropically etching the spacer layer to form spacers on the vertical sidewalls of the P-channel gates ; and (p) performing a blanket P-channel source/drain implant . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (vertical sidewalls) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area (second conductive layer) of said contact region is smaller than a metal layer coupling area of said contact region . |
US5494841A CLAIM 1 . A CMOS DRAM manufacturing process comprising the following sequence of steps : (a) forming both N-type regions and P-type regions within an upper stratum of a silicon substrate ; (b) forming field isolation regions ; (c) forming a gate dielectric layer which covers an upper surface of the substrate except where covered by field isolation regions ; (d) forming a first conductive layer which covers all field isolation regions and the gate dielectric layer ; (e) patterning N-channel gates from a first portion of said first conductive layer , said first portion overlying said P-type regions , while leaving an unetched second portion of said first conductive layer , said second portion overlying the N-type regions ; (f) performing at least one N-channel source/drain implant ; (g) depositing an insulative mold layer which blankets both N-type regions and P-type regions ; (h) etching storage-node contact openings through said insulative mold layer ; (i) forming a second conductive layer (substrate coupling area) which blankets both N-type regions and P-type regions and lines said storage-node contact openings ; (j) removing those portions of said second conductive layer which are on an upper surface of said mold layer , while leaving other portions of said second conductive layer which line said storage-node contact openings , said other portions becoming individual storage-node capacitor plates for individual memory cells ; (k) forming a cell dielectric layer superjacent said second conductive layer ; (l) forming a third conductive layer superjacent said cell dielectric layer ; (m) patterning P-channel gates having vertical sidewalls (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) from the unetched expanse of said first conductive layer ; and (n) depositing a dielectric spacer layer ; (o) anisotropically etching the spacer layer to form spacers on the vertical sidewalls of the P-channel gates ; and (p) performing a blanket P-channel source/drain implant . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (vertical sidewalls) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5494841A CLAIM 1 . A CMOS DRAM manufacturing process comprising the following sequence of steps : (a) forming both N-type regions and P-type regions within an upper stratum of a silicon substrate ; (b) forming field isolation regions ; (c) forming a gate dielectric layer which covers an upper surface of the substrate except where covered by field isolation regions ; (d) forming a first conductive layer which covers all field isolation regions and the gate dielectric layer ; (e) patterning N-channel gates from a first portion of said first conductive layer , said first portion overlying said P-type regions , while leaving an unetched second portion of said first conductive layer , said second portion overlying the N-type regions ; (f) performing at least one N-channel source/drain implant ; (g) depositing an insulative mold layer which blankets both N-type regions and P-type regions ; (h) etching storage-node contact openings through said insulative mold layer ; (i) forming a second conductive layer which blankets both N-type regions and P-type regions and lines said storage-node contact openings ; (j) removing those portions of said second conductive layer which are on an upper surface of said mold layer , while leaving other portions of said second conductive layer which line said storage-node contact openings , said other portions becoming individual storage-node capacitor plates for individual memory cells ; (k) forming a cell dielectric layer superjacent said second conductive layer ; (l) forming a third conductive layer superjacent said cell dielectric layer ; (m) patterning P-channel gates having vertical sidewalls (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) from the unetched expanse of said first conductive layer ; and (n) depositing a dielectric spacer layer ; (o) anisotropically etching the spacer layer to form spacers on the vertical sidewalls of the P-channel gates ; and (p) performing a blanket P-channel source/drain implant . |
| US7977797B2 CLAIM 13 . An integrated circuit of claim 11 further comprising a floating gate (drain region) . |
US5494841A CLAIM 12 . A process for manufacturing a CMOS dynamic random access memory cell array on a silicon wafer , said process comprising the following steps : (a) forming a conductive layer on an up : per surface of the wafer ; (b) patterning gates for transistors having a channel of a first conductivity type from a first portion of the conductive layer , while leaving an unetched second portion of the conductive layer from which gates for transistors having a channel of a second conductivity type will later be patterned ; (c) performing at least one source/drain implant for the transistors having a channel of said first conductivity type ; (d) depositing an insulative mold layer which completely overlies said upper surface ; (e) etching a cavity superjacent each memory cell location , each cavity having a floor which is in electrical contact to a source/drain region (floating gate) of one of said transistors having a channel of said first conductivity type ; (f) fabricating a cell capacitor at each memory cell location by using the cavity at each location as a mold to form at least one plate of the capacitor ; (g) patterning gates for transistors having a channel of the second conductivity type from said second portion of the conductive layer , said gates for transistors having a channel of the second conductivity type having sidewalls ; (h) forming spacers on the sidewalls ; and (i) performing at least one source/drain implant for the transistors having a channel of said second conductivity type , said at least one implant being offset from the sidewalls of the gates for transistors having a channel of the second conductivity type by the spacers . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5500558A Filed: 1994-08-31 Issued: 1996-03-19 Semiconductor device having a planarized surface (Original Assignee) Mitsubishi Electric Corp (Current Assignee) Mitsubishi Electric Corp Yoshio Hayashide |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (interlayer insulating film) layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5500558A CLAIM 1 . A semiconductor device having a planarized surface , comprising : a semiconductor substrate ; an interconnection layer portion provided on a surface of said semiconductor substrate and having a plurality of elements of at least one interconnection layer spreading horizontally , comprising a high density portion having a relatively high number of interconnection elements and a low density portion comprising a relatively low number of said interconnection elements ; a first interlayer insulating film (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer) provided on said semiconductor substrate to cover both said high interconnection density portion and said low interconnection density portion and having an insulating film surface ; a second interlayer insulating film provided over said first interlayer insulating film ; wherein at said high interconnection density portion , each of said first and second interlayer insulating films comprises a first silicon oxide film , a silicon nitride film and a second silicon oxide film , formed in this order relative to said substrate surface ; at said low interconnection density portion , said first interlayer insulating film includes said first silicon oxide film , said silicon nitride film , a PSG film and said second silicon oxide film , formed in this order relative to said substrate surface ; variations in height , as determined from said surface of said semiconductor substrate to said first insulating film surface extending over said high and said low interconnection density portions are limited to be within a range of ±0 . 3 μm . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer protects removal of a substrate material (silicon oxide) by an etch process . |
US5500558A CLAIM 1 . A semiconductor device having a planarized surface , comprising : a semiconductor substrate ; an interconnection layer portion provided on a surface of said semiconductor substrate and having a plurality of elements of at least one interconnection layer spreading horizontally , comprising a high density portion having a relatively high number of interconnection elements and a low density portion comprising a relatively low number of said interconnection elements ; a first interlayer insulating film provided on said semiconductor substrate to cover both said high interconnection density portion and said low interconnection density portion and having an insulating film surface ; a second interlayer insulating film provided over said first interlayer insulating film ; wherein at said high interconnection density portion , each of said first and second interlayer insulating films comprises a first silicon oxide (substrate material) film , a silicon nitride film and a second silicon oxide film , formed in this order relative to said substrate surface ; at said low interconnection density portion , said first interlayer insulating film includes said first silicon oxide film , said silicon nitride film , a PSG film and said second silicon oxide film , formed in this order relative to said substrate surface ; variations in height , as determined from said surface of said semiconductor substrate to said first insulating film surface extending over said high and said low interconnection density portions are limited to be within a range of ±0 . 3 μm . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (interlayer insulating film) layer insulates said contact region . |
US5500558A CLAIM 1 . A semiconductor device having a planarized surface , comprising : a semiconductor substrate ; an interconnection layer portion provided on a surface of said semiconductor substrate and having a plurality of elements of at least one interconnection layer spreading horizontally , comprising a high density portion having a relatively high number of interconnection elements and a low density portion comprising a relatively low number of said interconnection elements ; a first interlayer insulating film (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer) provided on said semiconductor substrate to cover both said high interconnection density portion and said low interconnection density portion and having an insulating film surface ; a second interlayer insulating film provided over said first interlayer insulating film ; wherein at said high interconnection density portion , each of said first and second interlayer insulating films comprises a first silicon oxide film , a silicon nitride film and a second silicon oxide film , formed in this order relative to said substrate surface ; at said low interconnection density portion , said first interlayer insulating film includes said first silicon oxide film , said silicon nitride film , a PSG film and said second silicon oxide film , formed in this order relative to said substrate surface ; variations in height , as determined from said surface of said semiconductor substrate to said first insulating film surface extending over said high and said low interconnection density portions are limited to be within a range of ±0 . 3 μm . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (interlayer insulating film) layer insulates said contact region . |
US5500558A CLAIM 1 . A semiconductor device having a planarized surface , comprising : a semiconductor substrate ; an interconnection layer portion provided on a surface of said semiconductor substrate and having a plurality of elements of at least one interconnection layer spreading horizontally , comprising a high density portion having a relatively high number of interconnection elements and a low density portion comprising a relatively low number of said interconnection elements ; a first interlayer insulating film (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer) provided on said semiconductor substrate to cover both said high interconnection density portion and said low interconnection density portion and having an insulating film surface ; a second interlayer insulating film provided over said first interlayer insulating film ; wherein at said high interconnection density portion , each of said first and second interlayer insulating films comprises a first silicon oxide film , a silicon nitride film and a second silicon oxide film , formed in this order relative to said substrate surface ; at said low interconnection density portion , said first interlayer insulating film includes said first silicon oxide film , said silicon nitride film , a PSG film and said second silicon oxide film , formed in this order relative to said substrate surface ; variations in height , as determined from said surface of said semiconductor substrate to said first insulating film surface extending over said high and said low interconnection density portions are limited to be within a range of ±0 . 3 μm . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (interlayer insulating film) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5500558A CLAIM 1 . A semiconductor device having a planarized surface , comprising : a semiconductor substrate ; an interconnection layer portion provided on a surface of said semiconductor substrate and having a plurality of elements of at least one interconnection layer spreading horizontally , comprising a high density portion having a relatively high number of interconnection elements and a low density portion comprising a relatively low number of said interconnection elements ; a first interlayer insulating film (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer) provided on said semiconductor substrate to cover both said high interconnection density portion and said low interconnection density portion and having an insulating film surface ; a second interlayer insulating film provided over said first interlayer insulating film ; wherein at said high interconnection density portion , each of said first and second interlayer insulating films comprises a first silicon oxide film , a silicon nitride film and a second silicon oxide film , formed in this order relative to said substrate surface ; at said low interconnection density portion , said first interlayer insulating film includes said first silicon oxide film , said silicon nitride film , a PSG film and said second silicon oxide film , formed in this order relative to said substrate surface ; variations in height , as determined from said surface of said semiconductor substrate to said first insulating film surface extending over said high and said low interconnection density portions are limited to be within a range of ±0 . 3 μm . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space (said sub) in a portion of said first sub interlevel dielectric (interlayer insulating film) layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5500558A CLAIM 1 . A semiconductor device having a planarized surface , comprising : a semiconductor substrate ; an interconnection layer portion provided on a surface of said semiconductor substrate and having a plurality of elements of at least one interconnection layer spreading horizontally , comprising a high density portion having a relatively high number of interconnection elements and a low density portion comprising a relatively low number of said interconnection elements ; a first interlayer insulating film (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer) provided on said semiconductor substrate to cover both said high interconnection density portion and said low interconnection density portion and having an insulating film surface ; a second interlayer insulating film provided over said first interlayer insulating film ; wherein at said high interconnection density portion , each of said first and second interlayer insulating films comprises a first silicon oxide film , a silicon nitride film and a second silicon oxide film , formed in this order relative to said sub (first space) strate surface ; at said low interconnection density portion , said first interlayer insulating film includes said first silicon oxide film , said silicon nitride film , a PSG film and said second silicon oxide film , formed in this order relative to said substrate surface ; variations in height , as determined from said surface of said semiconductor substrate to said first insulating film surface extending over said high and said low interconnection density portions are limited to be within a range of ±0 . 3 μm . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (interlayer insulating film) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US5500558A CLAIM 1 . A semiconductor device having a planarized surface , comprising : a semiconductor substrate ; an interconnection layer portion provided on a surface of said semiconductor substrate and having a plurality of elements of at least one interconnection layer spreading horizontally , comprising a high density portion having a relatively high number of interconnection elements and a low density portion comprising a relatively low number of said interconnection elements ; a first interlayer insulating film (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer) provided on said semiconductor substrate to cover both said high interconnection density portion and said low interconnection density portion and having an insulating film surface ; a second interlayer insulating film provided over said first interlayer insulating film ; wherein at said high interconnection density portion , each of said first and second interlayer insulating films comprises a first silicon oxide film , a silicon nitride film and a second silicon oxide film , formed in this order relative to said substrate surface ; at said low interconnection density portion , said first interlayer insulating film includes said first silicon oxide film , said silicon nitride film , a PSG film and said second silicon oxide film , formed in this order relative to said substrate surface ; variations in height , as determined from said surface of said semiconductor substrate to said first insulating film surface extending over said high and said low interconnection density portions are limited to be within a range of ±0 . 3 μm . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (interlayer insulating film) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5500558A CLAIM 1 . A semiconductor device having a planarized surface , comprising : a semiconductor substrate ; an interconnection layer portion provided on a surface of said semiconductor substrate and having a plurality of elements of at least one interconnection layer spreading horizontally , comprising a high density portion having a relatively high number of interconnection elements and a low density portion comprising a relatively low number of said interconnection elements ; a first interlayer insulating film (interlevel dielectric, second interlevel dielectric, second interlevel dielectric layer) provided on said semiconductor substrate to cover both said high interconnection density portion and said low interconnection density portion and having an insulating film surface ; a second interlayer insulating film provided over said first interlayer insulating film ; wherein at said high interconnection density portion , each of said first and second interlayer insulating films comprises a first silicon oxide film , a silicon nitride film and a second silicon oxide film , formed in this order relative to said substrate surface ; at said low interconnection density portion , said first interlayer insulating film includes said first silicon oxide film , said silicon nitride film , a PSG film and said second silicon oxide film , formed in this order relative to said substrate surface ; variations in height , as determined from said surface of said semiconductor substrate to said first insulating film surface extending over said high and said low interconnection density portions are limited to be within a range of ±0 . 3 μm . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5616960A Filed: 1994-07-06 Issued: 1997-04-01 Multilayered interconnection substrate having a resin wall formed on side surfaces of a contact hole (Original Assignee) Sony Corp (Current Assignee) Sony Corp Kazuhiro Noda, Shinji Nakamura, Hisao Hayashi |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (contact hole) layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5616960A CLAIM 1 . A multilayered interconnection substrate comprising : a first interconnection layer formed on a substrate ; first and second insulation films formed on said first interconnection layer , said first insulation film being directly formed on said first interconnection layer , said insulation films differing in composition from each other ; at least one contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) formed in said insulation films to expose a portion of said first interconnection layer , said contact hole being larger in an area of said first insulation film ; a resin wall formed within said contact hole , said resin wall extending to sides of the first insulation film ; and a second interconnection layer formed inside said contact hole along said resin wall and being electrically connected to the first interconnection layer exposed at a bottom portion of the contact hole . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (contact hole) layer insulates said contact region . |
US5616960A CLAIM 1 . A multilayered interconnection substrate comprising : a first interconnection layer formed on a substrate ; first and second insulation films formed on said first interconnection layer , said first insulation film being directly formed on said first interconnection layer , said insulation films differing in composition from each other ; at least one contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) formed in said insulation films to expose a portion of said first interconnection layer , said contact hole being larger in an area of said first insulation film ; a resin wall formed within said contact hole , said resin wall extending to sides of the first insulation film ; and a second interconnection layer formed inside said contact hole along said resin wall and being electrically connected to the first interconnection layer exposed at a bottom portion of the contact hole . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (contact hole) layer insulates said contact region . |
US5616960A CLAIM 1 . A multilayered interconnection substrate comprising : a first interconnection layer formed on a substrate ; first and second insulation films formed on said first interconnection layer , said first insulation film being directly formed on said first interconnection layer , said insulation films differing in composition from each other ; at least one contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) formed in said insulation films to expose a portion of said first interconnection layer , said contact hole being larger in an area of said first insulation film ; a resin wall formed within said contact hole , said resin wall extending to sides of the first insulation film ; and a second interconnection layer formed inside said contact hole along said resin wall and being electrically connected to the first interconnection layer exposed at a bottom portion of the contact hole . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (contact hole) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5616960A CLAIM 1 . A multilayered interconnection substrate comprising : a first interconnection layer formed on a substrate ; first and second insulation films formed on said first interconnection layer , said first insulation film being directly formed on said first interconnection layer , said insulation films differing in composition from each other ; at least one contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) formed in said insulation films to expose a portion of said first interconnection layer , said contact hole being larger in an area of said first insulation film ; a resin wall formed within said contact hole , said resin wall extending to sides of the first insulation film ; and a second interconnection layer formed inside said contact hole along said resin wall and being electrically connected to the first interconnection layer exposed at a bottom portion of the contact hole . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric (contact hole) layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5616960A CLAIM 1 . A multilayered interconnection substrate comprising : a first interconnection layer formed on a substrate ; first and second insulation films formed on said first interconnection layer , said first insulation film being directly formed on said first interconnection layer , said insulation films differing in composition from each other ; at least one contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) formed in said insulation films to expose a portion of said first interconnection layer , said contact hole being larger in an area of said first insulation film ; a resin wall formed within said contact hole , said resin wall extending to sides of the first insulation film ; and a second interconnection layer formed inside said contact hole along said resin wall and being electrically connected to the first interconnection layer exposed at a bottom portion of the contact hole . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (contact hole) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US5616960A CLAIM 1 . A multilayered interconnection substrate comprising : a first interconnection layer formed on a substrate ; first and second insulation films formed on said first interconnection layer , said first insulation film being directly formed on said first interconnection layer , said insulation films differing in composition from each other ; at least one contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) formed in said insulation films to expose a portion of said first interconnection layer , said contact hole being larger in an area of said first insulation film ; a resin wall formed within said contact hole , said resin wall extending to sides of the first insulation film ; and a second interconnection layer formed inside said contact hole along said resin wall and being electrically connected to the first interconnection layer exposed at a bottom portion of the contact hole . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (contact hole) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5616960A CLAIM 1 . A multilayered interconnection substrate comprising : a first interconnection layer formed on a substrate ; first and second insulation films formed on said first interconnection layer , said first insulation film being directly formed on said first interconnection layer , said insulation films differing in composition from each other ; at least one contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) formed in said insulation films to expose a portion of said first interconnection layer , said contact hole being larger in an area of said first insulation film ; a resin wall formed within said contact hole , said resin wall extending to sides of the first insulation film ; and a second interconnection layer formed inside said contact hole along said resin wall and being electrically connected to the first interconnection layer exposed at a bottom portion of the contact hole . |
| US7977797B2 CLAIM 13 . An integrated circuit of claim 11 further comprising a floating gate (second insulation) . |
US5616960A CLAIM 1 . A multilayered interconnection substrate comprising : a first interconnection layer formed on a substrate ; first and second insulation (floating gate) films formed on said first interconnection layer , said first insulation film being directly formed on said first interconnection layer , said insulation films differing in composition from each other ; at least one contact hole formed in said insulation films to expose a portion of said first interconnection layer , said contact hole being larger in an area of said first insulation film ; a resin wall formed within said contact hole , said resin wall extending to sides of the first insulation film ; and a second interconnection layer formed inside said contact hole along said resin wall and being electrically connected to the first interconnection layer exposed at a bottom portion of the contact hole . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5610099A Filed: 1994-06-28 Issued: 1997-03-11 Process for fabricating transistors using composite nitride structure (Original Assignee) Ramtron International Corp (Current Assignee) Intellectual Ventures I LLC E. Henry Stevens, Richard A. Bailey, Thomas C. Taylor |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance (sputter deposition) of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch (local interconnect, second plasma, first etch) stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (local interconnect, second plasma, first etch) layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5610099A CLAIM 1 . In the fabrication of an integrated circuit transistor having an electrode to which electrical contact is to be made , the electrode being proximate to another structure of the integrated circuit to which electrical contact is not to be made and wherein said another structure is surrounded by dielectric layers , the process comprising the steps of : establishing a first nitride layer that completely covers said electrode and overlies a first region that includes said electrode and said other structure , said first nitride layer and said electrode being formed by in-situ reaction of a deposited transition metal followed by reactive-sputter deposition (isolates guidance) of a transition metal nitride or refractory metal nitride ; establishing a second nitride layer over said first nitride layer ; patterning said second nitride layer to leave portions of said second nitride layer covering said electrode ; and oxidizing said first nitride layer using said portions of said second layer as a mask , so that exposed portions of said first nitride layer are converted into an insulating layer . US5610099A CLAIM 4 . The process according to claim 3 wherein said second nitride layer comprises silicon nitride and said first nitride layer comprises titanium nitride and said step of etching said window through said thick dielectric layer uses plasma etch conditions which favor a rapid etch rate through silicon oxide as a first etch (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) step ; said process further comprising the step of etching through said second nitride layer to said first nitride layer using a second plasma (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) etch condition which has extremely high etch selectivity between said first and second nitride layers . US5610099A CLAIM 7 . The process of claim 1 further comprising the step of forming a local interconnect (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) with titanium nitride as an electrical connection to an element selected from the group consisting of a transistor source , drain and gate region . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch (local interconnect, second plasma, first etch) stop layer protects removal of a substrate material (silicon oxide) by an etch process . |
US5610099A CLAIM 4 . The process according to claim 3 wherein said second nitride layer comprises silicon nitride and said first nitride layer comprises titanium nitride and said step of etching said window through said thick dielectric layer uses plasma etch conditions which favor a rapid etch rate through silicon oxide (substrate material) as a first etch (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) step ; said process further comprising the step of etching through said second nitride layer to said first nitride layer using a second plasma (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) etch condition which has extremely high etch selectivity between said first and second nitride layers . US5610099A CLAIM 7 . The process of claim 1 further comprising the step of forming a local interconnect (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) with titanium nitride as an electrical connection to an element selected from the group consisting of a transistor source , drain and gate region . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (local interconnect, second plasma, first etch) layer insulates said contact region . |
US5610099A CLAIM 4 . The process according to claim 3 wherein said second nitride layer comprises silicon nitride and said first nitride layer comprises titanium nitride and said step of etching said window through said thick dielectric layer uses plasma etch conditions which favor a rapid etch rate through silicon oxide as a first etch (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) step ; said process further comprising the step of etching through said second nitride layer to said first nitride layer using a second plasma (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) etch condition which has extremely high etch selectivity between said first and second nitride layers . US5610099A CLAIM 7 . The process of claim 1 further comprising the step of forming a local interconnect (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) with titanium nitride as an electrical connection to an element selected from the group consisting of a transistor source , drain and gate region . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (local interconnect, second plasma, first etch) layer insulates said contact region . |
US5610099A CLAIM 4 . The process according to claim 3 wherein said second nitride layer comprises silicon nitride and said first nitride layer comprises titanium nitride and said step of etching said window through said thick dielectric layer uses plasma etch conditions which favor a rapid etch rate through silicon oxide as a first etch (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) step ; said process further comprising the step of etching through said second nitride layer to said first nitride layer using a second plasma (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) etch condition which has extremely high etch selectivity between said first and second nitride layers . US5610099A CLAIM 7 . The process of claim 1 further comprising the step of forming a local interconnect (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) with titanium nitride as an electrical connection to an element selected from the group consisting of a transistor source , drain and gate region . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch (local interconnect, second plasma, first etch) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (local interconnect, second plasma, first etch) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5610099A CLAIM 4 . The process according to claim 3 wherein said second nitride layer comprises silicon nitride and said first nitride layer comprises titanium nitride and said step of etching said window through said thick dielectric layer uses plasma etch conditions which favor a rapid etch rate through silicon oxide as a first etch (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) step ; said process further comprising the step of etching through said second nitride layer to said first nitride layer using a second plasma (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) etch condition which has extremely high etch selectivity between said first and second nitride layers . US5610099A CLAIM 7 . The process of claim 1 further comprising the step of forming a local interconnect (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) with titanium nitride as an electrical connection to an element selected from the group consisting of a transistor source , drain and gate region . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric (local interconnect, second plasma, first etch) layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5610099A CLAIM 4 . The process according to claim 3 wherein said second nitride layer comprises silicon nitride and said first nitride layer comprises titanium nitride and said step of etching said window through said thick dielectric layer uses plasma etch conditions which favor a rapid etch rate through silicon oxide as a first etch (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) step ; said process further comprising the step of etching through said second nitride layer to said first nitride layer using a second plasma (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) etch condition which has extremely high etch selectivity between said first and second nitride layers . US5610099A CLAIM 7 . The process of claim 1 further comprising the step of forming a local interconnect (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) with titanium nitride as an electrical connection to an element selected from the group consisting of a transistor source , drain and gate region . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch (local interconnect, second plasma, first etch) stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (local interconnect, second plasma, first etch) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US5610099A CLAIM 4 . The process according to claim 3 wherein said second nitride layer comprises silicon nitride and said first nitride layer comprises titanium nitride and said step of etching said window through said thick dielectric layer uses plasma etch conditions which favor a rapid etch rate through silicon oxide as a first etch (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) step ; said process further comprising the step of etching through said second nitride layer to said first nitride layer using a second plasma (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) etch condition which has extremely high etch selectivity between said first and second nitride layers . US5610099A CLAIM 7 . The process of claim 1 further comprising the step of forming a local interconnect (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) with titanium nitride as an electrical connection to an element selected from the group consisting of a transistor source , drain and gate region . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch (local interconnect, second plasma, first etch) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (local interconnect, second plasma, first etch) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5610099A CLAIM 4 . The process according to claim 3 wherein said second nitride layer comprises silicon nitride and said first nitride layer comprises titanium nitride and said step of etching said window through said thick dielectric layer uses plasma etch conditions which favor a rapid etch rate through silicon oxide as a first etch (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) step ; said process further comprising the step of etching through said second nitride layer to said first nitride layer using a second plasma (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) etch condition which has extremely high etch selectivity between said first and second nitride layers . US5610099A CLAIM 7 . The process of claim 1 further comprising the step of forming a local interconnect (first etch, interlevel dielectric, second interlevel dielectric, first sub interlevel dielectric layer, second sub interlevel dielectric layer, second interlevel dielectric layer) with titanium nitride as an electrical connection to an element selected from the group consisting of a transistor source , drain and gate region . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5451543A Filed: 1994-04-25 Issued: 1995-09-19 Straight sidewall profile contact opening to underlying interconnect and method for making the same (Original Assignee) Motorola Solutions Inc (Current Assignee) NXP USA Inc Michael P. Woo, Robert P. Chebi, James D. Hayden |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer (first etch stop layer) directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5451543A CLAIM 2 . A method for making a plurality of contact openings to underlying multilevel interconnects , comprising the step of : forming a first conductor , on a first level , overlying a semiconductor substrate ; forming a first etch stop layer (first etch stop layer) overlying the first conductor ; forming a first dielectric layer overlying the first etch stop layer ; forming a second conductor , on a second level , overlying the semiconductor substrate , wherein the first and second conductors are vertically offset from each other ; forming a second etch stop layer overlying the second conductor ; forming a second dielectric layer overlying the second etch stop layer ; forming the plurality of contact openings by etching with a first etchant through the first and second dielectric layers down to the first and second etch stop layers , wherein the first and second etch stop layers prevent overetching of the first and second conductors ; and etching with a second etchant having a different chemistry than the first etchant through the first and second etch stop layers to allow subsequent electrical contact with the underlying multilevel interconnects . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer (first etch stop layer) protects removal of a substrate material (silicon oxide) by an etch process . |
US5451543A CLAIM 2 . A method for making a plurality of contact openings to underlying multilevel interconnects , comprising the step of : forming a first conductor , on a first level , overlying a semiconductor substrate ; forming a first etch stop layer (first etch stop layer) overlying the first conductor ; forming a first dielectric layer overlying the first etch stop layer ; forming a second conductor , on a second level , overlying the semiconductor substrate , wherein the first and second conductors are vertically offset from each other ; forming a second etch stop layer overlying the second conductor ; forming a second dielectric layer overlying the second etch stop layer ; forming the plurality of contact openings by etching with a first etchant through the first and second dielectric layers down to the first and second etch stop layers , wherein the first and second etch stop layers prevent overetching of the first and second conductors ; and etching with a second etchant having a different chemistry than the first etchant through the first and second etch stop layers to allow subsequent electrical contact with the underlying multilevel interconnects . US5451543A CLAIM 5 . The method of claim 2 , wherein the steps of forming the first and second dielectric layers comprise depositing a material selected from a group consisting of : plasma enhanced nitride , silicon oxide (substrate material) -based material , oxynitride , polyimide , spin-on-glass , and tetra ethyl orthosilicate . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer (first etch stop layer) is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5451543A CLAIM 2 . A method for making a plurality of contact openings to underlying multilevel interconnects , comprising the step of : forming a first conductor , on a first level , overlying a semiconductor substrate ; forming a first etch stop layer (first etch stop layer) overlying the first conductor ; forming a first dielectric layer overlying the first etch stop layer ; forming a second conductor , on a second level , overlying the semiconductor substrate , wherein the first and second conductors are vertically offset from each other ; forming a second etch stop layer overlying the second conductor ; forming a second dielectric layer overlying the second etch stop layer ; forming the plurality of contact openings by etching with a first etchant through the first and second dielectric layers down to the first and second etch stop layers , wherein the first and second etch stop layers prevent overetching of the first and second conductors ; and etching with a second etchant having a different chemistry than the first etchant through the first and second etch stop layers to allow subsequent electrical contact with the underlying multilevel interconnects . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer (first etch stop layer) and a second etch stop layer wherein said first etch stop layer and said second etch stop layers (second etch stop layers) have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom (vertical sidewall) , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US5451543A CLAIM 1 . A method for making a contact opening to an underlying interconnect , comprising the steps of : forming a first conductor overlying and abutting a metal plug in a first dielectric layer ; forming an etch stop layer overlying the first conductor ; forming a second dielectric layer overlying the etch stop layer ; forming an opening in the second dielectric layer by etching with a first etchant through the second dielectric layer down to the etch stop layer to form an exposed portion of the etch stop layer , wherein the etch stop layer prevents resputtering of the first conductor during etching , thus providing the opening with a proximately vertical sidewall (contact bottom) profile ; removing the exposed portion of the etch stop layer to allow subsequent electrical contact with the underlying interconnect ; . filling the opening with a metal to form a filled opening ; forming a second conductor overlying the filled opening ; forming a second etch stop layer overlying the second conductor ; forming a third dielectric layer overlying the second etch stop layer ; forming a second opening by etching with a second etchant through the third dielectric layer down to the second etch stop layer to form an exposed portion of the second etch stop layer , wherein the second etch stop layer prevents resputtering of the second conductor during etching , thus providing the second opening with a proximately vertical sidewall profile ; and etching the exposed portion of the second etch stop layer with a second etchant to allow subsequent electrical contact with the second conductor . US5451543A CLAIM 2 . A method for making a plurality of contact openings to underlying multilevel interconnects , comprising the step of : forming a first conductor , on a first level , overlying a semiconductor substrate ; forming a first etch stop layer (first etch stop layer) overlying the first conductor ; forming a first dielectric layer overlying the first etch stop layer ; forming a second conductor , on a second level , overlying the semiconductor substrate , wherein the first and second conductors are vertically offset from each other ; forming a second etch stop layer overlying the second conductor ; forming a second dielectric layer overlying the second etch stop layer ; forming the plurality of contact openings by etching with a first etchant through the first and second dielectric layers down to the first and second etch stop layers (second etch stop layers) , wherein the first and second etch stop layers prevent overetching of the first and second conductors ; and etching with a second etchant having a different chemistry than the first etchant through the first and second etch stop layers to allow subsequent electrical contact with the underlying multilevel interconnects . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer (first etch stop layer) is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5451543A CLAIM 2 . A method for making a plurality of contact openings to underlying multilevel interconnects , comprising the step of : forming a first conductor , on a first level , overlying a semiconductor substrate ; forming a first etch stop layer (first etch stop layer) overlying the first conductor ; forming a first dielectric layer overlying the first etch stop layer ; forming a second conductor , on a second level , overlying the semiconductor substrate , wherein the first and second conductors are vertically offset from each other ; forming a second etch stop layer overlying the second conductor ; forming a second dielectric layer overlying the second etch stop layer ; forming the plurality of contact openings by etching with a first etchant through the first and second dielectric layers down to the first and second etch stop layers , wherein the first and second etch stop layers prevent overetching of the first and second conductors ; and etching with a second etchant having a different chemistry than the first etchant through the first and second etch stop layers to allow subsequent electrical contact with the underlying multilevel interconnects . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5532191A Filed: 1994-03-23 Issued: 1996-07-02 Method of chemical mechanical polishing planarization of an insulating film using an etching stop (Original Assignee) Kawasaki Steel Corp (Current Assignee) Kawasaki Microelectronics Inc Tadashi Nakano, Nobuyoshi Sato, Tomohiro Ohta, Hiroshi Yamamoto |
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| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer protects removal of a substrate material (silicon oxide) by an etch process . |
US5532191A CLAIM 1 . A method of planarizing an insulating film comprising the steps of : (a) preparing a semiconductor substrate ; (b) forming an insulating film on an uneven surface of the substrate by one of a chemical vapor deposition using an organic silicon compound as a raw material , coating a solution of an insulating substance on the uneven surface , and coating a solution of a precursor of an insulating substance on the uneven surface ; (c) forming a film having a chemical mechanical polishing etching speed slower than that of the insulating film by depositing one of silicon oxide (substrate material) and silicon oxynitride by performing a chemical vapor deposition using an inorganic silicon compound as a raw material ; and (d) etching back at least a part of the insulating film formed on the uneven surface of the substrate by a chemical mechanical polishing process using the film having a slower chemical mechanical polishing etching speed as an etching stop . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space (said sub) in a portion of said first sub interlevel dielectric layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5532191A CLAIM 4 . A method as claimed in claim 1 , wherein the film having a slower chemical mechanical polishing etching speed is formed between said uneven surface of said sub (first space) strate and said insulating film . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5362666A Filed: 1994-03-15 Issued: 1994-11-08 Method of producing a self-aligned contact penetrating cell plate (Original Assignee) Micron Technology Inc (Current Assignee) Micron Technology Inc Charles H. Dennison |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch (etch process, hard mask) stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (stacked capacitor) layer over said first etch stop layer ; a second etch (etch process, hard mask) stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5362666A CLAIM 1 . A method of fabricating a capacitor insulating spacer for a contact that passes through a capacitor cell conducting layer in an integrated circuit DRAM , said method comprising : providing a semiconducting substrate having an active area formed therein ; providing a plurality of transistor gate members , one on either side of said active area , wherein each transistor gate member has a side that opposes a side of another transistor gate member ; providing a transistor insulating spacer member on each said opposing side of each said transistor gate member ; providing a lower insulating layer covering said transistor gate members , said transistor insulating spacer member , and said active area ; providing a capacitor conducting layer covering said lower insulating layer above said active area ; providing a hard mask (etch process, multiple etch, second etch, etching process, second etch stop layers) layer over said capacitor conducting layer ; utilizing a photo-mask and etch process (etch process, multiple etch, second etch, etching process, second etch stop layers) to define a contact region having Walls penetrating at least said hard mask layer and said capacitor conducting layer above said active area ; creating a cell insulating spacer layer on said walls and said hard mask layer , said cell insulating spacer layer made of a material that etches differently than said hard mask layer ; and performing an anisotropic etch of said cell insulating spacer layer to remove said cell insulating spacer layer from said hard mask layer and create a capacitor insulating spacer covering said capacitor conducting layer on said walls of said contact region , said capacitor insulating spacer traveling down said walls of said contact region during said anisotropic etch . US5362666A CLAIM 5 . A method of fabricating a bit line contact that penetrates a capacitor cell plate in a stacked capacitor (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) DRAM comprising the steps of : providing a semiconductor substrate having a surface and an active area formed therein , first and second transistor gate members formed on said surface of said substrate , each of the first and second transistor gate members having sides extending upward from said surface of said substrate , wherein said first and second transistor gate members are positioned on opposed sides of said active area ; forming transistor insulating spacers covering said sides of said first and said second gate members , wherein a first distance separates said transistor insulating spacer formed on said first transistor gate member from said transistor insulating spacer formed on said second transistor gate member ; forming a lower insulating layer covering said first and second transistor gate members , said first insulating spacers , and said active area , said lower insulating layer being significantly thicker than said first and second transistor gate members ; forming a capacitor cell plate layer covering said lower insulating layer above said active area ; forming an upper insulating layer covering said capacitor cell plate layer ; etching a contact region above said active area penetrating said upper insulating layer and said capacitor cell plate layer above said active area , said contact region having opposed sidewalls that are separated from each other by a second distance that is more than the first distance separating said transistor insulating spacers , wherein said etching exposes a portion of said capacitor cell plate layer in said opposed sidewalls ; creating a third insulating layer on said wafer covering said opposed sidewalls including said exposed portion of said capacitor cell plate ; performing an anisotropic etch of said third insulating layer and said lower insulating layer to expose said active area at said semiconductor substrate surface while forming a capacitor insulating spacer on said opposed sidewalls of said contact region covering said exposed portions of said capacitor cell plate layer , wherein said anisotropic etch defines an opening between said capacitor insulating spacer on said opposing sidewalls at least as large as said first distance ; and forming a bit line contact in said contact region making direct electrical contact to said active area and extending fully the first distance between the transistor insulating spacers . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer protects removal of a substrate material by an etch process (etch process, hard mask) . |
US5362666A CLAIM 1 . A method of fabricating a capacitor insulating spacer for a contact that passes through a capacitor cell conducting layer in an integrated circuit DRAM , said method comprising : providing a semiconducting substrate having an active area formed therein ; providing a plurality of transistor gate members , one on either side of said active area , wherein each transistor gate member has a side that opposes a side of another transistor gate member ; providing a transistor insulating spacer member on each said opposing side of each said transistor gate member ; providing a lower insulating layer covering said transistor gate members , said transistor insulating spacer member , and said active area ; providing a capacitor conducting layer covering said lower insulating layer above said active area ; providing a hard mask (etch process, multiple etch, second etch, etching process, second etch stop layers) layer over said capacitor conducting layer ; utilizing a photo-mask and etch process (etch process, multiple etch, second etch, etching process, second etch stop layers) to define a contact region having Walls penetrating at least said hard mask layer and said capacitor conducting layer above said active area ; creating a cell insulating spacer layer on said walls and said hard mask layer , said cell insulating spacer layer made of a material that etches differently than said hard mask layer ; and performing an anisotropic etch of said cell insulating spacer layer to remove said cell insulating spacer layer from said hard mask layer and create a capacitor insulating spacer covering said capacitor conducting layer on said walls of said contact region , said capacitor insulating spacer traveling down said walls of said contact region during said anisotropic etch . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (stacked capacitor) layer insulates said contact region . |
US5362666A CLAIM 5 . A method of fabricating a bit line contact that penetrates a capacitor cell plate in a stacked capacitor (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) DRAM comprising the steps of : providing a semiconductor substrate having a surface and an active area formed therein , first and second transistor gate members formed on said surface of said substrate , each of the first and second transistor gate members having sides extending upward from said surface of said substrate , wherein said first and second transistor gate members are positioned on opposed sides of said active area ; forming transistor insulating spacers covering said sides of said first and said second gate members , wherein a first distance separates said transistor insulating spacer formed on said first transistor gate member from said transistor insulating spacer formed on said second transistor gate member ; forming a lower insulating layer covering said first and second transistor gate members , said first insulating spacers , and said active area , said lower insulating layer being significantly thicker than said first and second transistor gate members ; forming a capacitor cell plate layer covering said lower insulating layer above said active area ; forming an upper insulating layer covering said capacitor cell plate layer ; etching a contact region above said active area penetrating said upper insulating layer and said capacitor cell plate layer above said active area , said contact region having opposed sidewalls that are separated from each other by a second distance that is more than the first distance separating said transistor insulating spacers , wherein said etching exposes a portion of said capacitor cell plate layer in said opposed sidewalls ; creating a third insulating layer on said wafer covering said opposed sidewalls including said exposed portion of said capacitor cell plate ; performing an anisotropic etch of said third insulating layer and said lower insulating layer to expose said active area at said semiconductor substrate surface while forming a capacitor insulating spacer on said opposed sidewalls of said contact region covering said exposed portions of said capacitor cell plate layer , wherein said anisotropic etch defines an opening between said capacitor insulating spacer on said opposing sidewalls at least as large as said first distance ; and forming a bit line contact in said contact region making direct electrical contact to said active area and extending fully the first distance between the transistor insulating spacers . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch (etch process, hard mask) stop layer protects lower layers during an etching process (etch process, hard mask) . |
US5362666A CLAIM 1 . A method of fabricating a capacitor insulating spacer for a contact that passes through a capacitor cell conducting layer in an integrated circuit DRAM , said method comprising : providing a semiconducting substrate having an active area formed therein ; providing a plurality of transistor gate members , one on either side of said active area , wherein each transistor gate member has a side that opposes a side of another transistor gate member ; providing a transistor insulating spacer member on each said opposing side of each said transistor gate member ; providing a lower insulating layer covering said transistor gate members , said transistor insulating spacer member , and said active area ; providing a capacitor conducting layer covering said lower insulating layer above said active area ; providing a hard mask (etch process, multiple etch, second etch, etching process, second etch stop layers) layer over said capacitor conducting layer ; utilizing a photo-mask and etch process (etch process, multiple etch, second etch, etching process, second etch stop layers) to define a contact region having Walls penetrating at least said hard mask layer and said capacitor conducting layer above said active area ; creating a cell insulating spacer layer on said walls and said hard mask layer , said cell insulating spacer layer made of a material that etches differently than said hard mask layer ; and performing an anisotropic etch of said cell insulating spacer layer to remove said cell insulating spacer layer from said hard mask layer and create a capacitor insulating spacer covering said capacitor conducting layer on said walls of said contact region , said capacitor insulating spacer traveling down said walls of said contact region during said anisotropic etch . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (stacked capacitor) layer insulates said contact region . |
US5362666A CLAIM 5 . A method of fabricating a bit line contact that penetrates a capacitor cell plate in a stacked capacitor (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) DRAM comprising the steps of : providing a semiconductor substrate having a surface and an active area formed therein , first and second transistor gate members formed on said surface of said substrate , each of the first and second transistor gate members having sides extending upward from said surface of said substrate , wherein said first and second transistor gate members are positioned on opposed sides of said active area ; forming transistor insulating spacers covering said sides of said first and said second gate members , wherein a first distance separates said transistor insulating spacer formed on said first transistor gate member from said transistor insulating spacer formed on said second transistor gate member ; forming a lower insulating layer covering said first and second transistor gate members , said first insulating spacers , and said active area , said lower insulating layer being significantly thicker than said first and second transistor gate members ; forming a capacitor cell plate layer covering said lower insulating layer above said active area ; forming an upper insulating layer covering said capacitor cell plate layer ; etching a contact region above said active area penetrating said upper insulating layer and said capacitor cell plate layer above said active area , said contact region having opposed sidewalls that are separated from each other by a second distance that is more than the first distance separating said transistor insulating spacers , wherein said etching exposes a portion of said capacitor cell plate layer in said opposed sidewalls ; creating a third insulating layer on said wafer covering said opposed sidewalls including said exposed portion of said capacitor cell plate ; performing an anisotropic etch of said third insulating layer and said lower insulating layer to expose said active area at said semiconductor substrate surface while forming a capacitor insulating spacer on said opposed sidewalls of said contact region covering said exposed portions of said capacitor cell plate layer , wherein said anisotropic etch defines an opening between said capacitor insulating spacer on said opposing sidewalls at least as large as said first distance ; and forming a bit line contact in said contact region making direct electrical contact to said active area and extending fully the first distance between the transistor insulating spacers . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (stacked capacitor) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (etch process, hard mask) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5362666A CLAIM 1 . A method of fabricating a capacitor insulating spacer for a contact that passes through a capacitor cell conducting layer in an integrated circuit DRAM , said method comprising : providing a semiconducting substrate having an active area formed therein ; providing a plurality of transistor gate members , one on either side of said active area , wherein each transistor gate member has a side that opposes a side of another transistor gate member ; providing a transistor insulating spacer member on each said opposing side of each said transistor gate member ; providing a lower insulating layer covering said transistor gate members , said transistor insulating spacer member , and said active area ; providing a capacitor conducting layer covering said lower insulating layer above said active area ; providing a hard mask (etch process, multiple etch, second etch, etching process, second etch stop layers) layer over said capacitor conducting layer ; utilizing a photo-mask and etch process (etch process, multiple etch, second etch, etching process, second etch stop layers) to define a contact region having Walls penetrating at least said hard mask layer and said capacitor conducting layer above said active area ; creating a cell insulating spacer layer on said walls and said hard mask layer , said cell insulating spacer layer made of a material that etches differently than said hard mask layer ; and performing an anisotropic etch of said cell insulating spacer layer to remove said cell insulating spacer layer from said hard mask layer and create a capacitor insulating spacer covering said capacitor conducting layer on said walls of said contact region , said capacitor insulating spacer traveling down said walls of said contact region during said anisotropic etch . US5362666A CLAIM 5 . A method of fabricating a bit line contact that penetrates a capacitor cell plate in a stacked capacitor (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) DRAM comprising the steps of : providing a semiconductor substrate having a surface and an active area formed therein , first and second transistor gate members formed on said surface of said substrate , each of the first and second transistor gate members having sides extending upward from said surface of said substrate , wherein said first and second transistor gate members are positioned on opposed sides of said active area ; forming transistor insulating spacers covering said sides of said first and said second gate members , wherein a first distance separates said transistor insulating spacer formed on said first transistor gate member from said transistor insulating spacer formed on said second transistor gate member ; forming a lower insulating layer covering said first and second transistor gate members , said first insulating spacers , and said active area , said lower insulating layer being significantly thicker than said first and second transistor gate members ; forming a capacitor cell plate layer covering said lower insulating layer above said active area ; forming an upper insulating layer covering said capacitor cell plate layer ; etching a contact region above said active area penetrating said upper insulating layer and said capacitor cell plate layer above said active area , said contact region having opposed sidewalls that are separated from each other by a second distance that is more than the first distance separating said transistor insulating spacers , wherein said etching exposes a portion of said capacitor cell plate layer in said opposed sidewalls ; creating a third insulating layer on said wafer covering said opposed sidewalls including said exposed portion of said capacitor cell plate ; performing an anisotropic etch of said third insulating layer and said lower insulating layer to expose said active area at said semiconductor substrate surface while forming a capacitor insulating spacer on said opposed sidewalls of said contact region covering said exposed portions of said capacitor cell plate layer , wherein said anisotropic etch defines an opening between said capacitor insulating spacer on said opposing sidewalls at least as large as said first distance ; and forming a bit line contact in said contact region making direct electrical contact to said active area and extending fully the first distance between the transistor insulating spacers . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space (said sub) in a portion of said first sub interlevel dielectric (stacked capacitor) layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5362666A CLAIM 5 . A method of fabricating a bit line contact that penetrates a capacitor cell plate in a stacked capacitor (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) DRAM comprising the steps of : providing a semiconductor substrate having a surface and an active area formed therein , first and second transistor gate members formed on said surface of said sub (first space) strate , each of the first and second transistor gate members having sides extending upward from said surface of said substrate , wherein said first and second transistor gate members are positioned on opposed sides of said active area ; forming transistor insulating spacers covering said sides of said first and said second gate members , wherein a first distance separates said transistor insulating spacer formed on said first transistor gate member from said transistor insulating spacer formed on said second transistor gate member ; forming a lower insulating layer covering said first and second transistor gate members , said first insulating spacers , and said active area , said lower insulating layer being significantly thicker than said first and second transistor gate members ; forming a capacitor cell plate layer covering said lower insulating layer above said active area ; forming an upper insulating layer covering said capacitor cell plate layer ; etching a contact region above said active area penetrating said upper insulating layer and said capacitor cell plate layer above said active area , said contact region having opposed sidewalls that are separated from each other by a second distance that is more than the first distance separating said transistor insulating spacers , wherein said etching exposes a portion of said capacitor cell plate layer in said opposed sidewalls ; creating a third insulating layer on said wafer covering said opposed sidewalls including said exposed portion of said capacitor cell plate ; performing an anisotropic etch of said third insulating layer and said lower insulating layer to expose said active area at said semiconductor substrate surface while forming a capacitor insulating spacer on said opposed sidewalls of said contact region covering said exposed portions of said capacitor cell plate layer , wherein said anisotropic etch defines an opening between said capacitor insulating spacer on said opposing sidewalls at least as large as said first distance ; and forming a bit line contact in said contact region making direct electrical contact to said active area and extending fully the first distance between the transistor insulating spacers . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US5362666A CLAIM 5 . A method of fabricating a bit line contact that penetrates a capacitor cell plate in a stacked capacitor DRAM comprising the steps of : providing a semiconductor substrate having a surface and an active area formed therein , first and second transistor gate members formed on said surface of said substrate , each of the first and second transistor gate members having sides extending upward from said surface of said substrate , wherein said first and second transistor gate members are positioned on opposed sides of said active area ; forming transistor insulating spacers covering said sides of said first and said second gate members , wherein a first distance separates said transistor insulating spacer formed on said first transistor gate member from said transistor insulating spacer formed on said second transistor gate member ; forming a lower insulating layer covering said first and second transistor gate members , said first insulating spacers , and said active area , said lower insulating layer being significantly thicker than said first and second transistor gate members ; forming a capacitor cell plate layer covering said lower insulating layer above said active area ; forming an upper insulating layer covering said capacitor cell plate layer ; etching a contact region above said active area penetrating said upper insulating layer and said capacitor cell plate layer above said active area , said contact region having opposed sidewalls that are separated from each other by a second distance that is more than the first distance separating said transistor insulating spacers , wherein said etching exposes a portion of said capacitor cell plate layer in said opposed sidewalls ; creating a third insulating layer on said wafer covering said opposed sidewalls including said exposed portion of said capacitor cell plate ; performing an anisotropic etch of said third insulating layer and said lower insulating layer to expose said active area at said semiconductor substrate surface while forming a capacitor insulating spacer on said opposed sidewalls of said contact region covering said exposed portions of said capacitor cell plate layer , wherein said anisotropic etch defines an opening between said capacitor insulating spacer on said opposing sidewalls at least as large as said first distance ; and forming (anti reflective coating) a bit line contact in said contact region making direct electrical contact to said active area and extending fully the first distance between the transistor insulating spacers . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch (etch process, hard mask) stop insulation layer comprising a first etch stop layer and a second etch (etch process, hard mask) stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (stacked capacitor) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US5362666A CLAIM 1 . A method of fabricating a capacitor insulating spacer for a contact that passes through a capacitor cell conducting layer in an integrated circuit DRAM , said method comprising : providing a semiconducting substrate having an active area formed therein ; providing a plurality of transistor gate members , one on either side of said active area , wherein each transistor gate member has a side that opposes a side of another transistor gate member ; providing a transistor insulating spacer member on each said opposing side of each said transistor gate member ; providing a lower insulating layer covering said transistor gate members , said transistor insulating spacer member , and said active area ; providing a capacitor conducting layer covering said lower insulating layer above said active area ; providing a hard mask (etch process, multiple etch, second etch, etching process, second etch stop layers) layer over said capacitor conducting layer ; utilizing a photo-mask and etch process (etch process, multiple etch, second etch, etching process, second etch stop layers) to define a contact region having Walls penetrating at least said hard mask layer and said capacitor conducting layer above said active area ; creating a cell insulating spacer layer on said walls and said hard mask layer , said cell insulating spacer layer made of a material that etches differently than said hard mask layer ; and performing an anisotropic etch of said cell insulating spacer layer to remove said cell insulating spacer layer from said hard mask layer and create a capacitor insulating spacer covering said capacitor conducting layer on said walls of said contact region , said capacitor insulating spacer traveling down said walls of said contact region during said anisotropic etch . US5362666A CLAIM 5 . A method of fabricating a bit line contact that penetrates a capacitor cell plate in a stacked capacitor (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) DRAM comprising the steps of : providing a semiconductor substrate having a surface and an active area formed therein , first and second transistor gate members formed on said surface of said substrate , each of the first and second transistor gate members having sides extending upward from said surface of said substrate , wherein said first and second transistor gate members are positioned on opposed sides of said active area ; forming transistor insulating spacers covering said sides of said first and said second gate members , wherein a first distance separates said transistor insulating spacer formed on said first transistor gate member from said transistor insulating spacer formed on said second transistor gate member ; forming a lower insulating layer covering said first and second transistor gate members , said first insulating spacers , and said active area , said lower insulating layer being significantly thicker than said first and second transistor gate members ; forming a capacitor cell plate layer covering said lower insulating layer above said active area ; forming an upper insulating layer covering said capacitor cell plate layer ; etching a contact region above said active area penetrating said upper insulating layer and said capacitor cell plate layer above said active area , said contact region having opposed sidewalls that are separated from each other by a second distance that is more than the first distance separating said transistor insulating spacers , wherein said etching exposes a portion of said capacitor cell plate layer in said opposed sidewalls ; creating a third insulating layer on said wafer covering said opposed sidewalls including said exposed portion of said capacitor cell plate ; performing an anisotropic etch of said third insulating layer and said lower insulating layer to expose said active area at said semiconductor substrate surface while forming a capacitor insulating spacer on said opposed sidewalls of said contact region covering said exposed portions of said capacitor cell plate layer , wherein said anisotropic etch defines an opening between said capacitor insulating spacer on said opposing sidewalls at least as large as said first distance ; and forming a bit line contact in said contact region making direct electrical contact to said active area and extending fully the first distance between the transistor insulating spacers . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (stacked capacitor) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (etch process, hard mask) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5362666A CLAIM 1 . A method of fabricating a capacitor insulating spacer for a contact that passes through a capacitor cell conducting layer in an integrated circuit DRAM , said method comprising : providing a semiconducting substrate having an active area formed therein ; providing a plurality of transistor gate members , one on either side of said active area , wherein each transistor gate member has a side that opposes a side of another transistor gate member ; providing a transistor insulating spacer member on each said opposing side of each said transistor gate member ; providing a lower insulating layer covering said transistor gate members , said transistor insulating spacer member , and said active area ; providing a capacitor conducting layer covering said lower insulating layer above said active area ; providing a hard mask (etch process, multiple etch, second etch, etching process, second etch stop layers) layer over said capacitor conducting layer ; utilizing a photo-mask and etch process (etch process, multiple etch, second etch, etching process, second etch stop layers) to define a contact region having Walls penetrating at least said hard mask layer and said capacitor conducting layer above said active area ; creating a cell insulating spacer layer on said walls and said hard mask layer , said cell insulating spacer layer made of a material that etches differently than said hard mask layer ; and performing an anisotropic etch of said cell insulating spacer layer to remove said cell insulating spacer layer from said hard mask layer and create a capacitor insulating spacer covering said capacitor conducting layer on said walls of said contact region , said capacitor insulating spacer traveling down said walls of said contact region during said anisotropic etch . US5362666A CLAIM 5 . A method of fabricating a bit line contact that penetrates a capacitor cell plate in a stacked capacitor (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) DRAM comprising the steps of : providing a semiconductor substrate having a surface and an active area formed therein , first and second transistor gate members formed on said surface of said substrate , each of the first and second transistor gate members having sides extending upward from said surface of said substrate , wherein said first and second transistor gate members are positioned on opposed sides of said active area ; forming transistor insulating spacers covering said sides of said first and said second gate members , wherein a first distance separates said transistor insulating spacer formed on said first transistor gate member from said transistor insulating spacer formed on said second transistor gate member ; forming a lower insulating layer covering said first and second transistor gate members , said first insulating spacers , and said active area , said lower insulating layer being significantly thicker than said first and second transistor gate members ; forming a capacitor cell plate layer covering said lower insulating layer above said active area ; forming an upper insulating layer covering said capacitor cell plate layer ; etching a contact region above said active area penetrating said upper insulating layer and said capacitor cell plate layer above said active area , said contact region having opposed sidewalls that are separated from each other by a second distance that is more than the first distance separating said transistor insulating spacers , wherein said etching exposes a portion of said capacitor cell plate layer in said opposed sidewalls ; creating a third insulating layer on said wafer covering said opposed sidewalls including said exposed portion of said capacitor cell plate ; performing an anisotropic etch of said third insulating layer and said lower insulating layer to expose said active area at said semiconductor substrate surface while forming a capacitor insulating spacer on said opposed sidewalls of said contact region covering said exposed portions of said capacitor cell plate layer , wherein said anisotropic etch defines an opening between said capacitor insulating spacer on said opposing sidewalls at least as large as said first distance ; and forming a bit line contact in said contact region making direct electrical contact to said active area and extending fully the first distance between the transistor insulating spacers . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US5362666A CLAIM 5 . A method of fabricating a bit line contact that penetrates a capacitor cell plate in a stacked capacitor DRAM comprising the steps of : providing a semiconductor substrate having a surface and an active area formed therein , first and second transistor gate members formed on said surface of said substrate , each of the first and second transistor gate members having sides extending upward from said surface of said substrate , wherein said first and second transistor gate members are positioned on opposed sides of said active area ; forming transistor insulating spacers covering said sides of said first and said second gate members , wherein a first distance separates said transistor insulating spacer formed on said first transistor gate member from said transistor insulating spacer formed on said second transistor gate member ; forming a lower insulating layer covering said first and second transistor gate members , said first insulating spacers , and said active area , said lower insulating layer being significantly thicker than said first and second transistor gate members ; forming a capacitor cell plate layer covering said lower insulating layer above said active area ; forming an upper insulating layer covering said capacitor cell plate layer ; etching a contact region above said active area penetrating said upper insulating layer and said capacitor cell plate layer above said active area , said contact region having opposed sidewalls that are separated from each other by a second distance that is more than the first distance separating said transistor insulating spacers , wherein said etching exposes a portion of said capacitor cell plate layer in said opposed sidewalls ; creating a third insulating layer on said wafer covering said opposed sidewalls including said exposed portion of said capacitor cell plate ; performing an anisotropic etch of said third insulating layer and said lower insulating layer to expose said active area at said semiconductor substrate surface while forming a capacitor insulating spacer on said opposed sidewalls of said contact region covering said exposed portions of said capacitor cell plate layer , wherein said anisotropic etch defines an opening between said capacitor insulating spacer on said opposing sidewalls at least as large as said first distance ; and forming (anti reflective coating) a bit line contact in said contact region making direct electrical contact to said active area and extending fully the first distance between the transistor insulating spacers . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5413961A Filed: 1993-11-16 Issued: 1995-05-09 Method for forming a contact of a semiconductor device (Original Assignee) SK Hynix Inc (Current Assignee) SK Hynix Inc Jae K. Kim |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area (second conductive layer) of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer (fourth insulating) directly on said substrate in said contact region ; a first sub interlevel dielectric (contact hole) layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5413961A CLAIM 1 . A method for forming a contact of a semiconductor device having increased packing density , comprising steps of : forming an impurity diffusion region on an isolation region on a substrate ; forming a first insulating layer on the surface of said substrate ; forming a first conductive pattern and a second insulating pattern on the upper portion of said first insulating layer ; forming an etch barrier pattern on the upper portion of said second insulating pattern ; forming a third insulating layer on the upper potion of said etch barrier pattern and said first insulating layer , and etching said third insulating layer to expose the upper portion of said barrier pattern ; forming a photoresist pattern for contact mask on the surfaces of said etch barrier pattern and third insulating layer ; etching said third insulating layer and first insulating layer exposed by said photoresist pattern to form a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) having a lower surface being said impurity diffusion region ; forming a spacer along the sidewall of said contact hole ; and forming a second conductive layer (substrate coupling area) on the upper portion of said substrate having said contact hole and etch barrier layer , and patterning said second conductive layer . US5413961A CLAIM 9 . A method for forming a contact of a semiconductor device comprising the steps of : forming an impurity diffusion region on an isolation region on a substrate ; sequentially forming a first insulating layer , a first conductive layer and a second insulating layer on the surface of said substrate ; sequentially forming a second conductive layer , a third insulating layer and an etch barrier layer on the upper portion of said second insulating layer ; patterning said second conductive layer , third insulating layer , and etch barrier layer using a mask ; forming a fourth insulating (first etch stop layer) layer on the upper portion of said etch barrier pattern and second insulating layer , and etching said fourth insulating layer to expose the upper portion of said etch barrier pattern ; forming a photoresist pattern for contact mask on the surface of said etch barrier pattern and fourth insulating layer ; etching said fourth insulating layer , second insulating layer and first conductive layer exposed by said photoresist pattern to form a contact hole having a lower surface of said first insulating layer ; forming a spacer along the sidewall of said contact hole ; removing the lower surface of said contact hole of said first insulating layer to expose said impurity diffusion region ; and forming a third conductive layer over the upper portion of said substrate having said exposed impurity diffusion region and etch barrier layer , and patterning said third conductive layer . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer (fourth insulating) protects removal of a substrate material by an etch process . |
US5413961A CLAIM 9 . A method for forming a contact of a semiconductor device comprising the steps of : forming an impurity diffusion region on an isolation region on a substrate ; sequentially forming a first insulating layer , a first conductive layer and a second insulating layer on the surface of said substrate ; sequentially forming a second conductive layer , a third insulating layer and an etch barrier layer on the upper portion of said second insulating layer ; patterning said second conductive layer , third insulating layer , and etch barrier layer using a mask ; forming a fourth insulating (first etch stop layer) layer on the upper portion of said etch barrier pattern and second insulating layer , and etching said fourth insulating layer to expose the upper portion of said etch barrier pattern ; forming a photoresist pattern for contact mask on the surface of said etch barrier pattern and fourth insulating layer ; etching said fourth insulating layer , second insulating layer and first conductive layer exposed by said photoresist pattern to form a contact hole having a lower surface of said first insulating layer ; forming a spacer along the sidewall of said contact hole ; removing the lower surface of said contact hole of said first insulating layer to expose said impurity diffusion region ; and forming a third conductive layer over the upper portion of said substrate having said exposed impurity diffusion region and etch barrier layer , and patterning said third conductive layer . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (contact hole) layer insulates said contact region . |
US5413961A CLAIM 1 . A method for forming a contact of a semiconductor device having increased packing density , comprising steps of : forming an impurity diffusion region on an isolation region on a substrate ; forming a first insulating layer on the surface of said substrate ; forming a first conductive pattern and a second insulating pattern on the upper portion of said first insulating layer ; forming an etch barrier pattern on the upper portion of said second insulating pattern ; forming a third insulating layer on the upper potion of said etch barrier pattern and said first insulating layer , and etching said third insulating layer to expose the upper portion of said barrier pattern ; forming a photoresist pattern for contact mask on the surfaces of said etch barrier pattern and third insulating layer ; etching said third insulating layer and first insulating layer exposed by said photoresist pattern to form a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) having a lower surface being said impurity diffusion region ; forming a spacer along the sidewall of said contact hole ; and forming a second conductive layer on the upper portion of said substrate having said contact hole and etch barrier layer , and patterning said second conductive layer . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (contact hole) layer insulates said contact region . |
US5413961A CLAIM 1 . A method for forming a contact of a semiconductor device having increased packing density , comprising steps of : forming an impurity diffusion region on an isolation region on a substrate ; forming a first insulating layer on the surface of said substrate ; forming a first conductive pattern and a second insulating pattern on the upper portion of said first insulating layer ; forming an etch barrier pattern on the upper portion of said second insulating pattern ; forming a third insulating layer on the upper potion of said etch barrier pattern and said first insulating layer , and etching said third insulating layer to expose the upper portion of said barrier pattern ; forming a photoresist pattern for contact mask on the surfaces of said etch barrier pattern and third insulating layer ; etching said third insulating layer and first insulating layer exposed by said photoresist pattern to form a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) having a lower surface being said impurity diffusion region ; forming a spacer along the sidewall of said contact hole ; and forming a second conductive layer on the upper portion of said substrate having said contact hole and etch barrier layer , and patterning said second conductive layer . |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area (second conductive layer) of said contact region permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
US5413961A CLAIM 1 . A method for forming a contact of a semiconductor device having increased packing density , comprising steps of : forming an impurity diffusion region on an isolation region on a substrate ; forming a first insulating layer on the surface of said substrate ; forming a first conductive pattern and a second insulating pattern on the upper portion of said first insulating layer ; forming an etch barrier pattern on the upper portion of said second insulating pattern ; forming a third insulating layer on the upper potion of said etch barrier pattern and said first insulating layer , and etching said third insulating layer to expose the upper portion of said barrier pattern ; forming a photoresist pattern for contact mask on the surfaces of said etch barrier pattern and third insulating layer ; etching said third insulating layer and first insulating layer exposed by said photoresist pattern to form a contact hole having a lower surface being said impurity diffusion region ; forming a spacer along the sidewall of said contact hole ; and forming a second conductive layer (substrate coupling area) on the upper portion of said substrate having said contact hole and etch barrier layer , and patterning said second conductive layer . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer (fourth insulating) is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (contact hole) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5413961A CLAIM 1 . A method for forming a contact of a semiconductor device having increased packing density , comprising steps of : forming an impurity diffusion region on an isolation region on a substrate ; forming a first insulating layer on the surface of said substrate ; forming a first conductive pattern and a second insulating pattern on the upper portion of said first insulating layer ; forming an etch barrier pattern on the upper portion of said second insulating pattern ; forming a third insulating layer on the upper potion of said etch barrier pattern and said first insulating layer , and etching said third insulating layer to expose the upper portion of said barrier pattern ; forming a photoresist pattern for contact mask on the surfaces of said etch barrier pattern and third insulating layer ; etching said third insulating layer and first insulating layer exposed by said photoresist pattern to form a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) having a lower surface being said impurity diffusion region ; forming a spacer along the sidewall of said contact hole ; and forming a second conductive layer on the upper portion of said substrate having said contact hole and etch barrier layer , and patterning said second conductive layer . US5413961A CLAIM 9 . A method for forming a contact of a semiconductor device comprising the steps of : forming an impurity diffusion region on an isolation region on a substrate ; sequentially forming a first insulating layer , a first conductive layer and a second insulating layer on the surface of said substrate ; sequentially forming a second conductive layer , a third insulating layer and an etch barrier layer on the upper portion of said second insulating layer ; patterning said second conductive layer , third insulating layer , and etch barrier layer using a mask ; forming a fourth insulating (first etch stop layer) layer on the upper portion of said etch barrier pattern and second insulating layer , and etching said fourth insulating layer to expose the upper portion of said etch barrier pattern ; forming a photoresist pattern for contact mask on the surface of said etch barrier pattern and fourth insulating layer ; etching said fourth insulating layer , second insulating layer and first conductive layer exposed by said photoresist pattern to form a contact hole having a lower surface of said first insulating layer ; forming a spacer along the sidewall of said contact hole ; removing the lower surface of said contact hole of said first insulating layer to expose said impurity diffusion region ; and forming a third conductive layer over the upper portion of said substrate having said exposed impurity diffusion region and etch barrier layer , and patterning said third conductive layer . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space (said sub) in a portion of said first sub interlevel dielectric (contact hole) layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5413961A CLAIM 1 . A method for forming a contact of a semiconductor device having increased packing density , comprising steps of : forming an impurity diffusion region on an isolation region on a substrate ; forming a first insulating layer on the surface of said sub (first space) strate ; forming a first conductive pattern and a second insulating pattern on the upper portion of said first insulating layer ; forming an etch barrier pattern on the upper portion of said second insulating pattern ; forming a third insulating layer on the upper potion of said etch barrier pattern and said first insulating layer , and etching said third insulating layer to expose the upper portion of said barrier pattern ; forming a photoresist pattern for contact mask on the surfaces of said etch barrier pattern and third insulating layer ; etching said third insulating layer and first insulating layer exposed by said photoresist pattern to form a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) having a lower surface being said impurity diffusion region ; forming a spacer along the sidewall of said contact hole ; and forming a second conductive layer on the upper portion of said substrate having said contact hole and etch barrier layer , and patterning said second conductive layer . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US5413961A CLAIM 1 . A method for forming a contact of a semiconductor device having increased packing density , comprising steps of : forming an impurity diffusion region on an isolation region on a substrate ; forming a first insulating layer on the surface of said substrate ; forming a first conductive pattern and a second insulating pattern on the upper portion of said first insulating layer ; forming an etch barrier pattern on the upper portion of said second insulating pattern ; forming a third insulating layer on the upper potion of said etch barrier pattern and said first insulating layer , and etching said third insulating layer to expose the upper portion of said barrier pattern ; forming a photoresist pattern for contact mask on the surfaces of said etch barrier pattern and third insulating layer ; etching said third insulating layer and first insulating layer exposed by said photoresist pattern to form a contact hole having a lower surface being said impurity diffusion region ; forming a spacer along the sidewall of said contact hole ; and forming (anti reflective coating) a second conductive layer on the upper portion of said substrate having said contact hole and etch barrier layer , and patterning said second conductive layer . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer (fourth insulating) and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (contact hole) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area (second conductive layer) of said contact region is smaller than a metal layer coupling area of said contact region . |
US5413961A CLAIM 1 . A method for forming a contact of a semiconductor device having increased packing density , comprising steps of : forming an impurity diffusion region on an isolation region on a substrate ; forming a first insulating layer on the surface of said substrate ; forming a first conductive pattern and a second insulating pattern on the upper portion of said first insulating layer ; forming an etch barrier pattern on the upper portion of said second insulating pattern ; forming a third insulating layer on the upper potion of said etch barrier pattern and said first insulating layer , and etching said third insulating layer to expose the upper portion of said barrier pattern ; forming a photoresist pattern for contact mask on the surfaces of said etch barrier pattern and third insulating layer ; etching said third insulating layer and first insulating layer exposed by said photoresist pattern to form a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) having a lower surface being said impurity diffusion region ; forming a spacer along the sidewall of said contact hole ; and forming a second conductive layer (substrate coupling area) on the upper portion of said substrate having said contact hole and etch barrier layer , and patterning said second conductive layer . US5413961A CLAIM 9 . A method for forming a contact of a semiconductor device comprising the steps of : forming an impurity diffusion region on an isolation region on a substrate ; sequentially forming a first insulating layer , a first conductive layer and a second insulating layer on the surface of said substrate ; sequentially forming a second conductive layer , a third insulating layer and an etch barrier layer on the upper portion of said second insulating layer ; patterning said second conductive layer , third insulating layer , and etch barrier layer using a mask ; forming a fourth insulating (first etch stop layer) layer on the upper portion of said etch barrier pattern and second insulating layer , and etching said fourth insulating layer to expose the upper portion of said etch barrier pattern ; forming a photoresist pattern for contact mask on the surface of said etch barrier pattern and fourth insulating layer ; etching said fourth insulating layer , second insulating layer and first conductive layer exposed by said photoresist pattern to form a contact hole having a lower surface of said first insulating layer ; forming a spacer along the sidewall of said contact hole ; removing the lower surface of said contact hole of said first insulating layer to expose said impurity diffusion region ; and forming a third conductive layer over the upper portion of said substrate having said exposed impurity diffusion region and etch barrier layer , and patterning said third conductive layer . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer (fourth insulating) is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (contact hole) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5413961A CLAIM 1 . A method for forming a contact of a semiconductor device having increased packing density , comprising steps of : forming an impurity diffusion region on an isolation region on a substrate ; forming a first insulating layer on the surface of said substrate ; forming a first conductive pattern and a second insulating pattern on the upper portion of said first insulating layer ; forming an etch barrier pattern on the upper portion of said second insulating pattern ; forming a third insulating layer on the upper potion of said etch barrier pattern and said first insulating layer , and etching said third insulating layer to expose the upper portion of said barrier pattern ; forming a photoresist pattern for contact mask on the surfaces of said etch barrier pattern and third insulating layer ; etching said third insulating layer and first insulating layer exposed by said photoresist pattern to form a contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) having a lower surface being said impurity diffusion region ; forming a spacer along the sidewall of said contact hole ; and forming a second conductive layer on the upper portion of said substrate having said contact hole and etch barrier layer , and patterning said second conductive layer . US5413961A CLAIM 9 . A method for forming a contact of a semiconductor device comprising the steps of : forming an impurity diffusion region on an isolation region on a substrate ; sequentially forming a first insulating layer , a first conductive layer and a second insulating layer on the surface of said substrate ; sequentially forming a second conductive layer , a third insulating layer and an etch barrier layer on the upper portion of said second insulating layer ; patterning said second conductive layer , third insulating layer , and etch barrier layer using a mask ; forming a fourth insulating (first etch stop layer) layer on the upper portion of said etch barrier pattern and second insulating layer , and etching said fourth insulating layer to expose the upper portion of said etch barrier pattern ; forming a photoresist pattern for contact mask on the surface of said etch barrier pattern and fourth insulating layer ; etching said fourth insulating layer , second insulating layer and first conductive layer exposed by said photoresist pattern to form a contact hole having a lower surface of said first insulating layer ; forming a spacer along the sidewall of said contact hole ; removing the lower surface of said contact hole of said first insulating layer to expose said impurity diffusion region ; and forming a third conductive layer over the upper portion of said substrate having said exposed impurity diffusion region and etch barrier layer , and patterning said third conductive layer . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US5413961A CLAIM 1 . A method for forming a contact of a semiconductor device having increased packing density , comprising steps of : forming an impurity diffusion region on an isolation region on a substrate ; forming a first insulating layer on the surface of said substrate ; forming a first conductive pattern and a second insulating pattern on the upper portion of said first insulating layer ; forming an etch barrier pattern on the upper portion of said second insulating pattern ; forming a third insulating layer on the upper potion of said etch barrier pattern and said first insulating layer , and etching said third insulating layer to expose the upper portion of said barrier pattern ; forming a photoresist pattern for contact mask on the surfaces of said etch barrier pattern and third insulating layer ; etching said third insulating layer and first insulating layer exposed by said photoresist pattern to form a contact hole having a lower surface being said impurity diffusion region ; forming a spacer along the sidewall of said contact hole ; and forming (anti reflective coating) a second conductive layer on the upper portion of said substrate having said contact hole and etch barrier layer , and patterning said second conductive layer . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5514822A Filed: 1993-10-06 Issued: 1996-05-07 Precursors and processes for making metal oxides (Original Assignee) Symetrix Corp (Current Assignee) Symetrix Corp Michael C. Scott, Carlos A. Paz de Araujo, Larry D. McMillan |
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| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer protects removal of a substrate material by an etch process (dielectric material) . |
US5514822A CLAIM 8 . The precursor as set forth in claim 1 , wherein said electronically competent metal oxide includes a dielectric material (etch process) having a dielectric constant of at least about 166 in combination with a leakage current of at most about 10 -8 amps/cm2 at 1-10 V . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range (boiling point) of about 0 . 16 μm to 0 . 18 μm wide . |
US5514822A CLAIM 1 . A liquid precursor for use in making a solid metal oxide , said precursor comprising : a polyoxyalkylated metal portion having a molecular formula including a metal-oxygen-metal structure ; and a solvent portion forming an essentially liquid solution with said polyoxyalkylated metal portion , said polyoxyalkylated metal portion being present in an effective amount for yielding a corresponding portion of an electronically competent thin-film metal oxide upon liquid deposition of said precursor followed by thermal treatment at effective metal-oxide forming temperatures , said precursor being essentially free of distillable portions having a boiling point (second range) of less than about 115° C . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric (said structure) layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US5514822A CLAIM 9 . A precursor for use in making a solid metal oxide , comprising ; a polyoxyalkylated metal portion having a molecular formula including a metal-oxygen-metal structure wherein at least one metal of said structure (second interlevel dielectric) is bonded to a 2-ethylhexanoate ligand . |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region is a first range of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range (boiling point) of about 0 . 16 μm to 0 . 18 μm wide . |
US5514822A CLAIM 1 . A liquid precursor for use in making a solid metal oxide , said precursor comprising : a polyoxyalkylated metal portion having a molecular formula including a metal-oxygen-metal structure ; and a solvent portion forming an essentially liquid solution with said polyoxyalkylated metal portion , said polyoxyalkylated metal portion being present in an effective amount for yielding a corresponding portion of an electronically competent thin-film metal oxide upon liquid deposition of said precursor followed by thermal treatment at effective metal-oxide forming temperatures , said precursor being essentially free of distillable portions having a boiling point (second range) of less than about 115° C . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5330934A Filed: 1993-06-16 Issued: 1994-07-19 Method of fabricating a semiconductor device having miniaturized contact electrode and wiring structure (Original Assignee) Toshiba Corp (Current Assignee) Toshiba Corp Hideki Shibata, Naoki Ikeda |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch (etching rate) stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5330934A CLAIM 9 . A method according to claim 1 , wherein said interlayer insulating film comprises at least two types of layers having different etching rate (first etch, etch process) s , and in executing etching by an RIE method in said step of selectively forming said first opening , said etching is stopped where said etching rate changes . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch (etching rate) stop layer protects removal of a substrate material by an etch process (etching rate) . |
US5330934A CLAIM 9 . A method according to claim 1 , wherein said interlayer insulating film comprises at least two types of layers having different etching rate (first etch, etch process) s , and in executing etching by an RIE method in said step of selectively forming said first opening , said etching is stopped where said etching rate changes . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch (etching rate) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5330934A CLAIM 9 . A method according to claim 1 , wherein said interlayer insulating film comprises at least two types of layers having different etching rate (first etch, etch process) s , and in executing etching by an RIE method in said step of selectively forming said first opening , said etching is stopped where said etching rate changes . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US5330934A CLAIM 1 . A method of fabricating a semiconductor having a miniaturized contact electrode and wiring structure , comprising the steps of : forming an interlayer insulating film on a semiconductor substrate ; forming a first buffer layer on said interlayer insulating film and a stopper insulating film on said first buffer layer ; selectively forming in said interlayer insulating film a first opening having a bottom inside said interlayer insulating film and shallower than a thickness of said interlayer insulating film ; forming a second buffer layer to cover said first opening and said stopper insulating film ; performing anisotropic etching to leave said second buffer layer on a sidewall of said first opening ; executing anisotropic etching with said first and second buffer layers used as masks to penetrate that part of said bottom of said first opening which is exposed , and forming (anti reflective coating) a second opening to expose a surface of said semiconductor substrate ; filling a wiring conductor in said second opening and said first opening following said second opening ; forming a contact electrode on said wiring conductor filled in said first opening as wide as a width of said first opening ; and depositing a third buffer layer to cover said contact electrode , and performing anisotropic etching to leave said third buffer layer on a sidewall of said contact electrode . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch (etching rate) stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US5330934A CLAIM 9 . A method according to claim 1 , wherein said interlayer insulating film comprises at least two types of layers having different etching rate (first etch, etch process) s , and in executing etching by an RIE method in said step of selectively forming said first opening , said etching is stopped where said etching rate changes . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch (etching rate) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5330934A CLAIM 9 . A method according to claim 1 , wherein said interlayer insulating film comprises at least two types of layers having different etching rate (first etch, etch process) s , and in executing etching by an RIE method in said step of selectively forming said first opening , said etching is stopped where said etching rate changes . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US5330934A CLAIM 1 . A method of fabricating a semiconductor having a miniaturized contact electrode and wiring structure , comprising the steps of : forming an interlayer insulating film on a semiconductor substrate ; forming a first buffer layer on said interlayer insulating film and a stopper insulating film on said first buffer layer ; selectively forming in said interlayer insulating film a first opening having a bottom inside said interlayer insulating film and shallower than a thickness of said interlayer insulating film ; forming a second buffer layer to cover said first opening and said stopper insulating film ; performing anisotropic etching to leave said second buffer layer on a sidewall of said first opening ; executing anisotropic etching with said first and second buffer layers used as masks to penetrate that part of said bottom of said first opening which is exposed , and forming (anti reflective coating) a second opening to expose a surface of said semiconductor substrate ; filling a wiring conductor in said second opening and said first opening following said second opening ; forming a contact electrode on said wiring conductor filled in said first opening as wide as a width of said first opening ; and depositing a third buffer layer to cover said contact electrode , and performing anisotropic etching to leave said third buffer layer on a sidewall of said contact electrode . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5346585A Filed: 1993-04-20 Issued: 1994-09-13 Use of a faceted etch process to eliminate stringers (Original Assignee) Micron Semiconductor Inc (Current Assignee) Micron Technology Inc Trung T. Doan, Guy T. Blalock |
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| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer protects removal of a substrate material (active ion) by an etch process . |
US5346585A CLAIM 11 . The process according to claim 10 , wherein said plasma is generated in a reactive ion (substrate material) etcher . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space (said sub) in a portion of said first sub interlevel dielectric layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range (second material) of about 0 . 16 μm to 0 . 18 μm wide . |
US5346585A CLAIM 12 . A method for etching relatively closely spaced features , said method comprising the following steps of : disposing a substrate in a reactor , said sub (first space) strate having closely spaced features disposed thereon , said features being covered by a first material ; and creating an atmosphere in said reactor , said atmosphere comprising ions , said ions preferentially removing said first material , thereby creating facets in said first material ; disposing a second material (second range) superjacent said first material ; and substantially removing a portion of said second material located between said features . |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region is a first range of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range (second material) of about 0 . 16 μm to 0 . 18 μm wide . |
US5346585A CLAIM 12 . A method for etching relatively closely spaced features , said method comprising the following steps of : disposing a substrate in a reactor , said substrate having closely spaced features disposed thereon , said features being covered by a first material ; and creating an atmosphere in said reactor , said atmosphere comprising ions , said ions preferentially removing said first material , thereby creating facets in said first material ; disposing a second material (second range) superjacent said first material ; and substantially removing a portion of said second material located between said features . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5338700A Filed: 1993-04-14 Issued: 1994-08-16 Method of forming a bit line over capacitor array of memory cells (Original Assignee) Micron Semiconductor Inc (Current Assignee) Micron Technology Inc Charles H. Dennison, Aftab Ahmad |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region (second contact) coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch (remaining portions, memory array) stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (oxidation barrier layer) layer over said first etch stop layer ; a second etch (second thickness) stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5338700A CLAIM 2 . The method of forming a bit line over capacitor array of memory cells of claim 1 wherein the first conductive material pillars have an upper surface area and the bit line contact openings have an open cross section , and wherein the step of providing bit line contact openings comprises photopatterning and etching , the method further comprising : fabricating the surface area of individual first conductive material pillars to be greater than the open cross section of individual bit line contact openings to substantially assure complete overlap of the individual bit line contact openings relative to the individual first conductive material pillar surface areas ; and photopatterning and etching area on the wafer peripheral to the memory array (first etch, first etch stop layer) in the same step in which the bit line contact openings are photopatterned and etched . US5338700A CLAIM 6 . The method of forming a bit line over capacitor array of memory cells of claim 3 wherein the material of the first conductive pillars and the material of the conductive layer provided over the covering layer comprises conductively doped polysilicon , and the method further comprising : providing an electrically insulative nitride oxidation barrier layer (interlevel dielectric) atop the cell capacitor layer to a thickness of from about 150 Angstroms to about 1500 Angstroms prior to providing the overlying insulating layer , the step of electrically insulating the exposed edges comprising exposing the wafer to an oxidizing ambient to oxidize the cell polysilicon exposed edges , the nitride oxidation barrier layer during such oxidation exposure inhibiting oxidation of the outer surface of the cell polysilicon layer . US5338700A CLAIM 14 . The semiconductor processing method of forming a memory cell of claim 12 wherein the base layer of insulating material is not homogeneous , the uppermost region being formed of a different material from remaining portions (first etch, first etch stop layer) of the base layer . US5338700A CLAIM 24 . A method of forming a bit line over capacitor array of memory cells comprising : providing an array of substantially electrically isolated word lines atop a semiconductor wafer ; providing active areas about the word lines to define an array of memory cell FETs , the active areas being defined by a first active region for electrical connection with a memory cell capacitor and a second active region for electrical connection with a bit line ; providing a planarized first layer of an insulating material over the word lines and active areas , the planarized layer of insulating material having an upper surface which is above the word lines ; providing first contact openings through the first layer of insulating material to second active regions ; providing second contact (contact region) openings through the first layer of insulating material to first active regions ; providing first conductive material pillars within the first contact openings , the first pillars having upper surfaces which are elevationally above the word lines ; providing second conductive material pillars within the second contact openings , the second pillars having upper surfaces which are elevationally above the word lines ; providing a covering layer of insulating material over the planarized first layer of insulating material and first and second pillars ; providing capacitor contact openings through the covering layer to the second pillar upper surfaces ; providing a layer of conductive material over the covering layer of insulating material and within the capacitor contact openings , the layer of conductive material having an outer surface ; removing conductive material from atop the covering layer to define isolated cell storage node containers electrically connecting with the first active regions ; providing a capacitor cell dielectric layer on the wafer atop the isolated storage nodes , insulating material of the covering layer being interposed between the first pillar upper surfaces and the capacitor cell dielectric layer ; providing a conductive capacitor cell layer atop the capacitor cell dielectric layer to define an array of memory cell capacitors ; providing an overlying layer of insulating material over the conductive capacitor cell layer ; providing bit line contact openings through the overlying layer , conductive capacitor cell layer , cell capacitor dielectric layer and covering layer to the first pillar upper surfaces , the bit line contact openings having sidewalls , the bit line contact opening sidewalls including exposed edges of the conductive capacitor cell layer ; electrically insulating exposed edges of the conductive capacitor cell layer within the bit line contact openings ; and after electrically insulating the exposed edges , providing a digit line layer of conductive material atop the wafer and within the bit line contact openings , the digit line layer electrically connecting with the first pillar upper surfaces . US5338700A CLAIM 31 . The method of forming a bit line over capacitor array of memory cells of claim 28 wherein , individual memory cell capacitors of the array are defined by an outwardly projecting container structure having a projecting outermost surface ; the planarized base layer is provided to a first thickness and the overlying layer is provided to a second thickness (second etch, second sub, second etch stop layer) above an outermost projecting surface of the container , the second thickness being greater than the first thickness ; and the step of providing bit line contact openings comprises : providing preliminary bit line contact openings through the overlying layer , conductive capacitor cell layer , and cell capacitor dielectric layer over the first pillars , the preliminary bit line contact openings having sidewalls , the preliminary bit line contact opening sidewalls including the exposed edges of the conductive capacitor cell layer ; and blanket etching without photomasking the base layer and overlying layer to extend the preliminary bit line contact to the first pillar upper surfaces , and leaving insulating material of the overlying layer atop the projecting outermost surfaces . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch (remaining portions, memory array) stop layer protects removal of a substrate material by an etch process . |
US5338700A CLAIM 2 . The method of forming a bit line over capacitor array of memory cells of claim 1 wherein the first conductive material pillars have an upper surface area and the bit line contact openings have an open cross section , and wherein the step of providing bit line contact openings comprises photopatterning and etching , the method further comprising : fabricating the surface area of individual first conductive material pillars to be greater than the open cross section of individual bit line contact openings to substantially assure complete overlap of the individual bit line contact openings relative to the individual first conductive material pillar surface areas ; and photopatterning and etching area on the wafer peripheral to the memory array (first etch, first etch stop layer) in the same step in which the bit line contact openings are photopatterned and etched . US5338700A CLAIM 14 . The semiconductor processing method of forming a memory cell of claim 12 wherein the base layer of insulating material is not homogeneous , the uppermost region being formed of a different material from remaining portions (first etch, first etch stop layer) of the base layer . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (oxidation barrier layer) layer insulates said contact region (second contact) . |
US5338700A CLAIM 6 . The method of forming a bit line over capacitor array of memory cells of claim 3 wherein the material of the first conductive pillars and the material of the conductive layer provided over the covering layer comprises conductively doped polysilicon , and the method further comprising : providing an electrically insulative nitride oxidation barrier layer (interlevel dielectric) atop the cell capacitor layer to a thickness of from about 150 Angstroms to about 1500 Angstroms prior to providing the overlying insulating layer , the step of electrically insulating the exposed edges comprising exposing the wafer to an oxidizing ambient to oxidize the cell polysilicon exposed edges , the nitride oxidation barrier layer during such oxidation exposure inhibiting oxidation of the outer surface of the cell polysilicon layer . US5338700A CLAIM 24 . A method of forming a bit line over capacitor array of memory cells comprising : providing an array of substantially electrically isolated word lines atop a semiconductor wafer ; providing active areas about the word lines to define an array of memory cell FETs , the active areas being defined by a first active region for electrical connection with a memory cell capacitor and a second active region for electrical connection with a bit line ; providing a planarized first layer of an insulating material over the word lines and active areas , the planarized layer of insulating material having an upper surface which is above the word lines ; providing first contact openings through the first layer of insulating material to second active regions ; providing second contact (contact region) openings through the first layer of insulating material to first active regions ; providing first conductive material pillars within the first contact openings , the first pillars having upper surfaces which are elevationally above the word lines ; providing second conductive material pillars within the second contact openings , the second pillars having upper surfaces which are elevationally above the word lines ; providing a covering layer of insulating material over the planarized first layer of insulating material and first and second pillars ; providing capacitor contact openings through the covering layer to the second pillar upper surfaces ; providing a layer of conductive material over the covering layer of insulating material and within the capacitor contact openings , the layer of conductive material having an outer surface ; removing conductive material from atop the covering layer to define isolated cell storage node containers electrically connecting with the first active regions ; providing a capacitor cell dielectric layer on the wafer atop the isolated storage nodes , insulating material of the covering layer being interposed between the first pillar upper surfaces and the capacitor cell dielectric layer ; providing a conductive capacitor cell layer atop the capacitor cell dielectric layer to define an array of memory cell capacitors ; providing an overlying layer of insulating material over the conductive capacitor cell layer ; providing bit line contact openings through the overlying layer , conductive capacitor cell layer , cell capacitor dielectric layer and covering layer to the first pillar upper surfaces , the bit line contact openings having sidewalls , the bit line contact opening sidewalls including exposed edges of the conductive capacitor cell layer ; electrically insulating exposed edges of the conductive capacitor cell layer within the bit line contact openings ; and after electrically insulating the exposed edges , providing a digit line layer of conductive material atop the wafer and within the bit line contact openings , the digit line layer electrically connecting with the first pillar upper surfaces . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch (second thickness) stop layer protects lower layers during an etching process (doped polysilicon) . |
US5338700A CLAIM 5 . The method of forming a bit line over capacitor array of memory cells of claim 3 wherein the material of the first conductive pillars and the material of the conductive layer provided over the covering layer comprises conductively doped polysilicon (etching process) . US5338700A CLAIM 31 . The method of forming a bit line over capacitor array of memory cells of claim 28 wherein , individual memory cell capacitors of the array are defined by an outwardly projecting container structure having a projecting outermost surface ; the planarized base layer is provided to a first thickness and the overlying layer is provided to a second thickness (second etch, second sub, second etch stop layer) above an outermost projecting surface of the container , the second thickness being greater than the first thickness ; and the step of providing bit line contact openings comprises : providing preliminary bit line contact openings through the overlying layer , conductive capacitor cell layer , and cell capacitor dielectric layer over the first pillars , the preliminary bit line contact openings having sidewalls , the preliminary bit line contact opening sidewalls including the exposed edges of the conductive capacitor cell layer ; and blanket etching without photomasking the base layer and overlying layer to extend the preliminary bit line contact to the first pillar upper surfaces , and leaving insulating material of the overlying layer atop the projecting outermost surfaces . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (oxidation barrier layer) layer insulates said contact region (second contact) . |
US5338700A CLAIM 6 . The method of forming a bit line over capacitor array of memory cells of claim 3 wherein the material of the first conductive pillars and the material of the conductive layer provided over the covering layer comprises conductively doped polysilicon , and the method further comprising : providing an electrically insulative nitride oxidation barrier layer (interlevel dielectric) atop the cell capacitor layer to a thickness of from about 150 Angstroms to about 1500 Angstroms prior to providing the overlying insulating layer , the step of electrically insulating the exposed edges comprising exposing the wafer to an oxidizing ambient to oxidize the cell polysilicon exposed edges , the nitride oxidation barrier layer during such oxidation exposure inhibiting oxidation of the outer surface of the cell polysilicon layer . US5338700A CLAIM 31 . The method of forming a bit line over capacitor array of memory cells of claim 28 wherein , individual memory cell capacitors of the array are defined by an outwardly projecting container structure having a projecting outermost surface ; the planarized base layer is provided to a first thickness and the overlying layer is provided to a second thickness (second etch, second sub, second etch stop layer) above an outermost projecting surface of the container , the second thickness being greater than the first thickness ; and the step of providing bit line contact openings comprises : providing preliminary bit line contact openings through the overlying layer , conductive capacitor cell layer , and cell capacitor dielectric layer over the first pillars , the preliminary bit line contact openings having sidewalls , the preliminary bit line contact opening sidewalls including the exposed edges of the conductive capacitor cell layer ; and blanket etching without photomasking the base layer and overlying layer to extend the preliminary bit line contact to the first pillar upper surfaces , and leaving insulating material of the overlying layer atop the projecting outermost surfaces . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch (remaining portions, memory array) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (oxidation barrier layer) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (second thickness) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5338700A CLAIM 2 . The method of forming a bit line over capacitor array of memory cells of claim 1 wherein the first conductive material pillars have an upper surface area and the bit line contact openings have an open cross section , and wherein the step of providing bit line contact openings comprises photopatterning and etching , the method further comprising : fabricating the surface area of individual first conductive material pillars to be greater than the open cross section of individual bit line contact openings to substantially assure complete overlap of the individual bit line contact openings relative to the individual first conductive material pillar surface areas ; and photopatterning and etching area on the wafer peripheral to the memory array (first etch, first etch stop layer) in the same step in which the bit line contact openings are photopatterned and etched . US5338700A CLAIM 6 . The method of forming a bit line over capacitor array of memory cells of claim 3 wherein the material of the first conductive pillars and the material of the conductive layer provided over the covering layer comprises conductively doped polysilicon , and the method further comprising : providing an electrically insulative nitride oxidation barrier layer (interlevel dielectric) atop the cell capacitor layer to a thickness of from about 150 Angstroms to about 1500 Angstroms prior to providing the overlying insulating layer , the step of electrically insulating the exposed edges comprising exposing the wafer to an oxidizing ambient to oxidize the cell polysilicon exposed edges , the nitride oxidation barrier layer during such oxidation exposure inhibiting oxidation of the outer surface of the cell polysilicon layer . US5338700A CLAIM 14 . The semiconductor processing method of forming a memory cell of claim 12 wherein the base layer of insulating material is not homogeneous , the uppermost region being formed of a different material from remaining portions (first etch, first etch stop layer) of the base layer . US5338700A CLAIM 31 . The method of forming a bit line over capacitor array of memory cells of claim 28 wherein , individual memory cell capacitors of the array are defined by an outwardly projecting container structure having a projecting outermost surface ; the planarized base layer is provided to a first thickness and the overlying layer is provided to a second thickness (second etch, second sub, second etch stop layer) above an outermost projecting surface of the container , the second thickness being greater than the first thickness ; and the step of providing bit line contact openings comprises : providing preliminary bit line contact openings through the overlying layer , conductive capacitor cell layer , and cell capacitor dielectric layer over the first pillars , the preliminary bit line contact openings having sidewalls , the preliminary bit line contact opening sidewalls including the exposed edges of the conductive capacitor cell layer ; and blanket etching without photomasking the base layer and overlying layer to extend the preliminary bit line contact to the first pillar upper surfaces , and leaving insulating material of the overlying layer atop the projecting outermost surfaces . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric (oxidation barrier layer) layer for said contact region (second contact) is in a first range (such oxidation) of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5338700A CLAIM 6 . The method of forming a bit line over capacitor array of memory cells of claim 3 wherein the material of the first conductive pillars and the material of the conductive layer provided over the covering layer comprises conductively doped polysilicon , and the method further comprising : providing an electrically insulative nitride oxidation barrier layer (interlevel dielectric) atop the cell capacitor layer to a thickness of from about 150 Angstroms to about 1500 Angstroms prior to providing the overlying insulating layer , the step of electrically insulating the exposed edges comprising exposing the wafer to an oxidizing ambient to oxidize the cell polysilicon exposed edges , the nitride oxidation barrier layer during such oxidation (first range) exposure inhibiting oxidation of the outer surface of the cell polysilicon layer . US5338700A CLAIM 31 . The method of forming a bit line over capacitor array of memory cells of claim 28 wherein , individual memory cell capacitors of the array are defined by an outwardly projecting container structure having a projecting outermost surface ; the planarized base layer is provided to a first thickness and the overlying layer is provided to a second thickness (second etch, second sub, second etch stop layer) above an outermost projecting surface of the container , the second thickness being greater than the first thickness ; and the step of providing bit line contact openings comprises : providing preliminary bit line contact openings through the overlying layer , conductive capacitor cell layer , and cell capacitor dielectric layer over the first pillars , the preliminary bit line contact openings having sidewalls , the preliminary bit line contact opening sidewalls including the exposed edges of the conductive capacitor cell layer ; and blanket etching without photomasking the base layer and overlying layer to extend the preliminary bit line contact to the first pillar upper surfaces , and leaving insulating material of the overlying layer atop the projecting outermost surfaces . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch (remaining portions, memory array) stop layer and a second etch (second thickness) stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region (second contact) and under a first sub interlevel dielectric (oxidation barrier layer) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US5338700A CLAIM 2 . The method of forming a bit line over capacitor array of memory cells of claim 1 wherein the first conductive material pillars have an upper surface area and the bit line contact openings have an open cross section , and wherein the step of providing bit line contact openings comprises photopatterning and etching , the method further comprising : fabricating the surface area of individual first conductive material pillars to be greater than the open cross section of individual bit line contact openings to substantially assure complete overlap of the individual bit line contact openings relative to the individual first conductive material pillar surface areas ; and photopatterning and etching area on the wafer peripheral to the memory array (first etch, first etch stop layer) in the same step in which the bit line contact openings are photopatterned and etched . US5338700A CLAIM 6 . The method of forming a bit line over capacitor array of memory cells of claim 3 wherein the material of the first conductive pillars and the material of the conductive layer provided over the covering layer comprises conductively doped polysilicon , and the method further comprising : providing an electrically insulative nitride oxidation barrier layer (interlevel dielectric) atop the cell capacitor layer to a thickness of from about 150 Angstroms to about 1500 Angstroms prior to providing the overlying insulating layer , the step of electrically insulating the exposed edges comprising exposing the wafer to an oxidizing ambient to oxidize the cell polysilicon exposed edges , the nitride oxidation barrier layer during such oxidation exposure inhibiting oxidation of the outer surface of the cell polysilicon layer . US5338700A CLAIM 14 . The semiconductor processing method of forming a memory cell of claim 12 wherein the base layer of insulating material is not homogeneous , the uppermost region being formed of a different material from remaining portions (first etch, first etch stop layer) of the base layer . US5338700A CLAIM 31 . The method of forming a bit line over capacitor array of memory cells of claim 28 wherein , individual memory cell capacitors of the array are defined by an outwardly projecting container structure having a projecting outermost surface ; the planarized base layer is provided to a first thickness and the overlying layer is provided to a second thickness (second etch, second sub, second etch stop layer) above an outermost projecting surface of the container , the second thickness being greater than the first thickness ; and the step of providing bit line contact openings comprises : providing preliminary bit line contact openings through the overlying layer , conductive capacitor cell layer , and cell capacitor dielectric layer over the first pillars , the preliminary bit line contact openings having sidewalls , the preliminary bit line contact opening sidewalls including the exposed edges of the conductive capacitor cell layer ; and blanket etching without photomasking the base layer and overlying layer to extend the preliminary bit line contact to the first pillar upper surfaces , and leaving insulating material of the overlying layer atop the projecting outermost surfaces . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch (remaining portions, memory array) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (oxidation barrier layer) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (second thickness) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5338700A CLAIM 2 . The method of forming a bit line over capacitor array of memory cells of claim 1 wherein the first conductive material pillars have an upper surface area and the bit line contact openings have an open cross section , and wherein the step of providing bit line contact openings comprises photopatterning and etching , the method further comprising : fabricating the surface area of individual first conductive material pillars to be greater than the open cross section of individual bit line contact openings to substantially assure complete overlap of the individual bit line contact openings relative to the individual first conductive material pillar surface areas ; and photopatterning and etching area on the wafer peripheral to the memory array (first etch, first etch stop layer) in the same step in which the bit line contact openings are photopatterned and etched . US5338700A CLAIM 6 . The method of forming a bit line over capacitor array of memory cells of claim 3 wherein the material of the first conductive pillars and the material of the conductive layer provided over the covering layer comprises conductively doped polysilicon , and the method further comprising : providing an electrically insulative nitride oxidation barrier layer (interlevel dielectric) atop the cell capacitor layer to a thickness of from about 150 Angstroms to about 1500 Angstroms prior to providing the overlying insulating layer , the step of electrically insulating the exposed edges comprising exposing the wafer to an oxidizing ambient to oxidize the cell polysilicon exposed edges , the nitride oxidation barrier layer during such oxidation exposure inhibiting oxidation of the outer surface of the cell polysilicon layer . US5338700A CLAIM 14 . The semiconductor processing method of forming a memory cell of claim 12 wherein the base layer of insulating material is not homogeneous , the uppermost region being formed of a different material from remaining portions (first etch, first etch stop layer) of the base layer . US5338700A CLAIM 31 . The method of forming a bit line over capacitor array of memory cells of claim 28 wherein , individual memory cell capacitors of the array are defined by an outwardly projecting container structure having a projecting outermost surface ; the planarized base layer is provided to a first thickness and the overlying layer is provided to a second thickness (second etch, second sub, second etch stop layer) above an outermost projecting surface of the container , the second thickness being greater than the first thickness ; and the step of providing bit line contact openings comprises : providing preliminary bit line contact openings through the overlying layer , conductive capacitor cell layer , and cell capacitor dielectric layer over the first pillars , the preliminary bit line contact openings having sidewalls , the preliminary bit line contact opening sidewalls including the exposed edges of the conductive capacitor cell layer ; and blanket etching without photomasking the base layer and overlying layer to extend the preliminary bit line contact to the first pillar upper surfaces , and leaving insulating material of the overlying layer atop the projecting outermost surfaces . |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region (second contact) is a first range (such oxidation) of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5338700A CLAIM 6 . The method of forming a bit line over capacitor array of memory cells of claim 3 wherein the material of the first conductive pillars and the material of the conductive layer provided over the covering layer comprises conductively doped polysilicon , and the method further comprising : providing an electrically insulative nitride oxidation barrier layer atop the cell capacitor layer to a thickness of from about 150 Angstroms to about 1500 Angstroms prior to providing the overlying insulating layer , the step of electrically insulating the exposed edges comprising exposing the wafer to an oxidizing ambient to oxidize the cell polysilicon exposed edges , the nitride oxidation barrier layer during such oxidation (first range) exposure inhibiting oxidation of the outer surface of the cell polysilicon layer . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5356834A Filed: 1993-03-23 Issued: 1994-10-18 Method of forming contact windows in semiconductor devices (Original Assignee) Toshiba Corp (Current Assignee) Toshiba Corp Shigeki Sugimoto, Katsuya Okumura |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch (said second pattern) stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5356834A CLAIM 13 . A manufacturing method of semiconductor devices , comprising the steps of : forming a plurality of first pattern portions containing first-level internal wiring layers over a semiconductor substrate ; forming first interlayer insulating films for insulating said internal wiring layers from each other over said semiconductor substrate ; forming a plurality of second pattern portions containing second-level internal wiring layers over said first interlayer insulating films ; forming second interlayer insulating films for insulating said second-level internal wiring layers from each other over said semiconductor substrate ; forming an opening portion , penetrating through said second interlayer insulating films and said first interlayer insulating films , which allows said substrate , at least one of said first pattern portions and at least one of said second pattern (multiple etch) portions to appear ; and forming a sidewall insulating film on each of the sidewalls of at least one of said first pattern portions and at least one of said second pattern portions appearing in said opening portion . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space (said sub) in a portion of said first sub interlevel dielectric layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5356834A CLAIM 1 . A manufacturing method of semiconductor devices , comprising the steps of : forming a plurality of pattern portions containing internal wiring layers over a semiconductor substrate ; forming interlayer insulating films for insulating said internal wiring layers from each other over said semiconductor substrate ; forming an opening portion , in said interlayer insulating films , which allows said sub (first space) strate and at least one of said pattern portions to appear ; and forming a sidewall insulating film on the sidewall of at least one of said pattern portions appearing in said opening portion . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US5356834A CLAIM 1 . A manufacturing method of semiconductor devices , comprising the steps of : forming a plurality of pattern portions containing internal wiring layers over a semiconductor substrate ; forming interlayer insulating films for insulating said internal wiring layers from each other over said semiconductor substrate ; forming an opening portion , in said interlayer insulating films , which allows said substrate and at least one of said pattern portions to appear ; and forming (anti reflective coating) a sidewall insulating film on the sidewall of at least one of said pattern portions appearing in said opening portion . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch (said second pattern) stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US5356834A CLAIM 13 . A manufacturing method of semiconductor devices , comprising the steps of : forming a plurality of first pattern portions containing first-level internal wiring layers over a semiconductor substrate ; forming first interlayer insulating films for insulating said internal wiring layers from each other over said semiconductor substrate ; forming a plurality of second pattern portions containing second-level internal wiring layers over said first interlayer insulating films ; forming second interlayer insulating films for insulating said second-level internal wiring layers from each other over said semiconductor substrate ; forming an opening portion , penetrating through said second interlayer insulating films and said first interlayer insulating films , which allows said substrate , at least one of said first pattern portions and at least one of said second pattern (multiple etch) portions to appear ; and forming a sidewall insulating film on each of the sidewalls of at least one of said first pattern portions and at least one of said second pattern portions appearing in said opening portion . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US5356834A CLAIM 1 . A manufacturing method of semiconductor devices , comprising the steps of : forming a plurality of pattern portions containing internal wiring layers over a semiconductor substrate ; forming interlayer insulating films for insulating said internal wiring layers from each other over said semiconductor substrate ; forming an opening portion , in said interlayer insulating films , which allows said substrate and at least one of said pattern portions to appear ; and forming (anti reflective coating) a sidewall insulating film on the sidewall of at least one of said pattern portions appearing in said opening portion . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5279989A Filed: 1993-03-01 Issued: 1994-01-18 Method for forming miniature contacts of highly integrated semiconductor devices (Original Assignee) SK Hynix Inc (Current Assignee) SK Hynix Inc Jeong Kim |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region (gate electrodes) such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch (second polysilicon layer, first polysilicon layer, etched portion) stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (contact hole) layer over said first etch stop layer ; a second etch (gate oxide) stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5279989A CLAIM 1 . A method for forming contacts of a highly integrated semiconductor device comprising the steps of forming over a silicon substrate an element isolation oxide film , a gate oxide (second etch) film , and a plurality of MOSFETs each including gate electrodes (spacer region) , a source and a drain , forming a first insulation layer over the gate electrodes , removing partially the first insulation layer at its portions disposed over the sources and drains of said plurality of MOSFETs to form contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) s , and forming a conductive layer in contact with the sources and drains exposed through the contact holes , the method comprising the further step of forming miniature contacts over the sources and drains , said further step comprising the steps of : coating a thick second insulation layer as a smoothing layer over the first insulation layer including the MOSFETs and coating over the second insulation layer a first polysilicon layer (first etch) , a third insulation layer and a photoresist film , in this order ; removing the photoresist film at its portions disposed above the sources and drains to form a photoresist film pattern and etching the third insulation layer at its portions exposed through the removed portions of the photoresist film to form a third insulation layer pattern ; removing the photoresist film pattern and forming spacers of a fourth insulation layer on side walls of the third insulation layer pattern ; etching the first polysilicon layer at its portions exposed through the removed portions of the third insulation layer , under a condition of using both the third insulation layer pattern and the fourth insulation layer spacers as a mask , to form a first polysilicon layer pattern ; removing the third insulation layer pattern and the fourth insulation layer spacers , etching the second insulation layer at its portion exposed through the removed third insulation layer pattern and fourth insulation layer spacers , under a condition of using the first polysilicon layer pattern as a mask , and etching the first insulation layer at its portion exposed through the etched portion (first etch) s of the second insulation layer , to form contact holes through which the sources and drains are exposed ; depositing over the contact holes and the first polysilicon layer pattern a second polysilicon layer (first etch) with a smooth upper surface and removing a portion of the second polysilicon layer and the first polysilicon layer pattern to form contact pads respectively connected to the sources and drains ; and applying conductive layers for selected electrodes or wirings to the contact pads . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch (second polysilicon layer, first polysilicon layer, etched portion) stop layer protects removal of a substrate material by an etch process . |
US5279989A CLAIM 1 . A method for forming contacts of a highly integrated semiconductor device comprising the steps of forming over a silicon substrate an element isolation oxide film , a gate oxide film , and a plurality of MOSFETs each including gate electrodes , a source and a drain , forming a first insulation layer over the gate electrodes , removing partially the first insulation layer at its portions disposed over the sources and drains of said plurality of MOSFETs to form contact holes , and forming a conductive layer in contact with the sources and drains exposed through the contact holes , the method comprising the further step of forming miniature contacts over the sources and drains , said further step comprising the steps of : coating a thick second insulation layer as a smoothing layer over the first insulation layer including the MOSFETs and coating over the second insulation layer a first polysilicon layer (first etch) , a third insulation layer and a photoresist film , in this order ; removing the photoresist film at its portions disposed above the sources and drains to form a photoresist film pattern and etching the third insulation layer at its portions exposed through the removed portions of the photoresist film to form a third insulation layer pattern ; removing the photoresist film pattern and forming spacers of a fourth insulation layer on side walls of the third insulation layer pattern ; etching the first polysilicon layer at its portions exposed through the removed portions of the third insulation layer , under a condition of using both the third insulation layer pattern and the fourth insulation layer spacers as a mask , to form a first polysilicon layer pattern ; removing the third insulation layer pattern and the fourth insulation layer spacers , etching the second insulation layer at its portion exposed through the removed third insulation layer pattern and fourth insulation layer spacers , under a condition of using the first polysilicon layer pattern as a mask , and etching the first insulation layer at its portion exposed through the etched portion (first etch) s of the second insulation layer , to form contact holes through which the sources and drains are exposed ; depositing over the contact holes and the first polysilicon layer pattern a second polysilicon layer (first etch) with a smooth upper surface and removing a portion of the second polysilicon layer and the first polysilicon layer pattern to form contact pads respectively connected to the sources and drains ; and applying conductive layers for selected electrodes or wirings to the contact pads . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (contact hole) layer insulates said contact region . |
US5279989A CLAIM 1 . A method for forming contacts of a highly integrated semiconductor device comprising the steps of forming over a silicon substrate an element isolation oxide film , a gate oxide film , and a plurality of MOSFETs each including gate electrodes , a source and a drain , forming a first insulation layer over the gate electrodes , removing partially the first insulation layer at its portions disposed over the sources and drains of said plurality of MOSFETs to form contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) s , and forming a conductive layer in contact with the sources and drains exposed through the contact holes , the method comprising the further step of forming miniature contacts over the sources and drains , said further step comprising the steps of : coating a thick second insulation layer as a smoothing layer over the first insulation layer including the MOSFETs and coating over the second insulation layer a first polysilicon layer , a third insulation layer and a photoresist film , in this order ; removing the photoresist film at its portions disposed above the sources and drains to form a photoresist film pattern and etching the third insulation layer at its portions exposed through the removed portions of the photoresist film to form a third insulation layer pattern ; removing the photoresist film pattern and forming spacers of a fourth insulation layer on side walls of the third insulation layer pattern ; etching the first polysilicon layer at its portions exposed through the removed portions of the third insulation layer , under a condition of using both the third insulation layer pattern and the fourth insulation layer spacers as a mask , to form a first polysilicon layer pattern ; removing the third insulation layer pattern and the fourth insulation layer spacers , etching the second insulation layer at its portion exposed through the removed third insulation layer pattern and fourth insulation layer spacers , under a condition of using the first polysilicon layer pattern as a mask , and etching the first insulation layer at its portion exposed through the etched portions of the second insulation layer , to form contact holes through which the sources and drains are exposed ; depositing over the contact holes and the first polysilicon layer pattern a second polysilicon layer with a smooth upper surface and removing a portion of the second polysilicon layer and the first polysilicon layer pattern to form contact pads respectively connected to the sources and drains ; and applying conductive layers for selected electrodes or wirings to the contact pads . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch (gate oxide) stop layer protects lower layers during an etching process . |
US5279989A CLAIM 1 . A method for forming contacts of a highly integrated semiconductor device comprising the steps of forming over a silicon substrate an element isolation oxide film , a gate oxide (second etch) film , and a plurality of MOSFETs each including gate electrodes , a source and a drain , forming a first insulation layer over the gate electrodes , removing partially the first insulation layer at its portions disposed over the sources and drains of said plurality of MOSFETs to form contact holes , and forming a conductive layer in contact with the sources and drains exposed through the contact holes , the method comprising the further step of forming miniature contacts over the sources and drains , said further step comprising the steps of : coating a thick second insulation layer as a smoothing layer over the first insulation layer including the MOSFETs and coating over the second insulation layer a first polysilicon layer , a third insulation layer and a photoresist film , in this order ; removing the photoresist film at its portions disposed above the sources and drains to form a photoresist film pattern and etching the third insulation layer at its portions exposed through the removed portions of the photoresist film to form a third insulation layer pattern ; removing the photoresist film pattern and forming spacers of a fourth insulation layer on side walls of the third insulation layer pattern ; etching the first polysilicon layer at its portions exposed through the removed portions of the third insulation layer , under a condition of using both the third insulation layer pattern and the fourth insulation layer spacers as a mask , to form a first polysilicon layer pattern ; removing the third insulation layer pattern and the fourth insulation layer spacers , etching the second insulation layer at its portion exposed through the removed third insulation layer pattern and fourth insulation layer spacers , under a condition of using the first polysilicon layer pattern as a mask , and etching the first insulation layer at its portion exposed through the etched portions of the second insulation layer , to form contact holes through which the sources and drains are exposed ; depositing over the contact holes and the first polysilicon layer pattern a second polysilicon layer with a smooth upper surface and removing a portion of the second polysilicon layer and the first polysilicon layer pattern to form contact pads respectively connected to the sources and drains ; and applying conductive layers for selected electrodes or wirings to the contact pads . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (contact hole) layer insulates said contact region . |
US5279989A CLAIM 1 . A method for forming contacts of a highly integrated semiconductor device comprising the steps of forming over a silicon substrate an element isolation oxide film , a gate oxide film , and a plurality of MOSFETs each including gate electrodes , a source and a drain , forming a first insulation layer over the gate electrodes , removing partially the first insulation layer at its portions disposed over the sources and drains of said plurality of MOSFETs to form contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) s , and forming a conductive layer in contact with the sources and drains exposed through the contact holes , the method comprising the further step of forming miniature contacts over the sources and drains , said further step comprising the steps of : coating a thick second insulation layer as a smoothing layer over the first insulation layer including the MOSFETs and coating over the second insulation layer a first polysilicon layer , a third insulation layer and a photoresist film , in this order ; removing the photoresist film at its portions disposed above the sources and drains to form a photoresist film pattern and etching the third insulation layer at its portions exposed through the removed portions of the photoresist film to form a third insulation layer pattern ; removing the photoresist film pattern and forming spacers of a fourth insulation layer on side walls of the third insulation layer pattern ; etching the first polysilicon layer at its portions exposed through the removed portions of the third insulation layer , under a condition of using both the third insulation layer pattern and the fourth insulation layer spacers as a mask , to form a first polysilicon layer pattern ; removing the third insulation layer pattern and the fourth insulation layer spacers , etching the second insulation layer at its portion exposed through the removed third insulation layer pattern and fourth insulation layer spacers , under a condition of using the first polysilicon layer pattern as a mask , and etching the first insulation layer at its portion exposed through the etched portions of the second insulation layer , to form contact holes through which the sources and drains are exposed ; depositing over the contact holes and the first polysilicon layer pattern a second polysilicon layer with a smooth upper surface and removing a portion of the second polysilicon layer and the first polysilicon layer pattern to form contact pads respectively connected to the sources and drains ; and applying conductive layers for selected electrodes or wirings to the contact pads . |
| US7977797B2 CLAIM 6 . An integrated circuit of claim 1 wherein said spacer region (gate electrodes) insulates said contact region . |
US5279989A CLAIM 1 . A method for forming contacts of a highly integrated semiconductor device comprising the steps of forming over a silicon substrate an element isolation oxide film , a gate oxide film , and a plurality of MOSFETs each including gate electrodes (spacer region) , a source and a drain , forming a first insulation layer over the gate electrodes , removing partially the first insulation layer at its portions disposed over the sources and drains of said plurality of MOSFETs to form contact holes , and forming a conductive layer in contact with the sources and drains exposed through the contact holes , the method comprising the further step of forming miniature contacts over the sources and drains , said further step comprising the steps of : coating a thick second insulation layer as a smoothing layer over the first insulation layer including the MOSFETs and coating over the second insulation layer a first polysilicon layer , a third insulation layer and a photoresist film , in this order ; removing the photoresist film at its portions disposed above the sources and drains to form a photoresist film pattern and etching the third insulation layer at its portions exposed through the removed portions of the photoresist film to form a third insulation layer pattern ; removing the photoresist film pattern and forming spacers of a fourth insulation layer on side walls of the third insulation layer pattern ; etching the first polysilicon layer at its portions exposed through the removed portions of the third insulation layer , under a condition of using both the third insulation layer pattern and the fourth insulation layer spacers as a mask , to form a first polysilicon layer pattern ; removing the third insulation layer pattern and the fourth insulation layer spacers , etching the second insulation layer at its portion exposed through the removed third insulation layer pattern and fourth insulation layer spacers , under a condition of using the first polysilicon layer pattern as a mask , and etching the first insulation layer at its portion exposed through the etched portions of the second insulation layer , to form contact holes through which the sources and drains are exposed ; depositing over the contact holes and the first polysilicon layer pattern a second polysilicon layer with a smooth upper surface and removing a portion of the second polysilicon layer and the first polysilicon layer pattern to form contact pads respectively connected to the sources and drains ; and applying conductive layers for selected electrodes or wirings to the contact pads . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch (second polysilicon layer, first polysilicon layer, etched portion) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (contact hole) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (gate oxide) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5279989A CLAIM 1 . A method for forming contacts of a highly integrated semiconductor device comprising the steps of forming over a silicon substrate an element isolation oxide film , a gate oxide (second etch) film , and a plurality of MOSFETs each including gate electrodes , a source and a drain , forming a first insulation layer over the gate electrodes , removing partially the first insulation layer at its portions disposed over the sources and drains of said plurality of MOSFETs to form contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) s , and forming a conductive layer in contact with the sources and drains exposed through the contact holes , the method comprising the further step of forming miniature contacts over the sources and drains , said further step comprising the steps of : coating a thick second insulation layer as a smoothing layer over the first insulation layer including the MOSFETs and coating over the second insulation layer a first polysilicon layer (first etch) , a third insulation layer and a photoresist film , in this order ; removing the photoresist film at its portions disposed above the sources and drains to form a photoresist film pattern and etching the third insulation layer at its portions exposed through the removed portions of the photoresist film to form a third insulation layer pattern ; removing the photoresist film pattern and forming spacers of a fourth insulation layer on side walls of the third insulation layer pattern ; etching the first polysilicon layer at its portions exposed through the removed portions of the third insulation layer , under a condition of using both the third insulation layer pattern and the fourth insulation layer spacers as a mask , to form a first polysilicon layer pattern ; removing the third insulation layer pattern and the fourth insulation layer spacers , etching the second insulation layer at its portion exposed through the removed third insulation layer pattern and fourth insulation layer spacers , under a condition of using the first polysilicon layer pattern as a mask , and etching the first insulation layer at its portion exposed through the etched portion (first etch) s of the second insulation layer , to form contact holes through which the sources and drains are exposed ; depositing over the contact holes and the first polysilicon layer pattern a second polysilicon layer (first etch) with a smooth upper surface and removing a portion of the second polysilicon layer and the first polysilicon layer pattern to form contact pads respectively connected to the sources and drains ; and applying conductive layers for selected electrodes or wirings to the contact pads . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric (contact hole) layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space (mask pattern) in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5279989A CLAIM 1 . A method for forming contacts of a highly integrated semiconductor device comprising the steps of forming over a silicon substrate an element isolation oxide film , a gate oxide film , and a plurality of MOSFETs each including gate electrodes , a source and a drain , forming a first insulation layer over the gate electrodes , removing partially the first insulation layer at its portions disposed over the sources and drains of said plurality of MOSFETs to form contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) s , and forming a conductive layer in contact with the sources and drains exposed through the contact holes , the method comprising the further step of forming miniature contacts over the sources and drains , said further step comprising the steps of : coating a thick second insulation layer as a smoothing layer over the first insulation layer including the MOSFETs and coating over the second insulation layer a first polysilicon layer , a third insulation layer and a photoresist film , in this order ; removing the photoresist film at its portions disposed above the sources and drains to form a photoresist film pattern and etching the third insulation layer at its portions exposed through the removed portions of the photoresist film to form a third insulation layer pattern ; removing the photoresist film pattern and forming spacers of a fourth insulation layer on side walls of the third insulation layer pattern ; etching the first polysilicon layer at its portions exposed through the removed portions of the third insulation layer , under a condition of using both the third insulation layer pattern and the fourth insulation layer spacers as a mask , to form a first polysilicon layer pattern ; removing the third insulation layer pattern and the fourth insulation layer spacers , etching the second insulation layer at its portion exposed through the removed third insulation layer pattern and fourth insulation layer spacers , under a condition of using the first polysilicon layer pattern as a mask , and etching the first insulation layer at its portion exposed through the etched portions of the second insulation layer , to form contact holes through which the sources and drains are exposed ; depositing over the contact holes and the first polysilicon layer pattern a second polysilicon layer with a smooth upper surface and removing a portion of the second polysilicon layer and the first polysilicon layer pattern to form contact pads respectively connected to the sources and drains ; and applying conductive layers for selected electrodes or wirings to the contact pads . US5279989A CLAIM 5 . The method in accordance with claim 1 , further comprising the steps of coating a fifth insulation layer over the entire exposed upper surface of the resultant structure obtained after the formation of the contact pads , removing portions of the fifth insulation layer to expose the contact pads therethrough , depositing a conductive layer for a bit line over the resultant entire exposed surface defined after the removal of the fifth insulation layer , and forming the bit line over and in contact with a corresponding one of the exposed contact pads by use of a mask pattern (second space) process . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US5279989A CLAIM 1 . A method for forming contacts of a highly integrated semiconductor device comprising the steps of forming over a silicon substrate an element isolation oxide film , a gate oxide film , and a plurality of MOSFETs each including gate electrodes , a source and a drain , forming a first insulation layer over the gate electrodes , removing partially the first insulation layer at its portions disposed over the sources and drains of said plurality of MOSFETs to form contact holes , and forming (anti reflective coating) a conductive layer in contact with the sources and drains exposed through the contact holes , the method comprising the further step of forming miniature contacts over the sources and drains , said further step comprising the steps of : coating a thick second insulation layer as a smoothing layer over the first insulation layer including the MOSFETs and coating over the second insulation layer a first polysilicon layer , a third insulation layer and a photoresist film , in this order ; removing the photoresist film at its portions disposed above the sources and drains to form a photoresist film pattern and etching the third insulation layer at its portions exposed through the removed portions of the photoresist film to form a third insulation layer pattern ; removing the photoresist film pattern and forming spacers of a fourth insulation layer on side walls of the third insulation layer pattern ; etching the first polysilicon layer at its portions exposed through the removed portions of the third insulation layer , under a condition of using both the third insulation layer pattern and the fourth insulation layer spacers as a mask , to form a first polysilicon layer pattern ; removing the third insulation layer pattern and the fourth insulation layer spacers , etching the second insulation layer at its portion exposed through the removed third insulation layer pattern and fourth insulation layer spacers , under a condition of using the first polysilicon layer pattern as a mask , and etching the first insulation layer at its portion exposed through the etched portions of the second insulation layer , to form contact holes through which the sources and drains are exposed ; depositing over the contact holes and the first polysilicon layer pattern a second polysilicon layer with a smooth upper surface and removing a portion of the second polysilicon layer and the first polysilicon layer pattern to form contact pads respectively connected to the sources and drains ; and applying conductive layers for selected electrodes or wirings to the contact pads . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch (second polysilicon layer, first polysilicon layer, etched portion) stop layer and a second etch (gate oxide) stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (contact hole) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom (smoothing layer) , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US5279989A CLAIM 1 . A method for forming contacts of a highly integrated semiconductor device comprising the steps of forming over a silicon substrate an element isolation oxide film , a gate oxide (second etch) film , and a plurality of MOSFETs each including gate electrodes , a source and a drain , forming a first insulation layer over the gate electrodes , removing partially the first insulation layer at its portions disposed over the sources and drains of said plurality of MOSFETs to form contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) s , and forming a conductive layer in contact with the sources and drains exposed through the contact holes , the method comprising the further step of forming miniature contacts over the sources and drains , said further step comprising the steps of : coating a thick second insulation layer as a smoothing layer (contact bottom) over the first insulation layer including the MOSFETs and coating over the second insulation layer a first polysilicon layer (first etch) , a third insulation layer and a photoresist film , in this order ; removing the photoresist film at its portions disposed above the sources and drains to form a photoresist film pattern and etching the third insulation layer at its portions exposed through the removed portions of the photoresist film to form a third insulation layer pattern ; removing the photoresist film pattern and forming spacers of a fourth insulation layer on side walls of the third insulation layer pattern ; etching the first polysilicon layer at its portions exposed through the removed portions of the third insulation layer , under a condition of using both the third insulation layer pattern and the fourth insulation layer spacers as a mask , to form a first polysilicon layer pattern ; removing the third insulation layer pattern and the fourth insulation layer spacers , etching the second insulation layer at its portion exposed through the removed third insulation layer pattern and fourth insulation layer spacers , under a condition of using the first polysilicon layer pattern as a mask , and etching the first insulation layer at its portion exposed through the etched portion (first etch) s of the second insulation layer , to form contact holes through which the sources and drains are exposed ; depositing over the contact holes and the first polysilicon layer pattern a second polysilicon layer (first etch) with a smooth upper surface and removing a portion of the second polysilicon layer and the first polysilicon layer pattern to form contact pads respectively connected to the sources and drains ; and applying conductive layers for selected electrodes or wirings to the contact pads . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch (second polysilicon layer, first polysilicon layer, etched portion) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (contact hole) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (gate oxide) stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5279989A CLAIM 1 . A method for forming contacts of a highly integrated semiconductor device comprising the steps of forming over a silicon substrate an element isolation oxide film , a gate oxide (second etch) film , and a plurality of MOSFETs each including gate electrodes , a source and a drain , forming a first insulation layer over the gate electrodes , removing partially the first insulation layer at its portions disposed over the sources and drains of said plurality of MOSFETs to form contact hole (interlevel dielectric, second interlevel dielectric, second sub interlevel dielectric layer, second interlevel dielectric layer) s , and forming a conductive layer in contact with the sources and drains exposed through the contact holes , the method comprising the further step of forming miniature contacts over the sources and drains , said further step comprising the steps of : coating a thick second insulation layer as a smoothing layer over the first insulation layer including the MOSFETs and coating over the second insulation layer a first polysilicon layer (first etch) , a third insulation layer and a photoresist film , in this order ; removing the photoresist film at its portions disposed above the sources and drains to form a photoresist film pattern and etching the third insulation layer at its portions exposed through the removed portions of the photoresist film to form a third insulation layer pattern ; removing the photoresist film pattern and forming spacers of a fourth insulation layer on side walls of the third insulation layer pattern ; etching the first polysilicon layer at its portions exposed through the removed portions of the third insulation layer , under a condition of using both the third insulation layer pattern and the fourth insulation layer spacers as a mask , to form a first polysilicon layer pattern ; removing the third insulation layer pattern and the fourth insulation layer spacers , etching the second insulation layer at its portion exposed through the removed third insulation layer pattern and fourth insulation layer spacers , under a condition of using the first polysilicon layer pattern as a mask , and etching the first insulation layer at its portion exposed through the etched portion (first etch) s of the second insulation layer , to form contact holes through which the sources and drains are exposed ; depositing over the contact holes and the first polysilicon layer pattern a second polysilicon layer (first etch) with a smooth upper surface and removing a portion of the second polysilicon layer and the first polysilicon layer pattern to form contact pads respectively connected to the sources and drains ; and applying conductive layers for selected electrodes or wirings to the contact pads . |
| US7977797B2 CLAIM 13 . An integrated circuit of claim 11 further comprising a floating gate (second insulation) . |
US5279989A CLAIM 1 . A method for forming contacts of a highly integrated semiconductor device comprising the steps of forming over a silicon substrate an element isolation oxide film , a gate oxide film , and a plurality of MOSFETs each including gate electrodes , a source and a drain , forming a first insulation layer over the gate electrodes , removing partially the first insulation layer at its portions disposed over the sources and drains of said plurality of MOSFETs to form contact holes , and forming a conductive layer in contact with the sources and drains exposed through the contact holes , the method comprising the further step of forming miniature contacts over the sources and drains , said further step comprising the steps of : coating a thick second insulation (floating gate) layer as a smoothing layer over the first insulation layer including the MOSFETs and coating over the second insulation layer a first polysilicon layer , a third insulation layer and a photoresist film , in this order ; removing the photoresist film at its portions disposed above the sources and drains to form a photoresist film pattern and etching the third insulation layer at its portions exposed through the removed portions of the photoresist film to form a third insulation layer pattern ; removing the photoresist film pattern and forming spacers of a fourth insulation layer on side walls of the third insulation layer pattern ; etching the first polysilicon layer at its portions exposed through the removed portions of the third insulation layer , under a condition of using both the third insulation layer pattern and the fourth insulation layer spacers as a mask , to form a first polysilicon layer pattern ; removing the third insulation layer pattern and the fourth insulation layer spacers , etching the second insulation layer at its portion exposed through the removed third insulation layer pattern and fourth insulation layer spacers , under a condition of using the first polysilicon layer pattern as a mask , and etching the first insulation layer at its portion exposed through the etched portions of the second insulation layer , to form contact holes through which the sources and drains are exposed ; depositing over the contact holes and the first polysilicon layer pattern a second polysilicon layer with a smooth upper surface and removing a portion of the second polysilicon layer and the first polysilicon layer pattern to form contact pads respectively connected to the sources and drains ; and applying conductive layers for selected electrodes or wirings to the contact pads . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US5279989A CLAIM 5 . The method in accordance with claim 1 , further comprising the steps of coating a fifth insulation layer over the entire exposed upper surface of the resultant structure obtained after the formation of the contact pads , removing portions of the fifth insulation layer to expose the contact pads therethrough , depositing a conductive layer for a bit line over the resultant entire exposed surface defined after the removal of the fifth insulation layer , and forming (anti reflective coating) the bit line over and in contact with a corresponding one of the exposed contact pads by use of a mask pattern process . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5292677A Filed: 1992-09-18 Issued: 1994-03-08 Reduced mask CMOS process for fabricating stacked capacitor multi-megabit dynamic random access memories utilizing single etch stop layer for contacts (Original Assignee) Micron Technology Inc (Current Assignee) Round Rock Research LLC Charles H. Dennison |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer (first etch stop layer) directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer (insulating film, protective insulating, following steps a) over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer (insulating film, protective insulating, following steps a) over said second etch stop layer . |
US5292677A CLAIM 1 . A method of fabricating a integrated circuit dynamic random access memory (DRAM) , said DRAM comprising a semiconducting wafer having : a semiconducting substrate ; a plurality of transistors formed on said substrate , each transistor including a gate conducting layer ; a capacitor formed on said substrate and having a capacitor first conducting layer , a capacitor dielectric layer , and a capacitor second conducting layer ; an active area on said substrate adjacent one of said transistors ; a bit line contact contacting said active area ; and a gate contact contacting said gate conducting layer ; said method comprising the steps of : employing a first etch stop layer (first etch stop layer) to self align said capacitor first conducting layer contact to said gate conducting layer ; employing said first etch stop layer to self align said bit line contact to said gate conducting layer ; and utilizing a single photo-mask and etch process to define said bit line contact and etch to said active area and to define said gate contact and etch to said gate conducting layer . US5292677A CLAIM 8 . The method of claim 5 wherein between said steps e) and f) the following steps a (second etch stop layer, second interlevel dielectric layer, second sub interlevel dielectric layer) re performed : creating a layer of resist on said wafer ; etching said resist to leave the resist partially filling said capacitor container and said gate conducting layer contact region ; and partially etching said capacitor first conducting layer to isolate the capacitor first conducting layer from other circuit elements of said DRAM ; and stripping said resist . US5292677A CLAIM 11 . The method of claim 5 wherein step j) comprises etching through said upper insulating layer , said capacitor second conducting layer , said capacitor dielectric layer , said lower insulating layer , and said first etch stop layer to said second active area ; and said step k) comprises : depositing an insulating film (second etch stop layer, second interlevel dielectric layer, second sub interlevel dielectric layer) on said wafer ; and etching said insulating film to expose said second active area while leaving said capacitor insulating spacer covering said capacitor second conducting layer . US5292677A CLAIM 16 . The method of claim 5 wherein said integrated circuit wafer includes a protective insulating (second etch stop layer, second interlevel dielectric layer, second sub interlevel dielectric layer) layer over said gate conducting layer , and said step of utilizing a second photo-mask and etch process further comprises removing said protective insulating layer above the gate conducting layer in said gate conducting layer contact region . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer (first etch stop layer) protects removal of a substrate material by an etch process . |
US5292677A CLAIM 1 . A method of fabricating a integrated circuit dynamic random access memory (DRAM) , said DRAM comprising a semiconducting wafer having : a semiconducting substrate ; a plurality of transistors formed on said substrate , each transistor including a gate conducting layer ; a capacitor formed on said substrate and having a capacitor first conducting layer , a capacitor dielectric layer , and a capacitor second conducting layer ; an active area on said substrate adjacent one of said transistors ; a bit line contact contacting said active area ; and a gate contact contacting said gate conducting layer ; said method comprising the steps of : employing a first etch stop layer (first etch stop layer) to self align said capacitor first conducting layer contact to said gate conducting layer ; employing said first etch stop layer to self align said bit line contact to said gate conducting layer ; and utilizing a single photo-mask and etch process to define said bit line contact and etch to said active area and to define said gate contact and etch to said gate conducting layer . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch stop layer (insulating film, protective insulating, following steps a) protects lower layers during an etching process . |
US5292677A CLAIM 8 . The method of claim 5 wherein between said steps e) and f) the following steps a (second etch stop layer, second interlevel dielectric layer, second sub interlevel dielectric layer) re performed : creating a layer of resist on said wafer ; etching said resist to leave the resist partially filling said capacitor container and said gate conducting layer contact region ; and partially etching said capacitor first conducting layer to isolate the capacitor first conducting layer from other circuit elements of said DRAM ; and stripping said resist . US5292677A CLAIM 11 . The method of claim 5 wherein step j) comprises etching through said upper insulating layer , said capacitor second conducting layer , said capacitor dielectric layer , said lower insulating layer , and said first etch stop layer to said second active area ; and said step k) comprises : depositing an insulating film (second etch stop layer, second interlevel dielectric layer, second sub interlevel dielectric layer) on said wafer ; and etching said insulating film to expose said second active area while leaving said capacitor insulating spacer covering said capacitor second conducting layer . US5292677A CLAIM 16 . The method of claim 5 wherein said integrated circuit wafer includes a protective insulating (second etch stop layer, second interlevel dielectric layer, second sub interlevel dielectric layer) layer over said gate conducting layer , and said step of utilizing a second photo-mask and etch process further comprises removing said protective insulating layer above the gate conducting layer in said gate conducting layer contact region . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric layer (insulating film, protective insulating, following steps a) insulates said contact region . |
US5292677A CLAIM 8 . The method of claim 5 wherein between said steps e) and f) the following steps a (second etch stop layer, second interlevel dielectric layer, second sub interlevel dielectric layer) re performed : creating a layer of resist on said wafer ; etching said resist to leave the resist partially filling said capacitor container and said gate conducting layer contact region ; and partially etching said capacitor first conducting layer to isolate the capacitor first conducting layer from other circuit elements of said DRAM ; and stripping said resist . US5292677A CLAIM 11 . The method of claim 5 wherein step j) comprises etching through said upper insulating layer , said capacitor second conducting layer , said capacitor dielectric layer , said lower insulating layer , and said first etch stop layer to said second active area ; and said step k) comprises : depositing an insulating film (second etch stop layer, second interlevel dielectric layer, second sub interlevel dielectric layer) on said wafer ; and etching said insulating film to expose said second active area while leaving said capacitor insulating spacer covering said capacitor second conducting layer . US5292677A CLAIM 16 . The method of claim 5 wherein said integrated circuit wafer includes a protective insulating (second etch stop layer, second interlevel dielectric layer, second sub interlevel dielectric layer) layer over said gate conducting layer , and said step of utilizing a second photo-mask and etch process further comprises removing said protective insulating layer above the gate conducting layer in said gate conducting layer contact region . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer (first etch stop layer) is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer (insulating film, protective insulating, following steps a) is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer (insulating film, protective insulating, following steps a) is in a range of about 10K ű1K Šthick . |
US5292677A CLAIM 1 . A method of fabricating a integrated circuit dynamic random access memory (DRAM) , said DRAM comprising a semiconducting wafer having : a semiconducting substrate ; a plurality of transistors formed on said substrate , each transistor including a gate conducting layer ; a capacitor formed on said substrate and having a capacitor first conducting layer , a capacitor dielectric layer , and a capacitor second conducting layer ; an active area on said substrate adjacent one of said transistors ; a bit line contact contacting said active area ; and a gate contact contacting said gate conducting layer ; said method comprising the steps of : employing a first etch stop layer (first etch stop layer) to self align said capacitor first conducting layer contact to said gate conducting layer ; employing said first etch stop layer to self align said bit line contact to said gate conducting layer ; and utilizing a single photo-mask and etch process to define said bit line contact and etch to said active area and to define said gate contact and etch to said gate conducting layer . US5292677A CLAIM 8 . The method of claim 5 wherein between said steps e) and f) the following steps a (second etch stop layer, second interlevel dielectric layer, second sub interlevel dielectric layer) re performed : creating a layer of resist on said wafer ; etching said resist to leave the resist partially filling said capacitor container and said gate conducting layer contact region ; and partially etching said capacitor first conducting layer to isolate the capacitor first conducting layer from other circuit elements of said DRAM ; and stripping said resist . US5292677A CLAIM 11 . The method of claim 5 wherein step j) comprises etching through said upper insulating layer , said capacitor second conducting layer , said capacitor dielectric layer , said lower insulating layer , and said first etch stop layer to said second active area ; and said step k) comprises : depositing an insulating film (second etch stop layer, second interlevel dielectric layer, second sub interlevel dielectric layer) on said wafer ; and etching said insulating film to expose said second active area while leaving said capacitor insulating spacer covering said capacitor second conducting layer . US5292677A CLAIM 16 . The method of claim 5 wherein said integrated circuit wafer includes a protective insulating (second etch stop layer, second interlevel dielectric layer, second sub interlevel dielectric layer) layer over said gate conducting layer , and said step of utilizing a second photo-mask and etch process further comprises removing said protective insulating layer above the gate conducting layer in said gate conducting layer contact region . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space (said sub) in a portion of said first sub interlevel dielectric layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer (insulating film, protective insulating, following steps a) for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5292677A CLAIM 1 . A method of fabricating a integrated circuit dynamic random access memory (DRAM) , said DRAM comprising a semiconducting wafer having : a semiconducting substrate ; a plurality of transistors formed on said sub (first space) strate , each transistor including a gate conducting layer ; a capacitor formed on said substrate and having a capacitor first conducting layer , a capacitor dielectric layer , and a capacitor second conducting layer ; an active area on said substrate adjacent one of said transistors ; a bit line contact contacting said active area ; and a gate contact contacting said gate conducting layer ; said method comprising the steps of : employing a first etch stop layer to self align said capacitor first conducting layer contact to said gate conducting layer ; employing said first etch stop layer to self align said bit line contact to said gate conducting layer ; and utilizing a single photo-mask and etch process to define said bit line contact and etch to said active area and to define said gate contact and etch to said gate conducting layer . US5292677A CLAIM 8 . The method of claim 5 wherein between said steps e) and f) the following steps a (second etch stop layer, second interlevel dielectric layer, second sub interlevel dielectric layer) re performed : creating a layer of resist on said wafer ; etching said resist to leave the resist partially filling said capacitor container and said gate conducting layer contact region ; and partially etching said capacitor first conducting layer to isolate the capacitor first conducting layer from other circuit elements of said DRAM ; and stripping said resist . US5292677A CLAIM 11 . The method of claim 5 wherein step j) comprises etching through said upper insulating layer , said capacitor second conducting layer , said capacitor dielectric layer , said lower insulating layer , and said first etch stop layer to said second active area ; and said step k) comprises : depositing an insulating film (second etch stop layer, second interlevel dielectric layer, second sub interlevel dielectric layer) on said wafer ; and etching said insulating film to expose said second active area while leaving said capacitor insulating spacer covering said capacitor second conducting layer . US5292677A CLAIM 16 . The method of claim 5 wherein said integrated circuit wafer includes a protective insulating (second etch stop layer, second interlevel dielectric layer, second sub interlevel dielectric layer) layer over said gate conducting layer , and said step of utilizing a second photo-mask and etch process further comprises removing said protective insulating layer above the gate conducting layer in said gate conducting layer contact region . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US5292677A CLAIM 17 . A method of fabricating an integrated circuit comprising a capacitor and a transistor , said method comprising : providing an integrated circuit wafer with a semiconducting substrate having : a gate conducting layer forming the gate of said transistor , said gate conducting layer made of a material which has selectivity in both a first etch process and a second etch process ; an active area , and an insulating spacer isolating said active area from said transistor gate , said insulating spacer made of a material which has selectivity in a said second etch process ; forming an etch stop layer on said wafer , said etch stop layer made of a material having selectivity in said first etch process and being etchable in said second etch process , said etch stop layer covering said active area ; forming a lower insulating layer on said wafer , said lower insulating layer made of a material which is etchable in said first etch process ; using a container photo-mask and first etch process to etch through said lower insulating layer and a second etch process to etch away said etch stop layer to form a capacitor container while removing said lower insulating layer and said etch stop layer from above a least a portion of said gate conducting layer ; forming a capacitor cell in said capacitor container ; forming an upper insulating layer on said wafer , said upper insulating layer made out of a material which is etchable in said first etch process ; using a contact photo-mask and said first etch process etch to etch through said upper and lower insulating layers and stop on said etch stop layer above said active area and on said portion of said gate conducting layer ; etching away said etch stop layer above said active area using said second etch process ; and forming (anti reflective coating) a contact contacting said portion of said gate conducting layer and a contact contacting said active area . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer (first etch stop layer) and a second etch stop layer (insulating film, protective insulating, following steps a) wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer (insulating film, protective insulating, following steps a) , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer (insulating film, protective insulating, following steps a) and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US5292677A CLAIM 1 . A method of fabricating a integrated circuit dynamic random access memory (DRAM) , said DRAM comprising a semiconducting wafer having : a semiconducting substrate ; a plurality of transistors formed on said substrate , each transistor including a gate conducting layer ; a capacitor formed on said substrate and having a capacitor first conducting layer , a capacitor dielectric layer , and a capacitor second conducting layer ; an active area on said substrate adjacent one of said transistors ; a bit line contact contacting said active area ; and a gate contact contacting said gate conducting layer ; said method comprising the steps of : employing a first etch stop layer (first etch stop layer) to self align said capacitor first conducting layer contact to said gate conducting layer ; employing said first etch stop layer to self align said bit line contact to said gate conducting layer ; and utilizing a single photo-mask and etch process to define said bit line contact and etch to said active area and to define said gate contact and etch to said gate conducting layer . US5292677A CLAIM 8 . The method of claim 5 wherein between said steps e) and f) the following steps a (second etch stop layer, second interlevel dielectric layer, second sub interlevel dielectric layer) re performed : creating a layer of resist on said wafer ; etching said resist to leave the resist partially filling said capacitor container and said gate conducting layer contact region ; and partially etching said capacitor first conducting layer to isolate the capacitor first conducting layer from other circuit elements of said DRAM ; and stripping said resist . US5292677A CLAIM 11 . The method of claim 5 wherein step j) comprises etching through said upper insulating layer , said capacitor second conducting layer , said capacitor dielectric layer , said lower insulating layer , and said first etch stop layer to said second active area ; and said step k) comprises : depositing an insulating film (second etch stop layer, second interlevel dielectric layer, second sub interlevel dielectric layer) on said wafer ; and etching said insulating film to expose said second active area while leaving said capacitor insulating spacer covering said capacitor second conducting layer . US5292677A CLAIM 16 . The method of claim 5 wherein said integrated circuit wafer includes a protective insulating (second etch stop layer, second interlevel dielectric layer, second sub interlevel dielectric layer) layer over said gate conducting layer , and said step of utilizing a second photo-mask and etch process further comprises removing said protective insulating layer above the gate conducting layer in said gate conducting layer contact region . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer (first etch stop layer) is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer (insulating film, protective insulating, following steps a) is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer (insulating film, protective insulating, following steps a) is in a range of about 10K ű1K Šthick . |
US5292677A CLAIM 1 . A method of fabricating a integrated circuit dynamic random access memory (DRAM) , said DRAM comprising a semiconducting wafer having : a semiconducting substrate ; a plurality of transistors formed on said substrate , each transistor including a gate conducting layer ; a capacitor formed on said substrate and having a capacitor first conducting layer , a capacitor dielectric layer , and a capacitor second conducting layer ; an active area on said substrate adjacent one of said transistors ; a bit line contact contacting said active area ; and a gate contact contacting said gate conducting layer ; said method comprising the steps of : employing a first etch stop layer (first etch stop layer) to self align said capacitor first conducting layer contact to said gate conducting layer ; employing said first etch stop layer to self align said bit line contact to said gate conducting layer ; and utilizing a single photo-mask and etch process to define said bit line contact and etch to said active area and to define said gate contact and etch to said gate conducting layer . US5292677A CLAIM 8 . The method of claim 5 wherein between said steps e) and f) the following steps a (second etch stop layer, second interlevel dielectric layer, second sub interlevel dielectric layer) re performed : creating a layer of resist on said wafer ; etching said resist to leave the resist partially filling said capacitor container and said gate conducting layer contact region ; and partially etching said capacitor first conducting layer to isolate the capacitor first conducting layer from other circuit elements of said DRAM ; and stripping said resist . US5292677A CLAIM 11 . The method of claim 5 wherein step j) comprises etching through said upper insulating layer , said capacitor second conducting layer , said capacitor dielectric layer , said lower insulating layer , and said first etch stop layer to said second active area ; and said step k) comprises : depositing an insulating film (second etch stop layer, second interlevel dielectric layer, second sub interlevel dielectric layer) on said wafer ; and etching said insulating film to expose said second active area while leaving said capacitor insulating spacer covering said capacitor second conducting layer . US5292677A CLAIM 16 . The method of claim 5 wherein said integrated circuit wafer includes a protective insulating (second etch stop layer, second interlevel dielectric layer, second sub interlevel dielectric layer) layer over said gate conducting layer , and said step of utilizing a second photo-mask and etch process further comprises removing said protective insulating layer above the gate conducting layer in said gate conducting layer contact region . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US5292677A CLAIM 17 . A method of fabricating an integrated circuit comprising a capacitor and a transistor , said method comprising : providing an integrated circuit wafer with a semiconducting substrate having : a gate conducting layer forming the gate of said transistor , said gate conducting layer made of a material which has selectivity in both a first etch process and a second etch process ; an active area , and an insulating spacer isolating said active area from said transistor gate , said insulating spacer made of a material which has selectivity in a said second etch process ; forming an etch stop layer on said wafer , said etch stop layer made of a material having selectivity in said first etch process and being etchable in said second etch process , said etch stop layer covering said active area ; forming a lower insulating layer on said wafer , said lower insulating layer made of a material which is etchable in said first etch process ; using a container photo-mask and first etch process to etch through said lower insulating layer and a second etch process to etch away said etch stop layer to form a capacitor container while removing said lower insulating layer and said etch stop layer from above a least a portion of said gate conducting layer ; forming a capacitor cell in said capacitor container ; forming an upper insulating layer on said wafer , said upper insulating layer made out of a material which is etchable in said first etch process ; using a contact photo-mask and said first etch process etch to etch through said upper and lower insulating layers and stop on said etch stop layer above said active area and on said portion of said gate conducting layer ; etching away said etch stop layer above said active area using said second etch process ; and forming (anti reflective coating) a contact contacting said portion of said gate conducting layer and a contact contacting said active area . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5332924A Filed: 1992-09-11 Issued: 1994-07-26 Semiconductor device and production method thereof (Original Assignee) NEC Corp (Current Assignee) Micron Memory Japan Ltd Migaku Kobayashi |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch (selective removal, insulating film, wet etch, dry etch) stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch (selective removal, insulating film, wet etch, dry etch) stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (intermediate insulating) layer over said first etch stop layer ; a second etch (selective removal, insulating film, wet etch, dry etch) stop layer (selective removal, insulating film, wet etch, dry etch) over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5332924A CLAIM 8 . A production method of a semiconductor device , comprising the steps of : forming a lower conductive layer on a surface of or over a semiconductor substrate ; forming a lower insulating layer on said lower conductive layer ; forming an intermediate conductive layer on said lower insulating layer ; forming a first inter-layer insulating layer on said intermediate conductive layer ; forming a second inter-layer insulating layer on said first inter-layer insulating layer ; forming a third inter-layer insulating layer on said second inter-layer insulating layer ; selectively removing said third inter-layer insulating layer thereby forming a first through-hole for wiring extended to said second inter-layer insulating layer , said selective removal (second etch stop layer, second interlevel dielectric layer, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, etch process, second etch stop layers, second etch) action in a direction perpendicular to said third inter-layer insulating layer being stopped by said second inter-layer insulating layer ; selectively removing said second inter-layer insulating layer , first inter-layer insulating layer and lower insulating layer thereby forming a second through-hole for wiring , said second through-hole communicating said first through-hole and extending to said lower conductive layer , an opening area of said second through-hole being smaller in size than an opening area of a top of said first through-hole ; and forming an upper conductive layer for wiring on said third inter-layer insulating layer , which is electrically connected through said first and said second through-holes of said lower insulating layer , first inter-layer insulating layer , second inter-layer insulating layer and third inter-layer insulating layer to the said lower conductive layer , said upper conductive layer not being connected electrically to said intermediate conductive layer ; wherein said upper conductive layer is in contact with an upper face of said first inter-layer insulating layer in said first contact-hole of said third inter-layer insulating layer . US5332924A CLAIM 9 . The production method as claimed in claim 8 , wherein said step of forming a first through-hole for wiring in said third inter-layer insulating layer is achieved by an isotropic wet etch (second etch stop layer, second interlevel dielectric layer, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, etch process, second etch stop layers, second etch) ing technique , and said step of forming said second through-hole for wiring in said second inter-layer insulating layer , first inter-layer insulating layer and lower insulating layer are achieved by an anisotropic dry etch (second etch stop layer, second interlevel dielectric layer, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, etch process, second etch stop layers, second etch) ing technique . US5332924A CLAIM 14 . A semiconductor device comprising : a lower conductive layer formed on a surface of or over a semiconductor substrate ; at least one lower insulating layer formed on said lower conductive layer and having a first through-hole for wiring ; an intermediate conductive layer formed on said lower insulating layer ; a first inter-layer insulating layer and a second inter-layer insulating layer formed on said intermediate insulating (interlevel dielectric) layer and having a second through-hole for wiring communicated to the first through-hole for wiring of said lower conductive layer and not extended to the first inter-layer insulating layer ; and an upper conductive layer formed on said second inter-layer conductive layer , which is electrically connected through the first and second wiring through-holes of said lower insulating layer and inter-layer insulating layers to said lower conductive layer , said upper conductive layer not being electrically connected to said intermediate conductive layer ; wherein the thickness of said at least one lower insulating layer adjacent to said first wiring through-hole is formed is thinner than at positions not adjacent to said first wiring through-hole and said lower insulating layer includes a film having a removal action limiting property in the thickness direction when said lower insulating layer is selectively removed to reduce the thickness thereof . US5332924A CLAIM 19 . A production method of semiconductor device comprising the steps of : forming a lower conductive layer on a surface of or over a semiconductor substrate ; forming at least one insulating layer on said lower conductive layer ; selectively removing said at least one lower insulating layer thereby to form a layer area with a small thickness ; forming an intermediate conductive layer on said at least one lower insulating layer said layer area with a small thickness ; forming a first inter-layer insulating layer and a second inter-layer insulating layer on said intermediate conductive layer ; selectively removing said second inter-layer insulating layer thereby to form a first through-hole for wiring , said first through-hole not extending to said first inter-layer insulating layer ; selectively removing said first inter-layer insulating layer and lower insulating layer to form a second through-hole for wiring which is communicated to the first through-hole of said second inter-layer insulating layer and extended to said lower conductive layer , said second through-hole having an opening area smaller than said first through-hole of said second inter-layer insulating layer ; and forming an upper conductive layer on said second inter-layer insulating layer , which is electrically connected through the first and second wiring through-holes of said lower insulating layer and inter-layer insulating layers , said upper conductive layer extending to said lower conductive layer and not being electrically connected to said intermediate conductive layer ; wherein the step of selectively removing said lower insulating layer to form a layer area small in thickness utilizes an insulating film (second etch stop layer, second interlevel dielectric layer, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, etch process, second etch stop layers, second etch) which is part of said at least one lower insulating layer and has a function of limiting removal of said lower insulating layer thereby to limit the removal action in the thickness direction thereof . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch (selective removal, insulating film, wet etch, dry etch) stop layer protects removal of a substrate material by an etch process (selective removal, insulating film, wet etch, dry etch) . |
US5332924A CLAIM 8 . A production method of a semiconductor device , comprising the steps of : forming a lower conductive layer on a surface of or over a semiconductor substrate ; forming a lower insulating layer on said lower conductive layer ; forming an intermediate conductive layer on said lower insulating layer ; forming a first inter-layer insulating layer on said intermediate conductive layer ; forming a second inter-layer insulating layer on said first inter-layer insulating layer ; forming a third inter-layer insulating layer on said second inter-layer insulating layer ; selectively removing said third inter-layer insulating layer thereby forming a first through-hole for wiring extended to said second inter-layer insulating layer , said selective removal (second etch stop layer, second interlevel dielectric layer, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, etch process, second etch stop layers, second etch) action in a direction perpendicular to said third inter-layer insulating layer being stopped by said second inter-layer insulating layer ; selectively removing said second inter-layer insulating layer , first inter-layer insulating layer and lower insulating layer thereby forming a second through-hole for wiring , said second through-hole communicating said first through-hole and extending to said lower conductive layer , an opening area of said second through-hole being smaller in size than an opening area of a top of said first through-hole ; and forming an upper conductive layer for wiring on said third inter-layer insulating layer , which is electrically connected through said first and said second through-holes of said lower insulating layer , first inter-layer insulating layer , second inter-layer insulating layer and third inter-layer insulating layer to the said lower conductive layer , said upper conductive layer not being connected electrically to said intermediate conductive layer ; wherein said upper conductive layer is in contact with an upper face of said first inter-layer insulating layer in said first contact-hole of said third inter-layer insulating layer . US5332924A CLAIM 9 . The production method as claimed in claim 8 , wherein said step of forming a first through-hole for wiring in said third inter-layer insulating layer is achieved by an isotropic wet etch (second etch stop layer, second interlevel dielectric layer, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, etch process, second etch stop layers, second etch) ing technique , and said step of forming said second through-hole for wiring in said second inter-layer insulating layer , first inter-layer insulating layer and lower insulating layer are achieved by an anisotropic dry etch (second etch stop layer, second interlevel dielectric layer, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, etch process, second etch stop layers, second etch) ing technique . US5332924A CLAIM 19 . A production method of semiconductor device comprising the steps of : forming a lower conductive layer on a surface of or over a semiconductor substrate ; forming at least one insulating layer on said lower conductive layer ; selectively removing said at least one lower insulating layer thereby to form a layer area with a small thickness ; forming an intermediate conductive layer on said at least one lower insulating layer said layer area with a small thickness ; forming a first inter-layer insulating layer and a second inter-layer insulating layer on said intermediate conductive layer ; selectively removing said second inter-layer insulating layer thereby to form a first through-hole for wiring , said first through-hole not extending to said first inter-layer insulating layer ; selectively removing said first inter-layer insulating layer and lower insulating layer to form a second through-hole for wiring which is communicated to the first through-hole of said second inter-layer insulating layer and extended to said lower conductive layer , said second through-hole having an opening area smaller than said first through-hole of said second inter-layer insulating layer ; and forming an upper conductive layer on said second inter-layer insulating layer , which is electrically connected through the first and second wiring through-holes of said lower insulating layer and inter-layer insulating layers , said upper conductive layer extending to said lower conductive layer and not being electrically connected to said intermediate conductive layer ; wherein the step of selectively removing said lower insulating layer to form a layer area small in thickness utilizes an insulating film (second etch stop layer, second interlevel dielectric layer, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, etch process, second etch stop layers, second etch) which is part of said at least one lower insulating layer and has a function of limiting removal of said lower insulating layer thereby to limit the removal action in the thickness direction thereof . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (intermediate insulating) layer insulates said contact region . |
US5332924A CLAIM 14 . A semiconductor device comprising : a lower conductive layer formed on a surface of or over a semiconductor substrate ; at least one lower insulating layer formed on said lower conductive layer and having a first through-hole for wiring ; an intermediate conductive layer formed on said lower insulating layer ; a first inter-layer insulating layer and a second inter-layer insulating layer formed on said intermediate insulating (interlevel dielectric) layer and having a second through-hole for wiring communicated to the first through-hole for wiring of said lower conductive layer and not extended to the first inter-layer insulating layer ; and an upper conductive layer formed on said second inter-layer conductive layer , which is electrically connected through the first and second wiring through-holes of said lower insulating layer and inter-layer insulating layers to said lower conductive layer , said upper conductive layer not being electrically connected to said intermediate conductive layer ; wherein the thickness of said at least one lower insulating layer adjacent to said first wiring through-hole is formed is thinner than at positions not adjacent to said first wiring through-hole and said lower insulating layer includes a film having a removal action limiting property in the thickness direction when said lower insulating layer is selectively removed to reduce the thickness thereof . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch (selective removal, insulating film, wet etch, dry etch) stop layer (selective removal, insulating film, wet etch, dry etch) protects lower layers during an etching process . |
US5332924A CLAIM 8 . A production method of a semiconductor device , comprising the steps of : forming a lower conductive layer on a surface of or over a semiconductor substrate ; forming a lower insulating layer on said lower conductive layer ; forming an intermediate conductive layer on said lower insulating layer ; forming a first inter-layer insulating layer on said intermediate conductive layer ; forming a second inter-layer insulating layer on said first inter-layer insulating layer ; forming a third inter-layer insulating layer on said second inter-layer insulating layer ; selectively removing said third inter-layer insulating layer thereby forming a first through-hole for wiring extended to said second inter-layer insulating layer , said selective removal (second etch stop layer, second interlevel dielectric layer, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, etch process, second etch stop layers, second etch) action in a direction perpendicular to said third inter-layer insulating layer being stopped by said second inter-layer insulating layer ; selectively removing said second inter-layer insulating layer , first inter-layer insulating layer and lower insulating layer thereby forming a second through-hole for wiring , said second through-hole communicating said first through-hole and extending to said lower conductive layer , an opening area of said second through-hole being smaller in size than an opening area of a top of said first through-hole ; and forming an upper conductive layer for wiring on said third inter-layer insulating layer , which is electrically connected through said first and said second through-holes of said lower insulating layer , first inter-layer insulating layer , second inter-layer insulating layer and third inter-layer insulating layer to the said lower conductive layer , said upper conductive layer not being connected electrically to said intermediate conductive layer ; wherein said upper conductive layer is in contact with an upper face of said first inter-layer insulating layer in said first contact-hole of said third inter-layer insulating layer . US5332924A CLAIM 9 . The production method as claimed in claim 8 , wherein said step of forming a first through-hole for wiring in said third inter-layer insulating layer is achieved by an isotropic wet etch (second etch stop layer, second interlevel dielectric layer, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, etch process, second etch stop layers, second etch) ing technique , and said step of forming said second through-hole for wiring in said second inter-layer insulating layer , first inter-layer insulating layer and lower insulating layer are achieved by an anisotropic dry etch (second etch stop layer, second interlevel dielectric layer, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, etch process, second etch stop layers, second etch) ing technique . US5332924A CLAIM 19 . A production method of semiconductor device comprising the steps of : forming a lower conductive layer on a surface of or over a semiconductor substrate ; forming at least one insulating layer on said lower conductive layer ; selectively removing said at least one lower insulating layer thereby to form a layer area with a small thickness ; forming an intermediate conductive layer on said at least one lower insulating layer said layer area with a small thickness ; forming a first inter-layer insulating layer and a second inter-layer insulating layer on said intermediate conductive layer ; selectively removing said second inter-layer insulating layer thereby to form a first through-hole for wiring , said first through-hole not extending to said first inter-layer insulating layer ; selectively removing said first inter-layer insulating layer and lower insulating layer to form a second through-hole for wiring which is communicated to the first through-hole of said second inter-layer insulating layer and extended to said lower conductive layer , said second through-hole having an opening area smaller than said first through-hole of said second inter-layer insulating layer ; and forming an upper conductive layer on said second inter-layer insulating layer , which is electrically connected through the first and second wiring through-holes of said lower insulating layer and inter-layer insulating layers , said upper conductive layer extending to said lower conductive layer and not being electrically connected to said intermediate conductive layer ; wherein the step of selectively removing said lower insulating layer to form a layer area small in thickness utilizes an insulating film (second etch stop layer, second interlevel dielectric layer, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, etch process, second etch stop layers, second etch) which is part of said at least one lower insulating layer and has a function of limiting removal of said lower insulating layer thereby to limit the removal action in the thickness direction thereof . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (intermediate insulating) layer insulates said contact region . |
US5332924A CLAIM 14 . A semiconductor device comprising : a lower conductive layer formed on a surface of or over a semiconductor substrate ; at least one lower insulating layer formed on said lower conductive layer and having a first through-hole for wiring ; an intermediate conductive layer formed on said lower insulating layer ; a first inter-layer insulating layer and a second inter-layer insulating layer formed on said intermediate insulating (interlevel dielectric) layer and having a second through-hole for wiring communicated to the first through-hole for wiring of said lower conductive layer and not extended to the first inter-layer insulating layer ; and an upper conductive layer formed on said second inter-layer conductive layer , which is electrically connected through the first and second wiring through-holes of said lower insulating layer and inter-layer insulating layers to said lower conductive layer , said upper conductive layer not being electrically connected to said intermediate conductive layer ; wherein the thickness of said at least one lower insulating layer adjacent to said first wiring through-hole is formed is thinner than at positions not adjacent to said first wiring through-hole and said lower insulating layer includes a film having a removal action limiting property in the thickness direction when said lower insulating layer is selectively removed to reduce the thickness thereof . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch (selective removal, insulating film, wet etch, dry etch) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (intermediate insulating) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (selective removal, insulating film, wet etch, dry etch) stop layer (selective removal, insulating film, wet etch, dry etch) is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5332924A CLAIM 8 . A production method of a semiconductor device , comprising the steps of : forming a lower conductive layer on a surface of or over a semiconductor substrate ; forming a lower insulating layer on said lower conductive layer ; forming an intermediate conductive layer on said lower insulating layer ; forming a first inter-layer insulating layer on said intermediate conductive layer ; forming a second inter-layer insulating layer on said first inter-layer insulating layer ; forming a third inter-layer insulating layer on said second inter-layer insulating layer ; selectively removing said third inter-layer insulating layer thereby forming a first through-hole for wiring extended to said second inter-layer insulating layer , said selective removal (second etch stop layer, second interlevel dielectric layer, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, etch process, second etch stop layers, second etch) action in a direction perpendicular to said third inter-layer insulating layer being stopped by said second inter-layer insulating layer ; selectively removing said second inter-layer insulating layer , first inter-layer insulating layer and lower insulating layer thereby forming a second through-hole for wiring , said second through-hole communicating said first through-hole and extending to said lower conductive layer , an opening area of said second through-hole being smaller in size than an opening area of a top of said first through-hole ; and forming an upper conductive layer for wiring on said third inter-layer insulating layer , which is electrically connected through said first and said second through-holes of said lower insulating layer , first inter-layer insulating layer , second inter-layer insulating layer and third inter-layer insulating layer to the said lower conductive layer , said upper conductive layer not being connected electrically to said intermediate conductive layer ; wherein said upper conductive layer is in contact with an upper face of said first inter-layer insulating layer in said first contact-hole of said third inter-layer insulating layer . US5332924A CLAIM 9 . The production method as claimed in claim 8 , wherein said step of forming a first through-hole for wiring in said third inter-layer insulating layer is achieved by an isotropic wet etch (second etch stop layer, second interlevel dielectric layer, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, etch process, second etch stop layers, second etch) ing technique , and said step of forming said second through-hole for wiring in said second inter-layer insulating layer , first inter-layer insulating layer and lower insulating layer are achieved by an anisotropic dry etch (second etch stop layer, second interlevel dielectric layer, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, etch process, second etch stop layers, second etch) ing technique . US5332924A CLAIM 14 . A semiconductor device comprising : a lower conductive layer formed on a surface of or over a semiconductor substrate ; at least one lower insulating layer formed on said lower conductive layer and having a first through-hole for wiring ; an intermediate conductive layer formed on said lower insulating layer ; a first inter-layer insulating layer and a second inter-layer insulating layer formed on said intermediate insulating (interlevel dielectric) layer and having a second through-hole for wiring communicated to the first through-hole for wiring of said lower conductive layer and not extended to the first inter-layer insulating layer ; and an upper conductive layer formed on said second inter-layer conductive layer , which is electrically connected through the first and second wiring through-holes of said lower insulating layer and inter-layer insulating layers to said lower conductive layer , said upper conductive layer not being electrically connected to said intermediate conductive layer ; wherein the thickness of said at least one lower insulating layer adjacent to said first wiring through-hole is formed is thinner than at positions not adjacent to said first wiring through-hole and said lower insulating layer includes a film having a removal action limiting property in the thickness direction when said lower insulating layer is selectively removed to reduce the thickness thereof . US5332924A CLAIM 19 . A production method of semiconductor device comprising the steps of : forming a lower conductive layer on a surface of or over a semiconductor substrate ; forming at least one insulating layer on said lower conductive layer ; selectively removing said at least one lower insulating layer thereby to form a layer area with a small thickness ; forming an intermediate conductive layer on said at least one lower insulating layer said layer area with a small thickness ; forming a first inter-layer insulating layer and a second inter-layer insulating layer on said intermediate conductive layer ; selectively removing said second inter-layer insulating layer thereby to form a first through-hole for wiring , said first through-hole not extending to said first inter-layer insulating layer ; selectively removing said first inter-layer insulating layer and lower insulating layer to form a second through-hole for wiring which is communicated to the first through-hole of said second inter-layer insulating layer and extended to said lower conductive layer , said second through-hole having an opening area smaller than said first through-hole of said second inter-layer insulating layer ; and forming an upper conductive layer on said second inter-layer insulating layer , which is electrically connected through the first and second wiring through-holes of said lower insulating layer and inter-layer insulating layers , said upper conductive layer extending to said lower conductive layer and not being electrically connected to said intermediate conductive layer ; wherein the step of selectively removing said lower insulating layer to form a layer area small in thickness utilizes an insulating film (second etch stop layer, second interlevel dielectric layer, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, etch process, second etch stop layers, second etch) which is part of said at least one lower insulating layer and has a function of limiting removal of said lower insulating layer thereby to limit the removal action in the thickness direction thereof . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric (intermediate insulating) layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5332924A CLAIM 14 . A semiconductor device comprising : a lower conductive layer formed on a surface of or over a semiconductor substrate ; at least one lower insulating layer formed on said lower conductive layer and having a first through-hole for wiring ; an intermediate conductive layer formed on said lower insulating layer ; a first inter-layer insulating layer and a second inter-layer insulating layer formed on said intermediate insulating (interlevel dielectric) layer and having a second through-hole for wiring communicated to the first through-hole for wiring of said lower conductive layer and not extended to the first inter-layer insulating layer ; and an upper conductive layer formed on said second inter-layer conductive layer , which is electrically connected through the first and second wiring through-holes of said lower insulating layer and inter-layer insulating layers to said lower conductive layer , said upper conductive layer not being electrically connected to said intermediate conductive layer ; wherein the thickness of said at least one lower insulating layer adjacent to said first wiring through-hole is formed is thinner than at positions not adjacent to said first wiring through-hole and said lower insulating layer includes a film having a removal action limiting property in the thickness direction when said lower insulating layer is selectively removed to reduce the thickness thereof . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US5332924A CLAIM 8 . A production method of a semiconductor device , comprising the steps of : forming a lower conductive layer on a surface of or over a semiconductor substrate ; forming a lower insulating layer on said lower conductive layer ; forming an intermediate conductive layer on said lower insulating layer ; forming a first inter-layer insulating layer on said intermediate conductive layer ; forming a second inter-layer insulating layer on said first inter-layer insulating layer ; forming a third inter-layer insulating layer on said second inter-layer insulating layer ; selectively removing said third inter-layer insulating layer thereby forming a first through-hole for wiring extended to said second inter-layer insulating layer , said selective removal action in a direction perpendicular to said third inter-layer insulating layer being stopped by said second inter-layer insulating layer ; selectively removing said second inter-layer insulating layer , first inter-layer insulating layer and lower insulating layer thereby forming a second through-hole for wiring , said second through-hole communicating said first through-hole and extending to said lower conductive layer , an opening area of said second through-hole being smaller in size than an opening area of a top of said first through-hole ; and forming (anti reflective coating) an upper conductive layer for wiring on said third inter-layer insulating layer , which is electrically connected through said first and said second through-holes of said lower insulating layer , first inter-layer insulating layer , second inter-layer insulating layer and third inter-layer insulating layer to the said lower conductive layer , said upper conductive layer not being connected electrically to said intermediate conductive layer ; wherein said upper conductive layer is in contact with an upper face of said first inter-layer insulating layer in said first contact-hole of said third inter-layer insulating layer . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch (selective removal, insulating film, wet etch, dry etch) stop insulation layer comprising a first etch (selective removal, insulating film, wet etch, dry etch) stop layer and a second etch (selective removal, insulating film, wet etch, dry etch) stop layer (selective removal, insulating film, wet etch, dry etch) wherein said first etch stop layer and said second etch stop layers (selective removal, insulating film, wet etch, dry etch) have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (intermediate insulating) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom (open top) , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US5332924A CLAIM 4 . The semiconductor device as claimed in claim 1 , wherein said fourth through-hole of said third inter-layer insulating layer is substantially hemispherical in shape and an open top (contact bottom) of said through-hole of said third inter-layer insulating layer is larger in diameter than a bottom thereof . US5332924A CLAIM 8 . A production method of a semiconductor device , comprising the steps of : forming a lower conductive layer on a surface of or over a semiconductor substrate ; forming a lower insulating layer on said lower conductive layer ; forming an intermediate conductive layer on said lower insulating layer ; forming a first inter-layer insulating layer on said intermediate conductive layer ; forming a second inter-layer insulating layer on said first inter-layer insulating layer ; forming a third inter-layer insulating layer on said second inter-layer insulating layer ; selectively removing said third inter-layer insulating layer thereby forming a first through-hole for wiring extended to said second inter-layer insulating layer , said selective removal (second etch stop layer, second interlevel dielectric layer, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, etch process, second etch stop layers, second etch) action in a direction perpendicular to said third inter-layer insulating layer being stopped by said second inter-layer insulating layer ; selectively removing said second inter-layer insulating layer , first inter-layer insulating layer and lower insulating layer thereby forming a second through-hole for wiring , said second through-hole communicating said first through-hole and extending to said lower conductive layer , an opening area of said second through-hole being smaller in size than an opening area of a top of said first through-hole ; and forming an upper conductive layer for wiring on said third inter-layer insulating layer , which is electrically connected through said first and said second through-holes of said lower insulating layer , first inter-layer insulating layer , second inter-layer insulating layer and third inter-layer insulating layer to the said lower conductive layer , said upper conductive layer not being connected electrically to said intermediate conductive layer ; wherein said upper conductive layer is in contact with an upper face of said first inter-layer insulating layer in said first contact-hole of said third inter-layer insulating layer . US5332924A CLAIM 9 . The production method as claimed in claim 8 , wherein said step of forming a first through-hole for wiring in said third inter-layer insulating layer is achieved by an isotropic wet etch (second etch stop layer, second interlevel dielectric layer, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, etch process, second etch stop layers, second etch) ing technique , and said step of forming said second through-hole for wiring in said second inter-layer insulating layer , first inter-layer insulating layer and lower insulating layer are achieved by an anisotropic dry etch (second etch stop layer, second interlevel dielectric layer, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, etch process, second etch stop layers, second etch) ing technique . US5332924A CLAIM 14 . A semiconductor device comprising : a lower conductive layer formed on a surface of or over a semiconductor substrate ; at least one lower insulating layer formed on said lower conductive layer and having a first through-hole for wiring ; an intermediate conductive layer formed on said lower insulating layer ; a first inter-layer insulating layer and a second inter-layer insulating layer formed on said intermediate insulating (interlevel dielectric) layer and having a second through-hole for wiring communicated to the first through-hole for wiring of said lower conductive layer and not extended to the first inter-layer insulating layer ; and an upper conductive layer formed on said second inter-layer conductive layer , which is electrically connected through the first and second wiring through-holes of said lower insulating layer and inter-layer insulating layers to said lower conductive layer , said upper conductive layer not being electrically connected to said intermediate conductive layer ; wherein the thickness of said at least one lower insulating layer adjacent to said first wiring through-hole is formed is thinner than at positions not adjacent to said first wiring through-hole and said lower insulating layer includes a film having a removal action limiting property in the thickness direction when said lower insulating layer is selectively removed to reduce the thickness thereof . US5332924A CLAIM 19 . A production method of semiconductor device comprising the steps of : forming a lower conductive layer on a surface of or over a semiconductor substrate ; forming at least one insulating layer on said lower conductive layer ; selectively removing said at least one lower insulating layer thereby to form a layer area with a small thickness ; forming an intermediate conductive layer on said at least one lower insulating layer said layer area with a small thickness ; forming a first inter-layer insulating layer and a second inter-layer insulating layer on said intermediate conductive layer ; selectively removing said second inter-layer insulating layer thereby to form a first through-hole for wiring , said first through-hole not extending to said first inter-layer insulating layer ; selectively removing said first inter-layer insulating layer and lower insulating layer to form a second through-hole for wiring which is communicated to the first through-hole of said second inter-layer insulating layer and extended to said lower conductive layer , said second through-hole having an opening area smaller than said first through-hole of said second inter-layer insulating layer ; and forming an upper conductive layer on said second inter-layer insulating layer , which is electrically connected through the first and second wiring through-holes of said lower insulating layer and inter-layer insulating layers , said upper conductive layer extending to said lower conductive layer and not being electrically connected to said intermediate conductive layer ; wherein the step of selectively removing said lower insulating layer to form a layer area small in thickness utilizes an insulating film (second etch stop layer, second interlevel dielectric layer, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, etch process, second etch stop layers, second etch) which is part of said at least one lower insulating layer and has a function of limiting removal of said lower insulating layer thereby to limit the removal action in the thickness direction thereof . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch (selective removal, insulating film, wet etch, dry etch) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (intermediate insulating) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch (selective removal, insulating film, wet etch, dry etch) stop layer (selective removal, insulating film, wet etch, dry etch) is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5332924A CLAIM 8 . A production method of a semiconductor device , comprising the steps of : forming a lower conductive layer on a surface of or over a semiconductor substrate ; forming a lower insulating layer on said lower conductive layer ; forming an intermediate conductive layer on said lower insulating layer ; forming a first inter-layer insulating layer on said intermediate conductive layer ; forming a second inter-layer insulating layer on said first inter-layer insulating layer ; forming a third inter-layer insulating layer on said second inter-layer insulating layer ; selectively removing said third inter-layer insulating layer thereby forming a first through-hole for wiring extended to said second inter-layer insulating layer , said selective removal (second etch stop layer, second interlevel dielectric layer, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, etch process, second etch stop layers, second etch) action in a direction perpendicular to said third inter-layer insulating layer being stopped by said second inter-layer insulating layer ; selectively removing said second inter-layer insulating layer , first inter-layer insulating layer and lower insulating layer thereby forming a second through-hole for wiring , said second through-hole communicating said first through-hole and extending to said lower conductive layer , an opening area of said second through-hole being smaller in size than an opening area of a top of said first through-hole ; and forming an upper conductive layer for wiring on said third inter-layer insulating layer , which is electrically connected through said first and said second through-holes of said lower insulating layer , first inter-layer insulating layer , second inter-layer insulating layer and third inter-layer insulating layer to the said lower conductive layer , said upper conductive layer not being connected electrically to said intermediate conductive layer ; wherein said upper conductive layer is in contact with an upper face of said first inter-layer insulating layer in said first contact-hole of said third inter-layer insulating layer . US5332924A CLAIM 9 . The production method as claimed in claim 8 , wherein said step of forming a first through-hole for wiring in said third inter-layer insulating layer is achieved by an isotropic wet etch (second etch stop layer, second interlevel dielectric layer, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, etch process, second etch stop layers, second etch) ing technique , and said step of forming said second through-hole for wiring in said second inter-layer insulating layer , first inter-layer insulating layer and lower insulating layer are achieved by an anisotropic dry etch (second etch stop layer, second interlevel dielectric layer, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, etch process, second etch stop layers, second etch) ing technique . US5332924A CLAIM 14 . A semiconductor device comprising : a lower conductive layer formed on a surface of or over a semiconductor substrate ; at least one lower insulating layer formed on said lower conductive layer and having a first through-hole for wiring ; an intermediate conductive layer formed on said lower insulating layer ; a first inter-layer insulating layer and a second inter-layer insulating layer formed on said intermediate insulating (interlevel dielectric) layer and having a second through-hole for wiring communicated to the first through-hole for wiring of said lower conductive layer and not extended to the first inter-layer insulating layer ; and an upper conductive layer formed on said second inter-layer conductive layer , which is electrically connected through the first and second wiring through-holes of said lower insulating layer and inter-layer insulating layers to said lower conductive layer , said upper conductive layer not being electrically connected to said intermediate conductive layer ; wherein the thickness of said at least one lower insulating layer adjacent to said first wiring through-hole is formed is thinner than at positions not adjacent to said first wiring through-hole and said lower insulating layer includes a film having a removal action limiting property in the thickness direction when said lower insulating layer is selectively removed to reduce the thickness thereof . US5332924A CLAIM 19 . A production method of semiconductor device comprising the steps of : forming a lower conductive layer on a surface of or over a semiconductor substrate ; forming at least one insulating layer on said lower conductive layer ; selectively removing said at least one lower insulating layer thereby to form a layer area with a small thickness ; forming an intermediate conductive layer on said at least one lower insulating layer said layer area with a small thickness ; forming a first inter-layer insulating layer and a second inter-layer insulating layer on said intermediate conductive layer ; selectively removing said second inter-layer insulating layer thereby to form a first through-hole for wiring , said first through-hole not extending to said first inter-layer insulating layer ; selectively removing said first inter-layer insulating layer and lower insulating layer to form a second through-hole for wiring which is communicated to the first through-hole of said second inter-layer insulating layer and extended to said lower conductive layer , said second through-hole having an opening area smaller than said first through-hole of said second inter-layer insulating layer ; and forming an upper conductive layer on said second inter-layer insulating layer , which is electrically connected through the first and second wiring through-holes of said lower insulating layer and inter-layer insulating layers , said upper conductive layer extending to said lower conductive layer and not being electrically connected to said intermediate conductive layer ; wherein the step of selectively removing said lower insulating layer to form a layer area small in thickness utilizes an insulating film (second etch stop layer, second interlevel dielectric layer, multiple etch, first etch, multiple etch stop insulation layer, first etch stop layer, etch process, second etch stop layers, second etch) which is part of said at least one lower insulating layer and has a function of limiting removal of said lower insulating layer thereby to limit the removal action in the thickness direction thereof . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US5332924A CLAIM 8 . A production method of a semiconductor device , comprising the steps of : forming a lower conductive layer on a surface of or over a semiconductor substrate ; forming a lower insulating layer on said lower conductive layer ; forming an intermediate conductive layer on said lower insulating layer ; forming a first inter-layer insulating layer on said intermediate conductive layer ; forming a second inter-layer insulating layer on said first inter-layer insulating layer ; forming a third inter-layer insulating layer on said second inter-layer insulating layer ; selectively removing said third inter-layer insulating layer thereby forming a first through-hole for wiring extended to said second inter-layer insulating layer , said selective removal action in a direction perpendicular to said third inter-layer insulating layer being stopped by said second inter-layer insulating layer ; selectively removing said second inter-layer insulating layer , first inter-layer insulating layer and lower insulating layer thereby forming a second through-hole for wiring , said second through-hole communicating said first through-hole and extending to said lower conductive layer , an opening area of said second through-hole being smaller in size than an opening area of a top of said first through-hole ; and forming (anti reflective coating) an upper conductive layer for wiring on said third inter-layer insulating layer , which is electrically connected through said first and said second through-holes of said lower insulating layer , first inter-layer insulating layer , second inter-layer insulating layer and third inter-layer insulating layer to the said lower conductive layer , said upper conductive layer not being connected electrically to said intermediate conductive layer ; wherein said upper conductive layer is in contact with an upper face of said first inter-layer insulating layer in said first contact-hole of said third inter-layer insulating layer . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5275972A Filed: 1992-08-14 Issued: 1994-01-04 Method for fabricating a semiconductor integrated circuit device including the self-aligned formation of a contact window (Original Assignee) Panasonic Corp (Current Assignee) Panasonic Corp Hisashi Ogawa, Yasushi Naito, Masanori Fukumoto |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region (second contact) coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area (second conductive layer) of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch (first etch) stop layer (fourth insulating) directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5275972A CLAIM 1 . A method for fabricating a semiconductor integrated circuit device including a semiconductor substrate having surface regions , a plurality of first conductive layers , each of said first conductive layers covered with a first insulating film forming a plurality of first insulating films , and a plurality of diffusion layers in the surface regions of said semiconductor substrate between said first conductive layers , each of said diffusion layers functioning as a second conductive layer (substrate coupling area) , comprising the steps of : forming a second insulating film over said semiconductor substrate to cover said plurality of diffusion layers and said first insulating films ; forming a silicon oxide film on said second insulating film , said silicon oxide film being doped with impurities ; forming a first etch (first etch) ing mask on said silicon oxide film , said first etching mask having first openings that define a pattern of first contact windows ; performing an isotropic dry etching process to remove portions of said silicon oxide film exposed through said first openings in said first etching mask , thereby exposing the surface of said second insulating film ; performing an anisotropic dry etching process to remove portions of said second insulating film exposed through said first openings in said first etching mask , thereby exposing the surface of said plurality of diffusion layers , and forming said first contact windows ; removing said first etching mask ; performing a glass flow process to make said silicon oxide film soften and flow ; forming a plurality of third conductive layers on said silicon oxide film , to contact with said plurality of diffusion layers through said first contact windows ; forming a third insulating film on said silicon oxide film , to cover said plurality of third conductive layers ; forming a second etching mask on said third insulating film , said second etching mask having second openings that define a pattern of second contact (contact region) windows ; performing an anisotropic dry etching process to remove portions of said third insulating film exposed through said second openings in said second etching mask , to remove portions of said silicon oxide film and said second insulating film exposed through said second openings in said second etching mask , thereby exposing the surface of said plurality of diffusion layers and forming said second contact windows ; removing said second etching mask ; and forming a plurality of fourth conductive layers on said third insulating film , to contact with said plurality of diffusion layers through said second contact windows . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch (first etch) stop layer (fourth insulating) protects removal of a substrate material by an etch process (etching apparatus) . |
US5275972A CLAIM 1 . A method for fabricating a semiconductor integrated circuit device including a semiconductor substrate having surface regions , a plurality of first conductive layers , each of said first conductive layers covered with a first insulating film forming a plurality of first insulating films , and a plurality of diffusion layers in the surface regions of said semiconductor substrate between said first conductive layers , each of said diffusion layers functioning as a second conductive layer , comprising the steps of : forming a second insulating film over said semiconductor substrate to cover said plurality of diffusion layers and said first insulating films ; forming a silicon oxide film on said second insulating film , said silicon oxide film being doped with impurities ; forming a first etch (first etch) ing mask on said silicon oxide film , said first etching mask having first openings that define a pattern of first contact windows ; performing an isotropic dry etching process to remove portions of said silicon oxide film exposed through said first openings in said first etching mask , thereby exposing the surface of said second insulating film ; performing an anisotropic dry etching process to remove portions of said second insulating film exposed through said first openings in said first etching mask , thereby exposing the surface of said plurality of diffusion layers , and forming said first contact windows ; removing said first etching mask ; performing a glass flow process to make said silicon oxide film soften and flow ; forming a plurality of third conductive layers on said silicon oxide film , to contact with said plurality of diffusion layers through said first contact windows ; forming a third insulating film on said silicon oxide film , to cover said plurality of third conductive layers ; forming a second etching mask on said third insulating film , said second etching mask having second openings that define a pattern of second contact windows ; performing an anisotropic dry etching process to remove portions of said third insulating film exposed through said second openings in said second etching mask , to remove portions of said silicon oxide film and said second insulating film exposed through said second openings in said second etching mask , thereby exposing the surface of said plurality of diffusion layers and forming said second contact windows ; removing said second etching mask ; and forming a plurality of fourth conductive layers on said third insulating film , to contact with said plurality of diffusion layers through said second contact windows . US5275972A CLAIM 4 . A method according to claim 1 , wherein said isotropic dry etching process is performed in a microwave plasma etching apparatus (etch process, lithography process) . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric layer insulates said contact region (second contact) . |
US5275972A CLAIM 1 . A method for fabricating a semiconductor integrated circuit device including a semiconductor substrate having surface regions , a plurality of first conductive layers , each of said first conductive layers covered with a first insulating film forming a plurality of first insulating films , and a plurality of diffusion layers in the surface regions of said semiconductor substrate between said first conductive layers , each of said diffusion layers functioning as a second conductive layer , comprising the steps of : forming a second insulating film over said semiconductor substrate to cover said plurality of diffusion layers and said first insulating films ; forming a silicon oxide film on said second insulating film , said silicon oxide film being doped with impurities ; forming a first etching mask on said silicon oxide film , said first etching mask having first openings that define a pattern of first contact windows ; performing an isotropic dry etching process to remove portions of said silicon oxide film exposed through said first openings in said first etching mask , thereby exposing the surface of said second insulating film ; performing an anisotropic dry etching process to remove portions of said second insulating film exposed through said first openings in said first etching mask , thereby exposing the surface of said plurality of diffusion layers , and forming said first contact windows ; removing said first etching mask ; performing a glass flow process to make said silicon oxide film soften and flow ; forming a plurality of third conductive layers on said silicon oxide film , to contact with said plurality of diffusion layers through said first contact windows ; forming a third insulating film on said silicon oxide film , to cover said plurality of third conductive layers ; forming a second etching mask on said third insulating film , said second etching mask having second openings that define a pattern of second contact (contact region) windows ; performing an anisotropic dry etching process to remove portions of said third insulating film exposed through said second openings in said second etching mask , to remove portions of said silicon oxide film and said second insulating film exposed through said second openings in said second etching mask , thereby exposing the surface of said plurality of diffusion layers and forming said second contact windows ; removing said second etching mask ; and forming a plurality of fourth conductive layers on said third insulating film , to contact with said plurality of diffusion layers through said second contact windows . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric layer insulates said contact region (second contact) . |
US5275972A CLAIM 1 . A method for fabricating a semiconductor integrated circuit device including a semiconductor substrate having surface regions , a plurality of first conductive layers , each of said first conductive layers covered with a first insulating film forming a plurality of first insulating films , and a plurality of diffusion layers in the surface regions of said semiconductor substrate between said first conductive layers , each of said diffusion layers functioning as a second conductive layer , comprising the steps of : forming a second insulating film over said semiconductor substrate to cover said plurality of diffusion layers and said first insulating films ; forming a silicon oxide film on said second insulating film , said silicon oxide film being doped with impurities ; forming a first etching mask on said silicon oxide film , said first etching mask having first openings that define a pattern of first contact windows ; performing an isotropic dry etching process to remove portions of said silicon oxide film exposed through said first openings in said first etching mask , thereby exposing the surface of said second insulating film ; performing an anisotropic dry etching process to remove portions of said second insulating film exposed through said first openings in said first etching mask , thereby exposing the surface of said plurality of diffusion layers , and forming said first contact windows ; removing said first etching mask ; performing a glass flow process to make said silicon oxide film soften and flow ; forming a plurality of third conductive layers on said silicon oxide film , to contact with said plurality of diffusion layers through said first contact windows ; forming a third insulating film on said silicon oxide film , to cover said plurality of third conductive layers ; forming a second etching mask on said third insulating film , said second etching mask having second openings that define a pattern of second contact (contact region) windows ; performing an anisotropic dry etching process to remove portions of said third insulating film exposed through said second openings in said second etching mask , to remove portions of said silicon oxide film and said second insulating film exposed through said second openings in said second etching mask , thereby exposing the surface of said plurality of diffusion layers and forming said second contact windows ; removing said second etching mask ; and forming a plurality of fourth conductive layers on said third insulating film , to contact with said plurality of diffusion layers through said second contact windows . |
| US7977797B2 CLAIM 6 . An integrated circuit of claim 1 wherein said spacer region insulates said contact region (second contact) . |
US5275972A CLAIM 1 . A method for fabricating a semiconductor integrated circuit device including a semiconductor substrate having surface regions , a plurality of first conductive layers , each of said first conductive layers covered with a first insulating film forming a plurality of first insulating films , and a plurality of diffusion layers in the surface regions of said semiconductor substrate between said first conductive layers , each of said diffusion layers functioning as a second conductive layer , comprising the steps of : forming a second insulating film over said semiconductor substrate to cover said plurality of diffusion layers and said first insulating films ; forming a silicon oxide film on said second insulating film , said silicon oxide film being doped with impurities ; forming a first etching mask on said silicon oxide film , said first etching mask having first openings that define a pattern of first contact windows ; performing an isotropic dry etching process to remove portions of said silicon oxide film exposed through said first openings in said first etching mask , thereby exposing the surface of said second insulating film ; performing an anisotropic dry etching process to remove portions of said second insulating film exposed through said first openings in said first etching mask , thereby exposing the surface of said plurality of diffusion layers , and forming said first contact windows ; removing said first etching mask ; performing a glass flow process to make said silicon oxide film soften and flow ; forming a plurality of third conductive layers on said silicon oxide film , to contact with said plurality of diffusion layers through said first contact windows ; forming a third insulating film on said silicon oxide film , to cover said plurality of third conductive layers ; forming a second etching mask on said third insulating film , said second etching mask having second openings that define a pattern of second contact (contact region) windows ; performing an anisotropic dry etching process to remove portions of said third insulating film exposed through said second openings in said second etching mask , to remove portions of said silicon oxide film and said second insulating film exposed through said second openings in said second etching mask , thereby exposing the surface of said plurality of diffusion layers and forming said second contact windows ; removing said second etching mask ; and forming a plurality of fourth conductive layers on said third insulating film , to contact with said plurality of diffusion layers through said second contact windows . |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area (second conductive layer) of said contact region (second contact) permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
US5275972A CLAIM 1 . A method for fabricating a semiconductor integrated circuit device including a semiconductor substrate having surface regions , a plurality of first conductive layers , each of said first conductive layers covered with a first insulating film forming a plurality of first insulating films , and a plurality of diffusion layers in the surface regions of said semiconductor substrate between said first conductive layers , each of said diffusion layers functioning as a second conductive layer (substrate coupling area) , comprising the steps of : forming a second insulating film over said semiconductor substrate to cover said plurality of diffusion layers and said first insulating films ; forming a silicon oxide film on said second insulating film , said silicon oxide film being doped with impurities ; forming a first etching mask on said silicon oxide film , said first etching mask having first openings that define a pattern of first contact windows ; performing an isotropic dry etching process to remove portions of said silicon oxide film exposed through said first openings in said first etching mask , thereby exposing the surface of said second insulating film ; performing an anisotropic dry etching process to remove portions of said second insulating film exposed through said first openings in said first etching mask , thereby exposing the surface of said plurality of diffusion layers , and forming said first contact windows ; removing said first etching mask ; performing a glass flow process to make said silicon oxide film soften and flow ; forming a plurality of third conductive layers on said silicon oxide film , to contact with said plurality of diffusion layers through said first contact windows ; forming a third insulating film on said silicon oxide film , to cover said plurality of third conductive layers ; forming a second etching mask on said third insulating film , said second etching mask having second openings that define a pattern of second contact (contact region) windows ; performing an anisotropic dry etching process to remove portions of said third insulating film exposed through said second openings in said second etching mask , to remove portions of said silicon oxide film and said second insulating film exposed through said second openings in said second etching mask , thereby exposing the surface of said plurality of diffusion layers and forming said second contact windows ; removing said second etching mask ; and forming a plurality of fourth conductive layers on said third insulating film , to contact with said plurality of diffusion layers through said second contact windows . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch (first etch) stop layer (fourth insulating) is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5275972A CLAIM 1 . A method for fabricating a semiconductor integrated circuit device including a semiconductor substrate having surface regions , a plurality of first conductive layers , each of said first conductive layers covered with a first insulating film forming a plurality of first insulating films , and a plurality of diffusion layers in the surface regions of said semiconductor substrate between said first conductive layers , each of said diffusion layers functioning as a second conductive layer , comprising the steps of : forming a second insulating film over said semiconductor substrate to cover said plurality of diffusion layers and said first insulating films ; forming a silicon oxide film on said second insulating film , said silicon oxide film being doped with impurities ; forming a first etch (first etch) ing mask on said silicon oxide film , said first etching mask having first openings that define a pattern of first contact windows ; performing an isotropic dry etching process to remove portions of said silicon oxide film exposed through said first openings in said first etching mask , thereby exposing the surface of said second insulating film ; performing an anisotropic dry etching process to remove portions of said second insulating film exposed through said first openings in said first etching mask , thereby exposing the surface of said plurality of diffusion layers , and forming said first contact windows ; removing said first etching mask ; performing a glass flow process to make said silicon oxide film soften and flow ; forming a plurality of third conductive layers on said silicon oxide film , to contact with said plurality of diffusion layers through said first contact windows ; forming a third insulating film on said silicon oxide film , to cover said plurality of third conductive layers ; forming a second etching mask on said third insulating film , said second etching mask having second openings that define a pattern of second contact windows ; performing an anisotropic dry etching process to remove portions of said third insulating film exposed through said second openings in said second etching mask , to remove portions of said silicon oxide film and said second insulating film exposed through said second openings in said second etching mask , thereby exposing the surface of said plurality of diffusion layers and forming said second contact windows ; removing said second etching mask ; and forming a plurality of fourth conductive layers on said third insulating film , to contact with said plurality of diffusion layers through said second contact windows . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric layer for said contact region (second contact) is in a first range (surface region) of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5275972A CLAIM 1 . A method for fabricating a semiconductor integrated circuit device including a semiconductor substrate having surface region (first range) s , a plurality of first conductive layers , each of said first conductive layers covered with a first insulating film forming a plurality of first insulating films , and a plurality of diffusion layers in the surface regions of said semiconductor substrate between said first conductive layers , each of said diffusion layers functioning as a second conductive layer , comprising the steps of : forming a second insulating film over said semiconductor substrate to cover said plurality of diffusion layers and said first insulating films ; forming a silicon oxide film on said second insulating film , said silicon oxide film being doped with impurities ; forming a first etching mask on said silicon oxide film , said first etching mask having first openings that define a pattern of first contact windows ; performing an isotropic dry etching process to remove portions of said silicon oxide film exposed through said first openings in said first etching mask , thereby exposing the surface of said second insulating film ; performing an anisotropic dry etching process to remove portions of said second insulating film exposed through said first openings in said first etching mask , thereby exposing the surface of said plurality of diffusion layers , and forming said first contact windows ; removing said first etching mask ; performing a glass flow process to make said silicon oxide film soften and flow ; forming a plurality of third conductive layers on said silicon oxide film , to contact with said plurality of diffusion layers through said first contact windows ; forming a third insulating film on said silicon oxide film , to cover said plurality of third conductive layers ; forming a second etching mask on said third insulating film , said second etching mask having second openings that define a pattern of second contact (contact region) windows ; performing an anisotropic dry etching process to remove portions of said third insulating film exposed through said second openings in said second etching mask , to remove portions of said silicon oxide film and said second insulating film exposed through said second openings in said second etching mask , thereby exposing the surface of said plurality of diffusion layers and forming said second contact windows ; removing said second etching mask ; and forming a plurality of fourth conductive layers on said third insulating film , to contact with said plurality of diffusion layers through said second contact windows . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US5275972A CLAIM 1 . A method for fabricating a semiconductor integrated circuit device including a semiconductor substrate having surface regions , a plurality of first conductive layers , each of said first conductive layers covered with a first insulating film forming a plurality of first insulating films , and a plurality of diffusion layers in the surface regions of said semiconductor substrate between said first conductive layers , each of said diffusion layers functioning as a second conductive layer , comprising the steps of : forming a second insulating film over said semiconductor substrate to cover said plurality of diffusion layers and said first insulating films ; forming a silicon oxide film on said second insulating film , said silicon oxide film being doped with impurities ; forming a first etching mask on said silicon oxide film , said first etching mask having first openings that define a pattern of first contact windows ; performing an isotropic dry etching process to remove portions of said silicon oxide film exposed through said first openings in said first etching mask , thereby exposing the surface of said second insulating film ; performing an anisotropic dry etching process to remove portions of said second insulating film exposed through said first openings in said first etching mask , thereby exposing the surface of said plurality of diffusion layers , and forming (anti reflective coating) said first contact windows ; removing said first etching mask ; performing a glass flow process to make said silicon oxide film soften and flow ; forming a plurality of third conductive layers on said silicon oxide film , to contact with said plurality of diffusion layers through said first contact windows ; forming a third insulating film on said silicon oxide film , to cover said plurality of third conductive layers ; forming a second etching mask on said third insulating film , said second etching mask having second openings that define a pattern of second contact windows ; performing an anisotropic dry etching process to remove portions of said third insulating film exposed through said second openings in said second etching mask , to remove portions of said silicon oxide film and said second insulating film exposed through said second openings in said second etching mask , thereby exposing the surface of said plurality of diffusion layers and forming said second contact windows ; removing said second etching mask ; and forming a plurality of fourth conductive layers on said third insulating film , to contact with said plurality of diffusion layers through said second contact windows . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch (first etch) stop layer (fourth insulating) and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region (second contact) and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process (etching apparatus) ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area (second conductive layer) of said contact region is smaller than a metal layer coupling area of said contact region . |
US5275972A CLAIM 4 . A method according to claim 1 , wherein said isotropic dry etching process is performed in a microwave plasma etching apparatus (etch process, lithography process) . US5275972A CLAIM 5 . A method for fabricating a semiconductor integrated circuit device including a semiconductor substrate having surface regions , a plurality of first conductive layers , each of said first conductive layers covered with a first insulating film forming a plurality of first insulating films , and a plurality of diffusion layers in the surface regions of said semiconductor substrate between said first conductive layers , each of said diffusion layers functioning as a second conductive layer (substrate coupling area) , comprising the steps of : forming a second insulating film over said semiconductor substrate to cover said plurality of diffusion layers and said first insulating films ; forming a silicon film on said second insulating film ; forming a silicon oxide film on said silicon film , said silicon oxide film being doped with impurities ; forming an etching mask on said silicon oxide film , said etching mask having openings that define a pattern of contact windows ; performing an anisotropic dry etching process to remove portions of said silicon oxide film exposed through said openings in said etching mask , thereby exposing the surface of said silicon film ; performing an isotropic dry etching process to remove portions of said silicon film exposed through said openings in said etching mask , thereby causing said silicon oxide film to overhang ; performing an anisotropic dry etching process to remove portions of said second insulating film exposed through said openings in said etching mask , thereby exposing the surface of said plurality of diffusion layers , and forming said contact windows ; removing said etching mask ; and performing a glass flow process to make said silicon oxide film soften and flow , thereby making said silicon oxide film cover fully said silicon film . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US5275972A CLAIM 2 . A method according to claim 1 , wherein said step of forming said second insulating film comprises the steps of : forming a base silicon oxide film over said semiconductor substrate ; and forming (anti reflective coating) a silicon nitride film on said base silicon oxide film . |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region (second contact) is a first range (surface region) of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5275972A CLAIM 5 . A method for fabricating a semiconductor integrated circuit device including a semiconductor substrate having surface region (first range) s , a plurality of first conductive layers , each of said first conductive layers covered with a first insulating film forming a plurality of first insulating films , and a plurality of diffusion layers in the surface regions of said semiconductor substrate between said first conductive layers , each of said diffusion layers functioning as a second conductive layer , comprising the steps of : forming a second insulating film over said semiconductor substrate to cover said plurality of diffusion layers and said first insulating films ; forming a silicon film on said second insulating film ; forming a silicon oxide film on said silicon film , said silicon oxide film being doped with impurities ; forming an etching mask on said silicon oxide film , said etching mask having openings that define a pattern of contact windows ; performing an anisotropic dry etching process to remove portions of said silicon oxide film exposed through said openings in said etching mask , thereby exposing the surface of said silicon film ; performing an isotropic dry etching process to remove portions of said silicon film exposed through said openings in said etching mask , thereby causing said silicon oxide film to overhang ; performing an anisotropic dry etching process to remove portions of said second insulating film exposed through said openings in said etching mask , thereby exposing the surface of said plurality of diffusion layers , and forming said contact windows ; removing said etching mask ; and performing a glass flow process to make said silicon oxide film soften and flow , thereby making said silicon oxide film cover fully said silicon film . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5187638A Filed: 1992-07-27 Issued: 1993-02-16 Barrier layers for ferroelectric and pzt dielectric on silicon (Original Assignee) Micron Technology Inc (Current Assignee) Micron Technology Inc ; Micron Semiconductor Inc Gurtej S. Sandhu, Pierre Fazan |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (conductive oxide) of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5187638A CLAIM 1 . A capacitor for a semiconductor device constructed on a silicon substrate comprising : a) a first conductive electrode comprising a single metal ; b) a cell dielectric material superjacent said first conductive electrode ; and c) a second conductive electrode superjacent said cell dielectric material ; wherein a conductive oxide (metal layer coupling area) layer exists between said metal electrode and said cell dielectric and a metal silicide contact between said metal electrode and said silicon substrate . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch stop layer protects removal of a substrate material by an etch process (dielectric material) . |
US5187638A CLAIM 1 . A capacitor for a semiconductor device constructed on a silicon substrate comprising : a) a first conductive electrode comprising a single metal ; b) a cell dielectric material (etch process) superjacent said first conductive electrode ; and c) a second conductive electrode superjacent said cell dielectric material ; wherein a conductive oxide layer exists between said metal electrode and said cell dielectric and a metal silicide contact between said metal electrode and said silicon substrate . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch stop layer protects lower layers during an etching process (doped polysilicon) . |
US5187638A CLAIM 9 . The capacitor of claim 1 wherein said second conductive electrode comprises conductively doped polysilicon (etching process) . |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area of said contact region permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area (conductive oxide) of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
US5187638A CLAIM 1 . A capacitor for a semiconductor device constructed on a silicon substrate comprising : a) a first conductive electrode comprising a single metal ; b) a cell dielectric material superjacent said first conductive electrode ; and c) a second conductive electrode superjacent said cell dielectric material ; wherein a conductive oxide (metal layer coupling area) layer exists between said metal electrode and said cell dielectric and a metal silicide contact between said metal electrode and said silicon substrate . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US5187638A CLAIM 21 . The process of claim 17 wherein said forming (anti reflective coating) a transition metal electrode comprises depositing said transition metal via chemical vapor deposition . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (conductive oxide) of said contact region . |
US5187638A CLAIM 1 . A capacitor for a semiconductor device constructed on a silicon substrate comprising : a) a first conductive electrode comprising a single metal ; b) a cell dielectric material superjacent said first conductive electrode ; and c) a second conductive electrode superjacent said cell dielectric material ; wherein a conductive oxide (metal layer coupling area) layer exists between said metal electrode and said cell dielectric and a metal silicide contact between said metal electrode and said silicon substrate . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US5187638A CLAIM 21 . The process of claim 17 wherein said forming (anti reflective coating) a transition metal electrode comprises depositing said transition metal via chemical vapor deposition . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5346844A Filed: 1992-06-30 Issued: 1994-09-13 Method for fabricating semiconductor memory device (Original Assignee) Samsung Electronics Co Ltd (Current Assignee) Samsung Electronics Co Ltd Hyun-jin Cho, Taek-Yong Jang |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region (second contact) coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch (said second pattern) stop insulation layer (second insulating layers) coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch (etching rate) stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5346844A CLAIM 1 . A method for fabricating a semiconductor memory device comprising the steps of : forming a first planarized insulating layer on a semiconductor substrate where a transistor having a source , drain and gate electrode is formed ; forming a first contact hole by partly removing said first insulating layer formed on said drain region ; forming a first spacer on an inner side wall of said first contact hole ; forming a bit line connected to said drain region via said first contact hole ; forming a second planarized insulating layer on the overall resultant structure ; forming a second contact (contact region) hole by partly removing said first and second insulating layers (multiple etch stop insulation layer) formed on said source region ; forming a second spacer on an inner side wall of said second contact hole ; and forming a storage electrode connected to said source region via said second contact hole . US5346844A CLAIM 4 . A method for fabricating a semiconductor memory device as claimed in claim 1 , wherein said step Of forming the first spacer on the inner side walls of said contact hole is divided into a step of covering a first insulating material having the different etching rate (first etch, etch process) from that of said first insulating layer with respect to a first anisotropical etching on the overall resultant structure and a step of carrying out said first anisotropical etching on the overall resultant structure , and said step of forming the second spacer on the inner side walls of said second contact hole is divided into a step of covering a second insulating material having the different etching rate from that of said second insulating layer with respect to a second anisotropical etching on the overall resultant structure and a step of carrying out said second anisotropical etching on the overall resultant structure . US5346844A CLAIM 7 . A method for fabricating a semiconductor memory device comprising the steps of : forming a first planarized insulating layer on a semiconductor substrate where a transistor having a source , drain and gate electrode is formed ; forming a first contact hole by partly removing said first insulating layer formed on said drain region , said first contact hole removing step including the steps of : forming a first material layer where a first pattern for forming said first contact hole is formed , on the overall resultant structure where said first insulating layer is formed , forming a third spacer on the inner side walls of said first pattern , and anisotropically etching on the resultant structure using said first pattern and third spacer as an etching mask and taking the surface of said substrate as its etching end point ; forming a bit line connected to said drain region via said first contact hole ; forming a second planarized insulating layer on the overall resultant structure ; forming a second contact hole by partly removing said first and second insulating layers formed on said source region , said second hole forming step including the steps of : forming a second material layer where a second pattern for forming said second contact hole is formed on the overall resultant structure where said second insulating layer is formed , forming a fourth spacer on the inner side wall of said second pattern (multiple etch) , and anisotropically etching on the resultant structure using said second pattern and fourth spacer as an etching mask and taking the surface of said substrate as its etching end point ; and forming a storage electrode connected to said source region via said second contact hole . |
| US7977797B2 CLAIM 2 . An integrated circuit of claim 1 wherein said first etch (etching rate) stop layer protects removal of a substrate material by an etch process (etching rate) . |
US5346844A CLAIM 4 . A method for fabricating a semiconductor memory device as claimed in claim 1 , wherein said step Of forming the first spacer on the inner side walls of said contact hole is divided into a step of covering a first insulating material having the different etching rate (first etch, etch process) from that of said first insulating layer with respect to a first anisotropical etching on the overall resultant structure and a step of carrying out said first anisotropical etching on the overall resultant structure , and said step of forming the second spacer on the inner side walls of said second contact hole is divided into a step of covering a second insulating material having the different etching rate from that of said second insulating layer with respect to a second anisotropical etching on the overall resultant structure and a step of carrying out said second anisotropical etching on the overall resultant structure . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric layer insulates said contact region (second contact) . |
US5346844A CLAIM 1 . A method for fabricating a semiconductor memory device comprising the steps of : forming a first planarized insulating layer on a semiconductor substrate where a transistor having a source , drain and gate electrode is formed ; forming a first contact hole by partly removing said first insulating layer formed on said drain region ; forming a first spacer on an inner side wall of said first contact hole ; forming a bit line connected to said drain region via said first contact hole ; forming a second planarized insulating layer on the overall resultant structure ; forming a second contact (contact region) hole by partly removing said first and second insulating layers formed on said source region ; forming a second spacer on an inner side wall of said second contact hole ; and forming a storage electrode connected to said source region via said second contact hole . |
| US7977797B2 CLAIM 4 . An integrated circuit of claim 1 wherein said second etch stop layer protects lower layers during an etching process (doped polysilicon) . |
US5346844A CLAIM 6 . A method for fabricating a semiconductor memory device as claimed in claim 5 , wherein said first and second spacers are formed of one or a combination of a CVD oxide layer , a nitride insulating material , undoped polysilicon (etching process) , monocrystal silicon and a PE-TEOS oxide layer . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric layer insulates said contact region (second contact) . |
US5346844A CLAIM 1 . A method for fabricating a semiconductor memory device comprising the steps of : forming a first planarized insulating layer on a semiconductor substrate where a transistor having a source , drain and gate electrode is formed ; forming a first contact hole by partly removing said first insulating layer formed on said drain region ; forming a first spacer on an inner side wall of said first contact hole ; forming a bit line connected to said drain region via said first contact hole ; forming a second planarized insulating layer on the overall resultant structure ; forming a second contact (contact region) hole by partly removing said first and second insulating layers formed on said source region ; forming a second spacer on an inner side wall of said second contact hole ; and forming a storage electrode connected to said source region via said second contact hole . |
| US7977797B2 CLAIM 6 . An integrated circuit of claim 1 wherein said spacer region insulates said contact region (second contact) . |
US5346844A CLAIM 1 . A method for fabricating a semiconductor memory device comprising the steps of : forming a first planarized insulating layer on a semiconductor substrate where a transistor having a source , drain and gate electrode is formed ; forming a first contact hole by partly removing said first insulating layer formed on said drain region ; forming a first spacer on an inner side wall of said first contact hole ; forming a bit line connected to said drain region via said first contact hole ; forming a second planarized insulating layer on the overall resultant structure ; forming a second contact (contact region) hole by partly removing said first and second insulating layers formed on said source region ; forming a second spacer on an inner side wall of said second contact hole ; and forming a storage electrode connected to said source region via said second contact hole . |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area of said contact region (second contact) permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
US5346844A CLAIM 1 . A method for fabricating a semiconductor memory device comprising the steps of : forming a first planarized insulating layer on a semiconductor substrate where a transistor having a source , drain and gate electrode is formed ; forming a first contact hole by partly removing said first insulating layer formed on said drain region ; forming a first spacer on an inner side wall of said first contact hole ; forming a bit line connected to said drain region via said first contact hole ; forming a second planarized insulating layer on the overall resultant structure ; forming a second contact (contact region) hole by partly removing said first and second insulating layers formed on said source region ; forming a second spacer on an inner side wall of said second contact hole ; and forming a storage electrode connected to said source region via said second contact hole . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch (etching rate) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5346844A CLAIM 4 . A method for fabricating a semiconductor memory device as claimed in claim 1 , wherein said step Of forming the first spacer on the inner side walls of said contact hole is divided into a step of covering a first insulating material having the different etching rate (first etch, etch process) from that of said first insulating layer with respect to a first anisotropical etching on the overall resultant structure and a step of carrying out said first anisotropical etching on the overall resultant structure , and said step of forming the second spacer on the inner side walls of said second contact hole is divided into a step of covering a second insulating material having the different etching rate from that of said second insulating layer with respect to a second anisotropical etching on the overall resultant structure and a step of carrying out said second anisotropical etching on the overall resultant structure . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space (first space, said sub) in a portion of said first sub interlevel dielectric layer for said contact region (second contact) is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space (second space) in said second sub interlevel dielectric layer for said contact region is in a second range (second material) of about 0 . 16 μm to 0 . 18 μm wide . |
US5346844A CLAIM 1 . A method for fabricating a semiconductor memory device comprising the steps of : forming a first planarized insulating layer on a semiconductor substrate where a transistor having a source , drain and gate electrode is formed ; forming a first contact hole by partly removing said first insulating layer formed on said drain region ; forming a first space (first space) r on an inner side wall of said first contact hole ; forming a bit line connected to said drain region via said first contact hole ; forming a second planarized insulating layer on the overall resultant structure ; forming a second contact (contact region) hole by partly removing said first and second insulating layers formed on said source region ; forming a second space (second space) r on an inner side wall of said second contact hole ; and forming a storage electrode connected to said source region via said second contact hole . US5346844A CLAIM 7 . A method for fabricating a semiconductor memory device comprising the steps of : forming a first planarized insulating layer on a semiconductor substrate where a transistor having a source , drain and gate electrode is formed ; forming a first contact hole by partly removing said first insulating layer formed on said drain region , said first contact hole removing step including the steps of : forming a first material layer where a first pattern for forming said first contact hole is formed , on the overall resultant structure where said first insulating layer is formed , forming a third spacer on the inner side walls of said first pattern , and anisotropically etching on the resultant structure using said first pattern and third spacer as an etching mask and taking the surface of said sub (first space) strate as its etching end point ; forming a bit line connected to said drain region via said first contact hole ; forming a second planarized insulating layer on the overall resultant structure ; forming a second contact hole by partly removing said first and second insulating layers formed on said source region , said second hole forming step including the steps of : forming a second material (second range) layer where a second pattern for forming said second contact hole is formed on the overall resultant structure where said second insulating layer is formed , forming a fourth spacer on the inner side wall of said second pattern , and anisotropically etching on the resultant structure using said second pattern and fourth spacer as an etching mask and taking the surface of said substrate as its etching end point ; and forming a storage electrode connected to said source region via said second contact hole . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US5346844A CLAIM 1 . A method for fabricating a semiconductor memory device comprising the steps of : forming a first planarized insulating layer on a semiconductor substrate where a transistor having a source , drain and gate electrode is formed ; forming a first contact hole by partly removing said first insulating layer formed on said drain region ; forming a first spacer on an inner side wall of said first contact hole ; forming a bit line connected to said drain region via said first contact hole ; forming a second planarized insulating layer on the overall resultant structure ; forming a second contact hole by partly removing said first and second insulating layers formed on said source region ; forming a second spacer on an inner side wall of said second contact hole ; and forming (anti reflective coating) a storage electrode connected to said source region via said second contact hole . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch (said second pattern) stop insulation layer (second insulating layers) comprising a first etch (etching rate) stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region (second contact) and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US5346844A CLAIM 1 . A method for fabricating a semiconductor memory device comprising the steps of : forming a first planarized insulating layer on a semiconductor substrate where a transistor having a source , drain and gate electrode is formed ; forming a first contact hole by partly removing said first insulating layer formed on said drain region ; forming a first spacer on an inner side wall of said first contact hole ; forming a bit line connected to said drain region via said first contact hole ; forming a second planarized insulating layer on the overall resultant structure ; forming a second contact (contact region) hole by partly removing said first and second insulating layers (multiple etch stop insulation layer) formed on said source region ; forming a second spacer on an inner side wall of said second contact hole ; and forming a storage electrode connected to said source region via said second contact hole . US5346844A CLAIM 4 . A method for fabricating a semiconductor memory device as claimed in claim 1 , wherein said step Of forming the first spacer on the inner side walls of said contact hole is divided into a step of covering a first insulating material having the different etching rate (first etch, etch process) from that of said first insulating layer with respect to a first anisotropical etching on the overall resultant structure and a step of carrying out said first anisotropical etching on the overall resultant structure , and said step of forming the second spacer on the inner side walls of said second contact hole is divided into a step of covering a second insulating material having the different etching rate from that of said second insulating layer with respect to a second anisotropical etching on the overall resultant structure and a step of carrying out said second anisotropical etching on the overall resultant structure . US5346844A CLAIM 7 . A method for fabricating a semiconductor memory device comprising the steps of : forming a first planarized insulating layer on a semiconductor substrate where a transistor having a source , drain and gate electrode is formed ; forming a first contact hole by partly removing said first insulating layer formed on said drain region , said first contact hole removing step including the steps of : forming a first material layer where a first pattern for forming said first contact hole is formed , on the overall resultant structure where said first insulating layer is formed , forming a third spacer on the inner side walls of said first pattern , and anisotropically etching on the resultant structure using said first pattern and third spacer as an etching mask and taking the surface of said substrate as its etching end point ; forming a bit line connected to said drain region via said first contact hole ; forming a second planarized insulating layer on the overall resultant structure ; forming a second contact hole by partly removing said first and second insulating layers formed on said source region , said second hole forming step including the steps of : forming a second material layer where a second pattern for forming said second contact hole is formed on the overall resultant structure where said second insulating layer is formed , forming a fourth spacer on the inner side wall of said second pattern (multiple etch) , and anisotropically etching on the resultant structure using said second pattern and fourth spacer as an etching mask and taking the surface of said substrate as its etching end point ; and forming a storage electrode connected to said source region via said second contact hole . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch (etching rate) stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5346844A CLAIM 4 . A method for fabricating a semiconductor memory device as claimed in claim 1 , wherein said step Of forming the first spacer on the inner side walls of said contact hole is divided into a step of covering a first insulating material having the different etching rate (first etch, etch process) from that of said first insulating layer with respect to a first anisotropical etching on the overall resultant structure and a step of carrying out said first anisotropical etching on the overall resultant structure , and said step of forming the second spacer on the inner side walls of said second contact hole is divided into a step of covering a second insulating material having the different etching rate from that of said second insulating layer with respect to a second anisotropical etching on the overall resultant structure and a step of carrying out said second anisotropical etching on the overall resultant structure . |
| US7977797B2 CLAIM 13 . An integrated circuit of claim 11 further comprising a floating gate (drain region) . |
US5346844A CLAIM 1 . A method for fabricating a semiconductor memory device comprising the steps of : forming a first planarized insulating layer on a semiconductor substrate where a transistor having a source , drain and gate electrode is formed ; forming a first contact hole by partly removing said first insulating layer formed on said drain region (floating gate) ; forming a first spacer on an inner side wall of said first contact hole ; forming a bit line connected to said drain region via said first contact hole ; forming a second planarized insulating layer on the overall resultant structure ; forming a second contact hole by partly removing said first and second insulating layers formed on said source region ; forming a second spacer on an inner side wall of said second contact hole ; and forming a storage electrode connected to said source region via said second contact hole . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US5346844A CLAIM 1 . A method for fabricating a semiconductor memory device comprising the steps of : forming a first planarized insulating layer on a semiconductor substrate where a transistor having a source , drain and gate electrode is formed ; forming a first contact hole by partly removing said first insulating layer formed on said drain region ; forming a first spacer on an inner side wall of said first contact hole ; forming a bit line connected to said drain region via said first contact hole ; forming a second planarized insulating layer on the overall resultant structure ; forming a second contact hole by partly removing said first and second insulating layers formed on said source region ; forming a second spacer on an inner side wall of said second contact hole ; and forming (anti reflective coating) a storage electrode connected to said source region via said second contact hole . |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region (second contact) is a first range of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range (second material) of about 0 . 16 μm to 0 . 18 μm wide . |
US5346844A CLAIM 1 . A method for fabricating a semiconductor memory device comprising the steps of : forming a first planarized insulating layer on a semiconductor substrate where a transistor having a source , drain and gate electrode is formed ; forming a first contact hole by partly removing said first insulating layer formed on said drain region ; forming a first spacer on an inner side wall of said first contact hole ; forming a bit line connected to said drain region via said first contact hole ; forming a second planarized insulating layer on the overall resultant structure ; forming a second contact (contact region) hole by partly removing said first and second insulating layers formed on said source region ; forming a second spacer on an inner side wall of said second contact hole ; and forming a storage electrode connected to said source region via said second contact hole . US5346844A CLAIM 7 . A method for fabricating a semiconductor memory device comprising the steps of : forming a first planarized insulating layer on a semiconductor substrate where a transistor having a source , drain and gate electrode is formed ; forming a first contact hole by partly removing said first insulating layer formed on said drain region , said first contact hole removing step including the steps of : forming a first material layer where a first pattern for forming said first contact hole is formed , on the overall resultant structure where said first insulating layer is formed , forming a third spacer on the inner side walls of said first pattern , and anisotropically etching on the resultant structure using said first pattern and third spacer as an etching mask and taking the surface of said substrate as its etching end point ; forming a bit line connected to said drain region via said first contact hole ; forming a second planarized insulating layer on the overall resultant structure ; forming a second contact hole by partly removing said first and second insulating layers formed on said source region , said second hole forming step including the steps of : forming a second material (second range) layer where a second pattern for forming said second contact hole is formed on the overall resultant structure where said second insulating layer is formed , forming a fourth spacer on the inner side wall of said second pattern , and anisotropically etching on the resultant structure using said second pattern and fourth spacer as an etching mask and taking the surface of said substrate as its etching end point ; and forming a storage electrode connected to said source region via said second contact hole . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5612254A Filed: 1992-06-29 Issued: 1997-03-18 Methods of forming an interconnect on a semiconductor substrate (Original Assignee) Intel Corp (Current Assignee) Intel Corp Xiao-Chun Mu, Srinivasan Sivaram, Donald S. Gardner, David B. Fraser |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric (contact plug) layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5612254A CLAIM 2 . The method of claim 1 , wherein said first and said second dielectric layers comprise a material selected from the group consisting of silicon dioxide , silicon nitride , silicon oxynitride , fluoropolymer , parylene , and polyimide , and wherein said first opening is a type selected from the group consisting of a contact opening and a via opening , said conductive plug is a type selected from the group consisting of a contact plug (interlevel dielectric) and a via plug , and said conductive plug comprises a material selected from the group consisting of tungsten , tantalum , titanium nitride , molybdenum , silicide , and polysilicon . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric (contact plug) layer insulates said contact region . |
US5612254A CLAIM 2 . The method of claim 1 , wherein said first and said second dielectric layers comprise a material selected from the group consisting of silicon dioxide , silicon nitride , silicon oxynitride , fluoropolymer , parylene , and polyimide , and wherein said first opening is a type selected from the group consisting of a contact opening and a via opening , said conductive plug is a type selected from the group consisting of a contact plug (interlevel dielectric) and a via plug , and said conductive plug comprises a material selected from the group consisting of tungsten , tantalum , titanium nitride , molybdenum , silicide , and polysilicon . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric (contact plug) layer insulates said contact region . |
US5612254A CLAIM 2 . The method of claim 1 , wherein said first and said second dielectric layers comprise a material selected from the group consisting of silicon dioxide , silicon nitride , silicon oxynitride , fluoropolymer , parylene , and polyimide , and wherein said first opening is a type selected from the group consisting of a contact opening and a via opening , said conductive plug is a type selected from the group consisting of a contact plug (interlevel dielectric) and a via plug , and said conductive plug comprises a material selected from the group consisting of tungsten , tantalum , titanium nitride , molybdenum , silicide , and polysilicon . |
| US7977797B2 CLAIM 8 . An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (contact plug) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5612254A CLAIM 2 . The method of claim 1 , wherein said first and said second dielectric layers comprise a material selected from the group consisting of silicon dioxide , silicon nitride , silicon oxynitride , fluoropolymer , parylene , and polyimide , and wherein said first opening is a type selected from the group consisting of a contact opening and a via opening , said conductive plug is a type selected from the group consisting of a contact plug (interlevel dielectric) and a via plug , and said conductive plug comprises a material selected from the group consisting of tungsten , tantalum , titanium nitride , molybdenum , silicide , and polysilicon . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric (contact plug) layer for said contact region is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5612254A CLAIM 2 . The method of claim 1 , wherein said first and said second dielectric layers comprise a material selected from the group consisting of silicon dioxide , silicon nitride , silicon oxynitride , fluoropolymer , parylene , and polyimide , and wherein said first opening is a type selected from the group consisting of a contact opening and a via opening , said conductive plug is a type selected from the group consisting of a contact plug (interlevel dielectric) and a via plug , and said conductive plug comprises a material selected from the group consisting of tungsten , tantalum , titanium nitride , molybdenum , silicide , and polysilicon . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers (silicon nitride layer) have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric (contact plug) layer and said second etch stop layer formed under a second interlevel dielectric layer , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region . |
US5612254A CLAIM 2 . The method of claim 1 , wherein said first and said second dielectric layers comprise a material selected from the group consisting of silicon dioxide , silicon nitride , silicon oxynitride , fluoropolymer , parylene , and polyimide , and wherein said first opening is a type selected from the group consisting of a contact opening and a via opening , said conductive plug is a type selected from the group consisting of a contact plug (interlevel dielectric) and a via plug , and said conductive plug comprises a material selected from the group consisting of tungsten , tantalum , titanium nitride , molybdenum , silicide , and polysilicon . US5612254A CLAIM 13 . A method of forming an interconnect on a semiconductor substrate comprising the steps of : depositing a silicon nitride layer (second etch stop layers) on said substrate ; patterning said silicon nitride layer to form a patterned silicon nitride layer having a first opening ; filling said fast opening with a conductive plug ; depositing a dielectric layer over said patterned silicon nitride layer and said conductive plug ; patterning said dielectric layer to form a patterned dielectric layer having an interconnect channel such that at least part of said interconnect channel lies over at least part of said conductive plug ; depositing an interconnect layer over said patterned dielectric layer and within said interconnect channel ; patterning said interconnect layer to form said interconnect such that said interconnect lies on at least part of said conductive plug and part of said patterned silicon nitride layer ; removing said patterned dielectric layer after said step of patterning said interconnect layer ; and depositing a diffusion barrier layer over said interconnect , said interconnect being encapsulated by said patterned silicon nitride layer , said conductive plug , and said diffusion barrier layer . |
| US7977797B2 CLAIM 12 . An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Šthick , said first sub interlevel dielectric (contact plug) layer is in a range of about 1 , 000 to 2 , 000 Šthick , said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10K ű1K Šthick . |
US5612254A CLAIM 2 . The method of claim 1 , wherein said first and said second dielectric layers comprise a material selected from the group consisting of silicon dioxide , silicon nitride , silicon oxynitride , fluoropolymer , parylene , and polyimide , and wherein said first opening is a type selected from the group consisting of a contact opening and a via opening , said conductive plug is a type selected from the group consisting of a contact plug (interlevel dielectric) and a via plug , and said conductive plug comprises a material selected from the group consisting of tungsten , tantalum , titanium nitride , molybdenum , silicide , and polysilicon . |
| US7977797B2 Filed: 2004-09-02 Issued: 2011-07-12 Integrated circuit with contact region and multiple etch stop insulation layer (Original Assignee) Spansion LLC (Current Assignee) Monterey Research LLC Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari | US5248628A Filed: 1992-06-09 Issued: 1993-09-28 Method of fabricating a semiconductor memory device (Original Assignee) Toshiba Corp (Current Assignee) Toshiba Corp Naoko Okabe, Satoshi Inoue, Kazumasa Sunouchi, Takashi Yamada, Akihiro Nitayama, Hiroshi Takato |
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| US7977797B2 CLAIM 1 . An integrated circuit comprising a substrate for providing an electrical well for said integrated circuit ; a contact region (second electrical conductivity, first electrical conductivity, second contact) coupled to said substrate , said contact region provides an electrical path to and from said substrate ; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (said plate) of said contact region ; and a multiple etch stop insulation layer coupled to said contact region , wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region , and wherein said multiple etch stop insulation layer includes : a first etch stop layer directly on said substrate in said contact region ; a first sub interlevel dielectric layer over said first etch stop layer ; a second etch stop layer over said first sub interlevel dielectric layer , wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer ; and a second sub interlevel dielectric layer over said second etch stop layer . |
US5248628A CLAIM 1 . A method of fabricating a semiconductor memory device comprising the steps of : forming a MOSFET having a gate electrode , source and drain regions of a second electrical conductivity (contact region) type impurity material formed in a surface of a semiconductor substrate of a first electrical conductivity (contact region) type material ; forming a first inter-layer insulating film over said gate electrode ; forming a first contact hole such as to expose a surface of said substrate and to be contacted with at least one of the source and drain regions of said MOSFET ; forming a second contact (contact region) hole such as to expose a surface of said substrate and to be contacted with another of the source and drain regions of said MOSFET ; embedding a first electrically conductive layer in said first contact hole up to a position higher than the gate electrode ; embedding a second electrically conductive layer in said second contact hole up to a position higher than the gate electrode ; forming a second inter-layer insulating film over said first and second electrically conductive layers ; forming a third contact hole as a storage node contact hole by selectively removing part of said second inter-layer insulating film to expose the first electrically conductive layer ; forming a storage node electrode connected to one of the source and drain regions of the MOSFET through said storage node contact hole ; forming a capacitor insulating film over said storage node electrode ; forming a plate electrode over said capacitor insulating film ; forming a third inter-layer insulating film over said plate (metal layer coupling area, second interlevel dielectric layer) electrode ; forming a fourth contact hole as a bit line contact hole by selectively removing part of said second and third inter-layer insulating films to expose the second electrically conductive layer ; and forming a bit line connected to another of the source and drain regions of said MOSFET through said bit line contact hole . |
| US7977797B2 CLAIM 3 . An integrated circuit of claim 1 wherein said first sub interlevel dielectric layer insulates said contact region (second electrical conductivity, first electrical conductivity, second contact) . |
US5248628A CLAIM 1 . A method of fabricating a semiconductor memory device comprising the steps of : forming a MOSFET having a gate electrode , source and drain regions of a second electrical conductivity (contact region) type impurity material formed in a surface of a semiconductor substrate of a first electrical conductivity (contact region) type material ; forming a first inter-layer insulating film over said gate electrode ; forming a first contact hole such as to expose a surface of said substrate and to be contacted with at least one of the source and drain regions of said MOSFET ; forming a second contact (contact region) hole such as to expose a surface of said substrate and to be contacted with another of the source and drain regions of said MOSFET ; embedding a first electrically conductive layer in said first contact hole up to a position higher than the gate electrode ; embedding a second electrically conductive layer in said second contact hole up to a position higher than the gate electrode ; forming a second inter-layer insulating film over said first and second electrically conductive layers ; forming a third contact hole as a storage node contact hole by selectively removing part of said second inter-layer insulating film to expose the first electrically conductive layer ; forming a storage node electrode connected to one of the source and drain regions of the MOSFET through said storage node contact hole ; forming a capacitor insulating film over said storage node electrode ; forming a plate electrode over said capacitor insulating film ; forming a third inter-layer insulating film over said plate electrode ; forming a fourth contact hole as a bit line contact hole by selectively removing part of said second and third inter-layer insulating films to expose the second electrically conductive layer ; and forming a bit line connected to another of the source and drain regions of said MOSFET through said bit line contact hole . |
| US7977797B2 CLAIM 5 . An integrated circuit of claim 1 wherein said second sub interlevel dielectric layer insulates said contact region (second electrical conductivity, first electrical conductivity, second contact) . |
US5248628A CLAIM 1 . A method of fabricating a semiconductor memory device comprising the steps of : forming a MOSFET having a gate electrode , source and drain regions of a second electrical conductivity (contact region) type impurity material formed in a surface of a semiconductor substrate of a first electrical conductivity (contact region) type material ; forming a first inter-layer insulating film over said gate electrode ; forming a first contact hole such as to expose a surface of said substrate and to be contacted with at least one of the source and drain regions of said MOSFET ; forming a second contact (contact region) hole such as to expose a surface of said substrate and to be contacted with another of the source and drain regions of said MOSFET ; embedding a first electrically conductive layer in said first contact hole up to a position higher than the gate electrode ; embedding a second electrically conductive layer in said second contact hole up to a position higher than the gate electrode ; forming a second inter-layer insulating film over said first and second electrically conductive layers ; forming a third contact hole as a storage node contact hole by selectively removing part of said second inter-layer insulating film to expose the first electrically conductive layer ; forming a storage node electrode connected to one of the source and drain regions of the MOSFET through said storage node contact hole ; forming a capacitor insulating film over said storage node electrode ; forming a plate electrode over said capacitor insulating film ; forming a third inter-layer insulating film over said plate electrode ; forming a fourth contact hole as a bit line contact hole by selectively removing part of said second and third inter-layer insulating films to expose the second electrically conductive layer ; and forming a bit line connected to another of the source and drain regions of said MOSFET through said bit line contact hole . |
| US7977797B2 CLAIM 6 . An integrated circuit of claim 1 wherein said spacer region insulates said contact region (second electrical conductivity, first electrical conductivity, second contact) . |
US5248628A CLAIM 1 . A method of fabricating a semiconductor memory device comprising the steps of : forming a MOSFET having a gate electrode , source and drain regions of a second electrical conductivity (contact region) type impurity material formed in a surface of a semiconductor substrate of a first electrical conductivity (contact region) type material ; forming a first inter-layer insulating film over said gate electrode ; forming a first contact hole such as to expose a surface of said substrate and to be contacted with at least one of the source and drain regions of said MOSFET ; forming a second contact (contact region) hole such as to expose a surface of said substrate and to be contacted with another of the source and drain regions of said MOSFET ; embedding a first electrically conductive layer in said first contact hole up to a position higher than the gate electrode ; embedding a second electrically conductive layer in said second contact hole up to a position higher than the gate electrode ; forming a second inter-layer insulating film over said first and second electrically conductive layers ; forming a third contact hole as a storage node contact hole by selectively removing part of said second inter-layer insulating film to expose the first electrically conductive layer ; forming a storage node electrode connected to one of the source and drain regions of the MOSFET through said storage node contact hole ; forming a capacitor insulating film over said storage node electrode ; forming a plate electrode over said capacitor insulating film ; forming a third inter-layer insulating film over said plate electrode ; forming a fourth contact hole as a bit line contact hole by selectively removing part of said second and third inter-layer insulating films to expose the second electrically conductive layer ; and forming a bit line connected to another of the source and drain regions of said MOSFET through said bit line contact hole . |
| US7977797B2 CLAIM 7 . An integrated circuit of claim 1 wherein said substrate coupling area of said contact region (second electrical conductivity, first electrical conductivity, second contact) permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area (said plate) of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD) . |
US5248628A CLAIM 1 . A method of fabricating a semiconductor memory device comprising the steps of : forming a MOSFET having a gate electrode , source and drain regions of a second electrical conductivity (contact region) type impurity material formed in a surface of a semiconductor substrate of a first electrical conductivity (contact region) type material ; forming a first inter-layer insulating film over said gate electrode ; forming a first contact hole such as to expose a surface of said substrate and to be contacted with at least one of the source and drain regions of said MOSFET ; forming a second contact (contact region) hole such as to expose a surface of said substrate and to be contacted with another of the source and drain regions of said MOSFET ; embedding a first electrically conductive layer in said first contact hole up to a position higher than the gate electrode ; embedding a second electrically conductive layer in said second contact hole up to a position higher than the gate electrode ; forming a second inter-layer insulating film over said first and second electrically conductive layers ; forming a third contact hole as a storage node contact hole by selectively removing part of said second inter-layer insulating film to expose the first electrically conductive layer ; forming a storage node electrode connected to one of the source and drain regions of the MOSFET through said storage node contact hole ; forming a capacitor insulating film over said storage node electrode ; forming a plate electrode over said capacitor insulating film ; forming a third inter-layer insulating film over said plate (metal layer coupling area, second interlevel dielectric layer) electrode ; forming a fourth contact hole as a bit line contact hole by selectively removing part of said second and third inter-layer insulating films to expose the second electrically conductive layer ; and forming a bit line connected to another of the source and drain regions of said MOSFET through said bit line contact hole . |
| US7977797B2 CLAIM 9 . An integrated circuit of claim 1 wherein an area of a first space (said sub) in a portion of said first sub interlevel dielectric layer for said contact region (second electrical conductivity, first electrical conductivity, second contact) is in a first range of about 0 . 06 μm to 0 . 13 μm wide and an area of a second space (drain regions, storage node) in said second sub interlevel dielectric layer for said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5248628A CLAIM 1 . A method of fabricating a semiconductor memory device comprising the steps of : forming a MOSFET having a gate electrode , source and drain regions (floating gate, second space) of a second electrical conductivity (contact region) type impurity material formed in a surface of a semiconductor substrate of a first electrical conductivity (contact region) type material ; forming a first inter-layer insulating film over said gate electrode ; forming a first contact hole such as to expose a surface of said sub (first space) strate and to be contacted with at least one of the source and drain regions of said MOSFET ; forming a second contact (contact region) hole such as to expose a surface of said substrate and to be contacted with another of the source and drain regions of said MOSFET ; embedding a first electrically conductive layer in said first contact hole up to a position higher than the gate electrode ; embedding a second electrically conductive layer in said second contact hole up to a position higher than the gate electrode ; forming a second inter-layer insulating film over said first and second electrically conductive layers ; forming a third contact hole as a storage node (floating gate, second space) contact hole by selectively removing part of said second inter-layer insulating film to expose the first electrically conductive layer ; forming a storage node electrode connected to one of the source and drain regions of the MOSFET through said storage node contact hole ; forming a capacitor insulating film over said storage node electrode ; forming a plate electrode over said capacitor insulating film ; forming a third inter-layer insulating film over said plate electrode ; forming a fourth contact hole as a bit line contact hole by selectively removing part of said second and third inter-layer insulating films to expose the second electrically conductive layer ; and forming a bit line connected to another of the source and drain regions of said MOSFET through said bit line contact hole . |
| US7977797B2 CLAIM 10 . An integrated circuit of claim 1 further comprising depositing an anti reflective coating (d forming) layer . |
US5248628A CLAIM 1 . A method of fabricating a semiconductor memory device comprising the steps of : forming a MOSFET having a gate electrode , source and drain regions of a second electrical conductivity type impurity material formed in a surface of a semiconductor substrate of a first electrical conductivity type material ; forming a first inter-layer insulating film over said gate electrode ; forming a first contact hole such as to expose a surface of said substrate and to be contacted with at least one of the source and drain regions of said MOSFET ; forming a second contact hole such as to expose a surface of said substrate and to be contacted with another of the source and drain regions of said MOSFET ; embedding a first electrically conductive layer in said first contact hole up to a position higher than the gate electrode ; embedding a second electrically conductive layer in said second contact hole up to a position higher than the gate electrode ; forming a second inter-layer insulating film over said first and second electrically conductive layers ; forming a third contact hole as a storage node contact hole by selectively removing part of said second inter-layer insulating film to expose the first electrically conductive layer ; forming a storage node electrode connected to one of the source and drain regions of the MOSFET through said storage node contact hole ; forming a capacitor insulating film over said storage node electrode ; forming a plate electrode over said capacitor insulating film ; forming a third inter-layer insulating film over said plate electrode ; forming a fourth contact hole as a bit line contact hole by selectively removing part of said second and third inter-layer insulating films to expose the second electrically conductive layer ; and forming (anti reflective coating) a bit line connected to another of the source and drain regions of said MOSFET through said bit line contact hole . |
| US7977797B2 CLAIM 11 . An integrated circuit comprising : a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics , said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region (second electrical conductivity, first electrical conductivity, second contact) and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer (said plate) , wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer , wherein said multiple etch stop insulation layer is formed utilizing a lithography process ; a contact region in said multiple etch stop insulation layer , wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer , wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom , such that a substrate coupling area of said contact region is smaller than a metal layer coupling area (said plate) of said contact region . |
US5248628A CLAIM 1 . A method of fabricating a semiconductor memory device comprising the steps of : forming a MOSFET having a gate electrode , source and drain regions of a second electrical conductivity (contact region) type impurity material formed in a surface of a semiconductor substrate of a first electrical conductivity (contact region) type material ; forming a first inter-layer insulating film over said gate electrode ; forming a first contact hole such as to expose a surface of said substrate and to be contacted with at least one of the source and drain regions of said MOSFET ; forming a second contact (contact region) hole such as to expose a surface of said substrate and to be contacted with another of the source and drain regions of said MOSFET ; embedding a first electrically conductive layer in said first contact hole up to a position higher than the gate electrode ; embedding a second electrically conductive layer in said second contact hole up to a position higher than the gate electrode ; forming a second inter-layer insulating film over said first and second electrically conductive layers ; forming a third contact hole as a storage node contact hole by selectively removing part of said second inter-layer insulating film to expose the first electrically conductive layer ; forming a storage node electrode connected to one of the source and drain regions of the MOSFET through said storage node contact hole ; forming a capacitor insulating film over said storage node electrode ; forming a plate electrode over said capacitor insulating film ; forming a third inter-layer insulating film over said plate (metal layer coupling area, second interlevel dielectric layer) electrode ; forming a fourth contact hole as a bit line contact hole by selectively removing part of said second and third inter-layer insulating films to expose the second electrically conductive layer ; and forming a bit line connected to another of the source and drain regions of said MOSFET through said bit line contact hole . |
| US7977797B2 CLAIM 13 . An integrated circuit of claim 11 further comprising a floating gate (drain regions, storage node) . |
US5248628A CLAIM 1 . A method of fabricating a semiconductor memory device comprising the steps of : forming a MOSFET having a gate electrode , source and drain regions (floating gate, second space) of a second electrical conductivity type impurity material formed in a surface of a semiconductor substrate of a first electrical conductivity type material ; forming a first inter-layer insulating film over said gate electrode ; forming a first contact hole such as to expose a surface of said substrate and to be contacted with at least one of the source and drain regions of said MOSFET ; forming a second contact hole such as to expose a surface of said substrate and to be contacted with another of the source and drain regions of said MOSFET ; embedding a first electrically conductive layer in said first contact hole up to a position higher than the gate electrode ; embedding a second electrically conductive layer in said second contact hole up to a position higher than the gate electrode ; forming a second inter-layer insulating film over said first and second electrically conductive layers ; forming a third contact hole as a storage node (floating gate, second space) contact hole by selectively removing part of said second inter-layer insulating film to expose the first electrically conductive layer ; forming a storage node electrode connected to one of the source and drain regions of the MOSFET through said storage node contact hole ; forming a capacitor insulating film over said storage node electrode ; forming a plate electrode over said capacitor insulating film ; forming a third inter-layer insulating film over said plate electrode ; forming a fourth contact hole as a bit line contact hole by selectively removing part of said second and third inter-layer insulating films to expose the second electrically conductive layer ; and forming a bit line connected to another of the source and drain regions of said MOSFET through said bit line contact hole . |
| US7977797B2 CLAIM 14 . An integrated circuit of claim 11 further comprising depositing an anti reflective coating (d forming) layer . |
US5248628A CLAIM 1 . A method of fabricating a semiconductor memory device comprising the steps of : forming a MOSFET having a gate electrode , source and drain regions of a second electrical conductivity type impurity material formed in a surface of a semiconductor substrate of a first electrical conductivity type material ; forming a first inter-layer insulating film over said gate electrode ; forming a first contact hole such as to expose a surface of said substrate and to be contacted with at least one of the source and drain regions of said MOSFET ; forming a second contact hole such as to expose a surface of said substrate and to be contacted with another of the source and drain regions of said MOSFET ; embedding a first electrically conductive layer in said first contact hole up to a position higher than the gate electrode ; embedding a second electrically conductive layer in said second contact hole up to a position higher than the gate electrode ; forming a second inter-layer insulating film over said first and second electrically conductive layers ; forming a third contact hole as a storage node contact hole by selectively removing part of said second inter-layer insulating film to expose the first electrically conductive layer ; forming a storage node electrode connected to one of the source and drain regions of the MOSFET through said storage node contact hole ; forming a capacitor insulating film over said storage node electrode ; forming a plate electrode over said capacitor insulating film ; forming a third inter-layer insulating film over said plate electrode ; forming a fourth contact hole as a bit line contact hole by selectively removing part of said second and third inter-layer insulating films to expose the second electrically conductive layer ; and forming (anti reflective coating) a bit line connected to another of the source and drain regions of said MOSFET through said bit line contact hole . |
| US7977797B2 CLAIM 15 . An integrated circuit of claim 11 wherein a bottom of said contact region (second electrical conductivity, first electrical conductivity, second contact) is a first range of about 0 . 06 μm to 0 . 13 μm wide and a top of said contact region is in a second range of about 0 . 16 μm to 0 . 18 μm wide . |
US5248628A CLAIM 1 . A method of fabricating a semiconductor memory device comprising the steps of : forming a MOSFET having a gate electrode , source and drain regions of a second electrical conductivity (contact region) type impurity material formed in a surface of a semiconductor substrate of a first electrical conductivity (contact region) type material ; forming a first inter-layer insulating film over said gate electrode ; forming a first contact hole such as to expose a surface of said substrate and to be contacted with at least one of the source and drain regions of said MOSFET ; forming a second contact (contact region) hole such as to expose a surface of said substrate and to be contacted with another of the source and drain regions of said MOSFET ; embedding a first electrically conductive layer in said first contact hole up to a position higher than the gate electrode ; embedding a second electrically conductive layer in said second contact hole up to a position higher than the gate electrode ; forming a second inter-layer insulating film over said first and second electrically conductive layers ; forming a third contact hole as a storage node contact hole by selectively removing part of said second inter-layer insulating film to expose the first electrically conductive layer ; forming a storage node electrode connected to one of the source and drain regions of the MOSFET through said storage node contact hole ; forming a capacitor insulating film over said storage node electrode ; forming a plate electrode over said capacitor insulating film ; forming a third inter-layer insulating film over said plate electrode ; forming a fourth contact hole as a bit line contact hole by selectively removing part of said second and third inter-layer insulating films to expose the second electrically conductive layer ; and forming a bit line connected to another of the source and drain regions of said MOSFET through said bit line contact hole . |