AS Pseudo Claim Charting Due Diligence US6854067B1

Purpose: Invalidity Analysis

Patent: US6854067B1
Filed: 2000-10-30
Issued: 2005-02-08
Patent Holder: (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC
Inventor(s): Harold Kutz, Warren Snyder

Title: Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller

Abstract: A method and system dynamically controlling microcontroller power. In one embodiment, the method and system configures a microcontroller power state, senses its condition, and determines its suitability status, communicates that status between a POR circuit and a processor, controls certain microcontroller functions accordingly, and dynamically programs power related functions. This is enabled, in one embodiment, by dynamic interaction between the POR circuit and the processor. Microcontroller power status is ascertained, and a corresponding optimal power state determined. Optimal values for programmable independent multiples of a supply voltage is programmatically calculated and set, dynamically adjusting microcontroller power states. In one embodiment, the optimal values are communicated to a scaler in the POR circuit by the processor, and registered within a multiplexer/register matrix within the scaler. The processor commands the matrix to change programmable independent multiples of supply voltage to correspond with the optimal values, and monitors corresponding action and power status.

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Ground	References	Owner of the Reference	Title	Semantic Mapping	Challenged Claims
Ground	References	Owner of the Reference	Title	Semantic Mapping	1	2	3	4	5	6	7	9	11	12	13	14	15	16	17	18	19	20
1	US5850156A (Brian Albert Wittman, 1998)	(Original Assignee) Nokia of America Corp (Current Assignee) Avago Technologies General IP Singapore Pte Ltd ; Nokia of America Corp	Processor supervisory circuit and method having increased range of power-on reset signal stability	▪ reset circuit ≈ reset circuit ▪ precision reference voltage ≈ said switch	X	X	X	X		X	X				X	X		X				X
2	US5511161A (Kaoru Sato, 1996)	(Original Assignee) Canon Inc (Current Assignee) Canon Inc	Method and apparatus to reset a microcomputer by resetting the power supply	▪ optimal power, optimal power state ≈ predetermined level ▪ power stability functions ≈ control means	X								X		X					X
3	US5339446A (Takuma Yamasaki, 1994)	(Original Assignee) Toshiba Corp (Current Assignee) Toshiba Corp	Power supply and method for use in a computer system to confirm a save operation of the computer system and to stop a supply of power to the computer system after confirmation	▪ mode pump power supply ≈ control system ▪ precision reference voltage ≈ current values ▪ comparisons comparing one ≈ comparing step ▪ aspect voltages ≈ voltage drop ▪ reset circuit ≈ when power	X	X	X	X		X	X				X	X		X				X
4	US5430395A (Kouzo Ichimaru, 1995)	(Original Assignee) Texas Instruments Inc (Current Assignee) Texas Instruments Inc	Temperature compensated constant-voltage circuit and temperature compensated constant-current circuit	▪ power stability functions ≈ temperature dependence ▪ precision reference voltage ≈ absolute value	X					X	X				X			X
5	US5008846A (Akifumi Inoue, 1991)	(Original Assignee) Toshiba Corp (Current Assignee) Toshiba Corp	Power and signal supply control device	▪ power stability functions ≈ control means ▪ precision reference voltage ≈ said switch ▪ optimal power state ≈ one end	X					X	X		X		X			X		X
6	US4999519A (Goro Kitsukawa, 1991)	(Original Assignee) Hitachi ULSI Engineering Corp; Hitachi Ltd (Current Assignee) Hitachi ULSI Engineering Corp ; Hitachi Ltd	Semiconductor circuit with low power consumption having emitter-coupled logic or differential amplifier	▪ precision reference voltage ≈ absolute value, current values ▪ mode pump power supply, power supply scaler ≈ load circuit ▪ reset circuit ≈ level value	X	X	X	X		X	X	X		X	X	X		X	X		X	X
7	US4766567A (Mitsuharu Kato, 1988)	(Original Assignee) Denso Corp (Current Assignee) Denso Corp	One-chip data processing device including low voltage detector	▪ optimal power ≈ supply voltage level ▪ power state, power state condition ≈ minimum length ▪ power stability functions ≈ control means	X				X	X			X		X		X	X		X		X
8	US6107769A (Michael J. Saylor, 2000)	(Original Assignee) Schneider Automation Inc (Current Assignee) Schneider Electric USA Inc ; Schneider Electric USA Inc	Positional-based motion controller with a bias latch	▪ suitability status ≈ function value ▪ comparisons comparing one ≈ second lookup	X					X					X			X
9	JP2000039937A (Mayumi Maeda, 2000)	(Original Assignee) Toshiba Corp; 株式会社東芝	コンピュータシステムおよびそのパワーセーブ制御方法	▪ power state, power state condition ≈ ロック, の条件 ▪ suitability status ≈ パワー	X				X	X			X		X		X	X		X		X
10	JPH11237931A (Toshiaki Iizuka, 1999)	(Original Assignee) Canon Inc; キヤノン株式会社	情報処理装置	▪ power state condition, power state condition signals ≈ ロック, 備えること ▪ comparisons comparing one ≈ の比較	X				X	X			X		X		X	X		X		X
11	WO9917186A1 (Millind Mittal, 1999)	(Original Assignee) Intel Corporation	Localized performance throttling to reduce ic power consumption	▪ precision reference voltage ≈ current values ▪ power stability functions ≈ control means	X					X	X				X			X
12	JPH1165719A (Yoshio Matsuoka, 1999)	(Original Assignee) Toshiba Corp; 株式会社東芝	コンピュータおよび画像表示方法	▪ precision reference voltage ≈ 画像表示方法 ▪ mode pump power supply, power supply scaler ≈ 電力供給 ▪ power state, power state condition ≈ ロック	X				X	X	X	X	X	X	X		X	X	X	X	X	X
13	JPH1115542A (Takuya Harada, 1999)	(Original Assignee) Denso Corp; 株式会社デンソー	電子制御装置	▪ power state condition signals ≈ なること ▪ mode pump power supply ≈ ライン	X					X					X			X				X
14	JPH10341158A (Masaru Hoshikawa, 1998)	(Original Assignee) Mitsubishi Electric Corp; 三菱電機株式会社	Ａ／ｄ変換装置	▪ suitability status ≈ 前記Ａ ▪ comparisons comparing one ≈ の比較	X					X					X			X
15	JPH10337023A (Masaaki Isa, 1998)	(Original Assignee) Nemic Lambda Kk; ネミック・ラムダ株式会社	スイッチング電源装置	▪ power stability functions ≈ 電源装置 ▪ mode pump power supply ≈ ダイオ, ライン	X										X							X
16	JPH10222256A (Hidenobu Fukushima, 1998)	(Original Assignee) Mitsubishi Electric Corp; 三菱電機株式会社	電力制御装置および電力制御方法	▪ mode pump power supply, power supply scaler ≈ 電力供給 ▪ power state, power state condition ≈ ロック	X				X	X		X	X	X	X		X	X	X	X	X	X
17	US6018559A (Kengo Azegami, 2000)	(Original Assignee) Fujitsu Ltd (Current Assignee) Fujitsu Ltd	Chain-connected shift register and programmable logic circuit whose logic function is changeable in real time	▪ reset circuit ≈ one input terminal ▪ aspect voltages ≈ producing one ▪ power stability functions ≈ NAND gate ▪ optimal power state ≈ d log	X	X	X	X		X			X		X	X		X		X		X
18	US5835396A (Guobiao Zhang, 1998)	(Original Assignee) Zhang; Guobiao	Three-dimensional read-only memory	▪ power state, power state condition ≈ semiconductor layer ▪ optimal power ≈ applied voltage ▪ precision reference voltage ≈ straight line	X				X	X	X		X		X		X	X		X		X
19	US5744944A (Eric J. Danstrom, 1998)	(Original Assignee) SGS Thomson Microelectronics Inc (Current Assignee) STMicroelectronics lnc USA	Programmable bandwidth voltage regulator	▪ mode pump power supply, power state ≈ control output ▪ optimal power ≈ two levels	X				X	X			X		X		X	X		X		X
20	US5614861A (Hiroyuki Harada, 1997)	(Original Assignee) Mitsubishi Electric Corp (Current Assignee) Mitsubishi Electric Corp	N-phase modulated signal demodulation system with carrier reproduction	▪ reset circuit ≈ respective output ▪ optimal power state ≈ d log	X	X	X	X					X		X	X				X		X
21	JPH07209091A (Miki Moyal, 1995)	(Original Assignee) Advanced Micro Devicds Inc; アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド	マイクロプロセッサの温度に関する検知信号提供装置	▪ optimal value ≈ 比較的一定 ▪ power state, power state condition ≈ ロック ▪ mode pump power supply ≈ ダイオ	X				X	X			X	X	X		X	X		X	X	X
22	US5604466A (Daniel M. Dreps, 1997)	(Original Assignee) International Business Machines Corp (Current Assignee) International Business Machines Corp	On-chip voltage controlled oscillator	▪ comparisons comparing one ≈ variable current ▪ aspect voltages ≈ voltage drop ▪ optimal power state ≈ one end						X			X					X		X
23	US5399922A (Khusrow Kiani, 1995)	(Original Assignee) Altera Corp (Current Assignee) Altera Corp	Macrocell comprised of two look-up tables and two flip-flops	▪ power stability functions ≈ control means, NAND gate ▪ optimal value ≈ second log, first log	X								X	X	X					X	X
24	JPH06318160A (Atsushi Fujihira, 1994)	(Original Assignee) Fujitsu Ltd; 富士通株式会社	二重化プロセッサ・システムの系構成制御方式	▪ reset circuit ≈ それぞれダイオード ▪ power state, power state condition ≈ ロック	X	X	X	X	X	X			X		X	X	X	X		X		X
25	EP0566395A1 (Osamu Ikeda, 1993)	(Original Assignee) Dia Semicon Systems Inc (Current Assignee) Dia Semicon Systems Inc	Drive control system for microprocessor with conditional power saving	▪ comparisons comparing one ≈ predetermined criterion ▪ power state, power state condition ≈ lower limit ▪ optimal value ≈ high power	X				X	X			X	X	X		X	X		X	X	X
26	US5376834A (Francesco Carobolante, 1994)	(Original Assignee) SGS Thomson Microelectronics Inc (Current Assignee) STMicroelectronics lnc USA	Initialization circuit for automatically establishing an output to zero or desired reference potential	▪ power supply scaler ≈ phase locked loop circuit ▪ precision reference voltage ≈ said switch						X	X	X		X				X	X		X
27	GB2262004A (Peter John Sladen, 1993)	(Original Assignee) Shaye Communications Ltd (Current Assignee) Shaye Communications Ltd	Charging batteries in portable equipment	▪ mode pump power supply, power state ≈ control output ▪ power stability functions ≈ control means	X				X	X			X		X		X	X		X		X
28	EP0544362A2 (Edward Allyn c/o Int. Octrooiburaau B.V. Burton, 1993)	(Original Assignee) Koninklijke Philips NV (Current Assignee) Koninklijke Philips NV	Electronic circuit with programmable gradual power consumption control	▪ optimal power, power state ≈ second power supply, d log ▪ power stability functions ≈ control means	X				X	X			X		X		X	X		X		X
29	US5304955A (Ahmad H. Atriss, 1994)	(Original Assignee) Motorola Solutions Inc (Current Assignee) Motorola Solutions Inc	Voltage controlled oscillator operating with digital controlled loads in a phase lock loop	▪ reset circuit ≈ second control terminal ▪ optimal power, power state ≈ second power supply, predetermined level ▪ mode pump power supply, power supply scaler ≈ load circuit ▪ optimal value ≈ first log	X	X	X	X	X	X		X	X	X	X	X	X	X	X	X	X	X
30	US5289023A (Carver A. Mead, 1994)	(Original Assignee) Synaptics Inc (Current Assignee) Foveon Inc	High-density photosensor and contactless imaging array having wide dynamic range	▪ reset circuit ≈ output node ▪ optimal power state ≈ one end	X	X	X	X					X		X	X				X		X
31	US5305017A (George E. Gerpheide, 1994)	(Original Assignee) Gerpheide George E (Current Assignee) Cirque Corp	Methods and apparatus for data input	▪ suitability status ≈ data input device ▪ power stability functions ≈ control means ▪ optimal value ≈ first side	X								X	X	X					X	X
32	US5303329A (Carver A. Mead, 1994)	(Original Assignee) Synaptics Inc (Current Assignee) Industrial Technology Research Institute ITRI ; Synaptics Inc	Continuous synaptic weight update mechanism	▪ power stability functions ≈ control means ▪ reset circuit ≈ output node	X										X
33	US5160899A (Janeen D. W. Anderson, 1992)	(Original Assignee) Synaptics Inc (Current Assignee) Synaptics Inc	Adaptable MOS current mirror	▪ power state condition signals ≈ negative voltage ▪ reset circuit ≈ output node	X	X	X	X		X					X	X		X				X
34	US5136188A (Chang W. Ha, 1992)	(Original Assignee) SK Hynix Inc (Current Assignee) Intellectual Ventures II LLC	Input/output macrocell for programmable logic device	▪ power supply scaler ≈ logic operations ▪ optimal power state ≈ d log								X	X	X					X	X	X
35	US5142247A (Henry F. Lada, 1992)	(Original Assignee) Compaq Computer Corp (Current Assignee) Hewlett Packard Development Co LP	Multiple frequency phase-locked loop clock generator with stable transitions between frequencies	▪ reset circuit ≈ second frequency divider, first frequency divider ▪ optimal power state ≈ d log	X	X	X	X					X		X	X				X		X
36	US5235617A (William C. Mallard, 1993)	(Original Assignee) Digital Equipment Corp (Current Assignee) Enterasys Networks Inc	Transmission media driving system	▪ power stability functions ≈ switching signals, control means ▪ precision reference voltage ≈ said switch ▪ optimal power state ≈ one end, d log	X					X	X		X		X			X		X
37	US5166562A (Timothy P. Allen, 1992)	(Original Assignee) Synaptics Inc (Current Assignee) Synaptics Inc	Writable analog reference voltage storage device	▪ power stability functions ≈ control means ▪ reset circuit ≈ output node ▪ precision reference voltage ≈ gate device	X	X	X	X		X	X				X	X		X				X
38	US5146106A (Janeen D. W. Anderson, 1992)	(Original Assignee) Synaptics Inc (Current Assignee) Synaptics Inc	CMOS winner-take all circuit with offset adaptation	▪ precision reference voltage ≈ second layer ▪ reset circuit ≈ output node	X	X	X	X		X	X				X	X		X				X
39	WO9210032A1 (Stephen G. Owens, 1992)	(Original Assignee) Adaptive Solutions, Inc.	Temperature-sensing control system and method for integrated circuits	▪ power state condition, power supply scaler ≈ predetermined temperature ▪ suitability status ≈ determined relationship	X					X		X		X	X			X	X		X
40	US5049758A (Carver A. Mead, 1991)	(Original Assignee) Synaptics Inc (Current Assignee) Synaptics Inc	Adaptable CMOS winner-take all circuit	▪ power state condition signals ≈ negative voltage ▪ reset circuit ≈ output node	X	X	X
41	US5109261A (Carver A. Mead, 1992)	(Original Assignee) Synaptics Inc (Current Assignee) Synaptics Inc	CMOS amplifier with offset adaptation	▪ optimal value ≈ conductive layers ▪ precision reference voltage ≈ second layer						X	X		X	X				X		X	X
42	US5120996A (Carver A. Mead, 1992)	(Original Assignee) Synaptics Inc (Current Assignee) Synaptics Inc	Synaptic element and array	▪ power state condition signals ≈ negative voltage ▪ precision reference voltage ≈ hold circuits						X	X							X
43	US5175884A (Jose I. Suarez, 1992)	(Original Assignee) Motorola Solutions Inc (Current Assignee) Motorola Solutions Inc	Voltage controlled oscillator with current control	▪ suitability status ≈ determined relationship ▪ precision reference voltage ≈ current values ▪ power stability functions ≈ control means	X					X	X				X			X
44	US5059920A (Janeen D. W. Anderson, 1991)	(Original Assignee) Synaptics Inc (Current Assignee) Synaptics Inc	CMOS amplifier with offset adaptation	▪ precision reference voltage ≈ second layer ▪ reset circuit ≈ output node	X	X	X	X		X	X				X	X		X				X
45	US5043674A (Anthony R. Bonaccio, 1991)	(Original Assignee) International Business Machines Corp (Current Assignee) International Business Machines Corp	Differential receiver with high common-mode range	▪ precision reference voltage ≈ source follower transistor ▪ mode pump power supply, power supply scaler ≈ load circuit	X					X	X	X		X	X			X	X		X	X
46	US5006974A (Reza Kazerounian, 1991)	(Original Assignee) Waferscale Integration Inc (Current Assignee) STMicroelectronics lnc USA	On-chip high voltage generator and regulator in an integrated circuit	▪ optimal value ≈ conductive layers ▪ precision reference voltage ≈ said switch						X	X		X	X				X		X	X
47	US5198817A (Robert H. Walden, 1993)	(Original Assignee) Hughes Aircraft Co (Current Assignee) DirecTV Group Inc	High-order sigma-delta analog-to-digital converter	▪ optimal value ≈ first integrating ▪ optimal power ≈ back circuit ▪ comparisons comparing one ≈ first sample						X			X	X				X		X	X
48	US5144582A (Randy C. Steele, 1992)	(Original Assignee) SGS Thomson Microelectronics Inc (Current Assignee) STMicroelectronics lnc USA	Sram based cell for programmable logic devices	▪ mode pump power supply, precision reference voltage ≈ single line ▪ reset circuit ≈ output node ▪ optimal value ≈ first log ▪ power stability functions ≈ NAND gate ▪ optimal power state ≈ d log	X	X	X	X		X	X		X	X	X	X		X		X	X	X
49	US5068622A (Carver A. Mead, 1991)	(Original Assignee) Synaptics Inc (Current Assignee) Synaptics Inc	CMOS amplifier with offset adaptation	▪ power state condition signals ≈ negative voltage ▪ reset circuit ≈ output node	X	X	X	X		X					X	X						X
50	US4980652A (Yoshiaki Tarusawa, 1990)	(Original Assignee) Nippon Telegraph and Telephone Corp (Current Assignee) NTT Docomo Inc	Frequency synthesizer having compensation for nonlinearities	▪ precision reference voltage ≈ measured value, said switch ▪ reset circuit ≈ pass filter	X	X	X	X		X	X				X	X		X				X
51	US4977381A (William E. Main, 1990)	(Original Assignee) Motorola Solutions Inc (Current Assignee) NXP USA Inc	Differential relaxation oscillator	▪ power supply scaler ≈ dynamic voltage ▪ precision reference voltage ≈ said switch						X	X	X		X				X	X		X
52	US5083044A (Carver A. Mead, 1992)	(Original Assignee) Synaptics Inc (Current Assignee) Synaptics Inc	Synaptic element and array	▪ precision reference voltage ≈ hold circuits, said switch ▪ power stability functions ≈ control means ▪ reset circuit ≈ output node	X	X	X	X		X	X				X	X						X
53	US5155836A (Dale A. Jordan, 1992)	(Original Assignee) Jordan Dale A; Fitzsimmons Lynne A; Greenseth William A; Hoffman Gregory L; Stubbs David D	Block diagram system and method for controlling electronic instruments with simulated graphic display	▪ optimal value ≈ predetermined ranges ▪ aspect voltages ≈ signal data						X			X	X				X		X	X
54	US5168463A (Hiroshi Ikeda, 1992)	(Original Assignee) Nissan Motor Co Ltd (Current Assignee) Nissan Motor Co Ltd	Shift register apparatus for storing data therein	▪ suitability status ≈ vehicle state ▪ optimal power state ≈ one end	X								X		X					X
55	US4964074A (Noriyuki Suzuki, 1990)	(Original Assignee) Ando Electric Co Ltd (Current Assignee) Ando Electric Co Ltd	In-circuit emulator	▪ suitability status ≈ second logic value ▪ power state ≈ circuit portion ▪ optimal value ≈ first log	X				X	X			X	X	X		X	X		X	X	X
56	US4876466A (Harufusa Kondou, 1989)	(Original Assignee) Mitsubishi Electric Corp (Current Assignee) Mitsubishi Electric Corp	Programmable logic array having a changeable logic structure	▪ precision reference voltage ≈ said switch ▪ optimal power state ≈ d log						X	X		X					X		X
57	US4868525A (Donald R. Dias, 1989)	(Original Assignee) Dallas Semiconductor Corp (Current Assignee) Maxim Integrated Products Inc	Temperature-stabilized oscillator	▪ power supply scaler ≈ discharging circuit ▪ reset circuit ≈ respective output ▪ optimal power state ≈ d log	X	X	X	X				X	X	X	X	X			X	X	X	X
58	US4833418A (John J. Quintus, 1989)	(Original Assignee) Archive Corp (Current Assignee) Certance LLC	Compensation circuit for nullifying differential offset voltage and regulating common mode voltage of differential signals	▪ optimal value ≈ differential input signal ▪ comparisons comparing one ≈ relative magnitude ▪ reset circuit ≈ first sum signal, pass filter	X	X	X	X		X			X	X	X	X		X		X	X	X
59	US4879461A (Harald Philipp, 1989)	(Original Assignee) Harald Philipp	Energy field sensor using summing means	▪ power state condition ≈ received energy ▪ power stability functions ≈ control means	X					X					X			X
60	US4907121A (Petr Hrassky, 1990)	(Original Assignee) SGS Thomson Microelectronics GmbH (Current Assignee) STMicroelectronics GmbH	Comparator with extended common-mode input voltage range	▪ optimal power ≈ back circuit ▪ precision reference voltage ≈ said switch						X	X		X					X		X
61	US4876534A (Carver A. Mead, 1989)	(Original Assignee) Synaptics Inc (Current Assignee) Foveon Inc	Scanning method and apparatus for current signals having large dynamic range	▪ power state condition signals ≈ negative voltage ▪ optimal power ≈ back circuit						X			X					X		X
62	EP0265209A1 (Shigeru Goda, 1988)	(Original Assignee) Daiwa Shinku Corp (Current Assignee) Daiwa Shinku Corp	Remote control system for a display apparatus	▪ mode pump power supply ≈ control system ▪ precision reference voltage ≈ said switch	X					X	X				X			X				X
63	US4809345A (Kuniaki Tabata, 1989)	(Original Assignee) Hitachi Ltd (Current Assignee) Hitachi Ltd	Method of and apparatus for enlarging/reducing two-dimensional images	▪ suitability status ≈ determined relationship ▪ power stability functions ≈ said first step ▪ comparisons comparing one ≈ first two	X					X					X			X

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	US5850156A Filed: 1996-02-07 Issued: 1998-12-15 Processor supervisory circuit and method having increased range of power-on reset signal stability (Original Assignee) Nokia of America Corp (Current Assignee) Avago Technologies General IP Singapore Pte Ltd ; Nokia of America Corp Brian Albert Wittman
US6854067B1 CLAIM 1 . In a microcontroller with an embedded processor , a switched mode pump power supply and power on reset circuit (reset circuit) , a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply , wherein said processor and said power on reset circuit are interconnectedly coupled , and wherein said switched mode pump power supply is interconnectedly coupled with said power on reset circuit and responsive to signals therefrom ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor ; e) controlling certain functions of said microcontroller accordingly .	US5850156A CLAIM 1 . For use in a processor supervisory circuit , a power-on reset circuit (reset circuit) , comprising : an adaptive , nonlinear voltage divider having a voltage input and a voltage output , said divider dividing an unscaled , unregulated voltage received at said voltage input by a factor that varies as a function of said unscaled , unregulated voltage to produce a scaled , unregulated voltage at said voltage output ; and a comparison circuit for comparing said scaled , unregulated voltage with a scaled , regulated voltage to produce a power-on reset (RESET) signal when said scaled , regulated voltage exceeds said scaled , unregulated voltage , said divider being adaptive and nonlinear to ensure that said comparison circuit continuously produces said RESET signal when said scaled , regulated voltage exceeds said scaled , unregulated voltage and thereby avoid premature activation of a processor couplable to said power-on reset circuit , said comparison circuit employing positive feedback to obtain transfer characteristics with hysteresis .
US6854067B1 CLAIM 2 . The method as recited in claim 1 , further comprising : f) dynamically programming said power on reset circuit (reset circuit) .	US5850156A CLAIM 1 . For use in a processor supervisory circuit , a power-on reset circuit (reset circuit) , comprising : an adaptive , nonlinear voltage divider having a voltage input and a voltage output , said divider dividing an unscaled , unregulated voltage received at said voltage input by a factor that varies as a function of said unscaled , unregulated voltage to produce a scaled , unregulated voltage at said voltage output ; and a comparison circuit for comparing said scaled , unregulated voltage with a scaled , regulated voltage to produce a power-on reset (RESET) signal when said scaled , regulated voltage exceeds said scaled , unregulated voltage , said divider being adaptive and nonlinear to ensure that said comparison circuit continuously produces said RESET signal when said scaled , regulated voltage exceeds said scaled , unregulated voltage and thereby avoid premature activation of a processor couplable to said power-on reset circuit , said comparison circuit employing positive feedback to obtain transfer characteristics with hysteresis .
US6854067B1 CLAIM 3 . The method as recited in claim 2 , wherein said power on reset circuit (reset circuit) and said processor are interconnected via a bus .	US5850156A CLAIM 1 . For use in a processor supervisory circuit , a power-on reset circuit (reset circuit) , comprising : an adaptive , nonlinear voltage divider having a voltage input and a voltage output , said divider dividing an unscaled , unregulated voltage received at said voltage input by a factor that varies as a function of said unscaled , unregulated voltage to produce a scaled , unregulated voltage at said voltage output ; and a comparison circuit for comparing said scaled , unregulated voltage with a scaled , regulated voltage to produce a power-on reset (RESET) signal when said scaled , regulated voltage exceeds said scaled , unregulated voltage , said divider being adaptive and nonlinear to ensure that said comparison circuit continuously produces said RESET signal when said scaled , regulated voltage exceeds said scaled , unregulated voltage and thereby avoid premature activation of a processor couplable to said power-on reset circuit , said comparison circuit employing positive feedback to obtain transfer characteristics with hysteresis .
US6854067B1 CLAIM 4 . The method as recited in claim 3 , wherein said b) and said c) are accomplished by said power on reset circuit (reset circuit) .	US5850156A CLAIM 1 . For use in a processor supervisory circuit , a power-on reset circuit (reset circuit) , comprising : an adaptive , nonlinear voltage divider having a voltage input and a voltage output , said divider dividing an unscaled , unregulated voltage received at said voltage input by a factor that varies as a function of said unscaled , unregulated voltage to produce a scaled , unregulated voltage at said voltage output ; and a comparison circuit for comparing said scaled , unregulated voltage with a scaled , regulated voltage to produce a power-on reset (RESET) signal when said scaled , regulated voltage exceeds said scaled , unregulated voltage , said divider being adaptive and nonlinear to ensure that said comparison circuit continuously produces said RESET signal when said scaled , regulated voltage exceeds said scaled , unregulated voltage and thereby avoid premature activation of a processor couplable to said power-on reset circuit , said comparison circuit employing positive feedback to obtain transfer characteristics with hysteresis .
US6854067B1 CLAIM 6 . The method as recited in claim 5 , wherein said c) further comprises : c1) generating a precision reference voltage (said switch) ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US5850156A CLAIM 9 . The method as recited in claim 8 wherein said divider comprises a switch activatable as a function of said unscaled , unregulated voltage , said step of dividing comprising the step of toggling said switch (precision reference voltage) to introduce an additional resistive element into said divider to change said factor .
US6854067B1 CLAIM 7 . The method as recited in claim 6 , wherein said precision reference voltage (said switch) is independent of said common supply voltage .	US5850156A CLAIM 9 . The method as recited in claim 8 wherein said divider comprises a switch activatable as a function of said unscaled , unregulated voltage , said step of dividing comprising the step of toggling said switch (precision reference voltage) to introduce an additional resistive element into said divider to change said factor .
US6854067B1 CLAIM 13 . In a microcontroller , a system comprising : a bus ; a processor coupled to said bus ; a power on reset circuit (reset circuit) , said processor and said power on reset circuit coupled to said bus and interconnectedly coupled with said processor via said bus ; and a switched mode pump power supply interconnectedly coupled with said power on reset circuit and responsive to signals therefrom wherein said system executes a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor via said bus ; e) controlling certain functions of said microcontroller according to said suitability status ; and f) dynamically programming said power on reset circuit via said bus .	US5850156A CLAIM 1 . For use in a processor supervisory circuit , a power-on reset circuit (reset circuit) , comprising : an adaptive , nonlinear voltage divider having a voltage input and a voltage output , said divider dividing an unscaled , unregulated voltage received at said voltage input by a factor that varies as a function of said unscaled , unregulated voltage to produce a scaled , unregulated voltage at said voltage output ; and a comparison circuit for comparing said scaled , unregulated voltage with a scaled , regulated voltage to produce a power-on reset (RESET) signal when said scaled , regulated voltage exceeds said scaled , unregulated voltage , said divider being adaptive and nonlinear to ensure that said comparison circuit continuously produces said RESET signal when said scaled , regulated voltage exceeds said scaled , unregulated voltage and thereby avoid premature activation of a processor couplable to said power-on reset circuit , said comparison circuit employing positive feedback to obtain transfer characteristics with hysteresis .
US6854067B1 CLAIM 14 . The system as recited in claim 13 , wherein said b) and said c) of said method are accomplished by said power on reset circuit (reset circuit) .	US5850156A CLAIM 1 . For use in a processor supervisory circuit , a power-on reset circuit (reset circuit) , comprising : an adaptive , nonlinear voltage divider having a voltage input and a voltage output , said divider dividing an unscaled , unregulated voltage received at said voltage input by a factor that varies as a function of said unscaled , unregulated voltage to produce a scaled , unregulated voltage at said voltage output ; and a comparison circuit for comparing said scaled , unregulated voltage with a scaled , regulated voltage to produce a power-on reset (RESET) signal when said scaled , regulated voltage exceeds said scaled , unregulated voltage , said divider being adaptive and nonlinear to ensure that said comparison circuit continuously produces said RESET signal when said scaled , regulated voltage exceeds said scaled , unregulated voltage and thereby avoid premature activation of a processor couplable to said power-on reset circuit , said comparison circuit employing positive feedback to obtain transfer characteristics with hysteresis .
US6854067B1 CLAIM 16 . The system as recited in claim 15 , wherein said c) further comprises : c1) generating a precision reference voltage (said switch) , said precision reference voltage independent of said common supply voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US5850156A CLAIM 9 . The method as recited in claim 8 wherein said divider comprises a switch activatable as a function of said unscaled , unregulated voltage , said step of dividing comprising the step of toggling said switch (precision reference voltage) to introduce an additional resistive element into said divider to change said factor .
US6854067B1 CLAIM 20 . In a microcontroller having a power on reset circuit (reset circuit) interconnected with a processor a method of dynamically controlling said power state , said method comprising : a) ascertaining a power state powered by a switched mode pump power supply , said switched mode pump power supply interconnected with and responsive to control by said power on reset circuit ; b) programmatically determining desired changes to said power state ; c) intercommunicating between said processor and said power on reset circuit ; d) adjusting said power on reset circuit corresponding to said desired changes to said power state ; e) controlling said switched mode pump power supply according to said d) ; and f) repeating said a) through e) .	US5850156A CLAIM 1 . For use in a processor supervisory circuit , a power-on reset circuit (reset circuit) , comprising : an adaptive , nonlinear voltage divider having a voltage input and a voltage output , said divider dividing an unscaled , unregulated voltage received at said voltage input by a factor that varies as a function of said unscaled , unregulated voltage to produce a scaled , unregulated voltage at said voltage output ; and a comparison circuit for comparing said scaled , unregulated voltage with a scaled , regulated voltage to produce a power-on reset (RESET) signal when said scaled , regulated voltage exceeds said scaled , unregulated voltage , said divider being adaptive and nonlinear to ensure that said comparison circuit continuously produces said RESET signal when said scaled , regulated voltage exceeds said scaled , unregulated voltage and thereby avoid premature activation of a processor couplable to said power-on reset circuit , said comparison circuit employing positive feedback to obtain transfer characteristics with hysteresis .

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	US5511161A Filed: 1993-11-29 Issued: 1996-04-23 Method and apparatus to reset a microcomputer by resetting the power supply (Original Assignee) Canon Inc (Current Assignee) Canon Inc Kaoru Sato, Toshiyuki Itoh, Kazuhiko Okazawa, Junichi Kimizuka, Akihisa Kusano, Makoto Abe, Toshihiko Inuyama
US6854067B1 CLAIM 1 . In a microcontroller with an embedded processor , a switched mode pump power supply and power on reset circuit , a method of dynamically controlling a plurality of power stability functions (control means) for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply , wherein said processor and said power on reset circuit are interconnectedly coupled , and wherein said switched mode pump power supply is interconnectedly coupled with said power on reset circuit and responsive to signals therefrom ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor ; e) controlling certain functions of said microcontroller accordingly .	US5511161A CLAIM 6 . An interunit communicating system comprising : a main unit ; and at least one subunit , each subunit being connected to the main unit through a power line , wherein said main unit comprises control means (power stability functions) for controlling a power supply to each subunit via said power line , and monitoring means for monitoring a voltage of the power line , and wherein when said main units resets the at least one subunit , the control means shuts off the power supplied to the at least one subunit and restarts the power supply to said at least one subunit after said monitoring means acknowledges that a voltage of the power line drops to a predetermined level by shutting off the power supply so as not to restart the power supply before the voltage of the power line drops to the predetermined level after the power supplied to the at least one subunit is shut off .
US6854067B1 CLAIM 11 . The method as recited in claim 10 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power (predetermined level) state corresponding to said status ; f3) programmatically calculating an optimal value for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	US5511161A CLAIM 1 . A method of resetting a subunit comprising the steps of : shutting off power supplied to the subunit ; discriminating whether a voltage of a power line to the subunit drops to a predetermined level (optimal power, optimal power state) by shutting off the power supplied to the subunit in said shutting off step ; and restarting the power supply to the subunit after it is discriminated that the Voltage drops to the predetermined level in said discriminating step so as not to restart the power supply before the voltage reaches the predetermined level .
US6854067B1 CLAIM 13 . In a microcontroller , a system comprising : a bus ; a processor coupled to said bus ; a power on reset circuit , said processor and said power on reset circuit coupled to said bus and interconnectedly coupled with said processor via said bus ; and a switched mode pump power supply interconnectedly coupled with said power on reset circuit and responsive to signals therefrom wherein said system executes a method of dynamically controlling a plurality of power stability functions (control means) for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor via said bus ; e) controlling certain functions of said microcontroller according to said suitability status ; and f) dynamically programming said power on reset circuit via said bus .	US5511161A CLAIM 6 . An interunit communicating system comprising : a main unit ; and at least one subunit , each subunit being connected to the main unit through a power line , wherein said main unit comprises control means (power stability functions) for controlling a power supply to each subunit via said power line , and monitoring means for monitoring a voltage of the power line , and wherein when said main units resets the at least one subunit , the control means shuts off the power supplied to the at least one subunit and restarts the power supply to said at least one subunit after said monitoring means acknowledges that a voltage of the power line drops to a predetermined level by shutting off the power supply so as not to restart the power supply before the voltage of the power line drops to the predetermined level after the power supplied to the at least one subunit is shut off .
US6854067B1 CLAIM 18 . The system as recited in claim 17 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power (predetermined level) state corresponding to said status ; f3) programmatically calculating an optimal value for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	US5511161A CLAIM 1 . A method of resetting a subunit comprising the steps of : shutting off power supplied to the subunit ; discriminating whether a voltage of a power line to the subunit drops to a predetermined level (optimal power, optimal power state) by shutting off the power supplied to the subunit in said shutting off step ; and restarting the power supply to the subunit after it is discriminated that the Voltage drops to the predetermined level in said discriminating step so as not to restart the power supply before the voltage reaches the predetermined level .

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	US5339446A Filed: 1993-05-18 Issued: 1994-08-16 Power supply and method for use in a computer system to confirm a save operation of the computer system and to stop a supply of power to the computer system after confirmation (Original Assignee) Toshiba Corp (Current Assignee) Toshiba Corp Takuma Yamasaki, Yuuichi Saito
US6854067B1 CLAIM 1 . In a microcontroller with an embedded processor , a switched mode pump power supply (control system) and power on reset circuit (when power) , a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply , wherein said processor and said power on reset circuit are interconnectedly coupled , and wherein said switched mode pump power supply is interconnectedly coupled with said power on reset circuit and responsive to signals therefrom ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor ; e) controlling certain functions of said microcontroller accordingly .	US5339446A CLAIM 9 . The power supply system according to claim 1 , wherein said externally-supplied power off request signal is sent to said computer system when power (reset circuit) of said battery is below a predetermined value . US5339446A CLAIM 12 . A power supply system for use in a computer having a main memory , registers and a battery backed-up random access memory (RAM) , comprising : a power supply section comprising any of a battery and an AC adapter , said power supply section having an output voltage ; a power output section coupled to said power supply section and including coupling means for supplying power from said power supply section to said computer system , and means , responsive to a power off signal , for inhibiting the supply of all power to said computer system ; and a power control section having coupling means for connecting said power control system (mode pump power supply) through a serial transmission path , means including a microcomputer for detecting a degradation of said power supply section output voltage indicative of impending power failure , for receiving an externally-supplied power off request signal and subsequently transmitting a system power off request signal through said serial transmission path to command a save operation to be performed by said computer system , the computer system saving at least contents of the main memory and the registers into the battery backed-up RAM in response to the system power off request signal , and for receiving an acknowledgment signal through said serial transmission path to confirm the completion of said save operation , and means for transmitting said power off signal to said power output section to inhibit the supply of power through said power output section after receipt of said acknowledgment signal .
US6854067B1 CLAIM 2 . The method as recited in claim 1 , further comprising : f) dynamically programming said power on reset circuit (when power) .	US5339446A CLAIM 9 . The power supply system according to claim 1 , wherein said externally-supplied power off request signal is sent to said computer system when power (reset circuit) of said battery is below a predetermined value .
US6854067B1 CLAIM 3 . The method as recited in claim 2 , wherein said power on reset circuit (when power) and said processor are interconnected via a bus .	US5339446A CLAIM 9 . The power supply system according to claim 1 , wherein said externally-supplied power off request signal is sent to said computer system when power (reset circuit) of said battery is below a predetermined value .
US6854067B1 CLAIM 4 . The method as recited in claim 3 , wherein said b) and said c) are accomplished by said power on reset circuit (when power) .	US5339446A CLAIM 9 . The power supply system according to claim 1 , wherein said externally-supplied power off request signal is sent to said computer system when power (reset circuit) of said battery is below a predetermined value .
US6854067B1 CLAIM 6 . The method as recited in claim 5 , wherein said c) further comprises : c1) generating a precision reference voltage (current values) ; c2) dividing said common supply voltage into a plurality of aspect voltages (voltage drop) , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one (comparing step) of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US5339446A CLAIM 5 . The power supply system according to claim 1 , wherein said power control section includes analog-to-digital converter means for converting voltage values and current values (precision reference voltage) from said battery and said AC adapter into digital values . US5339446A CLAIM 11 . A method for cutting off a supply of power by a power supply system for use in a computer , the power supply system including a power supply section comprising any of a battery and an AC adapter , said power supply section having an output voltage , and a power output section coupled to said power supply section , said power output section having a coupling for supplying power from said power supply section to said computer system and being responsive to a power off signal to inhibit the supply of all power to said computer system , the method comprising the steps of : monitoring a voltage and a current of said battery ; changing a reference voltage value in accordance with a detected current value ; comparing a detected voltage value with said reference voltage value and causing a low battery display section to indicate a low battery when said detected voltage value is below said reference voltage value , the comparing step (comparisons comparing one) including the steps of dividing a level of said low battery into first through third sub-levels in accordance with said detected current value , causing said low battery display section to indicate said low battery upon detection of said first sub-level , sending a power off request signal to said computer system upon detection of said second sub-level , and outputting said power off signal to said power output section ; receiving an externally-supplied power off request signal and subsequently transmitting a system power off request signal through said serial transmission path to command a save operation to be performed by said computer system ; receiving an acknowledgment signal through said serial transmission path to confirm the completion of said save operation ; and transmitting said power off signal to said power output section to inhibit the supply of power through said power output section after receipt of said acknowledgment signal . US5339446A CLAIM 32 . A power supply system for use in a computer comprising : a power supply section comprising any of a battery and an AC adapter , said power supply section having an output voltage ; a power output section coupled to said power supply section and including coupling means for supplying power from said power supply section to said computer system , and means , responsive to a power off signal , for inhibiting the supply of all power to said computer system ; and a power control section including means including a microcomputer for charging the battery and for detecting completion of a charge operation when any of the following conditions is satisfied : when the battery voltage drop (aspect voltages) s from a peak value by a given value ; when a charged capacitance of the battery becomes 150% , provided that a nominal capacitance of the battery is 100% ; and when a charging time of the battery exceeds 10 hours .
US6854067B1 CLAIM 7 . The method as recited in claim 6 , wherein said precision reference voltage (current values) is independent of said common supply voltage .	US5339446A CLAIM 5 . The power supply system according to claim 1 , wherein said power control section includes analog-to-digital converter means for converting voltage values and current values (precision reference voltage) from said battery and said AC adapter into digital values .
US6854067B1 CLAIM 13 . In a microcontroller , a system comprising : a bus ; a processor coupled to said bus ; a power on reset circuit (when power) , said processor and said power on reset circuit coupled to said bus and interconnectedly coupled with said processor via said bus ; and a switched mode pump power supply (control system) interconnectedly coupled with said power on reset circuit and responsive to signals therefrom wherein said system executes a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor via said bus ; e) controlling certain functions of said microcontroller according to said suitability status ; and f) dynamically programming said power on reset circuit via said bus .	US5339446A CLAIM 9 . The power supply system according to claim 1 , wherein said externally-supplied power off request signal is sent to said computer system when power (reset circuit) of said battery is below a predetermined value . US5339446A CLAIM 12 . A power supply system for use in a computer having a main memory , registers and a battery backed-up random access memory (RAM) , comprising : a power supply section comprising any of a battery and an AC adapter , said power supply section having an output voltage ; a power output section coupled to said power supply section and including coupling means for supplying power from said power supply section to said computer system , and means , responsive to a power off signal , for inhibiting the supply of all power to said computer system ; and a power control section having coupling means for connecting said power control system (mode pump power supply) through a serial transmission path , means including a microcomputer for detecting a degradation of said power supply section output voltage indicative of impending power failure , for receiving an externally-supplied power off request signal and subsequently transmitting a system power off request signal through said serial transmission path to command a save operation to be performed by said computer system , the computer system saving at least contents of the main memory and the registers into the battery backed-up RAM in response to the system power off request signal , and for receiving an acknowledgment signal through said serial transmission path to confirm the completion of said save operation , and means for transmitting said power off signal to said power output section to inhibit the supply of power through said power output section after receipt of said acknowledgment signal .
US6854067B1 CLAIM 14 . The system as recited in claim 13 , wherein said b) and said c) of said method are accomplished by said power on reset circuit (when power) .	US5339446A CLAIM 9 . The power supply system according to claim 1 , wherein said externally-supplied power off request signal is sent to said computer system when power (reset circuit) of said battery is below a predetermined value .
US6854067B1 CLAIM 16 . The system as recited in claim 15 , wherein said c) further comprises : c1) generating a precision reference voltage (current values) , said precision reference voltage independent of said common supply voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages (voltage drop) , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one (comparing step) of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US5339446A CLAIM 5 . The power supply system according to claim 1 , wherein said power control section includes analog-to-digital converter means for converting voltage values and current values (precision reference voltage) from said battery and said AC adapter into digital values . US5339446A CLAIM 11 . A method for cutting off a supply of power by a power supply system for use in a computer , the power supply system including a power supply section comprising any of a battery and an AC adapter , said power supply section having an output voltage , and a power output section coupled to said power supply section , said power output section having a coupling for supplying power from said power supply section to said computer system and being responsive to a power off signal to inhibit the supply of all power to said computer system , the method comprising the steps of : monitoring a voltage and a current of said battery ; changing a reference voltage value in accordance with a detected current value ; comparing a detected voltage value with said reference voltage value and causing a low battery display section to indicate a low battery when said detected voltage value is below said reference voltage value , the comparing step (comparisons comparing one) including the steps of dividing a level of said low battery into first through third sub-levels in accordance with said detected current value , causing said low battery display section to indicate said low battery upon detection of said first sub-level , sending a power off request signal to said computer system upon detection of said second sub-level , and outputting said power off signal to said power output section ; receiving an externally-supplied power off request signal and subsequently transmitting a system power off request signal through said serial transmission path to command a save operation to be performed by said computer system ; receiving an acknowledgment signal through said serial transmission path to confirm the completion of said save operation ; and transmitting said power off signal to said power output section to inhibit the supply of power through said power output section after receipt of said acknowledgment signal . US5339446A CLAIM 32 . A power supply system for use in a computer comprising : a power supply section comprising any of a battery and an AC adapter , said power supply section having an output voltage ; a power output section coupled to said power supply section and including coupling means for supplying power from said power supply section to said computer system , and means , responsive to a power off signal , for inhibiting the supply of all power to said computer system ; and a power control section including means including a microcomputer for charging the battery and for detecting completion of a charge operation when any of the following conditions is satisfied : when the battery voltage drop (aspect voltages) s from a peak value by a given value ; when a charged capacitance of the battery becomes 150% , provided that a nominal capacitance of the battery is 100% ; and when a charging time of the battery exceeds 10 hours .
US6854067B1 CLAIM 20 . In a microcontroller having a power on reset circuit (when power) interconnected with a processor a method of dynamically controlling said power state , said method comprising : a) ascertaining a power state powered by a switched mode pump power supply (control system) , said switched mode pump power supply interconnected with and responsive to control by said power on reset circuit ; b) programmatically determining desired changes to said power state ; c) intercommunicating between said processor and said power on reset circuit ; d) adjusting said power on reset circuit corresponding to said desired changes to said power state ; e) controlling said switched mode pump power supply according to said d) ; and f) repeating said a) through e) .	US5339446A CLAIM 9 . The power supply system according to claim 1 , wherein said externally-supplied power off request signal is sent to said computer system when power (reset circuit) of said battery is below a predetermined value . US5339446A CLAIM 12 . A power supply system for use in a computer having a main memory , registers and a battery backed-up random access memory (RAM) , comprising : a power supply section comprising any of a battery and an AC adapter , said power supply section having an output voltage ; a power output section coupled to said power supply section and including coupling means for supplying power from said power supply section to said computer system , and means , responsive to a power off signal , for inhibiting the supply of all power to said computer system ; and a power control section having coupling means for connecting said power control system (mode pump power supply) through a serial transmission path , means including a microcomputer for detecting a degradation of said power supply section output voltage indicative of impending power failure , for receiving an externally-supplied power off request signal and subsequently transmitting a system power off request signal through said serial transmission path to command a save operation to be performed by said computer system , the computer system saving at least contents of the main memory and the registers into the battery backed-up RAM in response to the system power off request signal , and for receiving an acknowledgment signal through said serial transmission path to confirm the completion of said save operation , and means for transmitting said power off signal to said power output section to inhibit the supply of power through said power output section after receipt of said acknowledgment signal .

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	US5430395A Filed: 1993-02-26 Issued: 1995-07-04 Temperature compensated constant-voltage circuit and temperature compensated constant-current circuit (Original Assignee) Texas Instruments Inc (Current Assignee) Texas Instruments Inc Kouzo Ichimaru
US6854067B1 CLAIM 1 . In a microcontroller with an embedded processor , a switched mode pump power supply and power on reset circuit , a method of dynamically controlling a plurality of power stability functions (temperature dependence) for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply , wherein said processor and said power on reset circuit are interconnectedly coupled , and wherein said switched mode pump power supply is interconnectedly coupled with said power on reset circuit and responsive to signals therefrom ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor ; e) controlling certain functions of said microcontroller accordingly .	US5430395A CLAIM 5 . The circuit of claim 1 wherein the ratio of area between a pair of transistors that form said first constant-current source circuit , and the value of said first resistor element and the value of said second resistor element are adjusted such that said first temperature coefficient and said second temperature coefficient cancel each other resulting in said circuit being operable without temperature dependence (power stability functions) .
US6854067B1 CLAIM 6 . The method as recited in claim 5 , wherein said c) further comprises : c1) generating a precision reference voltage (absolute value) ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US5430395A CLAIM 3 . The circuit of claim 1 , wherein said second temperature coefficient is the reverse of said first temperature coefficient and the absolute value (precision reference voltage) of said first temperature coefficient and said second temperature coefficient are equal or nearly equal .
US6854067B1 CLAIM 7 . The method as recited in claim 6 , wherein said precision reference voltage (absolute value) is independent of said common supply voltage .	US5430395A CLAIM 3 . The circuit of claim 1 , wherein said second temperature coefficient is the reverse of said first temperature coefficient and the absolute value (precision reference voltage) of said first temperature coefficient and said second temperature coefficient are equal or nearly equal .
US6854067B1 CLAIM 13 . In a microcontroller , a system comprising : a bus ; a processor coupled to said bus ; a power on reset circuit , said processor and said power on reset circuit coupled to said bus and interconnectedly coupled with said processor via said bus ; and a switched mode pump power supply interconnectedly coupled with said power on reset circuit and responsive to signals therefrom wherein said system executes a method of dynamically controlling a plurality of power stability functions (temperature dependence) for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor via said bus ; e) controlling certain functions of said microcontroller according to said suitability status ; and f) dynamically programming said power on reset circuit via said bus .	US5430395A CLAIM 5 . The circuit of claim 1 wherein the ratio of area between a pair of transistors that form said first constant-current source circuit , and the value of said first resistor element and the value of said second resistor element are adjusted such that said first temperature coefficient and said second temperature coefficient cancel each other resulting in said circuit being operable without temperature dependence (power stability functions) .
US6854067B1 CLAIM 16 . The system as recited in claim 15 , wherein said c) further comprises : c1) generating a precision reference voltage (absolute value) , said precision reference voltage independent of said common supply voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US5430395A CLAIM 3 . The circuit of claim 1 , wherein said second temperature coefficient is the reverse of said first temperature coefficient and the absolute value (precision reference voltage) of said first temperature coefficient and said second temperature coefficient are equal or nearly equal .

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	US5008846A Filed: 1989-11-27 Issued: 1991-04-16 Power and signal supply control device (Original Assignee) Toshiba Corp (Current Assignee) Toshiba Corp Akifumi Inoue
US6854067B1 CLAIM 1 . In a microcontroller with an embedded processor , a switched mode pump power supply and power on reset circuit , a method of dynamically controlling a plurality of power stability functions (control means) for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply , wherein said processor and said power on reset circuit are interconnectedly coupled , and wherein said switched mode pump power supply is interconnectedly coupled with said power on reset circuit and responsive to signals therefrom ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor ; e) controlling certain functions of said microcontroller accordingly .	US5008846A CLAIM 1 . A device for controlling supply of power and signals from a main system comprising : a display which is configured to be connected to and disconnected from said main system ; detecting means for detecting whether said display is connected to said main system or not ; supply instructing means responsive to said detecting means , and a reset signal applied thereto , for automatically generating an instruction signal for instructing the supply of power and signals to said display responsive to said reset signal and until said detecting means detects that said display is not connected to said system ; power control means (power stability functions) responsive to the instruction signal for controlling the supply of power to said display to be supplied while said instruction signal instructs said supply of power and signals ; and signal controlling means , responsive to the instruction signal , for controlling the supply of the signals to said display to be supplied while said instruction signal instructs said supply of power and signals .
US6854067B1 CLAIM 6 . The method as recited in claim 5 , wherein said c) further comprises : c1) generating a precision reference voltage (said switch) ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US5008846A CLAIM 8 . A device according to claim 1 , in which said detecting means includes a switch having one end connected to a signal ground of said main system and the other end connected to an end of a pull-up resistor the other end of which is connected to a power supply of said main system , said switch (precision reference voltage) being switched in response to connection or disconnection of said display to and from said main system respectively .
US6854067B1 CLAIM 7 . The method as recited in claim 6 , wherein said precision reference voltage (said switch) is independent of said common supply voltage .	US5008846A CLAIM 8 . A device according to claim 1 , in which said detecting means includes a switch having one end connected to a signal ground of said main system and the other end connected to an end of a pull-up resistor the other end of which is connected to a power supply of said main system , said switch (precision reference voltage) being switched in response to connection or disconnection of said display to and from said main system respectively .
US6854067B1 CLAIM 11 . The method as recited in claim 10 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state (one end) corresponding to said status ; f3) programmatically calculating an optimal value for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	US5008846A CLAIM 7 . A device according to claim 1 , in which said detecting means includes a signal line connecting an input of said supply instructing means to a signal ground of said main system via said display , and a pull-up resistor having one end (optimal power state) connected to a power supply of said main system and the other end connected to said input of said supply instructing means .
US6854067B1 CLAIM 13 . In a microcontroller , a system comprising : a bus ; a processor coupled to said bus ; a power on reset circuit , said processor and said power on reset circuit coupled to said bus and interconnectedly coupled with said processor via said bus ; and a switched mode pump power supply interconnectedly coupled with said power on reset circuit and responsive to signals therefrom wherein said system executes a method of dynamically controlling a plurality of power stability functions (control means) for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor via said bus ; e) controlling certain functions of said microcontroller according to said suitability status ; and f) dynamically programming said power on reset circuit via said bus .	US5008846A CLAIM 1 . A device for controlling supply of power and signals from a main system comprising : a display which is configured to be connected to and disconnected from said main system ; detecting means for detecting whether said display is connected to said main system or not ; supply instructing means responsive to said detecting means , and a reset signal applied thereto , for automatically generating an instruction signal for instructing the supply of power and signals to said display responsive to said reset signal and until said detecting means detects that said display is not connected to said system ; power control means (power stability functions) responsive to the instruction signal for controlling the supply of power to said display to be supplied while said instruction signal instructs said supply of power and signals ; and signal controlling means , responsive to the instruction signal , for controlling the supply of the signals to said display to be supplied while said instruction signal instructs said supply of power and signals .
US6854067B1 CLAIM 16 . The system as recited in claim 15 , wherein said c) further comprises : c1) generating a precision reference voltage (said switch) , said precision reference voltage independent of said common supply voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US5008846A CLAIM 8 . A device according to claim 1 , in which said detecting means includes a switch having one end connected to a signal ground of said main system and the other end connected to an end of a pull-up resistor the other end of which is connected to a power supply of said main system , said switch (precision reference voltage) being switched in response to connection or disconnection of said display to and from said main system respectively .
US6854067B1 CLAIM 18 . The system as recited in claim 17 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state (one end) corresponding to said status ; f3) programmatically calculating an optimal value for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	US5008846A CLAIM 7 . A device according to claim 1 , in which said detecting means includes a signal line connecting an input of said supply instructing means to a signal ground of said main system via said display , and a pull-up resistor having one end (optimal power state) connected to a power supply of said main system and the other end connected to said input of said supply instructing means .

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	US4999519A Filed: 1988-11-30 Issued: 1991-03-12 Semiconductor circuit with low power consumption having emitter-coupled logic or differential amplifier (Original Assignee) Hitachi ULSI Engineering Corp; Hitachi Ltd (Current Assignee) Hitachi ULSI Engineering Corp ; Hitachi Ltd Goro Kitsukawa, Kazumasa Yanagisawa, Takayuki Kawahara, Ryoichi Hori, Yoshinobu Nakagome, Noriyuki Hamma, Kiyoo Itoh, Hiromi Tukada
US6854067B1 CLAIM 1 . In a microcontroller with an embedded processor , a switched mode pump power supply (load circuit) and power on reset circuit (level value) , a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply , wherein said processor and said power on reset circuit are interconnectedly coupled , and wherein said switched mode pump power supply is interconnectedly coupled with said power on reset circuit and responsive to signals therefrom ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor ; e) controlling certain functions of said microcontroller accordingly .	US4999519A CLAIM 7 . A semiconductor circuit comprising : a first circuit having a bipolar current switch and a bipolar emitter-follower ; a second circuit for controlling a current through the first circuit , connected to at least one of a common emitter node of said bipolar current switch and an output of the emitter-follower , said second circuit having at least one MOS transistor arranged to cause the current in said first circuit to be smaller in a standby mode than the current in said first circuit in an operating mode thereof , a first current source for a minute current which is normally caused to flow , and a second current source for a larger current which can be switched on and off ; a third circuit for use as a load circuit (mode pump power supply, power supply scaler) of said bipolar current switch connected to a collector of said bipolar current switch , said third circuit having at lease one MOS transistor arranged to render an output voltage level of said first circuit to substantially the same high and low level value (reset circuit) s irrespective of values of the current ; wherein in accordance with a control timing arrangement the current of said first circuit is caused to flow by both the first and second current sources in the operating mode and the current is caused to flow by only the second current course in the standby mode .
US6854067B1 CLAIM 2 . The method as recited in claim 1 , further comprising : f) dynamically programming said power on reset circuit (level value) .	US4999519A CLAIM 7 . A semiconductor circuit comprising : a first circuit having a bipolar current switch and a bipolar emitter-follower ; a second circuit for controlling a current through the first circuit , connected to at least one of a common emitter node of said bipolar current switch and an output of the emitter-follower , said second circuit having at least one MOS transistor arranged to cause the current in said first circuit to be smaller in a standby mode than the current in said first circuit in an operating mode thereof , a first current source for a minute current which is normally caused to flow , and a second current source for a larger current which can be switched on and off ; a third circuit for use as a load circuit of said bipolar current switch connected to a collector of said bipolar current switch , said third circuit having at lease one MOS transistor arranged to render an output voltage level of said first circuit to substantially the same high and low level value (reset circuit) s irrespective of values of the current ; wherein in accordance with a control timing arrangement the current of said first circuit is caused to flow by both the first and second current sources in the operating mode and the current is caused to flow by only the second current course in the standby mode .
US6854067B1 CLAIM 3 . The method as recited in claim 2 , wherein said power on reset circuit (level value) and said processor are interconnected via a bus .	US4999519A CLAIM 7 . A semiconductor circuit comprising : a first circuit having a bipolar current switch and a bipolar emitter-follower ; a second circuit for controlling a current through the first circuit , connected to at least one of a common emitter node of said bipolar current switch and an output of the emitter-follower , said second circuit having at least one MOS transistor arranged to cause the current in said first circuit to be smaller in a standby mode than the current in said first circuit in an operating mode thereof , a first current source for a minute current which is normally caused to flow , and a second current source for a larger current which can be switched on and off ; a third circuit for use as a load circuit of said bipolar current switch connected to a collector of said bipolar current switch , said third circuit having at lease one MOS transistor arranged to render an output voltage level of said first circuit to substantially the same high and low level value (reset circuit) s irrespective of values of the current ; wherein in accordance with a control timing arrangement the current of said first circuit is caused to flow by both the first and second current sources in the operating mode and the current is caused to flow by only the second current course in the standby mode .
US6854067B1 CLAIM 4 . The method as recited in claim 3 , wherein said b) and said c) are accomplished by said power on reset circuit (level value) .	US4999519A CLAIM 7 . A semiconductor circuit comprising : a first circuit having a bipolar current switch and a bipolar emitter-follower ; a second circuit for controlling a current through the first circuit , connected to at least one of a common emitter node of said bipolar current switch and an output of the emitter-follower , said second circuit having at least one MOS transistor arranged to cause the current in said first circuit to be smaller in a standby mode than the current in said first circuit in an operating mode thereof , a first current source for a minute current which is normally caused to flow , and a second current source for a larger current which can be switched on and off ; a third circuit for use as a load circuit of said bipolar current switch connected to a collector of said bipolar current switch , said third circuit having at lease one MOS transistor arranged to render an output voltage level of said first circuit to substantially the same high and low level value (reset circuit) s irrespective of values of the current ; wherein in accordance with a control timing arrangement the current of said first circuit is caused to flow by both the first and second current sources in the operating mode and the current is caused to flow by only the second current course in the standby mode .
US6854067B1 CLAIM 6 . The method as recited in claim 5 , wherein said c) further comprises : c1) generating a precision reference voltage (absolute value, current values) ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US4999519A CLAIM 11 . The semiconductor circuit of claim 10 , wherein an absolute value (precision reference voltage) of a threshold voltage of said each P-channel MOS transistor in said third circuit is set to be smaller than that of a forward voltage of said each diode in said third circuit . US4999519A CLAIM 13 . A semiconductor circuit comprising : a first circuit having a bipolar current switch and a bipolar emitter-follower ; a second circuit connected to at least one of a common emitter node of said bipolar current switch and an output of the bipolar emitter-follower for control of a current through the first circuit such that the current in said first circuit is made smaller in a standby mode than the current in said first circuit in an operating mode thereof , the second circuit having two sets of MOS transistors connected in series , wherein pulse control signals having polarities different from each other are applied to gates of two MOS transistors selected from the series of MOS transistors , and wherein a common bias voltage is applied to gates of two other MOS transistors , such that a current of said second circuit changes over between two current values (precision reference voltage) determined by a ratio of gate width to gate length of the MOS transistors to which the bias voltage is applied ; and , a third circuit connected as a load to a collector of said bipolar current switch , having at least one MOS transistor arranged such that high and low output voltage levels of said first circuit are substantially constant irrespective of a variance in value of said current .
US6854067B1 CLAIM 7 . The method as recited in claim 6 , wherein said precision reference voltage (absolute value, current values) is independent of said common supply voltage .	US4999519A CLAIM 11 . The semiconductor circuit of claim 10 , wherein an absolute value (precision reference voltage) of a threshold voltage of said each P-channel MOS transistor in said third circuit is set to be smaller than that of a forward voltage of said each diode in said third circuit . US4999519A CLAIM 13 . A semiconductor circuit comprising : a first circuit having a bipolar current switch and a bipolar emitter-follower ; a second circuit connected to at least one of a common emitter node of said bipolar current switch and an output of the bipolar emitter-follower for control of a current through the first circuit such that the current in said first circuit is made smaller in a standby mode than the current in said first circuit in an operating mode thereof , the second circuit having two sets of MOS transistors connected in series , wherein pulse control signals having polarities different from each other are applied to gates of two MOS transistors selected from the series of MOS transistors , and wherein a common bias voltage is applied to gates of two other MOS transistors , such that a current of said second circuit changes over between two current values (precision reference voltage) determined by a ratio of gate width to gate length of the MOS transistors to which the bias voltage is applied ; and , a third circuit connected as a load to a collector of said bipolar current switch , having at least one MOS transistor arranged such that high and low output voltage levels of said first circuit are substantially constant irrespective of a variance in value of said current .
US6854067B1 CLAIM 9 . The method as recited in claim 8 , wherein said b2) is performed by a power supply scaler (load circuit) , and wherein said power supply scaler comprises : a) a divider of said common supply voltage ; b) a matrix of multiplexers and registers , and c) an interconnection to said bus .	US4999519A CLAIM 7 . A semiconductor circuit comprising : a first circuit having a bipolar current switch and a bipolar emitter-follower ; a second circuit for controlling a current through the first circuit , connected to at least one of a common emitter node of said bipolar current switch and an output of the emitter-follower , said second circuit having at least one MOS transistor arranged to cause the current in said first circuit to be smaller in a standby mode than the current in said first circuit in an operating mode thereof , a first current source for a minute current which is normally caused to flow , and a second current source for a larger current which can be switched on and off ; a third circuit for use as a load circuit (mode pump power supply, power supply scaler) of said bipolar current switch connected to a collector of said bipolar current switch , said third circuit having at lease one MOS transistor arranged to render an output voltage level of said first circuit to substantially the same high and low level values irrespective of values of the current ; wherein in accordance with a control timing arrangement the current of said first circuit is caused to flow by both the first and second current sources in the operating mode and the current is caused to flow by only the second current course in the standby mode .
US6854067B1 CLAIM 12 . The method as recited in claim 11 , wherein said f4) further comprises : communicating each said optimal value to said power supply scaler (load circuit) via said bus ; registering each said optimal value with said matrix of multiplexers and registers ; commanding said matrix of multiplexers and registers to change said independent multiple of said common supply voltage to correspond with said optimal value ; and monitoring said matrix of multiplexers and registers .	US4999519A CLAIM 7 . A semiconductor circuit comprising : a first circuit having a bipolar current switch and a bipolar emitter-follower ; a second circuit for controlling a current through the first circuit , connected to at least one of a common emitter node of said bipolar current switch and an output of the emitter-follower , said second circuit having at least one MOS transistor arranged to cause the current in said first circuit to be smaller in a standby mode than the current in said first circuit in an operating mode thereof , a first current source for a minute current which is normally caused to flow , and a second current source for a larger current which can be switched on and off ; a third circuit for use as a load circuit (mode pump power supply, power supply scaler) of said bipolar current switch connected to a collector of said bipolar current switch , said third circuit having at lease one MOS transistor arranged to render an output voltage level of said first circuit to substantially the same high and low level values irrespective of values of the current ; wherein in accordance with a control timing arrangement the current of said first circuit is caused to flow by both the first and second current sources in the operating mode and the current is caused to flow by only the second current course in the standby mode .
US6854067B1 CLAIM 13 . In a microcontroller , a system comprising : a bus ; a processor coupled to said bus ; a power on reset circuit (level value) , said processor and said power on reset circuit coupled to said bus and interconnectedly coupled with said processor via said bus ; and a switched mode pump power supply (load circuit) interconnectedly coupled with said power on reset circuit and responsive to signals therefrom wherein said system executes a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor via said bus ; e) controlling certain functions of said microcontroller according to said suitability status ; and f) dynamically programming said power on reset circuit via said bus .	US4999519A CLAIM 7 . A semiconductor circuit comprising : a first circuit having a bipolar current switch and a bipolar emitter-follower ; a second circuit for controlling a current through the first circuit , connected to at least one of a common emitter node of said bipolar current switch and an output of the emitter-follower , said second circuit having at least one MOS transistor arranged to cause the current in said first circuit to be smaller in a standby mode than the current in said first circuit in an operating mode thereof , a first current source for a minute current which is normally caused to flow , and a second current source for a larger current which can be switched on and off ; a third circuit for use as a load circuit (mode pump power supply, power supply scaler) of said bipolar current switch connected to a collector of said bipolar current switch , said third circuit having at lease one MOS transistor arranged to render an output voltage level of said first circuit to substantially the same high and low level value (reset circuit) s irrespective of values of the current ; wherein in accordance with a control timing arrangement the current of said first circuit is caused to flow by both the first and second current sources in the operating mode and the current is caused to flow by only the second current course in the standby mode .
US6854067B1 CLAIM 14 . The system as recited in claim 13 , wherein said b) and said c) of said method are accomplished by said power on reset circuit (level value) .	US4999519A CLAIM 7 . A semiconductor circuit comprising : a first circuit having a bipolar current switch and a bipolar emitter-follower ; a second circuit for controlling a current through the first circuit , connected to at least one of a common emitter node of said bipolar current switch and an output of the emitter-follower , said second circuit having at least one MOS transistor arranged to cause the current in said first circuit to be smaller in a standby mode than the current in said first circuit in an operating mode thereof , a first current source for a minute current which is normally caused to flow , and a second current source for a larger current which can be switched on and off ; a third circuit for use as a load circuit of said bipolar current switch connected to a collector of said bipolar current switch , said third circuit having at lease one MOS transistor arranged to render an output voltage level of said first circuit to substantially the same high and low level value (reset circuit) s irrespective of values of the current ; wherein in accordance with a control timing arrangement the current of said first circuit is caused to flow by both the first and second current sources in the operating mode and the current is caused to flow by only the second current course in the standby mode .
US6854067B1 CLAIM 16 . The system as recited in claim 15 , wherein said c) further comprises : c1) generating a precision reference voltage (absolute value, current values) , said precision reference voltage independent of said common supply voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US4999519A CLAIM 11 . The semiconductor circuit of claim 10 , wherein an absolute value (precision reference voltage) of a threshold voltage of said each P-channel MOS transistor in said third circuit is set to be smaller than that of a forward voltage of said each diode in said third circuit . US4999519A CLAIM 13 . A semiconductor circuit comprising : a first circuit having a bipolar current switch and a bipolar emitter-follower ; a second circuit connected to at least one of a common emitter node of said bipolar current switch and an output of the bipolar emitter-follower for control of a current through the first circuit such that the current in said first circuit is made smaller in a standby mode than the current in said first circuit in an operating mode thereof , the second circuit having two sets of MOS transistors connected in series , wherein pulse control signals having polarities different from each other are applied to gates of two MOS transistors selected from the series of MOS transistors , and wherein a common bias voltage is applied to gates of two other MOS transistors , such that a current of said second circuit changes over between two current values (precision reference voltage) determined by a ratio of gate width to gate length of the MOS transistors to which the bias voltage is applied ; and , a third circuit connected as a load to a collector of said bipolar current switch , having at least one MOS transistor arranged such that high and low output voltage levels of said first circuit are substantially constant irrespective of a variance in value of said current .
US6854067B1 CLAIM 17 . The system as recited in claim 16 , wherein said b2) is performed by a power supply scaler (load circuit) , wherein said power supply scaler comprises : a) a divider of said common supply voltage ; b) a matrix of multiplexers and registers , and c) an interconnection to said bus .	US4999519A CLAIM 7 . A semiconductor circuit comprising : a first circuit having a bipolar current switch and a bipolar emitter-follower ; a second circuit for controlling a current through the first circuit , connected to at least one of a common emitter node of said bipolar current switch and an output of the emitter-follower , said second circuit having at least one MOS transistor arranged to cause the current in said first circuit to be smaller in a standby mode than the current in said first circuit in an operating mode thereof , a first current source for a minute current which is normally caused to flow , and a second current source for a larger current which can be switched on and off ; a third circuit for use as a load circuit (mode pump power supply, power supply scaler) of said bipolar current switch connected to a collector of said bipolar current switch , said third circuit having at lease one MOS transistor arranged to render an output voltage level of said first circuit to substantially the same high and low level values irrespective of values of the current ; wherein in accordance with a control timing arrangement the current of said first circuit is caused to flow by both the first and second current sources in the operating mode and the current is caused to flow by only the second current course in the standby mode .
US6854067B1 CLAIM 19 . The method as recited in claim 18 , wherein said f4) further comprises : communicating each said optimal value to said power supply scaler (load circuit) via said bus ; registering each said optimal value with said matrix of multiplexers and registers ; commanding said matrix of multiplexers and registers to change said independent multiple of said common supply voltage to correspond with said optimal value ; and monitoring said matrix of multiplexers and registers .	US4999519A CLAIM 7 . A semiconductor circuit comprising : a first circuit having a bipolar current switch and a bipolar emitter-follower ; a second circuit for controlling a current through the first circuit , connected to at least one of a common emitter node of said bipolar current switch and an output of the emitter-follower , said second circuit having at least one MOS transistor arranged to cause the current in said first circuit to be smaller in a standby mode than the current in said first circuit in an operating mode thereof , a first current source for a minute current which is normally caused to flow , and a second current source for a larger current which can be switched on and off ; a third circuit for use as a load circuit (mode pump power supply, power supply scaler) of said bipolar current switch connected to a collector of said bipolar current switch , said third circuit having at lease one MOS transistor arranged to render an output voltage level of said first circuit to substantially the same high and low level values irrespective of values of the current ; wherein in accordance with a control timing arrangement the current of said first circuit is caused to flow by both the first and second current sources in the operating mode and the current is caused to flow by only the second current course in the standby mode .
US6854067B1 CLAIM 20 . In a microcontroller having a power on reset circuit (level value) interconnected with a processor a method of dynamically controlling said power state , said method comprising : a) ascertaining a power state powered by a switched mode pump power supply (load circuit) , said switched mode pump power supply interconnected with and responsive to control by said power on reset circuit ; b) programmatically determining desired changes to said power state ; c) intercommunicating between said processor and said power on reset circuit ; d) adjusting said power on reset circuit corresponding to said desired changes to said power state ; e) controlling said switched mode pump power supply according to said d) ; and f) repeating said a) through e) .	US4999519A CLAIM 7 . A semiconductor circuit comprising : a first circuit having a bipolar current switch and a bipolar emitter-follower ; a second circuit for controlling a current through the first circuit , connected to at least one of a common emitter node of said bipolar current switch and an output of the emitter-follower , said second circuit having at least one MOS transistor arranged to cause the current in said first circuit to be smaller in a standby mode than the current in said first circuit in an operating mode thereof , a first current source for a minute current which is normally caused to flow , and a second current source for a larger current which can be switched on and off ; a third circuit for use as a load circuit (mode pump power supply, power supply scaler) of said bipolar current switch connected to a collector of said bipolar current switch , said third circuit having at lease one MOS transistor arranged to render an output voltage level of said first circuit to substantially the same high and low level value (reset circuit) s irrespective of values of the current ; wherein in accordance with a control timing arrangement the current of said first circuit is caused to flow by both the first and second current sources in the operating mode and the current is caused to flow by only the second current course in the standby mode .

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	US4766567A Filed: 1985-04-11 Issued: 1988-08-23 One-chip data processing device including low voltage detector (Original Assignee) Denso Corp (Current Assignee) Denso Corp Mitsuharu Kato
US6854067B1 CLAIM 1 . In a microcontroller with an embedded processor , a switched mode pump power supply and power on reset circuit , a method of dynamically controlling a plurality of power stability functions (control means) for said microcontroller , said method comprising : a) supplying a power state (minimum length) to said microcontroller from said switched mode pump power supply , wherein said processor and said power on reset circuit are interconnectedly coupled , and wherein said switched mode pump power supply is interconnectedly coupled with said power on reset circuit and responsive to signals therefrom ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor ; e) controlling certain functions of said microcontroller accordingly .	US4766567A CLAIM 4 . A one-chip semiconductor device according to claim 1 , wherein said clock stopping means includes means , controlled by the clock signal , to provide a clock cycle of a minimum length (power state, power state condition, power state condition signals) required by said data processing means to execute an instruction . US4766567A CLAIM 12 . A one-chip data processing device comprising : a semiconductor substrate ; a plurality of power supply terminals mounted on said substrate and adapted to be coupled to an external power source ; a plurality of data terminals mounted on said substrate , for receiving data input from , and outputting data to , an external device ; clock generating means , formed on said substrate , for generating a clock signal which has a frequency determined by a control signal ; data processing means , formed on said substrate and connected to said clock generating means and said data terminals , and driven by the clock signal generated by said clock generating means , for processing said data input from said data terminals ; voltage detecting means , formed on said substrate and connected to the power supply terminals , for detecting a power supply voltage level ; clock frequency control means (power stability functions) , formed on said substrate and connected to said clock generating means and said voltage detecting means , for producing said control signal used for controlling said clock generating means such that a frequency of the clock signal is lowered when a decrease in said power supply voltage level is detected by said voltage detecting means ; and initializing means , formed on said substrate , for producing an initializing signal to said data processing means when the power supply voltage level detected by said voltage detecting means , falls below a range that ensures a normal state of said data processing means , to restart the operation of said data processing means from a beginning of its operation .
US6854067B1 CLAIM 5 . The method as recited in claim 4 , wherein said b) further comprises sensing a common supply voltage , wherein said common supply voltage is the voltage of said power state (minimum length) .	US4766567A CLAIM 4 . A one-chip semiconductor device according to claim 1 , wherein said clock stopping means includes means , controlled by the clock signal , to provide a clock cycle of a minimum length (power state, power state condition, power state condition signals) required by said data processing means to execute an instruction .
US6854067B1 CLAIM 6 . The method as recited in claim 5 , wherein said c) further comprises : c1) generating a precision reference voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state (minimum length) condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US4766567A CLAIM 4 . A one-chip semiconductor device according to claim 1 , wherein said clock stopping means includes means , controlled by the clock signal , to provide a clock cycle of a minimum length (power state, power state condition, power state condition signals) required by said data processing means to execute an instruction .
US6854067B1 CLAIM 11 . The method as recited in claim 10 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power (supply voltage level) state corresponding to said status ; f3) programmatically calculating an optimal value for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	US4766567A CLAIM 4 . A one-chip semiconductor device according to claim 1 , wherein said clock stopping means includes means , controlled by the clock signal , to provide a clock cycle of a minimum length (power state, power state condition, power state condition signals) required by said data processing means to execute an instruction . US4766567A CLAIM 12 . A one-chip data processing device comprising : a semiconductor substrate ; a plurality of power supply terminals mounted on said substrate and adapted to be coupled to an external power source ; a plurality of data terminals mounted on said substrate , for receiving data input from , and outputting data to , an external device ; clock generating means , formed on said substrate , for generating a clock signal which has a frequency determined by a control signal ; data processing means , formed on said substrate and connected to said clock generating means and said data terminals , and driven by the clock signal generated by said clock generating means , for processing said data input from said data terminals ; voltage detecting means , formed on said substrate and connected to the power supply terminals , for detecting a power supply voltage level (optimal power) ; clock frequency control means , formed on said substrate and connected to said clock generating means and said voltage detecting means , for producing said control signal used for controlling said clock generating means such that a frequency of the clock signal is lowered when a decrease in said power supply voltage level is detected by said voltage detecting means ; and initializing means , formed on said substrate , for producing an initializing signal to said data processing means when the power supply voltage level detected by said voltage detecting means , falls below a range that ensures a normal state of said data processing means , to restart the operation of said data processing means from a beginning of its operation .
US6854067B1 CLAIM 13 . In a microcontroller , a system comprising : a bus ; a processor coupled to said bus ; a power on reset circuit , said processor and said power on reset circuit coupled to said bus and interconnectedly coupled with said processor via said bus ; and a switched mode pump power supply interconnectedly coupled with said power on reset circuit and responsive to signals therefrom wherein said system executes a method of dynamically controlling a plurality of power stability functions (control means) for said microcontroller , said method comprising : a) supplying a power state (minimum length) to said microcontroller from said switched mode pump power supply ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor via said bus ; e) controlling certain functions of said microcontroller according to said suitability status ; and f) dynamically programming said power on reset circuit via said bus .	US4766567A CLAIM 4 . A one-chip semiconductor device according to claim 1 , wherein said clock stopping means includes means , controlled by the clock signal , to provide a clock cycle of a minimum length (power state, power state condition, power state condition signals) required by said data processing means to execute an instruction . US4766567A CLAIM 12 . A one-chip data processing device comprising : a semiconductor substrate ; a plurality of power supply terminals mounted on said substrate and adapted to be coupled to an external power source ; a plurality of data terminals mounted on said substrate , for receiving data input from , and outputting data to , an external device ; clock generating means , formed on said substrate , for generating a clock signal which has a frequency determined by a control signal ; data processing means , formed on said substrate and connected to said clock generating means and said data terminals , and driven by the clock signal generated by said clock generating means , for processing said data input from said data terminals ; voltage detecting means , formed on said substrate and connected to the power supply terminals , for detecting a power supply voltage level ; clock frequency control means (power stability functions) , formed on said substrate and connected to said clock generating means and said voltage detecting means , for producing said control signal used for controlling said clock generating means such that a frequency of the clock signal is lowered when a decrease in said power supply voltage level is detected by said voltage detecting means ; and initializing means , formed on said substrate , for producing an initializing signal to said data processing means when the power supply voltage level detected by said voltage detecting means , falls below a range that ensures a normal state of said data processing means , to restart the operation of said data processing means from a beginning of its operation .
US6854067B1 CLAIM 15 . The system as recited in claim 14 , wherein said b) of said method further comprises sensing a common supply voltage , wherein said common supply voltage is the voltage of said power state (minimum length) .	US4766567A CLAIM 4 . A one-chip semiconductor device according to claim 1 , wherein said clock stopping means includes means , controlled by the clock signal , to provide a clock cycle of a minimum length (power state, power state condition, power state condition signals) required by said data processing means to execute an instruction .
US6854067B1 CLAIM 16 . The system as recited in claim 15 , wherein said c) further comprises : c1) generating a precision reference voltage , said precision reference voltage independent of said common supply voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state (minimum length) condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US4766567A CLAIM 4 . A one-chip semiconductor device according to claim 1 , wherein said clock stopping means includes means , controlled by the clock signal , to provide a clock cycle of a minimum length (power state, power state condition, power state condition signals) required by said data processing means to execute an instruction .
US6854067B1 CLAIM 18 . The system as recited in claim 17 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power (supply voltage level) state corresponding to said status ; f3) programmatically calculating an optimal value for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	US4766567A CLAIM 4 . A one-chip semiconductor device according to claim 1 , wherein said clock stopping means includes means , controlled by the clock signal , to provide a clock cycle of a minimum length (power state, power state condition, power state condition signals) required by said data processing means to execute an instruction . US4766567A CLAIM 12 . A one-chip data processing device comprising : a semiconductor substrate ; a plurality of power supply terminals mounted on said substrate and adapted to be coupled to an external power source ; a plurality of data terminals mounted on said substrate , for receiving data input from , and outputting data to , an external device ; clock generating means , formed on said substrate , for generating a clock signal which has a frequency determined by a control signal ; data processing means , formed on said substrate and connected to said clock generating means and said data terminals , and driven by the clock signal generated by said clock generating means , for processing said data input from said data terminals ; voltage detecting means , formed on said substrate and connected to the power supply terminals , for detecting a power supply voltage level (optimal power) ; clock frequency control means , formed on said substrate and connected to said clock generating means and said voltage detecting means , for producing said control signal used for controlling said clock generating means such that a frequency of the clock signal is lowered when a decrease in said power supply voltage level is detected by said voltage detecting means ; and initializing means , formed on said substrate , for producing an initializing signal to said data processing means when the power supply voltage level detected by said voltage detecting means , falls below a range that ensures a normal state of said data processing means , to restart the operation of said data processing means from a beginning of its operation .
US6854067B1 CLAIM 20 . In a microcontroller having a power on reset circuit interconnected with a processor a method of dynamically controlling said power state (minimum length) , said method comprising : a) ascertaining a power state powered by a switched mode pump power supply , said switched mode pump power supply interconnected with and responsive to control by said power on reset circuit ; b) programmatically determining desired changes to said power state ; c) intercommunicating between said processor and said power on reset circuit ; d) adjusting said power on reset circuit corresponding to said desired changes to said power state ; e) controlling said switched mode pump power supply according to said d) ; and f) repeating said a) through e) .	US4766567A CLAIM 4 . A one-chip semiconductor device according to claim 1 , wherein said clock stopping means includes means , controlled by the clock signal , to provide a clock cycle of a minimum length (power state, power state condition, power state condition signals) required by said data processing means to execute an instruction .

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	US6107769A Filed: 1998-12-29 Issued: 2000-08-22 Positional-based motion controller with a bias latch (Original Assignee) Schneider Automation Inc (Current Assignee) Schneider Electric USA Inc ; Schneider Electric USA Inc Michael J. Saylor, Nathan H. Pillsbury
US6854067B1 CLAIM 1 . In a microcontroller with an embedded processor , a switched mode pump power supply and power on reset circuit , a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply , wherein said processor and said power on reset circuit are interconnectedly coupled , and wherein said switched mode pump power supply is interconnectedly coupled with said power on reset circuit and responsive to signals therefrom ; b) sensing a power state condition of said power state ; c) determining a suitability status (function value) of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor ; e) controlling certain functions of said microcontroller accordingly .	US6107769A CLAIM 23 . The method of claim 21 wherein said generating a transfer function value (suitability status) step comprises providing a second lookup table which generates said transfer function position value in response to said master axis position value , and changing from utilizing said first lookup table to said second lookup table .
US6854067B1 CLAIM 6 . The method as recited in claim 5 , wherein said c) further comprises : c1) generating a precision reference voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one (second lookup) of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US6107769A CLAIM 8 . The controller of claim 7 wherein said bias position value changes in response to a change from said first lookup table to said second lookup (comparisons comparing one) table .
US6854067B1 CLAIM 13 . In a microcontroller , a system comprising : a bus ; a processor coupled to said bus ; a power on reset circuit , said processor and said power on reset circuit coupled to said bus and interconnectedly coupled with said processor via said bus ; and a switched mode pump power supply interconnectedly coupled with said power on reset circuit and responsive to signals therefrom wherein said system executes a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply ; b) sensing a power state condition of said power state ; c) determining a suitability status (function value) of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor via said bus ; e) controlling certain functions of said microcontroller according to said suitability status ; and f) dynamically programming said power on reset circuit via said bus .	US6107769A CLAIM 23 . The method of claim 21 wherein said generating a transfer function value (suitability status) step comprises providing a second lookup table which generates said transfer function position value in response to said master axis position value , and changing from utilizing said first lookup table to said second lookup table .
US6854067B1 CLAIM 16 . The system as recited in claim 15 , wherein said c) further comprises : c1) generating a precision reference voltage , said precision reference voltage independent of said common supply voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one (second lookup) of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US6107769A CLAIM 8 . The controller of claim 7 wherein said bias position value changes in response to a change from said first lookup table to said second lookup (comparisons comparing one) table .

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	JP2000039937A Filed: 1998-07-22 Issued: 2000-02-08 コンピュータシステムおよびそのパワーセーブ制御方法 (Original Assignee) Toshiba Corp; 株式会社東芝 Mayumi Maeda, Koji Nakamura, 浩二中村, 真弓前田
US6854067B1 CLAIM 1 . In a microcontroller with an embedded processor , a switched mode pump power supply and power on reset circuit , a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state (ロック, の条件) to said microcontroller from said switched mode pump power supply , wherein said processor and said power on reset circuit are interconnectedly coupled , and wherein said switched mode pump power supply is interconnectedly coupled with said power on reset circuit and responsive to signals therefrom ; b) sensing a power state condition of said power state ; c) determining a suitability status (パワー) of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor ; e) controlling certain functions of said microcontroller accordingly .	JP2000039937A CLAIM 3 【請求項３】前記スリープ手段は、前記コンピュータシステムのＣＰＵを、命令実行可能な動作状態から、命令実行が停止される低消費電力のスリープ状態に移行させるＣＰＵスリープ手段を含み、前記処理速度制御手段は、前記ＣＰＵが前記スリープ状態から前記動作状態に復帰したとき、前記ＣＰＵの動作速度を低レベルから所定の高レベルにまで所定の時間間隔で段階的に上昇させるＣＰＵ速度制御手段を含み、前記ＣＰＵ速度制御手段は、所定のレジスタに設定されたデューティ制御情報に基づいて、前記ＣＰＵのクロック (power state, power state condition, power state condition signals, optimal power state) を制御するためのストップクロック信号のデューティ比を複数段階に可変設定して前記ＣＰＵに供給するＣＰＵスロットリング制御手段と、前記デューティ制御情報の更新要求を示す割り込み信号を所定の時間間隔で前記ＣＰＵに発生する手段と、前記ＣＰＵの動作速度が低レベルから所定の高レベルにまで段階的に上昇されるように、前記割り込み信号の発生の度に前記デューティ制御情報を更新する手段とを具備することを特徴とする請求項１記載のコンピュータシステム。 JP2000039937A CLAIM 4 【請求項４】前記スリープ手段は、前記コンピュータシステムのＣＰＵを、命令実行可能な動作状態から、命令実行が停止される低消費電力のスリープ状態に移行させるＣＰＵスリープ手段を含み、前記処理速度制御手段は、前記ＣＰＵが前記スリープ状態から前記動作状態に復帰したとき、前記ＣＰＵの動作速度を低レベルから所定の高レベルにまで所定の時間間隔で段階的に上昇させるＣＰＵ速度制御手段を含み、前記ＣＰＵは、第１のスリープ状態と、この第１のスリープ状態よりも低消費電力の第２のスリープ状態とを有し、前記ＣＰＵスリープ手段は、前記コンピュータシステムの状態が、前記第２のスリープ状態への移行が許可される所定の条件 (power state, power state condition, power state condition signals, optimal power state) を満足しているか否かを判別する手段と、前記条件が満足されているとき前記ＣＰＵを前記第２のスリープ状態に移行させ、前記条件が満足されないとき前記ＣＰＵを前記第１のスリープ状態に移行させる手段とを含む含むことを特徴とする請求項１記載のコンピュータシステム。 JP2000039937A CLAIM 8 【請求項８】コンピュータシステムのパワー (suitability status) セーブ制御方法であって、前記コンピュータシステムのアイドル時に、前記コンピュータシステムを動作状態からスリープ状態に移行させるステップと、所定のウェイクアップイベントの発生に応答して前記コンピュータシステムが前記スリープ状態から前記動作状態に復帰したとき、前記コンピュータシステムの処理速度を、低レベルから所定の高レベルにまで段階的に上昇させるステップとを具備することを特徴とするパワーセーブ制御方法。
US6854067B1 CLAIM 5 . The method as recited in claim 4 , wherein said b) further comprises sensing a common supply voltage , wherein said common supply voltage is the voltage of said power state (ロック, の条件) .	JP2000039937A CLAIM 3 【請求項３】前記スリープ手段は、前記コンピュータシステムのＣＰＵを、命令実行可能な動作状態から、命令実行が停止される低消費電力のスリープ状態に移行させるＣＰＵスリープ手段を含み、前記処理速度制御手段は、前記ＣＰＵが前記スリープ状態から前記動作状態に復帰したとき、前記ＣＰＵの動作速度を低レベルから所定の高レベルにまで所定の時間間隔で段階的に上昇させるＣＰＵ速度制御手段を含み、前記ＣＰＵ速度制御手段は、所定のレジスタに設定されたデューティ制御情報に基づいて、前記ＣＰＵのクロック (power state, power state condition, power state condition signals, optimal power state) を制御するためのストップクロック信号のデューティ比を複数段階に可変設定して前記ＣＰＵに供給するＣＰＵスロットリング制御手段と、前記デューティ制御情報の更新要求を示す割り込み信号を所定の時間間隔で前記ＣＰＵに発生する手段と、前記ＣＰＵの動作速度が低レベルから所定の高レベルにまで段階的に上昇されるように、前記割り込み信号の発生の度に前記デューティ制御情報を更新する手段とを具備することを特徴とする請求項１記載のコンピュータシステム。 JP2000039937A CLAIM 4 【請求項４】前記スリープ手段は、前記コンピュータシステムのＣＰＵを、命令実行可能な動作状態から、命令実行が停止される低消費電力のスリープ状態に移行させるＣＰＵスリープ手段を含み、前記処理速度制御手段は、前記ＣＰＵが前記スリープ状態から前記動作状態に復帰したとき、前記ＣＰＵの動作速度を低レベルから所定の高レベルにまで所定の時間間隔で段階的に上昇させるＣＰＵ速度制御手段を含み、前記ＣＰＵは、第１のスリープ状態と、この第１のスリープ状態よりも低消費電力の第２のスリープ状態とを有し、前記ＣＰＵスリープ手段は、前記コンピュータシステムの状態が、前記第２のスリープ状態への移行が許可される所定の条件 (power state, power state condition, power state condition signals, optimal power state) を満足しているか否かを判別する手段と、前記条件が満足されているとき前記ＣＰＵを前記第２のスリープ状態に移行させ、前記条件が満足されないとき前記ＣＰＵを前記第１のスリープ状態に移行させる手段とを含む含むことを特徴とする請求項１記載のコンピュータシステム。
US6854067B1 CLAIM 6 . The method as recited in claim 5 , wherein said c) further comprises : c1) generating a precision reference voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state (ロック, の条件) condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	JP2000039937A CLAIM 3 【請求項３】前記スリープ手段は、前記コンピュータシステムのＣＰＵを、命令実行可能な動作状態から、命令実行が停止される低消費電力のスリープ状態に移行させるＣＰＵスリープ手段を含み、前記処理速度制御手段は、前記ＣＰＵが前記スリープ状態から前記動作状態に復帰したとき、前記ＣＰＵの動作速度を低レベルから所定の高レベルにまで所定の時間間隔で段階的に上昇させるＣＰＵ速度制御手段を含み、前記ＣＰＵ速度制御手段は、所定のレジスタに設定されたデューティ制御情報に基づいて、前記ＣＰＵのクロック (power state, power state condition, power state condition signals, optimal power state) を制御するためのストップクロック信号のデューティ比を複数段階に可変設定して前記ＣＰＵに供給するＣＰＵスロットリング制御手段と、前記デューティ制御情報の更新要求を示す割り込み信号を所定の時間間隔で前記ＣＰＵに発生する手段と、前記ＣＰＵの動作速度が低レベルから所定の高レベルにまで段階的に上昇されるように、前記割り込み信号の発生の度に前記デューティ制御情報を更新する手段とを具備することを特徴とする請求項１記載のコンピュータシステム。 JP2000039937A CLAIM 4 【請求項４】前記スリープ手段は、前記コンピュータシステムのＣＰＵを、命令実行可能な動作状態から、命令実行が停止される低消費電力のスリープ状態に移行させるＣＰＵスリープ手段を含み、前記処理速度制御手段は、前記ＣＰＵが前記スリープ状態から前記動作状態に復帰したとき、前記ＣＰＵの動作速度を低レベルから所定の高レベルにまで所定の時間間隔で段階的に上昇させるＣＰＵ速度制御手段を含み、前記ＣＰＵは、第１のスリープ状態と、この第１のスリープ状態よりも低消費電力の第２のスリープ状態とを有し、前記ＣＰＵスリープ手段は、前記コンピュータシステムの状態が、前記第２のスリープ状態への移行が許可される所定の条件 (power state, power state condition, power state condition signals, optimal power state) を満足しているか否かを判別する手段と、前記条件が満足されているとき前記ＣＰＵを前記第２のスリープ状態に移行させ、前記条件が満足されないとき前記ＣＰＵを前記第１のスリープ状態に移行させる手段とを含む含むことを特徴とする請求項１記載のコンピュータシステム。
US6854067B1 CLAIM 11 . The method as recited in claim 10 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state (ロック, の条件) corresponding to said status ; f3) programmatically calculating an optimal value for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	JP2000039937A CLAIM 3 【請求項３】前記スリープ手段は、前記コンピュータシステムのＣＰＵを、命令実行可能な動作状態から、命令実行が停止される低消費電力のスリープ状態に移行させるＣＰＵスリープ手段を含み、前記処理速度制御手段は、前記ＣＰＵが前記スリープ状態から前記動作状態に復帰したとき、前記ＣＰＵの動作速度を低レベルから所定の高レベルにまで所定の時間間隔で段階的に上昇させるＣＰＵ速度制御手段を含み、前記ＣＰＵ速度制御手段は、所定のレジスタに設定されたデューティ制御情報に基づいて、前記ＣＰＵのクロック (power state, power state condition, power state condition signals, optimal power state) を制御するためのストップクロック信号のデューティ比を複数段階に可変設定して前記ＣＰＵに供給するＣＰＵスロットリング制御手段と、前記デューティ制御情報の更新要求を示す割り込み信号を所定の時間間隔で前記ＣＰＵに発生する手段と、前記ＣＰＵの動作速度が低レベルから所定の高レベルにまで段階的に上昇されるように、前記割り込み信号の発生の度に前記デューティ制御情報を更新する手段とを具備することを特徴とする請求項１記載のコンピュータシステム。 JP2000039937A CLAIM 4 【請求項４】前記スリープ手段は、前記コンピュータシステムのＣＰＵを、命令実行可能な動作状態から、命令実行が停止される低消費電力のスリープ状態に移行させるＣＰＵスリープ手段を含み、前記処理速度制御手段は、前記ＣＰＵが前記スリープ状態から前記動作状態に復帰したとき、前記ＣＰＵの動作速度を低レベルから所定の高レベルにまで所定の時間間隔で段階的に上昇させるＣＰＵ速度制御手段を含み、前記ＣＰＵは、第１のスリープ状態と、この第１のスリープ状態よりも低消費電力の第２のスリープ状態とを有し、前記ＣＰＵスリープ手段は、前記コンピュータシステムの状態が、前記第２のスリープ状態への移行が許可される所定の条件 (power state, power state condition, power state condition signals, optimal power state) を満足しているか否かを判別する手段と、前記条件が満足されているとき前記ＣＰＵを前記第２のスリープ状態に移行させ、前記条件が満足されないとき前記ＣＰＵを前記第１のスリープ状態に移行させる手段とを含む含むことを特徴とする請求項１記載のコンピュータシステム。
US6854067B1 CLAIM 13 . In a microcontroller , a system comprising : a bus ; a processor coupled to said bus ; a power on reset circuit , said processor and said power on reset circuit coupled to said bus and interconnectedly coupled with said processor via said bus ; and a switched mode pump power supply interconnectedly coupled with said power on reset circuit and responsive to signals therefrom wherein said system executes a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state (ロック, の条件) to said microcontroller from said switched mode pump power supply ; b) sensing a power state condition of said power state ; c) determining a suitability status (パワー) of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor via said bus ; e) controlling certain functions of said microcontroller according to said suitability status ; and f) dynamically programming said power on reset circuit via said bus .	JP2000039937A CLAIM 3 【請求項３】前記スリープ手段は、前記コンピュータシステムのＣＰＵを、命令実行可能な動作状態から、命令実行が停止される低消費電力のスリープ状態に移行させるＣＰＵスリープ手段を含み、前記処理速度制御手段は、前記ＣＰＵが前記スリープ状態から前記動作状態に復帰したとき、前記ＣＰＵの動作速度を低レベルから所定の高レベルにまで所定の時間間隔で段階的に上昇させるＣＰＵ速度制御手段を含み、前記ＣＰＵ速度制御手段は、所定のレジスタに設定されたデューティ制御情報に基づいて、前記ＣＰＵのクロック (power state, power state condition, power state condition signals, optimal power state) を制御するためのストップクロック信号のデューティ比を複数段階に可変設定して前記ＣＰＵに供給するＣＰＵスロットリング制御手段と、前記デューティ制御情報の更新要求を示す割り込み信号を所定の時間間隔で前記ＣＰＵに発生する手段と、前記ＣＰＵの動作速度が低レベルから所定の高レベルにまで段階的に上昇されるように、前記割り込み信号の発生の度に前記デューティ制御情報を更新する手段とを具備することを特徴とする請求項１記載のコンピュータシステム。 JP2000039937A CLAIM 4 【請求項４】前記スリープ手段は、前記コンピュータシステムのＣＰＵを、命令実行可能な動作状態から、命令実行が停止される低消費電力のスリープ状態に移行させるＣＰＵスリープ手段を含み、前記処理速度制御手段は、前記ＣＰＵが前記スリープ状態から前記動作状態に復帰したとき、前記ＣＰＵの動作速度を低レベルから所定の高レベルにまで所定の時間間隔で段階的に上昇させるＣＰＵ速度制御手段を含み、前記ＣＰＵは、第１のスリープ状態と、この第１のスリープ状態よりも低消費電力の第２のスリープ状態とを有し、前記ＣＰＵスリープ手段は、前記コンピュータシステムの状態が、前記第２のスリープ状態への移行が許可される所定の条件 (power state, power state condition, power state condition signals, optimal power state) を満足しているか否かを判別する手段と、前記条件が満足されているとき前記ＣＰＵを前記第２のスリープ状態に移行させ、前記条件が満足されないとき前記ＣＰＵを前記第１のスリープ状態に移行させる手段とを含む含むことを特徴とする請求項１記載のコンピュータシステム。 JP2000039937A CLAIM 8 【請求項８】コンピュータシステムのパワー (suitability status) セーブ制御方法であって、前記コンピュータシステムのアイドル時に、前記コンピュータシステムを動作状態からスリープ状態に移行させるステップと、所定のウェイクアップイベントの発生に応答して前記コンピュータシステムが前記スリープ状態から前記動作状態に復帰したとき、前記コンピュータシステムの処理速度を、低レベルから所定の高レベルにまで段階的に上昇させるステップとを具備することを特徴とするパワーセーブ制御方法。
US6854067B1 CLAIM 15 . The system as recited in claim 14 , wherein said b) of said method further comprises sensing a common supply voltage , wherein said common supply voltage is the voltage of said power state (ロック, の条件) .	JP2000039937A CLAIM 3 【請求項３】前記スリープ手段は、前記コンピュータシステムのＣＰＵを、命令実行可能な動作状態から、命令実行が停止される低消費電力のスリープ状態に移行させるＣＰＵスリープ手段を含み、前記処理速度制御手段は、前記ＣＰＵが前記スリープ状態から前記動作状態に復帰したとき、前記ＣＰＵの動作速度を低レベルから所定の高レベルにまで所定の時間間隔で段階的に上昇させるＣＰＵ速度制御手段を含み、前記ＣＰＵ速度制御手段は、所定のレジスタに設定されたデューティ制御情報に基づいて、前記ＣＰＵのクロック (power state, power state condition, power state condition signals, optimal power state) を制御するためのストップクロック信号のデューティ比を複数段階に可変設定して前記ＣＰＵに供給するＣＰＵスロットリング制御手段と、前記デューティ制御情報の更新要求を示す割り込み信号を所定の時間間隔で前記ＣＰＵに発生する手段と、前記ＣＰＵの動作速度が低レベルから所定の高レベルにまで段階的に上昇されるように、前記割り込み信号の発生の度に前記デューティ制御情報を更新する手段とを具備することを特徴とする請求項１記載のコンピュータシステム。 JP2000039937A CLAIM 4 【請求項４】前記スリープ手段は、前記コンピュータシステムのＣＰＵを、命令実行可能な動作状態から、命令実行が停止される低消費電力のスリープ状態に移行させるＣＰＵスリープ手段を含み、前記処理速度制御手段は、前記ＣＰＵが前記スリープ状態から前記動作状態に復帰したとき、前記ＣＰＵの動作速度を低レベルから所定の高レベルにまで所定の時間間隔で段階的に上昇させるＣＰＵ速度制御手段を含み、前記ＣＰＵは、第１のスリープ状態と、この第１のスリープ状態よりも低消費電力の第２のスリープ状態とを有し、前記ＣＰＵスリープ手段は、前記コンピュータシステムの状態が、前記第２のスリープ状態への移行が許可される所定の条件 (power state, power state condition, power state condition signals, optimal power state) を満足しているか否かを判別する手段と、前記条件が満足されているとき前記ＣＰＵを前記第２のスリープ状態に移行させ、前記条件が満足されないとき前記ＣＰＵを前記第１のスリープ状態に移行させる手段とを含む含むことを特徴とする請求項１記載のコンピュータシステム。
US6854067B1 CLAIM 16 . The system as recited in claim 15 , wherein said c) further comprises : c1) generating a precision reference voltage , said precision reference voltage independent of said common supply voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state (ロック, の条件) condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	JP2000039937A CLAIM 3 【請求項３】前記スリープ手段は、前記コンピュータシステムのＣＰＵを、命令実行可能な動作状態から、命令実行が停止される低消費電力のスリープ状態に移行させるＣＰＵスリープ手段を含み、前記処理速度制御手段は、前記ＣＰＵが前記スリープ状態から前記動作状態に復帰したとき、前記ＣＰＵの動作速度を低レベルから所定の高レベルにまで所定の時間間隔で段階的に上昇させるＣＰＵ速度制御手段を含み、前記ＣＰＵ速度制御手段は、所定のレジスタに設定されたデューティ制御情報に基づいて、前記ＣＰＵのクロック (power state, power state condition, power state condition signals, optimal power state) を制御するためのストップクロック信号のデューティ比を複数段階に可変設定して前記ＣＰＵに供給するＣＰＵスロットリング制御手段と、前記デューティ制御情報の更新要求を示す割り込み信号を所定の時間間隔で前記ＣＰＵに発生する手段と、前記ＣＰＵの動作速度が低レベルから所定の高レベルにまで段階的に上昇されるように、前記割り込み信号の発生の度に前記デューティ制御情報を更新する手段とを具備することを特徴とする請求項１記載のコンピュータシステム。 JP2000039937A CLAIM 4 【請求項４】前記スリープ手段は、前記コンピュータシステムのＣＰＵを、命令実行可能な動作状態から、命令実行が停止される低消費電力のスリープ状態に移行させるＣＰＵスリープ手段を含み、前記処理速度制御手段は、前記ＣＰＵが前記スリープ状態から前記動作状態に復帰したとき、前記ＣＰＵの動作速度を低レベルから所定の高レベルにまで所定の時間間隔で段階的に上昇させるＣＰＵ速度制御手段を含み、前記ＣＰＵは、第１のスリープ状態と、この第１のスリープ状態よりも低消費電力の第２のスリープ状態とを有し、前記ＣＰＵスリープ手段は、前記コンピュータシステムの状態が、前記第２のスリープ状態への移行が許可される所定の条件 (power state, power state condition, power state condition signals, optimal power state) を満足しているか否かを判別する手段と、前記条件が満足されているとき前記ＣＰＵを前記第２のスリープ状態に移行させ、前記条件が満足されないとき前記ＣＰＵを前記第１のスリープ状態に移行させる手段とを含む含むことを特徴とする請求項１記載のコンピュータシステム。
US6854067B1 CLAIM 18 . The system as recited in claim 17 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state (ロック, の条件) corresponding to said status ; f3) programmatically calculating an optimal value for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	JP2000039937A CLAIM 3 【請求項３】前記スリープ手段は、前記コンピュータシステムのＣＰＵを、命令実行可能な動作状態から、命令実行が停止される低消費電力のスリープ状態に移行させるＣＰＵスリープ手段を含み、前記処理速度制御手段は、前記ＣＰＵが前記スリープ状態から前記動作状態に復帰したとき、前記ＣＰＵの動作速度を低レベルから所定の高レベルにまで所定の時間間隔で段階的に上昇させるＣＰＵ速度制御手段を含み、前記ＣＰＵ速度制御手段は、所定のレジスタに設定されたデューティ制御情報に基づいて、前記ＣＰＵのクロック (power state, power state condition, power state condition signals, optimal power state) を制御するためのストップクロック信号のデューティ比を複数段階に可変設定して前記ＣＰＵに供給するＣＰＵスロットリング制御手段と、前記デューティ制御情報の更新要求を示す割り込み信号を所定の時間間隔で前記ＣＰＵに発生する手段と、前記ＣＰＵの動作速度が低レベルから所定の高レベルにまで段階的に上昇されるように、前記割り込み信号の発生の度に前記デューティ制御情報を更新する手段とを具備することを特徴とする請求項１記載のコンピュータシステム。 JP2000039937A CLAIM 4 【請求項４】前記スリープ手段は、前記コンピュータシステムのＣＰＵを、命令実行可能な動作状態から、命令実行が停止される低消費電力のスリープ状態に移行させるＣＰＵスリープ手段を含み、前記処理速度制御手段は、前記ＣＰＵが前記スリープ状態から前記動作状態に復帰したとき、前記ＣＰＵの動作速度を低レベルから所定の高レベルにまで所定の時間間隔で段階的に上昇させるＣＰＵ速度制御手段を含み、前記ＣＰＵは、第１のスリープ状態と、この第１のスリープ状態よりも低消費電力の第２のスリープ状態とを有し、前記ＣＰＵスリープ手段は、前記コンピュータシステムの状態が、前記第２のスリープ状態への移行が許可される所定の条件 (power state, power state condition, power state condition signals, optimal power state) を満足しているか否かを判別する手段と、前記条件が満足されているとき前記ＣＰＵを前記第２のスリープ状態に移行させ、前記条件が満足されないとき前記ＣＰＵを前記第１のスリープ状態に移行させる手段とを含む含むことを特徴とする請求項１記載のコンピュータシステム。
US6854067B1 CLAIM 20 . In a microcontroller having a power on reset circuit interconnected with a processor a method of dynamically controlling said power state (ロック, の条件) , said method comprising : a) ascertaining a power state powered by a switched mode pump power supply , said switched mode pump power supply interconnected with and responsive to control by said power on reset circuit ; b) programmatically determining desired changes to said power state ; c) intercommunicating between said processor and said power on reset circuit ; d) adjusting said power on reset circuit corresponding to said desired changes to said power state ; e) controlling said switched mode pump power supply according to said d) ; and f) repeating said a) through e) .	JP2000039937A CLAIM 3 【請求項３】前記スリープ手段は、前記コンピュータシステムのＣＰＵを、命令実行可能な動作状態から、命令実行が停止される低消費電力のスリープ状態に移行させるＣＰＵスリープ手段を含み、前記処理速度制御手段は、前記ＣＰＵが前記スリープ状態から前記動作状態に復帰したとき、前記ＣＰＵの動作速度を低レベルから所定の高レベルにまで所定の時間間隔で段階的に上昇させるＣＰＵ速度制御手段を含み、前記ＣＰＵ速度制御手段は、所定のレジスタに設定されたデューティ制御情報に基づいて、前記ＣＰＵのクロック (power state, power state condition, power state condition signals, optimal power state) を制御するためのストップクロック信号のデューティ比を複数段階に可変設定して前記ＣＰＵに供給するＣＰＵスロットリング制御手段と、前記デューティ制御情報の更新要求を示す割り込み信号を所定の時間間隔で前記ＣＰＵに発生する手段と、前記ＣＰＵの動作速度が低レベルから所定の高レベルにまで段階的に上昇されるように、前記割り込み信号の発生の度に前記デューティ制御情報を更新する手段とを具備することを特徴とする請求項１記載のコンピュータシステム。 JP2000039937A CLAIM 4 【請求項４】前記スリープ手段は、前記コンピュータシステムのＣＰＵを、命令実行可能な動作状態から、命令実行が停止される低消費電力のスリープ状態に移行させるＣＰＵスリープ手段を含み、前記処理速度制御手段は、前記ＣＰＵが前記スリープ状態から前記動作状態に復帰したとき、前記ＣＰＵの動作速度を低レベルから所定の高レベルにまで所定の時間間隔で段階的に上昇させるＣＰＵ速度制御手段を含み、前記ＣＰＵは、第１のスリープ状態と、この第１のスリープ状態よりも低消費電力の第２のスリープ状態とを有し、前記ＣＰＵスリープ手段は、前記コンピュータシステムの状態が、前記第２のスリープ状態への移行が許可される所定の条件 (power state, power state condition, power state condition signals, optimal power state) を満足しているか否かを判別する手段と、前記条件が満足されているとき前記ＣＰＵを前記第２のスリープ状態に移行させ、前記条件が満足されないとき前記ＣＰＵを前記第１のスリープ状態に移行させる手段とを含む含むことを特徴とする請求項１記載のコンピュータシステム。

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	JPH11237931A Filed: 1998-02-19 Issued: 1999-08-31 情報処理装置 (Original Assignee) Canon Inc; キヤノン株式会社 Toshiaki Iizuka, 利明飯塚
US6854067B1 CLAIM 1 . In a microcontroller with an embedded processor , a switched mode pump power supply and power on reset circuit , a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state (ロック, 備えること) to said microcontroller from said switched mode pump power supply , wherein said processor and said power on reset circuit are interconnectedly coupled , and wherein said switched mode pump power supply is interconnectedly coupled with said power on reset circuit and responsive to signals therefrom ; b) sensing a power state condition (ロック, 備えること) of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor ; e) controlling certain functions of said microcontroller accordingly .	JPH11237931A CLAIM 1 【請求項１】冷却対策を必要とする半導体部品と、該半導体部品を内蔵した本体と、前記半導体部品に冷却用空気を対流させるファンモータと、前記本体内の温度を検出する温度検出手段と、前記本体の周辺の音を検出する周辺音検出手段と、前記半導体部品に供給するクロックを一時停止させるクロック (power state condition, power state condition signals, optimal power, optimal power state, power state) 制御部と、前記温度検出手段による検出温度が設定値を越えたことを条件に前記周辺音検出手段による周辺音検出レベルに応じて前記ファンモータをオンにし或いは前記クロック制御部を動作させる制御手段を備えること (power state condition, power state condition signals, optimal power, optimal power state, power state) を特徴とする情報処理装置。
US6854067B1 CLAIM 5 . The method as recited in claim 4 , wherein said b) further comprises sensing a common supply voltage , wherein said common supply voltage is the voltage of said power state (ロック, 備えること) .	JPH11237931A CLAIM 1 【請求項１】冷却対策を必要とする半導体部品と、該半導体部品を内蔵した本体と、前記半導体部品に冷却用空気を対流させるファンモータと、前記本体内の温度を検出する温度検出手段と、前記本体の周辺の音を検出する周辺音検出手段と、前記半導体部品に供給するクロックを一時停止させるクロック (power state condition, power state condition signals, optimal power, optimal power state, power state) 制御部と、前記温度検出手段による検出温度が設定値を越えたことを条件に前記周辺音検出手段による周辺音検出レベルに応じて前記ファンモータをオンにし或いは前記クロック制御部を動作させる制御手段を備えること (power state condition, power state condition signals, optimal power, optimal power state, power state) を特徴とする情報処理装置。
US6854067B1 CLAIM 6 . The method as recited in claim 5 , wherein said c) further comprises : c1) generating a precision reference voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one (の比較) of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state (ロック, 備えること) condition (ロック, 備えること) signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	JPH11237931A CLAIM 1 【請求項１】冷却対策を必要とする半導体部品と、該半導体部品を内蔵した本体と、前記半導体部品に冷却用空気を対流させるファンモータと、前記本体内の温度を検出する温度検出手段と、前記本体の周辺の音を検出する周辺音検出手段と、前記半導体部品に供給するクロックを一時停止させるクロック (power state condition, power state condition signals, optimal power, optimal power state, power state) 制御部と、前記温度検出手段による検出温度が設定値を越えたことを条件に前記周辺音検出手段による周辺音検出レベルに応じて前記ファンモータをオンにし或いは前記クロック制御部を動作させる制御手段を備えること (power state condition, power state condition signals, optimal power, optimal power state, power state) を特徴とする情報処理装置。 JPH11237931A CLAIM 3 【請求項３】前記制御手段は、前記温度検出手段による検出温度の設定値との比較 (comparisons comparing one) 処理の直前に前記周辺音検出手段からの検出値を取り込むことを特徴とする請求項１又は２記載の情報処理装置。
US6854067B1 CLAIM 11 . The method as recited in claim 10 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power (ロック, 備えること) state corresponding to said status ; f3) programmatically calculating an optimal value for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	JPH11237931A CLAIM 1 【請求項１】冷却対策を必要とする半導体部品と、該半導体部品を内蔵した本体と、前記半導体部品に冷却用空気を対流させるファンモータと、前記本体内の温度を検出する温度検出手段と、前記本体の周辺の音を検出する周辺音検出手段と、前記半導体部品に供給するクロックを一時停止させるクロック (power state condition, power state condition signals, optimal power, optimal power state, power state) 制御部と、前記温度検出手段による検出温度が設定値を越えたことを条件に前記周辺音検出手段による周辺音検出レベルに応じて前記ファンモータをオンにし或いは前記クロック制御部を動作させる制御手段を備えること (power state condition, power state condition signals, optimal power, optimal power state, power state) を特徴とする情報処理装置。
US6854067B1 CLAIM 13 . In a microcontroller , a system comprising : a bus ; a processor coupled to said bus ; a power on reset circuit , said processor and said power on reset circuit coupled to said bus and interconnectedly coupled with said processor via said bus ; and a switched mode pump power supply interconnectedly coupled with said power on reset circuit and responsive to signals therefrom wherein said system executes a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state (ロック, 備えること) to said microcontroller from said switched mode pump power supply ; b) sensing a power state condition (ロック, 備えること) of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor via said bus ; e) controlling certain functions of said microcontroller according to said suitability status ; and f) dynamically programming said power on reset circuit via said bus .	JPH11237931A CLAIM 1 【請求項１】冷却対策を必要とする半導体部品と、該半導体部品を内蔵した本体と、前記半導体部品に冷却用空気を対流させるファンモータと、前記本体内の温度を検出する温度検出手段と、前記本体の周辺の音を検出する周辺音検出手段と、前記半導体部品に供給するクロックを一時停止させるクロック (power state condition, power state condition signals, optimal power, optimal power state, power state) 制御部と、前記温度検出手段による検出温度が設定値を越えたことを条件に前記周辺音検出手段による周辺音検出レベルに応じて前記ファンモータをオンにし或いは前記クロック制御部を動作させる制御手段を備えること (power state condition, power state condition signals, optimal power, optimal power state, power state) を特徴とする情報処理装置。
US6854067B1 CLAIM 15 . The system as recited in claim 14 , wherein said b) of said method further comprises sensing a common supply voltage , wherein said common supply voltage is the voltage of said power state (ロック, 備えること) .	JPH11237931A CLAIM 1 【請求項１】冷却対策を必要とする半導体部品と、該半導体部品を内蔵した本体と、前記半導体部品に冷却用空気を対流させるファンモータと、前記本体内の温度を検出する温度検出手段と、前記本体の周辺の音を検出する周辺音検出手段と、前記半導体部品に供給するクロックを一時停止させるクロック (power state condition, power state condition signals, optimal power, optimal power state, power state) 制御部と、前記温度検出手段による検出温度が設定値を越えたことを条件に前記周辺音検出手段による周辺音検出レベルに応じて前記ファンモータをオンにし或いは前記クロック制御部を動作させる制御手段を備えること (power state condition, power state condition signals, optimal power, optimal power state, power state) を特徴とする情報処理装置。
US6854067B1 CLAIM 16 . The system as recited in claim 15 , wherein said c) further comprises : c1) generating a precision reference voltage , said precision reference voltage independent of said common supply voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one (の比較) of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state (ロック, 備えること) condition (ロック, 備えること) signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	JPH11237931A CLAIM 1 【請求項１】冷却対策を必要とする半導体部品と、該半導体部品を内蔵した本体と、前記半導体部品に冷却用空気を対流させるファンモータと、前記本体内の温度を検出する温度検出手段と、前記本体の周辺の音を検出する周辺音検出手段と、前記半導体部品に供給するクロックを一時停止させるクロック (power state condition, power state condition signals, optimal power, optimal power state, power state) 制御部と、前記温度検出手段による検出温度が設定値を越えたことを条件に前記周辺音検出手段による周辺音検出レベルに応じて前記ファンモータをオンにし或いは前記クロック制御部を動作させる制御手段を備えること (power state condition, power state condition signals, optimal power, optimal power state, power state) を特徴とする情報処理装置。 JPH11237931A CLAIM 3 【請求項３】前記制御手段は、前記温度検出手段による検出温度の設定値との比較 (comparisons comparing one) 処理の直前に前記周辺音検出手段からの検出値を取り込むことを特徴とする請求項１又は２記載の情報処理装置。
US6854067B1 CLAIM 18 . The system as recited in claim 17 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power (ロック, 備えること) state corresponding to said status ; f3) programmatically calculating an optimal value for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	JPH11237931A CLAIM 1 【請求項１】冷却対策を必要とする半導体部品と、該半導体部品を内蔵した本体と、前記半導体部品に冷却用空気を対流させるファンモータと、前記本体内の温度を検出する温度検出手段と、前記本体の周辺の音を検出する周辺音検出手段と、前記半導体部品に供給するクロックを一時停止させるクロック (power state condition, power state condition signals, optimal power, optimal power state, power state) 制御部と、前記温度検出手段による検出温度が設定値を越えたことを条件に前記周辺音検出手段による周辺音検出レベルに応じて前記ファンモータをオンにし或いは前記クロック制御部を動作させる制御手段を備えること (power state condition, power state condition signals, optimal power, optimal power state, power state) を特徴とする情報処理装置。
US6854067B1 CLAIM 20 . In a microcontroller having a power on reset circuit interconnected with a processor a method of dynamically controlling said power state (ロック, 備えること) , said method comprising : a) ascertaining a power state powered by a switched mode pump power supply , said switched mode pump power supply interconnected with and responsive to control by said power on reset circuit ; b) programmatically determining desired changes to said power state ; c) intercommunicating between said processor and said power on reset circuit ; d) adjusting said power on reset circuit corresponding to said desired changes to said power state ; e) controlling said switched mode pump power supply according to said d) ; and f) repeating said a) through e) .	JPH11237931A CLAIM 1 【請求項１】冷却対策を必要とする半導体部品と、該半導体部品を内蔵した本体と、前記半導体部品に冷却用空気を対流させるファンモータと、前記本体内の温度を検出する温度検出手段と、前記本体の周辺の音を検出する周辺音検出手段と、前記半導体部品に供給するクロックを一時停止させるクロック (power state condition, power state condition signals, optimal power, optimal power state, power state) 制御部と、前記温度検出手段による検出温度が設定値を越えたことを条件に前記周辺音検出手段による周辺音検出レベルに応じて前記ファンモータをオンにし或いは前記クロック制御部を動作させる制御手段を備えること (power state condition, power state condition signals, optimal power, optimal power state, power state) を特徴とする情報処理装置。

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	WO9917186A1 Filed: 1997-09-29 Issued: 1999-04-08 Localized performance throttling to reduce ic power consumption (Original Assignee) Intel Corporation Millind Mittal, Robert Valentine
US6854067B1 CLAIM 1 . In a microcontroller with an embedded processor , a switched mode pump power supply and power on reset circuit , a method of dynamically controlling a plurality of power stability functions (control means) for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply , wherein said processor and said power on reset circuit are interconnectedly coupled , and wherein said switched mode pump power supply is interconnectedly coupled with said power on reset circuit and responsive to signals therefrom ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor ; e) controlling certain functions of said microcontroller accordingly .	WO9917186A1 CLAIM 25 . An integrated circuit with controlled power consumption , comprising : a functional means for performing a function operable in a normal mode and in a reduced-power mode ; a monitor means , coupled to said functional means , for calculating an activity level indicative of the recent utilization of said functional means ; and a control means (power stability functions) , coupled to said functional means and to said monitoring means , operable to place said functional means in said reduced-power mode when said activity level is greater than a predetermined threshold .
US6854067B1 CLAIM 6 . The method as recited in claim 5 , wherein said c) further comprises : c1) generating a precision reference voltage (current values) ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	WO9917186A1 CLAIM 36 . An integrated circuit (IC) having controlled power consumption , comprising : a plurality of functional units each operable in a normal mode and in a reduced-power mode ; a plurality of local power controllers , each associated with at least one of said functional units and each having throttling parameters , operable to control the power consumption of said associated functional unit in accordance with the current values (precision reference voltage) of said throttling parameters ; and a power coordinator , coupled to at least two of said local power controllers , operable to read a throttling parameter in a first one of said coupled local power controllers and , based thereon , operable to alter a throttling parameter in a second one of said coupled local power controllers .
US6854067B1 CLAIM 7 . The method as recited in claim 6 , wherein said precision reference voltage (current values) is independent of said common supply voltage .	WO9917186A1 CLAIM 36 . An integrated circuit (IC) having controlled power consumption , comprising : a plurality of functional units each operable in a normal mode and in a reduced-power mode ; a plurality of local power controllers , each associated with at least one of said functional units and each having throttling parameters , operable to control the power consumption of said associated functional unit in accordance with the current values (precision reference voltage) of said throttling parameters ; and a power coordinator , coupled to at least two of said local power controllers , operable to read a throttling parameter in a first one of said coupled local power controllers and , based thereon , operable to alter a throttling parameter in a second one of said coupled local power controllers .
US6854067B1 CLAIM 13 . In a microcontroller , a system comprising : a bus ; a processor coupled to said bus ; a power on reset circuit , said processor and said power on reset circuit coupled to said bus and interconnectedly coupled with said processor via said bus ; and a switched mode pump power supply interconnectedly coupled with said power on reset circuit and responsive to signals therefrom wherein said system executes a method of dynamically controlling a plurality of power stability functions (control means) for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor via said bus ; e) controlling certain functions of said microcontroller according to said suitability status ; and f) dynamically programming said power on reset circuit via said bus .	WO9917186A1 CLAIM 25 . An integrated circuit with controlled power consumption , comprising : a functional means for performing a function operable in a normal mode and in a reduced-power mode ; a monitor means , coupled to said functional means , for calculating an activity level indicative of the recent utilization of said functional means ; and a control means (power stability functions) , coupled to said functional means and to said monitoring means , operable to place said functional means in said reduced-power mode when said activity level is greater than a predetermined threshold .
US6854067B1 CLAIM 16 . The system as recited in claim 15 , wherein said c) further comprises : c1) generating a precision reference voltage (current values) , said precision reference voltage independent of said common supply voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	WO9917186A1 CLAIM 36 . An integrated circuit (IC) having controlled power consumption , comprising : a plurality of functional units each operable in a normal mode and in a reduced-power mode ; a plurality of local power controllers , each associated with at least one of said functional units and each having throttling parameters , operable to control the power consumption of said associated functional unit in accordance with the current values (precision reference voltage) of said throttling parameters ; and a power coordinator , coupled to at least two of said local power controllers , operable to read a throttling parameter in a first one of said coupled local power controllers and , based thereon , operable to alter a throttling parameter in a second one of said coupled local power controllers .

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	JPH1165719A Filed: 1997-08-21 Issued: 1999-03-09 コンピュータおよび画像表示方法 (Original Assignee) Toshiba Corp; 株式会社東芝 Yoshio Matsuoka, Nobuyuki Minamino, 伸之南野, 義雄松岡
US6854067B1 CLAIM 1 . In a microcontroller with an embedded processor , a switched mode pump power supply (電力供給) and power on reset circuit , a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state (ロック) to said microcontroller from said switched mode pump power supply , wherein said processor and said power on reset circuit are interconnectedly coupled , and wherein said switched mode pump power supply is interconnectedly coupled with said power on reset circuit and responsive to signals therefrom ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor ; e) controlling certain functions of said microcontroller accordingly .	JPH1165719A CLAIM 2 【請求項２】画像メモリを有するコンピュータ本体に対して、機能を拡張するための拡張ユニットを装着できるコンピュータにおいて、前記コンピュータ本体に前記拡張ユニットが装着されたことを検出する検出手段と、この検出手段の検出結果に基づき、前記コンピュータ本体に前記拡張ユニットが装着されたとき前記画像メモリを動作させるためのクロック (power state, power state condition, power state condition signals, optimal power state) 信号の周波数を増加させる制御を行う制御手段とを備えたことを特徴とするコンピュータ。 JPH1165719A CLAIM 3 【請求項３】第１および第２の画像メモリを有するコンピュータ本体に対して、機能を拡張するための拡張ユニットを装着できるコンピュータにおいて、前記コンピュータ本体に前記拡張ユニットが装着されたことを検出する検出手段と、この検出手段の検出結果に基づき、前記コンピュータ本体に対し前記拡張ユニットが装着されているときは前記第１および第２の画像メモリに対し共に電力供給 (mode pump power supply, power supply scaler) を行い、前記コンピュータ本体に対し前記拡張ユニットが装着されていないときは前記第１および第２の画像メモリのいずれかへの電力供給を遮断する制御を行う制御手段とを備えたことを特徴とするコンピュータ。
US6854067B1 CLAIM 5 . The method as recited in claim 4 , wherein said b) further comprises sensing a common supply voltage , wherein said common supply voltage is the voltage of said power state (ロック) .	JPH1165719A CLAIM 2 【請求項２】画像メモリを有するコンピュータ本体に対して、機能を拡張するための拡張ユニットを装着できるコンピュータにおいて、前記コンピュータ本体に前記拡張ユニットが装着されたことを検出する検出手段と、この検出手段の検出結果に基づき、前記コンピュータ本体に前記拡張ユニットが装着されたとき前記画像メモリを動作させるためのクロック (power state, power state condition, power state condition signals, optimal power state) 信号の周波数を増加させる制御を行う制御手段とを備えたことを特徴とするコンピュータ。
US6854067B1 CLAIM 6 . The method as recited in claim 5 , wherein said c) further comprises : c1) generating a precision reference voltage (画像表示方法) ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state (ロック) condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	JPH1165719A CLAIM 2 【請求項２】画像メモリを有するコンピュータ本体に対して、機能を拡張するための拡張ユニットを装着できるコンピュータにおいて、前記コンピュータ本体に前記拡張ユニットが装着されたことを検出する検出手段と、この検出手段の検出結果に基づき、前記コンピュータ本体に前記拡張ユニットが装着されたとき前記画像メモリを動作させるためのクロック (power state, power state condition, power state condition signals, optimal power state) 信号の周波数を増加させる制御を行う制御手段とを備えたことを特徴とするコンピュータ。 JPH1165719A CLAIM 5 【請求項５】画像メモリを有するコンピュータ本体に対して、機能を拡張するための拡張ユニットを装着できるコンピュータの画像表示方法 (precision reference voltage) において、前記コンピュータ本体に前記拡張ユニットが装着されたことを検出し、この検出手段の検出結果に基づき、前記コンピュータ本体に前記拡張ユニットが装着されたとき前記画像メモリの使用領域を増加させる制御を行うことを特徴とする画像表示方法。
US6854067B1 CLAIM 7 . The method as recited in claim 6 , wherein said precision reference voltage (画像表示方法) is independent of said common supply voltage .	JPH1165719A CLAIM 5 【請求項５】画像メモリを有するコンピュータ本体に対して、機能を拡張するための拡張ユニットを装着できるコンピュータの画像表示方法 (precision reference voltage) において、前記コンピュータ本体に前記拡張ユニットが装着されたことを検出し、この検出手段の検出結果に基づき、前記コンピュータ本体に前記拡張ユニットが装着されたとき前記画像メモリの使用領域を増加させる制御を行うことを特徴とする画像表示方法。
US6854067B1 CLAIM 9 . The method as recited in claim 8 , wherein said b2) is performed by a power supply scaler (電力供給) , and wherein said power supply scaler comprises : a) a divider of said common supply voltage ; b) a matrix of multiplexers and registers , and c) an interconnection to said bus .	JPH1165719A CLAIM 3 【請求項３】第１および第２の画像メモリを有するコンピュータ本体に対して、機能を拡張するための拡張ユニットを装着できるコンピュータにおいて、前記コンピュータ本体に前記拡張ユニットが装着されたことを検出する検出手段と、この検出手段の検出結果に基づき、前記コンピュータ本体に対し前記拡張ユニットが装着されているときは前記第１および第２の画像メモリに対し共に電力供給 (mode pump power supply, power supply scaler) を行い、前記コンピュータ本体に対し前記拡張ユニットが装着されていないときは前記第１および第２の画像メモリのいずれかへの電力供給を遮断する制御を行う制御手段とを備えたことを特徴とするコンピュータ。
US6854067B1 CLAIM 11 . The method as recited in claim 10 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state (ロック) corresponding to said status ; f3) programmatically calculating an optimal value for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	JPH1165719A CLAIM 2 【請求項２】画像メモリを有するコンピュータ本体に対して、機能を拡張するための拡張ユニットを装着できるコンピュータにおいて、前記コンピュータ本体に前記拡張ユニットが装着されたことを検出する検出手段と、この検出手段の検出結果に基づき、前記コンピュータ本体に前記拡張ユニットが装着されたとき前記画像メモリを動作させるためのクロック (power state, power state condition, power state condition signals, optimal power state) 信号の周波数を増加させる制御を行う制御手段とを備えたことを特徴とするコンピュータ。
US6854067B1 CLAIM 12 . The method as recited in claim 11 , wherein said f4) further comprises : communicating each said optimal value to said power supply scaler (電力供給) via said bus ; registering each said optimal value with said matrix of multiplexers and registers ; commanding said matrix of multiplexers and registers to change said independent multiple of said common supply voltage to correspond with said optimal value ; and monitoring said matrix of multiplexers and registers .	JPH1165719A CLAIM 3 【請求項３】第１および第２の画像メモリを有するコンピュータ本体に対して、機能を拡張するための拡張ユニットを装着できるコンピュータにおいて、前記コンピュータ本体に前記拡張ユニットが装着されたことを検出する検出手段と、この検出手段の検出結果に基づき、前記コンピュータ本体に対し前記拡張ユニットが装着されているときは前記第１および第２の画像メモリに対し共に電力供給 (mode pump power supply, power supply scaler) を行い、前記コンピュータ本体に対し前記拡張ユニットが装着されていないときは前記第１および第２の画像メモリのいずれかへの電力供給を遮断する制御を行う制御手段とを備えたことを特徴とするコンピュータ。
US6854067B1 CLAIM 13 . In a microcontroller , a system comprising : a bus ; a processor coupled to said bus ; a power on reset circuit , said processor and said power on reset circuit coupled to said bus and interconnectedly coupled with said processor via said bus ; and a switched mode pump power supply (電力供給) interconnectedly coupled with said power on reset circuit and responsive to signals therefrom wherein said system executes a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state (ロック) to said microcontroller from said switched mode pump power supply ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor via said bus ; e) controlling certain functions of said microcontroller according to said suitability status ; and f) dynamically programming said power on reset circuit via said bus .	JPH1165719A CLAIM 2 【請求項２】画像メモリを有するコンピュータ本体に対して、機能を拡張するための拡張ユニットを装着できるコンピュータにおいて、前記コンピュータ本体に前記拡張ユニットが装着されたことを検出する検出手段と、この検出手段の検出結果に基づき、前記コンピュータ本体に前記拡張ユニットが装着されたとき前記画像メモリを動作させるためのクロック (power state, power state condition, power state condition signals, optimal power state) 信号の周波数を増加させる制御を行う制御手段とを備えたことを特徴とするコンピュータ。 JPH1165719A CLAIM 3 【請求項３】第１および第２の画像メモリを有するコンピュータ本体に対して、機能を拡張するための拡張ユニットを装着できるコンピュータにおいて、前記コンピュータ本体に前記拡張ユニットが装着されたことを検出する検出手段と、この検出手段の検出結果に基づき、前記コンピュータ本体に対し前記拡張ユニットが装着されているときは前記第１および第２の画像メモリに対し共に電力供給 (mode pump power supply, power supply scaler) を行い、前記コンピュータ本体に対し前記拡張ユニットが装着されていないときは前記第１および第２の画像メモリのいずれかへの電力供給を遮断する制御を行う制御手段とを備えたことを特徴とするコンピュータ。
US6854067B1 CLAIM 15 . The system as recited in claim 14 , wherein said b) of said method further comprises sensing a common supply voltage , wherein said common supply voltage is the voltage of said power state (ロック) .	JPH1165719A CLAIM 2 【請求項２】画像メモリを有するコンピュータ本体に対して、機能を拡張するための拡張ユニットを装着できるコンピュータにおいて、前記コンピュータ本体に前記拡張ユニットが装着されたことを検出する検出手段と、この検出手段の検出結果に基づき、前記コンピュータ本体に前記拡張ユニットが装着されたとき前記画像メモリを動作させるためのクロック (power state, power state condition, power state condition signals, optimal power state) 信号の周波数を増加させる制御を行う制御手段とを備えたことを特徴とするコンピュータ。
US6854067B1 CLAIM 16 . The system as recited in claim 15 , wherein said c) further comprises : c1) generating a precision reference voltage (画像表示方法) , said precision reference voltage independent of said common supply voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state (ロック) condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	JPH1165719A CLAIM 2 【請求項２】画像メモリを有するコンピュータ本体に対して、機能を拡張するための拡張ユニットを装着できるコンピュータにおいて、前記コンピュータ本体に前記拡張ユニットが装着されたことを検出する検出手段と、この検出手段の検出結果に基づき、前記コンピュータ本体に前記拡張ユニットが装着されたとき前記画像メモリを動作させるためのクロック (power state, power state condition, power state condition signals, optimal power state) 信号の周波数を増加させる制御を行う制御手段とを備えたことを特徴とするコンピュータ。 JPH1165719A CLAIM 5 【請求項５】画像メモリを有するコンピュータ本体に対して、機能を拡張するための拡張ユニットを装着できるコンピュータの画像表示方法 (precision reference voltage) において、前記コンピュータ本体に前記拡張ユニットが装着されたことを検出し、この検出手段の検出結果に基づき、前記コンピュータ本体に前記拡張ユニットが装着されたとき前記画像メモリの使用領域を増加させる制御を行うことを特徴とする画像表示方法。
US6854067B1 CLAIM 17 . The system as recited in claim 16 , wherein said b2) is performed by a power supply scaler (電力供給) , wherein said power supply scaler comprises : a) a divider of said common supply voltage ; b) a matrix of multiplexers and registers , and c) an interconnection to said bus .	JPH1165719A CLAIM 3 【請求項３】第１および第２の画像メモリを有するコンピュータ本体に対して、機能を拡張するための拡張ユニットを装着できるコンピュータにおいて、前記コンピュータ本体に前記拡張ユニットが装着されたことを検出する検出手段と、この検出手段の検出結果に基づき、前記コンピュータ本体に対し前記拡張ユニットが装着されているときは前記第１および第２の画像メモリに対し共に電力供給 (mode pump power supply, power supply scaler) を行い、前記コンピュータ本体に対し前記拡張ユニットが装着されていないときは前記第１および第２の画像メモリのいずれかへの電力供給を遮断する制御を行う制御手段とを備えたことを特徴とするコンピュータ。
US6854067B1 CLAIM 18 . The system as recited in claim 17 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state (ロック) corresponding to said status ; f3) programmatically calculating an optimal value for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	JPH1165719A CLAIM 2 【請求項２】画像メモリを有するコンピュータ本体に対して、機能を拡張するための拡張ユニットを装着できるコンピュータにおいて、前記コンピュータ本体に前記拡張ユニットが装着されたことを検出する検出手段と、この検出手段の検出結果に基づき、前記コンピュータ本体に前記拡張ユニットが装着されたとき前記画像メモリを動作させるためのクロック (power state, power state condition, power state condition signals, optimal power state) 信号の周波数を増加させる制御を行う制御手段とを備えたことを特徴とするコンピュータ。
US6854067B1 CLAIM 19 . The method as recited in claim 18 , wherein said f4) further comprises : communicating each said optimal value to said power supply scaler (電力供給) via said bus ; registering each said optimal value with said matrix of multiplexers and registers ; commanding said matrix of multiplexers and registers to change said independent multiple of said common supply voltage to correspond with said optimal value ; and monitoring said matrix of multiplexers and registers .	JPH1165719A CLAIM 3 【請求項３】第１および第２の画像メモリを有するコンピュータ本体に対して、機能を拡張するための拡張ユニットを装着できるコンピュータにおいて、前記コンピュータ本体に前記拡張ユニットが装着されたことを検出する検出手段と、この検出手段の検出結果に基づき、前記コンピュータ本体に対し前記拡張ユニットが装着されているときは前記第１および第２の画像メモリに対し共に電力供給 (mode pump power supply, power supply scaler) を行い、前記コンピュータ本体に対し前記拡張ユニットが装着されていないときは前記第１および第２の画像メモリのいずれかへの電力供給を遮断する制御を行う制御手段とを備えたことを特徴とするコンピュータ。
US6854067B1 CLAIM 20 . In a microcontroller having a power on reset circuit interconnected with a processor a method of dynamically controlling said power state (ロック) , said method comprising : a) ascertaining a power state powered by a switched mode pump power supply (電力供給) , said switched mode pump power supply interconnected with and responsive to control by said power on reset circuit ; b) programmatically determining desired changes to said power state ; c) intercommunicating between said processor and said power on reset circuit ; d) adjusting said power on reset circuit corresponding to said desired changes to said power state ; e) controlling said switched mode pump power supply according to said d) ; and f) repeating said a) through e) .	JPH1165719A CLAIM 2 【請求項２】画像メモリを有するコンピュータ本体に対して、機能を拡張するための拡張ユニットを装着できるコンピュータにおいて、前記コンピュータ本体に前記拡張ユニットが装着されたことを検出する検出手段と、この検出手段の検出結果に基づき、前記コンピュータ本体に前記拡張ユニットが装着されたとき前記画像メモリを動作させるためのクロック (power state, power state condition, power state condition signals, optimal power state) 信号の周波数を増加させる制御を行う制御手段とを備えたことを特徴とするコンピュータ。 JPH1165719A CLAIM 3 【請求項３】第１および第２の画像メモリを有するコンピュータ本体に対して、機能を拡張するための拡張ユニットを装着できるコンピュータにおいて、前記コンピュータ本体に前記拡張ユニットが装着されたことを検出する検出手段と、この検出手段の検出結果に基づき、前記コンピュータ本体に対し前記拡張ユニットが装着されているときは前記第１および第２の画像メモリに対し共に電力供給 (mode pump power supply, power supply scaler) を行い、前記コンピュータ本体に対し前記拡張ユニットが装着されていないときは前記第１および第２の画像メモリのいずれかへの電力供給を遮断する制御を行う制御手段とを備えたことを特徴とするコンピュータ。

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	JPH1115542A Filed: 1997-06-24 Issued: 1999-01-22 電子制御装置 (Original Assignee) Denso Corp; 株式会社デンソー Takuya Harada, Masumi Horie, Hiroyuki Ina, 博之伊奈, 卓哉原田, 真清堀江
US6854067B1 CLAIM 1 . In a microcontroller with an embedded processor , a switched mode pump power supply (ライン) and power on reset circuit , a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply , wherein said processor and said power on reset circuit are interconnectedly coupled , and wherein said switched mode pump power supply is interconnectedly coupled with said power on reset circuit and responsive to signals therefrom ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor ; e) controlling certain functions of said microcontroller accordingly .	JPH1115542A CLAIM 1 【請求項１】各種電子部品を接地するために設けられた第１及び第２のアースライン (mode pump power supply) と、上記第１のアースラインの電位を基準電位とした電圧信号を生成する信号生成手段と、該信号生成手段にて生成された電圧信号を、上記第２のアースラインの電位を基準電位として処理する信号処理手段と、を備えた電子制御装置において、上記信号処理手段に、上記信号生成手段にて生成された電圧信号の電圧レベルを、上記第２のアースラインの電位変動量以上のシフト電圧分だけレベルシフトさせるレベルシフト回路を設けたことを特徴とする電子制御装置。
US6854067B1 CLAIM 6 . The method as recited in claim 5 , wherein said c) further comprises : c1) generating a precision reference voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals (なること) , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	JPH1115542A CLAIM 3 【請求項３】請求項１または請求項２に記載の電子制御装置において、上記レベルシフト回路は、ゲートを当該レベルシフト回路の入力とし、ソースを当該レベルシフト回路の出力とし、ドレインを上記第２のアースラインを介して接地した電界効果トランジスタと、該電界効果トランジスタのソース，ゲート間の電位差が上記シフト電圧となるような一定電流を、該電界効果トランジスタのソース，ドレイン間に流す定電流回路と、からなること (power state condition signals) を特徴とする電子制御装置。
US6854067B1 CLAIM 13 . In a microcontroller , a system comprising : a bus ; a processor coupled to said bus ; a power on reset circuit , said processor and said power on reset circuit coupled to said bus and interconnectedly coupled with said processor via said bus ; and a switched mode pump power supply (ライン) interconnectedly coupled with said power on reset circuit and responsive to signals therefrom wherein said system executes a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor via said bus ; e) controlling certain functions of said microcontroller according to said suitability status ; and f) dynamically programming said power on reset circuit via said bus .	JPH1115542A CLAIM 1 【請求項１】各種電子部品を接地するために設けられた第１及び第２のアースライン (mode pump power supply) と、上記第１のアースラインの電位を基準電位とした電圧信号を生成する信号生成手段と、該信号生成手段にて生成された電圧信号を、上記第２のアースラインの電位を基準電位として処理する信号処理手段と、を備えた電子制御装置において、上記信号処理手段に、上記信号生成手段にて生成された電圧信号の電圧レベルを、上記第２のアースラインの電位変動量以上のシフト電圧分だけレベルシフトさせるレベルシフト回路を設けたことを特徴とする電子制御装置。
US6854067B1 CLAIM 16 . The system as recited in claim 15 , wherein said c) further comprises : c1) generating a precision reference voltage , said precision reference voltage independent of said common supply voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals (なること) , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	JPH1115542A CLAIM 3 【請求項３】請求項１または請求項２に記載の電子制御装置において、上記レベルシフト回路は、ゲートを当該レベルシフト回路の入力とし、ソースを当該レベルシフト回路の出力とし、ドレインを上記第２のアースラインを介して接地した電界効果トランジスタと、該電界効果トランジスタのソース，ゲート間の電位差が上記シフト電圧となるような一定電流を、該電界効果トランジスタのソース，ドレイン間に流す定電流回路と、からなること (power state condition signals) を特徴とする電子制御装置。
US6854067B1 CLAIM 20 . In a microcontroller having a power on reset circuit interconnected with a processor a method of dynamically controlling said power state , said method comprising : a) ascertaining a power state powered by a switched mode pump power supply (ライン) , said switched mode pump power supply interconnected with and responsive to control by said power on reset circuit ; b) programmatically determining desired changes to said power state ; c) intercommunicating between said processor and said power on reset circuit ; d) adjusting said power on reset circuit corresponding to said desired changes to said power state ; e) controlling said switched mode pump power supply according to said d) ; and f) repeating said a) through e) .	JPH1115542A CLAIM 1 【請求項１】各種電子部品を接地するために設けられた第１及び第２のアースライン (mode pump power supply) と、上記第１のアースラインの電位を基準電位とした電圧信号を生成する信号生成手段と、該信号生成手段にて生成された電圧信号を、上記第２のアースラインの電位を基準電位として処理する信号処理手段と、を備えた電子制御装置において、上記信号処理手段に、上記信号生成手段にて生成された電圧信号の電圧レベルを、上記第２のアースラインの電位変動量以上のシフト電圧分だけレベルシフトさせるレベルシフト回路を設けたことを特徴とする電子制御装置。

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	JPH10341158A Filed: 1997-06-10 Issued: 1998-12-22 Ａ／ｄ変換装置 (Original Assignee) Mitsubishi Electric Corp; 三菱電機株式会社 Masaru Hoshikawa, Shigeaki Takase, 星川　　賢, 茂明高瀬
US6854067B1 CLAIM 1 . In a microcontroller with an embedded processor , a switched mode pump power supply and power on reset circuit , a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply , wherein said processor and said power on reset circuit are interconnectedly coupled , and wherein said switched mode pump power supply is interconnectedly coupled with said power on reset circuit and responsive to signals therefrom ; b) sensing a power state condition of said power state ; c) determining a suitability status (前記Ａ) of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor ; e) controlling certain functions of said microcontroller accordingly .	JPH10341158A CLAIM 1 【請求項１】差動入力を短絡してオフセット用基準電圧を発生するオフセット用基準電圧部と、アナログ入力と前記オフセット用基準電圧の入力とを切り換えるアナログマルチプレクサと、前記アナログマルチプレクサから入力されるアナログ入力信号を適宜処理するアナログ入力回路部と、前記アナログ入力回路部から出力されるアナログ信号をデジタル信号に変換するＡ／Ｄ変換部と、前記アナログマルチプレクサの入力切り換え制御を行ってアナログ入力とオフセット用基準電圧とを周期的に取り込む制御切換部と、前記制御切換部によって周期的に取り込まれるアナログ入力とオフセット用基準電圧とを前記Ａ (suitability status) ／Ｄ変換部で変換したＡ／Ｄ変換値を一定周期ごとに更新してオフセット値を補正する補正部と、を備えていることを特徴とするＡ／Ｄ変換装置。
US6854067B1 CLAIM 6 . The method as recited in claim 5 , wherein said c) further comprises : c1) generating a precision reference voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one (の比較) of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	JPH10341158A CLAIM 5 【請求項５】前記ゲイン用基準電圧のＡ／Ｄ変換値と前記アナログ入力のＡ／Ｄ変換値との比較 (comparisons comparing one) 結果に基づいて装置の故障検出を行う故障検出部を、さらに備えたことを特徴とする請求項３又は４に記載のＡ／Ｄ変換装置。
US6854067B1 CLAIM 13 . In a microcontroller , a system comprising : a bus ; a processor coupled to said bus ; a power on reset circuit , said processor and said power on reset circuit coupled to said bus and interconnectedly coupled with said processor via said bus ; and a switched mode pump power supply interconnectedly coupled with said power on reset circuit and responsive to signals therefrom wherein said system executes a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply ; b) sensing a power state condition of said power state ; c) determining a suitability status (前記Ａ) of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor via said bus ; e) controlling certain functions of said microcontroller according to said suitability status ; and f) dynamically programming said power on reset circuit via said bus .	JPH10341158A CLAIM 1 【請求項１】差動入力を短絡してオフセット用基準電圧を発生するオフセット用基準電圧部と、アナログ入力と前記オフセット用基準電圧の入力とを切り換えるアナログマルチプレクサと、前記アナログマルチプレクサから入力されるアナログ入力信号を適宜処理するアナログ入力回路部と、前記アナログ入力回路部から出力されるアナログ信号をデジタル信号に変換するＡ／Ｄ変換部と、前記アナログマルチプレクサの入力切り換え制御を行ってアナログ入力とオフセット用基準電圧とを周期的に取り込む制御切換部と、前記制御切換部によって周期的に取り込まれるアナログ入力とオフセット用基準電圧とを前記Ａ (suitability status) ／Ｄ変換部で変換したＡ／Ｄ変換値を一定周期ごとに更新してオフセット値を補正する補正部と、を備えていることを特徴とするＡ／Ｄ変換装置。
US6854067B1 CLAIM 16 . The system as recited in claim 15 , wherein said c) further comprises : c1) generating a precision reference voltage , said precision reference voltage independent of said common supply voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one (の比較) of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	JPH10341158A CLAIM 5 【請求項５】前記ゲイン用基準電圧のＡ／Ｄ変換値と前記アナログ入力のＡ／Ｄ変換値との比較 (comparisons comparing one) 結果に基づいて装置の故障検出を行う故障検出部を、さらに備えたことを特徴とする請求項３又は４に記載のＡ／Ｄ変換装置。

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	JPH10337023A Filed: 1997-05-29 Issued: 1998-12-18 スイッチング電源装置 (Original Assignee) Nemic Lambda Kk; ネミック・ラムダ株式会社 Masaaki Isa, 正明井佐
US6854067B1 CLAIM 1 . In a microcontroller with an embedded processor , a switched mode pump power supply (ダイオ, ライン) and power on reset circuit , a method of dynamically controlling a plurality of power stability functions (電源装置) for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply , wherein said processor and said power on reset circuit are interconnectedly coupled , and wherein said switched mode pump power supply is interconnectedly coupled with said power on reset circuit and responsive to signals therefrom ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor ; e) controlling certain functions of said microcontroller accordingly .	JPH10337023A CLAIM 1 【請求項１】第１の制御手段により第１のスイッチング素子を通断電制御することにより、入力電流波形を正弦波状にして、平滑コンデンサの両端間に直流入力電圧を発生させる力率改善回路と、第２の制御手段により第２のスイッチング素子を通断電制御することで、前記直流入力電圧を絶縁トランスの一次巻線に断続的に印加して、安定した直流出力電圧を出力するＤＣ／ＤＣコンバータと、前記第１の制御手段の停止に同期して前記第２の制御手段を停止させる同期回路と、前記第２の制御手段が動作中のときには、前記平滑コンデンサから前記第１の制御手段に動作を継続させる動作電圧を供給する動作継続回路とから構成されることを特徴とするスイッチング電源装置 (power stability functions) 。 JPH10337023A CLAIM 2 【請求項２】前記力率改善回路の入力電圧レベルに応じた電圧検出信号をスイッチ素子の制御端子に供給し、起動時にこの入力電圧レベルが所定値以上になったら、前記スイッチ素子をオンして前記平滑コンデンサから前記第１の制御手段に動作電圧を供給する起動用回路をさらに備え、前記動作継続回路は、前記スイッチ素子と、このスイッチ素子の制御端子と前記第２の制御手段の動作電圧ライン (mode pump power supply) との間に接続されるダイオ (mode pump power supply) ードと抵抗との直列回路とにより構成されることを特徴とする請求項１記載のスイッチング電源装置。
US6854067B1 CLAIM 13 . In a microcontroller , a system comprising : a bus ; a processor coupled to said bus ; a power on reset circuit , said processor and said power on reset circuit coupled to said bus and interconnectedly coupled with said processor via said bus ; and a switched mode pump power supply (ダイオ, ライン) interconnectedly coupled with said power on reset circuit and responsive to signals therefrom wherein said system executes a method of dynamically controlling a plurality of power stability functions (電源装置) for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor via said bus ; e) controlling certain functions of said microcontroller according to said suitability status ; and f) dynamically programming said power on reset circuit via said bus .	JPH10337023A CLAIM 1 【請求項１】第１の制御手段により第１のスイッチング素子を通断電制御することにより、入力電流波形を正弦波状にして、平滑コンデンサの両端間に直流入力電圧を発生させる力率改善回路と、第２の制御手段により第２のスイッチング素子を通断電制御することで、前記直流入力電圧を絶縁トランスの一次巻線に断続的に印加して、安定した直流出力電圧を出力するＤＣ／ＤＣコンバータと、前記第１の制御手段の停止に同期して前記第２の制御手段を停止させる同期回路と、前記第２の制御手段が動作中のときには、前記平滑コンデンサから前記第１の制御手段に動作を継続させる動作電圧を供給する動作継続回路とから構成されることを特徴とするスイッチング電源装置 (power stability functions) 。 JPH10337023A CLAIM 2 【請求項２】前記力率改善回路の入力電圧レベルに応じた電圧検出信号をスイッチ素子の制御端子に供給し、起動時にこの入力電圧レベルが所定値以上になったら、前記スイッチ素子をオンして前記平滑コンデンサから前記第１の制御手段に動作電圧を供給する起動用回路をさらに備え、前記動作継続回路は、前記スイッチ素子と、このスイッチ素子の制御端子と前記第２の制御手段の動作電圧ライン (mode pump power supply) との間に接続されるダイオ (mode pump power supply) ードと抵抗との直列回路とにより構成されることを特徴とする請求項１記載のスイッチング電源装置。
US6854067B1 CLAIM 20 . In a microcontroller having a power on reset circuit interconnected with a processor a method of dynamically controlling said power state , said method comprising : a) ascertaining a power state powered by a switched mode pump power supply (ダイオ, ライン) , said switched mode pump power supply interconnected with and responsive to control by said power on reset circuit ; b) programmatically determining desired changes to said power state ; c) intercommunicating between said processor and said power on reset circuit ; d) adjusting said power on reset circuit corresponding to said desired changes to said power state ; e) controlling said switched mode pump power supply according to said d) ; and f) repeating said a) through e) .	JPH10337023A CLAIM 2 【請求項２】前記力率改善回路の入力電圧レベルに応じた電圧検出信号をスイッチ素子の制御端子に供給し、起動時にこの入力電圧レベルが所定値以上になったら、前記スイッチ素子をオンして前記平滑コンデンサから前記第１の制御手段に動作電圧を供給する起動用回路をさらに備え、前記動作継続回路は、前記スイッチ素子と、このスイッチ素子の制御端子と前記第２の制御手段の動作電圧ライン (mode pump power supply) との間に接続されるダイオ (mode pump power supply) ードと抵抗との直列回路とにより構成されることを特徴とする請求項１記載のスイッチング電源装置。

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	JPH10222256A Filed: 1997-02-12 Issued: 1998-08-21 電力制御装置および電力制御方法 (Original Assignee) Mitsubishi Electric Corp; 三菱電機株式会社 Hidenobu Fukushima, Hiroaki Ishikawa, Yoshinori Mizutani, Masahito Sato, 雅人佐藤, 良則水谷, 博章石川, 秀信福島
US6854067B1 CLAIM 1 . In a microcontroller with an embedded processor , a switched mode pump power supply (電力供給) and power on reset circuit , a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state (ロック) to said microcontroller from said switched mode pump power supply , wherein said processor and said power on reset circuit are interconnectedly coupled , and wherein said switched mode pump power supply is interconnectedly coupled with said power on reset circuit and responsive to signals therefrom ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor ; e) controlling certain functions of said microcontroller accordingly .	JPH10222256A CLAIM 4 【請求項４】前記処理回路は、前記バッテリから電力供給を受けてクロック (power state, power state condition, power state condition signals, optimal power state) 信号を出力するクロック発生手段であり、前記調整手段は、前記判定手段による判定結果に基づき、前記クロック発生手段から発生されるクロック信号の周波数を調整することを特徴とする請求項１乃至請求項３のいずれかに記載の電力制御装置。 JPH10222256A CLAIM 6 【請求項６】前記処理回路は、前記バッテリから電力供給を受けて動作するＬＳＩであり、前記調整手段は、前記判定手段による判定結果に基づき、前記ＬＳＩへの電力供給 (mode pump power supply, power supply scaler) を遮断することを特徴とする請求項１乃至請求項３のいずれかに記載の電力制御装置。
US6854067B1 CLAIM 5 . The method as recited in claim 4 , wherein said b) further comprises sensing a common supply voltage , wherein said common supply voltage is the voltage of said power state (ロック) .	JPH10222256A CLAIM 4 【請求項４】前記処理回路は、前記バッテリから電力供給を受けてクロック (power state, power state condition, power state condition signals, optimal power state) 信号を出力するクロック発生手段であり、前記調整手段は、前記判定手段による判定結果に基づき、前記クロック発生手段から発生されるクロック信号の周波数を調整することを特徴とする請求項１乃至請求項３のいずれかに記載の電力制御装置。
US6854067B1 CLAIM 6 . The method as recited in claim 5 , wherein said c) further comprises : c1) generating a precision reference voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state (ロック) condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	JPH10222256A CLAIM 4 【請求項４】前記処理回路は、前記バッテリから電力供給を受けてクロック (power state, power state condition, power state condition signals, optimal power state) 信号を出力するクロック発生手段であり、前記調整手段は、前記判定手段による判定結果に基づき、前記クロック発生手段から発生されるクロック信号の周波数を調整することを特徴とする請求項１乃至請求項３のいずれかに記載の電力制御装置。
US6854067B1 CLAIM 9 . The method as recited in claim 8 , wherein said b2) is performed by a power supply scaler (電力供給) , and wherein said power supply scaler comprises : a) a divider of said common supply voltage ; b) a matrix of multiplexers and registers , and c) an interconnection to said bus .	JPH10222256A CLAIM 6 【請求項６】前記処理回路は、前記バッテリから電力供給を受けて動作するＬＳＩであり、前記調整手段は、前記判定手段による判定結果に基づき、前記ＬＳＩへの電力供給 (mode pump power supply, power supply scaler) を遮断することを特徴とする請求項１乃至請求項３のいずれかに記載の電力制御装置。
US6854067B1 CLAIM 11 . The method as recited in claim 10 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state (ロック) corresponding to said status ; f3) programmatically calculating an optimal value for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	JPH10222256A CLAIM 4 【請求項４】前記処理回路は、前記バッテリから電力供給を受けてクロック (power state, power state condition, power state condition signals, optimal power state) 信号を出力するクロック発生手段であり、前記調整手段は、前記判定手段による判定結果に基づき、前記クロック発生手段から発生されるクロック信号の周波数を調整することを特徴とする請求項１乃至請求項３のいずれかに記載の電力制御装置。
US6854067B1 CLAIM 12 . The method as recited in claim 11 , wherein said f4) further comprises : communicating each said optimal value to said power supply scaler (電力供給) via said bus ; registering each said optimal value with said matrix of multiplexers and registers ; commanding said matrix of multiplexers and registers to change said independent multiple of said common supply voltage to correspond with said optimal value ; and monitoring said matrix of multiplexers and registers .	JPH10222256A CLAIM 6 【請求項６】前記処理回路は、前記バッテリから電力供給を受けて動作するＬＳＩであり、前記調整手段は、前記判定手段による判定結果に基づき、前記ＬＳＩへの電力供給 (mode pump power supply, power supply scaler) を遮断することを特徴とする請求項１乃至請求項３のいずれかに記載の電力制御装置。
US6854067B1 CLAIM 13 . In a microcontroller , a system comprising : a bus ; a processor coupled to said bus ; a power on reset circuit , said processor and said power on reset circuit coupled to said bus and interconnectedly coupled with said processor via said bus ; and a switched mode pump power supply (電力供給) interconnectedly coupled with said power on reset circuit and responsive to signals therefrom wherein said system executes a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state (ロック) to said microcontroller from said switched mode pump power supply ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor via said bus ; e) controlling certain functions of said microcontroller according to said suitability status ; and f) dynamically programming said power on reset circuit via said bus .	JPH10222256A CLAIM 4 【請求項４】前記処理回路は、前記バッテリから電力供給を受けてクロック (power state, power state condition, power state condition signals, optimal power state) 信号を出力するクロック発生手段であり、前記調整手段は、前記判定手段による判定結果に基づき、前記クロック発生手段から発生されるクロック信号の周波数を調整することを特徴とする請求項１乃至請求項３のいずれかに記載の電力制御装置。 JPH10222256A CLAIM 6 【請求項６】前記処理回路は、前記バッテリから電力供給を受けて動作するＬＳＩであり、前記調整手段は、前記判定手段による判定結果に基づき、前記ＬＳＩへの電力供給 (mode pump power supply, power supply scaler) を遮断することを特徴とする請求項１乃至請求項３のいずれかに記載の電力制御装置。
US6854067B1 CLAIM 15 . The system as recited in claim 14 , wherein said b) of said method further comprises sensing a common supply voltage , wherein said common supply voltage is the voltage of said power state (ロック) .	JPH10222256A CLAIM 4 【請求項４】前記処理回路は、前記バッテリから電力供給を受けてクロック (power state, power state condition, power state condition signals, optimal power state) 信号を出力するクロック発生手段であり、前記調整手段は、前記判定手段による判定結果に基づき、前記クロック発生手段から発生されるクロック信号の周波数を調整することを特徴とする請求項１乃至請求項３のいずれかに記載の電力制御装置。
US6854067B1 CLAIM 16 . The system as recited in claim 15 , wherein said c) further comprises : c1) generating a precision reference voltage , said precision reference voltage independent of said common supply voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state (ロック) condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	JPH10222256A CLAIM 4 【請求項４】前記処理回路は、前記バッテリから電力供給を受けてクロック (power state, power state condition, power state condition signals, optimal power state) 信号を出力するクロック発生手段であり、前記調整手段は、前記判定手段による判定結果に基づき、前記クロック発生手段から発生されるクロック信号の周波数を調整することを特徴とする請求項１乃至請求項３のいずれかに記載の電力制御装置。
US6854067B1 CLAIM 17 . The system as recited in claim 16 , wherein said b2) is performed by a power supply scaler (電力供給) , wherein said power supply scaler comprises : a) a divider of said common supply voltage ; b) a matrix of multiplexers and registers , and c) an interconnection to said bus .	JPH10222256A CLAIM 6 【請求項６】前記処理回路は、前記バッテリから電力供給を受けて動作するＬＳＩであり、前記調整手段は、前記判定手段による判定結果に基づき、前記ＬＳＩへの電力供給 (mode pump power supply, power supply scaler) を遮断することを特徴とする請求項１乃至請求項３のいずれかに記載の電力制御装置。
US6854067B1 CLAIM 18 . The system as recited in claim 17 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state (ロック) corresponding to said status ; f3) programmatically calculating an optimal value for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	JPH10222256A CLAIM 4 【請求項４】前記処理回路は、前記バッテリから電力供給を受けてクロック (power state, power state condition, power state condition signals, optimal power state) 信号を出力するクロック発生手段であり、前記調整手段は、前記判定手段による判定結果に基づき、前記クロック発生手段から発生されるクロック信号の周波数を調整することを特徴とする請求項１乃至請求項３のいずれかに記載の電力制御装置。
US6854067B1 CLAIM 19 . The method as recited in claim 18 , wherein said f4) further comprises : communicating each said optimal value to said power supply scaler (電力供給) via said bus ; registering each said optimal value with said matrix of multiplexers and registers ; commanding said matrix of multiplexers and registers to change said independent multiple of said common supply voltage to correspond with said optimal value ; and monitoring said matrix of multiplexers and registers .	JPH10222256A CLAIM 6 【請求項６】前記処理回路は、前記バッテリから電力供給を受けて動作するＬＳＩであり、前記調整手段は、前記判定手段による判定結果に基づき、前記ＬＳＩへの電力供給 (mode pump power supply, power supply scaler) を遮断することを特徴とする請求項１乃至請求項３のいずれかに記載の電力制御装置。
US6854067B1 CLAIM 20 . In a microcontroller having a power on reset circuit interconnected with a processor a method of dynamically controlling said power state (ロック) , said method comprising : a) ascertaining a power state powered by a switched mode pump power supply (電力供給) , said switched mode pump power supply interconnected with and responsive to control by said power on reset circuit ; b) programmatically determining desired changes to said power state ; c) intercommunicating between said processor and said power on reset circuit ; d) adjusting said power on reset circuit corresponding to said desired changes to said power state ; e) controlling said switched mode pump power supply according to said d) ; and f) repeating said a) through e) .	JPH10222256A CLAIM 4 【請求項４】前記処理回路は、前記バッテリから電力供給を受けてクロック (power state, power state condition, power state condition signals, optimal power state) 信号を出力するクロック発生手段であり、前記調整手段は、前記判定手段による判定結果に基づき、前記クロック発生手段から発生されるクロック信号の周波数を調整することを特徴とする請求項１乃至請求項３のいずれかに記載の電力制御装置。 JPH10222256A CLAIM 6 【請求項６】前記処理回路は、前記バッテリから電力供給を受けて動作するＬＳＩであり、前記調整手段は、前記判定手段による判定結果に基づき、前記ＬＳＩへの電力供給 (mode pump power supply, power supply scaler) を遮断することを特徴とする請求項１乃至請求項３のいずれかに記載の電力制御装置。

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	US6018559A Filed: 1996-12-16 Issued: 2000-01-25 Chain-connected shift register and programmable logic circuit whose logic function is changeable in real time (Original Assignee) Fujitsu Ltd (Current Assignee) Fujitsu Ltd Kengo Azegami, Koichi Yamashita
US6854067B1 CLAIM 1 . In a microcontroller with an embedded processor , a switched mode pump power supply and power on reset circuit (one input terminal) , a method of dynamically controlling a plurality of power stability functions (NAND gate) for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply , wherein said processor and said power on reset circuit are interconnectedly coupled , and wherein said switched mode pump power supply is interconnectedly coupled with said power on reset circuit and responsive to signals therefrom ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor ; e) controlling certain functions of said microcontroller accordingly .	US6018559A CLAIM 3 . The shift register as claimed in claim 1 , wherein said first inversion gate has a first NAND gate (power stability functions) , and said second inversion gate has a second NAND gate . US6018559A CLAIM 8 . The shift register as claimed in claim 3 , further comprising a state setting circuit , connected to one input terminal (reset circuit) of said first NAND gate and one input terminal of said second NAND gate , for setting a state in said circuit cell .
US6854067B1 CLAIM 2 . The method as recited in claim 1 , further comprising : f) dynamically programming said power on reset circuit (one input terminal) .	US6018559A CLAIM 8 . The shift register as claimed in claim 3 , further comprising a state setting circuit , connected to one input terminal (reset circuit) of said first NAND gate and one input terminal of said second NAND gate , for setting a state in said circuit cell .
US6854067B1 CLAIM 3 . The method as recited in claim 2 , wherein said power on reset circuit (one input terminal) and said processor are interconnected via a bus .	US6018559A CLAIM 8 . The shift register as claimed in claim 3 , further comprising a state setting circuit , connected to one input terminal (reset circuit) of said first NAND gate and one input terminal of said second NAND gate , for setting a state in said circuit cell .
US6854067B1 CLAIM 4 . The method as recited in claim 3 , wherein said b) and said c) are accomplished by said power on reset circuit (one input terminal) .	US6018559A CLAIM 8 . The shift register as claimed in claim 3 , further comprising a state setting circuit , connected to one input terminal (reset circuit) of said first NAND gate and one input terminal of said second NAND gate , for setting a state in said circuit cell .
US6854067B1 CLAIM 6 . The method as recited in claim 5 , wherein said c) further comprises : c1) generating a precision reference voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages (producing one) , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US6018559A CLAIM 10 . The shift register as claimed in claim 1 , wherein each of said circuit cells further comprises a data output terminal , and said shift register further comprises a decoder circuit , connected to said data output terminals of said circuit cells , producing one (aspect voltages) data set from said data output terminals according to a control input signal .
US6854067B1 CLAIM 11 . The method as recited in claim 10 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state (d log) corresponding to said status ; f3) programmatically calculating an optimal value for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	US6018559A CLAIM 12 . A programmable logic circuit having a configuration memory being provided with configuration data , and at least one logic cell operating with a desired log (optimal power state) ic function according to said configuration data , said configuration memory including a shift register which has a plurality of circuit cells successively connected in a chain formation , each of said circuit cells comprising : a first inversion gate ; a first transmission gate comprising a P-channel transsistor and an N-channel transistor , connected to an output of said first inversion gate , being switched by a clock ; a second inversion gate connected to an output of said first transmission gate ; a first feedback transmission gate comprising solely a first P-channel transistor , connected between an output of said second inversion gate and an input of said first inversion gate , being switched by said clock ; a second transmission gate , connected to the output of said second inversion gate , being switched by an inversion clock ; and a second P-channel transistor , connected to the output of said first transmission gate , being switched by said inversion clock ; wherein said plurality of circuit cells are successively connected such that the input of said first inversion gate of said circuit cell is connected to an output of a second feedback transmission gate of a former-stage circuit cell , and the output of said first inversion gate of said circuit cell is connected to an output of a second P-channel transistor of said former-stage circuit cell .
US6854067B1 CLAIM 13 . In a microcontroller , a system comprising : a bus ; a processor coupled to said bus ; a power on reset circuit (one input terminal) , said processor and said power on reset circuit coupled to said bus and interconnectedly coupled with said processor via said bus ; and a switched mode pump power supply interconnectedly coupled with said power on reset circuit and responsive to signals therefrom wherein said system executes a method of dynamically controlling a plurality of power stability functions (NAND gate) for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor via said bus ; e) controlling certain functions of said microcontroller according to said suitability status ; and f) dynamically programming said power on reset circuit via said bus .	US6018559A CLAIM 3 . The shift register as claimed in claim 1 , wherein said first inversion gate has a first NAND gate (power stability functions) , and said second inversion gate has a second NAND gate . US6018559A CLAIM 8 . The shift register as claimed in claim 3 , further comprising a state setting circuit , connected to one input terminal (reset circuit) of said first NAND gate and one input terminal of said second NAND gate , for setting a state in said circuit cell .
US6854067B1 CLAIM 14 . The system as recited in claim 13 , wherein said b) and said c) of said method are accomplished by said power on reset circuit (one input terminal) .	US6018559A CLAIM 8 . The shift register as claimed in claim 3 , further comprising a state setting circuit , connected to one input terminal (reset circuit) of said first NAND gate and one input terminal of said second NAND gate , for setting a state in said circuit cell .
US6854067B1 CLAIM 16 . The system as recited in claim 15 , wherein said c) further comprises : c1) generating a precision reference voltage , said precision reference voltage independent of said common supply voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages (producing one) , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US6018559A CLAIM 10 . The shift register as claimed in claim 1 , wherein each of said circuit cells further comprises a data output terminal , and said shift register further comprises a decoder circuit , connected to said data output terminals of said circuit cells , producing one (aspect voltages) data set from said data output terminals according to a control input signal .
US6854067B1 CLAIM 18 . The system as recited in claim 17 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state (d log) corresponding to said status ; f3) programmatically calculating an optimal value for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	US6018559A CLAIM 12 . A programmable logic circuit having a configuration memory being provided with configuration data , and at least one logic cell operating with a desired log (optimal power state) ic function according to said configuration data , said configuration memory including a shift register which has a plurality of circuit cells successively connected in a chain formation , each of said circuit cells comprising : a first inversion gate ; a first transmission gate comprising a P-channel transsistor and an N-channel transistor , connected to an output of said first inversion gate , being switched by a clock ; a second inversion gate connected to an output of said first transmission gate ; a first feedback transmission gate comprising solely a first P-channel transistor , connected between an output of said second inversion gate and an input of said first inversion gate , being switched by said clock ; a second transmission gate , connected to the output of said second inversion gate , being switched by an inversion clock ; and a second P-channel transistor , connected to the output of said first transmission gate , being switched by said inversion clock ; wherein said plurality of circuit cells are successively connected such that the input of said first inversion gate of said circuit cell is connected to an output of a second feedback transmission gate of a former-stage circuit cell , and the output of said first inversion gate of said circuit cell is connected to an output of a second P-channel transistor of said former-stage circuit cell .
US6854067B1 CLAIM 20 . In a microcontroller having a power on reset circuit (one input terminal) interconnected with a processor a method of dynamically controlling said power state , said method comprising : a) ascertaining a power state powered by a switched mode pump power supply , said switched mode pump power supply interconnected with and responsive to control by said power on reset circuit ; b) programmatically determining desired changes to said power state ; c) intercommunicating between said processor and said power on reset circuit ; d) adjusting said power on reset circuit corresponding to said desired changes to said power state ; e) controlling said switched mode pump power supply according to said d) ; and f) repeating said a) through e) .	US6018559A CLAIM 8 . The shift register as claimed in claim 3 , further comprising a state setting circuit , connected to one input terminal (reset circuit) of said first NAND gate and one input terminal of said second NAND gate , for setting a state in said circuit cell .

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	US5835396A Filed: 1996-10-17 Issued: 1998-11-10 Three-dimensional read-only memory (Original Assignee) Zhang; Guobiao Guobiao Zhang
US6854067B1 CLAIM 1 . In a microcontroller with an embedded processor , a switched mode pump power supply and power on reset circuit , a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state (semiconductor layer) to said microcontroller from said switched mode pump power supply , wherein said processor and said power on reset circuit are interconnectedly coupled , and wherein said switched mode pump power supply is interconnectedly coupled with said power on reset circuit and responsive to signals therefrom ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor ; e) controlling certain functions of said microcontroller accordingly .	US5835396A CLAIM 6 . The read-only memory element according to claim 5 wherein said quasi-conduction layer further comprises a first semiconductor layer (power state, power state condition, power state condition signals) and a second semiconductor layer , said first semiconductor layer and said second semiconductor layer being opposite doped .
US6854067B1 CLAIM 5 . The method as recited in claim 4 , wherein said b) further comprises sensing a common supply voltage , wherein said common supply voltage is the voltage of said power state (semiconductor layer) .	US5835396A CLAIM 6 . The read-only memory element according to claim 5 wherein said quasi-conduction layer further comprises a first semiconductor layer (power state, power state condition, power state condition signals) and a second semiconductor layer , said first semiconductor layer and said second semiconductor layer being opposite doped .
US6854067B1 CLAIM 6 . The method as recited in claim 5 , wherein said c) further comprises : c1) generating a precision reference voltage (straight line) ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state (semiconductor layer) condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US5835396A CLAIM 6 . The read-only memory element according to claim 5 wherein said quasi-conduction layer further comprises a first semiconductor layer (power state, power state condition, power state condition signals) and a second semiconductor layer , said first semiconductor layer and said second semiconductor layer being opposite doped . US5835396A CLAIM 15 . The semiconductor integrated circuit according to claim 12 wherein : said memory level further comprise a plurality of word lines and a plurality of first contact vias , said word lines being coupled to said semiconductor substrate through said first contact vias ; said semiconductor substrate further comprises a plurality of first contact points for said memory level , said first contact vias making contact with said semiconductor substrate at said first contact points ; and said first contact points form at least one straight line (precision reference voltage) .
US6854067B1 CLAIM 7 . The method as recited in claim 6 , wherein said precision reference voltage (straight line) is independent of said common supply voltage .	US5835396A CLAIM 15 . The semiconductor integrated circuit according to claim 12 wherein : said memory level further comprise a plurality of word lines and a plurality of first contact vias , said word lines being coupled to said semiconductor substrate through said first contact vias ; said semiconductor substrate further comprises a plurality of first contact points for said memory level , said first contact vias making contact with said semiconductor substrate at said first contact points ; and said first contact points form at least one straight line (precision reference voltage) .
US6854067B1 CLAIM 11 . The method as recited in claim 10 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state (semiconductor layer) corresponding to said status ; f3) programmatically calculating an optimal value for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	US5835396A CLAIM 1 . A read-only memory element in an integrated circuit comprising : a first electrode , said first electrode comprising metallic materials ; a second electrode , said second electrode comprising metallic materials ; a quasi-conduction layer separating said first electrode and said second electrode , said quasi-conduction layer being a nonlinear resistor , having a low resistance at the read voltage and having a higher resistance when the applied voltage (optimal power) is smaller than the read voltage . US5835396A CLAIM 6 . The read-only memory element according to claim 5 wherein said quasi-conduction layer further comprises a first semiconductor layer (power state, power state condition, power state condition signals) and a second semiconductor layer , said first semiconductor layer and said second semiconductor layer being opposite doped .
US6854067B1 CLAIM 13 . In a microcontroller , a system comprising : a bus ; a processor coupled to said bus ; a power on reset circuit , said processor and said power on reset circuit coupled to said bus and interconnectedly coupled with said processor via said bus ; and a switched mode pump power supply interconnectedly coupled with said power on reset circuit and responsive to signals therefrom wherein said system executes a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state (semiconductor layer) to said microcontroller from said switched mode pump power supply ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor via said bus ; e) controlling certain functions of said microcontroller according to said suitability status ; and f) dynamically programming said power on reset circuit via said bus .	US5835396A CLAIM 6 . The read-only memory element according to claim 5 wherein said quasi-conduction layer further comprises a first semiconductor layer (power state, power state condition, power state condition signals) and a second semiconductor layer , said first semiconductor layer and said second semiconductor layer being opposite doped .
US6854067B1 CLAIM 15 . The system as recited in claim 14 , wherein said b) of said method further comprises sensing a common supply voltage , wherein said common supply voltage is the voltage of said power state (semiconductor layer) .	US5835396A CLAIM 6 . The read-only memory element according to claim 5 wherein said quasi-conduction layer further comprises a first semiconductor layer (power state, power state condition, power state condition signals) and a second semiconductor layer , said first semiconductor layer and said second semiconductor layer being opposite doped .
US6854067B1 CLAIM 16 . The system as recited in claim 15 , wherein said c) further comprises : c1) generating a precision reference voltage (straight line) , said precision reference voltage independent of said common supply voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state (semiconductor layer) condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US5835396A CLAIM 6 . The read-only memory element according to claim 5 wherein said quasi-conduction layer further comprises a first semiconductor layer (power state, power state condition, power state condition signals) and a second semiconductor layer , said first semiconductor layer and said second semiconductor layer being opposite doped . US5835396A CLAIM 15 . The semiconductor integrated circuit according to claim 12 wherein : said memory level further comprise a plurality of word lines and a plurality of first contact vias , said word lines being coupled to said semiconductor substrate through said first contact vias ; said semiconductor substrate further comprises a plurality of first contact points for said memory level , said first contact vias making contact with said semiconductor substrate at said first contact points ; and said first contact points form at least one straight line (precision reference voltage) .
US6854067B1 CLAIM 18 . The system as recited in claim 17 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state (semiconductor layer) corresponding to said status ; f3) programmatically calculating an optimal value for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	US5835396A CLAIM 1 . A read-only memory element in an integrated circuit comprising : a first electrode , said first electrode comprising metallic materials ; a second electrode , said second electrode comprising metallic materials ; a quasi-conduction layer separating said first electrode and said second electrode , said quasi-conduction layer being a nonlinear resistor , having a low resistance at the read voltage and having a higher resistance when the applied voltage (optimal power) is smaller than the read voltage . US5835396A CLAIM 6 . The read-only memory element according to claim 5 wherein said quasi-conduction layer further comprises a first semiconductor layer (power state, power state condition, power state condition signals) and a second semiconductor layer , said first semiconductor layer and said second semiconductor layer being opposite doped .
US6854067B1 CLAIM 20 . In a microcontroller having a power on reset circuit interconnected with a processor a method of dynamically controlling said power state (semiconductor layer) , said method comprising : a) ascertaining a power state powered by a switched mode pump power supply , said switched mode pump power supply interconnected with and responsive to control by said power on reset circuit ; b) programmatically determining desired changes to said power state ; c) intercommunicating between said processor and said power on reset circuit ; d) adjusting said power on reset circuit corresponding to said desired changes to said power state ; e) controlling said switched mode pump power supply according to said d) ; and f) repeating said a) through e) .	US5835396A CLAIM 6 . The read-only memory element according to claim 5 wherein said quasi-conduction layer further comprises a first semiconductor layer (power state, power state condition, power state condition signals) and a second semiconductor layer , said first semiconductor layer and said second semiconductor layer being opposite doped .

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	US5744944A Filed: 1995-12-13 Issued: 1998-04-28 Programmable bandwidth voltage regulator (Original Assignee) SGS Thomson Microelectronics Inc (Current Assignee) STMicroelectronics lnc USA Eric J. Danstrom
US6854067B1 CLAIM 1 . In a microcontroller with an embedded processor , a switched mode pump power supply (control output) and power on reset circuit , a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state (control output) to said microcontroller from said switched mode pump power supply , wherein said processor and said power on reset circuit are interconnectedly coupled , and wherein said switched mode pump power supply is interconnectedly coupled with said power on reset circuit and responsive to signals therefrom ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor ; e) controlling certain functions of said microcontroller accordingly .	US5744944A CLAIM 1 . The electronic system comprising : at least one component capable of operating at either of at least two power consumption levels , having a power supply input , and a control input ; a control device for detecting that the component is to start and stop being accessed prior to the component being accessed based on an access signal , the control device having an access signal input , a first control output (mode pump power supply, power state) coupled to the control input of the component for signaling the component to switch from one power consumption level to another power consumption level , and a second control output for producing a control signal responsive to the access signal ; a power supply including : a voltage regulator capable of operating with two or more bandwidths comprising : a first input coupled to a power source ; a second input coupled to the second control output for receiving the control signal the voltage regulator switches from one bandwidth to another bandwidth responsive to the control signal received at the second input ; and , an output coupled to the power supply input of the component .
US6854067B1 CLAIM 5 . The method as recited in claim 4 , wherein said b) further comprises sensing a common supply voltage , wherein said common supply voltage is the voltage of said power state (control output) .	US5744944A CLAIM 1 . The electronic system comprising : at least one component capable of operating at either of at least two power consumption levels , having a power supply input , and a control input ; a control device for detecting that the component is to start and stop being accessed prior to the component being accessed based on an access signal , the control device having an access signal input , a first control output (mode pump power supply, power state) coupled to the control input of the component for signaling the component to switch from one power consumption level to another power consumption level , and a second control output for producing a control signal responsive to the access signal ; a power supply including : a voltage regulator capable of operating with two or more bandwidths comprising : a first input coupled to a power source ; a second input coupled to the second control output for receiving the control signal the voltage regulator switches from one bandwidth to another bandwidth responsive to the control signal received at the second input ; and , an output coupled to the power supply input of the component .
US6854067B1 CLAIM 6 . The method as recited in claim 5 , wherein said c) further comprises : c1) generating a precision reference voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state (control output) condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US5744944A CLAIM 1 . The electronic system comprising : at least one component capable of operating at either of at least two power consumption levels , having a power supply input , and a control input ; a control device for detecting that the component is to start and stop being accessed prior to the component being accessed based on an access signal , the control device having an access signal input , a first control output (mode pump power supply, power state) coupled to the control input of the component for signaling the component to switch from one power consumption level to another power consumption level , and a second control output for producing a control signal responsive to the access signal ; a power supply including : a voltage regulator capable of operating with two or more bandwidths comprising : a first input coupled to a power source ; a second input coupled to the second control output for receiving the control signal the voltage regulator switches from one bandwidth to another bandwidth responsive to the control signal received at the second input ; and , an output coupled to the power supply input of the component .
US6854067B1 CLAIM 11 . The method as recited in claim 10 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state (control output) corresponding to said status ; f3) programmatically calculating an optimal value for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	US5744944A CLAIM 1 . The electronic system comprising : at least one component capable of operating at either of at least two power consumption levels , having a power supply input , and a control input ; a control device for detecting that the component is to start and stop being accessed prior to the component being accessed based on an access signal , the control device having an access signal input , a first control output (mode pump power supply, power state) coupled to the control input of the component for signaling the component to switch from one power consumption level to another power consumption level , and a second control output for producing a control signal responsive to the access signal ; a power supply including : a voltage regulator capable of operating with two or more bandwidths comprising : a first input coupled to a power source ; a second input coupled to the second control output for receiving the control signal the voltage regulator switches from one bandwidth to another bandwidth responsive to the control signal received at the second input ; and , an output coupled to the power supply input of the component . US5744944A CLAIM 18 . A computer comprising : a voltage regulator capable of operating with two or more bandwidths comprising a first input , a second input , an output , and a regulating means coupled to the second input for stabilizing the voltage regulator by switching from one bandwidth to another bandwidth responsive to a control signal ; a dynamic load , having a power supply input coupled to the output , and a control input , the dynamic load capable of operating at either of at least two levels (optimal power) of power consumption ; and , a control device for detecting changes in operating conditions of the computer , and having a first control output coupled to said control input of the dynamic load , and a second control output coupled to said second input of said voltage regulator ; wherein said regulating means changes the bandwidth of said voltage regulator responsive to the control device detecting the dynamic load is going to start and stop being accessed .
US6854067B1 CLAIM 13 . In a microcontroller , a system comprising : a bus ; a processor coupled to said bus ; a power on reset circuit , said processor and said power on reset circuit coupled to said bus and interconnectedly coupled with said processor via said bus ; and a switched mode pump power supply (control output) interconnectedly coupled with said power on reset circuit and responsive to signals therefrom wherein said system executes a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state (control output) to said microcontroller from said switched mode pump power supply ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor via said bus ; e) controlling certain functions of said microcontroller according to said suitability status ; and f) dynamically programming said power on reset circuit via said bus .	US5744944A CLAIM 1 . The electronic system comprising : at least one component capable of operating at either of at least two power consumption levels , having a power supply input , and a control input ; a control device for detecting that the component is to start and stop being accessed prior to the component being accessed based on an access signal , the control device having an access signal input , a first control output (mode pump power supply, power state) coupled to the control input of the component for signaling the component to switch from one power consumption level to another power consumption level , and a second control output for producing a control signal responsive to the access signal ; a power supply including : a voltage regulator capable of operating with two or more bandwidths comprising : a first input coupled to a power source ; a second input coupled to the second control output for receiving the control signal the voltage regulator switches from one bandwidth to another bandwidth responsive to the control signal received at the second input ; and , an output coupled to the power supply input of the component .
US6854067B1 CLAIM 15 . The system as recited in claim 14 , wherein said b) of said method further comprises sensing a common supply voltage , wherein said common supply voltage is the voltage of said power state (control output) .	US5744944A CLAIM 1 . The electronic system comprising : at least one component capable of operating at either of at least two power consumption levels , having a power supply input , and a control input ; a control device for detecting that the component is to start and stop being accessed prior to the component being accessed based on an access signal , the control device having an access signal input , a first control output (mode pump power supply, power state) coupled to the control input of the component for signaling the component to switch from one power consumption level to another power consumption level , and a second control output for producing a control signal responsive to the access signal ; a power supply including : a voltage regulator capable of operating with two or more bandwidths comprising : a first input coupled to a power source ; a second input coupled to the second control output for receiving the control signal the voltage regulator switches from one bandwidth to another bandwidth responsive to the control signal received at the second input ; and , an output coupled to the power supply input of the component .
US6854067B1 CLAIM 16 . The system as recited in claim 15 , wherein said c) further comprises : c1) generating a precision reference voltage , said precision reference voltage independent of said common supply voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state (control output) condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US5744944A CLAIM 1 . The electronic system comprising : at least one component capable of operating at either of at least two power consumption levels , having a power supply input , and a control input ; a control device for detecting that the component is to start and stop being accessed prior to the component being accessed based on an access signal , the control device having an access signal input , a first control output (mode pump power supply, power state) coupled to the control input of the component for signaling the component to switch from one power consumption level to another power consumption level , and a second control output for producing a control signal responsive to the access signal ; a power supply including : a voltage regulator capable of operating with two or more bandwidths comprising : a first input coupled to a power source ; a second input coupled to the second control output for receiving the control signal the voltage regulator switches from one bandwidth to another bandwidth responsive to the control signal received at the second input ; and , an output coupled to the power supply input of the component .
US6854067B1 CLAIM 18 . The system as recited in claim 17 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state (control output) corresponding to said status ; f3) programmatically calculating an optimal value for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	US5744944A CLAIM 1 . The electronic system comprising : at least one component capable of operating at either of at least two power consumption levels , having a power supply input , and a control input ; a control device for detecting that the component is to start and stop being accessed prior to the component being accessed based on an access signal , the control device having an access signal input , a first control output (mode pump power supply, power state) coupled to the control input of the component for signaling the component to switch from one power consumption level to another power consumption level , and a second control output for producing a control signal responsive to the access signal ; a power supply including : a voltage regulator capable of operating with two or more bandwidths comprising : a first input coupled to a power source ; a second input coupled to the second control output for receiving the control signal the voltage regulator switches from one bandwidth to another bandwidth responsive to the control signal received at the second input ; and , an output coupled to the power supply input of the component . US5744944A CLAIM 18 . A computer comprising : a voltage regulator capable of operating with two or more bandwidths comprising a first input , a second input , an output , and a regulating means coupled to the second input for stabilizing the voltage regulator by switching from one bandwidth to another bandwidth responsive to a control signal ; a dynamic load , having a power supply input coupled to the output , and a control input , the dynamic load capable of operating at either of at least two levels (optimal power) of power consumption ; and , a control device for detecting changes in operating conditions of the computer , and having a first control output coupled to said control input of the dynamic load , and a second control output coupled to said second input of said voltage regulator ; wherein said regulating means changes the bandwidth of said voltage regulator responsive to the control device detecting the dynamic load is going to start and stop being accessed .
US6854067B1 CLAIM 20 . In a microcontroller having a power on reset circuit interconnected with a processor a method of dynamically controlling said power state (control output) , said method comprising : a) ascertaining a power state powered by a switched mode pump power supply (control output) , said switched mode pump power supply interconnected with and responsive to control by said power on reset circuit ; b) programmatically determining desired changes to said power state ; c) intercommunicating between said processor and said power on reset circuit ; d) adjusting said power on reset circuit corresponding to said desired changes to said power state ; e) controlling said switched mode pump power supply according to said d) ; and f) repeating said a) through e) .	US5744944A CLAIM 1 . The electronic system comprising : at least one component capable of operating at either of at least two power consumption levels , having a power supply input , and a control input ; a control device for detecting that the component is to start and stop being accessed prior to the component being accessed based on an access signal , the control device having an access signal input , a first control output (mode pump power supply, power state) coupled to the control input of the component for signaling the component to switch from one power consumption level to another power consumption level , and a second control output for producing a control signal responsive to the access signal ; a power supply including : a voltage regulator capable of operating with two or more bandwidths comprising : a first input coupled to a power source ; a second input coupled to the second control output for receiving the control signal the voltage regulator switches from one bandwidth to another bandwidth responsive to the control signal received at the second input ; and , an output coupled to the power supply input of the component .

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	US5614861A Filed: 1995-09-12 Issued: 1997-03-25 N-phase modulated signal demodulation system with carrier reproduction (Original Assignee) Mitsubishi Electric Corp (Current Assignee) Mitsubishi Electric Corp Hiroyuki Harada
US6854067B1 CLAIM 1 . In a microcontroller with an embedded processor , a switched mode pump power supply and power on reset circuit (respective output) , a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply , wherein said processor and said power on reset circuit are interconnectedly coupled , and wherein said switched mode pump power supply is interconnectedly coupled with said power on reset circuit and responsive to signals therefrom ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor ; e) controlling certain functions of said microcontroller accordingly .	US5614861A CLAIM 11 . A phase modulated signal demodulation system of claim 2 , comprising : said second clock generation circuit producing signals α , γ , β ; said phase detector further comprising a plurality of outputs ; said data protection circuit having a series of data count arrays , one said data count array for each of said phase detector outputs ; each said data count array comprising a NAND gate , a cascade connection of T flip-flops , and a D flip-flop ; each NAND gate having as inputs said signal α and a respective output (reset circuit) of said phase detector , and having an output applied to said cascade connection of T flip-flops ; said cascade connection of T flip-flops forming a majority counter , said majority counter outputting a majority value of said phase detector output in synchronization with signal α ; said cascaded T flip-flops having an output input into said D flip-flop in synchronization with said signal β ; said cascaded T flip-flops being reset in synchronization with said signal γ ; each said D flip-flop corresponding to each said data count array forming said phase information of said N-phase phase modulated signals .
US6854067B1 CLAIM 2 . The method as recited in claim 1 , further comprising : f) dynamically programming said power on reset circuit (respective output) .	US5614861A CLAIM 11 . A phase modulated signal demodulation system of claim 2 , comprising : said second clock generation circuit producing signals α , γ , β ; said phase detector further comprising a plurality of outputs ; said data protection circuit having a series of data count arrays , one said data count array for each of said phase detector outputs ; each said data count array comprising a NAND gate , a cascade connection of T flip-flops , and a D flip-flop ; each NAND gate having as inputs said signal α and a respective output (reset circuit) of said phase detector , and having an output applied to said cascade connection of T flip-flops ; said cascade connection of T flip-flops forming a majority counter , said majority counter outputting a majority value of said phase detector output in synchronization with signal α ; said cascaded T flip-flops having an output input into said D flip-flop in synchronization with said signal β ; said cascaded T flip-flops being reset in synchronization with said signal γ ; each said D flip-flop corresponding to each said data count array forming said phase information of said N-phase phase modulated signals .
US6854067B1 CLAIM 3 . The method as recited in claim 2 , wherein said power on reset circuit (respective output) and said processor are interconnected via a bus .	US5614861A CLAIM 11 . A phase modulated signal demodulation system of claim 2 , comprising : said second clock generation circuit producing signals α , γ , β ; said phase detector further comprising a plurality of outputs ; said data protection circuit having a series of data count arrays , one said data count array for each of said phase detector outputs ; each said data count array comprising a NAND gate , a cascade connection of T flip-flops , and a D flip-flop ; each NAND gate having as inputs said signal α and a respective output (reset circuit) of said phase detector , and having an output applied to said cascade connection of T flip-flops ; said cascade connection of T flip-flops forming a majority counter , said majority counter outputting a majority value of said phase detector output in synchronization with signal α ; said cascaded T flip-flops having an output input into said D flip-flop in synchronization with said signal β ; said cascaded T flip-flops being reset in synchronization with said signal γ ; each said D flip-flop corresponding to each said data count array forming said phase information of said N-phase phase modulated signals .
US6854067B1 CLAIM 4 . The method as recited in claim 3 , wherein said b) and said c) are accomplished by said power on reset circuit (respective output) .	US5614861A CLAIM 11 . A phase modulated signal demodulation system of claim 2 , comprising : said second clock generation circuit producing signals α , γ , β ; said phase detector further comprising a plurality of outputs ; said data protection circuit having a series of data count arrays , one said data count array for each of said phase detector outputs ; each said data count array comprising a NAND gate , a cascade connection of T flip-flops , and a D flip-flop ; each NAND gate having as inputs said signal α and a respective output (reset circuit) of said phase detector , and having an output applied to said cascade connection of T flip-flops ; said cascade connection of T flip-flops forming a majority counter , said majority counter outputting a majority value of said phase detector output in synchronization with signal α ; said cascaded T flip-flops having an output input into said D flip-flop in synchronization with said signal β ; said cascaded T flip-flops being reset in synchronization with said signal γ ; each said D flip-flop corresponding to each said data count array forming said phase information of said N-phase phase modulated signals .
US6854067B1 CLAIM 11 . The method as recited in claim 10 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state (d log) corresponding to said status ; f3) programmatically calculating an optimal value for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	US5614861A CLAIM 7 . A phase modulated signal demodulation system of claim 1 , wherein said phase detector further comprises a series of detection banks each corresponding to one of said N clocks , and each detection bank comprising : an exclusive OR gate , a comparing register , and a logical gate ; said exclusive OR gate carrying out an exclusive OR operation between an input of said N-phase phase modulated signal and a respective one of said N clocks to produce an output applied to a respective comparing register , and said comparing register producing an output applied to said log (optimal power state) ical gate to determine the phase of said N-phase phase modulated signal relative to the respective one of said clocks .
US6854067B1 CLAIM 13 . In a microcontroller , a system comprising : a bus ; a processor coupled to said bus ; a power on reset circuit (respective output) , said processor and said power on reset circuit coupled to said bus and interconnectedly coupled with said processor via said bus ; and a switched mode pump power supply interconnectedly coupled with said power on reset circuit and responsive to signals therefrom wherein said system executes a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor via said bus ; e) controlling certain functions of said microcontroller according to said suitability status ; and f) dynamically programming said power on reset circuit via said bus .	US5614861A CLAIM 11 . A phase modulated signal demodulation system of claim 2 , comprising : said second clock generation circuit producing signals α , γ , β ; said phase detector further comprising a plurality of outputs ; said data protection circuit having a series of data count arrays , one said data count array for each of said phase detector outputs ; each said data count array comprising a NAND gate , a cascade connection of T flip-flops , and a D flip-flop ; each NAND gate having as inputs said signal α and a respective output (reset circuit) of said phase detector , and having an output applied to said cascade connection of T flip-flops ; said cascade connection of T flip-flops forming a majority counter , said majority counter outputting a majority value of said phase detector output in synchronization with signal α ; said cascaded T flip-flops having an output input into said D flip-flop in synchronization with said signal β ; said cascaded T flip-flops being reset in synchronization with said signal γ ; each said D flip-flop corresponding to each said data count array forming said phase information of said N-phase phase modulated signals .
US6854067B1 CLAIM 14 . The system as recited in claim 13 , wherein said b) and said c) of said method are accomplished by said power on reset circuit (respective output) .	US5614861A CLAIM 11 . A phase modulated signal demodulation system of claim 2 , comprising : said second clock generation circuit producing signals α , γ , β ; said phase detector further comprising a plurality of outputs ; said data protection circuit having a series of data count arrays , one said data count array for each of said phase detector outputs ; each said data count array comprising a NAND gate , a cascade connection of T flip-flops , and a D flip-flop ; each NAND gate having as inputs said signal α and a respective output (reset circuit) of said phase detector , and having an output applied to said cascade connection of T flip-flops ; said cascade connection of T flip-flops forming a majority counter , said majority counter outputting a majority value of said phase detector output in synchronization with signal α ; said cascaded T flip-flops having an output input into said D flip-flop in synchronization with said signal β ; said cascaded T flip-flops being reset in synchronization with said signal γ ; each said D flip-flop corresponding to each said data count array forming said phase information of said N-phase phase modulated signals .
US6854067B1 CLAIM 18 . The system as recited in claim 17 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state (d log) corresponding to said status ; f3) programmatically calculating an optimal value for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	US5614861A CLAIM 7 . A phase modulated signal demodulation system of claim 1 , wherein said phase detector further comprises a series of detection banks each corresponding to one of said N clocks , and each detection bank comprising : an exclusive OR gate , a comparing register , and a logical gate ; said exclusive OR gate carrying out an exclusive OR operation between an input of said N-phase phase modulated signal and a respective one of said N clocks to produce an output applied to a respective comparing register , and said comparing register producing an output applied to said log (optimal power state) ical gate to determine the phase of said N-phase phase modulated signal relative to the respective one of said clocks .
US6854067B1 CLAIM 20 . In a microcontroller having a power on reset circuit (respective output) interconnected with a processor a method of dynamically controlling said power state , said method comprising : a) ascertaining a power state powered by a switched mode pump power supply , said switched mode pump power supply interconnected with and responsive to control by said power on reset circuit ; b) programmatically determining desired changes to said power state ; c) intercommunicating between said processor and said power on reset circuit ; d) adjusting said power on reset circuit corresponding to said desired changes to said power state ; e) controlling said switched mode pump power supply according to said d) ; and f) repeating said a) through e) .	US5614861A CLAIM 11 . A phase modulated signal demodulation system of claim 2 , comprising : said second clock generation circuit producing signals α , γ , β ; said phase detector further comprising a plurality of outputs ; said data protection circuit having a series of data count arrays , one said data count array for each of said phase detector outputs ; each said data count array comprising a NAND gate , a cascade connection of T flip-flops , and a D flip-flop ; each NAND gate having as inputs said signal α and a respective output (reset circuit) of said phase detector , and having an output applied to said cascade connection of T flip-flops ; said cascade connection of T flip-flops forming a majority counter , said majority counter outputting a majority value of said phase detector output in synchronization with signal α ; said cascaded T flip-flops having an output input into said D flip-flop in synchronization with said signal β ; said cascaded T flip-flops being reset in synchronization with said signal γ ; each said D flip-flop corresponding to each said data count array forming said phase information of said N-phase phase modulated signals .

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	JPH07209091A Filed: 1994-12-21 Issued: 1995-08-11 マイクロプロセッサの温度に関する検知信号提供装置 (Original Assignee) Advanced Micro Devicds Inc; アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド Miki Moyal, ミキ・モイヤル
US6854067B1 CLAIM 1 . In a microcontroller with an embedded processor , a switched mode pump power supply (ダイオ) and power on reset circuit , a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state (ロック) to said microcontroller from said switched mode pump power supply , wherein said processor and said power on reset circuit are interconnectedly coupled , and wherein said switched mode pump power supply is interconnectedly coupled with said power on reset circuit and responsive to signals therefrom ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor ; e) controlling certain functions of said microcontroller accordingly .	JPH07209091A CLAIM 1 【請求項１】マイクロプロセッサ（１０）の温度に関する検知信号を提供するための装置であって、前記マイクロプロセッサ（１０）はある位置にクロック (power state, power state condition, power state condition signals, optimal power state) ドライバ回路（１２）を有し、前記装置は、半導体素子（１５）を含み、前記半導体素子（１５）は出力信号を発し、前記出力信号は温度に関係し、前記半導体素子（１５）はマイクロプロセッサ（１０）内に集積化され、前記装置は、さらに、制御入力（７２）を有する制御回路を含み、前記制御入力（７２）は前記半導体素子（１５）に動作的に結合され前記出力信号を受信し、前記制御回路（２８）は前記出力信号に応答して前記検知信号を発生し、前記出力信号がしきい値と予め定められた関係にあるときに前記検知信号が発生されることを特徴とする、検知信号提供装置。 JPH07209091A CLAIM 3 【請求項３】前記半導体素子（１５）は複数のダイオ (mode pump power supply) ード（５２、５４）をさらに含むことをさらに特徴とする、請求項１または２に記載の検知信号提供装置。
US6854067B1 CLAIM 5 . The method as recited in claim 4 , wherein said b) further comprises sensing a common supply voltage , wherein said common supply voltage is the voltage of said power state (ロック) .	JPH07209091A CLAIM 1 【請求項１】マイクロプロセッサ（１０）の温度に関する検知信号を提供するための装置であって、前記マイクロプロセッサ（１０）はある位置にクロック (power state, power state condition, power state condition signals, optimal power state) ドライバ回路（１２）を有し、前記装置は、半導体素子（１５）を含み、前記半導体素子（１５）は出力信号を発し、前記出力信号は温度に関係し、前記半導体素子（１５）はマイクロプロセッサ（１０）内に集積化され、前記装置は、さらに、制御入力（７２）を有する制御回路を含み、前記制御入力（７２）は前記半導体素子（１５）に動作的に結合され前記出力信号を受信し、前記制御回路（２８）は前記出力信号に応答して前記検知信号を発生し、前記出力信号がしきい値と予め定められた関係にあるときに前記検知信号が発生されることを特徴とする、検知信号提供装置。
US6854067B1 CLAIM 6 . The method as recited in claim 5 , wherein said c) further comprises : c1) generating a precision reference voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state (ロック) condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	JPH07209091A CLAIM 1 【請求項１】マイクロプロセッサ（１０）の温度に関する検知信号を提供するための装置であって、前記マイクロプロセッサ（１０）はある位置にクロック (power state, power state condition, power state condition signals, optimal power state) ドライバ回路（１２）を有し、前記装置は、半導体素子（１５）を含み、前記半導体素子（１５）は出力信号を発し、前記出力信号は温度に関係し、前記半導体素子（１５）はマイクロプロセッサ（１０）内に集積化され、前記装置は、さらに、制御入力（７２）を有する制御回路を含み、前記制御入力（７２）は前記半導体素子（１５）に動作的に結合され前記出力信号を受信し、前記制御回路（２８）は前記出力信号に応答して前記検知信号を発生し、前記出力信号がしきい値と予め定められた関係にあるときに前記検知信号が発生されることを特徴とする、検知信号提供装置。
US6854067B1 CLAIM 11 . The method as recited in claim 10 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state (ロック) corresponding to said status ; f3) programmatically calculating an optimal value (比較的一定) for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	JPH07209091A CLAIM 1 【請求項１】マイクロプロセッサ（１０）の温度に関する検知信号を提供するための装置であって、前記マイクロプロセッサ（１０）はある位置にクロック (power state, power state condition, power state condition signals, optimal power state) ドライバ回路（１２）を有し、前記装置は、半導体素子（１５）を含み、前記半導体素子（１５）は出力信号を発し、前記出力信号は温度に関係し、前記半導体素子（１５）はマイクロプロセッサ（１０）内に集積化され、前記装置は、さらに、制御入力（７２）を有する制御回路を含み、前記制御入力（７２）は前記半導体素子（１５）に動作的に結合され前記出力信号を受信し、前記制御回路（２８）は前記出力信号に応答して前記検知信号を発生し、前記出力信号がしきい値と予め定められた関係にあるときに前記検知信号が発生されることを特徴とする、検知信号提供装置。 JPH07209091A CLAIM 8 【請求項８】前記半導体素子（１５）は前記出力信号を与えるための電流源（２０）と、前記電流源（２０）を制御するための電流源制御回路（１８）とを含み、前記電流源制御回路（１８）は温度に応答し、前記電流源（２０）は前記電流源制御回路（１８）と協動して前記出力信号を発生し、さらに、前記制御回路（２８）は第１の入力と第２の入力とを受け、前記第２の入力が前記第１の入力と予め定められた関係にあるとき前記制御回路（２８）は前記検知信号を与え、前記制御回路（２８）は前記第１の入力を与えるための第１のインピーダンス回路（２２）をさらに含み、前記第１のインピーダンス回路（２２）は前記電流源（２０）に結合され、前記第１のインピーダンス回路（２２）は前記出力信号を受け、前記出力信号に応答して前記第１の入力を発生し、さらに、前記制御回路（２８）は前記第２の入力を与えるための第２のインピーダンス回路（２４）を含み、前記第２のインピーダンス回路（２４）は前記電流源（２０）出力に結合され、前記第２のインピーダンス回路（２４）は前記出力信号を受け、前記出力信号に応答して前記第２の入力を発生し、前記第２の入力は前記出力信号の変化に対して比較的一定 (optimal value) であることを特徴とする、請求項１、２、３、４、５、６または７に記載の検知信号提供装置。
US6854067B1 CLAIM 12 . The method as recited in claim 11 , wherein said f4) further comprises : communicating each said optimal value (比較的一定) to said power supply scaler via said bus ; registering each said optimal value with said matrix of multiplexers and registers ; commanding said matrix of multiplexers and registers to change said independent multiple of said common supply voltage to correspond with said optimal value ; and monitoring said matrix of multiplexers and registers .	JPH07209091A CLAIM 8 【請求項８】前記半導体素子（１５）は前記出力信号を与えるための電流源（２０）と、前記電流源（２０）を制御するための電流源制御回路（１８）とを含み、前記電流源制御回路（１８）は温度に応答し、前記電流源（２０）は前記電流源制御回路（１８）と協動して前記出力信号を発生し、さらに、前記制御回路（２８）は第１の入力と第２の入力とを受け、前記第２の入力が前記第１の入力と予め定められた関係にあるとき前記制御回路（２８）は前記検知信号を与え、前記制御回路（２８）は前記第１の入力を与えるための第１のインピーダンス回路（２２）をさらに含み、前記第１のインピーダンス回路（２２）は前記電流源（２０）に結合され、前記第１のインピーダンス回路（２２）は前記出力信号を受け、前記出力信号に応答して前記第１の入力を発生し、さらに、前記制御回路（２８）は前記第２の入力を与えるための第２のインピーダンス回路（２４）を含み、前記第２のインピーダンス回路（２４）は前記電流源（２０）出力に結合され、前記第２のインピーダンス回路（２４）は前記出力信号を受け、前記出力信号に応答して前記第２の入力を発生し、前記第２の入力は前記出力信号の変化に対して比較的一定 (optimal value) であることを特徴とする、請求項１、２、３、４、５、６または７に記載の検知信号提供装置。
US6854067B1 CLAIM 13 . In a microcontroller , a system comprising : a bus ; a processor coupled to said bus ; a power on reset circuit , said processor and said power on reset circuit coupled to said bus and interconnectedly coupled with said processor via said bus ; and a switched mode pump power supply (ダイオ) interconnectedly coupled with said power on reset circuit and responsive to signals therefrom wherein said system executes a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state (ロック) to said microcontroller from said switched mode pump power supply ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor via said bus ; e) controlling certain functions of said microcontroller according to said suitability status ; and f) dynamically programming said power on reset circuit via said bus .	JPH07209091A CLAIM 1 【請求項１】マイクロプロセッサ（１０）の温度に関する検知信号を提供するための装置であって、前記マイクロプロセッサ（１０）はある位置にクロック (power state, power state condition, power state condition signals, optimal power state) ドライバ回路（１２）を有し、前記装置は、半導体素子（１５）を含み、前記半導体素子（１５）は出力信号を発し、前記出力信号は温度に関係し、前記半導体素子（１５）はマイクロプロセッサ（１０）内に集積化され、前記装置は、さらに、制御入力（７２）を有する制御回路を含み、前記制御入力（７２）は前記半導体素子（１５）に動作的に結合され前記出力信号を受信し、前記制御回路（２８）は前記出力信号に応答して前記検知信号を発生し、前記出力信号がしきい値と予め定められた関係にあるときに前記検知信号が発生されることを特徴とする、検知信号提供装置。 JPH07209091A CLAIM 3 【請求項３】前記半導体素子（１５）は複数のダイオ (mode pump power supply) ード（５２、５４）をさらに含むことをさらに特徴とする、請求項１または２に記載の検知信号提供装置。
US6854067B1 CLAIM 15 . The system as recited in claim 14 , wherein said b) of said method further comprises sensing a common supply voltage , wherein said common supply voltage is the voltage of said power state (ロック) .	JPH07209091A CLAIM 1 【請求項１】マイクロプロセッサ（１０）の温度に関する検知信号を提供するための装置であって、前記マイクロプロセッサ（１０）はある位置にクロック (power state, power state condition, power state condition signals, optimal power state) ドライバ回路（１２）を有し、前記装置は、半導体素子（１５）を含み、前記半導体素子（１５）は出力信号を発し、前記出力信号は温度に関係し、前記半導体素子（１５）はマイクロプロセッサ（１０）内に集積化され、前記装置は、さらに、制御入力（７２）を有する制御回路を含み、前記制御入力（７２）は前記半導体素子（１５）に動作的に結合され前記出力信号を受信し、前記制御回路（２８）は前記出力信号に応答して前記検知信号を発生し、前記出力信号がしきい値と予め定められた関係にあるときに前記検知信号が発生されることを特徴とする、検知信号提供装置。
US6854067B1 CLAIM 16 . The system as recited in claim 15 , wherein said c) further comprises : c1) generating a precision reference voltage , said precision reference voltage independent of said common supply voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state (ロック) condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	JPH07209091A CLAIM 1 【請求項１】マイクロプロセッサ（１０）の温度に関する検知信号を提供するための装置であって、前記マイクロプロセッサ（１０）はある位置にクロック (power state, power state condition, power state condition signals, optimal power state) ドライバ回路（１２）を有し、前記装置は、半導体素子（１５）を含み、前記半導体素子（１５）は出力信号を発し、前記出力信号は温度に関係し、前記半導体素子（１５）はマイクロプロセッサ（１０）内に集積化され、前記装置は、さらに、制御入力（７２）を有する制御回路を含み、前記制御入力（７２）は前記半導体素子（１５）に動作的に結合され前記出力信号を受信し、前記制御回路（２８）は前記出力信号に応答して前記検知信号を発生し、前記出力信号がしきい値と予め定められた関係にあるときに前記検知信号が発生されることを特徴とする、検知信号提供装置。
US6854067B1 CLAIM 18 . The system as recited in claim 17 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state (ロック) corresponding to said status ; f3) programmatically calculating an optimal value (比較的一定) for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	JPH07209091A CLAIM 1 【請求項１】マイクロプロセッサ（１０）の温度に関する検知信号を提供するための装置であって、前記マイクロプロセッサ（１０）はある位置にクロック (power state, power state condition, power state condition signals, optimal power state) ドライバ回路（１２）を有し、前記装置は、半導体素子（１５）を含み、前記半導体素子（１５）は出力信号を発し、前記出力信号は温度に関係し、前記半導体素子（１５）はマイクロプロセッサ（１０）内に集積化され、前記装置は、さらに、制御入力（７２）を有する制御回路を含み、前記制御入力（７２）は前記半導体素子（１５）に動作的に結合され前記出力信号を受信し、前記制御回路（２８）は前記出力信号に応答して前記検知信号を発生し、前記出力信号がしきい値と予め定められた関係にあるときに前記検知信号が発生されることを特徴とする、検知信号提供装置。 JPH07209091A CLAIM 8 【請求項８】前記半導体素子（１５）は前記出力信号を与えるための電流源（２０）と、前記電流源（２０）を制御するための電流源制御回路（１８）とを含み、前記電流源制御回路（１８）は温度に応答し、前記電流源（２０）は前記電流源制御回路（１８）と協動して前記出力信号を発生し、さらに、前記制御回路（２８）は第１の入力と第２の入力とを受け、前記第２の入力が前記第１の入力と予め定められた関係にあるとき前記制御回路（２８）は前記検知信号を与え、前記制御回路（２８）は前記第１の入力を与えるための第１のインピーダンス回路（２２）をさらに含み、前記第１のインピーダンス回路（２２）は前記電流源（２０）に結合され、前記第１のインピーダンス回路（２２）は前記出力信号を受け、前記出力信号に応答して前記第１の入力を発生し、さらに、前記制御回路（２８）は前記第２の入力を与えるための第２のインピーダンス回路（２４）を含み、前記第２のインピーダンス回路（２４）は前記電流源（２０）出力に結合され、前記第２のインピーダンス回路（２４）は前記出力信号を受け、前記出力信号に応答して前記第２の入力を発生し、前記第２の入力は前記出力信号の変化に対して比較的一定 (optimal value) であることを特徴とする、請求項１、２、３、４、５、６または７に記載の検知信号提供装置。
US6854067B1 CLAIM 19 . The method as recited in claim 18 , wherein said f4) further comprises : communicating each said optimal value (比較的一定) to said power supply scaler via said bus ; registering each said optimal value with said matrix of multiplexers and registers ; commanding said matrix of multiplexers and registers to change said independent multiple of said common supply voltage to correspond with said optimal value ; and monitoring said matrix of multiplexers and registers .	JPH07209091A CLAIM 8 【請求項８】前記半導体素子（１５）は前記出力信号を与えるための電流源（２０）と、前記電流源（２０）を制御するための電流源制御回路（１８）とを含み、前記電流源制御回路（１８）は温度に応答し、前記電流源（２０）は前記電流源制御回路（１８）と協動して前記出力信号を発生し、さらに、前記制御回路（２８）は第１の入力と第２の入力とを受け、前記第２の入力が前記第１の入力と予め定められた関係にあるとき前記制御回路（２８）は前記検知信号を与え、前記制御回路（２８）は前記第１の入力を与えるための第１のインピーダンス回路（２２）をさらに含み、前記第１のインピーダンス回路（２２）は前記電流源（２０）に結合され、前記第１のインピーダンス回路（２２）は前記出力信号を受け、前記出力信号に応答して前記第１の入力を発生し、さらに、前記制御回路（２８）は前記第２の入力を与えるための第２のインピーダンス回路（２４）を含み、前記第２のインピーダンス回路（２４）は前記電流源（２０）出力に結合され、前記第２のインピーダンス回路（２４）は前記出力信号を受け、前記出力信号に応答して前記第２の入力を発生し、前記第２の入力は前記出力信号の変化に対して比較的一定 (optimal value) であることを特徴とする、請求項１、２、３、４、５、６または７に記載の検知信号提供装置。
US6854067B1 CLAIM 20 . In a microcontroller having a power on reset circuit interconnected with a processor a method of dynamically controlling said power state (ロック) , said method comprising : a) ascertaining a power state powered by a switched mode pump power supply (ダイオ) , said switched mode pump power supply interconnected with and responsive to control by said power on reset circuit ; b) programmatically determining desired changes to said power state ; c) intercommunicating between said processor and said power on reset circuit ; d) adjusting said power on reset circuit corresponding to said desired changes to said power state ; e) controlling said switched mode pump power supply according to said d) ; and f) repeating said a) through e) .	JPH07209091A CLAIM 1 【請求項１】マイクロプロセッサ（１０）の温度に関する検知信号を提供するための装置であって、前記マイクロプロセッサ（１０）はある位置にクロック (power state, power state condition, power state condition signals, optimal power state) ドライバ回路（１２）を有し、前記装置は、半導体素子（１５）を含み、前記半導体素子（１５）は出力信号を発し、前記出力信号は温度に関係し、前記半導体素子（１５）はマイクロプロセッサ（１０）内に集積化され、前記装置は、さらに、制御入力（７２）を有する制御回路を含み、前記制御入力（７２）は前記半導体素子（１５）に動作的に結合され前記出力信号を受信し、前記制御回路（２８）は前記出力信号に応答して前記検知信号を発生し、前記出力信号がしきい値と予め定められた関係にあるときに前記検知信号が発生されることを特徴とする、検知信号提供装置。 JPH07209091A CLAIM 3 【請求項３】前記半導体素子（１５）は複数のダイオ (mode pump power supply) ード（５２、５４）をさらに含むことをさらに特徴とする、請求項１または２に記載の検知信号提供装置。

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	US5604466A Filed: 1994-11-28 Issued: 1997-02-18 On-chip voltage controlled oscillator (Original Assignee) International Business Machines Corp (Current Assignee) International Business Machines Corp Daniel M. Dreps, Raymond P. Rizzo
US6854067B1 CLAIM 6 . The method as recited in claim 5 , wherein said c) further comprises : c1) generating a precision reference voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages (voltage drop) , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one (variable current) of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US5604466A CLAIM 1 . A circuit comprising : a voltage regulator for rejecting low frequency noise from a regulated power supply , the voltage regulator including a voltage regulator output for providing a noise-attenuated regulated voltage ; and an oscillator , the voltage regulator and the oscillator implemented on a common substrate , the oscillator coupled to the voltage regulator output , the voltage regulator further including attenuation means , which attenuation means includes a passive filter coupled to the regulated power supply for attenuating high frequency noise from the regulated power supply , and for supplying power from the power supply to the voltage regulator , wherein the passive filter includes a first resistor-capacitor pair for attenuating noise frequencies higher than a response ability of the voltage regulator , wherein the noise frequencies are higher than about 5 MHz , the passive filter further including a second resistor-capacitor pair for attenuating noise frequencies higher than about 800 MHz , wherein the attenuation means further includes means for maintaining an attenuation of at least about -30 dB for noise frequencies in a range from about DC to at least about 800 MHz , wherein the voltage regulator further includes a band gap circuit and regulator means for providing adequate current to maintain the regulated voltage while preventing noise from passing through the regulator means to the voltage regulator output , the regulator means including a Darlington pair coupled to the voltage regulator output , and a control terminal of the Darlington pair coupled to the band gap circuit for receiving variable current (comparisons comparing one) , the band gap circuit coupled to the voltage regulator output and controlling the variable current in response to changes in the regulated voltage , wherein the oscillator comprises a multivibrator which includes a control voltage input , and capacitors connected in parallel , wherein a top plate of one of the capacitors is connected to a bottom plate of another one of the capacitors for providing a symmetric capacitance , and further wherein the control voltage input comprises a first transistor for receiving a control voltage signal , the first transistor coupled to the regulated power supply and to one end of a resistor , another end of the resistor coupled to both a collector and a base of a second transistor , the second transistor coupled to a plurality of transistors to form a multiple output current mirror , the multiple output current mirror coupled to the capacitors connected in parallel . US5604466A CLAIM 18 . The circuit of claim 10 , wherein the oscillator comprises a maximum number of diode voltage drop (aspect voltages) s from the voltage regulator output to ground , the maximum number of diode voltage drops equal to four .
US6854067B1 CLAIM 11 . The method as recited in claim 10 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state (one end) corresponding to said status ; f3) programmatically calculating an optimal value for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	US5604466A CLAIM 1 . A circuit comprising : a voltage regulator for rejecting low frequency noise from a regulated power supply , the voltage regulator including a voltage regulator output for providing a noise-attenuated regulated voltage ; and an oscillator , the voltage regulator and the oscillator implemented on a common substrate , the oscillator coupled to the voltage regulator output , the voltage regulator further including attenuation means , which attenuation means includes a passive filter coupled to the regulated power supply for attenuating high frequency noise from the regulated power supply , and for supplying power from the power supply to the voltage regulator , wherein the passive filter includes a first resistor-capacitor pair for attenuating noise frequencies higher than a response ability of the voltage regulator , wherein the noise frequencies are higher than about 5 MHz , the passive filter further including a second resistor-capacitor pair for attenuating noise frequencies higher than about 800 MHz , wherein the attenuation means further includes means for maintaining an attenuation of at least about -30 dB for noise frequencies in a range from about DC to at least about 800 MHz , wherein the voltage regulator further includes a band gap circuit and regulator means for providing adequate current to maintain the regulated voltage while preventing noise from passing through the regulator means to the voltage regulator output , the regulator means including a Darlington pair coupled to the voltage regulator output , and a control terminal of the Darlington pair coupled to the band gap circuit for receiving variable current , the band gap circuit coupled to the voltage regulator output and controlling the variable current in response to changes in the regulated voltage , wherein the oscillator comprises a multivibrator which includes a control voltage input , and capacitors connected in parallel , wherein a top plate of one of the capacitors is connected to a bottom plate of another one of the capacitors for providing a symmetric capacitance , and further wherein the control voltage input comprises a first transistor for receiving a control voltage signal , the first transistor coupled to the regulated power supply and to one end (optimal power state) of a resistor , another end of the resistor coupled to both a collector and a base of a second transistor , the second transistor coupled to a plurality of transistors to form a multiple output current mirror , the multiple output current mirror coupled to the capacitors connected in parallel .
US6854067B1 CLAIM 16 . The system as recited in claim 15 , wherein said c) further comprises : c1) generating a precision reference voltage , said precision reference voltage independent of said common supply voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages (voltage drop) , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one (variable current) of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US5604466A CLAIM 1 . A circuit comprising : a voltage regulator for rejecting low frequency noise from a regulated power supply , the voltage regulator including a voltage regulator output for providing a noise-attenuated regulated voltage ; and an oscillator , the voltage regulator and the oscillator implemented on a common substrate , the oscillator coupled to the voltage regulator output , the voltage regulator further including attenuation means , which attenuation means includes a passive filter coupled to the regulated power supply for attenuating high frequency noise from the regulated power supply , and for supplying power from the power supply to the voltage regulator , wherein the passive filter includes a first resistor-capacitor pair for attenuating noise frequencies higher than a response ability of the voltage regulator , wherein the noise frequencies are higher than about 5 MHz , the passive filter further including a second resistor-capacitor pair for attenuating noise frequencies higher than about 800 MHz , wherein the attenuation means further includes means for maintaining an attenuation of at least about -30 dB for noise frequencies in a range from about DC to at least about 800 MHz , wherein the voltage regulator further includes a band gap circuit and regulator means for providing adequate current to maintain the regulated voltage while preventing noise from passing through the regulator means to the voltage regulator output , the regulator means including a Darlington pair coupled to the voltage regulator output , and a control terminal of the Darlington pair coupled to the band gap circuit for receiving variable current (comparisons comparing one) , the band gap circuit coupled to the voltage regulator output and controlling the variable current in response to changes in the regulated voltage , wherein the oscillator comprises a multivibrator which includes a control voltage input , and capacitors connected in parallel , wherein a top plate of one of the capacitors is connected to a bottom plate of another one of the capacitors for providing a symmetric capacitance , and further wherein the control voltage input comprises a first transistor for receiving a control voltage signal , the first transistor coupled to the regulated power supply and to one end of a resistor , another end of the resistor coupled to both a collector and a base of a second transistor , the second transistor coupled to a plurality of transistors to form a multiple output current mirror , the multiple output current mirror coupled to the capacitors connected in parallel . US5604466A CLAIM 18 . The circuit of claim 10 , wherein the oscillator comprises a maximum number of diode voltage drop (aspect voltages) s from the voltage regulator output to ground , the maximum number of diode voltage drops equal to four .
US6854067B1 CLAIM 18 . The system as recited in claim 17 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state (one end) corresponding to said status ; f3) programmatically calculating an optimal value for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	US5604466A CLAIM 1 . A circuit comprising : a voltage regulator for rejecting low frequency noise from a regulated power supply , the voltage regulator including a voltage regulator output for providing a noise-attenuated regulated voltage ; and an oscillator , the voltage regulator and the oscillator implemented on a common substrate , the oscillator coupled to the voltage regulator output , the voltage regulator further including attenuation means , which attenuation means includes a passive filter coupled to the regulated power supply for attenuating high frequency noise from the regulated power supply , and for supplying power from the power supply to the voltage regulator , wherein the passive filter includes a first resistor-capacitor pair for attenuating noise frequencies higher than a response ability of the voltage regulator , wherein the noise frequencies are higher than about 5 MHz , the passive filter further including a second resistor-capacitor pair for attenuating noise frequencies higher than about 800 MHz , wherein the attenuation means further includes means for maintaining an attenuation of at least about -30 dB for noise frequencies in a range from about DC to at least about 800 MHz , wherein the voltage regulator further includes a band gap circuit and regulator means for providing adequate current to maintain the regulated voltage while preventing noise from passing through the regulator means to the voltage regulator output , the regulator means including a Darlington pair coupled to the voltage regulator output , and a control terminal of the Darlington pair coupled to the band gap circuit for receiving variable current , the band gap circuit coupled to the voltage regulator output and controlling the variable current in response to changes in the regulated voltage , wherein the oscillator comprises a multivibrator which includes a control voltage input , and capacitors connected in parallel , wherein a top plate of one of the capacitors is connected to a bottom plate of another one of the capacitors for providing a symmetric capacitance , and further wherein the control voltage input comprises a first transistor for receiving a control voltage signal , the first transistor coupled to the regulated power supply and to one end (optimal power state) of a resistor , another end of the resistor coupled to both a collector and a base of a second transistor , the second transistor coupled to a plurality of transistors to form a multiple output current mirror , the multiple output current mirror coupled to the capacitors connected in parallel .

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	US5399922A Filed: 1993-07-02 Issued: 1995-03-21 Macrocell comprised of two look-up tables and two flip-flops (Original Assignee) Altera Corp (Current Assignee) Altera Corp Khusrow Kiani, Janusz K. Balicki, Behzad Nouban, Ken Li
US6854067B1 CLAIM 1 . In a microcontroller with an embedded processor , a switched mode pump power supply and power on reset circuit , a method of dynamically controlling a plurality of power stability functions (control means, NAND gate) for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply , wherein said processor and said power on reset circuit are interconnectedly coupled , and wherein said switched mode pump power supply is interconnectedly coupled with said power on reset circuit and responsive to signals therefrom ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor ; e) controlling certain functions of said microcontroller accordingly .	US5399922A CLAIM 1 . In a programmable logic device (PLD) , a macrocell having a plurality of inputs and at least one output , comprising : at least one programmable logic circuit having a plurality of inputs coupled to the plurality of macrocell inputs and an output ; programmable logic means , having a first programmable input coupled to the output of the at least one programmable logic circuit , a second programmable input coupled to an output of another macrocell and a third programmable input coupled directly to an input/output terminal of the PLD , for programmably producing a logical combination of its inputs at at least one output ; and output control means (power stability functions) , coupled to the at least one output of the programmable logic means and responsive to control signals external to the macrocell , for outputing the at least one output of the programmable logic means at an output coupled to the at least one output of the macrocell , wherein , set up time is significantly reduced by programming the programmable logic means to receive an input signal directly from the input/output terminal of the PLD . US5399922A CLAIM 3 . A macrocell as recited in claim 1 , wherein the programmable logic means comprises two NAND gate (power stability functions) s with programmable inputs .
US6854067B1 CLAIM 11 . The method as recited in claim 10 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state corresponding to said status ; f3) programmatically calculating an optimal value (second log, first log) for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	US5399922A CLAIM 6 . A macrocell for use in a programmable logic device as recited in claim 5 further comprising selection means , having four inputs coupled respectively to the first log (optimal value) ic means output , to an output of the first register means , to the second log (optimal value) ic means output , and to an output of the second register means , the selection means for coupling two of its four inputs to a first and a second macrocell output , respectively .
US6854067B1 CLAIM 12 . The method as recited in claim 11 , wherein said f4) further comprises : communicating each said optimal value (second log, first log) to said power supply scaler via said bus ; registering each said optimal value with said matrix of multiplexers and registers ; commanding said matrix of multiplexers and registers to change said independent multiple of said common supply voltage to correspond with said optimal value ; and monitoring said matrix of multiplexers and registers .	US5399922A CLAIM 6 . A macrocell for use in a programmable logic device as recited in claim 5 further comprising selection means , having four inputs coupled respectively to the first log (optimal value) ic means output , to an output of the first register means , to the second log (optimal value) ic means output , and to an output of the second register means , the selection means for coupling two of its four inputs to a first and a second macrocell output , respectively .
US6854067B1 CLAIM 13 . In a microcontroller , a system comprising : a bus ; a processor coupled to said bus ; a power on reset circuit , said processor and said power on reset circuit coupled to said bus and interconnectedly coupled with said processor via said bus ; and a switched mode pump power supply interconnectedly coupled with said power on reset circuit and responsive to signals therefrom wherein said system executes a method of dynamically controlling a plurality of power stability functions (control means, NAND gate) for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor via said bus ; e) controlling certain functions of said microcontroller according to said suitability status ; and f) dynamically programming said power on reset circuit via said bus .	US5399922A CLAIM 1 . In a programmable logic device (PLD) , a macrocell having a plurality of inputs and at least one output , comprising : at least one programmable logic circuit having a plurality of inputs coupled to the plurality of macrocell inputs and an output ; programmable logic means , having a first programmable input coupled to the output of the at least one programmable logic circuit , a second programmable input coupled to an output of another macrocell and a third programmable input coupled directly to an input/output terminal of the PLD , for programmably producing a logical combination of its inputs at at least one output ; and output control means (power stability functions) , coupled to the at least one output of the programmable logic means and responsive to control signals external to the macrocell , for outputing the at least one output of the programmable logic means at an output coupled to the at least one output of the macrocell , wherein , set up time is significantly reduced by programming the programmable logic means to receive an input signal directly from the input/output terminal of the PLD . US5399922A CLAIM 3 . A macrocell as recited in claim 1 , wherein the programmable logic means comprises two NAND gate (power stability functions) s with programmable inputs .
US6854067B1 CLAIM 18 . The system as recited in claim 17 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state corresponding to said status ; f3) programmatically calculating an optimal value (second log, first log) for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	US5399922A CLAIM 6 . A macrocell for use in a programmable logic device as recited in claim 5 further comprising selection means , having four inputs coupled respectively to the first log (optimal value) ic means output , to an output of the first register means , to the second log (optimal value) ic means output , and to an output of the second register means , the selection means for coupling two of its four inputs to a first and a second macrocell output , respectively .
US6854067B1 CLAIM 19 . The method as recited in claim 18 , wherein said f4) further comprises : communicating each said optimal value (second log, first log) to said power supply scaler via said bus ; registering each said optimal value with said matrix of multiplexers and registers ; commanding said matrix of multiplexers and registers to change said independent multiple of said common supply voltage to correspond with said optimal value ; and monitoring said matrix of multiplexers and registers .	US5399922A CLAIM 6 . A macrocell for use in a programmable logic device as recited in claim 5 further comprising selection means , having four inputs coupled respectively to the first log (optimal value) ic means output , to an output of the first register means , to the second log (optimal value) ic means output , and to an output of the second register means , the selection means for coupling two of its four inputs to a first and a second macrocell output , respectively .

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	JPH06318160A Filed: 1993-05-07 Issued: 1994-11-15 二重化プロセッサ・システムの系構成制御方式 (Original Assignee) Fujitsu Ltd; 富士通株式会社 Atsushi Fujihira, Hiroshi Miyamoto, Tsuratoshi Nakano, 連利中野, 央宮本, 淳藤平
US6854067B1 CLAIM 1 . In a microcontroller with an embedded processor , a switched mode pump power supply and power on reset circuit (それぞれダイオード) , a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state (ロック) to said microcontroller from said switched mode pump power supply , wherein said processor and said power on reset circuit are interconnectedly coupled , and wherein said switched mode pump power supply is interconnectedly coupled with said power on reset circuit and responsive to signals therefrom ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor ; e) controlling certain functions of said microcontroller accordingly .	JPH06318160A CLAIM 1 【請求項１】二重化プロセッサ・システムにおいて、両系の電源部（５ 1 , ５ 2 ）から第１のダイオードの組（８ 1 , ８ 2 ）および第２のダイオードの組（９ 1 , ９ 2 ）を介して両系のシステム・クロック (power state, power state condition, power state condition signals, optimal power state) 発振部（１ 1 , １ 2 ）と制御部（２ 1 , ２ 2 ）にそれぞれ電源を供給し、両系のメイン・メモリ（３ 1 , ３ 2 ）をマスタ・スレーブ運転して内容を一致させ、両系のチャネル・コントローラ（４ 1 , ４ 2 ）をマスタ・スレーブ運転して接続先を一致させ、両系の電源監視部（６ 1 , ６ 2 ）がそれぞれ自系と他系の電源断を監視してそれぞれの電源断を示す信号を発生するとともに、現用系電源断時、現用系制御部が自系電源断に基づいてマイクロ・プログラムに制御を移して、現用系制御部の内部レジスタの内容を予備系制御部へ転送し、該転送終了後、自系を予備系に他系を現用系にそれぞれ設定して、他系を起動するとともに自系を停止状態に遷移し、起動された新現用系制御部が、両系のメイン・メモリおよびチャネル・コントローラのマスタ・スレーブの関係を構成したのち、プログラムに制御を移すことによって、中断点再開を行うことを特徴とする二重化プロセッサ・システムの系構成制御方式。 JPH06318160A CLAIM 3 【請求項３】請求項１または２に記載の二重化プロセッサ・システムの系構成制御方式において、両系の電源部（５ 1 , ５ 2 ）からそれぞれダイオード (reset circuit) （１０ 1 , １０ 2 ）を介して両系のシステム・クロック発振部（１ 1 , １ 2 ）と制御部（２ 1 , ２ 2 ）に並列に電源を供給するようにしたことを特徴とする二重化プロセッサ・システムの系構成制御方式。
US6854067B1 CLAIM 2 . The method as recited in claim 1 , further comprising : f) dynamically programming said power on reset circuit (それぞれダイオード) .	JPH06318160A CLAIM 3 【請求項３】請求項１または２に記載の二重化プロセッサ・システムの系構成制御方式において、両系の電源部（５ 1 , ５ 2 ）からそれぞれダイオード (reset circuit) （１０ 1 , １０ 2 ）を介して両系のシステム・クロック発振部（１ 1 , １ 2 ）と制御部（２ 1 , ２ 2 ）に並列に電源を供給するようにしたことを特徴とする二重化プロセッサ・システムの系構成制御方式。
US6854067B1 CLAIM 3 . The method as recited in claim 2 , wherein said power on reset circuit (それぞれダイオード) and said processor are interconnected via a bus .	JPH06318160A CLAIM 3 【請求項３】請求項１または２に記載の二重化プロセッサ・システムの系構成制御方式において、両系の電源部（５ 1 , ５ 2 ）からそれぞれダイオード (reset circuit) （１０ 1 , １０ 2 ）を介して両系のシステム・クロック発振部（１ 1 , １ 2 ）と制御部（２ 1 , ２ 2 ）に並列に電源を供給するようにしたことを特徴とする二重化プロセッサ・システムの系構成制御方式。
US6854067B1 CLAIM 4 . The method as recited in claim 3 , wherein said b) and said c) are accomplished by said power on reset circuit (それぞれダイオード) .	JPH06318160A CLAIM 3 【請求項３】請求項１または２に記載の二重化プロセッサ・システムの系構成制御方式において、両系の電源部（５ 1 , ５ 2 ）からそれぞれダイオード (reset circuit) （１０ 1 , １０ 2 ）を介して両系のシステム・クロック発振部（１ 1 , １ 2 ）と制御部（２ 1 , ２ 2 ）に並列に電源を供給するようにしたことを特徴とする二重化プロセッサ・システムの系構成制御方式。
US6854067B1 CLAIM 5 . The method as recited in claim 4 , wherein said b) further comprises sensing a common supply voltage , wherein said common supply voltage is the voltage of said power state (ロック) .	JPH06318160A CLAIM 1 【請求項１】二重化プロセッサ・システムにおいて、両系の電源部（５ 1 , ５ 2 ）から第１のダイオードの組（８ 1 , ８ 2 ）および第２のダイオードの組（９ 1 , ９ 2 ）を介して両系のシステム・クロック (power state, power state condition, power state condition signals, optimal power state) 発振部（１ 1 , １ 2 ）と制御部（２ 1 , ２ 2 ）にそれぞれ電源を供給し、両系のメイン・メモリ（３ 1 , ３ 2 ）をマスタ・スレーブ運転して内容を一致させ、両系のチャネル・コントローラ（４ 1 , ４ 2 ）をマスタ・スレーブ運転して接続先を一致させ、両系の電源監視部（６ 1 , ６ 2 ）がそれぞれ自系と他系の電源断を監視してそれぞれの電源断を示す信号を発生するとともに、現用系電源断時、現用系制御部が自系電源断に基づいてマイクロ・プログラムに制御を移して、現用系制御部の内部レジスタの内容を予備系制御部へ転送し、該転送終了後、自系を予備系に他系を現用系にそれぞれ設定して、他系を起動するとともに自系を停止状態に遷移し、起動された新現用系制御部が、両系のメイン・メモリおよびチャネル・コントローラのマスタ・スレーブの関係を構成したのち、プログラムに制御を移すことによって、中断点再開を行うことを特徴とする二重化プロセッサ・システムの系構成制御方式。
US6854067B1 CLAIM 6 . The method as recited in claim 5 , wherein said c) further comprises : c1) generating a precision reference voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state (ロック) condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	JPH06318160A CLAIM 1 【請求項１】二重化プロセッサ・システムにおいて、両系の電源部（５ 1 , ５ 2 ）から第１のダイオードの組（８ 1 , ８ 2 ）および第２のダイオードの組（９ 1 , ９ 2 ）を介して両系のシステム・クロック (power state, power state condition, power state condition signals, optimal power state) 発振部（１ 1 , １ 2 ）と制御部（２ 1 , ２ 2 ）にそれぞれ電源を供給し、両系のメイン・メモリ（３ 1 , ３ 2 ）をマスタ・スレーブ運転して内容を一致させ、両系のチャネル・コントローラ（４ 1 , ４ 2 ）をマスタ・スレーブ運転して接続先を一致させ、両系の電源監視部（６ 1 , ６ 2 ）がそれぞれ自系と他系の電源断を監視してそれぞれの電源断を示す信号を発生するとともに、現用系電源断時、現用系制御部が自系電源断に基づいてマイクロ・プログラムに制御を移して、現用系制御部の内部レジスタの内容を予備系制御部へ転送し、該転送終了後、自系を予備系に他系を現用系にそれぞれ設定して、他系を起動するとともに自系を停止状態に遷移し、起動された新現用系制御部が、両系のメイン・メモリおよびチャネル・コントローラのマスタ・スレーブの関係を構成したのち、プログラムに制御を移すことによって、中断点再開を行うことを特徴とする二重化プロセッサ・システムの系構成制御方式。
US6854067B1 CLAIM 11 . The method as recited in claim 10 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state (ロック) corresponding to said status ; f3) programmatically calculating an optimal value for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	JPH06318160A CLAIM 1 【請求項１】二重化プロセッサ・システムにおいて、両系の電源部（５ 1 , ５ 2 ）から第１のダイオードの組（８ 1 , ８ 2 ）および第２のダイオードの組（９ 1 , ９ 2 ）を介して両系のシステム・クロック (power state, power state condition, power state condition signals, optimal power state) 発振部（１ 1 , １ 2 ）と制御部（２ 1 , ２ 2 ）にそれぞれ電源を供給し、両系のメイン・メモリ（３ 1 , ３ 2 ）をマスタ・スレーブ運転して内容を一致させ、両系のチャネル・コントローラ（４ 1 , ４ 2 ）をマスタ・スレーブ運転して接続先を一致させ、両系の電源監視部（６ 1 , ６ 2 ）がそれぞれ自系と他系の電源断を監視してそれぞれの電源断を示す信号を発生するとともに、現用系電源断時、現用系制御部が自系電源断に基づいてマイクロ・プログラムに制御を移して、現用系制御部の内部レジスタの内容を予備系制御部へ転送し、該転送終了後、自系を予備系に他系を現用系にそれぞれ設定して、他系を起動するとともに自系を停止状態に遷移し、起動された新現用系制御部が、両系のメイン・メモリおよびチャネル・コントローラのマスタ・スレーブの関係を構成したのち、プログラムに制御を移すことによって、中断点再開を行うことを特徴とする二重化プロセッサ・システムの系構成制御方式。
US6854067B1 CLAIM 13 . In a microcontroller , a system comprising : a bus ; a processor coupled to said bus ; a power on reset circuit (それぞれダイオード) , said processor and said power on reset circuit coupled to said bus and interconnectedly coupled with said processor via said bus ; and a switched mode pump power supply interconnectedly coupled with said power on reset circuit and responsive to signals therefrom wherein said system executes a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state (ロック) to said microcontroller from said switched mode pump power supply ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor via said bus ; e) controlling certain functions of said microcontroller according to said suitability status ; and f) dynamically programming said power on reset circuit via said bus .	JPH06318160A CLAIM 1 【請求項１】二重化プロセッサ・システムにおいて、両系の電源部（５ 1 , ５ 2 ）から第１のダイオードの組（８ 1 , ８ 2 ）および第２のダイオードの組（９ 1 , ９ 2 ）を介して両系のシステム・クロック (power state, power state condition, power state condition signals, optimal power state) 発振部（１ 1 , １ 2 ）と制御部（２ 1 , ２ 2 ）にそれぞれ電源を供給し、両系のメイン・メモリ（３ 1 , ３ 2 ）をマスタ・スレーブ運転して内容を一致させ、両系のチャネル・コントローラ（４ 1 , ４ 2 ）をマスタ・スレーブ運転して接続先を一致させ、両系の電源監視部（６ 1 , ６ 2 ）がそれぞれ自系と他系の電源断を監視してそれぞれの電源断を示す信号を発生するとともに、現用系電源断時、現用系制御部が自系電源断に基づいてマイクロ・プログラムに制御を移して、現用系制御部の内部レジスタの内容を予備系制御部へ転送し、該転送終了後、自系を予備系に他系を現用系にそれぞれ設定して、他系を起動するとともに自系を停止状態に遷移し、起動された新現用系制御部が、両系のメイン・メモリおよびチャネル・コントローラのマスタ・スレーブの関係を構成したのち、プログラムに制御を移すことによって、中断点再開を行うことを特徴とする二重化プロセッサ・システムの系構成制御方式。 JPH06318160A CLAIM 3 【請求項３】請求項１または２に記載の二重化プロセッサ・システムの系構成制御方式において、両系の電源部（５ 1 , ５ 2 ）からそれぞれダイオード (reset circuit) （１０ 1 , １０ 2 ）を介して両系のシステム・クロック発振部（１ 1 , １ 2 ）と制御部（２ 1 , ２ 2 ）に並列に電源を供給するようにしたことを特徴とする二重化プロセッサ・システムの系構成制御方式。
US6854067B1 CLAIM 14 . The system as recited in claim 13 , wherein said b) and said c) of said method are accomplished by said power on reset circuit (それぞれダイオード) .	JPH06318160A CLAIM 3 【請求項３】請求項１または２に記載の二重化プロセッサ・システムの系構成制御方式において、両系の電源部（５ 1 , ５ 2 ）からそれぞれダイオード (reset circuit) （１０ 1 , １０ 2 ）を介して両系のシステム・クロック発振部（１ 1 , １ 2 ）と制御部（２ 1 , ２ 2 ）に並列に電源を供給するようにしたことを特徴とする二重化プロセッサ・システムの系構成制御方式。
US6854067B1 CLAIM 15 . The system as recited in claim 14 , wherein said b) of said method further comprises sensing a common supply voltage , wherein said common supply voltage is the voltage of said power state (ロック) .	JPH06318160A CLAIM 1 【請求項１】二重化プロセッサ・システムにおいて、両系の電源部（５ 1 , ５ 2 ）から第１のダイオードの組（８ 1 , ８ 2 ）および第２のダイオードの組（９ 1 , ９ 2 ）を介して両系のシステム・クロック (power state, power state condition, power state condition signals, optimal power state) 発振部（１ 1 , １ 2 ）と制御部（２ 1 , ２ 2 ）にそれぞれ電源を供給し、両系のメイン・メモリ（３ 1 , ３ 2 ）をマスタ・スレーブ運転して内容を一致させ、両系のチャネル・コントローラ（４ 1 , ４ 2 ）をマスタ・スレーブ運転して接続先を一致させ、両系の電源監視部（６ 1 , ６ 2 ）がそれぞれ自系と他系の電源断を監視してそれぞれの電源断を示す信号を発生するとともに、現用系電源断時、現用系制御部が自系電源断に基づいてマイクロ・プログラムに制御を移して、現用系制御部の内部レジスタの内容を予備系制御部へ転送し、該転送終了後、自系を予備系に他系を現用系にそれぞれ設定して、他系を起動するとともに自系を停止状態に遷移し、起動された新現用系制御部が、両系のメイン・メモリおよびチャネル・コントローラのマスタ・スレーブの関係を構成したのち、プログラムに制御を移すことによって、中断点再開を行うことを特徴とする二重化プロセッサ・システムの系構成制御方式。
US6854067B1 CLAIM 16 . The system as recited in claim 15 , wherein said c) further comprises : c1) generating a precision reference voltage , said precision reference voltage independent of said common supply voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state (ロック) condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	JPH06318160A CLAIM 1 【請求項１】二重化プロセッサ・システムにおいて、両系の電源部（５ 1 , ５ 2 ）から第１のダイオードの組（８ 1 , ８ 2 ）および第２のダイオードの組（９ 1 , ９ 2 ）を介して両系のシステム・クロック (power state, power state condition, power state condition signals, optimal power state) 発振部（１ 1 , １ 2 ）と制御部（２ 1 , ２ 2 ）にそれぞれ電源を供給し、両系のメイン・メモリ（３ 1 , ３ 2 ）をマスタ・スレーブ運転して内容を一致させ、両系のチャネル・コントローラ（４ 1 , ４ 2 ）をマスタ・スレーブ運転して接続先を一致させ、両系の電源監視部（６ 1 , ６ 2 ）がそれぞれ自系と他系の電源断を監視してそれぞれの電源断を示す信号を発生するとともに、現用系電源断時、現用系制御部が自系電源断に基づいてマイクロ・プログラムに制御を移して、現用系制御部の内部レジスタの内容を予備系制御部へ転送し、該転送終了後、自系を予備系に他系を現用系にそれぞれ設定して、他系を起動するとともに自系を停止状態に遷移し、起動された新現用系制御部が、両系のメイン・メモリおよびチャネル・コントローラのマスタ・スレーブの関係を構成したのち、プログラムに制御を移すことによって、中断点再開を行うことを特徴とする二重化プロセッサ・システムの系構成制御方式。
US6854067B1 CLAIM 18 . The system as recited in claim 17 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state (ロック) corresponding to said status ; f3) programmatically calculating an optimal value for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	JPH06318160A CLAIM 1 【請求項１】二重化プロセッサ・システムにおいて、両系の電源部（５ 1 , ５ 2 ）から第１のダイオードの組（８ 1 , ８ 2 ）および第２のダイオードの組（９ 1 , ９ 2 ）を介して両系のシステム・クロック (power state, power state condition, power state condition signals, optimal power state) 発振部（１ 1 , １ 2 ）と制御部（２ 1 , ２ 2 ）にそれぞれ電源を供給し、両系のメイン・メモリ（３ 1 , ３ 2 ）をマスタ・スレーブ運転して内容を一致させ、両系のチャネル・コントローラ（４ 1 , ４ 2 ）をマスタ・スレーブ運転して接続先を一致させ、両系の電源監視部（６ 1 , ６ 2 ）がそれぞれ自系と他系の電源断を監視してそれぞれの電源断を示す信号を発生するとともに、現用系電源断時、現用系制御部が自系電源断に基づいてマイクロ・プログラムに制御を移して、現用系制御部の内部レジスタの内容を予備系制御部へ転送し、該転送終了後、自系を予備系に他系を現用系にそれぞれ設定して、他系を起動するとともに自系を停止状態に遷移し、起動された新現用系制御部が、両系のメイン・メモリおよびチャネル・コントローラのマスタ・スレーブの関係を構成したのち、プログラムに制御を移すことによって、中断点再開を行うことを特徴とする二重化プロセッサ・システムの系構成制御方式。
US6854067B1 CLAIM 20 . In a microcontroller having a power on reset circuit (それぞれダイオード) interconnected with a processor a method of dynamically controlling said power state (ロック) , said method comprising : a) ascertaining a power state powered by a switched mode pump power supply , said switched mode pump power supply interconnected with and responsive to control by said power on reset circuit ; b) programmatically determining desired changes to said power state ; c) intercommunicating between said processor and said power on reset circuit ; d) adjusting said power on reset circuit corresponding to said desired changes to said power state ; e) controlling said switched mode pump power supply according to said d) ; and f) repeating said a) through e) .	JPH06318160A CLAIM 1 【請求項１】二重化プロセッサ・システムにおいて、両系の電源部（５ 1 , ５ 2 ）から第１のダイオードの組（８ 1 , ８ 2 ）および第２のダイオードの組（９ 1 , ９ 2 ）を介して両系のシステム・クロック (power state, power state condition, power state condition signals, optimal power state) 発振部（１ 1 , １ 2 ）と制御部（２ 1 , ２ 2 ）にそれぞれ電源を供給し、両系のメイン・メモリ（３ 1 , ３ 2 ）をマスタ・スレーブ運転して内容を一致させ、両系のチャネル・コントローラ（４ 1 , ４ 2 ）をマスタ・スレーブ運転して接続先を一致させ、両系の電源監視部（６ 1 , ６ 2 ）がそれぞれ自系と他系の電源断を監視してそれぞれの電源断を示す信号を発生するとともに、現用系電源断時、現用系制御部が自系電源断に基づいてマイクロ・プログラムに制御を移して、現用系制御部の内部レジスタの内容を予備系制御部へ転送し、該転送終了後、自系を予備系に他系を現用系にそれぞれ設定して、他系を起動するとともに自系を停止状態に遷移し、起動された新現用系制御部が、両系のメイン・メモリおよびチャネル・コントローラのマスタ・スレーブの関係を構成したのち、プログラムに制御を移すことによって、中断点再開を行うことを特徴とする二重化プロセッサ・システムの系構成制御方式。 JPH06318160A CLAIM 3 【請求項３】請求項１または２に記載の二重化プロセッサ・システムの系構成制御方式において、両系の電源部（５ 1 , ５ 2 ）からそれぞれダイオード (reset circuit) （１０ 1 , １０ 2 ）を介して両系のシステム・クロック発振部（１ 1 , １ 2 ）と制御部（２ 1 , ２ 2 ）に並列に電源を供給するようにしたことを特徴とする二重化プロセッサ・システムの系構成制御方式。

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	EP0566395A1 Filed: 1993-04-15 Issued: 1993-10-20 Drive control system for microprocessor with conditional power saving (Original Assignee) Dia Semicon Systems Inc (Current Assignee) Dia Semicon Systems Inc Osamu Ikeda
US6854067B1 CLAIM 1 . In a microcontroller with an embedded processor , a switched mode pump power supply and power on reset circuit , a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state (lower limit) to said microcontroller from said switched mode pump power supply , wherein said processor and said power on reset circuit are interconnectedly coupled , and wherein said switched mode pump power supply is interconnectedly coupled with said power on reset circuit and responsive to signals therefrom ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor ; e) controlling certain functions of said microcontroller accordingly .	EP0566395A1 CLAIM 8 . A power saving control system as claimed in claim 7 , wherein said second means varies said given learning period within a range defined by upper and lower limit (power state, power state condition) values .
US6854067B1 CLAIM 5 . The method as recited in claim 4 , wherein said b) further comprises sensing a common supply voltage , wherein said common supply voltage is the voltage of said power state (lower limit) .	EP0566395A1 CLAIM 8 . A power saving control system as claimed in claim 7 , wherein said second means varies said given learning period within a range defined by upper and lower limit (power state, power state condition) values .
US6854067B1 CLAIM 6 . The method as recited in claim 5 , wherein said c) further comprises : c1) generating a precision reference voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one (predetermined criterion) of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state (lower limit) condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	EP0566395A1 CLAIM 1 . A drive control system for a microprocessor comprising : a drive condition varying means for varying a drive condition of said microprocessor for varying a processing speed and a power consumption in mutually related manner ; an operational state dependent control means for monitoring operational state of said microprocessor and controlling said drive condition varying means for adapting the processing speed to the operational state ; and a temperature dependent control means for monitoring a temperature condition of said mi- croprocessorfor overriding said operational state dependent control means for lowering the power consumption of said microprocessor when the temperature condition of the microprocessor higher than a predetermined criterion (comparisons comparing one) temperature is detected . EP0566395A1 CLAIM 8 . A power saving control system as claimed in claim 7 , wherein said second means varies said given learning period within a range defined by upper and lower limit (power state, power state condition) values .
US6854067B1 CLAIM 11 . The method as recited in claim 10 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state (lower limit) corresponding to said status ; f3) programmatically calculating an optimal value (high power) for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	EP0566395A1 CLAIM 4 . A power saving control system for a computer system including a CPU , comprising : first means for selectively operating said CPU in a first mode with relatively high performance and high power (optimal value) consumption and a second mode with relatively low performance and low power consumption ; second means for monitoring addresses accessed by said CPU over a given period in order to detect a predetermined operational state of said CPU , in which only specific address group is repeatedly accessed ; third means associated with said first means for normally operating said first means in said first mode and responsive to said second means detecting said predetermined operational state , for operating said first means in said second mode as long as said predetermined operational state is maintained ; and fourth means for monitoring a temperature condition of said microprocessor for overriding said third means for lowering the power consumption of said microprocessor irrespective of the operational state of said microprocessor when the temperature condition of the microprocessor higher than a predetermined criterion temperature is detected . EP0566395A1 CLAIM 8 . A power saving control system as claimed in claim 7 , wherein said second means varies said given learning period within a range defined by upper and lower limit (power state, power state condition) values .
US6854067B1 CLAIM 12 . The method as recited in claim 11 , wherein said f4) further comprises : communicating each said optimal value (high power) to said power supply scaler via said bus ; registering each said optimal value with said matrix of multiplexers and registers ; commanding said matrix of multiplexers and registers to change said independent multiple of said common supply voltage to correspond with said optimal value ; and monitoring said matrix of multiplexers and registers .	EP0566395A1 CLAIM 4 . A power saving control system for a computer system including a CPU , comprising : first means for selectively operating said CPU in a first mode with relatively high performance and high power (optimal value) consumption and a second mode with relatively low performance and low power consumption ; second means for monitoring addresses accessed by said CPU over a given period in order to detect a predetermined operational state of said CPU , in which only specific address group is repeatedly accessed ; third means associated with said first means for normally operating said first means in said first mode and responsive to said second means detecting said predetermined operational state , for operating said first means in said second mode as long as said predetermined operational state is maintained ; and fourth means for monitoring a temperature condition of said microprocessor for overriding said third means for lowering the power consumption of said microprocessor irrespective of the operational state of said microprocessor when the temperature condition of the microprocessor higher than a predetermined criterion temperature is detected .
US6854067B1 CLAIM 13 . In a microcontroller , a system comprising : a bus ; a processor coupled to said bus ; a power on reset circuit , said processor and said power on reset circuit coupled to said bus and interconnectedly coupled with said processor via said bus ; and a switched mode pump power supply interconnectedly coupled with said power on reset circuit and responsive to signals therefrom wherein said system executes a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state (lower limit) to said microcontroller from said switched mode pump power supply ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor via said bus ; e) controlling certain functions of said microcontroller according to said suitability status ; and f) dynamically programming said power on reset circuit via said bus .	EP0566395A1 CLAIM 8 . A power saving control system as claimed in claim 7 , wherein said second means varies said given learning period within a range defined by upper and lower limit (power state, power state condition) values .
US6854067B1 CLAIM 15 . The system as recited in claim 14 , wherein said b) of said method further comprises sensing a common supply voltage , wherein said common supply voltage is the voltage of said power state (lower limit) .	EP0566395A1 CLAIM 8 . A power saving control system as claimed in claim 7 , wherein said second means varies said given learning period within a range defined by upper and lower limit (power state, power state condition) values .
US6854067B1 CLAIM 16 . The system as recited in claim 15 , wherein said c) further comprises : c1) generating a precision reference voltage , said precision reference voltage independent of said common supply voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one (predetermined criterion) of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state (lower limit) condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	EP0566395A1 CLAIM 1 . A drive control system for a microprocessor comprising : a drive condition varying means for varying a drive condition of said microprocessor for varying a processing speed and a power consumption in mutually related manner ; an operational state dependent control means for monitoring operational state of said microprocessor and controlling said drive condition varying means for adapting the processing speed to the operational state ; and a temperature dependent control means for monitoring a temperature condition of said mi- croprocessorfor overriding said operational state dependent control means for lowering the power consumption of said microprocessor when the temperature condition of the microprocessor higher than a predetermined criterion (comparisons comparing one) temperature is detected . EP0566395A1 CLAIM 8 . A power saving control system as claimed in claim 7 , wherein said second means varies said given learning period within a range defined by upper and lower limit (power state, power state condition) values .
US6854067B1 CLAIM 18 . The system as recited in claim 17 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state (lower limit) corresponding to said status ; f3) programmatically calculating an optimal value (high power) for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	EP0566395A1 CLAIM 4 . A power saving control system for a computer system including a CPU , comprising : first means for selectively operating said CPU in a first mode with relatively high performance and high power (optimal value) consumption and a second mode with relatively low performance and low power consumption ; second means for monitoring addresses accessed by said CPU over a given period in order to detect a predetermined operational state of said CPU , in which only specific address group is repeatedly accessed ; third means associated with said first means for normally operating said first means in said first mode and responsive to said second means detecting said predetermined operational state , for operating said first means in said second mode as long as said predetermined operational state is maintained ; and fourth means for monitoring a temperature condition of said microprocessor for overriding said third means for lowering the power consumption of said microprocessor irrespective of the operational state of said microprocessor when the temperature condition of the microprocessor higher than a predetermined criterion temperature is detected . EP0566395A1 CLAIM 8 . A power saving control system as claimed in claim 7 , wherein said second means varies said given learning period within a range defined by upper and lower limit (power state, power state condition) values .
US6854067B1 CLAIM 19 . The method as recited in claim 18 , wherein said f4) further comprises : communicating each said optimal value (high power) to said power supply scaler via said bus ; registering each said optimal value with said matrix of multiplexers and registers ; commanding said matrix of multiplexers and registers to change said independent multiple of said common supply voltage to correspond with said optimal value ; and monitoring said matrix of multiplexers and registers .	EP0566395A1 CLAIM 4 . A power saving control system for a computer system including a CPU , comprising : first means for selectively operating said CPU in a first mode with relatively high performance and high power (optimal value) consumption and a second mode with relatively low performance and low power consumption ; second means for monitoring addresses accessed by said CPU over a given period in order to detect a predetermined operational state of said CPU , in which only specific address group is repeatedly accessed ; third means associated with said first means for normally operating said first means in said first mode and responsive to said second means detecting said predetermined operational state , for operating said first means in said second mode as long as said predetermined operational state is maintained ; and fourth means for monitoring a temperature condition of said microprocessor for overriding said third means for lowering the power consumption of said microprocessor irrespective of the operational state of said microprocessor when the temperature condition of the microprocessor higher than a predetermined criterion temperature is detected .
US6854067B1 CLAIM 20 . In a microcontroller having a power on reset circuit interconnected with a processor a method of dynamically controlling said power state (lower limit) , said method comprising : a) ascertaining a power state powered by a switched mode pump power supply , said switched mode pump power supply interconnected with and responsive to control by said power on reset circuit ; b) programmatically determining desired changes to said power state ; c) intercommunicating between said processor and said power on reset circuit ; d) adjusting said power on reset circuit corresponding to said desired changes to said power state ; e) controlling said switched mode pump power supply according to said d) ; and f) repeating said a) through e) .	EP0566395A1 CLAIM 8 . A power saving control system as claimed in claim 7 , wherein said second means varies said given learning period within a range defined by upper and lower limit (power state, power state condition) values .

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	US5376834A Filed: 1993-03-05 Issued: 1994-12-27 Initialization circuit for automatically establishing an output to zero or desired reference potential (Original Assignee) SGS Thomson Microelectronics Inc (Current Assignee) STMicroelectronics lnc USA Francesco Carobolante
US6854067B1 CLAIM 6 . The method as recited in claim 5 , wherein said c) further comprises : c1) generating a precision reference voltage (said switch) ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US5376834A CLAIM 4 . The circuit of claim 2 wherein said flip-flop has a reset input for resetting its state at the beginning of the initialization period : and wherein the output of said flip-flop is also connected to the switch control input of said switch (precision reference voltage) , so that said switch connects the input of the analog circuit to the reference potential during the initializing period , and connects the input of the analog circuit to the analog input responsive to said flip-flop changing states .
US6854067B1 CLAIM 7 . The method as recited in claim 6 , wherein said precision reference voltage (said switch) is independent of said common supply voltage .	US5376834A CLAIM 4 . The circuit of claim 2 wherein said flip-flop has a reset input for resetting its state at the beginning of the initialization period : and wherein the output of said flip-flop is also connected to the switch control input of said switch (precision reference voltage) , so that said switch connects the input of the analog circuit to the reference potential during the initializing period , and connects the input of the analog circuit to the analog input responsive to said flip-flop changing states .
US6854067B1 CLAIM 9 . The method as recited in claim 8 , wherein said b2) is performed by a power supply scaler (phase locked loop circuit) , and wherein said power supply scaler comprises : a) a divider of said common supply voltage ; b) a matrix of multiplexers and registers , and c) an interconnection to said bus .	US5376834A CLAIM 14 . An initializing phase locked loop circuit (power supply scaler) , comprising : a phase locked loop , of the type having : a plurality of input nodes , each for receiving signals to be summed , a summing amplifier having a first input coupled to said plurality of input nodes , having a second input , and having an output , an operational amplifier having a first input connected to a first reference potential , a second input , add an output , and feedback elements connected between the output and the second input of the operational amplifier to provide negative feedback thereto ; a first switch , having a control input , and operative during an initializing period to disconnect the feedback elements from the integrator circuit ; a plurality of second switches , each having a control input , and each operative during the initializing period to connect each of the plurality of input nodes to a second reference potential ; a resistor ladder having a plurality of voltage step output lines along its length ; a multiplexer having input terminals connected to the voltage step output lines of said resistor ladder , having a control input , and having an output connected to the second input of said summing amplifier to provide a bias reference thereto ; a counter having a clock input and a count output , said count output being connected to the control input of said multiplexer so that said multiplexer sequentially selects , among the steps of said resistor ladder responsive to an advance of the count output ; a control circuit having an input coupled to the output of said operational amplifier , having a first output coupled to the control inputs of said first switch and of said plurality of second switches , and having a second output coupled to the clock input of said counter , for clocking said counter responsive to the output of said operational amplifier not having reached a predetermined value , and for , responsive to the output of said operational amplifier reaching the predetermined value , controlling said first switch to connect said feedback elements to said operational amplifier and controlling said plurality of second switches to connect said input nodes to receive input signals .
US6854067B1 CLAIM 12 . The method as recited in claim 11 , wherein said f4) further comprises : communicating each said optimal value to said power supply scaler (phase locked loop circuit) via said bus ; registering each said optimal value with said matrix of multiplexers and registers ; commanding said matrix of multiplexers and registers to change said independent multiple of said common supply voltage to correspond with said optimal value ; and monitoring said matrix of multiplexers and registers .	US5376834A CLAIM 14 . An initializing phase locked loop circuit (power supply scaler) , comprising : a phase locked loop , of the type having : a plurality of input nodes , each for receiving signals to be summed , a summing amplifier having a first input coupled to said plurality of input nodes , having a second input , and having an output , an operational amplifier having a first input connected to a first reference potential , a second input , add an output , and feedback elements connected between the output and the second input of the operational amplifier to provide negative feedback thereto ; a first switch , having a control input , and operative during an initializing period to disconnect the feedback elements from the integrator circuit ; a plurality of second switches , each having a control input , and each operative during the initializing period to connect each of the plurality of input nodes to a second reference potential ; a resistor ladder having a plurality of voltage step output lines along its length ; a multiplexer having input terminals connected to the voltage step output lines of said resistor ladder , having a control input , and having an output connected to the second input of said summing amplifier to provide a bias reference thereto ; a counter having a clock input and a count output , said count output being connected to the control input of said multiplexer so that said multiplexer sequentially selects , among the steps of said resistor ladder responsive to an advance of the count output ; a control circuit having an input coupled to the output of said operational amplifier , having a first output coupled to the control inputs of said first switch and of said plurality of second switches , and having a second output coupled to the clock input of said counter , for clocking said counter responsive to the output of said operational amplifier not having reached a predetermined value , and for , responsive to the output of said operational amplifier reaching the predetermined value , controlling said first switch to connect said feedback elements to said operational amplifier and controlling said plurality of second switches to connect said input nodes to receive input signals .
US6854067B1 CLAIM 16 . The system as recited in claim 15 , wherein said c) further comprises : c1) generating a precision reference voltage (said switch) , said precision reference voltage independent of said common supply voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US5376834A CLAIM 4 . The circuit of claim 2 wherein said flip-flop has a reset input for resetting its state at the beginning of the initialization period : and wherein the output of said flip-flop is also connected to the switch control input of said switch (precision reference voltage) , so that said switch connects the input of the analog circuit to the reference potential during the initializing period , and connects the input of the analog circuit to the analog input responsive to said flip-flop changing states .
US6854067B1 CLAIM 17 . The system as recited in claim 16 , wherein said b2) is performed by a power supply scaler (phase locked loop circuit) , wherein said power supply scaler comprises : a) a divider of said common supply voltage ; b) a matrix of multiplexers and registers , and c) an interconnection to said bus .	US5376834A CLAIM 14 . An initializing phase locked loop circuit (power supply scaler) , comprising : a phase locked loop , of the type having : a plurality of input nodes , each for receiving signals to be summed , a summing amplifier having a first input coupled to said plurality of input nodes , having a second input , and having an output , an operational amplifier having a first input connected to a first reference potential , a second input , add an output , and feedback elements connected between the output and the second input of the operational amplifier to provide negative feedback thereto ; a first switch , having a control input , and operative during an initializing period to disconnect the feedback elements from the integrator circuit ; a plurality of second switches , each having a control input , and each operative during the initializing period to connect each of the plurality of input nodes to a second reference potential ; a resistor ladder having a plurality of voltage step output lines along its length ; a multiplexer having input terminals connected to the voltage step output lines of said resistor ladder , having a control input , and having an output connected to the second input of said summing amplifier to provide a bias reference thereto ; a counter having a clock input and a count output , said count output being connected to the control input of said multiplexer so that said multiplexer sequentially selects , among the steps of said resistor ladder responsive to an advance of the count output ; a control circuit having an input coupled to the output of said operational amplifier , having a first output coupled to the control inputs of said first switch and of said plurality of second switches , and having a second output coupled to the clock input of said counter , for clocking said counter responsive to the output of said operational amplifier not having reached a predetermined value , and for , responsive to the output of said operational amplifier reaching the predetermined value , controlling said first switch to connect said feedback elements to said operational amplifier and controlling said plurality of second switches to connect said input nodes to receive input signals .
US6854067B1 CLAIM 19 . The method as recited in claim 18 , wherein said f4) further comprises : communicating each said optimal value to said power supply scaler (phase locked loop circuit) via said bus ; registering each said optimal value with said matrix of multiplexers and registers ; commanding said matrix of multiplexers and registers to change said independent multiple of said common supply voltage to correspond with said optimal value ; and monitoring said matrix of multiplexers and registers .	US5376834A CLAIM 14 . An initializing phase locked loop circuit (power supply scaler) , comprising : a phase locked loop , of the type having : a plurality of input nodes , each for receiving signals to be summed , a summing amplifier having a first input coupled to said plurality of input nodes , having a second input , and having an output , an operational amplifier having a first input connected to a first reference potential , a second input , add an output , and feedback elements connected between the output and the second input of the operational amplifier to provide negative feedback thereto ; a first switch , having a control input , and operative during an initializing period to disconnect the feedback elements from the integrator circuit ; a plurality of second switches , each having a control input , and each operative during the initializing period to connect each of the plurality of input nodes to a second reference potential ; a resistor ladder having a plurality of voltage step output lines along its length ; a multiplexer having input terminals connected to the voltage step output lines of said resistor ladder , having a control input , and having an output connected to the second input of said summing amplifier to provide a bias reference thereto ; a counter having a clock input and a count output , said count output being connected to the control input of said multiplexer so that said multiplexer sequentially selects , among the steps of said resistor ladder responsive to an advance of the count output ; a control circuit having an input coupled to the output of said operational amplifier , having a first output coupled to the control inputs of said first switch and of said plurality of second switches , and having a second output coupled to the clock input of said counter , for clocking said counter responsive to the output of said operational amplifier not having reached a predetermined value , and for , responsive to the output of said operational amplifier reaching the predetermined value , controlling said first switch to connect said feedback elements to said operational amplifier and controlling said plurality of second switches to connect said input nodes to receive input signals .

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	GB2262004A Filed: 1992-11-26 Issued: 1993-06-02 Charging batteries in portable equipment (Original Assignee) Shaye Communications Ltd (Current Assignee) Shaye Communications Ltd Peter John Sladen
US6854067B1 CLAIM 1 . In a microcontroller with an embedded processor , a switched mode pump power supply (control output) and power on reset circuit , a method of dynamically controlling a plurality of power stability functions (control means) for said microcontroller , said method comprising : a) supplying a power state (control output) to said microcontroller from said switched mode pump power supply , wherein said processor and said power on reset circuit are interconnectedly coupled , and wherein said switched mode pump power supply is interconnectedly coupled with said power on reset circuit and responsive to signals therefrom ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor ; e) controlling certain functions of said microcontroller accordingly .	GB2262004A CLAIM 2 . An electronic system as claimed in claim 1 wherein said current control means (power stability functions) comprises a microprocessor forming part of said electronic circuits , and wherein said microprocessor further carries out the existing functions of said portable equipment . GB2262004A CLAIM 3 . An electronic system as claimed in either one of claims 1 or 2 wherein the current means incorporates means for monitoring the charging voltage applied to said battery or battery pack during charging , and for generating , on a control output (mode pump power supply, power state) , a control signal indicative of the charging voltage .
US6854067B1 CLAIM 5 . The method as recited in claim 4 , wherein said b) further comprises sensing a common supply voltage , wherein said common supply voltage is the voltage of said power state (control output) .	GB2262004A CLAIM 3 . An electronic system as claimed in either one of claims 1 or 2 wherein the current means incorporates means for monitoring the charging voltage applied to said battery or battery pack during charging , and for generating , on a control output (mode pump power supply, power state) , a control signal indicative of the charging voltage .
US6854067B1 CLAIM 6 . The method as recited in claim 5 , wherein said c) further comprises : c1) generating a precision reference voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state (control output) condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	GB2262004A CLAIM 3 . An electronic system as claimed in either one of claims 1 or 2 wherein the current means incorporates means for monitoring the charging voltage applied to said battery or battery pack during charging , and for generating , on a control output (mode pump power supply, power state) , a control signal indicative of the charging voltage .
US6854067B1 CLAIM 11 . The method as recited in claim 10 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state (control output) corresponding to said status ; f3) programmatically calculating an optimal value for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	GB2262004A CLAIM 3 . An electronic system as claimed in either one of claims 1 or 2 wherein the current means incorporates means for monitoring the charging voltage applied to said battery or battery pack during charging , and for generating , on a control output (mode pump power supply, power state) , a control signal indicative of the charging voltage .
US6854067B1 CLAIM 13 . In a microcontroller , a system comprising : a bus ; a processor coupled to said bus ; a power on reset circuit , said processor and said power on reset circuit coupled to said bus and interconnectedly coupled with said processor via said bus ; and a switched mode pump power supply (control output) interconnectedly coupled with said power on reset circuit and responsive to signals therefrom wherein said system executes a method of dynamically controlling a plurality of power stability functions (control means) for said microcontroller , said method comprising : a) supplying a power state (control output) to said microcontroller from said switched mode pump power supply ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor via said bus ; e) controlling certain functions of said microcontroller according to said suitability status ; and f) dynamically programming said power on reset circuit via said bus .	GB2262004A CLAIM 2 . An electronic system as claimed in claim 1 wherein said current control means (power stability functions) comprises a microprocessor forming part of said electronic circuits , and wherein said microprocessor further carries out the existing functions of said portable equipment . GB2262004A CLAIM 3 . An electronic system as claimed in either one of claims 1 or 2 wherein the current means incorporates means for monitoring the charging voltage applied to said battery or battery pack during charging , and for generating , on a control output (mode pump power supply, power state) , a control signal indicative of the charging voltage .
US6854067B1 CLAIM 15 . The system as recited in claim 14 , wherein said b) of said method further comprises sensing a common supply voltage , wherein said common supply voltage is the voltage of said power state (control output) .	GB2262004A CLAIM 3 . An electronic system as claimed in either one of claims 1 or 2 wherein the current means incorporates means for monitoring the charging voltage applied to said battery or battery pack during charging , and for generating , on a control output (mode pump power supply, power state) , a control signal indicative of the charging voltage .
US6854067B1 CLAIM 16 . The system as recited in claim 15 , wherein said c) further comprises : c1) generating a precision reference voltage , said precision reference voltage independent of said common supply voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state (control output) condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	GB2262004A CLAIM 3 . An electronic system as claimed in either one of claims 1 or 2 wherein the current means incorporates means for monitoring the charging voltage applied to said battery or battery pack during charging , and for generating , on a control output (mode pump power supply, power state) , a control signal indicative of the charging voltage .
US6854067B1 CLAIM 18 . The system as recited in claim 17 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state (control output) corresponding to said status ; f3) programmatically calculating an optimal value for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	GB2262004A CLAIM 3 . An electronic system as claimed in either one of claims 1 or 2 wherein the current means incorporates means for monitoring the charging voltage applied to said battery or battery pack during charging , and for generating , on a control output (mode pump power supply, power state) , a control signal indicative of the charging voltage .
US6854067B1 CLAIM 20 . In a microcontroller having a power on reset circuit interconnected with a processor a method of dynamically controlling said power state (control output) , said method comprising : a) ascertaining a power state powered by a switched mode pump power supply (control output) , said switched mode pump power supply interconnected with and responsive to control by said power on reset circuit ; b) programmatically determining desired changes to said power state ; c) intercommunicating between said processor and said power on reset circuit ; d) adjusting said power on reset circuit corresponding to said desired changes to said power state ; e) controlling said switched mode pump power supply according to said d) ; and f) repeating said a) through e) .	GB2262004A CLAIM 3 . An electronic system as claimed in either one of claims 1 or 2 wherein the current means incorporates means for monitoring the charging voltage applied to said battery or battery pack during charging , and for generating , on a control output (mode pump power supply, power state) , a control signal indicative of the charging voltage .

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	EP0544362A2 Filed: 1992-11-19 Issued: 1993-06-02 Electronic circuit with programmable gradual power consumption control (Original Assignee) Koninklijke Philips NV (Current Assignee) Koninklijke Philips NV Edward Allyn c/o Int. Octrooiburaau B.V. Burton, Farrell c/o Int. Octrooiburaau B.V. Ostler
US6854067B1 CLAIM 1 . In a microcontroller with an embedded processor , a switched mode pump power supply and power on reset circuit , a method of dynamically controlling a plurality of power stability functions (control means) for said microcontroller , said method comprising : a) supplying a power state (second power supply, d log) to said microcontroller from said switched mode pump power supply , wherein said processor and said power on reset circuit are interconnectedly coupled , and wherein said switched mode pump power supply is interconnectedly coupled with said power on reset circuit and responsive to signals therefrom ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor ; e) controlling certain functions of said microcontroller accordingly .	EP0544362A2 CLAIM 1 . An electronic device comprising : first and second power supply (optimal power, power state, optimal power state) nodes for receiving first and second power supply voltages , respectively ; a circuit coupled between the first and second power supply nodes ; user-programmable power control means (power stability functions) for incrementally modifying power consumption by the circuit under control of a program signal applied to the power control means . EP0544362A2 CLAIM 9 . The device of claim 1 wherein the circuit comprises wired log (optimal power, power state, optimal power state) ic circuitry with a plurality of current sources , each of which is incrementally and independently controlled by the programmable power control means .
US6854067B1 CLAIM 5 . The method as recited in claim 4 , wherein said b) further comprises sensing a common supply voltage , wherein said common supply voltage is the voltage of said power state (second power supply, d log) .	EP0544362A2 CLAIM 1 . An electronic device comprising : first and second power supply (optimal power, power state, optimal power state) nodes for receiving first and second power supply voltages , respectively ; a circuit coupled between the first and second power supply nodes ; user-programmable power control means for incrementally modifying power consumption by the circuit under control of a program signal applied to the power control means . EP0544362A2 CLAIM 9 . The device of claim 1 wherein the circuit comprises wired log (optimal power, power state, optimal power state) ic circuitry with a plurality of current sources , each of which is incrementally and independently controlled by the programmable power control means .
US6854067B1 CLAIM 6 . The method as recited in claim 5 , wherein said c) further comprises : c1) generating a precision reference voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state (second power supply, d log) condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	EP0544362A2 CLAIM 1 . An electronic device comprising : first and second power supply (optimal power, power state, optimal power state) nodes for receiving first and second power supply voltages , respectively ; a circuit coupled between the first and second power supply nodes ; user-programmable power control means for incrementally modifying power consumption by the circuit under control of a program signal applied to the power control means . EP0544362A2 CLAIM 9 . The device of claim 1 wherein the circuit comprises wired log (optimal power, power state, optimal power state) ic circuitry with a plurality of current sources , each of which is incrementally and independently controlled by the programmable power control means .
US6854067B1 CLAIM 11 . The method as recited in claim 10 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power (second power supply, d log) state corresponding to said status ; f3) programmatically calculating an optimal value for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	EP0544362A2 CLAIM 1 . An electronic device comprising : first and second power supply (optimal power, power state, optimal power state) nodes for receiving first and second power supply voltages , respectively ; a circuit coupled between the first and second power supply nodes ; user-programmable power control means for incrementally modifying power consumption by the circuit under control of a program signal applied to the power control means . EP0544362A2 CLAIM 9 . The device of claim 1 wherein the circuit comprises wired log (optimal power, power state, optimal power state) ic circuitry with a plurality of current sources , each of which is incrementally and independently controlled by the programmable power control means .
US6854067B1 CLAIM 13 . In a microcontroller , a system comprising : a bus ; a processor coupled to said bus ; a power on reset circuit , said processor and said power on reset circuit coupled to said bus and interconnectedly coupled with said processor via said bus ; and a switched mode pump power supply interconnectedly coupled with said power on reset circuit and responsive to signals therefrom wherein said system executes a method of dynamically controlling a plurality of power stability functions (control means) for said microcontroller , said method comprising : a) supplying a power state (second power supply, d log) to said microcontroller from said switched mode pump power supply ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor via said bus ; e) controlling certain functions of said microcontroller according to said suitability status ; and f) dynamically programming said power on reset circuit via said bus .	EP0544362A2 CLAIM 1 . An electronic device comprising : first and second power supply (optimal power, power state, optimal power state) nodes for receiving first and second power supply voltages , respectively ; a circuit coupled between the first and second power supply nodes ; user-programmable power control means (power stability functions) for incrementally modifying power consumption by the circuit under control of a program signal applied to the power control means . EP0544362A2 CLAIM 9 . The device of claim 1 wherein the circuit comprises wired log (optimal power, power state, optimal power state) ic circuitry with a plurality of current sources , each of which is incrementally and independently controlled by the programmable power control means .
US6854067B1 CLAIM 15 . The system as recited in claim 14 , wherein said b) of said method further comprises sensing a common supply voltage , wherein said common supply voltage is the voltage of said power state (second power supply, d log) .	EP0544362A2 CLAIM 1 . An electronic device comprising : first and second power supply (optimal power, power state, optimal power state) nodes for receiving first and second power supply voltages , respectively ; a circuit coupled between the first and second power supply nodes ; user-programmable power control means for incrementally modifying power consumption by the circuit under control of a program signal applied to the power control means . EP0544362A2 CLAIM 9 . The device of claim 1 wherein the circuit comprises wired log (optimal power, power state, optimal power state) ic circuitry with a plurality of current sources , each of which is incrementally and independently controlled by the programmable power control means .
US6854067B1 CLAIM 16 . The system as recited in claim 15 , wherein said c) further comprises : c1) generating a precision reference voltage , said precision reference voltage independent of said common supply voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state (second power supply, d log) condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	EP0544362A2 CLAIM 1 . An electronic device comprising : first and second power supply (optimal power, power state, optimal power state) nodes for receiving first and second power supply voltages , respectively ; a circuit coupled between the first and second power supply nodes ; user-programmable power control means for incrementally modifying power consumption by the circuit under control of a program signal applied to the power control means . EP0544362A2 CLAIM 9 . The device of claim 1 wherein the circuit comprises wired log (optimal power, power state, optimal power state) ic circuitry with a plurality of current sources , each of which is incrementally and independently controlled by the programmable power control means .
US6854067B1 CLAIM 18 . The system as recited in claim 17 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power (second power supply, d log) state corresponding to said status ; f3) programmatically calculating an optimal value for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	EP0544362A2 CLAIM 1 . An electronic device comprising : first and second power supply (optimal power, power state, optimal power state) nodes for receiving first and second power supply voltages , respectively ; a circuit coupled between the first and second power supply nodes ; user-programmable power control means for incrementally modifying power consumption by the circuit under control of a program signal applied to the power control means . EP0544362A2 CLAIM 9 . The device of claim 1 wherein the circuit comprises wired log (optimal power, power state, optimal power state) ic circuitry with a plurality of current sources , each of which is incrementally and independently controlled by the programmable power control means .
US6854067B1 CLAIM 20 . In a microcontroller having a power on reset circuit interconnected with a processor a method of dynamically controlling said power state (second power supply, d log) , said method comprising : a) ascertaining a power state powered by a switched mode pump power supply , said switched mode pump power supply interconnected with and responsive to control by said power on reset circuit ; b) programmatically determining desired changes to said power state ; c) intercommunicating between said processor and said power on reset circuit ; d) adjusting said power on reset circuit corresponding to said desired changes to said power state ; e) controlling said switched mode pump power supply according to said d) ; and f) repeating said a) through e) .	EP0544362A2 CLAIM 1 . An electronic device comprising : first and second power supply (optimal power, power state, optimal power state) nodes for receiving first and second power supply voltages , respectively ; a circuit coupled between the first and second power supply nodes ; user-programmable power control means for incrementally modifying power consumption by the circuit under control of a program signal applied to the power control means . EP0544362A2 CLAIM 9 . The device of claim 1 wherein the circuit comprises wired log (optimal power, power state, optimal power state) ic circuitry with a plurality of current sources , each of which is incrementally and independently controlled by the programmable power control means .

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	US5304955A Filed: 1992-11-19 Issued: 1994-04-19 Voltage controlled oscillator operating with digital controlled loads in a phase lock loop (Original Assignee) Motorola Solutions Inc (Current Assignee) Motorola Solutions Inc Ahmad H. Atriss, Benjamin C. Peterson, Lanny L. Parker
US6854067B1 CLAIM 1 . In a microcontroller with an embedded processor , a switched mode pump power supply (load circuit) and power on reset circuit (second control terminal) , a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state (second power supply, predetermined level) to said microcontroller from said switched mode pump power supply , wherein said processor and said power on reset circuit are interconnectedly coupled , and wherein said switched mode pump power supply is interconnectedly coupled with said power on reset circuit and responsive to signals therefrom ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor ; e) controlling certain functions of said microcontroller accordingly .	US5304955A CLAIM 1 . A phase lock loop , comprising : first means for comparing a phase difference of first and second input signals and generating an output signal to charge and discharge a loop node ; a VCO having an input coupled for receiving said output signal of said first means and having an output for providing an oscillator signal ; second means for dividing down said oscillator signal into first and second divided oscillator signals , said first divided oscillator signal operating as said second input signal of said first means ; third means coupled for receiving said second divided oscillator signal and said first input signal and generating a first load control signal when said second divided oscillator signal changes logic state more than a predetermined number of times during a first logic state of said first input signal ; and a first load circuit (mode pump power supply, power supply scaler) coupled to said output of said VCO and operating in response to said first load control signal to increase loading at said output of said VCO . US5304955A CLAIM 6 . The oscillator of claim 5 wherein said first loading circuit includes : a first transmission gate having first and second conduction terminals and first and second control terminal (reset circuit) s , said first control terminal receiving said first load control signal , said first conduction terminal being coupled to said output of said first inverter ; a fourth inverter having an input for receiving said first load control signal and an output coupled to said second control terminal of said first transmission gate ; and a first capacitor coupled between said second conduction terminal of said first transmission gate and a power supply conductor . US5304955A CLAIM 8 . A method of controlling a maximum operating frequency of a phase lock loop , comprising the steps of : comparing a phase difference of first and second input signals and generating an output signal to charge and discharge a loop node and develop a loop node voltage ; initializing said loop node voltage to a predetermined level (optimal power, power state, optimal power state) ; generating an oscillator signal operating at a frequency determined by said loop node voltage ; dividing down said oscillator signal into first and second divided oscillator signals , said first divided oscillator signal operating as said second input signal ; generating a first load control signal when said second divided oscillator signal changes logic state more than a predetermined number of times during a first logic state of said first input signal ; and reducing said frequency of said oscillator signal in response to said first load control signal by increasing loading on said oscillator signal . US5304955A CLAIM 16 . The oscillator of claim 15 wherein said first loading circuit includes : a first transmission gate having first and second conduction terminals and first and second control terminals , said first control terminal receiving said first load control signal , said first conduction terminal being coupled to said output of said first inverter ; a fourth inverter having an input for receiving said first load control signal and an output coupled to said second control terminal of said first transmission gate ; and a first capacitor coupled between said second conduction terminal of said first transmission gate and a second power supply (optimal power, power state, optimal power state) conductor .
US6854067B1 CLAIM 2 . The method as recited in claim 1 , further comprising : f) dynamically programming said power on reset circuit (second control terminal) .	US5304955A CLAIM 6 . The oscillator of claim 5 wherein said first loading circuit includes : a first transmission gate having first and second conduction terminals and first and second control terminal (reset circuit) s , said first control terminal receiving said first load control signal , said first conduction terminal being coupled to said output of said first inverter ; a fourth inverter having an input for receiving said first load control signal and an output coupled to said second control terminal of said first transmission gate ; and a first capacitor coupled between said second conduction terminal of said first transmission gate and a power supply conductor .
US6854067B1 CLAIM 3 . The method as recited in claim 2 , wherein said power on reset circuit (second control terminal) and said processor are interconnected via a bus .	US5304955A CLAIM 6 . The oscillator of claim 5 wherein said first loading circuit includes : a first transmission gate having first and second conduction terminals and first and second control terminal (reset circuit) s , said first control terminal receiving said first load control signal , said first conduction terminal being coupled to said output of said first inverter ; a fourth inverter having an input for receiving said first load control signal and an output coupled to said second control terminal of said first transmission gate ; and a first capacitor coupled between said second conduction terminal of said first transmission gate and a power supply conductor .
US6854067B1 CLAIM 4 . The method as recited in claim 3 , wherein said b) and said c) are accomplished by said power on reset circuit (second control terminal) .	US5304955A CLAIM 6 . The oscillator of claim 5 wherein said first loading circuit includes : a first transmission gate having first and second conduction terminals and first and second control terminal (reset circuit) s , said first control terminal receiving said first load control signal , said first conduction terminal being coupled to said output of said first inverter ; a fourth inverter having an input for receiving said first load control signal and an output coupled to said second control terminal of said first transmission gate ; and a first capacitor coupled between said second conduction terminal of said first transmission gate and a power supply conductor .
US6854067B1 CLAIM 5 . The method as recited in claim 4 , wherein said b) further comprises sensing a common supply voltage , wherein said common supply voltage is the voltage of said power state (second power supply, predetermined level) .	US5304955A CLAIM 8 . A method of controlling a maximum operating frequency of a phase lock loop , comprising the steps of : comparing a phase difference of first and second input signals and generating an output signal to charge and discharge a loop node and develop a loop node voltage ; initializing said loop node voltage to a predetermined level (optimal power, power state, optimal power state) ; generating an oscillator signal operating at a frequency determined by said loop node voltage ; dividing down said oscillator signal into first and second divided oscillator signals , said first divided oscillator signal operating as said second input signal ; generating a first load control signal when said second divided oscillator signal changes logic state more than a predetermined number of times during a first logic state of said first input signal ; and reducing said frequency of said oscillator signal in response to said first load control signal by increasing loading on said oscillator signal . US5304955A CLAIM 16 . The oscillator of claim 15 wherein said first loading circuit includes : a first transmission gate having first and second conduction terminals and first and second control terminals , said first control terminal receiving said first load control signal , said first conduction terminal being coupled to said output of said first inverter ; a fourth inverter having an input for receiving said first load control signal and an output coupled to said second control terminal of said first transmission gate ; and a first capacitor coupled between said second conduction terminal of said first transmission gate and a second power supply (optimal power, power state, optimal power state) conductor .
US6854067B1 CLAIM 6 . The method as recited in claim 5 , wherein said c) further comprises : c1) generating a precision reference voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state (second power supply, predetermined level) condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US5304955A CLAIM 8 . A method of controlling a maximum operating frequency of a phase lock loop , comprising the steps of : comparing a phase difference of first and second input signals and generating an output signal to charge and discharge a loop node and develop a loop node voltage ; initializing said loop node voltage to a predetermined level (optimal power, power state, optimal power state) ; generating an oscillator signal operating at a frequency determined by said loop node voltage ; dividing down said oscillator signal into first and second divided oscillator signals , said first divided oscillator signal operating as said second input signal ; generating a first load control signal when said second divided oscillator signal changes logic state more than a predetermined number of times during a first logic state of said first input signal ; and reducing said frequency of said oscillator signal in response to said first load control signal by increasing loading on said oscillator signal . US5304955A CLAIM 16 . The oscillator of claim 15 wherein said first loading circuit includes : a first transmission gate having first and second conduction terminals and first and second control terminals , said first control terminal receiving said first load control signal , said first conduction terminal being coupled to said output of said first inverter ; a fourth inverter having an input for receiving said first load control signal and an output coupled to said second control terminal of said first transmission gate ; and a first capacitor coupled between said second conduction terminal of said first transmission gate and a second power supply (optimal power, power state, optimal power state) conductor .
US6854067B1 CLAIM 9 . The method as recited in claim 8 , wherein said b2) is performed by a power supply scaler (load circuit) , and wherein said power supply scaler comprises : a) a divider of said common supply voltage ; b) a matrix of multiplexers and registers , and c) an interconnection to said bus .	US5304955A CLAIM 1 . A phase lock loop , comprising : first means for comparing a phase difference of first and second input signals and generating an output signal to charge and discharge a loop node ; a VCO having an input coupled for receiving said output signal of said first means and having an output for providing an oscillator signal ; second means for dividing down said oscillator signal into first and second divided oscillator signals , said first divided oscillator signal operating as said second input signal of said first means ; third means coupled for receiving said second divided oscillator signal and said first input signal and generating a first load control signal when said second divided oscillator signal changes logic state more than a predetermined number of times during a first logic state of said first input signal ; and a first load circuit (mode pump power supply, power supply scaler) coupled to said output of said VCO and operating in response to said first load control signal to increase loading at said output of said VCO .
US6854067B1 CLAIM 11 . The method as recited in claim 10 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power (second power supply, predetermined level) state corresponding to said status ; f3) programmatically calculating an optimal value (first log) for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	US5304955A CLAIM 1 . A phase lock loop , comprising : first means for comparing a phase difference of first and second input signals and generating an output signal to charge and discharge a loop node ; a VCO having an input coupled for receiving said output signal of said first means and having an output for providing an oscillator signal ; second means for dividing down said oscillator signal into first and second divided oscillator signals , said first divided oscillator signal operating as said second input signal of said first means ; third means coupled for receiving said second divided oscillator signal and said first input signal and generating a first load control signal when said second divided oscillator signal changes logic state more than a predetermined number of times during a first log (optimal value) ic state of said first input signal ; and a first load circuit coupled to said output of said VCO and operating in response to said first load control signal to increase loading at said output of said VCO . US5304955A CLAIM 8 . A method of controlling a maximum operating frequency of a phase lock loop , comprising the steps of : comparing a phase difference of first and second input signals and generating an output signal to charge and discharge a loop node and develop a loop node voltage ; initializing said loop node voltage to a predetermined level (optimal power, power state, optimal power state) ; generating an oscillator signal operating at a frequency determined by said loop node voltage ; dividing down said oscillator signal into first and second divided oscillator signals , said first divided oscillator signal operating as said second input signal ; generating a first load control signal when said second divided oscillator signal changes logic state more than a predetermined number of times during a first logic state of said first input signal ; and reducing said frequency of said oscillator signal in response to said first load control signal by increasing loading on said oscillator signal . US5304955A CLAIM 16 . The oscillator of claim 15 wherein said first loading circuit includes : a first transmission gate having first and second conduction terminals and first and second control terminals , said first control terminal receiving said first load control signal , said first conduction terminal being coupled to said output of said first inverter ; a fourth inverter having an input for receiving said first load control signal and an output coupled to said second control terminal of said first transmission gate ; and a first capacitor coupled between said second conduction terminal of said first transmission gate and a second power supply (optimal power, power state, optimal power state) conductor .
US6854067B1 CLAIM 12 . The method as recited in claim 11 , wherein said f4) further comprises : communicating each said optimal value (first log) to said power supply scaler (load circuit) via said bus ; registering each said optimal value with said matrix of multiplexers and registers ; commanding said matrix of multiplexers and registers to change said independent multiple of said common supply voltage to correspond with said optimal value ; and monitoring said matrix of multiplexers and registers .	US5304955A CLAIM 1 . A phase lock loop , comprising : first means for comparing a phase difference of first and second input signals and generating an output signal to charge and discharge a loop node ; a VCO having an input coupled for receiving said output signal of said first means and having an output for providing an oscillator signal ; second means for dividing down said oscillator signal into first and second divided oscillator signals , said first divided oscillator signal operating as said second input signal of said first means ; third means coupled for receiving said second divided oscillator signal and said first input signal and generating a first load control signal when said second divided oscillator signal changes logic state more than a predetermined number of times during a first log (optimal value) ic state of said first input signal ; and a first load circuit (mode pump power supply, power supply scaler) coupled to said output of said VCO and operating in response to said first load control signal to increase loading at said output of said VCO .
US6854067B1 CLAIM 13 . In a microcontroller , a system comprising : a bus ; a processor coupled to said bus ; a power on reset circuit (second control terminal) , said processor and said power on reset circuit coupled to said bus and interconnectedly coupled with said processor via said bus ; and a switched mode pump power supply (load circuit) interconnectedly coupled with said power on reset circuit and responsive to signals therefrom wherein said system executes a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state (second power supply, predetermined level) to said microcontroller from said switched mode pump power supply ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor via said bus ; e) controlling certain functions of said microcontroller according to said suitability status ; and f) dynamically programming said power on reset circuit via said bus .	US5304955A CLAIM 1 . A phase lock loop , comprising : first means for comparing a phase difference of first and second input signals and generating an output signal to charge and discharge a loop node ; a VCO having an input coupled for receiving said output signal of said first means and having an output for providing an oscillator signal ; second means for dividing down said oscillator signal into first and second divided oscillator signals , said first divided oscillator signal operating as said second input signal of said first means ; third means coupled for receiving said second divided oscillator signal and said first input signal and generating a first load control signal when said second divided oscillator signal changes logic state more than a predetermined number of times during a first logic state of said first input signal ; and a first load circuit (mode pump power supply, power supply scaler) coupled to said output of said VCO and operating in response to said first load control signal to increase loading at said output of said VCO . US5304955A CLAIM 6 . The oscillator of claim 5 wherein said first loading circuit includes : a first transmission gate having first and second conduction terminals and first and second control terminal (reset circuit) s , said first control terminal receiving said first load control signal , said first conduction terminal being coupled to said output of said first inverter ; a fourth inverter having an input for receiving said first load control signal and an output coupled to said second control terminal of said first transmission gate ; and a first capacitor coupled between said second conduction terminal of said first transmission gate and a power supply conductor . US5304955A CLAIM 8 . A method of controlling a maximum operating frequency of a phase lock loop , comprising the steps of : comparing a phase difference of first and second input signals and generating an output signal to charge and discharge a loop node and develop a loop node voltage ; initializing said loop node voltage to a predetermined level (optimal power, power state, optimal power state) ; generating an oscillator signal operating at a frequency determined by said loop node voltage ; dividing down said oscillator signal into first and second divided oscillator signals , said first divided oscillator signal operating as said second input signal ; generating a first load control signal when said second divided oscillator signal changes logic state more than a predetermined number of times during a first logic state of said first input signal ; and reducing said frequency of said oscillator signal in response to said first load control signal by increasing loading on said oscillator signal . US5304955A CLAIM 16 . The oscillator of claim 15 wherein said first loading circuit includes : a first transmission gate having first and second conduction terminals and first and second control terminals , said first control terminal receiving said first load control signal , said first conduction terminal being coupled to said output of said first inverter ; a fourth inverter having an input for receiving said first load control signal and an output coupled to said second control terminal of said first transmission gate ; and a first capacitor coupled between said second conduction terminal of said first transmission gate and a second power supply (optimal power, power state, optimal power state) conductor .
US6854067B1 CLAIM 14 . The system as recited in claim 13 , wherein said b) and said c) of said method are accomplished by said power on reset circuit (second control terminal) .	US5304955A CLAIM 6 . The oscillator of claim 5 wherein said first loading circuit includes : a first transmission gate having first and second conduction terminals and first and second control terminal (reset circuit) s , said first control terminal receiving said first load control signal , said first conduction terminal being coupled to said output of said first inverter ; a fourth inverter having an input for receiving said first load control signal and an output coupled to said second control terminal of said first transmission gate ; and a first capacitor coupled between said second conduction terminal of said first transmission gate and a power supply conductor .
US6854067B1 CLAIM 15 . The system as recited in claim 14 , wherein said b) of said method further comprises sensing a common supply voltage , wherein said common supply voltage is the voltage of said power state (second power supply, predetermined level) .	US5304955A CLAIM 8 . A method of controlling a maximum operating frequency of a phase lock loop , comprising the steps of : comparing a phase difference of first and second input signals and generating an output signal to charge and discharge a loop node and develop a loop node voltage ; initializing said loop node voltage to a predetermined level (optimal power, power state, optimal power state) ; generating an oscillator signal operating at a frequency determined by said loop node voltage ; dividing down said oscillator signal into first and second divided oscillator signals , said first divided oscillator signal operating as said second input signal ; generating a first load control signal when said second divided oscillator signal changes logic state more than a predetermined number of times during a first logic state of said first input signal ; and reducing said frequency of said oscillator signal in response to said first load control signal by increasing loading on said oscillator signal . US5304955A CLAIM 16 . The oscillator of claim 15 wherein said first loading circuit includes : a first transmission gate having first and second conduction terminals and first and second control terminals , said first control terminal receiving said first load control signal , said first conduction terminal being coupled to said output of said first inverter ; a fourth inverter having an input for receiving said first load control signal and an output coupled to said second control terminal of said first transmission gate ; and a first capacitor coupled between said second conduction terminal of said first transmission gate and a second power supply (optimal power, power state, optimal power state) conductor .
US6854067B1 CLAIM 16 . The system as recited in claim 15 , wherein said c) further comprises : c1) generating a precision reference voltage , said precision reference voltage independent of said common supply voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state (second power supply, predetermined level) condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US5304955A CLAIM 8 . A method of controlling a maximum operating frequency of a phase lock loop , comprising the steps of : comparing a phase difference of first and second input signals and generating an output signal to charge and discharge a loop node and develop a loop node voltage ; initializing said loop node voltage to a predetermined level (optimal power, power state, optimal power state) ; generating an oscillator signal operating at a frequency determined by said loop node voltage ; dividing down said oscillator signal into first and second divided oscillator signals , said first divided oscillator signal operating as said second input signal ; generating a first load control signal when said second divided oscillator signal changes logic state more than a predetermined number of times during a first logic state of said first input signal ; and reducing said frequency of said oscillator signal in response to said first load control signal by increasing loading on said oscillator signal . US5304955A CLAIM 16 . The oscillator of claim 15 wherein said first loading circuit includes : a first transmission gate having first and second conduction terminals and first and second control terminals , said first control terminal receiving said first load control signal , said first conduction terminal being coupled to said output of said first inverter ; a fourth inverter having an input for receiving said first load control signal and an output coupled to said second control terminal of said first transmission gate ; and a first capacitor coupled between said second conduction terminal of said first transmission gate and a second power supply (optimal power, power state, optimal power state) conductor .
US6854067B1 CLAIM 17 . The system as recited in claim 16 , wherein said b2) is performed by a power supply scaler (load circuit) , wherein said power supply scaler comprises : a) a divider of said common supply voltage ; b) a matrix of multiplexers and registers , and c) an interconnection to said bus .	US5304955A CLAIM 1 . A phase lock loop , comprising : first means for comparing a phase difference of first and second input signals and generating an output signal to charge and discharge a loop node ; a VCO having an input coupled for receiving said output signal of said first means and having an output for providing an oscillator signal ; second means for dividing down said oscillator signal into first and second divided oscillator signals , said first divided oscillator signal operating as said second input signal of said first means ; third means coupled for receiving said second divided oscillator signal and said first input signal and generating a first load control signal when said second divided oscillator signal changes logic state more than a predetermined number of times during a first logic state of said first input signal ; and a first load circuit (mode pump power supply, power supply scaler) coupled to said output of said VCO and operating in response to said first load control signal to increase loading at said output of said VCO .
US6854067B1 CLAIM 18 . The system as recited in claim 17 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power (second power supply, predetermined level) state corresponding to said status ; f3) programmatically calculating an optimal value (first log) for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	US5304955A CLAIM 1 . A phase lock loop , comprising : first means for comparing a phase difference of first and second input signals and generating an output signal to charge and discharge a loop node ; a VCO having an input coupled for receiving said output signal of said first means and having an output for providing an oscillator signal ; second means for dividing down said oscillator signal into first and second divided oscillator signals , said first divided oscillator signal operating as said second input signal of said first means ; third means coupled for receiving said second divided oscillator signal and said first input signal and generating a first load control signal when said second divided oscillator signal changes logic state more than a predetermined number of times during a first log (optimal value) ic state of said first input signal ; and a first load circuit coupled to said output of said VCO and operating in response to said first load control signal to increase loading at said output of said VCO . US5304955A CLAIM 8 . A method of controlling a maximum operating frequency of a phase lock loop , comprising the steps of : comparing a phase difference of first and second input signals and generating an output signal to charge and discharge a loop node and develop a loop node voltage ; initializing said loop node voltage to a predetermined level (optimal power, power state, optimal power state) ; generating an oscillator signal operating at a frequency determined by said loop node voltage ; dividing down said oscillator signal into first and second divided oscillator signals , said first divided oscillator signal operating as said second input signal ; generating a first load control signal when said second divided oscillator signal changes logic state more than a predetermined number of times during a first logic state of said first input signal ; and reducing said frequency of said oscillator signal in response to said first load control signal by increasing loading on said oscillator signal . US5304955A CLAIM 16 . The oscillator of claim 15 wherein said first loading circuit includes : a first transmission gate having first and second conduction terminals and first and second control terminals , said first control terminal receiving said first load control signal , said first conduction terminal being coupled to said output of said first inverter ; a fourth inverter having an input for receiving said first load control signal and an output coupled to said second control terminal of said first transmission gate ; and a first capacitor coupled between said second conduction terminal of said first transmission gate and a second power supply (optimal power, power state, optimal power state) conductor .
US6854067B1 CLAIM 19 . The method as recited in claim 18 , wherein said f4) further comprises : communicating each said optimal value (first log) to said power supply scaler (load circuit) via said bus ; registering each said optimal value with said matrix of multiplexers and registers ; commanding said matrix of multiplexers and registers to change said independent multiple of said common supply voltage to correspond with said optimal value ; and monitoring said matrix of multiplexers and registers .	US5304955A CLAIM 1 . A phase lock loop , comprising : first means for comparing a phase difference of first and second input signals and generating an output signal to charge and discharge a loop node ; a VCO having an input coupled for receiving said output signal of said first means and having an output for providing an oscillator signal ; second means for dividing down said oscillator signal into first and second divided oscillator signals , said first divided oscillator signal operating as said second input signal of said first means ; third means coupled for receiving said second divided oscillator signal and said first input signal and generating a first load control signal when said second divided oscillator signal changes logic state more than a predetermined number of times during a first log (optimal value) ic state of said first input signal ; and a first load circuit (mode pump power supply, power supply scaler) coupled to said output of said VCO and operating in response to said first load control signal to increase loading at said output of said VCO .
US6854067B1 CLAIM 20 . In a microcontroller having a power on reset circuit (second control terminal) interconnected with a processor a method of dynamically controlling said power state (second power supply, predetermined level) , said method comprising : a) ascertaining a power state powered by a switched mode pump power supply (load circuit) , said switched mode pump power supply interconnected with and responsive to control by said power on reset circuit ; b) programmatically determining desired changes to said power state ; c) intercommunicating between said processor and said power on reset circuit ; d) adjusting said power on reset circuit corresponding to said desired changes to said power state ; e) controlling said switched mode pump power supply according to said d) ; and f) repeating said a) through e) .	US5304955A CLAIM 1 . A phase lock loop , comprising : first means for comparing a phase difference of first and second input signals and generating an output signal to charge and discharge a loop node ; a VCO having an input coupled for receiving said output signal of said first means and having an output for providing an oscillator signal ; second means for dividing down said oscillator signal into first and second divided oscillator signals , said first divided oscillator signal operating as said second input signal of said first means ; third means coupled for receiving said second divided oscillator signal and said first input signal and generating a first load control signal when said second divided oscillator signal changes logic state more than a predetermined number of times during a first logic state of said first input signal ; and a first load circuit (mode pump power supply, power supply scaler) coupled to said output of said VCO and operating in response to said first load control signal to increase loading at said output of said VCO . US5304955A CLAIM 6 . The oscillator of claim 5 wherein said first loading circuit includes : a first transmission gate having first and second conduction terminals and first and second control terminal (reset circuit) s , said first control terminal receiving said first load control signal , said first conduction terminal being coupled to said output of said first inverter ; a fourth inverter having an input for receiving said first load control signal and an output coupled to said second control terminal of said first transmission gate ; and a first capacitor coupled between said second conduction terminal of said first transmission gate and a power supply conductor . US5304955A CLAIM 8 . A method of controlling a maximum operating frequency of a phase lock loop , comprising the steps of : comparing a phase difference of first and second input signals and generating an output signal to charge and discharge a loop node and develop a loop node voltage ; initializing said loop node voltage to a predetermined level (optimal power, power state, optimal power state) ; generating an oscillator signal operating at a frequency determined by said loop node voltage ; dividing down said oscillator signal into first and second divided oscillator signals , said first divided oscillator signal operating as said second input signal ; generating a first load control signal when said second divided oscillator signal changes logic state more than a predetermined number of times during a first logic state of said first input signal ; and reducing said frequency of said oscillator signal in response to said first load control signal by increasing loading on said oscillator signal . US5304955A CLAIM 16 . The oscillator of claim 15 wherein said first loading circuit includes : a first transmission gate having first and second conduction terminals and first and second control terminals , said first control terminal receiving said first load control signal , said first conduction terminal being coupled to said output of said first inverter ; a fourth inverter having an input for receiving said first load control signal and an output coupled to said second control terminal of said first transmission gate ; and a first capacitor coupled between said second conduction terminal of said first transmission gate and a second power supply (optimal power, power state, optimal power state) conductor .

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	US5289023A Filed: 1992-08-07 Issued: 1994-02-22 High-density photosensor and contactless imaging array having wide dynamic range (Original Assignee) Synaptics Inc (Current Assignee) Foveon Inc Carver A. Mead
US6854067B1 CLAIM 1 . In a microcontroller with an embedded processor , a switched mode pump power supply and power on reset circuit (output node) , a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply , wherein said processor and said power on reset circuit are interconnectedly coupled , and wherein said switched mode pump power supply is interconnectedly coupled with said power on reset circuit and responsive to signals therefrom ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor ; e) controlling certain functions of said microcontroller accordingly .	US5289023A CLAIM 11 . The integrating imaging array of claim 10 wherein said means for selectively connecting comprises an MOS transistor connected between said input node and said output node (reset circuit) , said MOS transistor having its gate connected to a balance input node .
US6854067B1 CLAIM 2 . The method as recited in claim 1 , further comprising : f) dynamically programming said power on reset circuit (output node) .	US5289023A CLAIM 11 . The integrating imaging array of claim 10 wherein said means for selectively connecting comprises an MOS transistor connected between said input node and said output node (reset circuit) , said MOS transistor having its gate connected to a balance input node .
US6854067B1 CLAIM 3 . The method as recited in claim 2 , wherein said power on reset circuit (output node) and said processor are interconnected via a bus .	US5289023A CLAIM 11 . The integrating imaging array of claim 10 wherein said means for selectively connecting comprises an MOS transistor connected between said input node and said output node (reset circuit) , said MOS transistor having its gate connected to a balance input node .
US6854067B1 CLAIM 4 . The method as recited in claim 3 , wherein said b) and said c) are accomplished by said power on reset circuit (output node) .	US5289023A CLAIM 11 . The integrating imaging array of claim 10 wherein said means for selectively connecting comprises an MOS transistor connected between said input node and said output node (reset circuit) , said MOS transistor having its gate connected to a balance input node .
US6854067B1 CLAIM 11 . The method as recited in claim 10 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state (one end) corresponding to said status ; f3) programmatically calculating an optimal value for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	US5289023A CLAIM 5 . An integrating imaging array disposed on a single piece of semiconductor substrate material , including : a plurality of integrating photosensors arranged in an array of at least one row and at least one column , each of said photosensors comprising a bipolar phototransistor having a collector connected to a fixed voltage source , a base connected to one end (optimal power state) of a capacitor , the other end of said capacitor connected to a select node , and an emitter ; a plurality of row lines , each one of said row lines associated with a different row in said array , each of said row lines connected to the select nodes of all of the integrating photosensors associated with its row ; and a plurality of sense lines , each one of said sense lines associated with a different column in said array and comprising a doped polysilicon line , regions of said doped polysilicon line in contact with the base regions of all of said phototransistors in its column to form said emitters thereof .
US6854067B1 CLAIM 13 . In a microcontroller , a system comprising : a bus ; a processor coupled to said bus ; a power on reset circuit (output node) , said processor and said power on reset circuit coupled to said bus and interconnectedly coupled with said processor via said bus ; and a switched mode pump power supply interconnectedly coupled with said power on reset circuit and responsive to signals therefrom wherein said system executes a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor via said bus ; e) controlling certain functions of said microcontroller according to said suitability status ; and f) dynamically programming said power on reset circuit via said bus .	US5289023A CLAIM 11 . The integrating imaging array of claim 10 wherein said means for selectively connecting comprises an MOS transistor connected between said input node and said output node (reset circuit) , said MOS transistor having its gate connected to a balance input node .
US6854067B1 CLAIM 14 . The system as recited in claim 13 , wherein said b) and said c) of said method are accomplished by said power on reset circuit (output node) .	US5289023A CLAIM 11 . The integrating imaging array of claim 10 wherein said means for selectively connecting comprises an MOS transistor connected between said input node and said output node (reset circuit) , said MOS transistor having its gate connected to a balance input node .
US6854067B1 CLAIM 18 . The system as recited in claim 17 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state (one end) corresponding to said status ; f3) programmatically calculating an optimal value for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	US5289023A CLAIM 5 . An integrating imaging array disposed on a single piece of semiconductor substrate material , including : a plurality of integrating photosensors arranged in an array of at least one row and at least one column , each of said photosensors comprising a bipolar phototransistor having a collector connected to a fixed voltage source , a base connected to one end (optimal power state) of a capacitor , the other end of said capacitor connected to a select node , and an emitter ; a plurality of row lines , each one of said row lines associated with a different row in said array , each of said row lines connected to the select nodes of all of the integrating photosensors associated with its row ; and a plurality of sense lines , each one of said sense lines associated with a different column in said array and comprising a doped polysilicon line , regions of said doped polysilicon line in contact with the base regions of all of said phototransistors in its column to form said emitters thereof .
US6854067B1 CLAIM 20 . In a microcontroller having a power on reset circuit (output node) interconnected with a processor a method of dynamically controlling said power state , said method comprising : a) ascertaining a power state powered by a switched mode pump power supply , said switched mode pump power supply interconnected with and responsive to control by said power on reset circuit ; b) programmatically determining desired changes to said power state ; c) intercommunicating between said processor and said power on reset circuit ; d) adjusting said power on reset circuit corresponding to said desired changes to said power state ; e) controlling said switched mode pump power supply according to said d) ; and f) repeating said a) through e) .	US5289023A CLAIM 11 . The integrating imaging array of claim 10 wherein said means for selectively connecting comprises an MOS transistor connected between said input node and said output node (reset circuit) , said MOS transistor having its gate connected to a balance input node .

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	US5305017A Filed: 1992-07-13 Issued: 1994-04-19 Methods and apparatus for data input (Original Assignee) Gerpheide George E (Current Assignee) Cirque Corp George E. Gerpheide
US6854067B1 CLAIM 1 . In a microcontroller with an embedded processor , a switched mode pump power supply and power on reset circuit , a method of dynamically controlling a plurality of power stability functions (control means) for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply , wherein said processor and said power on reset circuit are interconnectedly coupled , and wherein said switched mode pump power supply is interconnectedly coupled with said power on reset circuit and responsive to signals therefrom ; b) sensing a power state condition of said power state ; c) determining a suitability status (data input device) of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor ; e) controlling certain functions of said microcontroller accordingly .	US5305017A CLAIM 1 . Apparatus for data input through sensing the position of a passive object relative to the apparatus comprising : pad means for sensing the object' ; s position , the pad means having a plurality of first electrode strips spaced apart in a first array , one or more second electrode strips disposed in proximity to the first electrode strips to cross thereover for establishing electric fields , including fringe electric fields , between the second electrode strip and selected first electrode strips , to thereby develop capacitive balances in the pad means , wherein the object perturbs a fringe electric field when the object comes in proximity to the pad means , thereby changing the capacitive balances ; and measurement means operatively coupled to the pad means for measuring the capacitive balances in the pad means to thereby determine the position of the object relative to the pad means , said measurement means including synthesis means responsive to control signals for selecting first electrode strips which , along with the second electrode strip , will develop electric fields , control means (power stability functions) for supplying control signals to the synthesis means to designate the selected first electrode strips , means for causing development of electric fields between the selected first electrode strips and the second electrode strip , and means for detecting the changes in capacitive balances in the pad means and the locations of such changes . US5305017A CLAIM 10 . The apparatus recited in claim 8 wherein the apparatus is mounted to a keyboard data input device (suitability status) of a computer .
US6854067B1 CLAIM 11 . The method as recited in claim 10 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state corresponding to said status ; f3) programmatically calculating an optimal value (first side) for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	US5305017A CLAIM 2 . The apparatus recited in claim 1 wherein the pad means further comprises : insulator means having first and second sides electrically interfaced with the plurality of first electrode strips on the first side (optimal value) for providing an insulating substrate for the pad means ; and said second electrode strip being interfaced with the insulator means on the second side .
US6854067B1 CLAIM 12 . The method as recited in claim 11 , wherein said f4) further comprises : communicating each said optimal value (first side) to said power supply scaler via said bus ; registering each said optimal value with said matrix of multiplexers and registers ; commanding said matrix of multiplexers and registers to change said independent multiple of said common supply voltage to correspond with said optimal value ; and monitoring said matrix of multiplexers and registers .	US5305017A CLAIM 2 . The apparatus recited in claim 1 wherein the pad means further comprises : insulator means having first and second sides electrically interfaced with the plurality of first electrode strips on the first side (optimal value) for providing an insulating substrate for the pad means ; and said second electrode strip being interfaced with the insulator means on the second side .
US6854067B1 CLAIM 13 . In a microcontroller , a system comprising : a bus ; a processor coupled to said bus ; a power on reset circuit , said processor and said power on reset circuit coupled to said bus and interconnectedly coupled with said processor via said bus ; and a switched mode pump power supply interconnectedly coupled with said power on reset circuit and responsive to signals therefrom wherein said system executes a method of dynamically controlling a plurality of power stability functions (control means) for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply ; b) sensing a power state condition of said power state ; c) determining a suitability status (data input device) of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor via said bus ; e) controlling certain functions of said microcontroller according to said suitability status ; and f) dynamically programming said power on reset circuit via said bus .	US5305017A CLAIM 1 . Apparatus for data input through sensing the position of a passive object relative to the apparatus comprising : pad means for sensing the object' ; s position , the pad means having a plurality of first electrode strips spaced apart in a first array , one or more second electrode strips disposed in proximity to the first electrode strips to cross thereover for establishing electric fields , including fringe electric fields , between the second electrode strip and selected first electrode strips , to thereby develop capacitive balances in the pad means , wherein the object perturbs a fringe electric field when the object comes in proximity to the pad means , thereby changing the capacitive balances ; and measurement means operatively coupled to the pad means for measuring the capacitive balances in the pad means to thereby determine the position of the object relative to the pad means , said measurement means including synthesis means responsive to control signals for selecting first electrode strips which , along with the second electrode strip , will develop electric fields , control means (power stability functions) for supplying control signals to the synthesis means to designate the selected first electrode strips , means for causing development of electric fields between the selected first electrode strips and the second electrode strip , and means for detecting the changes in capacitive balances in the pad means and the locations of such changes . US5305017A CLAIM 10 . The apparatus recited in claim 8 wherein the apparatus is mounted to a keyboard data input device (suitability status) of a computer .
US6854067B1 CLAIM 18 . The system as recited in claim 17 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state corresponding to said status ; f3) programmatically calculating an optimal value (first side) for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	US5305017A CLAIM 2 . The apparatus recited in claim 1 wherein the pad means further comprises : insulator means having first and second sides electrically interfaced with the plurality of first electrode strips on the first side (optimal value) for providing an insulating substrate for the pad means ; and said second electrode strip being interfaced with the insulator means on the second side .
US6854067B1 CLAIM 19 . The method as recited in claim 18 , wherein said f4) further comprises : communicating each said optimal value (first side) to said power supply scaler via said bus ; registering each said optimal value with said matrix of multiplexers and registers ; commanding said matrix of multiplexers and registers to change said independent multiple of said common supply voltage to correspond with said optimal value ; and monitoring said matrix of multiplexers and registers .	US5305017A CLAIM 2 . The apparatus recited in claim 1 wherein the pad means further comprises : insulator means having first and second sides electrically interfaced with the plurality of first electrode strips on the first side (optimal value) for providing an insulating substrate for the pad means ; and said second electrode strip being interfaced with the insulator means on the second side .

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	US5303329A Filed: 1991-12-10 Issued: 1994-04-12 Continuous synaptic weight update mechanism (Original Assignee) Synaptics Inc (Current Assignee) Industrial Technology Research Institute ITRI ; Synaptics Inc Carver A. Mead, Janeen D. W. Anderson, John C. Platt
US6854067B1 CLAIM 1 . In a microcontroller with an embedded processor , a switched mode pump power supply and power on reset circuit (output node) , a method of dynamically controlling a plurality of power stability functions (control means) for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply , wherein said processor and said power on reset circuit are interconnectedly coupled , and wherein said switched mode pump power supply is interconnectedly coupled with said power on reset circuit and responsive to signals therefrom ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor ; e) controlling certain functions of said microcontroller accordingly .	US5303329A CLAIM 1 . A continuous synaptic weight-update device comprising : a single floating node having a capacitance associated therewith ; first and second signal input lines ; first and second error input lines ; electron tunneling means , connected to said floating node , for tunneling electrons from said floating node ; hot electron injecting means , connected to said floating node , for injecting hot electrons onto said floating node ; first driving means for driving voltages on said first signal input line and said first error input line in opposite directions with respect to a first reference voltage when it is desired to remove electrons from said floating node ; second driving means for driving voltages on said second signal input line and said second error input line in opposite directions with respect to a second reference voltage when it is desired to place electrons onto said floating node ; first control means (power stability functions) , responsive to the product of said votlages on said first signal input line and said first error input line , for activating said electron tunneling means ; and second control means , responsive to the product of said voltages on said second signal input line and said second error input line , for activating said hot electron injecting means .
US6854067B1 CLAIM 13 . In a microcontroller , a system comprising : a bus ; a processor coupled to said bus ; a power on reset circuit (output node) , said processor and said power on reset circuit coupled to said bus and interconnectedly coupled with said processor via said bus ; and a switched mode pump power supply interconnectedly coupled with said power on reset circuit and responsive to signals therefrom wherein said system executes a method of dynamically controlling a plurality of power stability functions (control means) for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor via said bus ; e) controlling certain functions of said microcontroller according to said suitability status ; and f) dynamically programming said power on reset circuit via said bus .	US5303329A CLAIM 1 . A continuous synaptic weight-update device comprising : a single floating node having a capacitance associated therewith ; first and second signal input lines ; first and second error input lines ; electron tunneling means , connected to said floating node , for tunneling electrons from said floating node ; hot electron injecting means , connected to said floating node , for injecting hot electrons onto said floating node ; first driving means for driving voltages on said first signal input line and said first error input line in opposite directions with respect to a first reference voltage when it is desired to remove electrons from said floating node ; second driving means for driving voltages on said second signal input line and said second error input line in opposite directions with respect to a second reference voltage when it is desired to place electrons onto said floating node ; first control means (power stability functions) , responsive to the product of said votlages on said first signal input line and said first error input line , for activating said electron tunneling means ; and second control means , responsive to the product of said voltages on said second signal input line and said second error input line , for activating said hot electron injecting means .

US6854067B1

Filed: 2000-10-30 Issued: 2005-02-08

Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller

(Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC

Harold Kutz, Warren Snyder

US5303329A

Filed: 1991-12-10 Issued: 1994-04-12

Continuous synaptic weight update mechanism

(Original Assignee) Synaptics Inc (Current Assignee) Industrial Technology Research Institute ITRI ; Synaptics Inc

Carver A. Mead, Janeen D. W. Anderson, John C. Platt

US6854067B1
CLAIM 1 . In a microcontroller with an embedded processor , a switched mode pump power supply and power on reset circuit (output node) , a method of dynamically controlling a plurality of power stability functions (control means) for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply , wherein said processor and said power on reset circuit are interconnectedly coupled , and wherein said switched mode pump power supply is interconnectedly coupled with said power on reset circuit and responsive to signals therefrom ;

b) sensing a power state condition of said power state ;

c) determining a suitability status of said power state condition ;

d) communicating said suitability status between said power on reset circuit and said processor ;

e) controlling certain functions of said microcontroller accordingly .

US5303329A
CLAIM 1 . A continuous synaptic weight-update device comprising : a single floating node having a capacitance associated therewith ;
first and second signal input lines ;
first and second error input lines ;
electron tunneling means , connected to said floating node , for tunneling electrons from said floating node ;
hot electron injecting means , connected to said floating node , for injecting hot electrons onto said floating node ;
first driving means for driving voltages on said first signal input line and said first error input line in opposite directions with respect to a first reference voltage when it is desired to remove electrons from said floating node ;
second driving means for driving voltages on said second signal input line and said second error input line in opposite directions with respect to a second reference voltage when it is desired to place electrons onto said floating node ;
first control means (power stability functions) , responsive to the product of said votlages on said first signal input line and said first error input line , for activating said electron tunneling means ;
and second control means , responsive to the product of said voltages on said second signal input line and said second error input line , for activating said hot electron injecting means .

US6854067B1
CLAIM 13 . In a microcontroller , a system comprising : a bus ;

a processor coupled to said bus ;

a power on reset circuit (output node) , said processor and said power on reset circuit coupled to said bus and interconnectedly coupled with said processor via said bus ;

and a switched mode pump power supply interconnectedly coupled with said power on reset circuit and responsive to signals therefrom wherein said system executes a method of dynamically controlling a plurality of power stability functions (control means) for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply ;

b) sensing a power state condition of said power state ;

c) determining a suitability status of said power state condition ;

d) communicating said suitability status between said power on reset circuit and said processor via said bus ;

e) controlling certain functions of said microcontroller according to said suitability status ;

and f) dynamically programming said power on reset circuit via said bus .

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	US5160899A Filed: 1991-10-22 Issued: 1992-11-03 Adaptable MOS current mirror (Original Assignee) Synaptics Inc (Current Assignee) Synaptics Inc Janeen D. W. Anderson, Carver A. Mead, Timothy P. Allen, Michael F. Wall
US6854067B1 CLAIM 1 . In a microcontroller with an embedded processor , a switched mode pump power supply and power on reset circuit (output node) , a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply , wherein said processor and said power on reset circuit are interconnectedly coupled , and wherein said switched mode pump power supply is interconnectedly coupled with said power on reset circuit and responsive to signals therefrom ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor ; e) controlling certain functions of said microcontroller accordingly .	US5160899A CLAIM 1 . An adaptable MOS current mirror fabricated on a semiconductor substrate , said adaptable MOS current mirror having an input node and an output node (reset circuit) and including : first and second MOS transistors , each having a source , a gate , and a drain ; a first MOS capacitor having first and second electrodes ; the source of said first MOS transistor being connected to a source of fixed voltage , the gate and drain of said first MOS transistor being connected to said input node and to said first electrode of said first MOS capacitor , the source of said second MOS transistor being connected to a source of fixed voltage , the gate of said MOS transistor comprising a floating node connected to said second electrode of said first capacitor , the drain of said second MOS transistor forming said output node ; means for generating a first electrical control signal ; electron removal means coupled to said floating node and responsive to said means for generating said first electrical control signal , for removing electrons from said floating node , said electron removal means operating to vary the rate of removal of electrons from said floating gate in response to the magnitude of said first electrical control signal ; means for selectively supplying a calibration current to said input node during adaptation ; means for generating a second electrical control signal during adaptation ; electron injecting means coupled to said floating node and responsive to said second electrical control signal for injecting electrons on to said floating node , said electron injecting means operating to vary the rate of injection of electrons on to said floating node in response to the magnitude of said second electrical control signal ; whereby the output current of said current mirror is adapted to be equal to said desired output current when its input current is equal to said calibration current .
US6854067B1 CLAIM 2 . The method as recited in claim 1 , further comprising : f) dynamically programming said power on reset circuit (output node) .	US5160899A CLAIM 1 . An adaptable MOS current mirror fabricated on a semiconductor substrate , said adaptable MOS current mirror having an input node and an output node (reset circuit) and including : first and second MOS transistors , each having a source , a gate , and a drain ; a first MOS capacitor having first and second electrodes ; the source of said first MOS transistor being connected to a source of fixed voltage , the gate and drain of said first MOS transistor being connected to said input node and to said first electrode of said first MOS capacitor , the source of said second MOS transistor being connected to a source of fixed voltage , the gate of said MOS transistor comprising a floating node connected to said second electrode of said first capacitor , the drain of said second MOS transistor forming said output node ; means for generating a first electrical control signal ; electron removal means coupled to said floating node and responsive to said means for generating said first electrical control signal , for removing electrons from said floating node , said electron removal means operating to vary the rate of removal of electrons from said floating gate in response to the magnitude of said first electrical control signal ; means for selectively supplying a calibration current to said input node during adaptation ; means for generating a second electrical control signal during adaptation ; electron injecting means coupled to said floating node and responsive to said second electrical control signal for injecting electrons on to said floating node , said electron injecting means operating to vary the rate of injection of electrons on to said floating node in response to the magnitude of said second electrical control signal ; whereby the output current of said current mirror is adapted to be equal to said desired output current when its input current is equal to said calibration current .
US6854067B1 CLAIM 3 . The method as recited in claim 2 , wherein said power on reset circuit (output node) and said processor are interconnected via a bus .	US5160899A CLAIM 1 . An adaptable MOS current mirror fabricated on a semiconductor substrate , said adaptable MOS current mirror having an input node and an output node (reset circuit) and including : first and second MOS transistors , each having a source , a gate , and a drain ; a first MOS capacitor having first and second electrodes ; the source of said first MOS transistor being connected to a source of fixed voltage , the gate and drain of said first MOS transistor being connected to said input node and to said first electrode of said first MOS capacitor , the source of said second MOS transistor being connected to a source of fixed voltage , the gate of said MOS transistor comprising a floating node connected to said second electrode of said first capacitor , the drain of said second MOS transistor forming said output node ; means for generating a first electrical control signal ; electron removal means coupled to said floating node and responsive to said means for generating said first electrical control signal , for removing electrons from said floating node , said electron removal means operating to vary the rate of removal of electrons from said floating gate in response to the magnitude of said first electrical control signal ; means for selectively supplying a calibration current to said input node during adaptation ; means for generating a second electrical control signal during adaptation ; electron injecting means coupled to said floating node and responsive to said second electrical control signal for injecting electrons on to said floating node , said electron injecting means operating to vary the rate of injection of electrons on to said floating node in response to the magnitude of said second electrical control signal ; whereby the output current of said current mirror is adapted to be equal to said desired output current when its input current is equal to said calibration current .
US6854067B1 CLAIM 4 . The method as recited in claim 3 , wherein said b) and said c) are accomplished by said power on reset circuit (output node) .	US5160899A CLAIM 1 . An adaptable MOS current mirror fabricated on a semiconductor substrate , said adaptable MOS current mirror having an input node and an output node (reset circuit) and including : first and second MOS transistors , each having a source , a gate , and a drain ; a first MOS capacitor having first and second electrodes ; the source of said first MOS transistor being connected to a source of fixed voltage , the gate and drain of said first MOS transistor being connected to said input node and to said first electrode of said first MOS capacitor , the source of said second MOS transistor being connected to a source of fixed voltage , the gate of said MOS transistor comprising a floating node connected to said second electrode of said first capacitor , the drain of said second MOS transistor forming said output node ; means for generating a first electrical control signal ; electron removal means coupled to said floating node and responsive to said means for generating said first electrical control signal , for removing electrons from said floating node , said electron removal means operating to vary the rate of removal of electrons from said floating gate in response to the magnitude of said first electrical control signal ; means for selectively supplying a calibration current to said input node during adaptation ; means for generating a second electrical control signal during adaptation ; electron injecting means coupled to said floating node and responsive to said second electrical control signal for injecting electrons on to said floating node , said electron injecting means operating to vary the rate of injection of electrons on to said floating node in response to the magnitude of said second electrical control signal ; whereby the output current of said current mirror is adapted to be equal to said desired output current when its input current is equal to said calibration current .
US6854067B1 CLAIM 6 . The method as recited in claim 5 , wherein said c) further comprises : c1) generating a precision reference voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals (negative voltage) , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US5160899A CLAIM 5 . An adaptable circuit , communicating with a plurality of current-carrying lines , for indicating the output of the one of said plurality of current-carrying lines through which the most current is flowing , including : a plurality of capacitor coupled MOS current mirrors , each of said current mirrors including an input node , an output node , a driving MOS current mirror transistor and a driven MOS current mirror transistor , the sources of each driving MOS current mirror transistor and each driven MOS current mirror transistor connected to a source of fixed positive voltage , the gate and drain of each of said driving MOS current mirror transistors comprising said input node and connected to a different one of said current carrying lines and to a first electrode of an MOS capacitor , the gate of said driven MOS current mirror transistor connected to a floating node , the second electrode of said MOS capacitor comprising a portion of said floating node , and the drain of said driven MOS current mirror transistor comprising said output node ; a pulldown transistor associated with each of said current mirrors , each of said pulldown transistors having its source connected to a source of fixed negative voltage (power state condition signals) , and its gate connected to a common pulldown gate line ; a pulldown gate bias transistor , having its source connected to said source of negative voltage , its gate connected to a source of bias voltage ; a follower transistor associated with each of said current mirrors , each of said follower transistors having its gate connected to the output of the current mirror with which it is associated , and having a source-drain path connected between a source of fixed voltage and said common pulldown gate line ; means , operable during an operating mode of said circuit , for selectively connecting the drain of said pulldown gate bias transistor to said common pulldown gate line , and for enabling said source-drain path of each said follower transistor ; means , operable during an adapting mode of said circuit , for selectively connecting said common pulldown gate line to a source of fixed voltage , for disabling said source-drain path of said follower transistor , and for adjusting the charge on each floating node in response to the voltage at said output node of said current mirror with which it is associated ; whereby the offset voltages of said circuit can be adapted during said adapting mode of said circuit .
US6854067B1 CLAIM 13 . In a microcontroller , a system comprising : a bus ; a processor coupled to said bus ; a power on reset circuit (output node) , said processor and said power on reset circuit coupled to said bus and interconnectedly coupled with said processor via said bus ; and a switched mode pump power supply interconnectedly coupled with said power on reset circuit and responsive to signals therefrom wherein said system executes a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor via said bus ; e) controlling certain functions of said microcontroller according to said suitability status ; and f) dynamically programming said power on reset circuit via said bus .	US5160899A CLAIM 1 . An adaptable MOS current mirror fabricated on a semiconductor substrate , said adaptable MOS current mirror having an input node and an output node (reset circuit) and including : first and second MOS transistors , each having a source , a gate , and a drain ; a first MOS capacitor having first and second electrodes ; the source of said first MOS transistor being connected to a source of fixed voltage , the gate and drain of said first MOS transistor being connected to said input node and to said first electrode of said first MOS capacitor , the source of said second MOS transistor being connected to a source of fixed voltage , the gate of said MOS transistor comprising a floating node connected to said second electrode of said first capacitor , the drain of said second MOS transistor forming said output node ; means for generating a first electrical control signal ; electron removal means coupled to said floating node and responsive to said means for generating said first electrical control signal , for removing electrons from said floating node , said electron removal means operating to vary the rate of removal of electrons from said floating gate in response to the magnitude of said first electrical control signal ; means for selectively supplying a calibration current to said input node during adaptation ; means for generating a second electrical control signal during adaptation ; electron injecting means coupled to said floating node and responsive to said second electrical control signal for injecting electrons on to said floating node , said electron injecting means operating to vary the rate of injection of electrons on to said floating node in response to the magnitude of said second electrical control signal ; whereby the output current of said current mirror is adapted to be equal to said desired output current when its input current is equal to said calibration current .
US6854067B1 CLAIM 14 . The system as recited in claim 13 , wherein said b) and said c) of said method are accomplished by said power on reset circuit (output node) .	US5160899A CLAIM 1 . An adaptable MOS current mirror fabricated on a semiconductor substrate , said adaptable MOS current mirror having an input node and an output node (reset circuit) and including : first and second MOS transistors , each having a source , a gate , and a drain ; a first MOS capacitor having first and second electrodes ; the source of said first MOS transistor being connected to a source of fixed voltage , the gate and drain of said first MOS transistor being connected to said input node and to said first electrode of said first MOS capacitor , the source of said second MOS transistor being connected to a source of fixed voltage , the gate of said MOS transistor comprising a floating node connected to said second electrode of said first capacitor , the drain of said second MOS transistor forming said output node ; means for generating a first electrical control signal ; electron removal means coupled to said floating node and responsive to said means for generating said first electrical control signal , for removing electrons from said floating node , said electron removal means operating to vary the rate of removal of electrons from said floating gate in response to the magnitude of said first electrical control signal ; means for selectively supplying a calibration current to said input node during adaptation ; means for generating a second electrical control signal during adaptation ; electron injecting means coupled to said floating node and responsive to said second electrical control signal for injecting electrons on to said floating node , said electron injecting means operating to vary the rate of injection of electrons on to said floating node in response to the magnitude of said second electrical control signal ; whereby the output current of said current mirror is adapted to be equal to said desired output current when its input current is equal to said calibration current .
US6854067B1 CLAIM 16 . The system as recited in claim 15 , wherein said c) further comprises : c1) generating a precision reference voltage , said precision reference voltage independent of said common supply voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals (negative voltage) , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US5160899A CLAIM 5 . An adaptable circuit , communicating with a plurality of current-carrying lines , for indicating the output of the one of said plurality of current-carrying lines through which the most current is flowing , including : a plurality of capacitor coupled MOS current mirrors , each of said current mirrors including an input node , an output node , a driving MOS current mirror transistor and a driven MOS current mirror transistor , the sources of each driving MOS current mirror transistor and each driven MOS current mirror transistor connected to a source of fixed positive voltage , the gate and drain of each of said driving MOS current mirror transistors comprising said input node and connected to a different one of said current carrying lines and to a first electrode of an MOS capacitor , the gate of said driven MOS current mirror transistor connected to a floating node , the second electrode of said MOS capacitor comprising a portion of said floating node , and the drain of said driven MOS current mirror transistor comprising said output node ; a pulldown transistor associated with each of said current mirrors , each of said pulldown transistors having its source connected to a source of fixed negative voltage (power state condition signals) , and its gate connected to a common pulldown gate line ; a pulldown gate bias transistor , having its source connected to said source of negative voltage , its gate connected to a source of bias voltage ; a follower transistor associated with each of said current mirrors , each of said follower transistors having its gate connected to the output of the current mirror with which it is associated , and having a source-drain path connected between a source of fixed voltage and said common pulldown gate line ; means , operable during an operating mode of said circuit , for selectively connecting the drain of said pulldown gate bias transistor to said common pulldown gate line , and for enabling said source-drain path of each said follower transistor ; means , operable during an adapting mode of said circuit , for selectively connecting said common pulldown gate line to a source of fixed voltage , for disabling said source-drain path of said follower transistor , and for adjusting the charge on each floating node in response to the voltage at said output node of said current mirror with which it is associated ; whereby the offset voltages of said circuit can be adapted during said adapting mode of said circuit .
US6854067B1 CLAIM 20 . In a microcontroller having a power on reset circuit (output node) interconnected with a processor a method of dynamically controlling said power state , said method comprising : a) ascertaining a power state powered by a switched mode pump power supply , said switched mode pump power supply interconnected with and responsive to control by said power on reset circuit ; b) programmatically determining desired changes to said power state ; c) intercommunicating between said processor and said power on reset circuit ; d) adjusting said power on reset circuit corresponding to said desired changes to said power state ; e) controlling said switched mode pump power supply according to said d) ; and f) repeating said a) through e) .	US5160899A CLAIM 1 . An adaptable MOS current mirror fabricated on a semiconductor substrate , said adaptable MOS current mirror having an input node and an output node (reset circuit) and including : first and second MOS transistors , each having a source , a gate , and a drain ; a first MOS capacitor having first and second electrodes ; the source of said first MOS transistor being connected to a source of fixed voltage , the gate and drain of said first MOS transistor being connected to said input node and to said first electrode of said first MOS capacitor , the source of said second MOS transistor being connected to a source of fixed voltage , the gate of said MOS transistor comprising a floating node connected to said second electrode of said first capacitor , the drain of said second MOS transistor forming said output node ; means for generating a first electrical control signal ; electron removal means coupled to said floating node and responsive to said means for generating said first electrical control signal , for removing electrons from said floating node , said electron removal means operating to vary the rate of removal of electrons from said floating gate in response to the magnitude of said first electrical control signal ; means for selectively supplying a calibration current to said input node during adaptation ; means for generating a second electrical control signal during adaptation ; electron injecting means coupled to said floating node and responsive to said second electrical control signal for injecting electrons on to said floating node , said electron injecting means operating to vary the rate of injection of electrons on to said floating node in response to the magnitude of said second electrical control signal ; whereby the output current of said current mirror is adapted to be equal to said desired output current when its input current is equal to said calibration current .

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	US5136188A Filed: 1991-08-08 Issued: 1992-08-04 Input/output macrocell for programmable logic device (Original Assignee) SK Hynix Inc (Current Assignee) Intellectual Ventures II LLC Chang W. Ha, Joong K. Moon
US6854067B1 CLAIM 9 . The method as recited in claim 8 , wherein said b2) is performed by a power supply scaler (logic operations) , and wherein said power supply scaler comprises : a) a divider of said common supply voltage ; b) a matrix of multiplexers and registers , and c) an interconnection to said bus .	US5136188A CLAIM 8 . The macrocell as set forth in claim 1 , wherein said input/output means is capable of emulating combinatorial and sequential logic operations (power supply scaler) simultaneously .
US6854067B1 CLAIM 11 . The method as recited in claim 10 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state (d log) corresponding to said status ; f3) programmatically calculating an optimal value for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	US5136188A CLAIM 1 . In a programmable logic device having a programmable logic array adapted to receive a plurality of input signals and to provide a plurality of product terms as output signals through an AND logic which depend on said input signals and information stored in said log (optimal power state) ic array and a macrocell associated with said logic array , said macrocell comprising : first ORing means including a plurality of OR gates , each for ORing a predetermined number of said product terms from said logic array ; demultiplexing means including a plurality of demultiplexors each coupled to output of the corresponding OR gate in said first ORing means , each for generating two or more output signals per one input signal ; second ORing means including a plurality of OR gates each coupled to a corresponding one of outputs of each of said plurality of demultiplexors in said demultiplexing means , each for ORing said corresponding outputs from said plurality of demultiplexors in said demultiplexing means to form a sum data path from said product terms ; and input/output means for receiving data from said plurality of sum data paths for said product terms provided by said plurality of OR gates in said second ORing means to transfer the received data to an output stage or feedback that to said logic array ; whereby said plurality of sum data paths for said product terms are provided in one macrocell .
US6854067B1 CLAIM 12 . The method as recited in claim 11 , wherein said f4) further comprises : communicating each said optimal value to said power supply scaler (logic operations) via said bus ; registering each said optimal value with said matrix of multiplexers and registers ; commanding said matrix of multiplexers and registers to change said independent multiple of said common supply voltage to correspond with said optimal value ; and monitoring said matrix of multiplexers and registers .	US5136188A CLAIM 8 . The macrocell as set forth in claim 1 , wherein said input/output means is capable of emulating combinatorial and sequential logic operations (power supply scaler) simultaneously .
US6854067B1 CLAIM 17 . The system as recited in claim 16 , wherein said b2) is performed by a power supply scaler (logic operations) , wherein said power supply scaler comprises : a) a divider of said common supply voltage ; b) a matrix of multiplexers and registers , and c) an interconnection to said bus .	US5136188A CLAIM 8 . The macrocell as set forth in claim 1 , wherein said input/output means is capable of emulating combinatorial and sequential logic operations (power supply scaler) simultaneously .
US6854067B1 CLAIM 18 . The system as recited in claim 17 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state (d log) corresponding to said status ; f3) programmatically calculating an optimal value for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	US5136188A CLAIM 1 . In a programmable logic device having a programmable logic array adapted to receive a plurality of input signals and to provide a plurality of product terms as output signals through an AND logic which depend on said input signals and information stored in said log (optimal power state) ic array and a macrocell associated with said logic array , said macrocell comprising : first ORing means including a plurality of OR gates , each for ORing a predetermined number of said product terms from said logic array ; demultiplexing means including a plurality of demultiplexors each coupled to output of the corresponding OR gate in said first ORing means , each for generating two or more output signals per one input signal ; second ORing means including a plurality of OR gates each coupled to a corresponding one of outputs of each of said plurality of demultiplexors in said demultiplexing means , each for ORing said corresponding outputs from said plurality of demultiplexors in said demultiplexing means to form a sum data path from said product terms ; and input/output means for receiving data from said plurality of sum data paths for said product terms provided by said plurality of OR gates in said second ORing means to transfer the received data to an output stage or feedback that to said logic array ; whereby said plurality of sum data paths for said product terms are provided in one macrocell .
US6854067B1 CLAIM 19 . The method as recited in claim 18 , wherein said f4) further comprises : communicating each said optimal value to said power supply scaler (logic operations) via said bus ; registering each said optimal value with said matrix of multiplexers and registers ; commanding said matrix of multiplexers and registers to change said independent multiple of said common supply voltage to correspond with said optimal value ; and monitoring said matrix of multiplexers and registers .	US5136188A CLAIM 8 . The macrocell as set forth in claim 1 , wherein said input/output means is capable of emulating combinatorial and sequential logic operations (power supply scaler) simultaneously .

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	US5142247A Filed: 1991-08-06 Issued: 1992-08-25 Multiple frequency phase-locked loop clock generator with stable transitions between frequencies (Original Assignee) Compaq Computer Corp (Current Assignee) Hewlett Packard Development Co LP Henry F. Lada, Jr., Hung Q. Le, James H. Garrett, John M. Gromala
US6854067B1 CLAIM 1 . In a microcontroller with an embedded processor , a switched mode pump power supply and power on reset circuit (second frequency divider, first frequency divider) , a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply , wherein said processor and said power on reset circuit are interconnectedly coupled , and wherein said switched mode pump power supply is interconnectedly coupled with said power on reset circuit and responsive to signals therefrom ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor ; e) controlling certain functions of said microcontroller accordingly .	US5142247A CLAIM 2 . The circuit of claim 1 , wherein said selecting means comprises : a first frequency divider (reset circuit) , having an input coupled to receive said reference clock signal , having a control input coupled to said select input , and having an output coupled to a first input of said phase-locked loop . US5142247A CLAIM 3 . The circuit of claim 2 , wherein said selecting means further comprises : a second frequency divider (reset circuit) , having an input coupled to the output of said phase-locked loop , having a control input coupled to said select input , and having an output coupled to a feedback input of said phase-locked loop .
US6854067B1 CLAIM 2 . The method as recited in claim 1 , further comprising : f) dynamically programming said power on reset circuit (second frequency divider, first frequency divider) .	US5142247A CLAIM 2 . The circuit of claim 1 , wherein said selecting means comprises : a first frequency divider (reset circuit) , having an input coupled to receive said reference clock signal , having a control input coupled to said select input , and having an output coupled to a first input of said phase-locked loop . US5142247A CLAIM 3 . The circuit of claim 2 , wherein said selecting means further comprises : a second frequency divider (reset circuit) , having an input coupled to the output of said phase-locked loop , having a control input coupled to said select input , and having an output coupled to a feedback input of said phase-locked loop .
US6854067B1 CLAIM 3 . The method as recited in claim 2 , wherein said power on reset circuit (second frequency divider, first frequency divider) and said processor are interconnected via a bus .	US5142247A CLAIM 2 . The circuit of claim 1 , wherein said selecting means comprises : a first frequency divider (reset circuit) , having an input coupled to receive said reference clock signal , having a control input coupled to said select input , and having an output coupled to a first input of said phase-locked loop . US5142247A CLAIM 3 . The circuit of claim 2 , wherein said selecting means further comprises : a second frequency divider (reset circuit) , having an input coupled to the output of said phase-locked loop , having a control input coupled to said select input , and having an output coupled to a feedback input of said phase-locked loop .
US6854067B1 CLAIM 4 . The method as recited in claim 3 , wherein said b) and said c) are accomplished by said power on reset circuit (second frequency divider, first frequency divider) .	US5142247A CLAIM 2 . The circuit of claim 1 , wherein said selecting means comprises : a first frequency divider (reset circuit) , having an input coupled to receive said reference clock signal , having a control input coupled to said select input , and having an output coupled to a first input of said phase-locked loop . US5142247A CLAIM 3 . The circuit of claim 2 , wherein said selecting means further comprises : a second frequency divider (reset circuit) , having an input coupled to the output of said phase-locked loop , having a control input coupled to said select input , and having an output coupled to a feedback input of said phase-locked loop .
US6854067B1 CLAIM 11 . The method as recited in claim 10 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state (d log) corresponding to said status ; f3) programmatically calculating an optimal value for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	US5142247A CLAIM 13 . The circuit of claim 12 , wherein said output control circuit comprises : logic circuitry having an input coupled to said select input , and having an output , for monitoring transitions of said select input and for generating a pulse at its output responsive thereto ; and a multiplexer , having a first input coupled to the output of said phase-locked loop , having a second input coupled to said stable clock signal , having a control input coupled to the output of said log (optimal power state) ic circuitry , and having an output for presenting said output of said phase-locked loop or said stable clock signal responsive to signals received at its control input .
US6854067B1 CLAIM 13 . In a microcontroller , a system comprising : a bus ; a processor coupled to said bus ; a power on reset circuit (second frequency divider, first frequency divider) , said processor and said power on reset circuit coupled to said bus and interconnectedly coupled with said processor via said bus ; and a switched mode pump power supply interconnectedly coupled with said power on reset circuit and responsive to signals therefrom wherein said system executes a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor via said bus ; e) controlling certain functions of said microcontroller according to said suitability status ; and f) dynamically programming said power on reset circuit via said bus .	US5142247A CLAIM 2 . The circuit of claim 1 , wherein said selecting means comprises : a first frequency divider (reset circuit) , having an input coupled to receive said reference clock signal , having a control input coupled to said select input , and having an output coupled to a first input of said phase-locked loop . US5142247A CLAIM 3 . The circuit of claim 2 , wherein said selecting means further comprises : a second frequency divider (reset circuit) , having an input coupled to the output of said phase-locked loop , having a control input coupled to said select input , and having an output coupled to a feedback input of said phase-locked loop .
US6854067B1 CLAIM 14 . The system as recited in claim 13 , wherein said b) and said c) of said method are accomplished by said power on reset circuit (second frequency divider, first frequency divider) .	US5142247A CLAIM 2 . The circuit of claim 1 , wherein said selecting means comprises : a first frequency divider (reset circuit) , having an input coupled to receive said reference clock signal , having a control input coupled to said select input , and having an output coupled to a first input of said phase-locked loop . US5142247A CLAIM 3 . The circuit of claim 2 , wherein said selecting means further comprises : a second frequency divider (reset circuit) , having an input coupled to the output of said phase-locked loop , having a control input coupled to said select input , and having an output coupled to a feedback input of said phase-locked loop .
US6854067B1 CLAIM 18 . The system as recited in claim 17 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state (d log) corresponding to said status ; f3) programmatically calculating an optimal value for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	US5142247A CLAIM 13 . The circuit of claim 12 , wherein said output control circuit comprises : logic circuitry having an input coupled to said select input , and having an output , for monitoring transitions of said select input and for generating a pulse at its output responsive thereto ; and a multiplexer , having a first input coupled to the output of said phase-locked loop , having a second input coupled to said stable clock signal , having a control input coupled to the output of said log (optimal power state) ic circuitry , and having an output for presenting said output of said phase-locked loop or said stable clock signal responsive to signals received at its control input .
US6854067B1 CLAIM 20 . In a microcontroller having a power on reset circuit (second frequency divider, first frequency divider) interconnected with a processor a method of dynamically controlling said power state , said method comprising : a) ascertaining a power state powered by a switched mode pump power supply , said switched mode pump power supply interconnected with and responsive to control by said power on reset circuit ; b) programmatically determining desired changes to said power state ; c) intercommunicating between said processor and said power on reset circuit ; d) adjusting said power on reset circuit corresponding to said desired changes to said power state ; e) controlling said switched mode pump power supply according to said d) ; and f) repeating said a) through e) .	US5142247A CLAIM 2 . The circuit of claim 1 , wherein said selecting means comprises : a first frequency divider (reset circuit) , having an input coupled to receive said reference clock signal , having a control input coupled to said select input , and having an output coupled to a first input of said phase-locked loop . US5142247A CLAIM 3 . The circuit of claim 2 , wherein said selecting means further comprises : a second frequency divider (reset circuit) , having an input coupled to the output of said phase-locked loop , having a control input coupled to said select input , and having an output coupled to a feedback input of said phase-locked loop .

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	US5235617A Filed: 1991-06-11 Issued: 1993-08-10 Transmission media driving system (Original Assignee) Digital Equipment Corp (Current Assignee) Enterasys Networks Inc William C. Mallard, Jr.
US6854067B1 CLAIM 1 . In a microcontroller with an embedded processor , a switched mode pump power supply and power on reset circuit , a method of dynamically controlling a plurality of power stability functions (switching signals, control means) for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply , wherein said processor and said power on reset circuit are interconnectedly coupled , and wherein said switched mode pump power supply is interconnectedly coupled with said power on reset circuit and responsive to signals therefrom ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor ; e) controlling certain functions of said microcontroller accordingly .	US5235617A CLAIM 4 . The line driver circuit of claim 1 further including control means (power stability functions) , coupled to receive said drive control signal , for providing switching control signals to said first and second current source means to control the conducting state of each of said first and second current source means . US5235617A CLAIM 5 . The line driver circuit of claim 4 wherein the second current magnitude is twice the first current magnitude ; said first current source means includes first and second bipolar transistors (BPT) each having a collector terminal coupled to said first output terminal , and said second current source means includes third and fourth BPTs each having a collector terminal coupled to said second output terminal ; said line driver circuit further including : a fifth BPT having a collector terminal connected in common with emitter terminals of said first and third BPTs , an emitter terminal of said fifth BPT being coupled to the reference voltage bus ; a sixth BPT having a collector terminal connected in common with emitter terminals of said second and fourth BPTs , an emitter terminal of said sixth BPT being coupled to the reference voltage bus ; base terminals of said fifth and sixth BPTs being coupled in common to receive a predetermined voltage ; and base terminals of said first , second , third and fourth BPTs being coupled to receive said switching signals (power stability functions) .
US6854067B1 CLAIM 6 . The method as recited in claim 5 , wherein said c) further comprises : c1) generating a precision reference voltage (said switch) ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US5235617A CLAIM 5 . The line driver circuit of claim 4 wherein the second current magnitude is twice the first current magnitude ; said first current source means includes first and second bipolar transistors (BPT) each having a collector terminal coupled to said first output terminal , and said second current source means includes third and fourth BPTs each having a collector terminal coupled to said second output terminal ; said line driver circuit further including : a fifth BPT having a collector terminal connected in common with emitter terminals of said first and third BPTs , an emitter terminal of said fifth BPT being coupled to the reference voltage bus ; a sixth BPT having a collector terminal connected in common with emitter terminals of said second and fourth BPTs , an emitter terminal of said sixth BPT being coupled to the reference voltage bus ; base terminals of said fifth and sixth BPTs being coupled in common to receive a predetermined voltage ; and base terminals of said first , second , third and fourth BPTs being coupled to receive said switch (precision reference voltage) ing signals .
US6854067B1 CLAIM 7 . The method as recited in claim 6 , wherein said precision reference voltage (said switch) is independent of said common supply voltage .	US5235617A CLAIM 5 . The line driver circuit of claim 4 wherein the second current magnitude is twice the first current magnitude ; said first current source means includes first and second bipolar transistors (BPT) each having a collector terminal coupled to said first output terminal , and said second current source means includes third and fourth BPTs each having a collector terminal coupled to said second output terminal ; said line driver circuit further including : a fifth BPT having a collector terminal connected in common with emitter terminals of said first and third BPTs , an emitter terminal of said fifth BPT being coupled to the reference voltage bus ; a sixth BPT having a collector terminal connected in common with emitter terminals of said second and fourth BPTs , an emitter terminal of said sixth BPT being coupled to the reference voltage bus ; base terminals of said fifth and sixth BPTs being coupled in common to receive a predetermined voltage ; and base terminals of said first , second , third and fourth BPTs being coupled to receive said switch (precision reference voltage) ing signals .
US6854067B1 CLAIM 11 . The method as recited in claim 10 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state (one end, d log) corresponding to said status ; f3) programmatically calculating an optimal value for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	US5235617A CLAIM 8 . The line driver circuit of claim 7 wherein said first differential amplifier comprises emitter coupled log (optimal power state) ic circuitry and includes a logic zero voltage reference terminal ; a third resistor coupled to the logic zero voltage reference terminal ; a fourth resistor coupled between the first resistor and the reference voltage bus ; a capacitor coupled at one end (optimal power state) to a junction point between said third and fourth resistors and at its other end to the reference voltage bus ; and said base terminals of said fifth and sixth BPTs being coupled to the junction point to receive the predetermined voltage .
US6854067B1 CLAIM 13 . In a microcontroller , a system comprising : a bus ; a processor coupled to said bus ; a power on reset circuit , said processor and said power on reset circuit coupled to said bus and interconnectedly coupled with said processor via said bus ; and a switched mode pump power supply interconnectedly coupled with said power on reset circuit and responsive to signals therefrom wherein said system executes a method of dynamically controlling a plurality of power stability functions (switching signals, control means) for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor via said bus ; e) controlling certain functions of said microcontroller according to said suitability status ; and f) dynamically programming said power on reset circuit via said bus .	US5235617A CLAIM 4 . The line driver circuit of claim 1 further including control means (power stability functions) , coupled to receive said drive control signal , for providing switching control signals to said first and second current source means to control the conducting state of each of said first and second current source means . US5235617A CLAIM 5 . The line driver circuit of claim 4 wherein the second current magnitude is twice the first current magnitude ; said first current source means includes first and second bipolar transistors (BPT) each having a collector terminal coupled to said first output terminal , and said second current source means includes third and fourth BPTs each having a collector terminal coupled to said second output terminal ; said line driver circuit further including : a fifth BPT having a collector terminal connected in common with emitter terminals of said first and third BPTs , an emitter terminal of said fifth BPT being coupled to the reference voltage bus ; a sixth BPT having a collector terminal connected in common with emitter terminals of said second and fourth BPTs , an emitter terminal of said sixth BPT being coupled to the reference voltage bus ; base terminals of said fifth and sixth BPTs being coupled in common to receive a predetermined voltage ; and base terminals of said first , second , third and fourth BPTs being coupled to receive said switching signals (power stability functions) .
US6854067B1 CLAIM 16 . The system as recited in claim 15 , wherein said c) further comprises : c1) generating a precision reference voltage (said switch) , said precision reference voltage independent of said common supply voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US5235617A CLAIM 5 . The line driver circuit of claim 4 wherein the second current magnitude is twice the first current magnitude ; said first current source means includes first and second bipolar transistors (BPT) each having a collector terminal coupled to said first output terminal , and said second current source means includes third and fourth BPTs each having a collector terminal coupled to said second output terminal ; said line driver circuit further including : a fifth BPT having a collector terminal connected in common with emitter terminals of said first and third BPTs , an emitter terminal of said fifth BPT being coupled to the reference voltage bus ; a sixth BPT having a collector terminal connected in common with emitter terminals of said second and fourth BPTs , an emitter terminal of said sixth BPT being coupled to the reference voltage bus ; base terminals of said fifth and sixth BPTs being coupled in common to receive a predetermined voltage ; and base terminals of said first , second , third and fourth BPTs being coupled to receive said switch (precision reference voltage) ing signals .
US6854067B1 CLAIM 18 . The system as recited in claim 17 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state (one end, d log) corresponding to said status ; f3) programmatically calculating an optimal value for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	US5235617A CLAIM 8 . The line driver circuit of claim 7 wherein said first differential amplifier comprises emitter coupled log (optimal power state) ic circuitry and includes a logic zero voltage reference terminal ; a third resistor coupled to the logic zero voltage reference terminal ; a fourth resistor coupled between the first resistor and the reference voltage bus ; a capacitor coupled at one end (optimal power state) to a junction point between said third and fourth resistors and at its other end to the reference voltage bus ; and said base terminals of said fifth and sixth BPTs being coupled to the junction point to receive the predetermined voltage .

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	US5166562A Filed: 1991-05-09 Issued: 1992-11-24 Writable analog reference voltage storage device (Original Assignee) Synaptics Inc (Current Assignee) Synaptics Inc Timothy P. Allen, Adam K. Greenblatt, Carver A. Mead, Janeen D. W. Anderson
US6854067B1 CLAIM 1 . In a microcontroller with an embedded processor , a switched mode pump power supply and power on reset circuit (output node) , a method of dynamically controlling a plurality of power stability functions (control means) for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply , wherein said processor and said power on reset circuit are interconnectedly coupled , and wherein said switched mode pump power supply is interconnectedly coupled with said power on reset circuit and responsive to signals therefrom ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor ; e) controlling certain functions of said microcontroller accordingly .	US5166562A CLAIM 5 . The circuit of claim 1 , further including a bias circuit comprising : a first capacitor having a first plate and a second plate ; a second capacitor having a first plate and a second plate ; a diode-connected MOS transistor of a first conductivity type having a source connected to a first voltage rail and to said first plate of said first capacitor , and a gate and drain connected to said second plate of said first capacitor ; an MOS transistor of said first conductivity type having a gate connected to said analog output voltage bus and a source connected to the drain of said diode-connected MOS transistor of said first conductivity type to form a first bias output node (reset circuit) ; and a diode-connected MOS transistor of a second conductivity type opposite to said first conductivity type having a source connected to a second voltage rail and to said first plate of said second capacitor , and a gate and drain connected to said second plate of said second capacitor and to the drain of said MOS transistor of said first conductivity type to form a second bias output note . US5166562A CLAIM 7 . A circuit disposed on a semiconductor substrate for generating N analog voltage signals in a semiconductor integrated circuit disposed on said semiconductor substrate , including : N analog floating gate storage devices disposed on said semiconductor substrate , each of said analog floating gate storage devices including a floating gate ; a non-avalanche hot electron injection means associated with each of said analog floating gate device for injecting electrons onto its floating gate ; digital control means (power stability functions) for selectively activating each electron injection means ; means associated with each of said analog floating gate devices for removing electrons from its floating gate ; an analog output voltage bus associated with each of said analog floating gate devices , each of said analog output voltage busses having a capacitance associated therewith ; and a high input impedance follower amplifier associated with each of said analog floating gate devices , each of said follower amplifiers having an input connected to its floating gate and an output connected to its analog output voltage bus .
US6854067B1 CLAIM 2 . The method as recited in claim 1 , further comprising : f) dynamically programming said power on reset circuit (output node) .	US5166562A CLAIM 5 . The circuit of claim 1 , further including a bias circuit comprising : a first capacitor having a first plate and a second plate ; a second capacitor having a first plate and a second plate ; a diode-connected MOS transistor of a first conductivity type having a source connected to a first voltage rail and to said first plate of said first capacitor , and a gate and drain connected to said second plate of said first capacitor ; an MOS transistor of said first conductivity type having a gate connected to said analog output voltage bus and a source connected to the drain of said diode-connected MOS transistor of said first conductivity type to form a first bias output node (reset circuit) ; and a diode-connected MOS transistor of a second conductivity type opposite to said first conductivity type having a source connected to a second voltage rail and to said first plate of said second capacitor , and a gate and drain connected to said second plate of said second capacitor and to the drain of said MOS transistor of said first conductivity type to form a second bias output note .
US6854067B1 CLAIM 3 . The method as recited in claim 2 , wherein said power on reset circuit (output node) and said processor are interconnected via a bus .	US5166562A CLAIM 5 . The circuit of claim 1 , further including a bias circuit comprising : a first capacitor having a first plate and a second plate ; a second capacitor having a first plate and a second plate ; a diode-connected MOS transistor of a first conductivity type having a source connected to a first voltage rail and to said first plate of said first capacitor , and a gate and drain connected to said second plate of said first capacitor ; an MOS transistor of said first conductivity type having a gate connected to said analog output voltage bus and a source connected to the drain of said diode-connected MOS transistor of said first conductivity type to form a first bias output node (reset circuit) ; and a diode-connected MOS transistor of a second conductivity type opposite to said first conductivity type having a source connected to a second voltage rail and to said first plate of said second capacitor , and a gate and drain connected to said second plate of said second capacitor and to the drain of said MOS transistor of said first conductivity type to form a second bias output note .
US6854067B1 CLAIM 4 . The method as recited in claim 3 , wherein said b) and said c) are accomplished by said power on reset circuit (output node) .	US5166562A CLAIM 5 . The circuit of claim 1 , further including a bias circuit comprising : a first capacitor having a first plate and a second plate ; a second capacitor having a first plate and a second plate ; a diode-connected MOS transistor of a first conductivity type having a source connected to a first voltage rail and to said first plate of said first capacitor , and a gate and drain connected to said second plate of said first capacitor ; an MOS transistor of said first conductivity type having a gate connected to said analog output voltage bus and a source connected to the drain of said diode-connected MOS transistor of said first conductivity type to form a first bias output node (reset circuit) ; and a diode-connected MOS transistor of a second conductivity type opposite to said first conductivity type having a source connected to a second voltage rail and to said first plate of said second capacitor , and a gate and drain connected to said second plate of said second capacitor and to the drain of said MOS transistor of said first conductivity type to form a second bias output note .
US6854067B1 CLAIM 6 . The method as recited in claim 5 , wherein said c) further comprises : c1) generating a precision reference voltage (gate device) ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US5166562A CLAIM 1 . A circuit disposed on a semiconductor substrate for generating an analog voltage signal in a semiconductor integrated circuit disposed on said semiconductor substrate , including : an analog floating gate storage device disposed on said semiconductor substrate , said analog floating gate storage device including a floating gate ; a non-avalanche hot electron injection means associated with said analog floating gate device (precision reference voltage) for injecting electrons onto said floating gate ; means associated with said analog floating gate device for removing electrons from said floating gate ; an analog output voltage bus ; and a high input impedance follower amplifier having an input connected to said floating gate and an output connected to said analog output voltage bus .
US6854067B1 CLAIM 7 . The method as recited in claim 6 , wherein said precision reference voltage (gate device) is independent of said common supply voltage .	US5166562A CLAIM 1 . A circuit disposed on a semiconductor substrate for generating an analog voltage signal in a semiconductor integrated circuit disposed on said semiconductor substrate , including : an analog floating gate storage device disposed on said semiconductor substrate , said analog floating gate storage device including a floating gate ; a non-avalanche hot electron injection means associated with said analog floating gate device (precision reference voltage) for injecting electrons onto said floating gate ; means associated with said analog floating gate device for removing electrons from said floating gate ; an analog output voltage bus ; and a high input impedance follower amplifier having an input connected to said floating gate and an output connected to said analog output voltage bus .
US6854067B1 CLAIM 13 . In a microcontroller , a system comprising : a bus ; a processor coupled to said bus ; a power on reset circuit (output node) , said processor and said power on reset circuit coupled to said bus and interconnectedly coupled with said processor via said bus ; and a switched mode pump power supply interconnectedly coupled with said power on reset circuit and responsive to signals therefrom wherein said system executes a method of dynamically controlling a plurality of power stability functions (control means) for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor via said bus ; e) controlling certain functions of said microcontroller according to said suitability status ; and f) dynamically programming said power on reset circuit via said bus .	US5166562A CLAIM 5 . The circuit of claim 1 , further including a bias circuit comprising : a first capacitor having a first plate and a second plate ; a second capacitor having a first plate and a second plate ; a diode-connected MOS transistor of a first conductivity type having a source connected to a first voltage rail and to said first plate of said first capacitor , and a gate and drain connected to said second plate of said first capacitor ; an MOS transistor of said first conductivity type having a gate connected to said analog output voltage bus and a source connected to the drain of said diode-connected MOS transistor of said first conductivity type to form a first bias output node (reset circuit) ; and a diode-connected MOS transistor of a second conductivity type opposite to said first conductivity type having a source connected to a second voltage rail and to said first plate of said second capacitor , and a gate and drain connected to said second plate of said second capacitor and to the drain of said MOS transistor of said first conductivity type to form a second bias output note . US5166562A CLAIM 7 . A circuit disposed on a semiconductor substrate for generating N analog voltage signals in a semiconductor integrated circuit disposed on said semiconductor substrate , including : N analog floating gate storage devices disposed on said semiconductor substrate , each of said analog floating gate storage devices including a floating gate ; a non-avalanche hot electron injection means associated with each of said analog floating gate device for injecting electrons onto its floating gate ; digital control means (power stability functions) for selectively activating each electron injection means ; means associated with each of said analog floating gate devices for removing electrons from its floating gate ; an analog output voltage bus associated with each of said analog floating gate devices , each of said analog output voltage busses having a capacitance associated therewith ; and a high input impedance follower amplifier associated with each of said analog floating gate devices , each of said follower amplifiers having an input connected to its floating gate and an output connected to its analog output voltage bus .
US6854067B1 CLAIM 14 . The system as recited in claim 13 , wherein said b) and said c) of said method are accomplished by said power on reset circuit (output node) .	US5166562A CLAIM 5 . The circuit of claim 1 , further including a bias circuit comprising : a first capacitor having a first plate and a second plate ; a second capacitor having a first plate and a second plate ; a diode-connected MOS transistor of a first conductivity type having a source connected to a first voltage rail and to said first plate of said first capacitor , and a gate and drain connected to said second plate of said first capacitor ; an MOS transistor of said first conductivity type having a gate connected to said analog output voltage bus and a source connected to the drain of said diode-connected MOS transistor of said first conductivity type to form a first bias output node (reset circuit) ; and a diode-connected MOS transistor of a second conductivity type opposite to said first conductivity type having a source connected to a second voltage rail and to said first plate of said second capacitor , and a gate and drain connected to said second plate of said second capacitor and to the drain of said MOS transistor of said first conductivity type to form a second bias output note .
US6854067B1 CLAIM 16 . The system as recited in claim 15 , wherein said c) further comprises : c1) generating a precision reference voltage (gate device) , said precision reference voltage independent of said common supply voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US5166562A CLAIM 1 . A circuit disposed on a semiconductor substrate for generating an analog voltage signal in a semiconductor integrated circuit disposed on said semiconductor substrate , including : an analog floating gate storage device disposed on said semiconductor substrate , said analog floating gate storage device including a floating gate ; a non-avalanche hot electron injection means associated with said analog floating gate device (precision reference voltage) for injecting electrons onto said floating gate ; means associated with said analog floating gate device for removing electrons from said floating gate ; an analog output voltage bus ; and a high input impedance follower amplifier having an input connected to said floating gate and an output connected to said analog output voltage bus .
US6854067B1 CLAIM 20 . In a microcontroller having a power on reset circuit (output node) interconnected with a processor a method of dynamically controlling said power state , said method comprising : a) ascertaining a power state powered by a switched mode pump power supply , said switched mode pump power supply interconnected with and responsive to control by said power on reset circuit ; b) programmatically determining desired changes to said power state ; c) intercommunicating between said processor and said power on reset circuit ; d) adjusting said power on reset circuit corresponding to said desired changes to said power state ; e) controlling said switched mode pump power supply according to said d) ; and f) repeating said a) through e) .	US5166562A CLAIM 5 . The circuit of claim 1 , further including a bias circuit comprising : a first capacitor having a first plate and a second plate ; a second capacitor having a first plate and a second plate ; a diode-connected MOS transistor of a first conductivity type having a source connected to a first voltage rail and to said first plate of said first capacitor , and a gate and drain connected to said second plate of said first capacitor ; an MOS transistor of said first conductivity type having a gate connected to said analog output voltage bus and a source connected to the drain of said diode-connected MOS transistor of said first conductivity type to form a first bias output node (reset circuit) ; and a diode-connected MOS transistor of a second conductivity type opposite to said first conductivity type having a source connected to a second voltage rail and to said first plate of said second capacitor , and a gate and drain connected to said second plate of said second capacitor and to the drain of said MOS transistor of said first conductivity type to form a second bias output note .

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	US5146106A Filed: 1991-02-05 Issued: 1992-09-08 CMOS winner-take all circuit with offset adaptation (Original Assignee) Synaptics Inc (Current Assignee) Synaptics Inc Janeen D. W. Anderson, Carver A. Mead, Timothy P. Allen, Michael F. Wall
US6854067B1 CLAIM 1 . In a microcontroller with an embedded processor , a switched mode pump power supply and power on reset circuit (output node) , a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply , wherein said processor and said power on reset circuit are interconnectedly coupled , and wherein said switched mode pump power supply is interconnectedly coupled with said power on reset circuit and responsive to signals therefrom ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor ; e) controlling certain functions of said microcontroller accordingly .	US5146106A CLAIM 1 . An adaptable circuit , communicating with a plurality of current-carrying lines , for indicating the output of the one of said plurality of current-carrying lines through which the most current is flowing , including : a plurality of MOS current mirrors , each of said current mirrors including an input node , an output node (reset circuit) , a driving MOS current mirror transistor of a first conductivity type and a driven MOS current mirror transistor of said first conductivity type , the sources of said driving MOS current mirror transistor and said driven MOS current mirror transistor connected to a first voltage rail , the gate and drain of each of said driving MOS current mirror transistors comprising said input node and connected to a different one of said current carrying lines and to a first electrode of a capacitor , the gate of said driven MOS current mirror transistor connected to a floating node , a second electrode of said capacitor comprising a portion of said floating node , the drain of said driven MOS current mirror transistor comprising said output node ; a pulldown transistor of a second conductivity type opposite to said first conductivity type associated with each of said current mirrors , each of said pulldown transistors having its source connected to a second voltage rail , and its gate connected to a common pulldown gate line ; a pulldown gate bias transistor of said second conductivity type , having its source connected to said second voltage rail , its gate connected to a source of bias voltage ; a follower transistor of said second conductivity type associated with each of said current mirrors , having its gate connected to the output of the current mirror with which it is associated , and having a source-drain path connected between a source of fixed voltage and said common pulldown gate line ; means for selectively connecting the drain of said pulldown gate bias transistor to said common pulldown gate line , and for enabling said source-drain path of said follower transistor to conduct during an operating mode of said circuit , and for connecting said common pulldown gate line to a source of fixed voltage , and for disabling said source-drain path of said follower transistor during an adapting mode of said circuit ; and means for adjusting the charge on said floating node in response to the output current of said current mirror during said adapting mode of said circuit ; whereby the offset voltages of said circuit can be adapted during said adapting mode of said circuit .
US6854067B1 CLAIM 2 . The method as recited in claim 1 , further comprising : f) dynamically programming said power on reset circuit (output node) .	US5146106A CLAIM 1 . An adaptable circuit , communicating with a plurality of current-carrying lines , for indicating the output of the one of said plurality of current-carrying lines through which the most current is flowing , including : a plurality of MOS current mirrors , each of said current mirrors including an input node , an output node (reset circuit) , a driving MOS current mirror transistor of a first conductivity type and a driven MOS current mirror transistor of said first conductivity type , the sources of said driving MOS current mirror transistor and said driven MOS current mirror transistor connected to a first voltage rail , the gate and drain of each of said driving MOS current mirror transistors comprising said input node and connected to a different one of said current carrying lines and to a first electrode of a capacitor , the gate of said driven MOS current mirror transistor connected to a floating node , a second electrode of said capacitor comprising a portion of said floating node , the drain of said driven MOS current mirror transistor comprising said output node ; a pulldown transistor of a second conductivity type opposite to said first conductivity type associated with each of said current mirrors , each of said pulldown transistors having its source connected to a second voltage rail , and its gate connected to a common pulldown gate line ; a pulldown gate bias transistor of said second conductivity type , having its source connected to said second voltage rail , its gate connected to a source of bias voltage ; a follower transistor of said second conductivity type associated with each of said current mirrors , having its gate connected to the output of the current mirror with which it is associated , and having a source-drain path connected between a source of fixed voltage and said common pulldown gate line ; means for selectively connecting the drain of said pulldown gate bias transistor to said common pulldown gate line , and for enabling said source-drain path of said follower transistor to conduct during an operating mode of said circuit , and for connecting said common pulldown gate line to a source of fixed voltage , and for disabling said source-drain path of said follower transistor during an adapting mode of said circuit ; and means for adjusting the charge on said floating node in response to the output current of said current mirror during said adapting mode of said circuit ; whereby the offset voltages of said circuit can be adapted during said adapting mode of said circuit .
US6854067B1 CLAIM 3 . The method as recited in claim 2 , wherein said power on reset circuit (output node) and said processor are interconnected via a bus .	US5146106A CLAIM 1 . An adaptable circuit , communicating with a plurality of current-carrying lines , for indicating the output of the one of said plurality of current-carrying lines through which the most current is flowing , including : a plurality of MOS current mirrors , each of said current mirrors including an input node , an output node (reset circuit) , a driving MOS current mirror transistor of a first conductivity type and a driven MOS current mirror transistor of said first conductivity type , the sources of said driving MOS current mirror transistor and said driven MOS current mirror transistor connected to a first voltage rail , the gate and drain of each of said driving MOS current mirror transistors comprising said input node and connected to a different one of said current carrying lines and to a first electrode of a capacitor , the gate of said driven MOS current mirror transistor connected to a floating node , a second electrode of said capacitor comprising a portion of said floating node , the drain of said driven MOS current mirror transistor comprising said output node ; a pulldown transistor of a second conductivity type opposite to said first conductivity type associated with each of said current mirrors , each of said pulldown transistors having its source connected to a second voltage rail , and its gate connected to a common pulldown gate line ; a pulldown gate bias transistor of said second conductivity type , having its source connected to said second voltage rail , its gate connected to a source of bias voltage ; a follower transistor of said second conductivity type associated with each of said current mirrors , having its gate connected to the output of the current mirror with which it is associated , and having a source-drain path connected between a source of fixed voltage and said common pulldown gate line ; means for selectively connecting the drain of said pulldown gate bias transistor to said common pulldown gate line , and for enabling said source-drain path of said follower transistor to conduct during an operating mode of said circuit , and for connecting said common pulldown gate line to a source of fixed voltage , and for disabling said source-drain path of said follower transistor during an adapting mode of said circuit ; and means for adjusting the charge on said floating node in response to the output current of said current mirror during said adapting mode of said circuit ; whereby the offset voltages of said circuit can be adapted during said adapting mode of said circuit .
US6854067B1 CLAIM 4 . The method as recited in claim 3 , wherein said b) and said c) are accomplished by said power on reset circuit (output node) .	US5146106A CLAIM 1 . An adaptable circuit , communicating with a plurality of current-carrying lines , for indicating the output of the one of said plurality of current-carrying lines through which the most current is flowing , including : a plurality of MOS current mirrors , each of said current mirrors including an input node , an output node (reset circuit) , a driving MOS current mirror transistor of a first conductivity type and a driven MOS current mirror transistor of said first conductivity type , the sources of said driving MOS current mirror transistor and said driven MOS current mirror transistor connected to a first voltage rail , the gate and drain of each of said driving MOS current mirror transistors comprising said input node and connected to a different one of said current carrying lines and to a first electrode of a capacitor , the gate of said driven MOS current mirror transistor connected to a floating node , a second electrode of said capacitor comprising a portion of said floating node , the drain of said driven MOS current mirror transistor comprising said output node ; a pulldown transistor of a second conductivity type opposite to said first conductivity type associated with each of said current mirrors , each of said pulldown transistors having its source connected to a second voltage rail , and its gate connected to a common pulldown gate line ; a pulldown gate bias transistor of said second conductivity type , having its source connected to said second voltage rail , its gate connected to a source of bias voltage ; a follower transistor of said second conductivity type associated with each of said current mirrors , having its gate connected to the output of the current mirror with which it is associated , and having a source-drain path connected between a source of fixed voltage and said common pulldown gate line ; means for selectively connecting the drain of said pulldown gate bias transistor to said common pulldown gate line , and for enabling said source-drain path of said follower transistor to conduct during an operating mode of said circuit , and for connecting said common pulldown gate line to a source of fixed voltage , and for disabling said source-drain path of said follower transistor during an adapting mode of said circuit ; and means for adjusting the charge on said floating node in response to the output current of said current mirror during said adapting mode of said circuit ; whereby the offset voltages of said circuit can be adapted during said adapting mode of said circuit .
US6854067B1 CLAIM 6 . The method as recited in claim 5 , wherein said c) further comprises : c1) generating a precision reference voltage (second layer) ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US5146106A CLAIM 6 . The adaptable circuit of claim 2 wherein said floating node is a layer of polysilicon and said electron removal means includes a second layer (precision reference voltage) of polysilicon separated from said floating node by a layer of SiO 2 .
US6854067B1 CLAIM 7 . The method as recited in claim 6 , wherein said precision reference voltage (second layer) is independent of said common supply voltage .	US5146106A CLAIM 6 . The adaptable circuit of claim 2 wherein said floating node is a layer of polysilicon and said electron removal means includes a second layer (precision reference voltage) of polysilicon separated from said floating node by a layer of SiO 2 .
US6854067B1 CLAIM 13 . In a microcontroller , a system comprising : a bus ; a processor coupled to said bus ; a power on reset circuit (output node) , said processor and said power on reset circuit coupled to said bus and interconnectedly coupled with said processor via said bus ; and a switched mode pump power supply interconnectedly coupled with said power on reset circuit and responsive to signals therefrom wherein said system executes a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor via said bus ; e) controlling certain functions of said microcontroller according to said suitability status ; and f) dynamically programming said power on reset circuit via said bus .	US5146106A CLAIM 1 . An adaptable circuit , communicating with a plurality of current-carrying lines , for indicating the output of the one of said plurality of current-carrying lines through which the most current is flowing , including : a plurality of MOS current mirrors , each of said current mirrors including an input node , an output node (reset circuit) , a driving MOS current mirror transistor of a first conductivity type and a driven MOS current mirror transistor of said first conductivity type , the sources of said driving MOS current mirror transistor and said driven MOS current mirror transistor connected to a first voltage rail , the gate and drain of each of said driving MOS current mirror transistors comprising said input node and connected to a different one of said current carrying lines and to a first electrode of a capacitor , the gate of said driven MOS current mirror transistor connected to a floating node , a second electrode of said capacitor comprising a portion of said floating node , the drain of said driven MOS current mirror transistor comprising said output node ; a pulldown transistor of a second conductivity type opposite to said first conductivity type associated with each of said current mirrors , each of said pulldown transistors having its source connected to a second voltage rail , and its gate connected to a common pulldown gate line ; a pulldown gate bias transistor of said second conductivity type , having its source connected to said second voltage rail , its gate connected to a source of bias voltage ; a follower transistor of said second conductivity type associated with each of said current mirrors , having its gate connected to the output of the current mirror with which it is associated , and having a source-drain path connected between a source of fixed voltage and said common pulldown gate line ; means for selectively connecting the drain of said pulldown gate bias transistor to said common pulldown gate line , and for enabling said source-drain path of said follower transistor to conduct during an operating mode of said circuit , and for connecting said common pulldown gate line to a source of fixed voltage , and for disabling said source-drain path of said follower transistor during an adapting mode of said circuit ; and means for adjusting the charge on said floating node in response to the output current of said current mirror during said adapting mode of said circuit ; whereby the offset voltages of said circuit can be adapted during said adapting mode of said circuit .
US6854067B1 CLAIM 14 . The system as recited in claim 13 , wherein said b) and said c) of said method are accomplished by said power on reset circuit (output node) .	US5146106A CLAIM 1 . An adaptable circuit , communicating with a plurality of current-carrying lines , for indicating the output of the one of said plurality of current-carrying lines through which the most current is flowing , including : a plurality of MOS current mirrors , each of said current mirrors including an input node , an output node (reset circuit) , a driving MOS current mirror transistor of a first conductivity type and a driven MOS current mirror transistor of said first conductivity type , the sources of said driving MOS current mirror transistor and said driven MOS current mirror transistor connected to a first voltage rail , the gate and drain of each of said driving MOS current mirror transistors comprising said input node and connected to a different one of said current carrying lines and to a first electrode of a capacitor , the gate of said driven MOS current mirror transistor connected to a floating node , a second electrode of said capacitor comprising a portion of said floating node , the drain of said driven MOS current mirror transistor comprising said output node ; a pulldown transistor of a second conductivity type opposite to said first conductivity type associated with each of said current mirrors , each of said pulldown transistors having its source connected to a second voltage rail , and its gate connected to a common pulldown gate line ; a pulldown gate bias transistor of said second conductivity type , having its source connected to said second voltage rail , its gate connected to a source of bias voltage ; a follower transistor of said second conductivity type associated with each of said current mirrors , having its gate connected to the output of the current mirror with which it is associated , and having a source-drain path connected between a source of fixed voltage and said common pulldown gate line ; means for selectively connecting the drain of said pulldown gate bias transistor to said common pulldown gate line , and for enabling said source-drain path of said follower transistor to conduct during an operating mode of said circuit , and for connecting said common pulldown gate line to a source of fixed voltage , and for disabling said source-drain path of said follower transistor during an adapting mode of said circuit ; and means for adjusting the charge on said floating node in response to the output current of said current mirror during said adapting mode of said circuit ; whereby the offset voltages of said circuit can be adapted during said adapting mode of said circuit .
US6854067B1 CLAIM 16 . The system as recited in claim 15 , wherein said c) further comprises : c1) generating a precision reference voltage (second layer) , said precision reference voltage independent of said common supply voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US5146106A CLAIM 6 . The adaptable circuit of claim 2 wherein said floating node is a layer of polysilicon and said electron removal means includes a second layer (precision reference voltage) of polysilicon separated from said floating node by a layer of SiO 2 .
US6854067B1 CLAIM 20 . In a microcontroller having a power on reset circuit (output node) interconnected with a processor a method of dynamically controlling said power state , said method comprising : a) ascertaining a power state powered by a switched mode pump power supply , said switched mode pump power supply interconnected with and responsive to control by said power on reset circuit ; b) programmatically determining desired changes to said power state ; c) intercommunicating between said processor and said power on reset circuit ; d) adjusting said power on reset circuit corresponding to said desired changes to said power state ; e) controlling said switched mode pump power supply according to said d) ; and f) repeating said a) through e) .	US5146106A CLAIM 1 . An adaptable circuit , communicating with a plurality of current-carrying lines , for indicating the output of the one of said plurality of current-carrying lines through which the most current is flowing , including : a plurality of MOS current mirrors , each of said current mirrors including an input node , an output node (reset circuit) , a driving MOS current mirror transistor of a first conductivity type and a driven MOS current mirror transistor of said first conductivity type , the sources of said driving MOS current mirror transistor and said driven MOS current mirror transistor connected to a first voltage rail , the gate and drain of each of said driving MOS current mirror transistors comprising said input node and connected to a different one of said current carrying lines and to a first electrode of a capacitor , the gate of said driven MOS current mirror transistor connected to a floating node , a second electrode of said capacitor comprising a portion of said floating node , the drain of said driven MOS current mirror transistor comprising said output node ; a pulldown transistor of a second conductivity type opposite to said first conductivity type associated with each of said current mirrors , each of said pulldown transistors having its source connected to a second voltage rail , and its gate connected to a common pulldown gate line ; a pulldown gate bias transistor of said second conductivity type , having its source connected to said second voltage rail , its gate connected to a source of bias voltage ; a follower transistor of said second conductivity type associated with each of said current mirrors , having its gate connected to the output of the current mirror with which it is associated , and having a source-drain path connected between a source of fixed voltage and said common pulldown gate line ; means for selectively connecting the drain of said pulldown gate bias transistor to said common pulldown gate line , and for enabling said source-drain path of said follower transistor to conduct during an operating mode of said circuit , and for connecting said common pulldown gate line to a source of fixed voltage , and for disabling said source-drain path of said follower transistor during an adapting mode of said circuit ; and means for adjusting the charge on said floating node in response to the output current of said current mirror during said adapting mode of said circuit ; whereby the offset voltages of said circuit can be adapted during said adapting mode of said circuit .

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	WO9210032A1 Filed: 1990-11-26 Issued: 1992-06-11 Temperature-sensing control system and method for integrated circuits (Original Assignee) Adaptive Solutions, Inc. Stephen G. Owens
US6854067B1 CLAIM 1 . In a microcontroller with an embedded processor , a switched mode pump power supply and power on reset circuit , a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply , wherein said processor and said power on reset circuit are interconnectedly coupled , and wherein said switched mode pump power supply is interconnectedly coupled with said power on reset circuit and responsive to signals therefrom ; b) sensing a power state condition (predetermined temperature) of said power state ; c) determining a suitability status (determined relationship) of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor ; e) controlling certain functions of said microcontroller accordingly .	WO9210032A1 CLAIM 1 . A temperature-sensing control system for use on an integrated circuit comprising : an integrated circuit (14) having a sequence controller (12) operatively connected thereto , said sequence controller (12) providing instructions and/or data to said integrated circuit (14) which performs operations according to said instructions on said data ; temperature sensor means (20) thermally connected to the integrated circuit (14) and means associated with said temperature sensor means therewith for creating a temperature signal ; and hold means (36) associated with said sequence controller (12) for slowing operation of said integrated circuit (14) by a predetermined amount if said temperature signal has a predetermined relationship (suitability status) to a first predetermined value and for slowing operation of said integrated circuit (14) by a greater predetermined amount if said temperature signal has a predetermined relationship to a second predetermined value , which second predetermined value is higher than said first predetermined value . WO9210032A1 CLAIM 8 . The temperature-sensing control system of claim 5 wherein said hold means (36) includes a mechanism for sending noop instructions to said integrated circuit (14) for a predetermined number of system cycles at a predetermined frequency upon receipt of a first predetermined temperature (power state condition, power supply scaler) value .
US6854067B1 CLAIM 6 . The method as recited in claim 5 , wherein said c) further comprises : c1) generating a precision reference voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition (predetermined temperature) signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	WO9210032A1 CLAIM 8 . The temperature-sensing control system of claim 5 wherein said hold means (36) includes a mechanism for sending noop instructions to said integrated circuit (14) for a predetermined number of system cycles at a predetermined frequency upon receipt of a first predetermined temperature (power state condition, power supply scaler) value .
US6854067B1 CLAIM 9 . The method as recited in claim 8 , wherein said b2) is performed by a power supply scaler (predetermined temperature) , and wherein said power supply scaler comprises : a) a divider of said common supply voltage ; b) a matrix of multiplexers and registers , and c) an interconnection to said bus .	WO9210032A1 CLAIM 8 . The temperature-sensing control system of claim 5 wherein said hold means (36) includes a mechanism for sending noop instructions to said integrated circuit (14) for a predetermined number of system cycles at a predetermined frequency upon receipt of a first predetermined temperature (power state condition, power supply scaler) value .
US6854067B1 CLAIM 12 . The method as recited in claim 11 , wherein said f4) further comprises : communicating each said optimal value to said power supply scaler (predetermined temperature) via said bus ; registering each said optimal value with said matrix of multiplexers and registers ; commanding said matrix of multiplexers and registers to change said independent multiple of said common supply voltage to correspond with said optimal value ; and monitoring said matrix of multiplexers and registers .	WO9210032A1 CLAIM 8 . The temperature-sensing control system of claim 5 wherein said hold means (36) includes a mechanism for sending noop instructions to said integrated circuit (14) for a predetermined number of system cycles at a predetermined frequency upon receipt of a first predetermined temperature (power state condition, power supply scaler) value .
US6854067B1 CLAIM 13 . In a microcontroller , a system comprising : a bus ; a processor coupled to said bus ; a power on reset circuit , said processor and said power on reset circuit coupled to said bus and interconnectedly coupled with said processor via said bus ; and a switched mode pump power supply interconnectedly coupled with said power on reset circuit and responsive to signals therefrom wherein said system executes a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply ; b) sensing a power state condition (predetermined temperature) of said power state ; c) determining a suitability status (determined relationship) of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor via said bus ; e) controlling certain functions of said microcontroller according to said suitability status ; and f) dynamically programming said power on reset circuit via said bus .	WO9210032A1 CLAIM 1 . A temperature-sensing control system for use on an integrated circuit comprising : an integrated circuit (14) having a sequence controller (12) operatively connected thereto , said sequence controller (12) providing instructions and/or data to said integrated circuit (14) which performs operations according to said instructions on said data ; temperature sensor means (20) thermally connected to the integrated circuit (14) and means associated with said temperature sensor means therewith for creating a temperature signal ; and hold means (36) associated with said sequence controller (12) for slowing operation of said integrated circuit (14) by a predetermined amount if said temperature signal has a predetermined relationship (suitability status) to a first predetermined value and for slowing operation of said integrated circuit (14) by a greater predetermined amount if said temperature signal has a predetermined relationship to a second predetermined value , which second predetermined value is higher than said first predetermined value . WO9210032A1 CLAIM 8 . The temperature-sensing control system of claim 5 wherein said hold means (36) includes a mechanism for sending noop instructions to said integrated circuit (14) for a predetermined number of system cycles at a predetermined frequency upon receipt of a first predetermined temperature (power state condition, power supply scaler) value .
US6854067B1 CLAIM 16 . The system as recited in claim 15 , wherein said c) further comprises : c1) generating a precision reference voltage , said precision reference voltage independent of said common supply voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition (predetermined temperature) signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	WO9210032A1 CLAIM 8 . The temperature-sensing control system of claim 5 wherein said hold means (36) includes a mechanism for sending noop instructions to said integrated circuit (14) for a predetermined number of system cycles at a predetermined frequency upon receipt of a first predetermined temperature (power state condition, power supply scaler) value .
US6854067B1 CLAIM 17 . The system as recited in claim 16 , wherein said b2) is performed by a power supply scaler (predetermined temperature) , wherein said power supply scaler comprises : a) a divider of said common supply voltage ; b) a matrix of multiplexers and registers , and c) an interconnection to said bus .	WO9210032A1 CLAIM 8 . The temperature-sensing control system of claim 5 wherein said hold means (36) includes a mechanism for sending noop instructions to said integrated circuit (14) for a predetermined number of system cycles at a predetermined frequency upon receipt of a first predetermined temperature (power state condition, power supply scaler) value .
US6854067B1 CLAIM 19 . The method as recited in claim 18 , wherein said f4) further comprises : communicating each said optimal value to said power supply scaler (predetermined temperature) via said bus ; registering each said optimal value with said matrix of multiplexers and registers ; commanding said matrix of multiplexers and registers to change said independent multiple of said common supply voltage to correspond with said optimal value ; and monitoring said matrix of multiplexers and registers .	WO9210032A1 CLAIM 8 . The temperature-sensing control system of claim 5 wherein said hold means (36) includes a mechanism for sending noop instructions to said integrated circuit (14) for a predetermined number of system cycles at a predetermined frequency upon receipt of a first predetermined temperature (power state condition, power supply scaler) value .

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	US5049758A Filed: 1990-10-31 Issued: 1991-09-17 Adaptable CMOS winner-take all circuit (Original Assignee) Synaptics Inc (Current Assignee) Synaptics Inc Carver A. Mead, Timothy P. Allen
US6854067B1 CLAIM 1 . In a microcontroller with an embedded processor , a switched mode pump power supply and power on reset circuit (output node) , a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply , wherein said processor and said power on reset circuit are interconnectedly coupled , and wherein said switched mode pump power supply is interconnectedly coupled with said power on reset circuit and responsive to signals therefrom ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor ; e) controlling certain functions of said microcontroller accordingly .	US5049758A CLAIM 1 . An adaptable circuit , communicating with a plurality of current-carrying lines , for indicating the output of the one of said plurality of current-carrying lines through which the most current is flowing , including : a plurality of MOS current mirrors , each of said current mirrors including an input node , an output node (reset circuit) , a driving MOS current mirror transistor and a driven MOS current mirror transistor , the sources of said driving MOS current mirror transistor and said driven MOS current mirror transistor connected to a source of fixed positive voltage , the gate and drain of each of said driving MOS current mirror transistors comprising said input node and connected to a different one of said current carrying lines and to one electrode of a first MOS capacitor , the gate of said driven MOS current mirror transistor connected to a floating node , the second electrode of said first MOS capacitor comprising a portion of said floating node , drain of said driven MOS current mirror transistor comprising said output node and connected to the gate of said follower transistor , a second MOS capacitor associated with each of said plurality of current mirrors , each said second MOS capacitor having as a first electrode a portion of the floating node in the current mirror with which it is associated , and as a second electrode a second node , a pulldown transistor associated with each of said current mirrors , each of said pulldown transistors having its source connected to a source of fixed negative voltage , and its gate connected to a common pulldown gate line , a pulldown gate bias transistor , having its source connected to said source of negative voltage , its gate connected to a source of bias voltage , a follower transistor associated with each of said current mirrors , having its gate connected to the output of the current mirror with which it is associated , and having a source-drain path connected between a source of fixed voltage and said common pulldown gate line , means for selectively connecting the drain of said pulldown gate bias transistor to said common pulldown gate line , and for enabling said source-drain path of said follower transistor to conduct during an operating mode of said circuit , and for connecting said common pulldown gate line to a source of fixed voltage , for connecting each of said second nodes to the output node of said current mirror with which it is associated , and for disabling said source-drain path of said follower transistor during an adapting mode of said circuit , an opaque layer covering portions of the surface of said integrated circuit containing active circuits , said opaque layer having an aperture therein above said second capacitor for allowing ultraviolet light to fall onto said first and second electrodes of said second capacitor whereby the offset voltages of said circuit can be adapted while a source of ultraviolet light is present during said adapting mode of said circuit .
US6854067B1 CLAIM 2 . The method as recited in claim 1 , further comprising : f) dynamically programming said power on reset circuit (output node) .	US5049758A CLAIM 1 . An adaptable circuit , communicating with a plurality of current-carrying lines , for indicating the output of the one of said plurality of current-carrying lines through which the most current is flowing , including : a plurality of MOS current mirrors , each of said current mirrors including an input node , an output node (reset circuit) , a driving MOS current mirror transistor and a driven MOS current mirror transistor , the sources of said driving MOS current mirror transistor and said driven MOS current mirror transistor connected to a source of fixed positive voltage , the gate and drain of each of said driving MOS current mirror transistors comprising said input node and connected to a different one of said current carrying lines and to one electrode of a first MOS capacitor , the gate of said driven MOS current mirror transistor connected to a floating node , the second electrode of said first MOS capacitor comprising a portion of said floating node , drain of said driven MOS current mirror transistor comprising said output node and connected to the gate of said follower transistor , a second MOS capacitor associated with each of said plurality of current mirrors , each said second MOS capacitor having as a first electrode a portion of the floating node in the current mirror with which it is associated , and as a second electrode a second node , a pulldown transistor associated with each of said current mirrors , each of said pulldown transistors having its source connected to a source of fixed negative voltage , and its gate connected to a common pulldown gate line , a pulldown gate bias transistor , having its source connected to said source of negative voltage , its gate connected to a source of bias voltage , a follower transistor associated with each of said current mirrors , having its gate connected to the output of the current mirror with which it is associated , and having a source-drain path connected between a source of fixed voltage and said common pulldown gate line , means for selectively connecting the drain of said pulldown gate bias transistor to said common pulldown gate line , and for enabling said source-drain path of said follower transistor to conduct during an operating mode of said circuit , and for connecting said common pulldown gate line to a source of fixed voltage , for connecting each of said second nodes to the output node of said current mirror with which it is associated , and for disabling said source-drain path of said follower transistor during an adapting mode of said circuit , an opaque layer covering portions of the surface of said integrated circuit containing active circuits , said opaque layer having an aperture therein above said second capacitor for allowing ultraviolet light to fall onto said first and second electrodes of said second capacitor whereby the offset voltages of said circuit can be adapted while a source of ultraviolet light is present during said adapting mode of said circuit .
US6854067B1 CLAIM 3 . The method as recited in claim 2 , wherein said power on reset circuit (output node) and said processor are interconnected via a bus .	US5049758A CLAIM 1 . An adaptable circuit , communicating with a plurality of current-carrying lines , for indicating the output of the one of said plurality of current-carrying lines through which the most current is flowing , including : a plurality of MOS current mirrors , each of said current mirrors including an input node , an output node (reset circuit) , a driving MOS current mirror transistor and a driven MOS current mirror transistor , the sources of said driving MOS current mirror transistor and said driven MOS current mirror transistor connected to a source of fixed positive voltage , the gate and drain of each of said driving MOS current mirror transistors comprising said input node and connected to a different one of said current carrying lines and to one electrode of a first MOS capacitor , the gate of said driven MOS current mirror transistor connected to a floating node , the second electrode of said first MOS capacitor comprising a portion of said floating node , drain of said driven MOS current mirror transistor comprising said output node and connected to the gate of said follower transistor , a second MOS capacitor associated with each of said plurality of current mirrors , each said second MOS capacitor having as a first electrode a portion of the floating node in the current mirror with which it is associated , and as a second electrode a second node , a pulldown transistor associated with each of said current mirrors , each of said pulldown transistors having its source connected to a source of fixed negative voltage , and its gate connected to a common pulldown gate line , a pulldown gate bias transistor , having its source connected to said source of negative voltage , its gate connected to a source of bias voltage , a follower transistor associated with each of said current mirrors , having its gate connected to the output of the current mirror with which it is associated , and having a source-drain path connected between a source of fixed voltage and said common pulldown gate line , means for selectively connecting the drain of said pulldown gate bias transistor to said common pulldown gate line , and for enabling said source-drain path of said follower transistor to conduct during an operating mode of said circuit , and for connecting said common pulldown gate line to a source of fixed voltage , for connecting each of said second nodes to the output node of said current mirror with which it is associated , and for disabling said source-drain path of said follower transistor during an adapting mode of said circuit , an opaque layer covering portions of the surface of said integrated circuit containing active circuits , said opaque layer having an aperture therein above said second capacitor for allowing ultraviolet light to fall onto said first and second electrodes of said second capacitor whereby the offset voltages of said circuit can be adapted while a source of ultraviolet light is present during said adapting mode of said circuit .

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	US5109261A Filed: 1990-10-31 Issued: 1992-04-28 CMOS amplifier with offset adaptation (Original Assignee) Synaptics Inc (Current Assignee) Synaptics Inc Carver A. Mead, Timothy P. Allen
US6854067B1 CLAIM 6 . The method as recited in claim 5 , wherein said c) further comprises : c1) generating a precision reference voltage (second layer) ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US5109261A CLAIM 1 . A semiconductor structure , including : a semiconductor substrate , a first conductive layer disposed above said semiconductor substrate and separated therefrom by a first layer of insulating material , a second conductive layer disposed above said first conductive layer , said second conductive layer separated from said first conductive layer by a second layer (precision reference voltage) of insulating material , said second conductive layer including at least two physically separate regions , a portion of a first one of said regions of said at least two physically separate regions of said second conductive layer having a first aperture therein , said first aperture lying above said first conductive layer , an opaque layer disposed above said second conductive layer , said opaque layer having a second aperture therein , said second aperture lying substantially above said first aperture in said second conductive layer , and said second aperture being larger in area than said first aperture .
US6854067B1 CLAIM 7 . The method as recited in claim 6 , wherein said precision reference voltage (second layer) is independent of said common supply voltage .	US5109261A CLAIM 1 . A semiconductor structure , including : a semiconductor substrate , a first conductive layer disposed above said semiconductor substrate and separated therefrom by a first layer of insulating material , a second conductive layer disposed above said first conductive layer , said second conductive layer separated from said first conductive layer by a second layer (precision reference voltage) of insulating material , said second conductive layer including at least two physically separate regions , a portion of a first one of said regions of said at least two physically separate regions of said second conductive layer having a first aperture therein , said first aperture lying above said first conductive layer , an opaque layer disposed above said second conductive layer , said opaque layer having a second aperture therein , said second aperture lying substantially above said first aperture in said second conductive layer , and said second aperture being larger in area than said first aperture .
US6854067B1 CLAIM 11 . The method as recited in claim 10 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state corresponding to said status ; f3) programmatically calculating an optimal value (conductive layers) for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	US5109261A CLAIM 2 . The semiconductor structure of claim 1 wherein said first and second conductive layers (optimal value) are formed from polysilicon and said first and second insulating layers are formed from silicon dioxide .
US6854067B1 CLAIM 12 . The method as recited in claim 11 , wherein said f4) further comprises : communicating each said optimal value (conductive layers) to said power supply scaler via said bus ; registering each said optimal value with said matrix of multiplexers and registers ; commanding said matrix of multiplexers and registers to change said independent multiple of said common supply voltage to correspond with said optimal value ; and monitoring said matrix of multiplexers and registers .	US5109261A CLAIM 2 . The semiconductor structure of claim 1 wherein said first and second conductive layers (optimal value) are formed from polysilicon and said first and second insulating layers are formed from silicon dioxide .
US6854067B1 CLAIM 16 . The system as recited in claim 15 , wherein said c) further comprises : c1) generating a precision reference voltage (second layer) , said precision reference voltage independent of said common supply voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US5109261A CLAIM 1 . A semiconductor structure , including : a semiconductor substrate , a first conductive layer disposed above said semiconductor substrate and separated therefrom by a first layer of insulating material , a second conductive layer disposed above said first conductive layer , said second conductive layer separated from said first conductive layer by a second layer (precision reference voltage) of insulating material , said second conductive layer including at least two physically separate regions , a portion of a first one of said regions of said at least two physically separate regions of said second conductive layer having a first aperture therein , said first aperture lying above said first conductive layer , an opaque layer disposed above said second conductive layer , said opaque layer having a second aperture therein , said second aperture lying substantially above said first aperture in said second conductive layer , and said second aperture being larger in area than said first aperture .
US6854067B1 CLAIM 18 . The system as recited in claim 17 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state corresponding to said status ; f3) programmatically calculating an optimal value (conductive layers) for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	US5109261A CLAIM 2 . The semiconductor structure of claim 1 wherein said first and second conductive layers (optimal value) are formed from polysilicon and said first and second insulating layers are formed from silicon dioxide .
US6854067B1 CLAIM 19 . The method as recited in claim 18 , wherein said f4) further comprises : communicating each said optimal value (conductive layers) to said power supply scaler via said bus ; registering each said optimal value with said matrix of multiplexers and registers ; commanding said matrix of multiplexers and registers to change said independent multiple of said common supply voltage to correspond with said optimal value ; and monitoring said matrix of multiplexers and registers .	US5109261A CLAIM 2 . The semiconductor structure of claim 1 wherein said first and second conductive layers (optimal value) are formed from polysilicon and said first and second insulating layers are formed from silicon dioxide .

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	US5120996A Filed: 1990-06-06 Issued: 1992-06-09 Synaptic element and array (Original Assignee) Synaptics Inc (Current Assignee) Synaptics Inc Carver A. Mead, Federico Faggin, Timothy P. Allen, Janeen D. W. Anderson
US6854067B1 CLAIM 6 . The method as recited in claim 5 , wherein said c) further comprises : c1) generating a precision reference voltage (hold circuits) ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals (negative voltage) , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US5120996A CLAIM 9 . An electronic circuit fabricated as a part of an integrated circuit , said integrated circuit having a portion containing active circuits , including in combination : an adaptive amplifier having a gain of magnitude much larger than 1 , and including : an input node , an output node , an MOS N-channel transistor and an MOS P-channel transistor , said MOS N-channel transistor having a source connected to a source of negative voltage (power state condition signals) , and its drain connected to the drain of said MOS P-channel transistor and to said output node , the source of said MOS P-channel transistor connected to a source of positive voltage , a floating gate common to said MOS N-channel transistor connected to a source of positive voltage , a first MOS capacitor having a first electrode connected to said input node and a second electrode comprising a portion of said floating gate , a second MOS capacitor having a first electrode connected to said output node and a second electrode comprising a portion of said floating gate , an opaque layer covering said portion of said integrated circuit containing active circuits , said opaque layer having an aperture therein above said second capacitor for allowing ultraviolet light to fall onto said first and second electrodes of said second capacitor , a sample/hold circuit having an input , a select input , and an output , said output connected to said input node of said adaptive amplifier . US5120996A CLAIM 12 . An array of electronic circuits arranged in rows and columns , each of said electronic circuits including an adaptive amplifier having an input node and an output node and means for generating an error current , and a sample/hold circuit having an input , an output , and a select input , the output of said sample/hold circuit connected to the input node of said adaptive amplifier , the select inputs of all sample/hold circuits (precision reference voltage) associated with the electronic circuits in a given column of said array connected in common to one of a plurality of write lines , and the error current generated from each adaptive amplifier in a column connected in common to one of a plurality of output sense lines , and the inputs of all the sample/hold circuits in a row of said array connected in common to one of a plurality of input voltage lines .
US6854067B1 CLAIM 7 . The method as recited in claim 6 , wherein said precision reference voltage (hold circuits) is independent of said common supply voltage .	US5120996A CLAIM 12 . An array of electronic circuits arranged in rows and columns , each of said electronic circuits including an adaptive amplifier having an input node and an output node and means for generating an error current , and a sample/hold circuit having an input , an output , and a select input , the output of said sample/hold circuit connected to the input node of said adaptive amplifier , the select inputs of all sample/hold circuits (precision reference voltage) associated with the electronic circuits in a given column of said array connected in common to one of a plurality of write lines , and the error current generated from each adaptive amplifier in a column connected in common to one of a plurality of output sense lines , and the inputs of all the sample/hold circuits in a row of said array connected in common to one of a plurality of input voltage lines .
US6854067B1 CLAIM 16 . The system as recited in claim 15 , wherein said c) further comprises : c1) generating a precision reference voltage (hold circuits) , said precision reference voltage independent of said common supply voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals (negative voltage) , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US5120996A CLAIM 9 . An electronic circuit fabricated as a part of an integrated circuit , said integrated circuit having a portion containing active circuits , including in combination : an adaptive amplifier having a gain of magnitude much larger than 1 , and including : an input node , an output node , an MOS N-channel transistor and an MOS P-channel transistor , said MOS N-channel transistor having a source connected to a source of negative voltage (power state condition signals) , and its drain connected to the drain of said MOS P-channel transistor and to said output node , the source of said MOS P-channel transistor connected to a source of positive voltage , a floating gate common to said MOS N-channel transistor connected to a source of positive voltage , a first MOS capacitor having a first electrode connected to said input node and a second electrode comprising a portion of said floating gate , a second MOS capacitor having a first electrode connected to said output node and a second electrode comprising a portion of said floating gate , an opaque layer covering said portion of said integrated circuit containing active circuits , said opaque layer having an aperture therein above said second capacitor for allowing ultraviolet light to fall onto said first and second electrodes of said second capacitor , a sample/hold circuit having an input , a select input , and an output , said output connected to said input node of said adaptive amplifier . US5120996A CLAIM 12 . An array of electronic circuits arranged in rows and columns , each of said electronic circuits including an adaptive amplifier having an input node and an output node and means for generating an error current , and a sample/hold circuit having an input , an output , and a select input , the output of said sample/hold circuit connected to the input node of said adaptive amplifier , the select inputs of all sample/hold circuits (precision reference voltage) associated with the electronic circuits in a given column of said array connected in common to one of a plurality of write lines , and the error current generated from each adaptive amplifier in a column connected in common to one of a plurality of output sense lines , and the inputs of all the sample/hold circuits in a row of said array connected in common to one of a plurality of input voltage lines .

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	US5175884A Filed: 1990-06-01 Issued: 1992-12-29 Voltage controlled oscillator with current control (Original Assignee) Motorola Solutions Inc (Current Assignee) Motorola Solutions Inc Jose I. Suarez
US6854067B1 CLAIM 1 . In a microcontroller with an embedded processor , a switched mode pump power supply and power on reset circuit , a method of dynamically controlling a plurality of power stability functions (control means) for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply , wherein said processor and said power on reset circuit are interconnectedly coupled , and wherein said switched mode pump power supply is interconnectedly coupled with said power on reset circuit and responsive to signals therefrom ; b) sensing a power state condition of said power state ; c) determining a suitability status (determined relationship) of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor ; e) controlling certain functions of said microcontroller accordingly .	US5175884A CLAIM 1 . A circuit for setting a bias current of an oscillating device , the oscillating device having an output whose frequency is controlled by a tuning voltage , the circuit comprising : sensing means , coupled to the oscillating device , for sensing the tuning voltage of the oscillating device ; and control means (power stability functions) , responsive to the sensed tuning voltage , for controlling the bias current of the oscillating device , by setting a current value according to predetermined data relating to bias currents for minimizing sideband noise for each of a plurality of tuning voltages . US5175884A CLAIM 2 . The circuit of claim 1 , wherein the control means comprises a plurality of comparators , each comparator for comparing one of a plurality of reference voltages with the tuning voltage and producing an output signal , the output signal controlling the bias current in accordance with the predetermined relationship (suitability status) between the bias current and the tuning voltage .
US6854067B1 CLAIM 6 . The method as recited in claim 5 , wherein said c) further comprises : c1) generating a precision reference voltage (current values) ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US5175884A CLAIM 5 . The circuit of claim 3 wherein the predetermined data include optimum bias current values (precision reference voltage) for minimizing sideband noise for a plurality of tuning voltages at a plurality of temperatures .
US6854067B1 CLAIM 7 . The method as recited in claim 6 , wherein said precision reference voltage (current values) is independent of said common supply voltage .	US5175884A CLAIM 5 . The circuit of claim 3 wherein the predetermined data include optimum bias current values (precision reference voltage) for minimizing sideband noise for a plurality of tuning voltages at a plurality of temperatures .
US6854067B1 CLAIM 13 . In a microcontroller , a system comprising : a bus ; a processor coupled to said bus ; a power on reset circuit , said processor and said power on reset circuit coupled to said bus and interconnectedly coupled with said processor via said bus ; and a switched mode pump power supply interconnectedly coupled with said power on reset circuit and responsive to signals therefrom wherein said system executes a method of dynamically controlling a plurality of power stability functions (control means) for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply ; b) sensing a power state condition of said power state ; c) determining a suitability status (determined relationship) of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor via said bus ; e) controlling certain functions of said microcontroller according to said suitability status ; and f) dynamically programming said power on reset circuit via said bus .	US5175884A CLAIM 1 . A circuit for setting a bias current of an oscillating device , the oscillating device having an output whose frequency is controlled by a tuning voltage , the circuit comprising : sensing means , coupled to the oscillating device , for sensing the tuning voltage of the oscillating device ; and control means (power stability functions) , responsive to the sensed tuning voltage , for controlling the bias current of the oscillating device , by setting a current value according to predetermined data relating to bias currents for minimizing sideband noise for each of a plurality of tuning voltages . US5175884A CLAIM 2 . The circuit of claim 1 , wherein the control means comprises a plurality of comparators , each comparator for comparing one of a plurality of reference voltages with the tuning voltage and producing an output signal , the output signal controlling the bias current in accordance with the predetermined relationship (suitability status) between the bias current and the tuning voltage .
US6854067B1 CLAIM 16 . The system as recited in claim 15 , wherein said c) further comprises : c1) generating a precision reference voltage (current values) , said precision reference voltage independent of said common supply voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US5175884A CLAIM 5 . The circuit of claim 3 wherein the predetermined data include optimum bias current values (precision reference voltage) for minimizing sideband noise for a plurality of tuning voltages at a plurality of temperatures .

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	US5059920A Filed: 1990-05-18 Issued: 1991-10-22 CMOS amplifier with offset adaptation (Original Assignee) Synaptics Inc (Current Assignee) Synaptics Inc Janeen D. W. Anderson, Carver A. Mead, Timothy P. Allen, Michael F. Wall
US6854067B1 CLAIM 1 . In a microcontroller with an embedded processor , a switched mode pump power supply and power on reset circuit (output node) , a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply , wherein said processor and said power on reset circuit are interconnectedly coupled , and wherein said switched mode pump power supply is interconnectedly coupled with said power on reset circuit and responsive to signals therefrom ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor ; e) controlling certain functions of said microcontroller accordingly .	US5059920A CLAIM 1 . An analog MOS auto-compensating amplifier fabricated on a semiconductor substrate as a part of an integrated circuit , including : an input node , an output node (reset circuit) , an amplifier having an input connected to a floating node and an output connected to said output node , an MOS capacitor having a first plate connected to said input node and a second plate connected to said floating node , a source of an electrical control signal , electron injecting means coupled to said floating node and responsive to said electrical control signal for injecting electrons on to said floating node while the voltage on said floating node is within the normal operating range of said amplifier , said electron injecting means operating to vary the rate of injection of electrons on to said floating node in response to the magnitude of said electrical control signal .
US6854067B1 CLAIM 2 . The method as recited in claim 1 , further comprising : f) dynamically programming said power on reset circuit (output node) .	US5059920A CLAIM 1 . An analog MOS auto-compensating amplifier fabricated on a semiconductor substrate as a part of an integrated circuit , including : an input node , an output node (reset circuit) , an amplifier having an input connected to a floating node and an output connected to said output node , an MOS capacitor having a first plate connected to said input node and a second plate connected to said floating node , a source of an electrical control signal , electron injecting means coupled to said floating node and responsive to said electrical control signal for injecting electrons on to said floating node while the voltage on said floating node is within the normal operating range of said amplifier , said electron injecting means operating to vary the rate of injection of electrons on to said floating node in response to the magnitude of said electrical control signal .
US6854067B1 CLAIM 3 . The method as recited in claim 2 , wherein said power on reset circuit (output node) and said processor are interconnected via a bus .	US5059920A CLAIM 1 . An analog MOS auto-compensating amplifier fabricated on a semiconductor substrate as a part of an integrated circuit , including : an input node , an output node (reset circuit) , an amplifier having an input connected to a floating node and an output connected to said output node , an MOS capacitor having a first plate connected to said input node and a second plate connected to said floating node , a source of an electrical control signal , electron injecting means coupled to said floating node and responsive to said electrical control signal for injecting electrons on to said floating node while the voltage on said floating node is within the normal operating range of said amplifier , said electron injecting means operating to vary the rate of injection of electrons on to said floating node in response to the magnitude of said electrical control signal .
US6854067B1 CLAIM 4 . The method as recited in claim 3 , wherein said b) and said c) are accomplished by said power on reset circuit (output node) .	US5059920A CLAIM 1 . An analog MOS auto-compensating amplifier fabricated on a semiconductor substrate as a part of an integrated circuit , including : an input node , an output node (reset circuit) , an amplifier having an input connected to a floating node and an output connected to said output node , an MOS capacitor having a first plate connected to said input node and a second plate connected to said floating node , a source of an electrical control signal , electron injecting means coupled to said floating node and responsive to said electrical control signal for injecting electrons on to said floating node while the voltage on said floating node is within the normal operating range of said amplifier , said electron injecting means operating to vary the rate of injection of electrons on to said floating node in response to the magnitude of said electrical control signal .
US6854067B1 CLAIM 6 . The method as recited in claim 5 , wherein said c) further comprises : c1) generating a precision reference voltage (second layer) ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US5059920A CLAIM 8 . The auto-compensating amplifier of claim 7 wherein , said floating node is a layer of polysilicon and said electron removal means includes a second layer (precision reference voltage) of polysilicon separated from said floating node by a layer of SiO 2 .
US6854067B1 CLAIM 7 . The method as recited in claim 6 , wherein said precision reference voltage (second layer) is independent of said common supply voltage .	US5059920A CLAIM 8 . The auto-compensating amplifier of claim 7 wherein , said floating node is a layer of polysilicon and said electron removal means includes a second layer (precision reference voltage) of polysilicon separated from said floating node by a layer of SiO 2 .
US6854067B1 CLAIM 13 . In a microcontroller , a system comprising : a bus ; a processor coupled to said bus ; a power on reset circuit (output node) , said processor and said power on reset circuit coupled to said bus and interconnectedly coupled with said processor via said bus ; and a switched mode pump power supply interconnectedly coupled with said power on reset circuit and responsive to signals therefrom wherein said system executes a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor via said bus ; e) controlling certain functions of said microcontroller according to said suitability status ; and f) dynamically programming said power on reset circuit via said bus .	US5059920A CLAIM 1 . An analog MOS auto-compensating amplifier fabricated on a semiconductor substrate as a part of an integrated circuit , including : an input node , an output node (reset circuit) , an amplifier having an input connected to a floating node and an output connected to said output node , an MOS capacitor having a first plate connected to said input node and a second plate connected to said floating node , a source of an electrical control signal , electron injecting means coupled to said floating node and responsive to said electrical control signal for injecting electrons on to said floating node while the voltage on said floating node is within the normal operating range of said amplifier , said electron injecting means operating to vary the rate of injection of electrons on to said floating node in response to the magnitude of said electrical control signal .
US6854067B1 CLAIM 14 . The system as recited in claim 13 , wherein said b) and said c) of said method are accomplished by said power on reset circuit (output node) .	US5059920A CLAIM 1 . An analog MOS auto-compensating amplifier fabricated on a semiconductor substrate as a part of an integrated circuit , including : an input node , an output node (reset circuit) , an amplifier having an input connected to a floating node and an output connected to said output node , an MOS capacitor having a first plate connected to said input node and a second plate connected to said floating node , a source of an electrical control signal , electron injecting means coupled to said floating node and responsive to said electrical control signal for injecting electrons on to said floating node while the voltage on said floating node is within the normal operating range of said amplifier , said electron injecting means operating to vary the rate of injection of electrons on to said floating node in response to the magnitude of said electrical control signal .
US6854067B1 CLAIM 16 . The system as recited in claim 15 , wherein said c) further comprises : c1) generating a precision reference voltage (second layer) , said precision reference voltage independent of said common supply voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US5059920A CLAIM 8 . The auto-compensating amplifier of claim 7 wherein , said floating node is a layer of polysilicon and said electron removal means includes a second layer (precision reference voltage) of polysilicon separated from said floating node by a layer of SiO 2 .
US6854067B1 CLAIM 20 . In a microcontroller having a power on reset circuit (output node) interconnected with a processor a method of dynamically controlling said power state , said method comprising : a) ascertaining a power state powered by a switched mode pump power supply , said switched mode pump power supply interconnected with and responsive to control by said power on reset circuit ; b) programmatically determining desired changes to said power state ; c) intercommunicating between said processor and said power on reset circuit ; d) adjusting said power on reset circuit corresponding to said desired changes to said power state ; e) controlling said switched mode pump power supply according to said d) ; and f) repeating said a) through e) .	US5059920A CLAIM 1 . An analog MOS auto-compensating amplifier fabricated on a semiconductor substrate as a part of an integrated circuit , including : an input node , an output node (reset circuit) , an amplifier having an input connected to a floating node and an output connected to said output node , an MOS capacitor having a first plate connected to said input node and a second plate connected to said floating node , a source of an electrical control signal , electron injecting means coupled to said floating node and responsive to said electrical control signal for injecting electrons on to said floating node while the voltage on said floating node is within the normal operating range of said amplifier , said electron injecting means operating to vary the rate of injection of electrons on to said floating node in response to the magnitude of said electrical control signal .

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	US5043674A Filed: 1990-04-30 Issued: 1991-08-27 Differential receiver with high common-mode range (Original Assignee) International Business Machines Corp (Current Assignee) International Business Machines Corp Anthony R. Bonaccio, John E. Gersbach
US6854067B1 CLAIM 1 . In a microcontroller with an embedded processor , a switched mode pump power supply (load circuit) and power on reset circuit , a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply , wherein said processor and said power on reset circuit are interconnectedly coupled , and wherein said switched mode pump power supply is interconnectedly coupled with said power on reset circuit and responsive to signals therefrom ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor ; e) controlling certain functions of said microcontroller accordingly .	US5043674A CLAIM 1 . A differential amplifier circuit for producing an output current proportional to the differential input voltage regardless of the common-mode input voltage comprising : identical first and second voltage networks coupled between first and second differential voltage inputs and coupled to common differential current outputs , and to a common bias circuit , each of said networks being connected to a respective one of said differential voltage inputs through a respective input resistor , and to respective one of said differential current outputs and cross coupled to the other one of said differential current outputs and containing a current mirror consisting of a current mirror transistor , directly coupled to the said other one of said outputs , and a diode , and transistor means for generating an impedance reference voltage for the respective input resistor coupled to said network , said transistor means being further coupled to said respective one of said outputs and said current mirror , a load circuit (mode pump power supply, power supply scaler) coupled to the current outputs , and said common bias circuit coupled to said first and second networks consisting of a plurality of diodes and a constant current source coupled between a pair of supply voltages .
US6854067B1 CLAIM 6 . The method as recited in claim 5 , wherein said c) further comprises : c1) generating a precision reference voltage (source follower transistor) ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US5043674A CLAIM 3 . The differential amplifier of claim 1 wherein said transistor means comprises a pair of serially arranged source follower transistor (precision reference voltage) s and one of said source follower transistors is a NFET device and the other of said source follower transistors is a PFET device .
US6854067B1 CLAIM 7 . The method as recited in claim 6 , wherein said precision reference voltage (source follower transistor) is independent of said common supply voltage .	US5043674A CLAIM 3 . The differential amplifier of claim 1 wherein said transistor means comprises a pair of serially arranged source follower transistor (precision reference voltage) s and one of said source follower transistors is a NFET device and the other of said source follower transistors is a PFET device .
US6854067B1 CLAIM 9 . The method as recited in claim 8 , wherein said b2) is performed by a power supply scaler (load circuit) , and wherein said power supply scaler comprises : a) a divider of said common supply voltage ; b) a matrix of multiplexers and registers , and c) an interconnection to said bus .	US5043674A CLAIM 1 . A differential amplifier circuit for producing an output current proportional to the differential input voltage regardless of the common-mode input voltage comprising : identical first and second voltage networks coupled between first and second differential voltage inputs and coupled to common differential current outputs , and to a common bias circuit , each of said networks being connected to a respective one of said differential voltage inputs through a respective input resistor , and to respective one of said differential current outputs and cross coupled to the other one of said differential current outputs and containing a current mirror consisting of a current mirror transistor , directly coupled to the said other one of said outputs , and a diode , and transistor means for generating an impedance reference voltage for the respective input resistor coupled to said network , said transistor means being further coupled to said respective one of said outputs and said current mirror , a load circuit (mode pump power supply, power supply scaler) coupled to the current outputs , and said common bias circuit coupled to said first and second networks consisting of a plurality of diodes and a constant current source coupled between a pair of supply voltages .
US6854067B1 CLAIM 12 . The method as recited in claim 11 , wherein said f4) further comprises : communicating each said optimal value to said power supply scaler (load circuit) via said bus ; registering each said optimal value with said matrix of multiplexers and registers ; commanding said matrix of multiplexers and registers to change said independent multiple of said common supply voltage to correspond with said optimal value ; and monitoring said matrix of multiplexers and registers .	US5043674A CLAIM 1 . A differential amplifier circuit for producing an output current proportional to the differential input voltage regardless of the common-mode input voltage comprising : identical first and second voltage networks coupled between first and second differential voltage inputs and coupled to common differential current outputs , and to a common bias circuit , each of said networks being connected to a respective one of said differential voltage inputs through a respective input resistor , and to respective one of said differential current outputs and cross coupled to the other one of said differential current outputs and containing a current mirror consisting of a current mirror transistor , directly coupled to the said other one of said outputs , and a diode , and transistor means for generating an impedance reference voltage for the respective input resistor coupled to said network , said transistor means being further coupled to said respective one of said outputs and said current mirror , a load circuit (mode pump power supply, power supply scaler) coupled to the current outputs , and said common bias circuit coupled to said first and second networks consisting of a plurality of diodes and a constant current source coupled between a pair of supply voltages .
US6854067B1 CLAIM 13 . In a microcontroller , a system comprising : a bus ; a processor coupled to said bus ; a power on reset circuit , said processor and said power on reset circuit coupled to said bus and interconnectedly coupled with said processor via said bus ; and a switched mode pump power supply (load circuit) interconnectedly coupled with said power on reset circuit and responsive to signals therefrom wherein said system executes a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor via said bus ; e) controlling certain functions of said microcontroller according to said suitability status ; and f) dynamically programming said power on reset circuit via said bus .	US5043674A CLAIM 1 . A differential amplifier circuit for producing an output current proportional to the differential input voltage regardless of the common-mode input voltage comprising : identical first and second voltage networks coupled between first and second differential voltage inputs and coupled to common differential current outputs , and to a common bias circuit , each of said networks being connected to a respective one of said differential voltage inputs through a respective input resistor , and to respective one of said differential current outputs and cross coupled to the other one of said differential current outputs and containing a current mirror consisting of a current mirror transistor , directly coupled to the said other one of said outputs , and a diode , and transistor means for generating an impedance reference voltage for the respective input resistor coupled to said network , said transistor means being further coupled to said respective one of said outputs and said current mirror , a load circuit (mode pump power supply, power supply scaler) coupled to the current outputs , and said common bias circuit coupled to said first and second networks consisting of a plurality of diodes and a constant current source coupled between a pair of supply voltages .
US6854067B1 CLAIM 16 . The system as recited in claim 15 , wherein said c) further comprises : c1) generating a precision reference voltage (source follower transistor) , said precision reference voltage independent of said common supply voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US5043674A CLAIM 3 . The differential amplifier of claim 1 wherein said transistor means comprises a pair of serially arranged source follower transistor (precision reference voltage) s and one of said source follower transistors is a NFET device and the other of said source follower transistors is a PFET device .
US6854067B1 CLAIM 17 . The system as recited in claim 16 , wherein said b2) is performed by a power supply scaler (load circuit) , wherein said power supply scaler comprises : a) a divider of said common supply voltage ; b) a matrix of multiplexers and registers , and c) an interconnection to said bus .	US5043674A CLAIM 1 . A differential amplifier circuit for producing an output current proportional to the differential input voltage regardless of the common-mode input voltage comprising : identical first and second voltage networks coupled between first and second differential voltage inputs and coupled to common differential current outputs , and to a common bias circuit , each of said networks being connected to a respective one of said differential voltage inputs through a respective input resistor , and to respective one of said differential current outputs and cross coupled to the other one of said differential current outputs and containing a current mirror consisting of a current mirror transistor , directly coupled to the said other one of said outputs , and a diode , and transistor means for generating an impedance reference voltage for the respective input resistor coupled to said network , said transistor means being further coupled to said respective one of said outputs and said current mirror , a load circuit (mode pump power supply, power supply scaler) coupled to the current outputs , and said common bias circuit coupled to said first and second networks consisting of a plurality of diodes and a constant current source coupled between a pair of supply voltages .
US6854067B1 CLAIM 19 . The method as recited in claim 18 , wherein said f4) further comprises : communicating each said optimal value to said power supply scaler (load circuit) via said bus ; registering each said optimal value with said matrix of multiplexers and registers ; commanding said matrix of multiplexers and registers to change said independent multiple of said common supply voltage to correspond with said optimal value ; and monitoring said matrix of multiplexers and registers .	US5043674A CLAIM 1 . A differential amplifier circuit for producing an output current proportional to the differential input voltage regardless of the common-mode input voltage comprising : identical first and second voltage networks coupled between first and second differential voltage inputs and coupled to common differential current outputs , and to a common bias circuit , each of said networks being connected to a respective one of said differential voltage inputs through a respective input resistor , and to respective one of said differential current outputs and cross coupled to the other one of said differential current outputs and containing a current mirror consisting of a current mirror transistor , directly coupled to the said other one of said outputs , and a diode , and transistor means for generating an impedance reference voltage for the respective input resistor coupled to said network , said transistor means being further coupled to said respective one of said outputs and said current mirror , a load circuit (mode pump power supply, power supply scaler) coupled to the current outputs , and said common bias circuit coupled to said first and second networks consisting of a plurality of diodes and a constant current source coupled between a pair of supply voltages .
US6854067B1 CLAIM 20 . In a microcontroller having a power on reset circuit interconnected with a processor a method of dynamically controlling said power state , said method comprising : a) ascertaining a power state powered by a switched mode pump power supply (load circuit) , said switched mode pump power supply interconnected with and responsive to control by said power on reset circuit ; b) programmatically determining desired changes to said power state ; c) intercommunicating between said processor and said power on reset circuit ; d) adjusting said power on reset circuit corresponding to said desired changes to said power state ; e) controlling said switched mode pump power supply according to said d) ; and f) repeating said a) through e) .	US5043674A CLAIM 1 . A differential amplifier circuit for producing an output current proportional to the differential input voltage regardless of the common-mode input voltage comprising : identical first and second voltage networks coupled between first and second differential voltage inputs and coupled to common differential current outputs , and to a common bias circuit , each of said networks being connected to a respective one of said differential voltage inputs through a respective input resistor , and to respective one of said differential current outputs and cross coupled to the other one of said differential current outputs and containing a current mirror consisting of a current mirror transistor , directly coupled to the said other one of said outputs , and a diode , and transistor means for generating an impedance reference voltage for the respective input resistor coupled to said network , said transistor means being further coupled to said respective one of said outputs and said current mirror , a load circuit (mode pump power supply, power supply scaler) coupled to the current outputs , and said common bias circuit coupled to said first and second networks consisting of a plurality of diodes and a constant current source coupled between a pair of supply voltages .

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	US5006974A Filed: 1990-04-27 Issued: 1991-04-09 On-chip high voltage generator and regulator in an integrated circuit (Original Assignee) Waferscale Integration Inc (Current Assignee) STMicroelectronics lnc USA Reza Kazerounian, Syed Ali, Boaz Eitan
US6854067B1 CLAIM 6 . The method as recited in claim 5 , wherein said c) further comprises : c1) generating a precision reference voltage (said switch) ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US5006974A CLAIM 6 . The circuit of claim 4 further comprising a register , the state of said switch (precision reference voltage) es being determined by data stored in said register .
US6854067B1 CLAIM 7 . The method as recited in claim 6 , wherein said precision reference voltage (said switch) is independent of said common supply voltage .	US5006974A CLAIM 6 . The circuit of claim 4 further comprising a register , the state of said switch (precision reference voltage) es being determined by data stored in said register .
US6854067B1 CLAIM 11 . The method as recited in claim 10 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state corresponding to said status ; f3) programmatically calculating an optimal value (conductive layers) for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	US5006974A CLAIM 2 . The circuit of claim 1 wherein said plurality capacitors comprises : an insulating layer ; a first plurality of conductive layers (optimal value) formed over said insulating layer , each conductive layer within said plurality serving as a plate of at least one of said capacitors within said plurality of capacitors ; a second plurality of conductive layers , a first one of said conductive layers within said second plurality serving as a first plate of a first capacitor within said plurality of capacitors and being formed over but insulated from a first portion of a first conductive layer within said first plurality , said first conductive layer within said first plurality serving as the second plate of said first capacitor and a first plate of a second capacitor within said plurality of capacitors , a second conductive layer within said second plurality of conductive layers being formed over a second portion of said first conductive layer within said first plurality and serving as a second plate of said second capacitor , said second conductive layer within said second plurality extending over but being insulated from at least a portion of a second conductive layer within said first plurality and serving as a first plate of a third capacitor within said plurality of capacitors , said second conductive layer within said first plurality serving as a second plate of said third capacitor .
US6854067B1 CLAIM 12 . The method as recited in claim 11 , wherein said f4) further comprises : communicating each said optimal value (conductive layers) to said power supply scaler via said bus ; registering each said optimal value with said matrix of multiplexers and registers ; commanding said matrix of multiplexers and registers to change said independent multiple of said common supply voltage to correspond with said optimal value ; and monitoring said matrix of multiplexers and registers .	US5006974A CLAIM 2 . The circuit of claim 1 wherein said plurality capacitors comprises : an insulating layer ; a first plurality of conductive layers (optimal value) formed over said insulating layer , each conductive layer within said plurality serving as a plate of at least one of said capacitors within said plurality of capacitors ; a second plurality of conductive layers , a first one of said conductive layers within said second plurality serving as a first plate of a first capacitor within said plurality of capacitors and being formed over but insulated from a first portion of a first conductive layer within said first plurality , said first conductive layer within said first plurality serving as the second plate of said first capacitor and a first plate of a second capacitor within said plurality of capacitors , a second conductive layer within said second plurality of conductive layers being formed over a second portion of said first conductive layer within said first plurality and serving as a second plate of said second capacitor , said second conductive layer within said second plurality extending over but being insulated from at least a portion of a second conductive layer within said first plurality and serving as a first plate of a third capacitor within said plurality of capacitors , said second conductive layer within said first plurality serving as a second plate of said third capacitor .
US6854067B1 CLAIM 16 . The system as recited in claim 15 , wherein said c) further comprises : c1) generating a precision reference voltage (said switch) , said precision reference voltage independent of said common supply voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US5006974A CLAIM 6 . The circuit of claim 4 further comprising a register , the state of said switch (precision reference voltage) es being determined by data stored in said register .
US6854067B1 CLAIM 18 . The system as recited in claim 17 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state corresponding to said status ; f3) programmatically calculating an optimal value (conductive layers) for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	US5006974A CLAIM 2 . The circuit of claim 1 wherein said plurality capacitors comprises : an insulating layer ; a first plurality of conductive layers (optimal value) formed over said insulating layer , each conductive layer within said plurality serving as a plate of at least one of said capacitors within said plurality of capacitors ; a second plurality of conductive layers , a first one of said conductive layers within said second plurality serving as a first plate of a first capacitor within said plurality of capacitors and being formed over but insulated from a first portion of a first conductive layer within said first plurality , said first conductive layer within said first plurality serving as the second plate of said first capacitor and a first plate of a second capacitor within said plurality of capacitors , a second conductive layer within said second plurality of conductive layers being formed over a second portion of said first conductive layer within said first plurality and serving as a second plate of said second capacitor , said second conductive layer within said second plurality extending over but being insulated from at least a portion of a second conductive layer within said first plurality and serving as a first plate of a third capacitor within said plurality of capacitors , said second conductive layer within said first plurality serving as a second plate of said third capacitor .
US6854067B1 CLAIM 19 . The method as recited in claim 18 , wherein said f4) further comprises : communicating each said optimal value (conductive layers) to said power supply scaler via said bus ; registering each said optimal value with said matrix of multiplexers and registers ; commanding said matrix of multiplexers and registers to change said independent multiple of said common supply voltage to correspond with said optimal value ; and monitoring said matrix of multiplexers and registers .	US5006974A CLAIM 2 . The circuit of claim 1 wherein said plurality capacitors comprises : an insulating layer ; a first plurality of conductive layers (optimal value) formed over said insulating layer , each conductive layer within said plurality serving as a plate of at least one of said capacitors within said plurality of capacitors ; a second plurality of conductive layers , a first one of said conductive layers within said second plurality serving as a first plate of a first capacitor within said plurality of capacitors and being formed over but insulated from a first portion of a first conductive layer within said first plurality , said first conductive layer within said first plurality serving as the second plate of said first capacitor and a first plate of a second capacitor within said plurality of capacitors , a second conductive layer within said second plurality of conductive layers being formed over a second portion of said first conductive layer within said first plurality and serving as a second plate of said second capacitor , said second conductive layer within said second plurality extending over but being insulated from at least a portion of a second conductive layer within said first plurality and serving as a first plate of a third capacitor within said plurality of capacitors , said second conductive layer within said first plurality serving as a second plate of said third capacitor .

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	US5198817A Filed: 1990-04-26 Issued: 1993-03-30 High-order sigma-delta analog-to-digital converter (Original Assignee) Hughes Aircraft Co (Current Assignee) DirecTV Group Inc Robert H. Walden, Gabor C. Temes, Tanju Cataltepe
US6854067B1 CLAIM 6 . The method as recited in claim 5 , wherein said c) further comprises : c1) generating a precision reference voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one (first sample) of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US5198817A CLAIM 1 . An analog-to-digital converter for converting an analog input signal to a stable digital output sequence , comprising : first integrating network means for generating a first sample (comparisons comparing one) d analog signal in response to said analog input signal ; second integrating network means for generating a second sampled analog signal in response to said first sampled analog signal ; third integrating network means for generating a third sampled analog signal in response to said second sampled analog signal ; multibit quantizer means for generating said stable digital output sequence in response to said third sampled analog signal ; and feedback means operatively coupled to said first , second and third integrating network means for generating an analog feedback signal from said stable digital output sequence , wherein said second integrating network is coupled to said first integrating network and said third integrating network is coupled to said second integrating network and each of said first , second and third integrating network means includes a switched capacitor input element , a switched capacitor feedback element , and a switched capacitor integrator element , said switched capacitor input element and said switched capacitor feedback element are each operatively coupled to said switched capacitor integrator element , capacitive ratios , respectively , of said switched capacitor input element to said switched capacitor integrator element and of said switched capacitor feedback element to said switched capacitor integrator element being selected to provide a pole pattern having said stable digital output sequence .
US6854067B1 CLAIM 11 . The method as recited in claim 10 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power (back circuit) state corresponding to said status ; f3) programmatically calculating an optimal value (first integrating) for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	US5198817A CLAIM 1 . An analog-to-digital converter for converting an analog input signal to a stable digital output sequence , comprising : first integrating (optimal value) network means for generating a first sampled analog signal in response to said analog input signal ; second integrating network means for generating a second sampled analog signal in response to said first sampled analog signal ; third integrating network means for generating a third sampled analog signal in response to said second sampled analog signal ; multibit quantizer means for generating said stable digital output sequence in response to said third sampled analog signal ; and feedback means operatively coupled to said first , second and third integrating network means for generating an analog feedback signal from said stable digital output sequence , wherein said second integrating network is coupled to said first integrating network and said third integrating network is coupled to said second integrating network and each of said first , second and third integrating network means includes a switched capacitor input element , a switched capacitor feedback element , and a switched capacitor integrator element , said switched capacitor input element and said switched capacitor feedback element are each operatively coupled to said switched capacitor integrator element , capacitive ratios , respectively , of said switched capacitor input element to said switched capacitor integrator element and of said switched capacitor feedback element to said switched capacitor integrator element being selected to provide a pole pattern having said stable digital output sequence . US5198817A CLAIM 6 . A method for designing an analog-to-digital converter for converting an analog input signal to a stable digital output sequence , said method comprising the steps of : providing a first integrating network for generating a first sampled analog signal in response to said analog input signal ; providing a second integrating network for generating a second sampled analog signal in response to said first sampled analog signal ; providing a third integrating network for generating a third sampled analog signal in response to said second sampled analog signal ; wherein each of said first , second and third integrating networks includes a switched capacitor input element , a switched capacitor feedback element , and a switched capacitor integrator element ; providing a multiple quantizer for generating said stable digital output sequence in response to said third sampled analog signal ; providing a feedback circuit (optimal power) operatively coupled to said first , second and third integrating networks for generating an analog feedback signal from said stable digital output sequence ; and selecting a capacitor coefficient for each of said switched capacitor input element , switched capacitor feedback element , and switched capacitor integrator element such that capacitive ratios , respectively , of said switched capacitor input element to said switched capacitor integrator element and of said switched capacitor feedback element to said switched capacitor integrator element provides a pole pattern having said stable digital output sequence .
US6854067B1 CLAIM 12 . The method as recited in claim 11 , wherein said f4) further comprises : communicating each said optimal value (first integrating) to said power supply scaler via said bus ; registering each said optimal value with said matrix of multiplexers and registers ; commanding said matrix of multiplexers and registers to change said independent multiple of said common supply voltage to correspond with said optimal value ; and monitoring said matrix of multiplexers and registers .	US5198817A CLAIM 1 . An analog-to-digital converter for converting an analog input signal to a stable digital output sequence , comprising : first integrating (optimal value) network means for generating a first sampled analog signal in response to said analog input signal ; second integrating network means for generating a second sampled analog signal in response to said first sampled analog signal ; third integrating network means for generating a third sampled analog signal in response to said second sampled analog signal ; multibit quantizer means for generating said stable digital output sequence in response to said third sampled analog signal ; and feedback means operatively coupled to said first , second and third integrating network means for generating an analog feedback signal from said stable digital output sequence , wherein said second integrating network is coupled to said first integrating network and said third integrating network is coupled to said second integrating network and each of said first , second and third integrating network means includes a switched capacitor input element , a switched capacitor feedback element , and a switched capacitor integrator element , said switched capacitor input element and said switched capacitor feedback element are each operatively coupled to said switched capacitor integrator element , capacitive ratios , respectively , of said switched capacitor input element to said switched capacitor integrator element and of said switched capacitor feedback element to said switched capacitor integrator element being selected to provide a pole pattern having said stable digital output sequence .
US6854067B1 CLAIM 16 . The system as recited in claim 15 , wherein said c) further comprises : c1) generating a precision reference voltage , said precision reference voltage independent of said common supply voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one (first sample) of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US5198817A CLAIM 1 . An analog-to-digital converter for converting an analog input signal to a stable digital output sequence , comprising : first integrating network means for generating a first sample (comparisons comparing one) d analog signal in response to said analog input signal ; second integrating network means for generating a second sampled analog signal in response to said first sampled analog signal ; third integrating network means for generating a third sampled analog signal in response to said second sampled analog signal ; multibit quantizer means for generating said stable digital output sequence in response to said third sampled analog signal ; and feedback means operatively coupled to said first , second and third integrating network means for generating an analog feedback signal from said stable digital output sequence , wherein said second integrating network is coupled to said first integrating network and said third integrating network is coupled to said second integrating network and each of said first , second and third integrating network means includes a switched capacitor input element , a switched capacitor feedback element , and a switched capacitor integrator element , said switched capacitor input element and said switched capacitor feedback element are each operatively coupled to said switched capacitor integrator element , capacitive ratios , respectively , of said switched capacitor input element to said switched capacitor integrator element and of said switched capacitor feedback element to said switched capacitor integrator element being selected to provide a pole pattern having said stable digital output sequence .
US6854067B1 CLAIM 18 . The system as recited in claim 17 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power (back circuit) state corresponding to said status ; f3) programmatically calculating an optimal value (first integrating) for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	US5198817A CLAIM 1 . An analog-to-digital converter for converting an analog input signal to a stable digital output sequence , comprising : first integrating (optimal value) network means for generating a first sampled analog signal in response to said analog input signal ; second integrating network means for generating a second sampled analog signal in response to said first sampled analog signal ; third integrating network means for generating a third sampled analog signal in response to said second sampled analog signal ; multibit quantizer means for generating said stable digital output sequence in response to said third sampled analog signal ; and feedback means operatively coupled to said first , second and third integrating network means for generating an analog feedback signal from said stable digital output sequence , wherein said second integrating network is coupled to said first integrating network and said third integrating network is coupled to said second integrating network and each of said first , second and third integrating network means includes a switched capacitor input element , a switched capacitor feedback element , and a switched capacitor integrator element , said switched capacitor input element and said switched capacitor feedback element are each operatively coupled to said switched capacitor integrator element , capacitive ratios , respectively , of said switched capacitor input element to said switched capacitor integrator element and of said switched capacitor feedback element to said switched capacitor integrator element being selected to provide a pole pattern having said stable digital output sequence . US5198817A CLAIM 6 . A method for designing an analog-to-digital converter for converting an analog input signal to a stable digital output sequence , said method comprising the steps of : providing a first integrating network for generating a first sampled analog signal in response to said analog input signal ; providing a second integrating network for generating a second sampled analog signal in response to said first sampled analog signal ; providing a third integrating network for generating a third sampled analog signal in response to said second sampled analog signal ; wherein each of said first , second and third integrating networks includes a switched capacitor input element , a switched capacitor feedback element , and a switched capacitor integrator element ; providing a multiple quantizer for generating said stable digital output sequence in response to said third sampled analog signal ; providing a feedback circuit (optimal power) operatively coupled to said first , second and third integrating networks for generating an analog feedback signal from said stable digital output sequence ; and selecting a capacitor coefficient for each of said switched capacitor input element , switched capacitor feedback element , and switched capacitor integrator element such that capacitive ratios , respectively , of said switched capacitor input element to said switched capacitor integrator element and of said switched capacitor feedback element to said switched capacitor integrator element provides a pole pattern having said stable digital output sequence .
US6854067B1 CLAIM 19 . The method as recited in claim 18 , wherein said f4) further comprises : communicating each said optimal value (first integrating) to said power supply scaler via said bus ; registering each said optimal value with said matrix of multiplexers and registers ; commanding said matrix of multiplexers and registers to change said independent multiple of said common supply voltage to correspond with said optimal value ; and monitoring said matrix of multiplexers and registers .	US5198817A CLAIM 1 . An analog-to-digital converter for converting an analog input signal to a stable digital output sequence , comprising : first integrating (optimal value) network means for generating a first sampled analog signal in response to said analog input signal ; second integrating network means for generating a second sampled analog signal in response to said first sampled analog signal ; third integrating network means for generating a third sampled analog signal in response to said second sampled analog signal ; multibit quantizer means for generating said stable digital output sequence in response to said third sampled analog signal ; and feedback means operatively coupled to said first , second and third integrating network means for generating an analog feedback signal from said stable digital output sequence , wherein said second integrating network is coupled to said first integrating network and said third integrating network is coupled to said second integrating network and each of said first , second and third integrating network means includes a switched capacitor input element , a switched capacitor feedback element , and a switched capacitor integrator element , said switched capacitor input element and said switched capacitor feedback element are each operatively coupled to said switched capacitor integrator element , capacitive ratios , respectively , of said switched capacitor input element to said switched capacitor integrator element and of said switched capacitor feedback element to said switched capacitor integrator element being selected to provide a pole pattern having said stable digital output sequence .

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	US5144582A Filed: 1990-03-30 Issued: 1992-09-01 Sram based cell for programmable logic devices (Original Assignee) SGS Thomson Microelectronics Inc (Current Assignee) STMicroelectronics lnc USA Randy C. Steele
US6854067B1 CLAIM 1 . In a microcontroller with an embedded processor , a switched mode pump power supply (single line) and power on reset circuit (output node) , a method of dynamically controlling a plurality of power stability functions (NAND gate) for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply , wherein said processor and said power on reset circuit are interconnectedly coupled , and wherein said switched mode pump power supply is interconnectedly coupled with said power on reset circuit and responsive to signals therefrom ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor ; e) controlling certain functions of said microcontroller accordingly .	US5144582A CLAIM 6 . The device of claim 5 , wherein each SRAM cell in the matrix has an output connected to a NAND gate (power stability functions) , wherein a second input for each NAND gate is connected to a selected row or complementary row signal , and wherein an output of each NAND gate is connected to an input of one of said logic gates . US5144582A CLAIM 9 . An AND-OR array for a semiconductor integrated circuit programmable logic device , comprising : a plurality of linear arrays of SRAM cells , each linear array corresponding to a product term of the AND-OR array ; wherein each SRAM cell contains a programming bit defining a connection in the AND-OR array ; a plurality of first logic gates , each of said logic gates connected to at least two of the SRAM cells in a single line (mode pump power supply, precision reference voltage) ar array ; and at least one additional logic gate having inputs connected to outputs of selected first logic gates or to outputs of selected additional logic gates , wherein said additional logic gates combine signals from the SRAM cells so as to generate an output signal which is defined as a product term for each of said linear arrays . US5144582A CLAIM 10 . The AND-OR array of claim 9 , wherein the SRAM cells are grouped into pairs of cells having a common output node (reset circuit) , and wherein the common output nodes connect to the inputs of said first logic gates .
US6854067B1 CLAIM 2 . The method as recited in claim 1 , further comprising : f) dynamically programming said power on reset circuit (output node) .	US5144582A CLAIM 10 . The AND-OR array of claim 9 , wherein the SRAM cells are grouped into pairs of cells having a common output node (reset circuit) , and wherein the common output nodes connect to the inputs of said first logic gates .
US6854067B1 CLAIM 3 . The method as recited in claim 2 , wherein said power on reset circuit (output node) and said processor are interconnected via a bus .	US5144582A CLAIM 10 . The AND-OR array of claim 9 , wherein the SRAM cells are grouped into pairs of cells having a common output node (reset circuit) , and wherein the common output nodes connect to the inputs of said first logic gates .
US6854067B1 CLAIM 4 . The method as recited in claim 3 , wherein said b) and said c) are accomplished by said power on reset circuit (output node) .	US5144582A CLAIM 10 . The AND-OR array of claim 9 , wherein the SRAM cells are grouped into pairs of cells having a common output node (reset circuit) , and wherein the common output nodes connect to the inputs of said first logic gates .
US6854067B1 CLAIM 6 . The method as recited in claim 5 , wherein said c) further comprises : c1) generating a precision reference voltage (single line) ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US5144582A CLAIM 9 . An AND-OR array for a semiconductor integrated circuit programmable logic device , comprising : a plurality of linear arrays of SRAM cells , each linear array corresponding to a product term of the AND-OR array ; wherein each SRAM cell contains a programming bit defining a connection in the AND-OR array ; a plurality of first logic gates , each of said logic gates connected to at least two of the SRAM cells in a single line (mode pump power supply, precision reference voltage) ar array ; and at least one additional logic gate having inputs connected to outputs of selected first logic gates or to outputs of selected additional logic gates , wherein said additional logic gates combine signals from the SRAM cells so as to generate an output signal which is defined as a product term for each of said linear arrays .
US6854067B1 CLAIM 7 . The method as recited in claim 6 , wherein said precision reference voltage (single line) is independent of said common supply voltage .	US5144582A CLAIM 9 . An AND-OR array for a semiconductor integrated circuit programmable logic device , comprising : a plurality of linear arrays of SRAM cells , each linear array corresponding to a product term of the AND-OR array ; wherein each SRAM cell contains a programming bit defining a connection in the AND-OR array ; a plurality of first logic gates , each of said logic gates connected to at least two of the SRAM cells in a single line (mode pump power supply, precision reference voltage) ar array ; and at least one additional logic gate having inputs connected to outputs of selected first logic gates or to outputs of selected additional logic gates , wherein said additional logic gates combine signals from the SRAM cells so as to generate an output signal which is defined as a product term for each of said linear arrays .
US6854067B1 CLAIM 11 . The method as recited in claim 10 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state (d log) corresponding to said status ; f3) programmatically calculating an optimal value (first log) for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	US5144582A CLAIM 1 . A programmable logic device having a plurality of inputs and a plurality of outputs connected to an AND-OR array for defining logic functions to be performed by the device , comprising : a plurality of SRAM cells arranged in a regular matrix for storing program information defining connections in the AND-OR array ; and log (optimal power state) ic gates connecting outputs from selected SRAM cells together to perform logic functions thereon , said logic gates generating outputs which define product terms of the AND-OR array . US5144582A CLAIM 9 . An AND-OR array for a semiconductor integrated circuit programmable logic device , comprising : a plurality of linear arrays of SRAM cells , each linear array corresponding to a product term of the AND-OR array ; wherein each SRAM cell contains a programming bit defining a connection in the AND-OR array ; a plurality of first log (optimal value) ic gates , each of said logic gates connected to at least two of the SRAM cells in a single linear array ; and at least one additional logic gate having inputs connected to outputs of selected first logic gates or to outputs of selected additional logic gates , wherein said additional logic gates combine signals from the SRAM cells so as to generate an output signal which is defined as a product term for each of said linear arrays .
US6854067B1 CLAIM 12 . The method as recited in claim 11 , wherein said f4) further comprises : communicating each said optimal value (first log) to said power supply scaler via said bus ; registering each said optimal value with said matrix of multiplexers and registers ; commanding said matrix of multiplexers and registers to change said independent multiple of said common supply voltage to correspond with said optimal value ; and monitoring said matrix of multiplexers and registers .	US5144582A CLAIM 9 . An AND-OR array for a semiconductor integrated circuit programmable logic device , comprising : a plurality of linear arrays of SRAM cells , each linear array corresponding to a product term of the AND-OR array ; wherein each SRAM cell contains a programming bit defining a connection in the AND-OR array ; a plurality of first log (optimal value) ic gates , each of said logic gates connected to at least two of the SRAM cells in a single linear array ; and at least one additional logic gate having inputs connected to outputs of selected first logic gates or to outputs of selected additional logic gates , wherein said additional logic gates combine signals from the SRAM cells so as to generate an output signal which is defined as a product term for each of said linear arrays .
US6854067B1 CLAIM 13 . In a microcontroller , a system comprising : a bus ; a processor coupled to said bus ; a power on reset circuit (output node) , said processor and said power on reset circuit coupled to said bus and interconnectedly coupled with said processor via said bus ; and a switched mode pump power supply (single line) interconnectedly coupled with said power on reset circuit and responsive to signals therefrom wherein said system executes a method of dynamically controlling a plurality of power stability functions (NAND gate) for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor via said bus ; e) controlling certain functions of said microcontroller according to said suitability status ; and f) dynamically programming said power on reset circuit via said bus .	US5144582A CLAIM 6 . The device of claim 5 , wherein each SRAM cell in the matrix has an output connected to a NAND gate (power stability functions) , wherein a second input for each NAND gate is connected to a selected row or complementary row signal , and wherein an output of each NAND gate is connected to an input of one of said logic gates . US5144582A CLAIM 9 . An AND-OR array for a semiconductor integrated circuit programmable logic device , comprising : a plurality of linear arrays of SRAM cells , each linear array corresponding to a product term of the AND-OR array ; wherein each SRAM cell contains a programming bit defining a connection in the AND-OR array ; a plurality of first logic gates , each of said logic gates connected to at least two of the SRAM cells in a single line (mode pump power supply, precision reference voltage) ar array ; and at least one additional logic gate having inputs connected to outputs of selected first logic gates or to outputs of selected additional logic gates , wherein said additional logic gates combine signals from the SRAM cells so as to generate an output signal which is defined as a product term for each of said linear arrays . US5144582A CLAIM 10 . The AND-OR array of claim 9 , wherein the SRAM cells are grouped into pairs of cells having a common output node (reset circuit) , and wherein the common output nodes connect to the inputs of said first logic gates .
US6854067B1 CLAIM 14 . The system as recited in claim 13 , wherein said b) and said c) of said method are accomplished by said power on reset circuit (output node) .	US5144582A CLAIM 10 . The AND-OR array of claim 9 , wherein the SRAM cells are grouped into pairs of cells having a common output node (reset circuit) , and wherein the common output nodes connect to the inputs of said first logic gates .
US6854067B1 CLAIM 16 . The system as recited in claim 15 , wherein said c) further comprises : c1) generating a precision reference voltage (single line) , said precision reference voltage independent of said common supply voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US5144582A CLAIM 9 . An AND-OR array for a semiconductor integrated circuit programmable logic device , comprising : a plurality of linear arrays of SRAM cells , each linear array corresponding to a product term of the AND-OR array ; wherein each SRAM cell contains a programming bit defining a connection in the AND-OR array ; a plurality of first logic gates , each of said logic gates connected to at least two of the SRAM cells in a single line (mode pump power supply, precision reference voltage) ar array ; and at least one additional logic gate having inputs connected to outputs of selected first logic gates or to outputs of selected additional logic gates , wherein said additional logic gates combine signals from the SRAM cells so as to generate an output signal which is defined as a product term for each of said linear arrays .
US6854067B1 CLAIM 18 . The system as recited in claim 17 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state (d log) corresponding to said status ; f3) programmatically calculating an optimal value (first log) for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	US5144582A CLAIM 1 . A programmable logic device having a plurality of inputs and a plurality of outputs connected to an AND-OR array for defining logic functions to be performed by the device , comprising : a plurality of SRAM cells arranged in a regular matrix for storing program information defining connections in the AND-OR array ; and log (optimal power state) ic gates connecting outputs from selected SRAM cells together to perform logic functions thereon , said logic gates generating outputs which define product terms of the AND-OR array . US5144582A CLAIM 9 . An AND-OR array for a semiconductor integrated circuit programmable logic device , comprising : a plurality of linear arrays of SRAM cells , each linear array corresponding to a product term of the AND-OR array ; wherein each SRAM cell contains a programming bit defining a connection in the AND-OR array ; a plurality of first log (optimal value) ic gates , each of said logic gates connected to at least two of the SRAM cells in a single linear array ; and at least one additional logic gate having inputs connected to outputs of selected first logic gates or to outputs of selected additional logic gates , wherein said additional logic gates combine signals from the SRAM cells so as to generate an output signal which is defined as a product term for each of said linear arrays .
US6854067B1 CLAIM 19 . The method as recited in claim 18 , wherein said f4) further comprises : communicating each said optimal value (first log) to said power supply scaler via said bus ; registering each said optimal value with said matrix of multiplexers and registers ; commanding said matrix of multiplexers and registers to change said independent multiple of said common supply voltage to correspond with said optimal value ; and monitoring said matrix of multiplexers and registers .	US5144582A CLAIM 9 . An AND-OR array for a semiconductor integrated circuit programmable logic device , comprising : a plurality of linear arrays of SRAM cells , each linear array corresponding to a product term of the AND-OR array ; wherein each SRAM cell contains a programming bit defining a connection in the AND-OR array ; a plurality of first log (optimal value) ic gates , each of said logic gates connected to at least two of the SRAM cells in a single linear array ; and at least one additional logic gate having inputs connected to outputs of selected first logic gates or to outputs of selected additional logic gates , wherein said additional logic gates combine signals from the SRAM cells so as to generate an output signal which is defined as a product term for each of said linear arrays .
US6854067B1 CLAIM 20 . In a microcontroller having a power on reset circuit (output node) interconnected with a processor a method of dynamically controlling said power state , said method comprising : a) ascertaining a power state powered by a switched mode pump power supply (single line) , said switched mode pump power supply interconnected with and responsive to control by said power on reset circuit ; b) programmatically determining desired changes to said power state ; c) intercommunicating between said processor and said power on reset circuit ; d) adjusting said power on reset circuit corresponding to said desired changes to said power state ; e) controlling said switched mode pump power supply according to said d) ; and f) repeating said a) through e) .	US5144582A CLAIM 9 . An AND-OR array for a semiconductor integrated circuit programmable logic device , comprising : a plurality of linear arrays of SRAM cells , each linear array corresponding to a product term of the AND-OR array ; wherein each SRAM cell contains a programming bit defining a connection in the AND-OR array ; a plurality of first logic gates , each of said logic gates connected to at least two of the SRAM cells in a single line (mode pump power supply, precision reference voltage) ar array ; and at least one additional logic gate having inputs connected to outputs of selected first logic gates or to outputs of selected additional logic gates , wherein said additional logic gates combine signals from the SRAM cells so as to generate an output signal which is defined as a product term for each of said linear arrays . US5144582A CLAIM 10 . The AND-OR array of claim 9 , wherein the SRAM cells are grouped into pairs of cells having a common output node (reset circuit) , and wherein the common output nodes connect to the inputs of said first logic gates .

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	US5068622A Filed: 1990-02-28 Issued: 1991-11-26 CMOS amplifier with offset adaptation (Original Assignee) Synaptics Inc (Current Assignee) Synaptics Inc Carver A. Mead, Timothy P. Allen
US6854067B1 CLAIM 1 . In a microcontroller with an embedded processor , a switched mode pump power supply and power on reset circuit (output node) , a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply , wherein said processor and said power on reset circuit are interconnectedly coupled , and wherein said switched mode pump power supply is interconnectedly coupled with said power on reset circuit and responsive to signals therefrom ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor ; e) controlling certain functions of said microcontroller accordingly .	US5068622A CLAIM 1 . An analog MOS amplifier fabricated as a part of an integrated circuit , said amplifier having a gain of magnitude much larger than 1 , including : an non-inverting input node , an inverting input node , an output node (reset circuit) , a floating node , a first MOS P-channel input transistor , having its gate connected to said non-inverting input node , a second MOS P-channel input transistor , having its gate connected to said floating node , a first current mirror including first and second MOS N-channel transistors , said first MOS N-channel transistor having its drain and gate connected to the drain of said first MOS P-channel input transistor and its source connected to a source of negative voltage , said second MOS N-channel transistor having its gate connected to the gate of said first MOS N-channel transistor , its drain connected to said output node and its source connected to said source of negative voltage , an MOS P-channel bias transistor having its gate connected to a source of bias voltage , its drain connected to the sources of both said first and second MOS P-channel input transistors , and its source connected to a source of positive voltage , a second current mirror including third and fourth MOS N-channel transistors , said third MOS N-channel transistor having its drain and gate connected to the drain of said second MOS P-channel input transistor and its source connected to said source of negative voltage , said fourth MOS N-channel transistor having its gate connected to the gate of said third MOS N-channel transistor and its source connected to said source of negative voltage , a third current mirror including first and second MOS P-channel current mirror transistors , said first MOS P-channel current mirror transistor having its drain and gate connected to the drain of said fourth MOS N-channel transistor , and its source connected to said source of positive voltage , said second MOS P-channel current mirror transistor having its gate connected to the gate of said first MOS P-channel current mirror transistor , its drain connected to said output node and its source connected to said source of positive voltage , a first MOS capacitor having a first electrode connected to said inverting input node and a second electrode connected to said floating node , a second MOS capacitor having a first electrode connected to said output node and a second electrode connected to said floating node , an opaque layer covering portions of the surface of said integrated circuit containing active circuits , said opaque layer having an aperture therein above said second capacitor for allowing ultraviolet light to fall onto said first and second electrodes of said second capacitor whereby the offset voltage of said amplifier can be adapted while a source of ultraviolet light is present .
US6854067B1 CLAIM 2 . The method as recited in claim 1 , further comprising : f) dynamically programming said power on reset circuit (output node) .	US5068622A CLAIM 1 . An analog MOS amplifier fabricated as a part of an integrated circuit , said amplifier having a gain of magnitude much larger than 1 , including : an non-inverting input node , an inverting input node , an output node (reset circuit) , a floating node , a first MOS P-channel input transistor , having its gate connected to said non-inverting input node , a second MOS P-channel input transistor , having its gate connected to said floating node , a first current mirror including first and second MOS N-channel transistors , said first MOS N-channel transistor having its drain and gate connected to the drain of said first MOS P-channel input transistor and its source connected to a source of negative voltage , said second MOS N-channel transistor having its gate connected to the gate of said first MOS N-channel transistor , its drain connected to said output node and its source connected to said source of negative voltage , an MOS P-channel bias transistor having its gate connected to a source of bias voltage , its drain connected to the sources of both said first and second MOS P-channel input transistors , and its source connected to a source of positive voltage , a second current mirror including third and fourth MOS N-channel transistors , said third MOS N-channel transistor having its drain and gate connected to the drain of said second MOS P-channel input transistor and its source connected to said source of negative voltage , said fourth MOS N-channel transistor having its gate connected to the gate of said third MOS N-channel transistor and its source connected to said source of negative voltage , a third current mirror including first and second MOS P-channel current mirror transistors , said first MOS P-channel current mirror transistor having its drain and gate connected to the drain of said fourth MOS N-channel transistor , and its source connected to said source of positive voltage , said second MOS P-channel current mirror transistor having its gate connected to the gate of said first MOS P-channel current mirror transistor , its drain connected to said output node and its source connected to said source of positive voltage , a first MOS capacitor having a first electrode connected to said inverting input node and a second electrode connected to said floating node , a second MOS capacitor having a first electrode connected to said output node and a second electrode connected to said floating node , an opaque layer covering portions of the surface of said integrated circuit containing active circuits , said opaque layer having an aperture therein above said second capacitor for allowing ultraviolet light to fall onto said first and second electrodes of said second capacitor whereby the offset voltage of said amplifier can be adapted while a source of ultraviolet light is present .
US6854067B1 CLAIM 3 . The method as recited in claim 2 , wherein said power on reset circuit (output node) and said processor are interconnected via a bus .	US5068622A CLAIM 1 . An analog MOS amplifier fabricated as a part of an integrated circuit , said amplifier having a gain of magnitude much larger than 1 , including : an non-inverting input node , an inverting input node , an output node (reset circuit) , a floating node , a first MOS P-channel input transistor , having its gate connected to said non-inverting input node , a second MOS P-channel input transistor , having its gate connected to said floating node , a first current mirror including first and second MOS N-channel transistors , said first MOS N-channel transistor having its drain and gate connected to the drain of said first MOS P-channel input transistor and its source connected to a source of negative voltage , said second MOS N-channel transistor having its gate connected to the gate of said first MOS N-channel transistor , its drain connected to said output node and its source connected to said source of negative voltage , an MOS P-channel bias transistor having its gate connected to a source of bias voltage , its drain connected to the sources of both said first and second MOS P-channel input transistors , and its source connected to a source of positive voltage , a second current mirror including third and fourth MOS N-channel transistors , said third MOS N-channel transistor having its drain and gate connected to the drain of said second MOS P-channel input transistor and its source connected to said source of negative voltage , said fourth MOS N-channel transistor having its gate connected to the gate of said third MOS N-channel transistor and its source connected to said source of negative voltage , a third current mirror including first and second MOS P-channel current mirror transistors , said first MOS P-channel current mirror transistor having its drain and gate connected to the drain of said fourth MOS N-channel transistor , and its source connected to said source of positive voltage , said second MOS P-channel current mirror transistor having its gate connected to the gate of said first MOS P-channel current mirror transistor , its drain connected to said output node and its source connected to said source of positive voltage , a first MOS capacitor having a first electrode connected to said inverting input node and a second electrode connected to said floating node , a second MOS capacitor having a first electrode connected to said output node and a second electrode connected to said floating node , an opaque layer covering portions of the surface of said integrated circuit containing active circuits , said opaque layer having an aperture therein above said second capacitor for allowing ultraviolet light to fall onto said first and second electrodes of said second capacitor whereby the offset voltage of said amplifier can be adapted while a source of ultraviolet light is present .
US6854067B1 CLAIM 4 . The method as recited in claim 3 , wherein said b) and said c) are accomplished by said power on reset circuit (output node) .	US5068622A CLAIM 1 . An analog MOS amplifier fabricated as a part of an integrated circuit , said amplifier having a gain of magnitude much larger than 1 , including : an non-inverting input node , an inverting input node , an output node (reset circuit) , a floating node , a first MOS P-channel input transistor , having its gate connected to said non-inverting input node , a second MOS P-channel input transistor , having its gate connected to said floating node , a first current mirror including first and second MOS N-channel transistors , said first MOS N-channel transistor having its drain and gate connected to the drain of said first MOS P-channel input transistor and its source connected to a source of negative voltage , said second MOS N-channel transistor having its gate connected to the gate of said first MOS N-channel transistor , its drain connected to said output node and its source connected to said source of negative voltage , an MOS P-channel bias transistor having its gate connected to a source of bias voltage , its drain connected to the sources of both said first and second MOS P-channel input transistors , and its source connected to a source of positive voltage , a second current mirror including third and fourth MOS N-channel transistors , said third MOS N-channel transistor having its drain and gate connected to the drain of said second MOS P-channel input transistor and its source connected to said source of negative voltage , said fourth MOS N-channel transistor having its gate connected to the gate of said third MOS N-channel transistor and its source connected to said source of negative voltage , a third current mirror including first and second MOS P-channel current mirror transistors , said first MOS P-channel current mirror transistor having its drain and gate connected to the drain of said fourth MOS N-channel transistor , and its source connected to said source of positive voltage , said second MOS P-channel current mirror transistor having its gate connected to the gate of said first MOS P-channel current mirror transistor , its drain connected to said output node and its source connected to said source of positive voltage , a first MOS capacitor having a first electrode connected to said inverting input node and a second electrode connected to said floating node , a second MOS capacitor having a first electrode connected to said output node and a second electrode connected to said floating node , an opaque layer covering portions of the surface of said integrated circuit containing active circuits , said opaque layer having an aperture therein above said second capacitor for allowing ultraviolet light to fall onto said first and second electrodes of said second capacitor whereby the offset voltage of said amplifier can be adapted while a source of ultraviolet light is present .
US6854067B1 CLAIM 6 . The method as recited in claim 5 , wherein said c) further comprises : c1) generating a precision reference voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals (negative voltage) , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US5068622A CLAIM 1 . An analog MOS amplifier fabricated as a part of an integrated circuit , said amplifier having a gain of magnitude much larger than 1 , including : an non-inverting input node , an inverting input node , an output node , a floating node , a first MOS P-channel input transistor , having its gate connected to said non-inverting input node , a second MOS P-channel input transistor , having its gate connected to said floating node , a first current mirror including first and second MOS N-channel transistors , said first MOS N-channel transistor having its drain and gate connected to the drain of said first MOS P-channel input transistor and its source connected to a source of negative voltage (power state condition signals) , said second MOS N-channel transistor having its gate connected to the gate of said first MOS N-channel transistor , its drain connected to said output node and its source connected to said source of negative voltage , an MOS P-channel bias transistor having its gate connected to a source of bias voltage , its drain connected to the sources of both said first and second MOS P-channel input transistors , and its source connected to a source of positive voltage , a second current mirror including third and fourth MOS N-channel transistors , said third MOS N-channel transistor having its drain and gate connected to the drain of said second MOS P-channel input transistor and its source connected to said source of negative voltage , said fourth MOS N-channel transistor having its gate connected to the gate of said third MOS N-channel transistor and its source connected to said source of negative voltage , a third current mirror including first and second MOS P-channel current mirror transistors , said first MOS P-channel current mirror transistor having its drain and gate connected to the drain of said fourth MOS N-channel transistor , and its source connected to said source of positive voltage , said second MOS P-channel current mirror transistor having its gate connected to the gate of said first MOS P-channel current mirror transistor , its drain connected to said output node and its source connected to said source of positive voltage , a first MOS capacitor having a first electrode connected to said inverting input node and a second electrode connected to said floating node , a second MOS capacitor having a first electrode connected to said output node and a second electrode connected to said floating node , an opaque layer covering portions of the surface of said integrated circuit containing active circuits , said opaque layer having an aperture therein above said second capacitor for allowing ultraviolet light to fall onto said first and second electrodes of said second capacitor whereby the offset voltage of said amplifier can be adapted while a source of ultraviolet light is present .
US6854067B1 CLAIM 13 . In a microcontroller , a system comprising : a bus ; a processor coupled to said bus ; a power on reset circuit (output node) , said processor and said power on reset circuit coupled to said bus and interconnectedly coupled with said processor via said bus ; and a switched mode pump power supply interconnectedly coupled with said power on reset circuit and responsive to signals therefrom wherein said system executes a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor via said bus ; e) controlling certain functions of said microcontroller according to said suitability status ; and f) dynamically programming said power on reset circuit via said bus .	US5068622A CLAIM 1 . An analog MOS amplifier fabricated as a part of an integrated circuit , said amplifier having a gain of magnitude much larger than 1 , including : an non-inverting input node , an inverting input node , an output node (reset circuit) , a floating node , a first MOS P-channel input transistor , having its gate connected to said non-inverting input node , a second MOS P-channel input transistor , having its gate connected to said floating node , a first current mirror including first and second MOS N-channel transistors , said first MOS N-channel transistor having its drain and gate connected to the drain of said first MOS P-channel input transistor and its source connected to a source of negative voltage , said second MOS N-channel transistor having its gate connected to the gate of said first MOS N-channel transistor , its drain connected to said output node and its source connected to said source of negative voltage , an MOS P-channel bias transistor having its gate connected to a source of bias voltage , its drain connected to the sources of both said first and second MOS P-channel input transistors , and its source connected to a source of positive voltage , a second current mirror including third and fourth MOS N-channel transistors , said third MOS N-channel transistor having its drain and gate connected to the drain of said second MOS P-channel input transistor and its source connected to said source of negative voltage , said fourth MOS N-channel transistor having its gate connected to the gate of said third MOS N-channel transistor and its source connected to said source of negative voltage , a third current mirror including first and second MOS P-channel current mirror transistors , said first MOS P-channel current mirror transistor having its drain and gate connected to the drain of said fourth MOS N-channel transistor , and its source connected to said source of positive voltage , said second MOS P-channel current mirror transistor having its gate connected to the gate of said first MOS P-channel current mirror transistor , its drain connected to said output node and its source connected to said source of positive voltage , a first MOS capacitor having a first electrode connected to said inverting input node and a second electrode connected to said floating node , a second MOS capacitor having a first electrode connected to said output node and a second electrode connected to said floating node , an opaque layer covering portions of the surface of said integrated circuit containing active circuits , said opaque layer having an aperture therein above said second capacitor for allowing ultraviolet light to fall onto said first and second electrodes of said second capacitor whereby the offset voltage of said amplifier can be adapted while a source of ultraviolet light is present .
US6854067B1 CLAIM 14 . The system as recited in claim 13 , wherein said b) and said c) of said method are accomplished by said power on reset circuit (output node) .	US5068622A CLAIM 4 . An adaptive analog MOS inverting amplifier fabricated as a part of an integrated circuit , said amplifier having a gain of magnitude much larger than 1 , including : an non-inverting input node , an inverting input node , an output node (reset circuit) , an amplifying element having a gain larger than 1 , including an inverting input , a non-inverting input , and an output , said output connected to said output node , a first floating node , connected to the inverting input of said amplifying element , a first MOS capacitor having a first electrode connected to said inverting input node and a second electrode connected to said first floating node , a second floating node , connected to the non-inverting input of said amplifying element , a second MOS capacitor having a first electrode connected to said non-inverting input node and a second electrode connected to said second floating node , a third MOS capacitor having a first electrode connected to said output node and a second electrode connected to said first floating node , a fourth MOS capacitor having a first electrode connected to said second floating node and a second electrode connected to a source of fixed voltage , the ratio of said third MOS capacitor to said first MOS capacitor being substantially equal to the ratio of said fourth MOS capacitor to said second MOS capacitor , and an opaque layer covering portions of the surface of said integrated circuit containing active circuits , said opaque layer having an aperture therein above said third capacitor for allowing ultraviolet light to fall onto said first and second electrodes of said third capacitor whereby the offset voltage of said adaptive amplifier can be adapted while a source of ultraviolet light is present .
US6854067B1 CLAIM 20 . In a microcontroller having a power on reset circuit (output node) interconnected with a processor a method of dynamically controlling said power state , said method comprising : a) ascertaining a power state powered by a switched mode pump power supply , said switched mode pump power supply interconnected with and responsive to control by said power on reset circuit ; b) programmatically determining desired changes to said power state ; c) intercommunicating between said processor and said power on reset circuit ; d) adjusting said power on reset circuit corresponding to said desired changes to said power state ; e) controlling said switched mode pump power supply according to said d) ; and f) repeating said a) through e) .	US5068622A CLAIM 4 . An adaptive analog MOS inverting amplifier fabricated as a part of an integrated circuit , said amplifier having a gain of magnitude much larger than 1 , including : an non-inverting input node , an inverting input node , an output node (reset circuit) , an amplifying element having a gain larger than 1 , including an inverting input , a non-inverting input , and an output , said output connected to said output node , a first floating node , connected to the inverting input of said amplifying element , a first MOS capacitor having a first electrode connected to said inverting input node and a second electrode connected to said first floating node , a second floating node , connected to the non-inverting input of said amplifying element , a second MOS capacitor having a first electrode connected to said non-inverting input node and a second electrode connected to said second floating node , a third MOS capacitor having a first electrode connected to said output node and a second electrode connected to said first floating node , a fourth MOS capacitor having a first electrode connected to said second floating node and a second electrode connected to a source of fixed voltage , the ratio of said third MOS capacitor to said first MOS capacitor being substantially equal to the ratio of said fourth MOS capacitor to said second MOS capacitor , and an opaque layer covering portions of the surface of said integrated circuit containing active circuits , said opaque layer having an aperture therein above said third capacitor for allowing ultraviolet light to fall onto said first and second electrodes of said third capacitor whereby the offset voltage of said adaptive amplifier can be adapted while a source of ultraviolet light is present .

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	US4980652A Filed: 1989-08-31 Issued: 1990-12-25 Frequency synthesizer having compensation for nonlinearities (Original Assignee) Nippon Telegraph and Telephone Corp (Current Assignee) NTT Docomo Inc Yoshiaki Tarusawa, Shigeki Saito, Yasushi Yamao, Toshio Nojima
US6854067B1 CLAIM 1 . In a microcontroller with an embedded processor , a switched mode pump power supply and power on reset circuit (pass filter) , a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply , wherein said processor and said power on reset circuit are interconnectedly coupled , and wherein said switched mode pump power supply is interconnectedly coupled with said power on reset circuit and responsive to signals therefrom ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor ; e) controlling certain functions of said microcontroller accordingly .	US4980652A CLAIM 3 . A frequency synthesizer , comprising : a voltage controlled oscillator which produces an output having a frequency which is non-linearly dependent on an input control voltage , a variable ratio divider which divides said output from said voltage controlled oscillator according to a variable division ratio , a phase detector which compares a phase of a divided output from said variable ratio divider with a reference signal , a loop filter which smooths an output from said phase detector and supplies the smoothed output to said voltage controlled oscillator , and oscillation frequency switching means for switching an oscillation frequency of said voltage controlled oscillator by changing the division ratio of said variable divider ; wherein said oscillation frequency switching means includes : voltage supply means for producing said control voltage , corresponding to a commanded oscillation frequency after switching , in synchronization with the change of said division ratio at said variable ratio divider ; voltage measuring means for measuring the smoothed output voltage from said loop filter before said switching of the oscillation frequency , and wherein said voltage supply means includes control voltage compensation means for correcting said smoothed output voltage to produce said control voltage which is supplied to said voltage controlled oscillator , said correcting based on the measured voltage measured by said voltage measuring means and corresponding to a non-linearity of the voltage controlled oscillator ; wherein said voltage supply means is digital , and includes a D/A converter to produce an analog output signal , said voltage measuring means including an A/D converter ; and further comprising a low-pass filter (reset circuit) , connected between an output of the D/A converter and said input control voltage , and wherein said voltage supply means includes means for sequentially setting plural different voltages before setting said control voltage at the D/A converter output corresponding to the frequency after switching .
US6854067B1 CLAIM 2 . The method as recited in claim 1 , further comprising : f) dynamically programming said power on reset circuit (pass filter) .	US4980652A CLAIM 3 . A frequency synthesizer , comprising : a voltage controlled oscillator which produces an output having a frequency which is non-linearly dependent on an input control voltage , a variable ratio divider which divides said output from said voltage controlled oscillator according to a variable division ratio , a phase detector which compares a phase of a divided output from said variable ratio divider with a reference signal , a loop filter which smooths an output from said phase detector and supplies the smoothed output to said voltage controlled oscillator , and oscillation frequency switching means for switching an oscillation frequency of said voltage controlled oscillator by changing the division ratio of said variable divider ; wherein said oscillation frequency switching means includes : voltage supply means for producing said control voltage , corresponding to a commanded oscillation frequency after switching , in synchronization with the change of said division ratio at said variable ratio divider ; voltage measuring means for measuring the smoothed output voltage from said loop filter before said switching of the oscillation frequency , and wherein said voltage supply means includes control voltage compensation means for correcting said smoothed output voltage to produce said control voltage which is supplied to said voltage controlled oscillator , said correcting based on the measured voltage measured by said voltage measuring means and corresponding to a non-linearity of the voltage controlled oscillator ; wherein said voltage supply means is digital , and includes a D/A converter to produce an analog output signal , said voltage measuring means including an A/D converter ; and further comprising a low-pass filter (reset circuit) , connected between an output of the D/A converter and said input control voltage , and wherein said voltage supply means includes means for sequentially setting plural different voltages before setting said control voltage at the D/A converter output corresponding to the frequency after switching .
US6854067B1 CLAIM 3 . The method as recited in claim 2 , wherein said power on reset circuit (pass filter) and said processor are interconnected via a bus .	US4980652A CLAIM 3 . A frequency synthesizer , comprising : a voltage controlled oscillator which produces an output having a frequency which is non-linearly dependent on an input control voltage , a variable ratio divider which divides said output from said voltage controlled oscillator according to a variable division ratio , a phase detector which compares a phase of a divided output from said variable ratio divider with a reference signal , a loop filter which smooths an output from said phase detector and supplies the smoothed output to said voltage controlled oscillator , and oscillation frequency switching means for switching an oscillation frequency of said voltage controlled oscillator by changing the division ratio of said variable divider ; wherein said oscillation frequency switching means includes : voltage supply means for producing said control voltage , corresponding to a commanded oscillation frequency after switching , in synchronization with the change of said division ratio at said variable ratio divider ; voltage measuring means for measuring the smoothed output voltage from said loop filter before said switching of the oscillation frequency , and wherein said voltage supply means includes control voltage compensation means for correcting said smoothed output voltage to produce said control voltage which is supplied to said voltage controlled oscillator , said correcting based on the measured voltage measured by said voltage measuring means and corresponding to a non-linearity of the voltage controlled oscillator ; wherein said voltage supply means is digital , and includes a D/A converter to produce an analog output signal , said voltage measuring means including an A/D converter ; and further comprising a low-pass filter (reset circuit) , connected between an output of the D/A converter and said input control voltage , and wherein said voltage supply means includes means for sequentially setting plural different voltages before setting said control voltage at the D/A converter output corresponding to the frequency after switching .
US6854067B1 CLAIM 4 . The method as recited in claim 3 , wherein said b) and said c) are accomplished by said power on reset circuit (pass filter) .	US4980652A CLAIM 3 . A frequency synthesizer , comprising : a voltage controlled oscillator which produces an output having a frequency which is non-linearly dependent on an input control voltage , a variable ratio divider which divides said output from said voltage controlled oscillator according to a variable division ratio , a phase detector which compares a phase of a divided output from said variable ratio divider with a reference signal , a loop filter which smooths an output from said phase detector and supplies the smoothed output to said voltage controlled oscillator , and oscillation frequency switching means for switching an oscillation frequency of said voltage controlled oscillator by changing the division ratio of said variable divider ; wherein said oscillation frequency switching means includes : voltage supply means for producing said control voltage , corresponding to a commanded oscillation frequency after switching , in synchronization with the change of said division ratio at said variable ratio divider ; voltage measuring means for measuring the smoothed output voltage from said loop filter before said switching of the oscillation frequency , and wherein said voltage supply means includes control voltage compensation means for correcting said smoothed output voltage to produce said control voltage which is supplied to said voltage controlled oscillator , said correcting based on the measured voltage measured by said voltage measuring means and corresponding to a non-linearity of the voltage controlled oscillator ; wherein said voltage supply means is digital , and includes a D/A converter to produce an analog output signal , said voltage measuring means including an A/D converter ; and further comprising a low-pass filter (reset circuit) , connected between an output of the D/A converter and said input control voltage , and wherein said voltage supply means includes means for sequentially setting plural different voltages before setting said control voltage at the D/A converter output corresponding to the frequency after switching .
US6854067B1 CLAIM 6 . The method as recited in claim 5 , wherein said c) further comprises : c1) generating a precision reference voltage (measured value, said switch) ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US4980652A CLAIM 1 . A frequency synthesizer , comprising : a voltage controlled oscillator which produces an output having a frequency which is non-linearly dependent on an input control voltage , a variable ratio divider which divides said output from said voltage controlled oscillator according to a variable division ratio , a phase detector which compares a phase of a divided output from said variable ratio divider with a reference signal , a loop filter which smooths an output from said phase detector and supplies the smoothed output to said voltage controlled oscillator , and oscillation frequency switching means for switching an oscillation frequency of said voltage controlled oscillator by changing the division ratio of said variable divider ; wherein said oscillation frequency switching means includes : voltage supply means for producing said control voltage , corresponding to a commanded oscillation frequency after switching , in synchronization with the change of said division ratio at said variable ratio divider ; voltage measuring means for measuring the smoothed output voltage from said loop filter before said switch (precision reference voltage) ing of the oscillation frequency , and wherein said voltage supply means includes control voltage compensation means for correcting said smoothed output voltage to produce said control voltage which is supplied to said voltage controlled oscillator , said correcting based on the measured voltage measured by said voltage measuring means and corresponding to a non-linearity of the voltage controlled oscillator ; wherein said voltage supply means is digital , and includes a D/A converter to produce an analog output signal , said voltage measuring means including an A/D converter ; and further comprising a variable bandwidth filter connected to an output of the D/A converter and having its output connected to said voltage supply means , wherein the oscillation frequency switching means includes a bandwidth limiting means for narrowing a bandwidth of said variable bandwidth filter after switching the oscillation frequency . US4980652A CLAIM 6 . The frequency synthesizer as claimed in claim 4 wherein the voltage controlled oscillator is an oscillator in which oscillation frequency corresponding to the input voltage changes non-linearly , and further comprising : a voltage measuring means , which measures via an A/D converter the voltage supplied from the loop filter to the voltage controlled oscillator before switching of the oscillation frequency , and the voltage supply means includes control voltage compensation means for producing a correction factor which corrects the voltage supplied to said voltage controlled oscillator corresponding to the non-linearity of the voltage controlled oscillator and based on the measured value (precision reference voltage) of said voltage measuring means .
US6854067B1 CLAIM 7 . The method as recited in claim 6 , wherein said precision reference voltage (measured value, said switch) is independent of said common supply voltage .	US4980652A CLAIM 1 . A frequency synthesizer , comprising : a voltage controlled oscillator which produces an output having a frequency which is non-linearly dependent on an input control voltage , a variable ratio divider which divides said output from said voltage controlled oscillator according to a variable division ratio , a phase detector which compares a phase of a divided output from said variable ratio divider with a reference signal , a loop filter which smooths an output from said phase detector and supplies the smoothed output to said voltage controlled oscillator , and oscillation frequency switching means for switching an oscillation frequency of said voltage controlled oscillator by changing the division ratio of said variable divider ; wherein said oscillation frequency switching means includes : voltage supply means for producing said control voltage , corresponding to a commanded oscillation frequency after switching , in synchronization with the change of said division ratio at said variable ratio divider ; voltage measuring means for measuring the smoothed output voltage from said loop filter before said switch (precision reference voltage) ing of the oscillation frequency , and wherein said voltage supply means includes control voltage compensation means for correcting said smoothed output voltage to produce said control voltage which is supplied to said voltage controlled oscillator , said correcting based on the measured voltage measured by said voltage measuring means and corresponding to a non-linearity of the voltage controlled oscillator ; wherein said voltage supply means is digital , and includes a D/A converter to produce an analog output signal , said voltage measuring means including an A/D converter ; and further comprising a variable bandwidth filter connected to an output of the D/A converter and having its output connected to said voltage supply means , wherein the oscillation frequency switching means includes a bandwidth limiting means for narrowing a bandwidth of said variable bandwidth filter after switching the oscillation frequency . US4980652A CLAIM 6 . The frequency synthesizer as claimed in claim 4 wherein the voltage controlled oscillator is an oscillator in which oscillation frequency corresponding to the input voltage changes non-linearly , and further comprising : a voltage measuring means , which measures via an A/D converter the voltage supplied from the loop filter to the voltage controlled oscillator before switching of the oscillation frequency , and the voltage supply means includes control voltage compensation means for producing a correction factor which corrects the voltage supplied to said voltage controlled oscillator corresponding to the non-linearity of the voltage controlled oscillator and based on the measured value (precision reference voltage) of said voltage measuring means .
US6854067B1 CLAIM 13 . In a microcontroller , a system comprising : a bus ; a processor coupled to said bus ; a power on reset circuit (pass filter) , said processor and said power on reset circuit coupled to said bus and interconnectedly coupled with said processor via said bus ; and a switched mode pump power supply interconnectedly coupled with said power on reset circuit and responsive to signals therefrom wherein said system executes a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor via said bus ; e) controlling certain functions of said microcontroller according to said suitability status ; and f) dynamically programming said power on reset circuit via said bus .	US4980652A CLAIM 3 . A frequency synthesizer , comprising : a voltage controlled oscillator which produces an output having a frequency which is non-linearly dependent on an input control voltage , a variable ratio divider which divides said output from said voltage controlled oscillator according to a variable division ratio , a phase detector which compares a phase of a divided output from said variable ratio divider with a reference signal , a loop filter which smooths an output from said phase detector and supplies the smoothed output to said voltage controlled oscillator , and oscillation frequency switching means for switching an oscillation frequency of said voltage controlled oscillator by changing the division ratio of said variable divider ; wherein said oscillation frequency switching means includes : voltage supply means for producing said control voltage , corresponding to a commanded oscillation frequency after switching , in synchronization with the change of said division ratio at said variable ratio divider ; voltage measuring means for measuring the smoothed output voltage from said loop filter before said switching of the oscillation frequency , and wherein said voltage supply means includes control voltage compensation means for correcting said smoothed output voltage to produce said control voltage which is supplied to said voltage controlled oscillator , said correcting based on the measured voltage measured by said voltage measuring means and corresponding to a non-linearity of the voltage controlled oscillator ; wherein said voltage supply means is digital , and includes a D/A converter to produce an analog output signal , said voltage measuring means including an A/D converter ; and further comprising a low-pass filter (reset circuit) , connected between an output of the D/A converter and said input control voltage , and wherein said voltage supply means includes means for sequentially setting plural different voltages before setting said control voltage at the D/A converter output corresponding to the frequency after switching .
US6854067B1 CLAIM 14 . The system as recited in claim 13 , wherein said b) and said c) of said method are accomplished by said power on reset circuit (pass filter) .	US4980652A CLAIM 3 . A frequency synthesizer , comprising : a voltage controlled oscillator which produces an output having a frequency which is non-linearly dependent on an input control voltage , a variable ratio divider which divides said output from said voltage controlled oscillator according to a variable division ratio , a phase detector which compares a phase of a divided output from said variable ratio divider with a reference signal , a loop filter which smooths an output from said phase detector and supplies the smoothed output to said voltage controlled oscillator , and oscillation frequency switching means for switching an oscillation frequency of said voltage controlled oscillator by changing the division ratio of said variable divider ; wherein said oscillation frequency switching means includes : voltage supply means for producing said control voltage , corresponding to a commanded oscillation frequency after switching , in synchronization with the change of said division ratio at said variable ratio divider ; voltage measuring means for measuring the smoothed output voltage from said loop filter before said switching of the oscillation frequency , and wherein said voltage supply means includes control voltage compensation means for correcting said smoothed output voltage to produce said control voltage which is supplied to said voltage controlled oscillator , said correcting based on the measured voltage measured by said voltage measuring means and corresponding to a non-linearity of the voltage controlled oscillator ; wherein said voltage supply means is digital , and includes a D/A converter to produce an analog output signal , said voltage measuring means including an A/D converter ; and further comprising a low-pass filter (reset circuit) , connected between an output of the D/A converter and said input control voltage , and wherein said voltage supply means includes means for sequentially setting plural different voltages before setting said control voltage at the D/A converter output corresponding to the frequency after switching .
US6854067B1 CLAIM 16 . The system as recited in claim 15 , wherein said c) further comprises : c1) generating a precision reference voltage (measured value, said switch) , said precision reference voltage independent of said common supply voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US4980652A CLAIM 1 . A frequency synthesizer , comprising : a voltage controlled oscillator which produces an output having a frequency which is non-linearly dependent on an input control voltage , a variable ratio divider which divides said output from said voltage controlled oscillator according to a variable division ratio , a phase detector which compares a phase of a divided output from said variable ratio divider with a reference signal , a loop filter which smooths an output from said phase detector and supplies the smoothed output to said voltage controlled oscillator , and oscillation frequency switching means for switching an oscillation frequency of said voltage controlled oscillator by changing the division ratio of said variable divider ; wherein said oscillation frequency switching means includes : voltage supply means for producing said control voltage , corresponding to a commanded oscillation frequency after switching , in synchronization with the change of said division ratio at said variable ratio divider ; voltage measuring means for measuring the smoothed output voltage from said loop filter before said switch (precision reference voltage) ing of the oscillation frequency , and wherein said voltage supply means includes control voltage compensation means for correcting said smoothed output voltage to produce said control voltage which is supplied to said voltage controlled oscillator , said correcting based on the measured voltage measured by said voltage measuring means and corresponding to a non-linearity of the voltage controlled oscillator ; wherein said voltage supply means is digital , and includes a D/A converter to produce an analog output signal , said voltage measuring means including an A/D converter ; and further comprising a variable bandwidth filter connected to an output of the D/A converter and having its output connected to said voltage supply means , wherein the oscillation frequency switching means includes a bandwidth limiting means for narrowing a bandwidth of said variable bandwidth filter after switching the oscillation frequency . US4980652A CLAIM 6 . The frequency synthesizer as claimed in claim 4 wherein the voltage controlled oscillator is an oscillator in which oscillation frequency corresponding to the input voltage changes non-linearly , and further comprising : a voltage measuring means , which measures via an A/D converter the voltage supplied from the loop filter to the voltage controlled oscillator before switching of the oscillation frequency , and the voltage supply means includes control voltage compensation means for producing a correction factor which corrects the voltage supplied to said voltage controlled oscillator corresponding to the non-linearity of the voltage controlled oscillator and based on the measured value (precision reference voltage) of said voltage measuring means .
US6854067B1 CLAIM 20 . In a microcontroller having a power on reset circuit (pass filter) interconnected with a processor a method of dynamically controlling said power state , said method comprising : a) ascertaining a power state powered by a switched mode pump power supply , said switched mode pump power supply interconnected with and responsive to control by said power on reset circuit ; b) programmatically determining desired changes to said power state ; c) intercommunicating between said processor and said power on reset circuit ; d) adjusting said power on reset circuit corresponding to said desired changes to said power state ; e) controlling said switched mode pump power supply according to said d) ; and f) repeating said a) through e) .	US4980652A CLAIM 3 . A frequency synthesizer , comprising : a voltage controlled oscillator which produces an output having a frequency which is non-linearly dependent on an input control voltage , a variable ratio divider which divides said output from said voltage controlled oscillator according to a variable division ratio , a phase detector which compares a phase of a divided output from said variable ratio divider with a reference signal , a loop filter which smooths an output from said phase detector and supplies the smoothed output to said voltage controlled oscillator , and oscillation frequency switching means for switching an oscillation frequency of said voltage controlled oscillator by changing the division ratio of said variable divider ; wherein said oscillation frequency switching means includes : voltage supply means for producing said control voltage , corresponding to a commanded oscillation frequency after switching , in synchronization with the change of said division ratio at said variable ratio divider ; voltage measuring means for measuring the smoothed output voltage from said loop filter before said switching of the oscillation frequency , and wherein said voltage supply means includes control voltage compensation means for correcting said smoothed output voltage to produce said control voltage which is supplied to said voltage controlled oscillator , said correcting based on the measured voltage measured by said voltage measuring means and corresponding to a non-linearity of the voltage controlled oscillator ; wherein said voltage supply means is digital , and includes a D/A converter to produce an analog output signal , said voltage measuring means including an A/D converter ; and further comprising a low-pass filter (reset circuit) , connected between an output of the D/A converter and said input control voltage , and wherein said voltage supply means includes means for sequentially setting plural different voltages before setting said control voltage at the D/A converter output corresponding to the frequency after switching .

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	US4977381A Filed: 1989-06-05 Issued: 1990-12-11 Differential relaxation oscillator (Original Assignee) Motorola Solutions Inc (Current Assignee) NXP USA Inc William E. Main
US6854067B1 CLAIM 6 . The method as recited in claim 5 , wherein said c) further comprises : c1) generating a precision reference voltage (said switch) ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US4977381A CLAIM 1 . An oscillator , comprising : first current supply means for providing first and second currents at first and second outputs ; second current supply means for providing a current substantially equal to the sum of said first and second currents ; capacitive means coupled between said first and second outputs of said first current supply means for developing first and second dynamic voltages ; switching means having first and second inputs coupled to said first and second outputs of said first current supply means respectively and having an output coupled to said second current supply means wherein said switch (precision reference voltage) ing means is responsive to first and second complementary control signals for alternately switching the current flow of said first and second currents flowing through said capacitive means ; first means responsive to said first and second dynamic voltages for providing said first and second complementary control signals to control the switching of said switching means wherein the magnitude of the slew rate of said first and second dynamic voltages remains substantially constant for each frequency of operation ; and second means responsive to said first and second dynamic voltages for controlling said first current supply means or said second current supply means to maintain the magnitude of the DC (direct current) voltage developed across said capacitive means at a predetermined value .
US6854067B1 CLAIM 7 . The method as recited in claim 6 , wherein said precision reference voltage (said switch) is independent of said common supply voltage .	US4977381A CLAIM 1 . An oscillator , comprising : first current supply means for providing first and second currents at first and second outputs ; second current supply means for providing a current substantially equal to the sum of said first and second currents ; capacitive means coupled between said first and second outputs of said first current supply means for developing first and second dynamic voltages ; switching means having first and second inputs coupled to said first and second outputs of said first current supply means respectively and having an output coupled to said second current supply means wherein said switch (precision reference voltage) ing means is responsive to first and second complementary control signals for alternately switching the current flow of said first and second currents flowing through said capacitive means ; first means responsive to said first and second dynamic voltages for providing said first and second complementary control signals to control the switching of said switching means wherein the magnitude of the slew rate of said first and second dynamic voltages remains substantially constant for each frequency of operation ; and second means responsive to said first and second dynamic voltages for controlling said first current supply means or said second current supply means to maintain the magnitude of the DC (direct current) voltage developed across said capacitive means at a predetermined value .
US6854067B1 CLAIM 9 . The method as recited in claim 8 , wherein said b2) is performed by a power supply scaler (dynamic voltage) , and wherein said power supply scaler comprises : a) a divider of said common supply voltage ; b) a matrix of multiplexers and registers , and c) an interconnection to said bus .	US4977381A CLAIM 1 . An oscillator , comprising : first current supply means for providing first and second currents at first and second outputs ; second current supply means for providing a current substantially equal to the sum of said first and second currents ; capacitive means coupled between said first and second outputs of said first current supply means for developing first and second dynamic voltage (power supply scaler) s ; switching means having first and second inputs coupled to said first and second outputs of said first current supply means respectively and having an output coupled to said second current supply means wherein said switching means is responsive to first and second complementary control signals for alternately switching the current flow of said first and second currents flowing through said capacitive means ; first means responsive to said first and second dynamic voltages for providing said first and second complementary control signals to control the switching of said switching means wherein the magnitude of the slew rate of said first and second dynamic voltages remains substantially constant for each frequency of operation ; and second means responsive to said first and second dynamic voltages for controlling said first current supply means or said second current supply means to maintain the magnitude of the DC (direct current) voltage developed across said capacitive means at a predetermined value .
US6854067B1 CLAIM 12 . The method as recited in claim 11 , wherein said f4) further comprises : communicating each said optimal value to said power supply scaler (dynamic voltage) via said bus ; registering each said optimal value with said matrix of multiplexers and registers ; commanding said matrix of multiplexers and registers to change said independent multiple of said common supply voltage to correspond with said optimal value ; and monitoring said matrix of multiplexers and registers .	US4977381A CLAIM 1 . An oscillator , comprising : first current supply means for providing first and second currents at first and second outputs ; second current supply means for providing a current substantially equal to the sum of said first and second currents ; capacitive means coupled between said first and second outputs of said first current supply means for developing first and second dynamic voltage (power supply scaler) s ; switching means having first and second inputs coupled to said first and second outputs of said first current supply means respectively and having an output coupled to said second current supply means wherein said switching means is responsive to first and second complementary control signals for alternately switching the current flow of said first and second currents flowing through said capacitive means ; first means responsive to said first and second dynamic voltages for providing said first and second complementary control signals to control the switching of said switching means wherein the magnitude of the slew rate of said first and second dynamic voltages remains substantially constant for each frequency of operation ; and second means responsive to said first and second dynamic voltages for controlling said first current supply means or said second current supply means to maintain the magnitude of the DC (direct current) voltage developed across said capacitive means at a predetermined value .
US6854067B1 CLAIM 16 . The system as recited in claim 15 , wherein said c) further comprises : c1) generating a precision reference voltage (said switch) , said precision reference voltage independent of said common supply voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US4977381A CLAIM 1 . An oscillator , comprising : first current supply means for providing first and second currents at first and second outputs ; second current supply means for providing a current substantially equal to the sum of said first and second currents ; capacitive means coupled between said first and second outputs of said first current supply means for developing first and second dynamic voltages ; switching means having first and second inputs coupled to said first and second outputs of said first current supply means respectively and having an output coupled to said second current supply means wherein said switch (precision reference voltage) ing means is responsive to first and second complementary control signals for alternately switching the current flow of said first and second currents flowing through said capacitive means ; first means responsive to said first and second dynamic voltages for providing said first and second complementary control signals to control the switching of said switching means wherein the magnitude of the slew rate of said first and second dynamic voltages remains substantially constant for each frequency of operation ; and second means responsive to said first and second dynamic voltages for controlling said first current supply means or said second current supply means to maintain the magnitude of the DC (direct current) voltage developed across said capacitive means at a predetermined value .
US6854067B1 CLAIM 17 . The system as recited in claim 16 , wherein said b2) is performed by a power supply scaler (dynamic voltage) , wherein said power supply scaler comprises : a) a divider of said common supply voltage ; b) a matrix of multiplexers and registers , and c) an interconnection to said bus .	US4977381A CLAIM 1 . An oscillator , comprising : first current supply means for providing first and second currents at first and second outputs ; second current supply means for providing a current substantially equal to the sum of said first and second currents ; capacitive means coupled between said first and second outputs of said first current supply means for developing first and second dynamic voltage (power supply scaler) s ; switching means having first and second inputs coupled to said first and second outputs of said first current supply means respectively and having an output coupled to said second current supply means wherein said switching means is responsive to first and second complementary control signals for alternately switching the current flow of said first and second currents flowing through said capacitive means ; first means responsive to said first and second dynamic voltages for providing said first and second complementary control signals to control the switching of said switching means wherein the magnitude of the slew rate of said first and second dynamic voltages remains substantially constant for each frequency of operation ; and second means responsive to said first and second dynamic voltages for controlling said first current supply means or said second current supply means to maintain the magnitude of the DC (direct current) voltage developed across said capacitive means at a predetermined value .
US6854067B1 CLAIM 19 . The method as recited in claim 18 , wherein said f4) further comprises : communicating each said optimal value to said power supply scaler (dynamic voltage) via said bus ; registering each said optimal value with said matrix of multiplexers and registers ; commanding said matrix of multiplexers and registers to change said independent multiple of said common supply voltage to correspond with said optimal value ; and monitoring said matrix of multiplexers and registers .	US4977381A CLAIM 1 . An oscillator , comprising : first current supply means for providing first and second currents at first and second outputs ; second current supply means for providing a current substantially equal to the sum of said first and second currents ; capacitive means coupled between said first and second outputs of said first current supply means for developing first and second dynamic voltage (power supply scaler) s ; switching means having first and second inputs coupled to said first and second outputs of said first current supply means respectively and having an output coupled to said second current supply means wherein said switching means is responsive to first and second complementary control signals for alternately switching the current flow of said first and second currents flowing through said capacitive means ; first means responsive to said first and second dynamic voltages for providing said first and second complementary control signals to control the switching of said switching means wherein the magnitude of the slew rate of said first and second dynamic voltages remains substantially constant for each frequency of operation ; and second means responsive to said first and second dynamic voltages for controlling said first current supply means or said second current supply means to maintain the magnitude of the DC (direct current) voltage developed across said capacitive means at a predetermined value .

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	US5083044A Filed: 1989-05-25 Issued: 1992-01-21 Synaptic element and array (Original Assignee) Synaptics Inc (Current Assignee) Synaptics Inc Carver A. Mead, Timothy P. Allen, Federico Faggin, Janeen D. W. Anderson
US6854067B1 CLAIM 1 . In a microcontroller with an embedded processor , a switched mode pump power supply and power on reset circuit (output node) , a method of dynamically controlling a plurality of power stability functions (control means) for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply , wherein said processor and said power on reset circuit are interconnectedly coupled , and wherein said switched mode pump power supply is interconnectedly coupled with said power on reset circuit and responsive to signals therefrom ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor ; e) controlling certain functions of said microcontroller accordingly .	US5083044A CLAIM 1 . An electronic circuit fabricated as a part of an integrated circuit , said integrated circuit having a portion containing active circuits , said portion covered by an opaque layer , including in combination : a plurality of adaptive amplifiers arranged as an array including a plurality of columns and at least one row , each of said adaptive amplifiers having a gain of magnitude much larger than 1 and including : an output node (reset circuit) , a sense node , an inverting input node , said input node being a floating node forming the gate of at least one MOS transistor , a first capacitor for coupling an input to said adaptive amplifier to said floating node , said first capacitor having a first electrode connected to said input to said adaptive amplifier and a second electrode connected to said floating node , a second capacitor connected from said output node to said floating node , said second capacitor having a first electrode connected to said output node and a second electrode connected to said floating node , said opaque layer having an aperture therein above said second capacitor for allowing ultraviolet light to fall onto both electrodes of said second capacitor ; a voltage input line associated with each of said rows in said array , said voltage input line electrically connected to the first electrode of the first capacitor of each of said adaptive amplifiers associated with that particular row , a current output line associated with each of said columns in said array , said current output line electrically connected to the sense nodes of each of said adaptive amplifiers associated with that particular column . US5083044A CLAIM 3 . An electronic circuit fabricated as a part of an integrated circuit , said integrated circuit having a portion containing active circuits , said portion covered by an opaque layer , including in combination : a plurality of adaptive amplifiers arranged as an array including a plurality of columns and at least one row , each of said adaptive amplifiers having a gain of magnitude much larger than 1 and an offset voltage and including : an output node , a sense node , an inverting input node , said input node being a floating node forming the gate of at least one MOS transistor , a first capacitor for coupling an input to said adaptive amplifier to said floating node , said first capacitor having a first electrode connected to said input to said adaptive amplifier and a second electrode connected to said floating node , a second capacitor connected from said output node to said floating node , said second capacitor having a first electrode connected to said output node and a second electrode connected to said floating node , said opaque layer having an aperture therein above said second capacitor for allowing ultraviolet light to fall onto both electrodes of said second capacitor , a sample/hold circuit associated with each of said adaptive amplifiers , each of said sample/hold circuits having an input , a sample input , and an output , said output connected to said first electrode of said first capacitor , a voltage input/output line associated with each of said rows in said array , each of said voltage input lines electrically connected to the input of each of said sample/hold circuits associated with that particular row , a current output line associated with each of said columns in said array , each of said current output lines electrically connected to the sense node of each of said adaptive amplifiers associated with that particular column , a sample/hold line associated with each of said rows in said array , each of said sample/hold lines electrically connected to the sample inputs of each of said sample/hold circuits associated with that particular row , a plurality of switch means , including control means (power stability functions) , associated with each of said columns in said array , said switch means connected between the output nodes of each of said adaptive amplifiers associated with that particular column and the one of said input/output lines with which a particular adaptive amplifier in said column is associated , for selectively coupling the output nodes of said adaptive amplifiers to said input/output lines , a control line associated with each of said columns in said array , for activating said switch means to place the voltage on the output nodes of selected adaptive amplifiers onto said input/output lines .
US6854067B1 CLAIM 2 . The method as recited in claim 1 , further comprising : f) dynamically programming said power on reset circuit (output node) .	US5083044A CLAIM 1 . An electronic circuit fabricated as a part of an integrated circuit , said integrated circuit having a portion containing active circuits , said portion covered by an opaque layer , including in combination : a plurality of adaptive amplifiers arranged as an array including a plurality of columns and at least one row , each of said adaptive amplifiers having a gain of magnitude much larger than 1 and including : an output node (reset circuit) , a sense node , an inverting input node , said input node being a floating node forming the gate of at least one MOS transistor , a first capacitor for coupling an input to said adaptive amplifier to said floating node , said first capacitor having a first electrode connected to said input to said adaptive amplifier and a second electrode connected to said floating node , a second capacitor connected from said output node to said floating node , said second capacitor having a first electrode connected to said output node and a second electrode connected to said floating node , said opaque layer having an aperture therein above said second capacitor for allowing ultraviolet light to fall onto both electrodes of said second capacitor ; a voltage input line associated with each of said rows in said array , said voltage input line electrically connected to the first electrode of the first capacitor of each of said adaptive amplifiers associated with that particular row , a current output line associated with each of said columns in said array , said current output line electrically connected to the sense nodes of each of said adaptive amplifiers associated with that particular column .
US6854067B1 CLAIM 3 . The method as recited in claim 2 , wherein said power on reset circuit (output node) and said processor are interconnected via a bus .	US5083044A CLAIM 1 . An electronic circuit fabricated as a part of an integrated circuit , said integrated circuit having a portion containing active circuits , said portion covered by an opaque layer , including in combination : a plurality of adaptive amplifiers arranged as an array including a plurality of columns and at least one row , each of said adaptive amplifiers having a gain of magnitude much larger than 1 and including : an output node (reset circuit) , a sense node , an inverting input node , said input node being a floating node forming the gate of at least one MOS transistor , a first capacitor for coupling an input to said adaptive amplifier to said floating node , said first capacitor having a first electrode connected to said input to said adaptive amplifier and a second electrode connected to said floating node , a second capacitor connected from said output node to said floating node , said second capacitor having a first electrode connected to said output node and a second electrode connected to said floating node , said opaque layer having an aperture therein above said second capacitor for allowing ultraviolet light to fall onto both electrodes of said second capacitor ; a voltage input line associated with each of said rows in said array , said voltage input line electrically connected to the first electrode of the first capacitor of each of said adaptive amplifiers associated with that particular row , a current output line associated with each of said columns in said array , said current output line electrically connected to the sense nodes of each of said adaptive amplifiers associated with that particular column .
US6854067B1 CLAIM 4 . The method as recited in claim 3 , wherein said b) and said c) are accomplished by said power on reset circuit (output node) .	US5083044A CLAIM 1 . An electronic circuit fabricated as a part of an integrated circuit , said integrated circuit having a portion containing active circuits , said portion covered by an opaque layer , including in combination : a plurality of adaptive amplifiers arranged as an array including a plurality of columns and at least one row , each of said adaptive amplifiers having a gain of magnitude much larger than 1 and including : an output node (reset circuit) , a sense node , an inverting input node , said input node being a floating node forming the gate of at least one MOS transistor , a first capacitor for coupling an input to said adaptive amplifier to said floating node , said first capacitor having a first electrode connected to said input to said adaptive amplifier and a second electrode connected to said floating node , a second capacitor connected from said output node to said floating node , said second capacitor having a first electrode connected to said output node and a second electrode connected to said floating node , said opaque layer having an aperture therein above said second capacitor for allowing ultraviolet light to fall onto both electrodes of said second capacitor ; a voltage input line associated with each of said rows in said array , said voltage input line electrically connected to the first electrode of the first capacitor of each of said adaptive amplifiers associated with that particular row , a current output line associated with each of said columns in said array , said current output line electrically connected to the sense nodes of each of said adaptive amplifiers associated with that particular column .
US6854067B1 CLAIM 6 . The method as recited in claim 5 , wherein said c) further comprises : c1) generating a precision reference voltage (hold circuits, said switch) ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US5083044A CLAIM 3 . An electronic circuit fabricated as a part of an integrated circuit , said integrated circuit having a portion containing active circuits , said portion covered by an opaque layer , including in combination : a plurality of adaptive amplifiers arranged as an array including a plurality of columns and at least one row , each of said adaptive amplifiers having a gain of magnitude much larger than 1 and an offset voltage and including : an output node , a sense node , an inverting input node , said input node being a floating node forming the gate of at least one MOS transistor , a first capacitor for coupling an input to said adaptive amplifier to said floating node , said first capacitor having a first electrode connected to said input to said adaptive amplifier and a second electrode connected to said floating node , a second capacitor connected from said output node to said floating node , said second capacitor having a first electrode connected to said output node and a second electrode connected to said floating node , said opaque layer having an aperture therein above said second capacitor for allowing ultraviolet light to fall onto both electrodes of said second capacitor , a sample/hold circuit associated with each of said adaptive amplifiers , each of said sample/hold circuits (precision reference voltage) having an input , a sample input , and an output , said output connected to said first electrode of said first capacitor , a voltage input/output line associated with each of said rows in said array , each of said voltage input lines electrically connected to the input of each of said sample/hold circuits associated with that particular row , a current output line associated with each of said columns in said array , each of said current output lines electrically connected to the sense node of each of said adaptive amplifiers associated with that particular column , a sample/hold line associated with each of said rows in said array , each of said sample/hold lines electrically connected to the sample inputs of each of said sample/hold circuits associated with that particular row , a plurality of switch means , including control means , associated with each of said columns in said array , said switch (precision reference voltage) means connected between the output nodes of each of said adaptive amplifiers associated with that particular column and the one of said input/output lines with which a particular adaptive amplifier in said column is associated , for selectively coupling the output nodes of said adaptive amplifiers to said input/output lines , a control line associated with each of said columns in said array , for activating said switch means to place the voltage on the output nodes of selected adaptive amplifiers onto said input/output lines .
US6854067B1 CLAIM 7 . The method as recited in claim 6 , wherein said precision reference voltage (hold circuits, said switch) is independent of said common supply voltage .	US5083044A CLAIM 3 . An electronic circuit fabricated as a part of an integrated circuit , said integrated circuit having a portion containing active circuits , said portion covered by an opaque layer , including in combination : a plurality of adaptive amplifiers arranged as an array including a plurality of columns and at least one row , each of said adaptive amplifiers having a gain of magnitude much larger than 1 and an offset voltage and including : an output node , a sense node , an inverting input node , said input node being a floating node forming the gate of at least one MOS transistor , a first capacitor for coupling an input to said adaptive amplifier to said floating node , said first capacitor having a first electrode connected to said input to said adaptive amplifier and a second electrode connected to said floating node , a second capacitor connected from said output node to said floating node , said second capacitor having a first electrode connected to said output node and a second electrode connected to said floating node , said opaque layer having an aperture therein above said second capacitor for allowing ultraviolet light to fall onto both electrodes of said second capacitor , a sample/hold circuit associated with each of said adaptive amplifiers , each of said sample/hold circuits (precision reference voltage) having an input , a sample input , and an output , said output connected to said first electrode of said first capacitor , a voltage input/output line associated with each of said rows in said array , each of said voltage input lines electrically connected to the input of each of said sample/hold circuits associated with that particular row , a current output line associated with each of said columns in said array , each of said current output lines electrically connected to the sense node of each of said adaptive amplifiers associated with that particular column , a sample/hold line associated with each of said rows in said array , each of said sample/hold lines electrically connected to the sample inputs of each of said sample/hold circuits associated with that particular row , a plurality of switch means , including control means , associated with each of said columns in said array , said switch (precision reference voltage) means connected between the output nodes of each of said adaptive amplifiers associated with that particular column and the one of said input/output lines with which a particular adaptive amplifier in said column is associated , for selectively coupling the output nodes of said adaptive amplifiers to said input/output lines , a control line associated with each of said columns in said array , for activating said switch means to place the voltage on the output nodes of selected adaptive amplifiers onto said input/output lines .
US6854067B1 CLAIM 13 . In a microcontroller , a system comprising : a bus ; a processor coupled to said bus ; a power on reset circuit (output node) , said processor and said power on reset circuit coupled to said bus and interconnectedly coupled with said processor via said bus ; and a switched mode pump power supply interconnectedly coupled with said power on reset circuit and responsive to signals therefrom wherein said system executes a method of dynamically controlling a plurality of power stability functions (control means) for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor via said bus ; e) controlling certain functions of said microcontroller according to said suitability status ; and f) dynamically programming said power on reset circuit via said bus .	US5083044A CLAIM 1 . An electronic circuit fabricated as a part of an integrated circuit , said integrated circuit having a portion containing active circuits , said portion covered by an opaque layer , including in combination : a plurality of adaptive amplifiers arranged as an array including a plurality of columns and at least one row , each of said adaptive amplifiers having a gain of magnitude much larger than 1 and including : an output node (reset circuit) , a sense node , an inverting input node , said input node being a floating node forming the gate of at least one MOS transistor , a first capacitor for coupling an input to said adaptive amplifier to said floating node , said first capacitor having a first electrode connected to said input to said adaptive amplifier and a second electrode connected to said floating node , a second capacitor connected from said output node to said floating node , said second capacitor having a first electrode connected to said output node and a second electrode connected to said floating node , said opaque layer having an aperture therein above said second capacitor for allowing ultraviolet light to fall onto both electrodes of said second capacitor ; a voltage input line associated with each of said rows in said array , said voltage input line electrically connected to the first electrode of the first capacitor of each of said adaptive amplifiers associated with that particular row , a current output line associated with each of said columns in said array , said current output line electrically connected to the sense nodes of each of said adaptive amplifiers associated with that particular column .
US6854067B1 CLAIM 14 . The system as recited in claim 13 , wherein said b) and said c) of said method are accomplished by said power on reset circuit (output node) .	US5083044A CLAIM 1 . An electronic circuit fabricated as a part of an integrated circuit , said integrated circuit having a portion containing active circuits , said portion covered by an opaque layer , including in combination : a plurality of adaptive amplifiers arranged as an array including a plurality of columns and at least one row , each of said adaptive amplifiers having a gain of magnitude much larger than 1 and including : an output node (reset circuit) , a sense node , an inverting input node , said input node being a floating node forming the gate of at least one MOS transistor , a first capacitor for coupling an input to said adaptive amplifier to said floating node , said first capacitor having a first electrode connected to said input to said adaptive amplifier and a second electrode connected to said floating node , a second capacitor connected from said output node to said floating node , said second capacitor having a first electrode connected to said output node and a second electrode connected to said floating node , said opaque layer having an aperture therein above said second capacitor for allowing ultraviolet light to fall onto both electrodes of said second capacitor ; a voltage input line associated with each of said rows in said array , said voltage input line electrically connected to the first electrode of the first capacitor of each of said adaptive amplifiers associated with that particular row , a current output line associated with each of said columns in said array , said current output line electrically connected to the sense nodes of each of said adaptive amplifiers associated with that particular column .
US6854067B1 CLAIM 20 . In a microcontroller having a power on reset circuit (output node) interconnected with a processor a method of dynamically controlling said power state , said method comprising : a) ascertaining a power state powered by a switched mode pump power supply , said switched mode pump power supply interconnected with and responsive to control by said power on reset circuit ; b) programmatically determining desired changes to said power state ; c) intercommunicating between said processor and said power on reset circuit ; d) adjusting said power on reset circuit corresponding to said desired changes to said power state ; e) controlling said switched mode pump power supply according to said d) ; and f) repeating said a) through e) .	US5083044A CLAIM 1 . An electronic circuit fabricated as a part of an integrated circuit , said integrated circuit having a portion containing active circuits , said portion covered by an opaque layer , including in combination : a plurality of adaptive amplifiers arranged as an array including a plurality of columns and at least one row , each of said adaptive amplifiers having a gain of magnitude much larger than 1 and including : an output node (reset circuit) , a sense node , an inverting input node , said input node being a floating node forming the gate of at least one MOS transistor , a first capacitor for coupling an input to said adaptive amplifier to said floating node , said first capacitor having a first electrode connected to said input to said adaptive amplifier and a second electrode connected to said floating node , a second capacitor connected from said output node to said floating node , said second capacitor having a first electrode connected to said output node and a second electrode connected to said floating node , said opaque layer having an aperture therein above said second capacitor for allowing ultraviolet light to fall onto both electrodes of said second capacitor ; a voltage input line associated with each of said rows in said array , said voltage input line electrically connected to the first electrode of the first capacitor of each of said adaptive amplifiers associated with that particular row , a current output line associated with each of said columns in said array , said current output line electrically connected to the sense nodes of each of said adaptive amplifiers associated with that particular column .

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	US5155836A Filed: 1989-03-17 Issued: 1992-10-13 Block diagram system and method for controlling electronic instruments with simulated graphic display (Original Assignee) Jordan Dale A; Fitzsimmons Lynne A; Greenseth William A; Hoffman Gregory L; Stubbs David D Dale A. Jordan, Lynne A. Fitzsimmons, William A. Greenseth, Gregory L. Hoffman, David D. Stubbs
US6854067B1 CLAIM 6 . The method as recited in claim 5 , wherein said c) further comprises : c1) generating a precision reference voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages (signal data) , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US5155836A CLAIM 7 . A system according to claim 1 wherein the processing means is responsive to input data for producing graphic data representing a second selected block of the program , and flow of signal data (aspect voltages) between the block functions .
US6854067B1 CLAIM 11 . The method as recited in claim 10 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state corresponding to said status ; f3) programmatically calculating an optimal value (predetermined ranges) for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	US5155836A CLAIM 5 . A system according to claim 1 wherein the operation of a function associated with a selected block is specified by at least two associated parameters having corresponding predetermined ranges (optimal value) of values , specifying , in combination , an operating region of the associated function ; the processing means further produces graphic data representing an operating region of the associated function ; and the display means further displays a representation of the operating region of the associated function .
US6854067B1 CLAIM 12 . The method as recited in claim 11 , wherein said f4) further comprises : communicating each said optimal value (predetermined ranges) to said power supply scaler via said bus ; registering each said optimal value with said matrix of multiplexers and registers ; commanding said matrix of multiplexers and registers to change said independent multiple of said common supply voltage to correspond with said optimal value ; and monitoring said matrix of multiplexers and registers .	US5155836A CLAIM 5 . A system according to claim 1 wherein the operation of a function associated with a selected block is specified by at least two associated parameters having corresponding predetermined ranges (optimal value) of values , specifying , in combination , an operating region of the associated function ; the processing means further produces graphic data representing an operating region of the associated function ; and the display means further displays a representation of the operating region of the associated function .
US6854067B1 CLAIM 16 . The system as recited in claim 15 , wherein said c) further comprises : c1) generating a precision reference voltage , said precision reference voltage independent of said common supply voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages (signal data) , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US5155836A CLAIM 7 . A system according to claim 1 wherein the processing means is responsive to input data for producing graphic data representing a second selected block of the program , and flow of signal data (aspect voltages) between the block functions .
US6854067B1 CLAIM 18 . The system as recited in claim 17 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state corresponding to said status ; f3) programmatically calculating an optimal value (predetermined ranges) for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	US5155836A CLAIM 5 . A system according to claim 1 wherein the operation of a function associated with a selected block is specified by at least two associated parameters having corresponding predetermined ranges (optimal value) of values , specifying , in combination , an operating region of the associated function ; the processing means further produces graphic data representing an operating region of the associated function ; and the display means further displays a representation of the operating region of the associated function .
US6854067B1 CLAIM 19 . The method as recited in claim 18 , wherein said f4) further comprises : communicating each said optimal value (predetermined ranges) to said power supply scaler via said bus ; registering each said optimal value with said matrix of multiplexers and registers ; commanding said matrix of multiplexers and registers to change said independent multiple of said common supply voltage to correspond with said optimal value ; and monitoring said matrix of multiplexers and registers .	US5155836A CLAIM 5 . A system according to claim 1 wherein the operation of a function associated with a selected block is specified by at least two associated parameters having corresponding predetermined ranges (optimal value) of values , specifying , in combination , an operating region of the associated function ; the processing means further produces graphic data representing an operating region of the associated function ; and the display means further displays a representation of the operating region of the associated function .

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	US5168463A Filed: 1989-02-23 Issued: 1992-12-01 Shift register apparatus for storing data therein (Original Assignee) Nissan Motor Co Ltd (Current Assignee) Nissan Motor Co Ltd Hiroshi Ikeda, Norio Fujiki, Masaki Hirota
US6854067B1 CLAIM 1 . In a microcontroller with an embedded processor , a switched mode pump power supply and power on reset circuit , a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply , wherein said processor and said power on reset circuit are interconnectedly coupled , and wherein said switched mode pump power supply is interconnectedly coupled with said power on reset circuit and responsive to signals therefrom ; b) sensing a power state condition of said power state ; c) determining a suitability status (vehicle state) of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor ; e) controlling certain functions of said microcontroller accordingly .	US5168463A CLAIM 28 . An apparatus for storing data related to a state of a vehicle , comprising : a) first means for deriving a clock pulse signal having a predetermined period ; b) second means for controlling a plurality of data signals indicative of the vehicle state (suitability status) , each data signal having a plurality of serial data bits , the data bits being sequentially supplied to the data storing apparatus in synchronization with the clock pulse signal ; c) third means having plural data memory portions for storing respective bits of data of the data signal , the third means responding to the first and second means so that the respective bits of data are shifted in the data memory portions toward subsequent data memory portions of the third means in synchronization with the clock pulse signal ; and d) fourth means for protectively holding the data stored in the third means while an emergency occurs .
US6854067B1 CLAIM 11 . The method as recited in claim 10 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state (one end) corresponding to said status ; f3) programmatically calculating an optimal value for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	US5168463A CLAIM 15 . An apparatus as set forth in claim 14 , wherein the sixth means comprises an output buffer connected to one end (optimal power state) of the string of the shift registers .
US6854067B1 CLAIM 13 . In a microcontroller , a system comprising : a bus ; a processor coupled to said bus ; a power on reset circuit , said processor and said power on reset circuit coupled to said bus and interconnectedly coupled with said processor via said bus ; and a switched mode pump power supply interconnectedly coupled with said power on reset circuit and responsive to signals therefrom wherein said system executes a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply ; b) sensing a power state condition of said power state ; c) determining a suitability status (vehicle state) of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor via said bus ; e) controlling certain functions of said microcontroller according to said suitability status ; and f) dynamically programming said power on reset circuit via said bus .	US5168463A CLAIM 28 . An apparatus for storing data related to a state of a vehicle , comprising : a) first means for deriving a clock pulse signal having a predetermined period ; b) second means for controlling a plurality of data signals indicative of the vehicle state (suitability status) , each data signal having a plurality of serial data bits , the data bits being sequentially supplied to the data storing apparatus in synchronization with the clock pulse signal ; c) third means having plural data memory portions for storing respective bits of data of the data signal , the third means responding to the first and second means so that the respective bits of data are shifted in the data memory portions toward subsequent data memory portions of the third means in synchronization with the clock pulse signal ; and d) fourth means for protectively holding the data stored in the third means while an emergency occurs .
US6854067B1 CLAIM 18 . The system as recited in claim 17 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state (one end) corresponding to said status ; f3) programmatically calculating an optimal value for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	US5168463A CLAIM 15 . An apparatus as set forth in claim 14 , wherein the sixth means comprises an output buffer connected to one end (optimal power state) of the string of the shift registers .

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	US4964074A Filed: 1989-02-02 Issued: 1990-10-16 In-circuit emulator (Original Assignee) Ando Electric Co Ltd (Current Assignee) Ando Electric Co Ltd Noriyuki Suzuki, Hironobu Asai
US6854067B1 CLAIM 1 . In a microcontroller with an embedded processor , a switched mode pump power supply and power on reset circuit , a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state (circuit portion) to said microcontroller from said switched mode pump power supply , wherein said processor and said power on reset circuit are interconnectedly coupled , and wherein said switched mode pump power supply is interconnectedly coupled with said power on reset circuit and responsive to signals therefrom ; b) sensing a power state condition of said power state ; c) determining a suitability status (second logic value) of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor ; e) controlling certain functions of said microcontroller accordingly .	US4964074A CLAIM 1 . An in-circuit emulator comprising : (a) a selected CPU which is one of a plurality of CPUs (microprocessors) of different types , portions of constituent elements thereof being different from each other and producing a feature signal which includes a control signal output by each said CPU as an inherent part of normal operation thereof and which is different for each said CPU ; (b) a control circuit which controls emulation of said selected CPU , which is connected to said selected CPU and to an external actual apparatus having a circuit portion (power state) which is controlled by said feature signal , and which has a plurality of different emulation modes which each correspond to a respective said CPU ; and (c) identifier circuit means connected to said selected CPU and to said control circuit for identifying said selected CPU based upon said feature signal therefrom and for then producing an output signal which corresponds to said selected CPU , said control circuit having means for automatically switching it to a respective said emulation mode corresponding to said selected CPU in response to said output from said identifier circuit means . US4964074A CLAIM 3 . An in-circuit emulator according to claim 2 , wherein there are two different types of said CPUs , wherein said feature signal always has a first logic value when produced by a first said type of CPU and assumes a second logic value (suitability status) when produced by a second said type of CPU , and wherein said flip-flop circuit has a set input coupled to said feature signal and a reset input coupled to a system reset signal .
US6854067B1 CLAIM 5 . The method as recited in claim 4 , wherein said b) further comprises sensing a common supply voltage , wherein said common supply voltage is the voltage of said power state (circuit portion) .	US4964074A CLAIM 1 . An in-circuit emulator comprising : (a) a selected CPU which is one of a plurality of CPUs (microprocessors) of different types , portions of constituent elements thereof being different from each other and producing a feature signal which includes a control signal output by each said CPU as an inherent part of normal operation thereof and which is different for each said CPU ; (b) a control circuit which controls emulation of said selected CPU , which is connected to said selected CPU and to an external actual apparatus having a circuit portion (power state) which is controlled by said feature signal , and which has a plurality of different emulation modes which each correspond to a respective said CPU ; and (c) identifier circuit means connected to said selected CPU and to said control circuit for identifying said selected CPU based upon said feature signal therefrom and for then producing an output signal which corresponds to said selected CPU , said control circuit having means for automatically switching it to a respective said emulation mode corresponding to said selected CPU in response to said output from said identifier circuit means .
US6854067B1 CLAIM 6 . The method as recited in claim 5 , wherein said c) further comprises : c1) generating a precision reference voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state (circuit portion) condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US4964074A CLAIM 1 . An in-circuit emulator comprising : (a) a selected CPU which is one of a plurality of CPUs (microprocessors) of different types , portions of constituent elements thereof being different from each other and producing a feature signal which includes a control signal output by each said CPU as an inherent part of normal operation thereof and which is different for each said CPU ; (b) a control circuit which controls emulation of said selected CPU , which is connected to said selected CPU and to an external actual apparatus having a circuit portion (power state) which is controlled by said feature signal , and which has a plurality of different emulation modes which each correspond to a respective said CPU ; and (c) identifier circuit means connected to said selected CPU and to said control circuit for identifying said selected CPU based upon said feature signal therefrom and for then producing an output signal which corresponds to said selected CPU , said control circuit having means for automatically switching it to a respective said emulation mode corresponding to said selected CPU in response to said output from said identifier circuit means .
US6854067B1 CLAIM 11 . The method as recited in claim 10 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state (circuit portion) corresponding to said status ; f3) programmatically calculating an optimal value (first log) for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	US4964074A CLAIM 1 . An in-circuit emulator comprising : (a) a selected CPU which is one of a plurality of CPUs (microprocessors) of different types , portions of constituent elements thereof being different from each other and producing a feature signal which includes a control signal output by each said CPU as an inherent part of normal operation thereof and which is different for each said CPU ; (b) a control circuit which controls emulation of said selected CPU , which is connected to said selected CPU and to an external actual apparatus having a circuit portion (power state) which is controlled by said feature signal , and which has a plurality of different emulation modes which each correspond to a respective said CPU ; and (c) identifier circuit means connected to said selected CPU and to said control circuit for identifying said selected CPU based upon said feature signal therefrom and for then producing an output signal which corresponds to said selected CPU , said control circuit having means for automatically switching it to a respective said emulation mode corresponding to said selected CPU in response to said output from said identifier circuit means . US4964074A CLAIM 3 . An in-circuit emulator according to claim 2 , wherein there are two different types of said CPUs , wherein said feature signal always has a first log (optimal value) ic value when produced by a first said type of CPU and assumes a second logic value when produced by a second said type of CPU , and wherein said flip-flop circuit has a set input coupled to said feature signal and a reset input coupled to a system reset signal .
US6854067B1 CLAIM 12 . The method as recited in claim 11 , wherein said f4) further comprises : communicating each said optimal value (first log) to said power supply scaler via said bus ; registering each said optimal value with said matrix of multiplexers and registers ; commanding said matrix of multiplexers and registers to change said independent multiple of said common supply voltage to correspond with said optimal value ; and monitoring said matrix of multiplexers and registers .	US4964074A CLAIM 3 . An in-circuit emulator according to claim 2 , wherein there are two different types of said CPUs , wherein said feature signal always has a first log (optimal value) ic value when produced by a first said type of CPU and assumes a second logic value when produced by a second said type of CPU , and wherein said flip-flop circuit has a set input coupled to said feature signal and a reset input coupled to a system reset signal .
US6854067B1 CLAIM 13 . In a microcontroller , a system comprising : a bus ; a processor coupled to said bus ; a power on reset circuit , said processor and said power on reset circuit coupled to said bus and interconnectedly coupled with said processor via said bus ; and a switched mode pump power supply interconnectedly coupled with said power on reset circuit and responsive to signals therefrom wherein said system executes a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state (circuit portion) to said microcontroller from said switched mode pump power supply ; b) sensing a power state condition of said power state ; c) determining a suitability status (second logic value) of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor via said bus ; e) controlling certain functions of said microcontroller according to said suitability status ; and f) dynamically programming said power on reset circuit via said bus .	US4964074A CLAIM 1 . An in-circuit emulator comprising : (a) a selected CPU which is one of a plurality of CPUs (microprocessors) of different types , portions of constituent elements thereof being different from each other and producing a feature signal which includes a control signal output by each said CPU as an inherent part of normal operation thereof and which is different for each said CPU ; (b) a control circuit which controls emulation of said selected CPU , which is connected to said selected CPU and to an external actual apparatus having a circuit portion (power state) which is controlled by said feature signal , and which has a plurality of different emulation modes which each correspond to a respective said CPU ; and (c) identifier circuit means connected to said selected CPU and to said control circuit for identifying said selected CPU based upon said feature signal therefrom and for then producing an output signal which corresponds to said selected CPU , said control circuit having means for automatically switching it to a respective said emulation mode corresponding to said selected CPU in response to said output from said identifier circuit means . US4964074A CLAIM 3 . An in-circuit emulator according to claim 2 , wherein there are two different types of said CPUs , wherein said feature signal always has a first logic value when produced by a first said type of CPU and assumes a second logic value (suitability status) when produced by a second said type of CPU , and wherein said flip-flop circuit has a set input coupled to said feature signal and a reset input coupled to a system reset signal .
US6854067B1 CLAIM 15 . The system as recited in claim 14 , wherein said b) of said method further comprises sensing a common supply voltage , wherein said common supply voltage is the voltage of said power state (circuit portion) .	US4964074A CLAIM 1 . An in-circuit emulator comprising : (a) a selected CPU which is one of a plurality of CPUs (microprocessors) of different types , portions of constituent elements thereof being different from each other and producing a feature signal which includes a control signal output by each said CPU as an inherent part of normal operation thereof and which is different for each said CPU ; (b) a control circuit which controls emulation of said selected CPU , which is connected to said selected CPU and to an external actual apparatus having a circuit portion (power state) which is controlled by said feature signal , and which has a plurality of different emulation modes which each correspond to a respective said CPU ; and (c) identifier circuit means connected to said selected CPU and to said control circuit for identifying said selected CPU based upon said feature signal therefrom and for then producing an output signal which corresponds to said selected CPU , said control circuit having means for automatically switching it to a respective said emulation mode corresponding to said selected CPU in response to said output from said identifier circuit means .
US6854067B1 CLAIM 16 . The system as recited in claim 15 , wherein said c) further comprises : c1) generating a precision reference voltage , said precision reference voltage independent of said common supply voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state (circuit portion) condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US4964074A CLAIM 1 . An in-circuit emulator comprising : (a) a selected CPU which is one of a plurality of CPUs (microprocessors) of different types , portions of constituent elements thereof being different from each other and producing a feature signal which includes a control signal output by each said CPU as an inherent part of normal operation thereof and which is different for each said CPU ; (b) a control circuit which controls emulation of said selected CPU , which is connected to said selected CPU and to an external actual apparatus having a circuit portion (power state) which is controlled by said feature signal , and which has a plurality of different emulation modes which each correspond to a respective said CPU ; and (c) identifier circuit means connected to said selected CPU and to said control circuit for identifying said selected CPU based upon said feature signal therefrom and for then producing an output signal which corresponds to said selected CPU , said control circuit having means for automatically switching it to a respective said emulation mode corresponding to said selected CPU in response to said output from said identifier circuit means .
US6854067B1 CLAIM 18 . The system as recited in claim 17 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state (circuit portion) corresponding to said status ; f3) programmatically calculating an optimal value (first log) for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	US4964074A CLAIM 1 . An in-circuit emulator comprising : (a) a selected CPU which is one of a plurality of CPUs (microprocessors) of different types , portions of constituent elements thereof being different from each other and producing a feature signal which includes a control signal output by each said CPU as an inherent part of normal operation thereof and which is different for each said CPU ; (b) a control circuit which controls emulation of said selected CPU , which is connected to said selected CPU and to an external actual apparatus having a circuit portion (power state) which is controlled by said feature signal , and which has a plurality of different emulation modes which each correspond to a respective said CPU ; and (c) identifier circuit means connected to said selected CPU and to said control circuit for identifying said selected CPU based upon said feature signal therefrom and for then producing an output signal which corresponds to said selected CPU , said control circuit having means for automatically switching it to a respective said emulation mode corresponding to said selected CPU in response to said output from said identifier circuit means . US4964074A CLAIM 3 . An in-circuit emulator according to claim 2 , wherein there are two different types of said CPUs , wherein said feature signal always has a first log (optimal value) ic value when produced by a first said type of CPU and assumes a second logic value when produced by a second said type of CPU , and wherein said flip-flop circuit has a set input coupled to said feature signal and a reset input coupled to a system reset signal .
US6854067B1 CLAIM 19 . The method as recited in claim 18 , wherein said f4) further comprises : communicating each said optimal value (first log) to said power supply scaler via said bus ; registering each said optimal value with said matrix of multiplexers and registers ; commanding said matrix of multiplexers and registers to change said independent multiple of said common supply voltage to correspond with said optimal value ; and monitoring said matrix of multiplexers and registers .	US4964074A CLAIM 3 . An in-circuit emulator according to claim 2 , wherein there are two different types of said CPUs , wherein said feature signal always has a first log (optimal value) ic value when produced by a first said type of CPU and assumes a second logic value when produced by a second said type of CPU , and wherein said flip-flop circuit has a set input coupled to said feature signal and a reset input coupled to a system reset signal .
US6854067B1 CLAIM 20 . In a microcontroller having a power on reset circuit interconnected with a processor a method of dynamically controlling said power state (circuit portion) , said method comprising : a) ascertaining a power state powered by a switched mode pump power supply , said switched mode pump power supply interconnected with and responsive to control by said power on reset circuit ; b) programmatically determining desired changes to said power state ; c) intercommunicating between said processor and said power on reset circuit ; d) adjusting said power on reset circuit corresponding to said desired changes to said power state ; e) controlling said switched mode pump power supply according to said d) ; and f) repeating said a) through e) .	US4964074A CLAIM 1 . An in-circuit emulator comprising : (a) a selected CPU which is one of a plurality of CPUs (microprocessors) of different types , portions of constituent elements thereof being different from each other and producing a feature signal which includes a control signal output by each said CPU as an inherent part of normal operation thereof and which is different for each said CPU ; (b) a control circuit which controls emulation of said selected CPU , which is connected to said selected CPU and to an external actual apparatus having a circuit portion (power state) which is controlled by said feature signal , and which has a plurality of different emulation modes which each correspond to a respective said CPU ; and (c) identifier circuit means connected to said selected CPU and to said control circuit for identifying said selected CPU based upon said feature signal therefrom and for then producing an output signal which corresponds to said selected CPU , said control circuit having means for automatically switching it to a respective said emulation mode corresponding to said selected CPU in response to said output from said identifier circuit means .

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	US4876466A Filed: 1988-11-10 Issued: 1989-10-24 Programmable logic array having a changeable logic structure (Original Assignee) Mitsubishi Electric Corp (Current Assignee) Mitsubishi Electric Corp Harufusa Kondou, Hiroshi Kuranaga
US6854067B1 CLAIM 6 . The method as recited in claim 5 , wherein said c) further comprises : c1) generating a precision reference voltage (said switch) ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US4876466A CLAIM 1 . A programmable logic array (PLA) comprising : a plurality of input signal lines each including a first input line for directly transmitting an input signal and a second input line for transmitting an inverted input signal ; a plurality of output signal lines crossing said input signal lines ; a plurality of programmable logic array cells at intersections of said plurality of input signal lines and said plurality of output signal lines , said programmable logic array cells forming an AND plane , each of said cells being programmable and commonly provided to a pair of said first input signal lines and said second input signal lines ; and addressing means for selecting particular ones of said programmable logic array cells , wherein each said programmable logic array cell comprises (a) a random access memory for storing external data when selected by said addressing means , said memory being rewritable during operation of said PLA while carrying out a predetermined logic function for changing said function , (b) switching means which are opened or closed , selectively , by outputs of said memory means , and (c) PLA programming devices controlled by said switch (precision reference voltage) ing means and connected to corresponding ones of said input signal lines and said output signal lines ; wherein said PLA is alterably programmable by data stored in said memory means .
US6854067B1 CLAIM 7 . The method as recited in claim 6 , wherein said precision reference voltage (said switch) is independent of said common supply voltage .	US4876466A CLAIM 1 . A programmable logic array (PLA) comprising : a plurality of input signal lines each including a first input line for directly transmitting an input signal and a second input line for transmitting an inverted input signal ; a plurality of output signal lines crossing said input signal lines ; a plurality of programmable logic array cells at intersections of said plurality of input signal lines and said plurality of output signal lines , said programmable logic array cells forming an AND plane , each of said cells being programmable and commonly provided to a pair of said first input signal lines and said second input signal lines ; and addressing means for selecting particular ones of said programmable logic array cells , wherein each said programmable logic array cell comprises (a) a random access memory for storing external data when selected by said addressing means , said memory being rewritable during operation of said PLA while carrying out a predetermined logic function for changing said function , (b) switching means which are opened or closed , selectively , by outputs of said memory means , and (c) PLA programming devices controlled by said switch (precision reference voltage) ing means and connected to corresponding ones of said input signal lines and said output signal lines ; wherein said PLA is alterably programmable by data stored in said memory means .
US6854067B1 CLAIM 11 . The method as recited in claim 10 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state (d log) corresponding to said status ; f3) programmatically calculating an optimal value for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	US4876466A CLAIM 1 . A programmable logic array (PLA) comprising : a plurality of input signal lines each including a first input line for directly transmitting an input signal and a second input line for transmitting an inverted input signal ; a plurality of output signal lines crossing said input signal lines ; a plurality of programmable logic array cells at intersections of said plurality of input signal lines and said plurality of output signal lines , said programmable logic array cells forming an AND plane , each of said cells being programmable and commonly provided to a pair of said first input signal lines and said second input signal lines ; and addressing means for selecting particular ones of said programmable logic array cells , wherein each said programmable logic array cell comprises (a) a random access memory for storing external data when selected by said addressing means , said memory being rewritable during operation of said PLA while carrying out a predetermined log (optimal power state) ic function for changing said function , (b) switching means which are opened or closed , selectively , by outputs of said memory means , and (c) PLA programming devices controlled by said switching means and connected to corresponding ones of said input signal lines and said output signal lines ; wherein said PLA is alterably programmable by data stored in said memory means .
US6854067B1 CLAIM 16 . The system as recited in claim 15 , wherein said c) further comprises : c1) generating a precision reference voltage (said switch) , said precision reference voltage independent of said common supply voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US4876466A CLAIM 1 . A programmable logic array (PLA) comprising : a plurality of input signal lines each including a first input line for directly transmitting an input signal and a second input line for transmitting an inverted input signal ; a plurality of output signal lines crossing said input signal lines ; a plurality of programmable logic array cells at intersections of said plurality of input signal lines and said plurality of output signal lines , said programmable logic array cells forming an AND plane , each of said cells being programmable and commonly provided to a pair of said first input signal lines and said second input signal lines ; and addressing means for selecting particular ones of said programmable logic array cells , wherein each said programmable logic array cell comprises (a) a random access memory for storing external data when selected by said addressing means , said memory being rewritable during operation of said PLA while carrying out a predetermined logic function for changing said function , (b) switching means which are opened or closed , selectively , by outputs of said memory means , and (c) PLA programming devices controlled by said switch (precision reference voltage) ing means and connected to corresponding ones of said input signal lines and said output signal lines ; wherein said PLA is alterably programmable by data stored in said memory means .
US6854067B1 CLAIM 18 . The system as recited in claim 17 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state (d log) corresponding to said status ; f3) programmatically calculating an optimal value for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	US4876466A CLAIM 1 . A programmable logic array (PLA) comprising : a plurality of input signal lines each including a first input line for directly transmitting an input signal and a second input line for transmitting an inverted input signal ; a plurality of output signal lines crossing said input signal lines ; a plurality of programmable logic array cells at intersections of said plurality of input signal lines and said plurality of output signal lines , said programmable logic array cells forming an AND plane , each of said cells being programmable and commonly provided to a pair of said first input signal lines and said second input signal lines ; and addressing means for selecting particular ones of said programmable logic array cells , wherein each said programmable logic array cell comprises (a) a random access memory for storing external data when selected by said addressing means , said memory being rewritable during operation of said PLA while carrying out a predetermined log (optimal power state) ic function for changing said function , (b) switching means which are opened or closed , selectively , by outputs of said memory means , and (c) PLA programming devices controlled by said switching means and connected to corresponding ones of said input signal lines and said output signal lines ; wherein said PLA is alterably programmable by data stored in said memory means .

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	US4868525A Filed: 1988-09-23 Issued: 1989-09-19 Temperature-stabilized oscillator (Original Assignee) Dallas Semiconductor Corp (Current Assignee) Maxim Integrated Products Inc Donald R. Dias
US6854067B1 CLAIM 1 . In a microcontroller with an embedded processor , a switched mode pump power supply and power on reset circuit (respective output) , a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply , wherein said processor and said power on reset circuit are interconnectedly coupled , and wherein said switched mode pump power supply is interconnectedly coupled with said power on reset circuit and responsive to signals therefrom ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor ; e) controlling certain functions of said microcontroller accordingly .	US4868525A CLAIM 1 . A voltage- and temperature-insensitive oscillator , comprising : first and second time-delay circuits , each comprising a trip point detector , having an input and having an output which changes state whenever said input is charged to a substantially predetermined trip point voltage , a charging circuit which , when activated , charges said input of said trip point detector , and which includes a first resistance having a first temperature coefficient of resistance , a second resistance which has a second temperature coefficient of resistance different from said first temperature coefficient of resistance , and which is connected to discharge said input of said trip point detector , a capacitance connected to said input of said trip point detector , and a discharging circuit which , when activated , discharges the voltage on said input of said trip point detector , wherein said discharging circuit , when activated , discharges said input from said trip point to a first level more rapidly than said charging circuit , when activated , charges said input from said first level to said trip point ; and wherein , when said charging circuit is activated , said capacitance receives one part of the current flowing through said first resistance , and another part of the current flowing through said first resistance flows through said second resistance but is not received by said capacitance ; wherein , whenever said trip-point detector of either of said time-delay circuits is activated , said respective discharging circuit thereof is activated , and said charging circuit of the other of said time-delay circuits is also activated ; and further comprising an output circuit which combines the respective output (reset circuit) s of said first and second time-delay circuits .
US6854067B1 CLAIM 2 . The method as recited in claim 1 , further comprising : f) dynamically programming said power on reset circuit (respective output) .	US4868525A CLAIM 1 . A voltage- and temperature-insensitive oscillator , comprising : first and second time-delay circuits , each comprising a trip point detector , having an input and having an output which changes state whenever said input is charged to a substantially predetermined trip point voltage , a charging circuit which , when activated , charges said input of said trip point detector , and which includes a first resistance having a first temperature coefficient of resistance , a second resistance which has a second temperature coefficient of resistance different from said first temperature coefficient of resistance , and which is connected to discharge said input of said trip point detector , a capacitance connected to said input of said trip point detector , and a discharging circuit which , when activated , discharges the voltage on said input of said trip point detector , wherein said discharging circuit , when activated , discharges said input from said trip point to a first level more rapidly than said charging circuit , when activated , charges said input from said first level to said trip point ; and wherein , when said charging circuit is activated , said capacitance receives one part of the current flowing through said first resistance , and another part of the current flowing through said first resistance flows through said second resistance but is not received by said capacitance ; wherein , whenever said trip-point detector of either of said time-delay circuits is activated , said respective discharging circuit thereof is activated , and said charging circuit of the other of said time-delay circuits is also activated ; and further comprising an output circuit which combines the respective output (reset circuit) s of said first and second time-delay circuits .
US6854067B1 CLAIM 3 . The method as recited in claim 2 , wherein said power on reset circuit (respective output) and said processor are interconnected via a bus .	US4868525A CLAIM 1 . A voltage- and temperature-insensitive oscillator , comprising : first and second time-delay circuits , each comprising a trip point detector , having an input and having an output which changes state whenever said input is charged to a substantially predetermined trip point voltage , a charging circuit which , when activated , charges said input of said trip point detector , and which includes a first resistance having a first temperature coefficient of resistance , a second resistance which has a second temperature coefficient of resistance different from said first temperature coefficient of resistance , and which is connected to discharge said input of said trip point detector , a capacitance connected to said input of said trip point detector , and a discharging circuit which , when activated , discharges the voltage on said input of said trip point detector , wherein said discharging circuit , when activated , discharges said input from said trip point to a first level more rapidly than said charging circuit , when activated , charges said input from said first level to said trip point ; and wherein , when said charging circuit is activated , said capacitance receives one part of the current flowing through said first resistance , and another part of the current flowing through said first resistance flows through said second resistance but is not received by said capacitance ; wherein , whenever said trip-point detector of either of said time-delay circuits is activated , said respective discharging circuit thereof is activated , and said charging circuit of the other of said time-delay circuits is also activated ; and further comprising an output circuit which combines the respective output (reset circuit) s of said first and second time-delay circuits .
US6854067B1 CLAIM 4 . The method as recited in claim 3 , wherein said b) and said c) are accomplished by said power on reset circuit (respective output) .	US4868525A CLAIM 1 . A voltage- and temperature-insensitive oscillator , comprising : first and second time-delay circuits , each comprising a trip point detector , having an input and having an output which changes state whenever said input is charged to a substantially predetermined trip point voltage , a charging circuit which , when activated , charges said input of said trip point detector , and which includes a first resistance having a first temperature coefficient of resistance , a second resistance which has a second temperature coefficient of resistance different from said first temperature coefficient of resistance , and which is connected to discharge said input of said trip point detector , a capacitance connected to said input of said trip point detector , and a discharging circuit which , when activated , discharges the voltage on said input of said trip point detector , wherein said discharging circuit , when activated , discharges said input from said trip point to a first level more rapidly than said charging circuit , when activated , charges said input from said first level to said trip point ; and wherein , when said charging circuit is activated , said capacitance receives one part of the current flowing through said first resistance , and another part of the current flowing through said first resistance flows through said second resistance but is not received by said capacitance ; wherein , whenever said trip-point detector of either of said time-delay circuits is activated , said respective discharging circuit thereof is activated , and said charging circuit of the other of said time-delay circuits is also activated ; and further comprising an output circuit which combines the respective output (reset circuit) s of said first and second time-delay circuits .
US6854067B1 CLAIM 9 . The method as recited in claim 8 , wherein said b2) is performed by a power supply scaler (discharging circuit) , and wherein said power supply scaler comprises : a) a divider of said common supply voltage ; b) a matrix of multiplexers and registers , and c) an interconnection to said bus .	US4868525A CLAIM 1 . A voltage- and temperature-insensitive oscillator , comprising : first and second time-delay circuits , each comprising a trip point detector , having an input and having an output which changes state whenever said input is charged to a substantially predetermined trip point voltage , a charging circuit which , when activated , charges said input of said trip point detector , and which includes a first resistance having a first temperature coefficient of resistance , a second resistance which has a second temperature coefficient of resistance different from said first temperature coefficient of resistance , and which is connected to discharge said input of said trip point detector , a capacitance connected to said input of said trip point detector , and a discharging circuit (power supply scaler) which , when activated , discharges the voltage on said input of said trip point detector , wherein said discharging circuit , when activated , discharges said input from said trip point to a first level more rapidly than said charging circuit , when activated , charges said input from said first level to said trip point ; and wherein , when said charging circuit is activated , said capacitance receives one part of the current flowing through said first resistance , and another part of the current flowing through said first resistance flows through said second resistance but is not received by said capacitance ; wherein , whenever said trip-point detector of either of said time-delay circuits is activated , said respective discharging circuit thereof is activated , and said charging circuit of the other of said time-delay circuits is also activated ; and further comprising an output circuit which combines the respective outputs of said first and second time-delay circuits .
US6854067B1 CLAIM 11 . The method as recited in claim 10 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state (d log) corresponding to said status ; f3) programmatically calculating an optimal value for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	US4868525A CLAIM 22 . The oscillator of claim 1 , wherein said output circuit comprises logic which performs a logical operation on two corresponding respective outputs of said first time-delay circuit and said second time-delay circuit , and wherein said log (optimal power state) ical operation is selected from the group consisting of AND , NAND , and XOR .
US6854067B1 CLAIM 12 . The method as recited in claim 11 , wherein said f4) further comprises : communicating each said optimal value to said power supply scaler (discharging circuit) via said bus ; registering each said optimal value with said matrix of multiplexers and registers ; commanding said matrix of multiplexers and registers to change said independent multiple of said common supply voltage to correspond with said optimal value ; and monitoring said matrix of multiplexers and registers .	US4868525A CLAIM 1 . A voltage- and temperature-insensitive oscillator , comprising : first and second time-delay circuits , each comprising a trip point detector , having an input and having an output which changes state whenever said input is charged to a substantially predetermined trip point voltage , a charging circuit which , when activated , charges said input of said trip point detector , and which includes a first resistance having a first temperature coefficient of resistance , a second resistance which has a second temperature coefficient of resistance different from said first temperature coefficient of resistance , and which is connected to discharge said input of said trip point detector , a capacitance connected to said input of said trip point detector , and a discharging circuit (power supply scaler) which , when activated , discharges the voltage on said input of said trip point detector , wherein said discharging circuit , when activated , discharges said input from said trip point to a first level more rapidly than said charging circuit , when activated , charges said input from said first level to said trip point ; and wherein , when said charging circuit is activated , said capacitance receives one part of the current flowing through said first resistance , and another part of the current flowing through said first resistance flows through said second resistance but is not received by said capacitance ; wherein , whenever said trip-point detector of either of said time-delay circuits is activated , said respective discharging circuit thereof is activated , and said charging circuit of the other of said time-delay circuits is also activated ; and further comprising an output circuit which combines the respective outputs of said first and second time-delay circuits .
US6854067B1 CLAIM 13 . In a microcontroller , a system comprising : a bus ; a processor coupled to said bus ; a power on reset circuit (respective output) , said processor and said power on reset circuit coupled to said bus and interconnectedly coupled with said processor via said bus ; and a switched mode pump power supply interconnectedly coupled with said power on reset circuit and responsive to signals therefrom wherein said system executes a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor via said bus ; e) controlling certain functions of said microcontroller according to said suitability status ; and f) dynamically programming said power on reset circuit via said bus .	US4868525A CLAIM 1 . A voltage- and temperature-insensitive oscillator , comprising : first and second time-delay circuits , each comprising a trip point detector , having an input and having an output which changes state whenever said input is charged to a substantially predetermined trip point voltage , a charging circuit which , when activated , charges said input of said trip point detector , and which includes a first resistance having a first temperature coefficient of resistance , a second resistance which has a second temperature coefficient of resistance different from said first temperature coefficient of resistance , and which is connected to discharge said input of said trip point detector , a capacitance connected to said input of said trip point detector , and a discharging circuit which , when activated , discharges the voltage on said input of said trip point detector , wherein said discharging circuit , when activated , discharges said input from said trip point to a first level more rapidly than said charging circuit , when activated , charges said input from said first level to said trip point ; and wherein , when said charging circuit is activated , said capacitance receives one part of the current flowing through said first resistance , and another part of the current flowing through said first resistance flows through said second resistance but is not received by said capacitance ; wherein , whenever said trip-point detector of either of said time-delay circuits is activated , said respective discharging circuit thereof is activated , and said charging circuit of the other of said time-delay circuits is also activated ; and further comprising an output circuit which combines the respective output (reset circuit) s of said first and second time-delay circuits .
US6854067B1 CLAIM 14 . The system as recited in claim 13 , wherein said b) and said c) of said method are accomplished by said power on reset circuit (respective output) .	US4868525A CLAIM 1 . A voltage- and temperature-insensitive oscillator , comprising : first and second time-delay circuits , each comprising a trip point detector , having an input and having an output which changes state whenever said input is charged to a substantially predetermined trip point voltage , a charging circuit which , when activated , charges said input of said trip point detector , and which includes a first resistance having a first temperature coefficient of resistance , a second resistance which has a second temperature coefficient of resistance different from said first temperature coefficient of resistance , and which is connected to discharge said input of said trip point detector , a capacitance connected to said input of said trip point detector , and a discharging circuit which , when activated , discharges the voltage on said input of said trip point detector , wherein said discharging circuit , when activated , discharges said input from said trip point to a first level more rapidly than said charging circuit , when activated , charges said input from said first level to said trip point ; and wherein , when said charging circuit is activated , said capacitance receives one part of the current flowing through said first resistance , and another part of the current flowing through said first resistance flows through said second resistance but is not received by said capacitance ; wherein , whenever said trip-point detector of either of said time-delay circuits is activated , said respective discharging circuit thereof is activated , and said charging circuit of the other of said time-delay circuits is also activated ; and further comprising an output circuit which combines the respective output (reset circuit) s of said first and second time-delay circuits .
US6854067B1 CLAIM 17 . The system as recited in claim 16 , wherein said b2) is performed by a power supply scaler (discharging circuit) , wherein said power supply scaler comprises : a) a divider of said common supply voltage ; b) a matrix of multiplexers and registers , and c) an interconnection to said bus .	US4868525A CLAIM 1 . A voltage- and temperature-insensitive oscillator , comprising : first and second time-delay circuits , each comprising a trip point detector , having an input and having an output which changes state whenever said input is charged to a substantially predetermined trip point voltage , a charging circuit which , when activated , charges said input of said trip point detector , and which includes a first resistance having a first temperature coefficient of resistance , a second resistance which has a second temperature coefficient of resistance different from said first temperature coefficient of resistance , and which is connected to discharge said input of said trip point detector , a capacitance connected to said input of said trip point detector , and a discharging circuit (power supply scaler) which , when activated , discharges the voltage on said input of said trip point detector , wherein said discharging circuit , when activated , discharges said input from said trip point to a first level more rapidly than said charging circuit , when activated , charges said input from said first level to said trip point ; and wherein , when said charging circuit is activated , said capacitance receives one part of the current flowing through said first resistance , and another part of the current flowing through said first resistance flows through said second resistance but is not received by said capacitance ; wherein , whenever said trip-point detector of either of said time-delay circuits is activated , said respective discharging circuit thereof is activated , and said charging circuit of the other of said time-delay circuits is also activated ; and further comprising an output circuit which combines the respective outputs of said first and second time-delay circuits .
US6854067B1 CLAIM 18 . The system as recited in claim 17 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state (d log) corresponding to said status ; f3) programmatically calculating an optimal value for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	US4868525A CLAIM 22 . The oscillator of claim 1 , wherein said output circuit comprises logic which performs a logical operation on two corresponding respective outputs of said first time-delay circuit and said second time-delay circuit , and wherein said log (optimal power state) ical operation is selected from the group consisting of AND , NAND , and XOR .
US6854067B1 CLAIM 19 . The method as recited in claim 18 , wherein said f4) further comprises : communicating each said optimal value to said power supply scaler (discharging circuit) via said bus ; registering each said optimal value with said matrix of multiplexers and registers ; commanding said matrix of multiplexers and registers to change said independent multiple of said common supply voltage to correspond with said optimal value ; and monitoring said matrix of multiplexers and registers .	US4868525A CLAIM 1 . A voltage- and temperature-insensitive oscillator , comprising : first and second time-delay circuits , each comprising a trip point detector , having an input and having an output which changes state whenever said input is charged to a substantially predetermined trip point voltage , a charging circuit which , when activated , charges said input of said trip point detector , and which includes a first resistance having a first temperature coefficient of resistance , a second resistance which has a second temperature coefficient of resistance different from said first temperature coefficient of resistance , and which is connected to discharge said input of said trip point detector , a capacitance connected to said input of said trip point detector , and a discharging circuit (power supply scaler) which , when activated , discharges the voltage on said input of said trip point detector , wherein said discharging circuit , when activated , discharges said input from said trip point to a first level more rapidly than said charging circuit , when activated , charges said input from said first level to said trip point ; and wherein , when said charging circuit is activated , said capacitance receives one part of the current flowing through said first resistance , and another part of the current flowing through said first resistance flows through said second resistance but is not received by said capacitance ; wherein , whenever said trip-point detector of either of said time-delay circuits is activated , said respective discharging circuit thereof is activated , and said charging circuit of the other of said time-delay circuits is also activated ; and further comprising an output circuit which combines the respective outputs of said first and second time-delay circuits .
US6854067B1 CLAIM 20 . In a microcontroller having a power on reset circuit (respective output) interconnected with a processor a method of dynamically controlling said power state , said method comprising : a) ascertaining a power state powered by a switched mode pump power supply , said switched mode pump power supply interconnected with and responsive to control by said power on reset circuit ; b) programmatically determining desired changes to said power state ; c) intercommunicating between said processor and said power on reset circuit ; d) adjusting said power on reset circuit corresponding to said desired changes to said power state ; e) controlling said switched mode pump power supply according to said d) ; and f) repeating said a) through e) .	US4868525A CLAIM 1 . A voltage- and temperature-insensitive oscillator , comprising : first and second time-delay circuits , each comprising a trip point detector , having an input and having an output which changes state whenever said input is charged to a substantially predetermined trip point voltage , a charging circuit which , when activated , charges said input of said trip point detector , and which includes a first resistance having a first temperature coefficient of resistance , a second resistance which has a second temperature coefficient of resistance different from said first temperature coefficient of resistance , and which is connected to discharge said input of said trip point detector , a capacitance connected to said input of said trip point detector , and a discharging circuit which , when activated , discharges the voltage on said input of said trip point detector , wherein said discharging circuit , when activated , discharges said input from said trip point to a first level more rapidly than said charging circuit , when activated , charges said input from said first level to said trip point ; and wherein , when said charging circuit is activated , said capacitance receives one part of the current flowing through said first resistance , and another part of the current flowing through said first resistance flows through said second resistance but is not received by said capacitance ; wherein , whenever said trip-point detector of either of said time-delay circuits is activated , said respective discharging circuit thereof is activated , and said charging circuit of the other of said time-delay circuits is also activated ; and further comprising an output circuit which combines the respective output (reset circuit) s of said first and second time-delay circuits .

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	US4833418A Filed: 1988-09-01 Issued: 1989-05-23 Compensation circuit for nullifying differential offset voltage and regulating common mode voltage of differential signals (Original Assignee) Archive Corp (Current Assignee) Certance LLC John J. Quintus, Michael S. Sheehan
US6854067B1 CLAIM 1 . In a microcontroller with an embedded processor , a switched mode pump power supply and power on reset circuit (first sum signal, pass filter) , a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply , wherein said processor and said power on reset circuit are interconnectedly coupled , and wherein said switched mode pump power supply is interconnectedly coupled with said power on reset circuit and responsive to signals therefrom ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor ; e) controlling certain functions of said microcontroller accordingly .	US4833418A CLAIM 4 . The compensation circuit , as defined in claim 1 , wherein the amplifying circuit comprises an operational amplifier with a capacitor , such that the combination is an active low-pass filter (reset circuit) . US4833418A CLAIM 5 . A method of controlling DC differential offset of a differential amplifier that provides first and second differential output signals having a differential offset voltage therebetween , said method comprising the steps of : isolating DC components from AC components of each of the first and second differential signals ; summing the AC component of the first differential signal with the DC component from the second differential signal to provide a first sum signal (reset circuit) ; summing the AC component of the second differential signal with the DC component of the first differential signal to provide a second sum signal ; providing the first and second sum signals to an operational amplifier to provide an output signal responsive to the voltage difference between said first and second sum signals ; and providing the output signal from the operational amplifier as an input signal to a DC differential offset control input of the differential amplifier to control the DC differential offset of the differential amplifier to reduce the difference between the first and second sum signals , thereby reducing the difference between the DC components of the first and second differential output signals from said differential amplifier .
US6854067B1 CLAIM 2 . The method as recited in claim 1 , further comprising : f) dynamically programming said power on reset circuit (first sum signal, pass filter) .	US4833418A CLAIM 4 . The compensation circuit , as defined in claim 1 , wherein the amplifying circuit comprises an operational amplifier with a capacitor , such that the combination is an active low-pass filter (reset circuit) . US4833418A CLAIM 5 . A method of controlling DC differential offset of a differential amplifier that provides first and second differential output signals having a differential offset voltage therebetween , said method comprising the steps of : isolating DC components from AC components of each of the first and second differential signals ; summing the AC component of the first differential signal with the DC component from the second differential signal to provide a first sum signal (reset circuit) ; summing the AC component of the second differential signal with the DC component of the first differential signal to provide a second sum signal ; providing the first and second sum signals to an operational amplifier to provide an output signal responsive to the voltage difference between said first and second sum signals ; and providing the output signal from the operational amplifier as an input signal to a DC differential offset control input of the differential amplifier to control the DC differential offset of the differential amplifier to reduce the difference between the first and second sum signals , thereby reducing the difference between the DC components of the first and second differential output signals from said differential amplifier .
US6854067B1 CLAIM 3 . The method as recited in claim 2 , wherein said power on reset circuit (first sum signal, pass filter) and said processor are interconnected via a bus .	US4833418A CLAIM 4 . The compensation circuit , as defined in claim 1 , wherein the amplifying circuit comprises an operational amplifier with a capacitor , such that the combination is an active low-pass filter (reset circuit) . US4833418A CLAIM 5 . A method of controlling DC differential offset of a differential amplifier that provides first and second differential output signals having a differential offset voltage therebetween , said method comprising the steps of : isolating DC components from AC components of each of the first and second differential signals ; summing the AC component of the first differential signal with the DC component from the second differential signal to provide a first sum signal (reset circuit) ; summing the AC component of the second differential signal with the DC component of the first differential signal to provide a second sum signal ; providing the first and second sum signals to an operational amplifier to provide an output signal responsive to the voltage difference between said first and second sum signals ; and providing the output signal from the operational amplifier as an input signal to a DC differential offset control input of the differential amplifier to control the DC differential offset of the differential amplifier to reduce the difference between the first and second sum signals , thereby reducing the difference between the DC components of the first and second differential output signals from said differential amplifier .
US6854067B1 CLAIM 4 . The method as recited in claim 3 , wherein said b) and said c) are accomplished by said power on reset circuit (first sum signal, pass filter) .	US4833418A CLAIM 4 . The compensation circuit , as defined in claim 1 , wherein the amplifying circuit comprises an operational amplifier with a capacitor , such that the combination is an active low-pass filter (reset circuit) . US4833418A CLAIM 5 . A method of controlling DC differential offset of a differential amplifier that provides first and second differential output signals having a differential offset voltage therebetween , said method comprising the steps of : isolating DC components from AC components of each of the first and second differential signals ; summing the AC component of the first differential signal with the DC component from the second differential signal to provide a first sum signal (reset circuit) ; summing the AC component of the second differential signal with the DC component of the first differential signal to provide a second sum signal ; providing the first and second sum signals to an operational amplifier to provide an output signal responsive to the voltage difference between said first and second sum signals ; and providing the output signal from the operational amplifier as an input signal to a DC differential offset control input of the differential amplifier to control the DC differential offset of the differential amplifier to reduce the difference between the first and second sum signals , thereby reducing the difference between the DC components of the first and second differential output signals from said differential amplifier .
US6854067B1 CLAIM 6 . The method as recited in claim 5 , wherein said c) further comprises : c1) generating a precision reference voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one (relative magnitude) of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US4833418A CLAIM 9 . A signal processing apparatus , comprising : a differential amplifier having first and second inputs and first and second outputs , said first output producing a first output signal and said second output producing a second output signal , each of said first and second output signals having a DC component and an AC component , said DC components having unknown magnitudes ; a compensation circuit , connected to receive said first and second output signals , that generates a feedback signal that is provided to said differential amplifier to adjust relative magnitude (comparisons comparing one) s of said DC components of said first and second output signals to be substantially equal ; a control circuit , connected to receive said first and second output signals , said control circuit comparing a signal responsive to the DC component of at least one of said first and second output signals with a reference signal and adjusting the magnitudes of said DC components to provide first and second compensated output signals , each having a DC component with a known fixed magnitude ; and a zero-crossing detector that compares said first and second compensated output signals and provides a detector output signal responsive to the relative magnitudes of said first and second compensated output signals .
US6854067B1 CLAIM 11 . The method as recited in claim 10 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state corresponding to said status ; f3) programmatically calculating an optimal value (differential input signal) for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	US4833418A CLAIM 6 . A compensation circuit that receives first and second differential input signal (optimal value) s from a differential amplifier and that provides two differential output signals having a substantially constant common mode voltage of a predetermined magnitude responsive to a predetermined reference voltage , comprising : a first circuit that is responsive to a differential offset voltage between said first and second differential input signals from said differential amplifier and that provides a feedback signal to said differential amplifier to adjust DC differential offset of said differential amplifier so that said differential offset voltage is substantially equal to zero ; a second circuit that receives a first input signal responsive to the common mode voltage of said first and second differential input signals from said differential amplifier and a second input signal that is responsive to said predetermined reference voltage , said second circuit providing an output signal responsive to the difference between said first input signal and said second input signal ; and a voltage divider network that receives said output signal from said second circuit and that receives said differential input signals from said differential amplifier , said voltage divider network providing first and second differential output signals that have said substantially constant common mode voltage of said predetermined magnitude .
US6854067B1 CLAIM 12 . The method as recited in claim 11 , wherein said f4) further comprises : communicating each said optimal value (differential input signal) to said power supply scaler via said bus ; registering each said optimal value with said matrix of multiplexers and registers ; commanding said matrix of multiplexers and registers to change said independent multiple of said common supply voltage to correspond with said optimal value ; and monitoring said matrix of multiplexers and registers .	US4833418A CLAIM 6 . A compensation circuit that receives first and second differential input signal (optimal value) s from a differential amplifier and that provides two differential output signals having a substantially constant common mode voltage of a predetermined magnitude responsive to a predetermined reference voltage , comprising : a first circuit that is responsive to a differential offset voltage between said first and second differential input signals from said differential amplifier and that provides a feedback signal to said differential amplifier to adjust DC differential offset of said differential amplifier so that said differential offset voltage is substantially equal to zero ; a second circuit that receives a first input signal responsive to the common mode voltage of said first and second differential input signals from said differential amplifier and a second input signal that is responsive to said predetermined reference voltage , said second circuit providing an output signal responsive to the difference between said first input signal and said second input signal ; and a voltage divider network that receives said output signal from said second circuit and that receives said differential input signals from said differential amplifier , said voltage divider network providing first and second differential output signals that have said substantially constant common mode voltage of said predetermined magnitude .
US6854067B1 CLAIM 13 . In a microcontroller , a system comprising : a bus ; a processor coupled to said bus ; a power on reset circuit (first sum signal, pass filter) , said processor and said power on reset circuit coupled to said bus and interconnectedly coupled with said processor via said bus ; and a switched mode pump power supply interconnectedly coupled with said power on reset circuit and responsive to signals therefrom wherein said system executes a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor via said bus ; e) controlling certain functions of said microcontroller according to said suitability status ; and f) dynamically programming said power on reset circuit via said bus .	US4833418A CLAIM 4 . The compensation circuit , as defined in claim 1 , wherein the amplifying circuit comprises an operational amplifier with a capacitor , such that the combination is an active low-pass filter (reset circuit) . US4833418A CLAIM 5 . A method of controlling DC differential offset of a differential amplifier that provides first and second differential output signals having a differential offset voltage therebetween , said method comprising the steps of : isolating DC components from AC components of each of the first and second differential signals ; summing the AC component of the first differential signal with the DC component from the second differential signal to provide a first sum signal (reset circuit) ; summing the AC component of the second differential signal with the DC component of the first differential signal to provide a second sum signal ; providing the first and second sum signals to an operational amplifier to provide an output signal responsive to the voltage difference between said first and second sum signals ; and providing the output signal from the operational amplifier as an input signal to a DC differential offset control input of the differential amplifier to control the DC differential offset of the differential amplifier to reduce the difference between the first and second sum signals , thereby reducing the difference between the DC components of the first and second differential output signals from said differential amplifier .
US6854067B1 CLAIM 14 . The system as recited in claim 13 , wherein said b) and said c) of said method are accomplished by said power on reset circuit (first sum signal, pass filter) .	US4833418A CLAIM 4 . The compensation circuit , as defined in claim 1 , wherein the amplifying circuit comprises an operational amplifier with a capacitor , such that the combination is an active low-pass filter (reset circuit) . US4833418A CLAIM 5 . A method of controlling DC differential offset of a differential amplifier that provides first and second differential output signals having a differential offset voltage therebetween , said method comprising the steps of : isolating DC components from AC components of each of the first and second differential signals ; summing the AC component of the first differential signal with the DC component from the second differential signal to provide a first sum signal (reset circuit) ; summing the AC component of the second differential signal with the DC component of the first differential signal to provide a second sum signal ; providing the first and second sum signals to an operational amplifier to provide an output signal responsive to the voltage difference between said first and second sum signals ; and providing the output signal from the operational amplifier as an input signal to a DC differential offset control input of the differential amplifier to control the DC differential offset of the differential amplifier to reduce the difference between the first and second sum signals , thereby reducing the difference between the DC components of the first and second differential output signals from said differential amplifier .
US6854067B1 CLAIM 16 . The system as recited in claim 15 , wherein said c) further comprises : c1) generating a precision reference voltage , said precision reference voltage independent of said common supply voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one (relative magnitude) of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US4833418A CLAIM 9 . A signal processing apparatus , comprising : a differential amplifier having first and second inputs and first and second outputs , said first output producing a first output signal and said second output producing a second output signal , each of said first and second output signals having a DC component and an AC component , said DC components having unknown magnitudes ; a compensation circuit , connected to receive said first and second output signals , that generates a feedback signal that is provided to said differential amplifier to adjust relative magnitude (comparisons comparing one) s of said DC components of said first and second output signals to be substantially equal ; a control circuit , connected to receive said first and second output signals , said control circuit comparing a signal responsive to the DC component of at least one of said first and second output signals with a reference signal and adjusting the magnitudes of said DC components to provide first and second compensated output signals , each having a DC component with a known fixed magnitude ; and a zero-crossing detector that compares said first and second compensated output signals and provides a detector output signal responsive to the relative magnitudes of said first and second compensated output signals .
US6854067B1 CLAIM 18 . The system as recited in claim 17 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power state corresponding to said status ; f3) programmatically calculating an optimal value (differential input signal) for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	US4833418A CLAIM 6 . A compensation circuit that receives first and second differential input signal (optimal value) s from a differential amplifier and that provides two differential output signals having a substantially constant common mode voltage of a predetermined magnitude responsive to a predetermined reference voltage , comprising : a first circuit that is responsive to a differential offset voltage between said first and second differential input signals from said differential amplifier and that provides a feedback signal to said differential amplifier to adjust DC differential offset of said differential amplifier so that said differential offset voltage is substantially equal to zero ; a second circuit that receives a first input signal responsive to the common mode voltage of said first and second differential input signals from said differential amplifier and a second input signal that is responsive to said predetermined reference voltage , said second circuit providing an output signal responsive to the difference between said first input signal and said second input signal ; and a voltage divider network that receives said output signal from said second circuit and that receives said differential input signals from said differential amplifier , said voltage divider network providing first and second differential output signals that have said substantially constant common mode voltage of said predetermined magnitude .
US6854067B1 CLAIM 19 . The method as recited in claim 18 , wherein said f4) further comprises : communicating each said optimal value (differential input signal) to said power supply scaler via said bus ; registering each said optimal value with said matrix of multiplexers and registers ; commanding said matrix of multiplexers and registers to change said independent multiple of said common supply voltage to correspond with said optimal value ; and monitoring said matrix of multiplexers and registers .	US4833418A CLAIM 6 . A compensation circuit that receives first and second differential input signal (optimal value) s from a differential amplifier and that provides two differential output signals having a substantially constant common mode voltage of a predetermined magnitude responsive to a predetermined reference voltage , comprising : a first circuit that is responsive to a differential offset voltage between said first and second differential input signals from said differential amplifier and that provides a feedback signal to said differential amplifier to adjust DC differential offset of said differential amplifier so that said differential offset voltage is substantially equal to zero ; a second circuit that receives a first input signal responsive to the common mode voltage of said first and second differential input signals from said differential amplifier and a second input signal that is responsive to said predetermined reference voltage , said second circuit providing an output signal responsive to the difference between said first input signal and said second input signal ; and a voltage divider network that receives said output signal from said second circuit and that receives said differential input signals from said differential amplifier , said voltage divider network providing first and second differential output signals that have said substantially constant common mode voltage of said predetermined magnitude .
US6854067B1 CLAIM 20 . In a microcontroller having a power on reset circuit (first sum signal, pass filter) interconnected with a processor a method of dynamically controlling said power state , said method comprising : a) ascertaining a power state powered by a switched mode pump power supply , said switched mode pump power supply interconnected with and responsive to control by said power on reset circuit ; b) programmatically determining desired changes to said power state ; c) intercommunicating between said processor and said power on reset circuit ; d) adjusting said power on reset circuit corresponding to said desired changes to said power state ; e) controlling said switched mode pump power supply according to said d) ; and f) repeating said a) through e) .	US4833418A CLAIM 4 . The compensation circuit , as defined in claim 1 , wherein the amplifying circuit comprises an operational amplifier with a capacitor , such that the combination is an active low-pass filter (reset circuit) . US4833418A CLAIM 5 . A method of controlling DC differential offset of a differential amplifier that provides first and second differential output signals having a differential offset voltage therebetween , said method comprising the steps of : isolating DC components from AC components of each of the first and second differential signals ; summing the AC component of the first differential signal with the DC component from the second differential signal to provide a first sum signal (reset circuit) ; summing the AC component of the second differential signal with the DC component of the first differential signal to provide a second sum signal ; providing the first and second sum signals to an operational amplifier to provide an output signal responsive to the voltage difference between said first and second sum signals ; and providing the output signal from the operational amplifier as an input signal to a DC differential offset control input of the differential amplifier to control the DC differential offset of the differential amplifier to reduce the difference between the first and second sum signals , thereby reducing the difference between the DC components of the first and second differential output signals from said differential amplifier .

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	US4879461A Filed: 1988-04-25 Issued: 1989-11-07 Energy field sensor using summing means (Original Assignee) Harald Philipp Harald Philipp
US6854067B1 CLAIM 1 . In a microcontroller with an embedded processor , a switched mode pump power supply and power on reset circuit , a method of dynamically controlling a plurality of power stability functions (control means) for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply , wherein said processor and said power on reset circuit are interconnectedly coupled , and wherein said switched mode pump power supply is interconnectedly coupled with said power on reset circuit and responsive to signals therefrom ; b) sensing a power state condition (received energy) of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor ; e) controlling certain functions of said microcontroller accordingly .	US4879461A CLAIM 3 . An apparatus for sensing a disturbance within a sensing region , comprising : an emitting means for emitting a field of energy ; control means (power stability functions) to adjust the amplitude of the emitted field of energy ; sensing means for receiving energy from the emitted field to produce a corresponding electrical sensing signal ; signal generation means for producing an electrical signal complementary in nature to the sensing signal ; summing means for adding the electrical sensing signal and the electrical signal complementary to the sensing signal to create a summation signal whose amplitude is less than the sensing signal or opposite in polarity to the sensing signal ; and detection means responsive to the summation signal to create a detection signal indicative of an energy field disturbance . US4879461A CLAIM 14 . A method for sensing a disturbance within a region comprising : generating a radiated field of energy that is subject to being disturbed by objects within the region ; sensing of the radiated field of energy to produce a signal related to the received energy (power state condition) from the radiated field ; generating an electrical signal complementary to the signal resulting from the sensing of the radiated field ; generating a detection signal proportional to the sum of the signal related to the received energy from the radiated field and the electrical complementary signal , the sum and detection signal having a null or minimum condition ; adjusting the amplitude of the electrical complementary signal to alter the degree of field disturbance required to achieve a null or minimum condition , the adjustment being performed digitally .
US6854067B1 CLAIM 6 . The method as recited in claim 5 , wherein said c) further comprises : c1) generating a precision reference voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition (received energy) signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US4879461A CLAIM 14 . A method for sensing a disturbance within a region comprising : generating a radiated field of energy that is subject to being disturbed by objects within the region ; sensing of the radiated field of energy to produce a signal related to the received energy (power state condition) from the radiated field ; generating an electrical signal complementary to the signal resulting from the sensing of the radiated field ; generating a detection signal proportional to the sum of the signal related to the received energy from the radiated field and the electrical complementary signal , the sum and detection signal having a null or minimum condition ; adjusting the amplitude of the electrical complementary signal to alter the degree of field disturbance required to achieve a null or minimum condition , the adjustment being performed digitally .
US6854067B1 CLAIM 13 . In a microcontroller , a system comprising : a bus ; a processor coupled to said bus ; a power on reset circuit , said processor and said power on reset circuit coupled to said bus and interconnectedly coupled with said processor via said bus ; and a switched mode pump power supply interconnectedly coupled with said power on reset circuit and responsive to signals therefrom wherein said system executes a method of dynamically controlling a plurality of power stability functions (control means) for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply ; b) sensing a power state condition (received energy) of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor via said bus ; e) controlling certain functions of said microcontroller according to said suitability status ; and f) dynamically programming said power on reset circuit via said bus .	US4879461A CLAIM 3 . An apparatus for sensing a disturbance within a sensing region , comprising : an emitting means for emitting a field of energy ; control means (power stability functions) to adjust the amplitude of the emitted field of energy ; sensing means for receiving energy from the emitted field to produce a corresponding electrical sensing signal ; signal generation means for producing an electrical signal complementary in nature to the sensing signal ; summing means for adding the electrical sensing signal and the electrical signal complementary to the sensing signal to create a summation signal whose amplitude is less than the sensing signal or opposite in polarity to the sensing signal ; and detection means responsive to the summation signal to create a detection signal indicative of an energy field disturbance . US4879461A CLAIM 14 . A method for sensing a disturbance within a region comprising : generating a radiated field of energy that is subject to being disturbed by objects within the region ; sensing of the radiated field of energy to produce a signal related to the received energy (power state condition) from the radiated field ; generating an electrical signal complementary to the signal resulting from the sensing of the radiated field ; generating a detection signal proportional to the sum of the signal related to the received energy from the radiated field and the electrical complementary signal , the sum and detection signal having a null or minimum condition ; adjusting the amplitude of the electrical complementary signal to alter the degree of field disturbance required to achieve a null or minimum condition , the adjustment being performed digitally .
US6854067B1 CLAIM 16 . The system as recited in claim 15 , wherein said c) further comprises : c1) generating a precision reference voltage , said precision reference voltage independent of said common supply voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition (received energy) signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US4879461A CLAIM 14 . A method for sensing a disturbance within a region comprising : generating a radiated field of energy that is subject to being disturbed by objects within the region ; sensing of the radiated field of energy to produce a signal related to the received energy (power state condition) from the radiated field ; generating an electrical signal complementary to the signal resulting from the sensing of the radiated field ; generating a detection signal proportional to the sum of the signal related to the received energy from the radiated field and the electrical complementary signal , the sum and detection signal having a null or minimum condition ; adjusting the amplitude of the electrical complementary signal to alter the degree of field disturbance required to achieve a null or minimum condition , the adjustment being performed digitally .

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	US4907121A Filed: 1988-04-20 Issued: 1990-03-06 Comparator with extended common-mode input voltage range (Original Assignee) SGS Thomson Microelectronics GmbH (Current Assignee) STMicroelectronics GmbH Petr Hrassky
US6854067B1 CLAIM 6 . The method as recited in claim 5 , wherein said c) further comprises : c1) generating a precision reference voltage (said switch) ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US4907121A CLAIM 6 . A comparator according to claim 5 , further including a second current mirror circuit connected to said second of said two differential input stages and wherein said current diversion circuit includes a switching transistor having its collector-to-emitter path connected in series with said common constant current source and whose base is biased by said switch (precision reference voltage) ing reference voltage source , said switching transistor having its emitter connected by means of a diode to a common base connection of a transistor of the first differential input stage , and said switching transistor having its collector connected to said second current mirror circuit , so that said common constant current source , based upon the ratio between the values of said common-mode input voltage and said switching reference voltage , feeds at least one of both of said two differential input stages by means of said second current mirror circuit .
US6854067B1 CLAIM 7 . The method as recited in claim 6 , wherein said precision reference voltage (said switch) is independent of said common supply voltage .	US4907121A CLAIM 6 . A comparator according to claim 5 , further including a second current mirror circuit connected to said second of said two differential input stages and wherein said current diversion circuit includes a switching transistor having its collector-to-emitter path connected in series with said common constant current source and whose base is biased by said switch (precision reference voltage) ing reference voltage source , said switching transistor having its emitter connected by means of a diode to a common base connection of a transistor of the first differential input stage , and said switching transistor having its collector connected to said second current mirror circuit , so that said common constant current source , based upon the ratio between the values of said common-mode input voltage and said switching reference voltage , feeds at least one of both of said two differential input stages by means of said second current mirror circuit .
US6854067B1 CLAIM 11 . The method as recited in claim 10 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power (back circuit) state corresponding to said status ; f3) programmatically calculating an optimal value for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	US4907121A CLAIM 16 . A switching current regulator for driving an inductive load , including : a comparator comprising : two comparator inputs ; two differential input stages connected in parallel , each of said two differential input stages being connected to receive a voltage from a common-mode input voltage source coupled to each of said two comparator inputs ; a common constant current source connected to each of said two differential input stages ; a supply voltage source having two poles connected to said comparator ; said constant current source being connected to feed current to at least one of both of said two differential input stages , depending upon the relationship between said common-mode input voltage and said supply voltage ; and a first current mirror circuit connected downstream of the outputs of both differential input stages and from which the output of said comparator is derived , wherein at least one of said two differential input stages operates in a common-base connection and receives its emitter supply current from said common-mode input voltage source ; said switching regulator further including : flyback circuit (optimal power) means connected in series to a controllable switch , said flyback circuit means and series connected controllable switch being connected in parallel across said two poles of said supply voltage source ; said inductive load connected in series with a current sensing means and in parallel to said flyback circuit means , said current sensing means producing a current sensing signal representative of the current flowing through said inductive load ; said controllable switch being controlled by the output of said comparator ; a reference signal source connected to said comparator for producing a reference signal such that said comparator compares said current sensing signal to said reference signal and causes said controllable switch to be activated each time said current sensing signal reaches said reference signal value ; and said reference signal source being switchable between a high reference signal value which , when reached by said current sensing signal , said comparator effects an interruption of the previously conducting controllable switch and a low reference signal value which , when reached by said current sensing signal , said comparator effects switching of said controllable switch into a conducting state from the previously interrupted state .
US6854067B1 CLAIM 16 . The system as recited in claim 15 , wherein said c) further comprises : c1) generating a precision reference voltage (said switch) , said precision reference voltage independent of said common supply voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US4907121A CLAIM 6 . A comparator according to claim 5 , further including a second current mirror circuit connected to said second of said two differential input stages and wherein said current diversion circuit includes a switching transistor having its collector-to-emitter path connected in series with said common constant current source and whose base is biased by said switch (precision reference voltage) ing reference voltage source , said switching transistor having its emitter connected by means of a diode to a common base connection of a transistor of the first differential input stage , and said switching transistor having its collector connected to said second current mirror circuit , so that said common constant current source , based upon the ratio between the values of said common-mode input voltage and said switching reference voltage , feeds at least one of both of said two differential input stages by means of said second current mirror circuit .
US6854067B1 CLAIM 18 . The system as recited in claim 17 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power (back circuit) state corresponding to said status ; f3) programmatically calculating an optimal value for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	US4907121A CLAIM 16 . A switching current regulator for driving an inductive load , including : a comparator comprising : two comparator inputs ; two differential input stages connected in parallel , each of said two differential input stages being connected to receive a voltage from a common-mode input voltage source coupled to each of said two comparator inputs ; a common constant current source connected to each of said two differential input stages ; a supply voltage source having two poles connected to said comparator ; said constant current source being connected to feed current to at least one of both of said two differential input stages , depending upon the relationship between said common-mode input voltage and said supply voltage ; and a first current mirror circuit connected downstream of the outputs of both differential input stages and from which the output of said comparator is derived , wherein at least one of said two differential input stages operates in a common-base connection and receives its emitter supply current from said common-mode input voltage source ; said switching regulator further including : flyback circuit (optimal power) means connected in series to a controllable switch , said flyback circuit means and series connected controllable switch being connected in parallel across said two poles of said supply voltage source ; said inductive load connected in series with a current sensing means and in parallel to said flyback circuit means , said current sensing means producing a current sensing signal representative of the current flowing through said inductive load ; said controllable switch being controlled by the output of said comparator ; a reference signal source connected to said comparator for producing a reference signal such that said comparator compares said current sensing signal to said reference signal and causes said controllable switch to be activated each time said current sensing signal reaches said reference signal value ; and said reference signal source being switchable between a high reference signal value which , when reached by said current sensing signal , said comparator effects an interruption of the previously conducting controllable switch and a low reference signal value which , when reached by said current sensing signal , said comparator effects switching of said controllable switch into a conducting state from the previously interrupted state .

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	US4876534A Filed: 1988-02-05 Issued: 1989-10-24 Scanning method and apparatus for current signals having large dynamic range (Original Assignee) Synaptics Inc (Current Assignee) Foveon Inc Carver A. Mead, Timothy P. Allen
US6854067B1 CLAIM 6 . The method as recited in claim 5 , wherein said c) further comprises : c1) generating a precision reference voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals (negative voltage) , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US4876534A CLAIM 1 . An apparatus for reading a current signal from a source in an array of sources , each current having a changeable sign , a small amplitude and several orders of magnitude dynamic range comprising : a first conductor ; a second conductor means for carrying a first addressing signal ; coupling means for coupling said current signal to said first conductor upon receipt of said first addressing signal ; an output node ; compression means having an input for coupling to a source of a reference voltage and coupled to said current signal only through said first conductor and coupled to said output node for converting said current signal to an output signal at said output node by a transfer function relating the voltage difference between the voltage at said output node and said reference voltage to said current signal such that said current signal increases faster than linearly in the positive direction for positive voltage differences and increases faster than linearly in the negative direction for negative voltage (power state condition signals) differences .
US6854067B1 CLAIM 11 . The method as recited in claim 10 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power (back circuit) state corresponding to said status ; f3) programmatically calculating an optimal value for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	US4876534A CLAIM 8 . The apparatus of claim 1 wherein said compression means is a differential input amplifier having an inverting input coupled to said first conductor and having a non inverting input for coupling to a reference voltage source , and having an output , and further comprising a non linear feedback circuit (optimal power) coupled from said output to said inverting input wherein said current signal from said source in said array of sources is approximately equal to the current flowing through said non linear feedback circuit and further comprising a row conductor and isolation means coupled between said output node and said row conductor for selectively coupling the signal at said output node to said row conductor wherein said isolation means includes a pair of CMOS pass transistors each having a gate terminal coupled to receive an address signal and coupled between said output node and said row conductor so as to selectively couple the signal on said output node to said row conductor regardless of polarity of said signal when said address signals are in a predetermined state .
US6854067B1 CLAIM 16 . The system as recited in claim 15 , wherein said c) further comprises : c1) generating a precision reference voltage , said precision reference voltage independent of said common supply voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals (negative voltage) , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US4876534A CLAIM 1 . An apparatus for reading a current signal from a source in an array of sources , each current having a changeable sign , a small amplitude and several orders of magnitude dynamic range comprising : a first conductor ; a second conductor means for carrying a first addressing signal ; coupling means for coupling said current signal to said first conductor upon receipt of said first addressing signal ; an output node ; compression means having an input for coupling to a source of a reference voltage and coupled to said current signal only through said first conductor and coupled to said output node for converting said current signal to an output signal at said output node by a transfer function relating the voltage difference between the voltage at said output node and said reference voltage to said current signal such that said current signal increases faster than linearly in the positive direction for positive voltage differences and increases faster than linearly in the negative direction for negative voltage (power state condition signals) differences .
US6854067B1 CLAIM 18 . The system as recited in claim 17 , wherein said f) is performed by said microprocessor , and further comprises : f1) ascertaining a status of said microcontroller ; f2) determining an optimal power (back circuit) state corresponding to said status ; f3) programmatically calculating an optimal value for each programmable said independent multiple of said common supply voltage ; f4) setting each said optimal value ; and f5) repeating said f1) through f4) .	US4876534A CLAIM 8 . The apparatus of claim 1 wherein said compression means is a differential input amplifier having an inverting input coupled to said first conductor and having a non inverting input for coupling to a reference voltage source , and having an output , and further comprising a non linear feedback circuit (optimal power) coupled from said output to said inverting input wherein said current signal from said source in said array of sources is approximately equal to the current flowing through said non linear feedback circuit and further comprising a row conductor and isolation means coupled between said output node and said row conductor for selectively coupling the signal at said output node to said row conductor wherein said isolation means includes a pair of CMOS pass transistors each having a gate terminal coupled to receive an address signal and coupled between said output node and said row conductor so as to selectively couple the signal on said output node to said row conductor regardless of polarity of said signal when said address signals are in a predetermined state .

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	EP0265209A1 Filed: 1987-10-19 Issued: 1988-04-27 Remote control system for a display apparatus (Original Assignee) Daiwa Shinku Corp (Current Assignee) Daiwa Shinku Corp Shigeru Goda
US6854067B1 CLAIM 1 . In a microcontroller with an embedded processor , a switched mode pump power supply (control system) and power on reset circuit , a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply , wherein said processor and said power on reset circuit are interconnectedly coupled , and wherein said switched mode pump power supply is interconnectedly coupled with said power on reset circuit and responsive to signals therefrom ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor ; e) controlling certain functions of said microcontroller accordingly .	EP0265209A1 CLAIM 1 . A remote control system (mode pump power supply) (1) for use in a display apparatus which comprises a display section (4) and a display data control section (2) which has a memory to store display data and outputs clock signals and a series of digital data signals , both being based on said display data stored in said memory , characterized in that said remote control system (1) comprises a relay switch (13) for switching an electric power source (8) to said display section (4) , and a timer (11 , 12) devised so as to output a switching signal to make said relay switch (13) open only when said clock signals remain stopped for a predetermined period of time .
US6854067B1 CLAIM 6 . The method as recited in claim 5 , wherein said c) further comprises : c1) generating a precision reference voltage (said switch) ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	EP0265209A1 CLAIM 2 . A remote control system (1) defined in Claim 1 , wherein said timer (11 , 12) consists of an oscillator (11) and a counter (12) having a reset terminal (R) and being devised so as to output said switch (precision reference voltage) ing signal after counting a predetermined number of pulses outputted from said oscillator (11) , said counter being supplied at said reset terminal with said clock signals .
US6854067B1 CLAIM 7 . The method as recited in claim 6 , wherein said precision reference voltage (said switch) is independent of said common supply voltage .	EP0265209A1 CLAIM 2 . A remote control system (1) defined in Claim 1 , wherein said timer (11 , 12) consists of an oscillator (11) and a counter (12) having a reset terminal (R) and being devised so as to output said switch (precision reference voltage) ing signal after counting a predetermined number of pulses outputted from said oscillator (11) , said counter being supplied at said reset terminal with said clock signals .
US6854067B1 CLAIM 13 . In a microcontroller , a system comprising : a bus ; a processor coupled to said bus ; a power on reset circuit , said processor and said power on reset circuit coupled to said bus and interconnectedly coupled with said processor via said bus ; and a switched mode pump power supply (control system) interconnectedly coupled with said power on reset circuit and responsive to signals therefrom wherein said system executes a method of dynamically controlling a plurality of power stability functions for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply ; b) sensing a power state condition of said power state ; c) determining a suitability status of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor via said bus ; e) controlling certain functions of said microcontroller according to said suitability status ; and f) dynamically programming said power on reset circuit via said bus .	EP0265209A1 CLAIM 1 . A remote control system (mode pump power supply) (1) for use in a display apparatus which comprises a display section (4) and a display data control section (2) which has a memory to store display data and outputs clock signals and a series of digital data signals , both being based on said display data stored in said memory , characterized in that said remote control system (1) comprises a relay switch (13) for switching an electric power source (8) to said display section (4) , and a timer (11 , 12) devised so as to output a switching signal to make said relay switch (13) open only when said clock signals remain stopped for a predetermined period of time .
US6854067B1 CLAIM 16 . The system as recited in claim 15 , wherein said c) further comprises : c1) generating a precision reference voltage (said switch) , said precision reference voltage independent of said common supply voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	EP0265209A1 CLAIM 2 . A remote control system (1) defined in Claim 1 , wherein said timer (11 , 12) consists of an oscillator (11) and a counter (12) having a reset terminal (R) and being devised so as to output said switch (precision reference voltage) ing signal after counting a predetermined number of pulses outputted from said oscillator (11) , said counter being supplied at said reset terminal with said clock signals .
US6854067B1 CLAIM 20 . In a microcontroller having a power on reset circuit interconnected with a processor a method of dynamically controlling said power state , said method comprising : a) ascertaining a power state powered by a switched mode pump power supply (control system) , said switched mode pump power supply interconnected with and responsive to control by said power on reset circuit ; b) programmatically determining desired changes to said power state ; c) intercommunicating between said processor and said power on reset circuit ; d) adjusting said power on reset circuit corresponding to said desired changes to said power state ; e) controlling said switched mode pump power supply according to said d) ; and f) repeating said a) through e) .	EP0265209A1 CLAIM 1 . A remote control system (mode pump power supply) (1) for use in a display apparatus which comprises a display section (4) and a display data control section (2) which has a memory to store display data and outputs clock signals and a series of digital data signals , both being based on said display data stored in said memory , characterized in that said remote control system (1) comprises a relay switch (13) for switching an electric power source (8) to said display section (4) , and a timer (11 , 12) devised so as to output a switching signal to make said relay switch (13) open only when said clock signals remain stopped for a predetermined period of time .

US6854067B1 Filed: 2000-10-30 Issued: 2005-02-08 Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller (Original Assignee) Cypress Semiconductor Corp (Current Assignee) HERITAGE IP LLC ; Monterey Research LLC Harold Kutz, Warren Snyder	US4809345A Filed: 1986-08-29 Issued: 1989-02-28 Method of and apparatus for enlarging/reducing two-dimensional images (Original Assignee) Hitachi Ltd (Current Assignee) Hitachi Ltd Kuniaki Tabata, Tetsuo Machida, Haruo Takeda, Naoki Takada, Yasuyuki Okada
US6854067B1 CLAIM 1 . In a microcontroller with an embedded processor , a switched mode pump power supply and power on reset circuit , a method of dynamically controlling a plurality of power stability functions (said first step) for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply , wherein said processor and said power on reset circuit are interconnectedly coupled , and wherein said switched mode pump power supply is interconnectedly coupled with said power on reset circuit and responsive to signals therefrom ; b) sensing a power state condition of said power state ; c) determining a suitability status (determined relationship) of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor ; e) controlling certain functions of said microcontroller accordingly .	US4809345A CLAIM 3 . A method according to claim 1 , in which said first step (power stability functions) includes dividing said column direction and row direction scales by first and second positive integers to define coordinates positions on said first image , said coordinate positions being determined in correspondence with each of said second image elements . US4809345A CLAIM 10 . An apparatus for converting a first two-dimensional image on first column direction and row direction scales and row direction scales , each of said first and second two-dimensional image being of image elements arranged in matrix , in which the position on said first image corresponding to each of said second image elements is associated with a reference frame constituted by four first image elements lying on the intersections of two adjacent rows and two adjacent columns in the first image element matrix surrounding said second image elements , the apparatus comprising : means for producing at least one data sequence for a first fundamental cycle for row direction periodic sequences of data as determined on the basis of the ratio between said first and second row direction scales , which first fundamental cycle of data defines the positional relation between said second image elements and their associated reference frames in said first image element matrix ; means for selecting two rows of image elements data in said first matrix ; means for storing said selected two rows of image element data ; means coupled with said data sequence producing means for determining a reference frame for each of said second image elements from said stored image element data ; means for producing the vertical and horizontal coordinates for each of said second image elements within its associated reference frame , said coordinates having a predetermined relationship (suitability status) with said ratio between said first and second scales ; and means coupled with said reference frame determining means and with said coordinates producing means for determining a data value for each of said second image elements .
US6854067B1 CLAIM 6 . The method as recited in claim 5 , wherein said c) further comprises : c1) generating a precision reference voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one (first two) of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US4809345A CLAIM 1 . A method of converting a first two (comparisons comparing one) -dimensional image on first column direction and row direction scales to a second two-dimensional image on second column direction and rod direction scales , said first and second two-dimensional images being of image elements arranged in first and second matrices respectively , the ratios between said first and second scales being predetermined column direction and row direction scale factors , respectively , comprising : first step of preparing at least one data sequence of fundamental cycle representing differences between those column order numbers in said first matrix which are particularly related to coordinates of image elements in said second matrix and those column order numbers in said first matrix which are particularly related to coordinates of image elements adjacent to the first-mentioned image elements in said second matrix ; second step of selecting at least one row of image elements in said first matrix ; third step of selecting sequentially at least one of the image elements in said first matrix within said selected row by the use of said prepared data sequence ; and fourth step of determining sequentially a data value for each of the image elements on one row in said second matrix on the basis of the value for said selected at least one image element .
US6854067B1 CLAIM 13 . In a microcontroller , a system comprising : a bus ; a processor coupled to said bus ; a power on reset circuit , said processor and said power on reset circuit coupled to said bus and interconnectedly coupled with said processor via said bus ; and a switched mode pump power supply interconnectedly coupled with said power on reset circuit and responsive to signals therefrom wherein said system executes a method of dynamically controlling a plurality of power stability functions (said first step) for said microcontroller , said method comprising : a) supplying a power state to said microcontroller from said switched mode pump power supply ; b) sensing a power state condition of said power state ; c) determining a suitability status (determined relationship) of said power state condition ; d) communicating said suitability status between said power on reset circuit and said processor via said bus ; e) controlling certain functions of said microcontroller according to said suitability status ; and f) dynamically programming said power on reset circuit via said bus .	US4809345A CLAIM 3 . A method according to claim 1 , in which said first step (power stability functions) includes dividing said column direction and row direction scales by first and second positive integers to define coordinates positions on said first image , said coordinate positions being determined in correspondence with each of said second image elements . US4809345A CLAIM 10 . An apparatus for converting a first two-dimensional image on first column direction and row direction scales and row direction scales , each of said first and second two-dimensional image being of image elements arranged in matrix , in which the position on said first image corresponding to each of said second image elements is associated with a reference frame constituted by four first image elements lying on the intersections of two adjacent rows and two adjacent columns in the first image element matrix surrounding said second image elements , the apparatus comprising : means for producing at least one data sequence for a first fundamental cycle for row direction periodic sequences of data as determined on the basis of the ratio between said first and second row direction scales , which first fundamental cycle of data defines the positional relation between said second image elements and their associated reference frames in said first image element matrix ; means for selecting two rows of image elements data in said first matrix ; means for storing said selected two rows of image element data ; means coupled with said data sequence producing means for determining a reference frame for each of said second image elements from said stored image element data ; means for producing the vertical and horizontal coordinates for each of said second image elements within its associated reference frame , said coordinates having a predetermined relationship (suitability status) with said ratio between said first and second scales ; and means coupled with said reference frame determining means and with said coordinates producing means for determining a data value for each of said second image elements .
US6854067B1 CLAIM 16 . The system as recited in claim 15 , wherein said c) further comprises : c1) generating a precision reference voltage , said precision reference voltage independent of said common supply voltage ; c2) dividing said common supply voltage into a plurality of aspect voltages , each of said plurality of aspect voltages corresponding to separate voltage quantity , each separate voltage quantity an independent multiple of said common supply voltage ; c3) forming a plurality of comparisons , each of said plurality of comparisons comparing one (first two) of said plurality of aspect voltages to said precision reference voltage ; and c4) generating a plurality of power state condition signals , each of said plurality of power state condition signals corresponding to one of each of said plurality of comparisons .	US4809345A CLAIM 1 . A method of converting a first two (comparisons comparing one) -dimensional image on first column direction and row direction scales to a second two-dimensional image on second column direction and rod direction scales , said first and second two-dimensional images being of image elements arranged in first and second matrices respectively , the ratios between said first and second scales being predetermined column direction and row direction scale factors , respectively , comprising : first step of preparing at least one data sequence of fundamental cycle representing differences between those column order numbers in said first matrix which are particularly related to coordinates of image elements in said second matrix and those column order numbers in said first matrix which are particularly related to coordinates of image elements adjacent to the first-mentioned image elements in said second matrix ; second step of selecting at least one row of image elements in said first matrix ; third step of selecting sequentially at least one of the image elements in said first matrix within said selected row by the use of said prepared data sequence ; and fourth step of determining sequentially a data value for each of the image elements on one row in said second matrix on the basis of the value for said selected at least one image element .